mcu/service/kal/common/include/kal_cpuinfo.h

#ifndef KAL_CPUINFO_H
#define KAL_CPUINFO_H

/*******************************************************************************
 * Defines for TC_PRIORITY
 *******************************************************************************/
#if defined(__MD93__)
#define HW_ITC_GRP 3         /* Context takes HW ITC */
#define HRT_CONTEXT_GRP 2    /* HRT LISR or HISR/task DI on HRT domain */
#define NORMAL_CONTEXT_GRP 0 /* HISR/task */
#define IDLE_WAIT_GRP 0      /* Idle task enters WAIT state */

#elif defined(__MD95__)

#define HW_ITC_GRP 3         /* Context takes HW ITC */
#define HRT_CONTEXT_GRP 2    /* HRT LISR or HISR/task DI on HRT domain */
#define NORMAL_CONTEXT_GRP 1 /* HISR/task */
#define IDLE_WAIT_GRP 0      /* Idle task enters WAIT state */

#elif defined(__MD97__) || defined(__MD97P__)
/* this setting for MD97P is the same with MD97 */
#define HRT_RESERVED_GRP 3   /* HRT Issues */
#define HW_ITC_GRP 2         /* Context takes HW ITC, or Critical HRT LISR */
#define HRT_CONTEXT_GRP 1    /* HRT LISR, or HISR/task DI on HRT domain */
#define NORMAL_CONTEXT_GRP 0 /* HISR/task */

#else
#warning "unknown MDMCU version"
#endif

/*user must include "mips_ia_utils.h"*/
#if defined(__MD95__) || defined(MT6297_IA)
#define KAL_CURRENT_PRIO(current_prio)                              \
    do{                                                             \
       current_prio = (miu_mfc0(MIU_C0_TCSCHEDULE) & 0x3);          \
    }while(0); 
#elif defined(__MD97__) || defined(__MD97P__) 
#define KAL_CURRENT_PRIO(current_prio)                              \
    do{                                                             \
       current_prio = ((miu_mfc0(MIU_C0_TCSCHEDULE)>>MIU_C0_TCSCHEDULE_PRIO_BITFIELD_BEG) & 0x3);          \
    }while(0); 
#endif

#define KAL_HRT_RAISE_PRIO()                                 \
    do {                                                     \
        miu_save_and_set_c0_tcschedule_grp(HRT_CONTEXT_GRP); \
    } while (0);


#define KAL_ITC_RAISE_PRIO(old_prio)                               \
    do {                                                           \
        old_prio = miu_save_and_set_c0_tcschedule_grp(HW_ITC_GRP); \
    } while (0);


/* TCschedule trottle setting is binding with Task/HISR, independent with VPE it running */
#define KAL_RESTORE_PRIO(prio)                    \
    do {                                          \
        miu_save_and_set_c0_tcschedule_grp(prio); \
    } while (0);

/*user must include "intrCtrl.h"*/
#define LISR_RAISE_TC_PRIO(IRQ_prio)                                            \
    do {                                                                        \
        if (IRQ_prio < IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD) {              \
            miu_set_c0_tcschedule2(MIU_DEF_HRT_DOM_THROT_VAL, HRT_CONTEXT_GRP); \
        }                                                                       \
    } while (0);

/* Set TC's priority according to current VPE's domain */
#if (defined __MD97__ || defined __MD97P__) && !defined MT6297_IA
#define KAL_SET_DEFAULT_TC_PRIO()                                    \
    do {                                                             \
        register miu_reg32_t tc_priority;                            \
        tc_priority = miu_mfc0("$31,5");                             \
        miu_mtc0(MIU_C0_TCSCHEDULE,                                  \
                tc_priority << MIU_C0_TCSCHEDULE_PRIO_BITFIELD_BEG); \
    } while (0);
#else
#define KAL_SET_DEFAULT_TC_PRIO()
#endif /* defined __MD97__ && !defined MT6297_IA */

#endif