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/*****************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
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* permission of MediaTek Inc. (C) 2018
*
* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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*****************************************************************************/
/*****************************************************************************
*
* Filename:
* ---------
* mer_kernel_dpc.h
*
* Project:
* --------
* MERTOS
*
* Description:
* ------------
* The DPC header
*
* Author:
* -------
* -------
*
*****************************************************************************/
#ifndef _MER_KERNEL_DPC_H_
#define _MER_KERNEL_DPC_H_
#include "mer_service_types.h"
#include "mer_service_task.h"
#include "mer_kernel_utility.h"
#include "mer_kernel_config_public.h"
#include "mer_kernel_scheduler.h"
#include "mer_kernel_switch_target.h"
#include "mer_config_public.h"
#include <stddef.h>
///////////////////////////////////////////////////////////////////////////////
// Porting variable
///////////////////////////////////////////////////////////////////////////////
typedef mer_service_dpc_cb mer_kernel_dpc_cb;
extern mer_kernel_dpc_cb mer_kernel_dpc_info_table[];
extern const mer_uint32 mer_kernel_dpc_num;
extern const mer_uint32 mer_kernel_dpc_priority_num;
extern const mer_uint32 mer_kernel_dpc_priority_mask_num;
///////////////////////////////////////////////////////////////////////////////
// Compile time assertion check
///////////////////////////////////////////////////////////////////////////////
/* Make sure the sp is the first element in the control block */
MER_CASSERT(offsetof(mer_kernel_dpc_cb, stack_ptr) == 0);
#if defined(__MD97__) || defined(__MD97P__)
#include "mer_kernel_switch_target_shaolin.inc"
MER_CASSERT(offsetof(mer_kernel_dpc_cb, last_execution_vpe) == MER_KERNEL_SWITCH_LAST_EXE_VPE_OFFSET);
#endif /* defined(__MD97__) || defined(__MD97P__) */
///////////////////////////////////////////////////////////////////////////////
// Macro
///////////////////////////////////////////////////////////////////////////////
#define MER_KERNEL_DPC_LEVEL_BIT (30)
#define MER_KERNEL_DPC_LEVEL_MASK (1 << MER_KERNEL_DPC_LEVEL_BIT)
#define MER_KERNEL_DPC_NUM (mer_kernel_dpc_num)
//#define MER_KERNEL_DPC_MASK_NUM ((MER_KERNEL_DPC_NUM / 32) + (MER_KERNEL_DPC_NUM % 32 != 0))
#define MER_KERNEL_DPC_PRIORITY_NUM (mer_kernel_dpc_priority_num)
#define MER_KERNEL_DPC_PRIORITY_MASK_NUM (mer_kernel_dpc_priority_mask_num)
#define MER_KERNEL_DPC_APPEND_PRIORITY(dpc_id) ((1 << MER_KERNEL_DPC_LEVEL_BIT) | (dpc_id))
///////////////////////////////////////////////////////////////////////////////
// Typedef
///////////////////////////////////////////////////////////////////////////////
typedef struct {
mer_uint32 *mask;
} mer_kernel_dpc_mask;
typedef struct {
mer_uint8 head;
mer_uint8 tail;
} mer_kernel_dpc_list;
typedef mer_uint8 mer_kernel_dpc_id;
///////////////////////////////////////////////////////////////////////////////
// Enum
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Structure
///////////////////////////////////////////////////////////////////////////////
extern mer_kernel_dpc_mask mer_kernel_dpc_pending_mask[];
extern mer_kernel_dpc_list mer_kernel_dpc_priority_list[][MIPS_HW_VPE_NUM];
extern mer_uint32 mer_kernel_dpc_info_table_begin;
extern mer_uint32 mer_kernel_dpc_info_table_end;
///////////////////////////////////////////////////////////////////////////////
// External Function
///////////////////////////////////////////////////////////////////////////////
void mer_kernel_dpc_remove(mer_uint32 dpc_id);
void mer_kernel_dpc_insert(mer_uint32 dpc_id);
void mer_kernel_dpc_insert_to_head(mer_uint32 dpc_id);
void mer_kernel_dpc_set_running_state(mer_uint32 dpc_id);
void mer_kernel_dpc_initialization();
void mer_kernel_dpc_invoke(mer_uint32 dpc_id);
void mer_kernel_dpc_invoke_in_hrt_isr(mer_uint32 dpc_id);
void mer_kernel_dpc_change_current_affinity(mer_uint32 affinity_mask);
void mer_kernel_dpc_set_affinity_to_current_vpe();
#if defined(__MER_CONFIG_USE_DYNAMIC_ALLOCATION__)
void mer_kernel_dpc_stack_allocation();
#endif /* __MER_CONFIG_USE_DYNAMIC_ALLOCATION__ */
/**
* Return the dpc index with cb pointer
*
*
* Time complexity O(1)
*
* @param[out] Index of input cb pointer
* @param[in] The dpc pointer
*
*/
static inline mer_uint32 mer_kernel_dpc_get_index(mer_kernel_dpc_cb *cb){
//return (mer_uint32)(cb - mer_kernel_dpc_info_table);
return (mer_uint32)cb->job_index;
}
/**
* Return the current running dpc index
* Note that this function assume the schedule lock is taken
*
* Unless __MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__ is defined
*
* Time complexity O(1)
*
* @param[out] The current dpc id
* @param[in] vpe_id
*
*/
__attribute__((always_inline)) static inline mer_uint32 mer_kernel_dpc_get_current_index(){
#if defined(__MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__)
mer_kernel_dpc_cb *cb = (mer_kernel_dpc_cb *)(MER_KERNEL_GET_CURRENT_CONTROL_BLOCK());
return mer_kernel_dpc_get_index(cb);
#else
mer_uint32 current_vpe = mer_kernel_utility_get_current_vpe_id();
return mer_kernel_scheduler_running_job[current_vpe].job_index;
#endif /* __MER_KERNEL_USE_MIPS_CP0_CONTEXT_REG__ */
}
#endif /* _MER_KERNEL_DPC_H_ */