| #ifndef __SVC_DSP_DEBUG_CONTROL_H__ |
| #define __SVC_DSP_DEBUG_CONTROL_H__ |
| |
| #include "drv_comm.h" |
| #include "reg_base.h" |
| |
| /******************************************************************************* |
| * SCQ DBG APB CR Definition |
| *******************************************************************************/ |
| #if defined(__MD93__) || defined(__MD95__) |
| #define SCQ0_APB_BASE (BASE_MADDR_MDPERI_MD_DBGSYS2 + 0xC000) |
| #define SCQ1_APB_BASE (BASE_MADDR_MDPERI_MD_DBGSYS2 + 0xD000) |
| #elif defined(__MD97__) || defined(__MD97P__) |
| #define SCQ0_APB_BASE (BASE_MADDR_VDSP_1_MD32SCQ) |
| #define SCQ1_APB_BASE (BASE_MADDR_VDSP_2_MD32SCQ) |
| #define SCQ2_APB_BASE (BASE_MADDR_VDSP_3_MD32SCQ) |
| #define SCQ3_APB_BASE (BASE_MADDR_VDSP_4_MD32SCQ) |
| #else |
| #error "Unsupported project!!" |
| #endif |
| |
| /******************************************************************************* |
| * MACRO Definition |
| *******************************************************************************/ |
| #define SCQ_APB_DBG_EN_OFFSET 0x0 |
| #define SCQ_APB_MODE_SEL_OFFSET 0x4 |
| #define SCQ_APB_DBG_INST_OFFSET 0x10 |
| #define SCQ_APB_DBG_EXECUTE_OFFSET 0x14 |
| |
| #if defined(__MD93__) || defined(__MD95__) |
| #define SCQ_APB_DBG_STATUS_OFFSET 0x20 |
| #elif defined (__MD97__) || defined(__MD97P__) |
| #define SCQ_APB_DBG_STATUS_OFFSET 0x24 |
| #else |
| #error "Unsupported project!!" |
| #endif |
| |
| #define SCQ_APB_DBG_ATTACH_INST 0x900 |
| #define SCQ_APB_DBG_REQ_INST 0x811 |
| #define SCQ_APB_DBG_STATUS_INST 0x803 |
| #define SCQ_APB_DBG_RESUME_INST 0x812 |
| |
| #if defined(__SCQ16_SUPPORT_CTI_RESTART__) |
| /* TODO: Add code for 97 CTI restart when HW ready */ |
| #endif |
| |
| #endif |