| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /******************************************************************************* |
| * Filename: |
| * ----------- |
| * spv_api.h |
| * |
| * Project: |
| * ----------- |
| * UMOLY |
| * |
| * Description: |
| * ------------ |
| * SPV Related API Code |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| * ========================================================================== |
| * $Log$ |
| * |
| * 07 16 2020 yunciou.lin |
| * [MOLY00546717] [MT6833] [Palmer] feature check-in: SPV option & disable emimpu for palmer bringup. |
| * [Palmer] feature check-in: |
| * SPV option & |
| * disable emimpu for palmer bringup. |
| * |
| * 02 07 2020 chia-fu.lee |
| * [MOLY00475722] [VMOLY][MT6853] Mouton call for check in |
| * |
| * [SSS] Trace feature support on sampling mode |
| * |
| * 01 21 2020 justin.chen |
| * [MOLY00475722] [VMOLY][MT6853] Mouton call for check in |
| * . Update SPV related file. |
| * |
| * 12 26 2019 justin.chen |
| * [MOLY00462986] [MT6885] elm driver development |
| * .Update MT6873 force latency API. |
| * |
| * 12 26 2019 gway.lo |
| * [MOLY00462986] [MT6885] elm driver development |
| * 1. word count threshold change api |
| * 2. toggle elm on/off api |
| * |
| * 12 24 2019 gway.lo |
| * [MOLY00462986] [MT6885] elm driver development |
| * |
| * enable Margaux ELM 2nd assert |
| * |
| * 12 06 2019 chia-fu.lee |
| * [MOLY00460633] [MT6885][Petrus][MP1][SQC][CTC][FT][NSA][5G FT][China][Shanghai][Extension FT][MDST][CAT]md1:(MCU_core0,vpe1,tc2(VPE1)) [ASSERT] file:mcu/l1/ul1/ul1d_public/ul1_bb_error_check.c line:108 |
| * |
| * Rollback debugging patch for UL1 HRT fail issue |
| * |
| * 11 12 2019 chia-fu.lee |
| * [MOLY00458740] [MT6885][Petrus][MP1][SQC][CTC][FT][NSA][5G FT][China][Suzhou][Extension FT][MDST][CAT]file:mcu/l1/ul1/ul1d_public/ul1_bb_error_check.c line:108 |
| * |
| * EWSP0000059818 |
| * SSS debugging patch |
| * |
| * 11 07 2019 gway.lo |
| * [MOLY00457526] [MT6873] driver porting |
| * disable elm assert mode and porting emi force latency api on MT6873 |
| * |
| * 09 19 2019 gway.lo |
| * [MOLY00403390] [MT6297] ELM driver development |
| * petrus force emi latency |
| * |
| * 09 19 2019 chia-fu.lee |
| * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time |
| * |
| * Rollback debug patch for IRQ0xF5 issue |
| * |
| * 08 26 2019 chia-fu.lee |
| * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time |
| * |
| * Fixed Mercury(MD97P) build error. |
| * |
| * 08 26 2019 chia-fu.lee |
| * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time |
| * SSS Profiling |
| * |
| * 05 27 2019 gway.lo |
| * [MOLY00408920] [MT6297] SPV long time profile update |
| * long time profile feature update |
| * |
| * 04 12 2019 gway.lo |
| * [MOLY00398406] [MT6297] SS SPV AMIF profile feature |
| * AMIF profiling feature |
| * |
| * 01 14 2019 chia-fu.lee |
| * [MOLY00378963] [SystemService][MT6297] SWLA and CM2 counter / SSS PMU Profiling Development |
| * |
| * SSS PMU Profiling API |
| * |
| * 12 18 2018 gway.lo |
| * [MOLY00367306] [MT6297][SPV] basic profiling code check-in |
| * fix build error |
| * |
| * 12 18 2018 gway.lo |
| * [MOLY00367306] [MT6297][SPV] basic profiling code check-in |
| * force emi latenct, long time profiling |
| * |
| * 07 16 2018 chia-fu.lee |
| * [MOLY00338914] [SPV][Gen95] EBM in BW runtime profiling |
| * |
| * . |
| * |
| * 05 21 2018 chia-fu.lee |
| * [MOLY00327212] [Gen95][L2C LOCK]Remove Static L2 Cache Lock input sections |
| * |
| * [UMOLYE] SPV service Remove Static L2 Cache Lock input sections |
| * |
| * 04 02 2018 chin-chieh.hung |
| * [MOLY00309439] Eiger SPV utilities support |
| * Update EBM driver for Gen95 |
| * |
| * 03 19 2018 chia-fu.lee |
| * [MOLY00313462] [Gen95] SPV_SVC porting |
| * SPV_SVC modification support write latency information |
| * |
| * 03 14 2018 chia-fu.lee |
| * [MOLY00313462] [Gen95] SPV_SVC porting |
| * |
| * Modify ELM part |
| * |
| * 03 13 2018 chin-chieh.hung |
| * [MOLY00309439] Eiger SPV utilities support |
| * Disable EMI latency count by 26Mhz |
| * |
| * 03 08 2018 peng-chih.wang |
| * [MOLY00312351] [System Service] Add M4 force latency and AT cmd for Gen95 PS SPV |
| * Eiger PS SPV -- porting force M4 latency and AT cmd. |
| * |
| * 02 23 2018 chin-chieh.hung |
| * [MOLY00309439] Eiger SPV utilities support |
| * Add Gen95 SPV utilities - Force Latency / EBM counter |
| * |
| * 09 07 2017 yen-chun.liu |
| * [MOLY00274402] [Gen93] SPV profiling utility |
| * BW/latency profiling code v2. |
| * |
| * 09 07 2017 yen-chun.liu |
| * [MOLY00274402] [Gen93] SPV profiling utility |
| * BW/latency runtime profiling. |
| * |
| * 07 24 2017 wellken.chen |
| * [MOLY00265986] [SPVSVC] Add spv service 1st version related |
| * |
| * 06 02 2017 linson.du |
| * [MOLY00254730] [Gen93]: ELM driver update for EMI latency issue |
| * ELM driver update for SPV usage. |
| * |
| * 07 14 2015 wellken.chen |
| * [MOLY00128710] [Jade][SPV] Refine SPV API realted code |
| * |
| * |
| * |
| * |
| * |
| ****************************************************************************/ |
| |
| |
| #ifndef __SPV_API_H_ |
| #define __SPV_API_H_ |
| |
| #include "reg_base.h" |
| #include "kal_general_types.h" |
| #include "elm.h" |
| |
| #if defined(__FORCE_EMI_LATENCY_ENABLE__) |
| #if defined(MT6763)||defined(MT3967) //use AP EMI |
| |
| #define SPV_MADDR_MEMAPB (0xC0219000) |
| |
| #define EMI_CONE (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x20) |
| #define EMI_DRCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x78) |
| #define EMI_ARBD (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x118) |
| #define EMI_ARBE (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x120) |
| #define EMI_SLCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x158) |
| #define EMI_CONM (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x60) |
| #define EMI_TESTB (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0xE8) |
| |
| #if !defined(__SPV_EBM_DRIVER__) |
| #define EMI_BMEN (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x400) |
| #define EMI_BCNT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x408) |
| |
| #define EMI_TSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x418) |
| #define EMI_WSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x428) |
| #define EMI_BACT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x430) |
| #define EMI_BSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x438) |
| #define EMI_MSEL (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x440) |
| #define EMI_TSCT2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x448) |
| #define EMI_WSCT2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x458) |
| #define EMI_BMEN2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x4E8) |
| |
| |
| #define EMI_TTYPE1 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x500) |
| #define EMI_TTYPE2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x508) |
| #define EMI_TTYPE3 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x510) |
| #define EMI_TTYPE4 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x518) |
| #define EMI_TTYPE5 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x520) |
| #define EMI_TTYPE6 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x528) |
| #define EMI_TTYPE7 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x53C) |
| #endif //!defined(__SPV_EBM_DRIVER__) |
| |
| #if defined(MT3967) //use AP EMI |
| |
| #define EMI_FORCE_LATENCY(r, w) \ |
| do {\ |
| *EMI_CONE |= 1;\ |
| *EMI_DRCT = 0x23110000;\ |
| *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\ |
| *EMI_SLCT = 0x1F011700;\ |
| *EMI_CONM = 0xff000500;\ |
| } while (0) |
| |
| #else |
| |
| //psmcu ultra |
| #define SPV_PSMCU_QOS_CTL ((volatile kal_uint32 *)(BASE_MADDR_MDPERIMISC + 0xF0)) |
| |
| #define EMI_FORCE_LATENCY(r, w) \ |
| do {\ |
| while (*SPV_PSMCU_QOS_CTL & 0x11) {*SPV_PSMCU_QOS_CTL &= ~(0x11);}\ |
| *EMI_DRCT = 0x23110000;\ |
| *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\ |
| *EMI_SLCT = 0x1F011700;\ |
| *EMI_CONM = 0xff000500;\ |
| } while (0) |
| |
| #define EMI_FORCE_M4_LATENCY(r, w) \ |
| do {\ |
| while (*SPV_PSMCU_QOS_CTL & 0x11) {*SPV_PSMCU_QOS_CTL &= ~(0x11);}\ |
| *EMI_DRCT = 0x23110000;\ |
| *EMI_ARBE = 0x00003000 | (r<<16) | (w<<24);\ |
| *EMI_SLCT = 0x1F011700;\ |
| *EMI_CONM = 0xff000500;\ |
| } while (0) |
| #endif |
| |
| #define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \ |
| do {\ |
| *EMI_TESTB |= (1<<11);\ |
| } while(0) |
| |
| #elif defined(MT6297) |
| |
| #define SPV_MADDR_MEMAPB (0xC0219000) |
| |
| #define EMI_CONE (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x20 ) |
| #define EMI_DRCT (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x78 ) |
| #define EMI_CONM (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x60 ) |
| #define EMI_TESTB (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xE8 ) |
| #define EMI_ARBD (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x118) |
| #define EMI_ARBE_2ND (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x124) |
| #define EMI_SLCT (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x158) |
| #define EMI_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x710) |
| #define EMI_BWLMTA (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x890) |
| #define EMI_BWLMTF_2ND (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x8E4) |
| #define EMI_BWLMTF_5TH (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x934) |
| #define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD04) |
| #define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD08) |
| #define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD0C) |
| #define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD10) |
| #define EMI_QOS_MDR_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD14) |
| #define EMI_QOS_MDR_SHF1 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD18) |
| #define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD2C) |
| #define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD30) |
| |
| #define EMI_FORCE_LATENCY(r, w) \ |
| do {\ |
| *EMI_CONE |= 1;\ |
| *EMI_DRCT = 0x23110000;\ |
| *EMI_SHF0 &= 0xFFFFFFF0; \ |
| *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\ |
| *EMI_ARBE_2ND = (*EMI_ARBE_2ND & 0x0000FFFF) | (r<<16) | (w<<24);\ |
| *EMI_SLCT = 0x1F011700;\ |
| *EMI_CONM = 0xff000500;\ |
| \ |
| *EMI_BWLMTA |= (0x01UL<< 3); \ |
| *EMI_BWLMTA &= ~(0x01UL<<11); \ |
| *EMI_BWLMTA &= ~(0x01UL<<27); \ |
| *EMI_BWLMTF_2ND &= 0xFFFF0000UL; \ |
| *EMI_BWLMTF_5TH &= 0xFFFF0000UL; \ |
| *EMI_QOS_MDR_SHF0 = (*EMI_QOS_MDR_SHF0 & (0xFFF00000UL)) | (r&0xFF)<<8 | (r&0xFF); \ |
| *EMI_QOS_MDR_SHF1 = (*EMI_QOS_MDR_SHF1 & (0xFFF00000UL)) | (r&0xFF)<<8 | (r&0xFF); \ |
| *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0 & (0xFFF00000UL)) | (w&0xFF)<<8 | (w&0xFF); \ |
| *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1 & (0xFFF00000UL)) | (w&0xFF)<<8 | (w&0xFF); \ |
| *EMI_QOS_MDR_BE0A = 0x00000000; \ |
| *EMI_QOS_MDR_BE0B = 0x00000000; \ |
| *EMI_QOS_MDR_BE1A = 0x00000000; \ |
| *EMI_QOS_MDR_BE1B = 0x00000000; \ |
| } while (0) |
| |
| |
| #define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \ |
| do {\ |
| *EMI_TESTB |= (1<<11);\ |
| } while(0) |
| |
| #define FORCE_MD_ULTRA(p) \ |
| do {\ |
| if(p==0){\ |
| DRV_ClrReg32(BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG+0x1C,(0xF<<16)); \ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\ |
| DRV_WriteReg32(BASE_MADDR_MCOREPERI_INFRA_DSPSL2C+0x658, 0x0);\ |
| }else{\ |
| DRV_SetReg32(BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG+0x1C,(0xF<<16)); \ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0xEF);\ |
| DRV_WriteReg32(BASE_MADDR_MCOREPERI_INFRA_DSPSL2C+0x658, 0x2AAAA);\ |
| }\ |
| } while(0) |
| #elif defined(MT6885) || defined(MT6880) |
| |
| #define EMI_N_ARBE_2ND (volatile kal_uint32*)(0xC0219124) |
| #define EMI_N_ARBD (volatile kal_uint32*)(0xC0219118) |
| #define EMI_N_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC0219D14) |
| #define EMI_N_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC0219D18) |
| |
| #define EMI_S_ARBE_2ND (volatile kal_uint32*)(0xC021D124) |
| #define EMI_S_ARBD (volatile kal_uint32*)(0xC021D118) |
| #define EMI_S_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC021DD14) |
| #define EMI_S_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC021DD18) |
| |
| #define EMI_CH0_TESTB (volatile kal_uint32*)(0xC0235048) |
| #define EMI_CH1_TESTB (volatile kal_uint32*)(0xC0245048) |
| #define EMI_CH2_TESTB (volatile kal_uint32*)(0xC0255048) |
| #define EMI_CH3_TESTB (volatile kal_uint32*)(0xC0265048) |
| |
| |
| /***********************/ |
| |
| #define EMI_TESTC (volatile kal_uint32*)(0xc02190f0) |
| #define EMI_TESTC_S (volatile kal_uint32*)(0xc021d0f0) |
| |
| #define EMI_CONH_2ND (volatile kal_uint32*)(0xc021903c) |
| #define EMI_CONH_2ND_S (volatile kal_uint32*)(0xc021d03c) |
| |
| #define EMI_BWLMTE_4TH (volatile kal_uint32*)(0xc0219920) |
| #define EMI_BWLMTE_4TH_S (volatile kal_uint32*)(0xc021d920) |
| |
| #define EMI_BWLMTF_4TH (volatile kal_uint32*)(0xc0219924) |
| #define EMI_BWLMTF_4TH_S (volatile kal_uint32*)(0xc021d924) |
| |
| #define EMI_BWLMTE_5TH (volatile kal_uint32*)(0xc0219930) |
| #define EMI_BWLMTE_5TH_S (volatile kal_uint32*)(0xc021d930) |
| #define EMI_BWLMTF_5TH (volatile kal_uint32*)(0xc0219934) |
| #define EMI_BWLMTF_5TH_S (volatile kal_uint32*)(0xc021d934) |
| #define EMI_BWLMTG_5TH (volatile kal_uint32*)(0xc0219938) |
| #define EMI_BWLMTG_5TH_S (volatile kal_uint32*)(0xc021d938) |
| |
| #define EMI_BWLMTE (volatile kal_uint32*)(0xc02198A0) |
| #define EMI_BWLMTE_S (volatile kal_uint32*)(0xc021d8A0) |
| #define EMI_BWLMTF (volatile kal_uint32*)(0xc02198A4) |
| #define EMI_BWLMTF_S (volatile kal_uint32*)(0xc021d8A4) |
| |
| #define EMI_BWLMTE_2ND (volatile kal_uint32*)(0xc02198E0) |
| #define EMI_BWLMTE_2ND_S (volatile kal_uint32*)(0xc021d8E0) |
| #define EMI_BWLMTF_2ND (volatile kal_uint32*)(0xc02198E4) |
| #define EMI_BWLMTF_2ND_S (volatile kal_uint32*)(0xc021d8E4) |
| #define EMI_BWLMTG_2ND (volatile kal_uint32*)(0xc02198E8) |
| #define EMI_BWLMTG_2ND_S (volatile kal_uint32*)(0xc021d8E8) |
| |
| #define EMI_MDCT (volatile kal_uint32*)(0xc0219078) |
| #define EMI_MDCT_S (volatile kal_uint32*)(0xc021d078) |
| |
| #define EMI_THRO_PRD2 (volatile kal_uint32*)(0xC021985C) |
| #define EMI_THRO_PRD2_S (volatile kal_uint32*)(0xC021D85C) |
| |
| #define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(0xC0219D04) |
| #define EMI_QOS_MDR_BE0A_S (volatile kal_uint32*)(0xC021DD04) |
| #define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(0xC0219D08) |
| #define EMI_QOS_MDR_BE0B_S (volatile kal_uint32*)(0xC021DD08) |
| #define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(0xC0219D0C) |
| #define EMI_QOS_MDR_BE1A_S (volatile kal_uint32*)(0xC021DD0C) |
| #define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(0xC0219D10) |
| #define EMI_QOS_MDR_BE1B_S (volatile kal_uint32*)(0xC021DD10) |
| |
| #define EMI_QOS_MDW_BE0A (volatile kal_uint32*)(0xC0219D1C) |
| #define EMI_QOS_MDW_BE0A_S (volatile kal_uint32*)(0xC021DD1C) |
| #define EMI_QOS_MDW_BE0B (volatile kal_uint32*)(0xC0219D20) |
| #define EMI_QOS_MDW_BE0B_S (volatile kal_uint32*)(0xC021DD20) |
| #define EMI_QOS_MDW_BE1A (volatile kal_uint32*)(0xC0219D24) |
| #define EMI_QOS_MDW_BE1A_S (volatile kal_uint32*)(0xC021DD24) |
| #define EMI_QOS_MDW_BE1B (volatile kal_uint32*)(0xC0219D28) |
| #define EMI_QOS_MDW_BE1B_S (volatile kal_uint32*)(0xC021DD28) |
| |
| #define EMI_QOS_MDHWR_BE0A (volatile kal_uint32*)(0xC0219D98) |
| #define EMI_QOS_MDHWR_BE0A_S (volatile kal_uint32*)(0xC021DD98) |
| #define EMI_QOS_MDHWR_BE0B (volatile kal_uint32*)(0xC0219D9C) |
| #define EMI_QOS_MDHWR_BE0B_S (volatile kal_uint32*)(0xC021DD9C) |
| #define EMI_QOS_MDHWR_BE1A (volatile kal_uint32*)(0xC0219DA0) |
| #define EMI_QOS_MDHWR_BE1A_S (volatile kal_uint32*)(0xC021DDA0) |
| #define EMI_QOS_MDHWR_BE1B (volatile kal_uint32*)(0xC0219DA4) |
| #define EMI_QOS_MDHWR_BE1B_S (volatile kal_uint32*)(0xC021DDA4) |
| |
| #define EMI_QOS_MDHWW_BE0A (volatile kal_uint32*)(0xC0219DAC) |
| #define EMI_QOS_MDHWW_BE0A_S (volatile kal_uint32*)(0xC021DDAC) |
| #define EMI_QOS_MDHWW_BE0B (volatile kal_uint32*)(0xC0219DB0) |
| #define EMI_QOS_MDHWW_BE0B_S (volatile kal_uint32*)(0xC021DDB0) |
| #define EMI_QOS_MDHWW_BE1A (volatile kal_uint32*)(0xC0219DB4) |
| #define EMI_QOS_MDHWW_BE1A_S (volatile kal_uint32*)(0xC021DDB4) |
| #define EMI_QOS_MDHWW_BE1B (volatile kal_uint32*)(0xC0219DB8) |
| #define EMI_QOS_MDHWW_BE1B_S (volatile kal_uint32*)(0xC021DDB8) |
| |
| #define EMI_CONE (volatile kal_uint32*)(0xc0219020) |
| #define EMI_CONE_S (volatile kal_uint32*)(0xc021d020) |
| |
| #define CH0_EMI_CONC (volatile kal_uint32*)(0xC0235010) |
| #define CH1_EMI_CONC (volatile kal_uint32*)(0xC0245010) |
| #define CH2_EMI_CONC (volatile kal_uint32*)(0xC0255010) |
| #define CH3_EMI_CONC (volatile kal_uint32*)(0xC0265010) |
| |
| #define EMI_QOS_CTRL1 (volatile kal_uint32*)(0xc0219DF4) |
| #define EMI_QOS_CTRL1_S (volatile kal_uint32*)(0xc021dDF4) |
| |
| #define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(0xc0219D2C) |
| #define EMI_QOS_MDW_SHF0_S (volatile kal_uint32*)(0xc021dD2C) |
| #define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(0xc0219D30) |
| #define EMI_QOS_MDW_SHF1_S (volatile kal_uint32*)(0xc021dD30) |
| |
| /***********************/ |
| #define EMI_FORCE_LATENCY(r, w) \ |
| do {\ |
| *EMI_TESTC |= 1<<19;\ |
| *EMI_TESTC_S |= 1<<19;\ |
| *EMI_CONH_2ND |= 1<<9;\ |
| *EMI_CONH_2ND_S |= 1<<9;\ |
| *EMI_BWLMTE_4TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTE_4TH_S = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_4TH |= 0xFFFF;\ |
| *EMI_BWLMTF_4TH_S |= 0xFFFF;\ |
| *EMI_BWLMTE_5TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTE_5TH_S = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_5TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_5TH_S = 0xFFFFFFFF;\ |
| *EMI_BWLMTG_5TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTG_5TH_S = 0xFFFFFFFF;\ |
| *EMI_BWLMTE = 0xFF00FFFF;\ |
| *EMI_BWLMTE_S = 0xFF00FFFF;\ |
| *EMI_BWLMTF |= 0xFFFF;\ |
| *EMI_BWLMTF_S |= 0xFFFF;\ |
| *EMI_BWLMTE_2ND = 0xFFFFFFFF;\ |
| *EMI_BWLMTE_2ND_S = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_2ND = 0xFFFF0000;\ |
| *EMI_BWLMTF_2ND_S = 0xFFFF0000;\ |
| *EMI_BWLMTG_2ND = 0xFFFFFFFF;\ |
| *EMI_BWLMTG_2ND_S = 0xFFFFFFFF;\ |
| *EMI_N_ARBD |= 1<<13;\ |
| *EMI_S_ARBD |= 1<<13;\ |
| *EMI_N_ARBD &= ~(1<<14);\ |
| *EMI_S_ARBD &= ~(1<<14);\ |
| *EMI_MDCT &= ~((1<<1)|(1<<3));\ |
| *EMI_MDCT_S &= ~((1<<1)|(1<<3));\ |
| *EMI_THRO_PRD2 |= (7<<24) | (7<<28);\ |
| *EMI_THRO_PRD2_S |= (7<<24) | (7<<28);\ |
| \ |
| *EMI_QOS_MDR_BE0A = 0;\ |
| *EMI_QOS_MDR_BE0B = 0;\ |
| *EMI_QOS_MDR_BE1A = 0;\ |
| *EMI_QOS_MDR_BE1B = 0;\ |
| *EMI_QOS_MDW_BE0A = 0;\ |
| *EMI_QOS_MDW_BE0B = 0;\ |
| *EMI_QOS_MDW_BE1A = 0;\ |
| *EMI_QOS_MDW_BE1B = 0;\ |
| *EMI_QOS_MDR_BE0A_S = 0;\ |
| *EMI_QOS_MDR_BE0B_S = 0;\ |
| *EMI_QOS_MDR_BE1A_S = 0;\ |
| *EMI_QOS_MDR_BE1B_S = 0;\ |
| *EMI_QOS_MDW_BE0A_S = 0;\ |
| *EMI_QOS_MDW_BE0B_S = 0;\ |
| *EMI_QOS_MDW_BE1A_S = 0;\ |
| *EMI_QOS_MDW_BE1B_S = 0;\ |
| \ |
| *EMI_QOS_MDHWR_BE0A = 0;\ |
| *EMI_QOS_MDHWR_BE0B = 0;\ |
| *EMI_QOS_MDHWR_BE1A = 0;\ |
| *EMI_QOS_MDHWR_BE1B = 0;\ |
| *EMI_QOS_MDHWW_BE0A = 0;\ |
| *EMI_QOS_MDHWW_BE0B = 0;\ |
| *EMI_QOS_MDHWW_BE1A = 0;\ |
| *EMI_QOS_MDHWW_BE1B = 0;\ |
| *EMI_QOS_MDHWR_BE0A_S = 0;\ |
| *EMI_QOS_MDHWR_BE0B_S = 0;\ |
| *EMI_QOS_MDHWR_BE1A_S = 0;\ |
| *EMI_QOS_MDHWR_BE1B_S = 0;\ |
| *EMI_QOS_MDHWW_BE0A_S = 0;\ |
| *EMI_QOS_MDHWW_BE0B_S = 0;\ |
| *EMI_QOS_MDHWW_BE1A_S = 0;\ |
| *EMI_QOS_MDHWW_BE1B_S = 0;\ |
| \ |
| *EMI_N_ARBD = (*EMI_N_ARBD&0x00FFFFFF) | (w<<24);\ |
| *EMI_N_ARBE_2ND = (*EMI_N_ARBE_2ND&0x00FFFFFF) | (w<<24);\ |
| *EMI_S_ARBD = (*EMI_S_ARBD&0x00FFFFFF) | (w<<24);\ |
| *EMI_S_ARBE_2ND = (*EMI_S_ARBE_2ND&0x00FFFFFF) | (w<<24);\ |
| \ |
| *EMI_CONE |= 1 ;\ |
| *EMI_CONE_S |= 1 ;\ |
| \ |
| *CH0_EMI_CONC |= (1<<5) ;\ |
| *CH1_EMI_CONC |= (1<<5) ;\ |
| *CH2_EMI_CONC |= (1<<5) ;\ |
| *CH3_EMI_CONC |= (1<<5) ;\ |
| \ |
| *EMI_QOS_CTRL1 &= ~((0x1<<11)|(0x1<<27));\ |
| *EMI_QOS_CTRL1_S &= ~((0x1<<11)|(0x1<<27));\ |
| \ |
| *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0&0xffffff00) | w;\ |
| *EMI_QOS_MDW_SHF0_S = (*EMI_QOS_MDW_SHF0_S&0xffffff00) | w;\ |
| *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1&0xffffff00) | w;\ |
| *EMI_QOS_MDW_SHF1_S = (*EMI_QOS_MDW_SHF1_S&0xffffff00) | w;\ |
| \ |
| *EMI_N_ARBE_2ND = (*EMI_N_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\ |
| *EMI_N_ARBD = (*EMI_N_ARBD & 0xFF00FFFF) | (r<<16) ;\ |
| *EMI_N_QOS_MDR_SHF0 = (*EMI_N_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\ |
| *EMI_N_QOS_MDR_SHF1 = (*EMI_N_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\ |
| \ |
| *EMI_S_ARBE_2ND = (*EMI_S_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\ |
| *EMI_S_ARBD = (*EMI_S_ARBD & 0xFF00FFFF) | (r<<16) ;\ |
| *EMI_S_QOS_MDR_SHF0 = (*EMI_S_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\ |
| *EMI_S_QOS_MDR_SHF1 = (*EMI_S_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\ |
| \ |
| *EMI_CH0_TESTB |= ((1<<6)|(1<<13)) ; \ |
| *EMI_CH1_TESTB |= ((1<<6)|(1<<13)) ; \ |
| *EMI_CH2_TESTB |= ((1<<6)|(1<<13)) ; \ |
| *EMI_CH3_TESTB |= ((1<<6)|(1<<13)) ; \ |
| } while (0) |
| |
| #define EMI_AGING_26M() \ |
| do {\ |
| *EMI_CONE &= ~(1<<0) ;\ |
| *EMI_CONE_S &= ~(1<<0) ;\ |
| *CH0_EMI_CONC &= ~(1<<5) ;\ |
| *CH1_EMI_CONC &= ~(1<<5) ;\ |
| *CH2_EMI_CONC &= ~(1<<5) ;\ |
| *CH3_EMI_CONC &= ~(1<<5) ;\ |
| } while (0) |
| |
| #define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \ |
| do {\ |
| *EMI_CH0_TESTB |= (1<<11) ; \ |
| *EMI_CH1_TESTB |= (1<<11) ; \ |
| *EMI_CH2_TESTB |= (1<<11) ; \ |
| *EMI_CH3_TESTB |= (1<<11) ; \ |
| } while(0) |
| |
| #define FORCE_MD_ULTRA(p) \ |
| do {\ |
| if(p==0){\ |
| DRV_ClrReg32(0xa0060064,(0xf << 8)); \ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x0);\ |
| DRV_WriteReg32(0xa4c00000+0x8658, 0x0);\ |
| }else{\ |
| DRV_SetReg32(0xa0060064,(0xf << 8)); \ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x7EF);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x7E00000);\ |
| DRV_WriteReg32(0xa4c00000+0x8658, 0x2AAAA);\ |
| }\ |
| } while(0) |
| |
| #elif defined(MT6873) || defined(MT6853) || defined(MT6833) |
| |
| #define EMI_ARBE_2ND (volatile kal_uint32*)(0xC0219124) |
| #define EMI_ARBD (volatile kal_uint32*)(0xC0219118) |
| #define EMI_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC0219D14) |
| #define EMI_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC0219D18) |
| |
| #define EMI_CH0_TESTB (volatile kal_uint32*)(0xC0235048) |
| #define EMI_CH1_TESTB (volatile kal_uint32*)(0xC0245048) |
| |
| |
| /***********************/ |
| |
| #define EMI_TESTC (volatile kal_uint32*)(0xc02190f0) |
| #define EMI_CONH_2ND (volatile kal_uint32*)(0xc021903c) |
| #define EMI_BWLMTE_4TH (volatile kal_uint32*)(0xc0219920) |
| #define EMI_BWLMTF_4TH (volatile kal_uint32*)(0xc0219924) |
| |
| #define EMI_BWLMTE_5TH (volatile kal_uint32*)(0xc0219930) |
| #define EMI_BWLMTF_5TH (volatile kal_uint32*)(0xc0219934) |
| #define EMI_BWLMTG_5TH (volatile kal_uint32*)(0xc0219938) |
| |
| #define EMI_BWLMTE (volatile kal_uint32*)(0xc02198A0) |
| #define EMI_BWLMTF (volatile kal_uint32*)(0xc02198A4) |
| |
| #define EMI_BWLMTE_2ND (volatile kal_uint32*)(0xc02198E0) |
| #define EMI_BWLMTF_2ND (volatile kal_uint32*)(0xc02198E4) |
| #define EMI_BWLMTG_2ND (volatile kal_uint32*)(0xc02198E8) |
| |
| #define EMI_MDCT (volatile kal_uint32*)(0xc0219078) |
| |
| #define EMI_THRO_PRD2 (volatile kal_uint32*)(0xC021985C) |
| |
| #define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(0xC0219D04) |
| #define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(0xC0219D08) |
| #define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(0xC0219D0C) |
| #define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(0xC0219D10) |
| |
| #define EMI_QOS_MDW_BE0A (volatile kal_uint32*)(0xC0219D1C) |
| #define EMI_QOS_MDW_BE0B (volatile kal_uint32*)(0xC0219D20) |
| #define EMI_QOS_MDW_BE1A (volatile kal_uint32*)(0xC0219D24) |
| #define EMI_QOS_MDW_BE1B (volatile kal_uint32*)(0xC0219D28) |
| |
| #define EMI_QOS_MDHWR_BE0A (volatile kal_uint32*)(0xC0219D98) |
| #define EMI_QOS_MDHWR_BE0B (volatile kal_uint32*)(0xC0219D9C) |
| #define EMI_QOS_MDHWR_BE1A (volatile kal_uint32*)(0xC0219DA0) |
| #define EMI_QOS_MDHWR_BE1B (volatile kal_uint32*)(0xC0219DA4) |
| |
| #define EMI_QOS_MDHWW_BE0A (volatile kal_uint32*)(0xC0219DAC) |
| #define EMI_QOS_MDHWW_BE0B (volatile kal_uint32*)(0xC0219DB0) |
| #define EMI_QOS_MDHWW_BE1A (volatile kal_uint32*)(0xC0219DB4) |
| #define EMI_QOS_MDHWW_BE1B (volatile kal_uint32*)(0xC0219DB8) |
| |
| #define EMI_CONE (volatile kal_uint32*)(0xc0219020) |
| |
| #define CH0_EMI_CONC (volatile kal_uint32*)(0xC0235010) |
| #define CH1_EMI_CONC (volatile kal_uint32*)(0xC0245010) |
| |
| #define EMI_QOS_CTRL1 (volatile kal_uint32*)(0xc0219DF4) |
| |
| #define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(0xc0219D2C) |
| #define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(0xc0219D30) |
| |
| /***********************/ |
| #define EMI_FORCE_LATENCY(r, w) \ |
| do {\ |
| *EMI_TESTC |= 1<<19;\ |
| *EMI_CONH_2ND |= 1<<9;\ |
| *EMI_BWLMTE_4TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_4TH |= 0xFFFF;\ |
| *EMI_BWLMTE_5TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_5TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTG_5TH = 0xFFFFFFFF;\ |
| *EMI_BWLMTE = 0xFF00FFFF;\ |
| *EMI_BWLMTF |= 0xFFFF;\ |
| *EMI_BWLMTE_2ND = 0xFFFFFFFF;\ |
| *EMI_BWLMTF_2ND = 0xFFFF0000;\ |
| *EMI_BWLMTG_2ND = 0xFFFFFFFF;\ |
| *EMI_ARBD |= 1<<13;\ |
| *EMI_ARBD &= ~(1<<14);\ |
| *EMI_MDCT &= ~((1<<1)|(1<<3));\ |
| *EMI_THRO_PRD2 |= (7<<24) | (7<<28);\ |
| \ |
| *EMI_QOS_MDR_BE0A = 0;\ |
| *EMI_QOS_MDR_BE0B = 0;\ |
| *EMI_QOS_MDR_BE1A = 0;\ |
| *EMI_QOS_MDR_BE1B = 0;\ |
| *EMI_QOS_MDW_BE0A = 0;\ |
| *EMI_QOS_MDW_BE0B = 0;\ |
| *EMI_QOS_MDW_BE1A = 0;\ |
| *EMI_QOS_MDW_BE1B = 0;\ |
| \ |
| *EMI_QOS_MDHWR_BE0A = 0;\ |
| *EMI_QOS_MDHWR_BE0B = 0;\ |
| *EMI_QOS_MDHWR_BE1A = 0;\ |
| *EMI_QOS_MDHWR_BE1B = 0;\ |
| *EMI_QOS_MDHWW_BE0A = 0;\ |
| *EMI_QOS_MDHWW_BE0B = 0;\ |
| *EMI_QOS_MDHWW_BE1A = 0;\ |
| *EMI_QOS_MDHWW_BE1B = 0;\ |
| \ |
| *EMI_ARBD = (*EMI_ARBD&0x00FFFFFF) | (w<<24);\ |
| *EMI_ARBE_2ND = (*EMI_ARBE_2ND&0x00FFFFFF) | (w<<24);\ |
| \ |
| *EMI_CONE |= 1 ;\ |
| \ |
| *CH0_EMI_CONC |= (1<<5) ;\ |
| *CH1_EMI_CONC |= (1<<5) ;\ |
| \ |
| *EMI_QOS_CTRL1 &= ~((0x1<<11)|(0x1<<27));\ |
| \ |
| *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0&0xffffff00) | w;\ |
| *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1&0xffffff00) | w;\ |
| \ |
| *EMI_ARBE_2ND = (*EMI_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\ |
| *EMI_ARBD = (*EMI_ARBD & 0xFF00FFFF) | (r<<16) ;\ |
| *EMI_QOS_MDR_SHF0 = (*EMI_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\ |
| *EMI_QOS_MDR_SHF1 = (*EMI_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\ |
| \ |
| *EMI_CH0_TESTB |= ((1<<6)|(1<<13)) ; \ |
| *EMI_CH1_TESTB |= ((1<<6)|(1<<13)) ; \ |
| } while (0) |
| |
| #define EMI_AGING_26M() \ |
| do {\ |
| *EMI_CONE &= ~(1<<0) ;\ |
| *CH0_EMI_CONC &= ~(1<<5) ;\ |
| *CH1_EMI_CONC &= ~(1<<5) ;\ |
| } while (0) |
| |
| |
| #define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \ |
| do {\ |
| *EMI_CH0_TESTB |= (1<<11) ; \ |
| *EMI_CH1_TESTB |= (1<<11) ; \ |
| } while(0) |
| |
| #define FORCE_MD_ULTRA(p) \ |
| do {\ |
| if(p==0){\ |
| DRV_ClrReg32(0xa0060064,(0xf << 8)); \ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x0);\ |
| DRV_WriteReg32(0xa4c00000+0x8658, 0x0);\ |
| }else{\ |
| DRV_SetReg32(0xa0060064,(0xf << 8)); \ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x7EF);\ |
| DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x7E00000);\ |
| DRV_WriteReg32(0xa4c00000+0x8658, 0x2AAAA);\ |
| }\ |
| } while(0) |
| |
| #else |
| #error "No support force emi latency on this project" |
| #endif |
| |
| #endif //__FORCE_EMI_LATENCY_ENABLE__ |
| |
| |
| //for spv_service.c |
| typedef struct _ELM_BW_LOG_T |
| { |
| kal_uint32 m3_r_word_count; |
| kal_uint32 m3_w_word_count; |
| kal_uint32 m4_r_word_count; |
| kal_uint32 m4_w_word_count; |
| } ELM_BW_LOG_T; |
| |
| typedef struct __SPVSVC_MON { |
| kal_uint32 apb_Reliable; |
| kal_uint32 apb_CurIsWorst; |
| kal_uint32 apb_Duration; |
| kal_uint32 apb_Avg_RLat; |
| kal_uint32 apb_Avg_WLat; |
| kal_uint32 apb_Worst_AvgRLat; |
| kal_uint32 apb_Worst_AvgWLat; |
| kal_uint32 apb_Total_RCnt; |
| kal_uint32 apb_Total_WCnt; |
| kal_uint32 apb_Dummy0; |
| |
| kal_uint32 cm2_Reliable; |
| kal_uint32 cm2_CurIsWorst; |
| kal_uint32 cm2_Duration; |
| kal_uint32 cm2_Avg_UC_RW; |
| kal_uint32 cm2_Avg_L2Cache_RW; |
| kal_uint32 cm2_Worst_AvgUC_RW; |
| kal_uint32 cm2_Worst_AvgL2Cache_RW; |
| kal_uint32 cm2_Total_UC_RW; |
| kal_uint32 cm2_Total_L2Cache_RW; |
| kal_uint32 cm2_Dummy0; |
| |
| //might use union? |
| kal_uint32 elm_Reliable; |
| kal_uint32 elm_CurIsWorst; |
| kal_uint32 elm_Duration; |
| kal_uint32 elm_Avg_RLat; |
| kal_uint32 elm_Avg_WLat; |
| kal_uint32 elm_Worst_AvgRLat; |
| kal_uint32 elm_Worst_AvgWLat; |
| kal_uint32 elm_Total_RCnt; |
| kal_uint32 elm_Total_WCnt; |
| kal_uint32 elm_Dummy0; |
| |
| } SPVSVC_MON; |
| |
| kal_bool SPVSVC_Monitor_Get(SPVSVC_MON *pCnts); |
| extern kal_bool SPVSVC_Monitor_LogClear(void); |
| |
| #if defined(__BW_RUNTIME_PF__) |
| |
| #if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__) |
| #define __MD_ELM_TLW__ |
| #endif |
| #define WRAP_MAX 0xFFFFFFFF |
| #define DIFF_WRAP_TYPE(start, end) (((end) >= (start))? (((end) - (start))): ((WRAP_MAX - (start) + (end) + 1))) |
| |
| #if defined(__MD_ELM_TLW__) |
| |
| typedef struct _ELM_PROFILING_LOG_T |
| { |
| kal_uint32 m3_r_transaction; |
| kal_uint32 m3_r_word_count; |
| kal_uint32 m3_r_latency; |
| kal_uint32 m3_w_transaction; |
| kal_uint32 m3_w_word_count; |
| kal_uint32 m3_w_latency; |
| kal_uint32 m4_r_transaction; |
| kal_uint32 m4_r_word_count; |
| kal_uint32 m4_r_latency; |
| kal_uint32 m4_w_transaction; |
| kal_uint32 m4_w_word_count; |
| kal_uint32 m4_w_latency; |
| #if defined(MT6297) |
| kal_uint32 m4b_r_transaction; |
| kal_uint32 m4b_r_word_count; |
| kal_uint32 m4b_r_latency; |
| kal_uint32 m4b_w_transaction; |
| kal_uint32 m4b_w_word_count; |
| kal_uint32 m4b_w_latency; |
| #endif |
| } ELM_PROFILING_LOG_T; |
| |
| #define ELM_GET_M3_BW_LOG(c, l) do { \ |
| ELM_GET_WC_CNT(ELM_RD, (c), &((l).m3_r_word_count));\ |
| ELM_GET_WC_CNT(ELM_WR, (c), &((l).m3_w_word_count));\ |
| } while (0) |
| |
| #define ELM_GET_M4_BW_LOG(c, l) do { \ |
| ELM_INFRA_GET_WC_CNT(ELM_RD, (c), &((l).m4_r_word_count));\ |
| ELM_INFRA_GET_WC_CNT(ELM_WR, (c), &((l).m4_w_word_count));\ |
| } while (0) |
| |
| #define ELM_GET_M3_LATENCY_LOG(c, l) do { \ |
| ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m3_r_transaction));\ |
| ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m3_r_latency));\ |
| ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m3_w_transaction));\ |
| ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m3_w_latency));\ |
| } while (0) |
| |
| #define ELM_GET_M4_LATENCY_LOG(c, l) do { \ |
| ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4_r_transaction));\ |
| ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4_r_latency));\ |
| ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4_w_transaction));\ |
| ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4_w_latency));\ |
| } while (0) |
| |
| #if defined(MT6297) |
| #define ELM_GET_M4B_LATENCY_LOG(c, l) do { \ |
| ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4b_r_transaction));\ |
| ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4b_r_latency));\ |
| ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4b_w_transaction));\ |
| ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4b_w_latency));\ |
| } while (0) |
| #define ELM_GET_M4B_BW_LOG(c, l) do { \ |
| ELM_INFRA_B_GET_WC_CNT(ELM_RD, (c), &((l).m4b_r_word_count));\ |
| ELM_INFRA_B_GET_WC_CNT(ELM_WR, (c), &((l).m4b_w_word_count));\ |
| } while (0) |
| #endif |
| |
| #else |
| |
| typedef struct _ELM_PROFILING_LOG_T |
| { |
| kal_uint32 m3_r_transaction; |
| kal_uint32 m3_r_word_count; |
| kal_uint32 m3_r_latency; |
| kal_uint32 m3_w_word_count; |
| kal_uint32 m4_r_transaction; |
| kal_uint32 m4_r_word_count; |
| kal_uint32 m4_r_latency; |
| kal_uint32 m4_w_word_count; |
| } ELM_PROFILING_LOG_T; |
| |
| #define ELM_GET_M3_BW_LOG(c, l) do { \ |
| ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m3_r_word_count));\ |
| ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m3_w_word_count));\ |
| } while (0) |
| |
| #define ELM_GET_M4_BW_LOG(c, l) do { \ |
| ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4_r_word_count));\ |
| ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4_w_word_count));\ |
| } while (0) |
| |
| #define ELM_GET_M3_LATENCY_LOG(c, l) do { \ |
| ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m3_r_transaction));\ |
| ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m3_r_latency));\ |
| } while (0) |
| |
| #define ELM_GET_M4_LATENCY_LOG(c, l) do { \ |
| ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4_r_transaction));\ |
| ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4_r_latency));\ |
| } while (0) |
| |
| #endif /* __MD_ELM_TLW__ */ |
| |
| |
| kal_bool SPVSVC_BW_PF(kal_uint32 core_id); |
| void SPVSVC_BW_Max_Print(void); |
| void SPVSVC_BW_Max_Clear(void); |
| void SPVSVC_BW_Threshold_Print(void); |
| |
| extern volatile kal_uint32 RECORD_AP_DVFSRC; |
| extern volatile kal_uint32 BW_index; |
| extern kal_uint32 BW_Cor_Duration[] ; |
| extern kal_uint32 BW_Cor_Duration_Low[] ; |
| extern kal_uint32 BW_Cor_Duration_High[] ; |
| |
| extern volatile kal_uint32 BW_Cor_Duration_core[] ; |
| |
| extern volatile kal_uint32 BW_Cor_Enable; |
| |
| extern volatile kal_uint32 BW_M3_Worst_core[]; |
| extern volatile kal_uint32 BW_M3_Worst_Dur_core[]; |
| extern volatile kal_uint32 BW_M4_Worst_core[] ; |
| extern volatile kal_uint32 BW_M4_Worst_Dur_core[]; |
| extern volatile kal_uint32 BW_M3M4_Worst_core[]; |
| extern volatile kal_uint32 BW_M3M4_Worst_Dur_core[]; |
| |
| |
| extern volatile kal_uint32 BW_Dur_Low_core[] ; |
| extern volatile kal_uint32 BW_Dur_High_core[]; |
| |
| extern volatile kal_uint32 BW_Cor_Raw_Data_Print_Enable; |
| |
| extern volatile kal_uint32 BW_Transaction_Low_core[]; |
| |
| extern volatile kal_uint32 BW_M3_Assertion_core[]; |
| extern volatile kal_uint32 BW_M4_Assertion_core[]; |
| extern volatile kal_uint32 BW_M3M4_Assertion_core[]; |
| extern volatile kal_uint32 Latency_M3_Read_Assertion_core[]; |
| extern volatile kal_uint32 Latency_M4_Read_Assertion_core[]; |
| #if defined(__MD_ELM_TLW__) |
| extern volatile kal_uint32 Latency_M3_Write_Assertion_core[]; |
| extern volatile kal_uint32 Latency_M4_Write_Assertion_core[]; |
| #endif |
| |
| extern void SPV_IdleTask0( task_entry_struct * task_entry_ptr ); |
| extern void SPV_IdleTask1( task_entry_struct * task_entry_ptr ); |
| extern void SPV_IdleTask2( task_entry_struct * task_entry_ptr ); |
| extern void SPV_IdleTask3( task_entry_struct * task_entry_ptr ); |
| |
| #endif /* defined(__BW_RUNTIME_PF__) */ |
| |
| #if 0 // official load profiling |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| #endif |
| |
| void SSS_PF_INIT(void); |
| void SSS_CORE_PMU_PF_WriteRecord(kal_uint32 flag); |
| void SSS_CORE_PMU_PF_START(void); |
| void SSS_CORE_PMU_PF_END(void); |
| #if defined(__SPV_SSS_PF__) |
| #if defined(__SPV_SSS_CORE_PMU_PF__) |
| #if defined(__MIPS16__) |
| #if defined(__GNUC__) |
| #define SSS_MIPS32_ISA __attribute__((nomips16)) |
| #endif |
| #endif |
| |
| #ifndef SSS_MIPS32_ISA |
| #define SSS_MIPS32_ISA |
| #endif |
| |
| #define SSS_MIPS32_INLINE INLINE SSS_MIPS32_ISA |
| #define STATIC_INLINE \ |
| __attribute__((always_inline)) SSS_MIPS32_ISA static |
| |
| #if defined(__MD95__) |
| #define MAX_CORE_PMU_NUM_PER_VPE 8 // 2 pmu counters per TC, 4 TCs per-core => 2*4 = 8 |
| #elif defined(__MD97__) || defined(__MD97P__) |
| #define MAX_CORE_PMU_NUM_PER_VPE 12 // 4 pmu counters per VPE, 3 VPEs per-core => 4*3 = 12 |
| #endif |
| |
| typedef struct { |
| kal_int32 core_pmu_enable_return_state; |
| kal_int32 core_pmu_disable_return_state; |
| kal_int32 core_pmu_dump_return_state; |
| kal_uint32 frc_start; |
| kal_uint32 frc_end; |
| kal_uint32 cpu_cycle_start; |
| kal_uint32 core_pmu[MAX_CORE_PMU_NUM_PER_VPE]; |
| kal_uint32 cpu_cycle_end; |
| } SSS_CORE_PMU_PF_RECORD; |
| |
| #endif /* __SPV_SSS_CORE_PMU_PF__ */ |
| #endif /* __SPV_SSS_PF__ */ |
| |
| #endif //__SPV_API_H_ |
| |