commit 2b1408e6af87960b8264f9f352bece1d1bdd8773
author rjw <rjw@exm.com> Mon Dec 19 11:19:29 2022 +0800
committer rjw <rjw@exm.com> Mon Dec 19 11:19:29 2022 +0800
tree e143cadb8255686803ab833538374bb064960412
parent a82f26271d102f6e307a3625162d4031eb42d406

[Feature][Modem]1.merge MTK P2 patch 2.RF:bias modification of frequency band

Change-Id: I846de8f085e50c1b9557ad8c5d0b2cc088b18d86

mcu/interface/service/nvram/csg_nvram_def.h

diff --git a/mcu/interface/service/nvram/csg_nvram_def.h b/mcu/interface/service/nvram/csg_nvram_def.h
index 66448f9..246c4d8 100755
--- a/mcu/interface/service/nvram/csg_nvram_def.h
+++ b/mcu/interface/service/nvram/csg_nvram_def.h
@@ -59,6 +59,9 @@
  *
  * removed!
  * removed!
+ *
+ * removed!
+ * removed!
  * removed!
  * removed!
  * removed!
@@ -95,15 +98,17 @@
 
 // VERNO
 #if (defined(__3G_CSG_SUPPORT__) || defined(__LTE_RAT__))
-#define NVRAM_EF_UE_CSG_LIST_LID_VERNO                       "001"
-#define NVRAM_EF_UE_CSG_LIST_LID_HASH                        0x4D0D10AA
+#define NVRAM_EF_UE_CSG_LIST_LID_VERNO                       "002"
+#define NVRAM_EF_UE_CSG_LIST_LID_HASH                        0x2B76AE90
 #endif
 
 #if (defined(__3G_CSG_SUPPORT__) || defined(__LTE_RAT__))
 
 // Size and Total 
+#define NVRAM_EF_UE_CSG_SIZE                                   (sizeof(nvram_ef_ue_csg_list_struct))
 #define NVRAM_EF_UE_CSG_LIST_SIZE                              2500
 #define NVRAM_EF_UE_CSG_LIST_TOTAL                             (1 * NVRAM_DUAL_RECORD)
+#define NVRAM_EF_UE_CSG_IMSI_MAX_LEN                           15
 #endif
 
 #ifdef __cplusplus