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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/common/interface/driver/sys_drv/cmif/cmif_c2m_isr_config_u3g.h b/common/interface/driver/sys_drv/cmif/cmif_c2m_isr_config_u3g.h
new file mode 100644
index 0000000..b2135c9
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/cmif_c2m_isr_config_u3g.h
@@ -0,0 +1,254 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ_LOADER_OFF)
+irq_name("CMIF_C2M_U3G_IRQ_LOADER_OFF")
+irq_entry_function(rake_loader_off_isr)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ1)
+irq_name("CMIF_C2M_U3G_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ2)
+irq_name("CMIF_C2M_U3G_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(C2M_DEACTIVATE_IRQ)
+irq_name("C2M_DEACTIVATE_IRQ")
+irq_entry_function(sleep_irq_comment)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(C2M_ACTIVATE_IRQ)
+irq_name("C2M_ACTIVATE_IRQ")
+irq_entry_function(abort_irq_comment)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ5)
+irq_name("CMIF_C2M_U3G_IRQ5")
+irq_entry_function(loader_run_time_ddl_it_empty)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ6)
+irq_name("CMIF_C2M_U3G_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ7)
+irq_name("CMIF_C2M_U3G_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ8)
+irq_name("CMIF_C2M_U3G_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ9)
+irq_name("CMIF_C2M_U3G_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQA)
+irq_name("CMIF_C2M_U3G_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQB)
+irq_name("CMIF_C2M_U3G_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQC)
+irq_name("CMIF_C2M_U3G_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQD)
+irq_name("CMIF_C2M_U3G_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQE)
+irq_name("CMIF_C2M_U3G_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQF)
+irq_name("CMIF_C2M_U3G_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ10)
+irq_name("CMIF_C2M_U3G_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ11)
+irq_name("CMIF_C2M_U3G_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ12)
+irq_name("CMIF_C2M_U3G_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ13)
+irq_name("CMIF_C2M_U3G_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ14)
+irq_name("CMIF_C2M_U3G_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ15)
+irq_name("CMIF_C2M_U3G_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ16)
+irq_name("CMIF_C2M_U3G_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ17)
+irq_name("CMIF_C2M_U3G_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ18)
+irq_name("CMIF_C2M_U3G_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ19)
+irq_name("CMIF_C2M_U3G_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ1A)
+irq_name("CMIF_C2M_U3G_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ1B)
+irq_name("CMIF_C2M_U3G_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ1C)
+irq_name("CMIF_C2M_U3G_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ1D)
+irq_name("CMIF_C2M_U3G_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_U3G_IRQ1E)
+irq_name("CMIF_C2M_U3G_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_C2M_RAKE_ULSP_UT)
+irq_name("CMIF_C2M_RAKE_ULSP_UT")
+irq_entry_function(ulsp_ut_handler)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cmif/cmif_common_def.h b/common/interface/driver/sys_drv/cmif/cmif_common_def.h
new file mode 100644
index 0000000..75bb8a0
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/cmif_common_def.h
@@ -0,0 +1,60 @@
+/*******************************************************************************
+* please DO NOT include this file
+* this file is for usip/dsp cmif driver include only
+********************************************************************************/
+#ifndef __CMIF_COMMON_DEF_H__
+#define __CMIF_COMMON_DEF_H__
+
+#include "xmif_common_def.h"
+
+/*******************************************************************************
+ * Enums
+ ******************************************************************************/
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(index) index,
+#define irq_name(name)
+#define irq_entry_function(fun)
+#define irq_auto_eoi(eoi)
+
+typedef enum CMIF_CODE_C2M_U3G_RAKE_Enum{
+ #include "cmif_c2m_isr_config_u3g.h"
+ CMIF_C2M_U3G_TOTAL_NUMBER_RAKE
+}CMIF_C2M_U3G_Code_t;
+
+typedef enum CMIF_CODE_M2C_U3G_RAKE_Enum{
+ #include "cmif_m2c_isr_config_u3g_rake.h"
+ CMIF_M2C_U3G_TOTAL_NUMBER_RAKE
+}CMIF_M2C_U3G_Code_t;
+
+typedef enum CMIF_CODE_M2C_FPC_1X_Enum{
+ #include "cmif_m2c_isr_config_fpc_1x.h"
+ CMIF_M2C_FPC_1X_TOTAL_NUMBER
+}CMIF_M2C_FPC_1X_Code_t;
+
+typedef enum CMIF_CODE_M2C_DO_PD_Enum{
+ #include "cmif_m2c_isr_config_do_pd.h"
+ CMIF_M2C_DO_PD_TOTAL_NUMBER
+}CMIF_M2C_DO_PD_Code_t;
+
+typedef enum CMIF_CODE_M2C_FOE_1X_Enum{
+ #include "cmif_m2c_isr_config_foe_1x.h"
+ CMIF_M2C_FOE_1X_TOTAL_NUMBER
+}CMIF_M2C_FOE_1X_Code_t;
+
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(index)
+#define irq_name(name)
+#define irq_entry_function(fun)
+#define irq_auto_eoi(eoi)
+
+#endif /* __CMIF_COMMON_DEF_H__ */
+
diff --git a/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_do_pd.h b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_do_pd.h
new file mode 100644
index 0000000..64cf5ea
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_do_pd.h
@@ -0,0 +1,259 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ0)
+irq_name("CMIF_M2C_DO_PD_IRQ0")
+#ifdef __C2K_RAT__
+irq_entry_function(FmpHwSlotFoundLisr)
+#else
+irq_entry_function(CMIF_DefaultISR)
+#endif
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1)
+irq_name("CMIF_M2C_DO_PD_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ2)
+irq_name("CMIF_M2C_DO_PD_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ3)
+irq_name("CMIF_M2C_DO_PD_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ4)
+irq_name("CMIF_M2C_DO_PD_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ5)
+irq_name("CMIF_M2C_DO_PD_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ6)
+irq_name("CMIF_M2C_DO_PD_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ7)
+irq_name("CMIF_M2C_DO_PD_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ8)
+irq_name("CMIF_M2C_DO_PD_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ9)
+irq_name("CMIF_M2C_DO_PD_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQA)
+irq_name("CMIF_M2C_DO_PD_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQB)
+irq_name("CMIF_M2C_DO_PD_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQC)
+irq_name("CMIF_M2C_DO_PD_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQD)
+irq_name("CMIF_M2C_DO_PD_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQE)
+irq_name("CMIF_M2C_DO_PD_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQF)
+irq_name("CMIF_M2C_DO_PD_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ10)
+irq_name("CMIF_M2C_DO_PD_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ11)
+irq_name("CMIF_M2C_DO_PD_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ12)
+irq_name("CMIF_M2C_DO_PD_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ13)
+irq_name("CMIF_M2C_DO_PD_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ14)
+irq_name("CMIF_M2C_DO_PD_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ15)
+irq_name("CMIF_M2C_DO_PD_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ16)
+irq_name("CMIF_M2C_DO_PD_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ17)
+irq_name("CMIF_M2C_DO_PD_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ18)
+irq_name("CMIF_M2C_DO_PD_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ19)
+irq_name("CMIF_M2C_DO_PD_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1A)
+irq_name("CMIF_M2C_DO_PD_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1B)
+irq_name("CMIF_M2C_DO_PD_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1C)
+irq_name("CMIF_M2C_DO_PD_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1D)
+irq_name("CMIF_M2C_DO_PD_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1E)
+irq_name("CMIF_M2C_DO_PD_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1F)
+irq_name("CMIF_M2C_DO_PD_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_foe_1x.h b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_foe_1x.h
new file mode 100644
index 0000000..7cb7e2a
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_foe_1x.h
@@ -0,0 +1,255 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ0)
+irq_name("CMIF_M2C_FOE_1X_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1)
+irq_name("CMIF_M2C_FOE_1X_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ2)
+irq_name("CMIF_M2C_FOE_1X_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ3)
+irq_name("CMIF_M2C_FOE_1X_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ4)
+irq_name("CMIF_M2C_FOE_1X_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ5)
+irq_name("CMIF_M2C_FOE_1X_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ6)
+irq_name("CMIF_M2C_FOE_1X_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ7)
+irq_name("CMIF_M2C_FOE_1X_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ8)
+irq_name("CMIF_M2C_FOE_1X_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ9)
+irq_name("CMIF_M2C_FOE_1X_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQA)
+irq_name("CMIF_M2C_FOE_1X_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQB)
+irq_name("CMIF_M2C_FOE_1X_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQC)
+irq_name("CMIF_M2C_FOE_1X_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQD)
+irq_name("CMIF_M2C_FOE_1X_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQE)
+irq_name("CMIF_M2C_FOE_1X_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQF)
+irq_name("CMIF_M2C_FOE_1X_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ10)
+irq_name("CMIF_M2C_FOE_1X_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ11)
+irq_name("CMIF_M2C_FOE_1X_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ12)
+irq_name("CMIF_M2C_FOE_1X_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ13)
+irq_name("CMIF_M2C_FOE_1X_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ14)
+irq_name("CMIF_M2C_FOE_1X_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ15)
+irq_name("CMIF_M2C_FOE_1X_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ16)
+irq_name("CMIF_M2C_FOE_1X_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ17)
+irq_name("CMIF_M2C_FOE_1X_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ18)
+irq_name("CMIF_M2C_FOE_1X_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ19)
+irq_name("CMIF_M2C_FOE_1X_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1A)
+irq_name("CMIF_M2C_FOE_1X_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1B)
+irq_name("CMIF_M2C_FOE_1X_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1C)
+irq_name("CMIF_M2C_FOE_1X_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1D)
+irq_name("CMIF_M2C_FOE_1X_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1E)
+irq_name("CMIF_M2C_FOE_1X_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1F)
+irq_name("CMIF_M2C_FOE_1X_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_fpc_1x.h b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_fpc_1x.h
new file mode 100644
index 0000000..c8bd49a
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_fpc_1x.h
@@ -0,0 +1,255 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ0)
+irq_name("CMIF_M2C_FPC_1X_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1)
+irq_name("CMIF_M2C_FPC_1X_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ2)
+irq_name("CMIF_M2C_FPC_1X_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ3)
+irq_name("CMIF_M2C_FPC_1X_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ4)
+irq_name("CMIF_M2C_FPC_1X_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ5)
+irq_name("CMIF_M2C_FPC_1X_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ6)
+irq_name("CMIF_M2C_FPC_1X_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ7)
+irq_name("CMIF_M2C_FPC_1X_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ8)
+irq_name("CMIF_M2C_FPC_1X_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ9)
+irq_name("CMIF_M2C_FPC_1X_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQA)
+irq_name("CMIF_M2C_FPC_1X_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQB)
+irq_name("CMIF_M2C_FPC_1X_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQC)
+irq_name("CMIF_M2C_FPC_1X_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQD)
+irq_name("CMIF_M2C_FPC_1X_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQE)
+irq_name("CMIF_M2C_FPC_1X_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQF)
+irq_name("CMIF_M2C_FPC_1X_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ10)
+irq_name("CMIF_M2C_FPC_1X_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ11)
+irq_name("CMIF_M2C_FPC_1X_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ12)
+irq_name("CMIF_M2C_FPC_1X_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ13)
+irq_name("CMIF_M2C_FPC_1X_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ14)
+irq_name("CMIF_M2C_FPC_1X_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ15)
+irq_name("CMIF_M2C_FPC_1X_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ16)
+irq_name("CMIF_M2C_FPC_1X_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ17)
+irq_name("CMIF_M2C_FPC_1X_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ18)
+irq_name("CMIF_M2C_FPC_1X_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ19)
+irq_name("CMIF_M2C_FPC_1X_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1A)
+irq_name("CMIF_M2C_FPC_1X_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1B)
+irq_name("CMIF_M2C_FPC_1X_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1C)
+irq_name("CMIF_M2C_FPC_1X_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1D)
+irq_name("CMIF_M2C_FPC_1X_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1E)
+irq_name("CMIF_M2C_FPC_1X_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1F)
+irq_name("CMIF_M2C_FPC_1X_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_u3g_rake.h b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_u3g_rake.h
new file mode 100644
index 0000000..47893a4
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_u3g_rake.h
@@ -0,0 +1,255 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ0)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(RAKE_IRQ_M2C_U3G_IRQ_STA_AI)
+irq_name("RAKE_IRQ_M2C_U3G_IRQ_STA_AI")
+irq_entry_function(UL1D_RAKE_Interrupt_Handler)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(RAKE_IRQ_M2C_U3G_IRQ_STA_PI)
+irq_name("RAKE_IRQ_M2C_U3G_IRQ_STA_PI")
+irq_entry_function(UL1D_RAKE_Interrupt_Handler)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(RAKE_IRQ_M2C_U3G_IRQ_STA_TFCI_0)
+irq_name("RAKE_IRQ_M2C_U3G_IRQ_STA_TFCI_0")
+irq_entry_function(UL1D_RAKE_Interrupt_Handler)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(RAKE_IRQ_M2C_U3G_IRQ_STA_TFCI_1)
+irq_name("RAKE_IRQ_M2C_U3G_IRQ_STA_TFCI_1")
+irq_entry_function(UL1D_RAKE_Interrupt_Handler)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ5)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ6)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ7)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ8)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ9)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQA)
+irq_name("CMIF_M2C_U3G_RAKE_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQB)
+irq_name("CMIF_M2C_U3G_RAKE_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQC)
+irq_name("CMIF_M2C_U3G_RAKE_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQD)
+irq_name("CMIF_M2C_U3G_RAKE_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQE)
+irq_name("CMIF_M2C_U3G_RAKE_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQF)
+irq_name("CMIF_M2C_U3G_RAKE_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ10)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ11)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ12)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ13)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ14)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ15)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ16)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ17)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ18)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ19)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1A)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1B)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1C)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1D)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1E)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1F)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cmif/xmif_common_def.h b/common/interface/driver/sys_drv/cmif/xmif_common_def.h
new file mode 100644
index 0000000..839c0e7
--- /dev/null
+++ b/common/interface/driver/sys_drv/cmif/xmif_common_def.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+* please DO NOT include this file
+* this file is for usip/dsp cmif driver include only
+********************************************************************************/
+
+#ifndef __XMIF_COMMON_DEF_H__
+#define __XMIF_COMMON_DEF_H__
+
+#define CMIF_M2C_WFI_RAKE_INTERRUPT_STATUS_OFFSET (0x00)
+#define CMIF_M2C_WFI_RAKE_INTERRUPT_MASK_OFFSET (0x04)
+#define CMIF_M2C_WFI_RAKE_INTERRUPT_CLEAN_OFFSET (0x04)
+#define CMIF_M2C_CTI_EVENT_OFFSET (0x08)
+
+/* MCU, Rake use */
+#define CMIF_C2M_U3G_RAKE_INTERRUPT_STATUS_OFFSET (0x0C)
+#define CMIF_C2M_U3G_RAKE_INTERRUPT_SET_OFFSET (0x10)
+#define CMIF_C2M_U3G_RAKE_INTERRUPT_CLEAN_OFFSET (0x10)
+
+#define CMIF_M2C_U3G_RAKE_INTERRUPT_STATUS_OFFSET (0x14)
+#define CMIF_M2C_U3G_RAKE_INTERRUPT_SET_OFFSET (0x18)
+#define CMIF_M2C_U3G_RAKE_INTERRUPT_CLEAN_OFFSET (0x18)
+
+#define CMIF_M2C_FPC_1X_RAKE_INTERRUPT_STATUS_OFFSET (0x1C)
+#define CMIF_M2C_FPC_1X_RAKE_INTERRUPT_SET_OFFSET (0x20)
+#define CMIF_M2C_FPC_1X_RAKE_INTERRUPT_CLEAN_OFFSET (0x20)
+
+#define CMIF_M2C_DO_PD_RAKE_INTERRUPT_STATUS_OFFSET (0x24)
+#define CMIF_M2C_DO_PD_RAKE_INTERRUPT_SET_OFFSET (0x28)
+#define CMIF_M2C_DO_PD_RAKE_INTERRUPT_CLEAN_OFFSET (0x28)
+
+#define CMIF_M2C_FOE_1X_RAKE_INTERRUPT_STATUS_OFFSET (0x2C)
+#define CMIF_M2C_FOE_1X_RAKE_INTERRUPT_SET_OFFSET (0x30)
+#define CMIF_M2C_FOE_1X_RAKE_INTERRUPT_CLEAN_OFFSET (0x30)
+
+/* USIP, Rake use */
+#define UMIF_U2M_INN_RAKE_INTERRUPT_STATUS_OFFSET (0x34)
+#define UMIF_U2M_INN_RAKE_INTERRUPT_SET_OFFSET (0x38)
+#define UMIF_U2M_INN_RAKE_INTERRUPT_CLEAN_OFFSET (0x38)
+
+#define UMIF_M2U_INN_RAKE_INTERRUPT_STATUS_OFFSET (0x3C)
+#define UMIF_M2U_INN_RAKE_INTERRUPT_SET_OFFSET (0x40)
+#define UMIF_M2U_INN_RAKE_INTERRUPT_CLEAN_OFFSET (0x40)
+
+#define UMIF_U2M_OUT_RAKE_INTERRUPT_STATUS_OFFSET (0x44)
+#define UMIF_U2M_OUT_RAKE_INTERRUPT_SET_OFFSET (0x48)
+#define UMIF_U2M_OUT_RAKE_INTERRUPT_CLEAN_OFFSET (0x48)
+
+#define UMIF_M2U_OUT_RAKE_INTERRUPT_STATUS_OFFSET (0x4C)
+#define UMIF_M2U_OUT_RAKE_INTERRUPT_SET_OFFSET (0x50)
+#define UMIF_M2U_OUT_RAKE_INTERRUPT_CLEAN_OFFSET (0x50)
+
+#define XMIF_REGISTER_OFFSET (0x54)
+
+#define XMIF_NUM_INTERRUPT_SOURCES (32)
+
+// Define status register type
+typedef struct{
+ kal_uint32 mask31_0;
+ kal_uint32 *status_reg_addr;
+} CMIF_Mask_t;
+
+#define CMIF_TRUE KAL_TRUE
+#define CMIF_FALSE KAL_FALSE
+
+#endif /* __XMIF_COMMON_DEF_H__ */
+
diff --git a/common/interface/driver/sys_drv/config/gen93_proj_config.h b/common/interface/driver/sys_drv/config/gen93_proj_config.h
new file mode 100644
index 0000000..1be519a
--- /dev/null
+++ b/common/interface/driver/sys_drv/config/gen93_proj_config.h
@@ -0,0 +1,13 @@
+#ifndef __GEN93_PROJ_CONFIG_H__
+#define __GEN93_PROJ_CONFIG_H__
+
+#if defined(MT6763) || defined(MT6293)
+#define __CMIF_DRV_SW_WORKAROUND__
+#undef __SUPPORT_RAKE_TBUF_MON_PC__
+#else
+#undef __CMIF_DRV_SW_WORKAROUND__
+#define __SUPPORT_RAKE_TBUF_MON_PC__
+#endif
+
+#endif // __GEN93_PROJ_CONFIG_H__
+
diff --git a/common/interface/driver/sys_drv/csif/csif_common_def.h b/common/interface/driver/sys_drv/csif/csif_common_def.h
new file mode 100644
index 0000000..df5ed73
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/csif_common_def.h
@@ -0,0 +1,710 @@
+/*******************************************
+* please DO NOT include this file
+* this file is for mcu/dsp csif driver include only
+************************************************/
+
+/*******************************************************************************
+ * IRQ Enums
+ *******************************************************************************/
+
+/* C2S IRQ */
+
+#undef M_CSIF_C2S_INFO
+#define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIF_C2S_ID_##Code=Value,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N0_Enum{
+ #include "mt6297/csif_c2s_isr_config_n0.h"
+ CSIF_C2S_N0_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N0_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N1_Enum{
+ //CSIF_C2S_N1_START_ID = 31,
+ #include "mt6297/csif_c2s_isr_config_n1.h"
+ CSIF_C2S_N1_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N1_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N2_Enum{
+ //CSIF_C2S_N2_START_ID = 63,
+ #include "mt6297/csif_c2s_isr_config_n2.h"
+ CSIF_C2S_N2_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N2_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N3_Enum{
+ //CSIF_C2S_N3_START_ID = 95,
+ #include "mt6297/csif_c2s_isr_config_n3.h"
+ CSIF_C2S_N3_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N3_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N0_Enum{
+ #include "mt6297p/csif_c2s_isr_config_n0.h"
+ CSIF_C2S_N0_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N0_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N1_Enum{
+ //CSIF_C2S_N1_START_ID = 31,
+ #include "mt6297p/csif_c2s_isr_config_n1.h"
+ CSIF_C2S_N1_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N1_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N2_Enum{
+ //CSIF_C2S_N2_START_ID = 63,
+ #include "mt6297p/csif_c2s_isr_config_n2.h"
+ CSIF_C2S_N2_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N2_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N3_Enum{
+ //CSIF_C2S_N3_START_ID = 95,
+ #include "mt6297p/csif_c2s_isr_config_n3.h"
+ CSIF_C2S_N3_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N3_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N4_Enum{
+ //CSIF_C2S_N4_START_ID = 127,
+ #include "mt6297p/csif_c2s_isr_config_n4.h"
+ CSIF_C2S_N4_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N4_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N5_Enum{
+ //CSIF_C2S_N5_START_ID = 159,
+ #include "mt6297p/csif_c2s_isr_config_n5.h"
+ CSIF_C2S_N5_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N5_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N6_Enum{
+ //CSIF_C2S_N6_START_ID = 191,
+ #include "mt6297p/csif_c2s_isr_config_n6.h"
+ CSIF_C2S_N6_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N6_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N7_Enum{
+ //CSIF_C2S_N7_START_ID = 223,
+ #include "mt6297p/csif_c2s_isr_config_n7.h"
+ CSIF_C2S_N7_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N7_ENUM_T;
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_C2S_INFO
+
+/* S2C IRQ*/
+
+#undef M_CSIF_S2C_INFO
+#define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIF_S2C_ID_##Code=Value,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N0_Enum{
+ #include "mt6297/csif_s2c_isr_config_n0.h"
+ CSIF_S2C_N0_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N0_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N1_Enum{
+ //CSIF_S2C_N1_START_ID = 31,
+ #include "mt6297/csif_s2c_isr_config_n1.h"
+ CSIF_S2C_N1_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N1_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N2_Enum{
+ //CSIF_S2C_N2_START_ID = 63,
+ #include "mt6297/csif_s2c_isr_config_n2.h"
+ CSIF_S2C_N2_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N2_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N3_Enum{
+ //CSIF_S2C_N3_START_ID = 95,
+ #include "mt6297/csif_s2c_isr_config_n3.h"
+ CSIF_S2C_N3_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N3_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N4_Enum{
+ //CSIF_S2C_N4_START_ID = 127,
+ #include "mt6297/csif_s2c_isr_config_n4.h"
+ CSIF_S2C_N4_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N4_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N5_Enum{
+ //CSIF_S2C_N5_START_ID = 159,
+ #include "mt6297/csif_s2c_isr_config_n5.h"
+ CSIF_S2C_N5_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N5_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N0_Enum{
+ #include "mt6297p/csif_s2c_isr_config_n0.h"
+ CSIF_S2C_N0_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N0_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N1_Enum{
+ //CSIF_S2C_N1_START_ID = 31,
+ #include "mt6297p/csif_s2c_isr_config_n1.h"
+ CSIF_S2C_N1_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N1_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N2_Enum{
+ //CSIF_S2C_N2_START_ID = 63,
+ #include "mt6297p/csif_s2c_isr_config_n2.h"
+ CSIF_S2C_N2_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N2_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N3_Enum{
+ //CSIF_S2C_N3_START_ID = 95,
+ #include "mt6297p/csif_s2c_isr_config_n3.h"
+ CSIF_S2C_N3_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N3_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N4_Enum{
+ //CSIF_S2C_N4_START_ID = 127,
+ #include "mt6297p/csif_s2c_isr_config_n4.h"
+ CSIF_S2C_N4_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N4_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N5_Enum{
+ //CSIF_S2C_N5_START_ID = 159,
+ #include "mt6297p/csif_s2c_isr_config_n5.h"
+ CSIF_S2C_N5_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N5_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N6_Enum{
+ //CSIF_S2C_N6_START_ID = 63,
+ #include "mt6297p/csif_s2c_isr_config_n6.h"
+ CSIF_S2C_N6_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N6_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N7_Enum{
+ //CSIF_S2C_N7_START_ID = 95,
+ #include "mt6297p/csif_s2c_isr_config_n7.h"
+ CSIF_S2C_N7_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N7_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N8_Enum{
+ //CSIF_S2C_N8_START_ID = 127,
+ #include "mt6297p/csif_s2c_isr_config_n8.h"
+ CSIF_S2C_N8_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N8_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N9_Enum{
+ //CSIF_S2C_N9_START_ID = 159,
+ #include "mt6297p/csif_s2c_isr_config_n9.h"
+ CSIF_S2C_N9_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N9_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N10_Enum{
+ #include "mt6297p/csif_s2c_isr_config_n10.h"
+ CSIF_S2C_N10_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N10_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N11_Enum{
+ //CSIF_S2C_N11_START_ID = 31,
+ #include "mt6297p/csif_s2c_isr_config_n11.h"
+ CSIF_S2C_N11_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N11_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N12_Enum{
+ //CSIF_S2C_N12_START_ID = 63,
+ #include "mt6297p/csif_s2c_isr_config_n12.h"
+ CSIF_S2C_N12_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N12_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N13_Enum{
+ //CSIF_S2C_N13_START_ID = 95,
+ #include "mt6297p/csif_s2c_isr_config_n13.h"
+ CSIF_S2C_N13_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N13_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N14_Enum{
+ //CSIF_S2C_N14_START_ID = 127,
+ #include "mt6297p/csif_s2c_isr_config_n14.h"
+ CSIF_S2C_N14_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N14_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N15_Enum{
+ //CSIF_S2C_N15_START_ID = 159,
+ #include "mt6297p/csif_s2c_isr_config_n15.h"
+ CSIF_S2C_N15_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N15_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N16_Enum{
+ //CSIF_S2C_N16_START_ID = 127,
+ #include "mt6297p/csif_s2c_hw_isr_config_n16.h"
+ CSIF_S2C_N16_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N16_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N17_Enum{
+ //CSIF_S2C_N17_START_ID = 159,
+ #include "mt6297p/csif_s2c_hw_isr_config_n17.h"
+ CSIF_S2C_N17_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N17_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N18_Enum{
+ #include "mt6297p/csif_s2c_hw_isr_config_n18.h"
+ CSIF_S2C_N18_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N18_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N19_Enum{
+ //CSIF_S2C_N19_START_ID = 31,
+ #include "mt6297p/csif_s2c_hw_isr_config_n19.h"
+ CSIF_S2C_N19_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N19_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N20_Enum{
+ //CSIF_S2C_N20_START_ID = 63,
+ #include "mt6297p/csif_s2c_hw_isr_config_n20.h"
+ CSIF_S2C_N20_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N20_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N21_Enum{
+ //CSIF_S2C_N21_START_ID = 95,
+ #include "mt6297p/csif_s2c_hw_isr_config_n21.h"
+ CSIF_S2C_N21_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N21_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N22_Enum{
+ //CSIF_S2C_N22_START_ID = 127,
+ #include "mt6297p/csif_s2c_hw_isr_config_n22.h"
+ CSIF_S2C_N22_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N22_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N23_Enum{
+ //CSIF_S2C_N23_START_ID = 159,
+ #include "mt6297p/csif_s2c_hw_isr_config_n23.h"
+ CSIF_S2C_N23_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N23_ENUM_T;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_S2C_INFO
+
+
+#if defined(__MSONIC__)
+/* DSP Error */
+#undef M_CSIF_DSP_ERR_INFO
+#define M_CSIF_DSP_ERR_INFO(CSIFErrHandler, Code, Value) CSIF_DSP_Err_##Code=Value,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_DSP_Err_InterruptHandlerCode_Enum{
+ #include "mt6297/csif_dsp_err_isr_config.h"
+ CSIF_DSP_ERR_TOTAL_NUMBER
+}CSIF_DSP_ERR_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_DSP_Err_InterruptHandlerCode_Enum{
+ #include "mt6297p/csif_dsp_err_isr_config.h"
+ CSIF_DSP_ERR_TOTAL_NUMBER
+}CSIF_DSP_ERR_ENUM_T;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_DSP_ERR_INFO
+
+#elif defined(__CR4__) || defined(__MIPS_I7200__) || defined(__MIPS_IA__)
+/* L1 Error */
+#undef M_CSIF_L1_ERR_INFO
+#define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) CSIF_L1_Err_##Code=Value,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_L1_Err_InterruptHandlerCode_Enum{
+ #include "mt6297/csif_l1_err_isr_config.h"
+ CSIF_L1_ERR_TOTAL_NUMBER
+}CSIF_L1_ERR_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_L1_Err_InterruptHandlerCode_Enum{
+ #include "mt6297p/csif_l1_err_isr_config.h"
+ CSIF_L1_ERR_TOTAL_NUMBER
+}CSIF_L1_ERR_ENUM_T;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_L1_ERR_INFO
+#else
+#error "not supported core"
+#endif
+
+
+/* CSIF C2S Int enum */
+typedef enum CSIF_C2S_Index_Enum{
+#if defined(__DSP_CODEBASE_MT6297__)
+ CSIF_ENUM_C2S_N0,
+ CSIF_ENUM_C2S_N1,
+ CSIF_ENUM_C2S_N2,
+ CSIF_ENUM_C2S_N3,
+#elif defined(__DSP_CODEBASE_MT6297P__)
+ CSIF_ENUM_C2S_N0,
+ CSIF_ENUM_C2S_N1,
+ CSIF_ENUM_C2S_N2,
+ CSIF_ENUM_C2S_N3,
+ CSIF_ENUM_C2S_N4,
+ CSIF_ENUM_C2S_N5,
+ CSIF_ENUM_C2S_N6,
+ CSIF_ENUM_C2S_N7,
+#else
+ #error "Not support this generation !!!!"
+#endif
+ CSIF_ENUM_ALL_C2S_INT_NUM
+}CSIF_C2S_INDEX;
+
+/* CSIF S2C Int enum */
+typedef enum CSIF_S2C_Index_Enum{
+#if defined(__DSP_CODEBASE_MT6297__)
+ CSIF_ENUM_S2C_N0,
+ CSIF_ENUM_S2C_N1,
+ CSIF_ENUM_S2C_N2,
+ CSIF_ENUM_S2C_N3,
+ CSIF_ENUM_S2C_N4,
+ CSIF_ENUM_S2C_N5,
+#elif defined(__DSP_CODEBASE_MT6297P__)
+ CSIF_ENUM_S2C_N0,
+ CSIF_ENUM_S2C_N1,
+ CSIF_ENUM_S2C_N2,
+ CSIF_ENUM_S2C_N3,
+ CSIF_ENUM_S2C_N4,
+ CSIF_ENUM_S2C_N5,
+ CSIF_ENUM_S2C_N6,
+ CSIF_ENUM_S2C_N7,
+ CSIF_ENUM_S2C_N8,
+ CSIF_ENUM_S2C_N9,
+ CSIF_ENUM_S2C_N10,
+ CSIF_ENUM_S2C_N11,
+ CSIF_ENUM_S2C_N12,
+ CSIF_ENUM_S2C_N13,
+ CSIF_ENUM_S2C_N14,
+ CSIF_ENUM_S2C_N15,
+ CSIF_ENUM_S2C_N16,
+ CSIF_ENUM_S2C_N17,
+ CSIF_ENUM_S2C_N18,
+ CSIF_ENUM_S2C_N19,
+ CSIF_ENUM_S2C_N20,
+ CSIF_ENUM_S2C_N21,
+ CSIF_ENUM_S2C_N22,
+ CSIF_ENUM_S2C_N23,
+#else
+ #error "Not support this generation !!!!"
+#endif
+ CSIF_ENUM_ALL_S2C_INT_NUM
+}CSIF_S2C_INDEX;
+
+/* CSIF S2C SW Int enum */
+typedef enum CSIF_S2C_SWIRQ_Index_Enum{
+#if defined(__DSP_CODEBASE_MT6297__)
+ CSIF_ENUM_S2C_SW_N0,
+ CSIF_ENUM_S2C_SW_N1,
+ CSIF_ENUM_S2C_SW_N2,
+ CSIF_ENUM_S2C_SW_N3,
+ CSIF_ENUM_S2C_SW_N4,
+ CSIF_ENUM_S2C_SW_N5,
+#elif defined(__DSP_CODEBASE_MT6297P__)
+ CSIF_ENUM_S2C_SW_N0,
+ CSIF_ENUM_S2C_SW_N1,
+ CSIF_ENUM_S2C_SW_N2,
+ CSIF_ENUM_S2C_SW_N3,
+ CSIF_ENUM_S2C_SW_N4,
+ CSIF_ENUM_S2C_SW_N5,
+ CSIF_ENUM_S2C_SW_N6,
+ CSIF_ENUM_S2C_SW_N7,
+ CSIF_ENUM_S2C_SW_N8,
+ CSIF_ENUM_S2C_SW_N9,
+ CSIF_ENUM_S2C_SW_N10,
+ CSIF_ENUM_S2C_SW_N11,
+ CSIF_ENUM_S2C_SW_N12,
+ CSIF_ENUM_S2C_SW_N13,
+ CSIF_ENUM_S2C_SW_N14,
+ CSIF_ENUM_S2C_SW_N15,
+#else
+ #error "Not support this generation !!!!"
+#endif
+ CSIF_ENUM_ALL_S2C_SW_INT_NUM
+}CSIF_S2C_SWIRQ_INDEX;
+
+/* CSIF S2C HW Int enum */
+typedef enum CSIF_S2C_HWIRQ_Index_Enum{
+#if defined(__DSP_CODEBASE_MT6297__)
+#elif defined(__DSP_CODEBASE_MT6297P__)
+ CSIF_ENUM_S2C_HW_N0,
+ CSIF_ENUM_S2C_HW_N1,
+ CSIF_ENUM_S2C_HW_N2,
+ CSIF_ENUM_S2C_HW_N3,
+ CSIF_ENUM_S2C_HW_N4,
+ CSIF_ENUM_S2C_HW_N5,
+ CSIF_ENUM_S2C_HW_N6,
+ CSIF_ENUM_S2C_HW_N7,
+#else
+ #error "Not support this generation !!!!"
+#endif
+ CSIF_ENUM_ALL_S2C_HW_INT_NUM
+}CSIF_S2C_HWIRQ_INDEX;
+
+/*******************************************************************************
+ * Mailbox Enum
+ *******************************************************************************/
+/* MAILBOX HW INDEX */
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID) CSIF_MAILBOX_##HW_ID,
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_MAILBOX_HW_Index_Enum{
+ #include "mt6297/csif_mailbox_config.h"
+ CSIF_MAILBOX_HW_TOTAL_NUMBER
+}CSIF_MAILBOX_HW_INDEX;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_MAILBOX_HW_Index_Enum{
+ #include "mt6297p/csif_mailbox_config.h"
+ CSIF_MAILBOX_HW_TOTAL_NUMBER
+}CSIF_MAILBOX_HW_INDEX;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* MAILBOX Total num */
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_ID_##Code,
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_ID_##Code,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_MAILBOX_TOTAL_Index_Enum{
+ #include "mt6297/csif_mailbox_config.h"
+ CSIF_MAILBOX_SW_TOTAL_NUMBER
+}CSIF_MAILBOX_TOTAL_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_MAILBOX_TOTAL_Index_Enum{
+ #include "mt6297p/csif_mailbox_config.h"
+ CSIF_MAILBOX_SW_TOTAL_NUMBER
+}CSIF_MAILBOX_TOTAL_ENUM_T;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_MAILBOX_C2S_INFO
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_C2S_ID_##Code,
+#undef M_CSIF_MAILBOX_S2C_INFO
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_MAILBOX_TOTAL_C2S_NUM_Enum{
+ #include "mt6297/csif_mailbox_config.h"
+ CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER
+}CSIF_MAILBOX_TOTAL_C2S_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_MAILBOX_TOTAL_C2S_NUM_Enum{
+ #include "mt6297p/csif_mailbox_config.h"
+ CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER
+}CSIF_MAILBOX_TOTAL_C2S_ENUM_T;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_MAILBOX_C2S_INFO
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#undef M_CSIF_MAILBOX_S2C_INFO
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_S2C_ID_##Code,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_MAILBOX_TOTAL_S2C_NUM_Enum{
+ #include "mt6297/csif_mailbox_config.h"
+ CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER
+}CSIF_MAILBOX_TOTAL_S2C_ENUM_T;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_MAILBOX_TOTAL_S2C_NUM_Enum{
+ #include "mt6297p/csif_mailbox_config.h"
+ CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER
+}CSIF_MAILBOX_TOTAL_S2C_ENUM_T;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#if defined(__MSONIC__)
+KAL_CASSERT((CSIF_MAILBOX_SW_TOTAL_NUMBER <= CSIF_MAILBOX_HW_TOTAL_NUMBER));
+#endif
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* C2S MAILBOX Index*/
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_C2S_##Code=CSIF_MAILBOX_##HW_ID,
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_MAILBOX_C2S_Index_Enum{
+ #include "mt6297/csif_mailbox_config.h"
+ CSIF_MAILBOX_C2S_LAST_ID
+}CSIF_MAILBOX_C2S_INDEX;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_MAILBOX_C2S_Index_Enum{
+ #include "mt6297p/csif_mailbox_config.h"
+ CSIF_MAILBOX_C2S_LAST_ID
+}CSIF_MAILBOX_C2S_INDEX;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* S2C MAILBOX Index*/
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_S2C_##Code=CSIF_MAILBOX_##HW_ID,
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CSIF_MAILBOX_S2C_Index_Enum{
+ #include "mt6297/csif_mailbox_config.h"
+ CSIF_MAILBOX_S2C_LAST_ID
+}CSIF_MAILBOX_S2C_INDEX;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CSIF_MAILBOX_S2C_Index_Enum{
+ #include "mt6297p/csif_mailbox_config.h"
+ CSIF_MAILBOX_S2C_LAST_ID
+}CSIF_MAILBOX_S2C_INDEX;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+
+// Ring buffer index enum
+#if defined(__DSP_CODEBASE_MT6297__)
+// No ring buffer in MT6297
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+#undef M_CSIF_RING_BUFFER_INFO
+
+#define M_CSIF_RING_BUFFER_INFO(Code, ID) CSIF_RING_BUFFER_IDX_##Code,
+
+typedef enum CSIF_RING_BUFFER_Index_Enum{
+ #include "mt6297p/csif_ring_buffer_index.h"
+ CSIF_RING_BUFFER_INDEX_TOTAL_NUMBER
+}CSIF_RING_BUFFER_INDEX_ENUM;
+
+#undef M_CSIF_RING_BUFFER_INFO
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+#if defined(__DSP_CODEBASE_MT6297__)
+#define CSIF_C2S_N0_TOTAL_NUMBER (CSIF_C2S_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N1_TOTAL_NUMBER (CSIF_C2S_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N2_TOTAL_NUMBER (CSIF_C2S_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N3_TOTAL_NUMBER (CSIF_C2S_N3_TOTAL_NUMBER_ENUM)
+#elif defined(__DSP_CODEBASE_MT6297P__)
+#define CSIF_C2S_N0_TOTAL_NUMBER (CSIF_C2S_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N1_TOTAL_NUMBER (CSIF_C2S_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N2_TOTAL_NUMBER (CSIF_C2S_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N3_TOTAL_NUMBER (CSIF_C2S_N3_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N4_TOTAL_NUMBER (CSIF_C2S_N4_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N5_TOTAL_NUMBER (CSIF_C2S_N5_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N6_TOTAL_NUMBER (CSIF_C2S_N6_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N7_TOTAL_NUMBER (CSIF_C2S_N7_TOTAL_NUMBER_ENUM)
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#if defined(__DSP_CODEBASE_MT6297__)
+#define CSIF_S2C_N0_TOTAL_NUMBER (CSIF_S2C_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N1_TOTAL_NUMBER (CSIF_S2C_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N2_TOTAL_NUMBER (CSIF_S2C_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N3_TOTAL_NUMBER (CSIF_S2C_N3_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N4_TOTAL_NUMBER (CSIF_S2C_N4_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N5_TOTAL_NUMBER (CSIF_S2C_N5_TOTAL_NUMBER_ENUM)
+#elif defined(__DSP_CODEBASE_MT6297P__)
+#define CSIF_S2C_N0_TOTAL_NUMBER (CSIF_S2C_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N1_TOTAL_NUMBER (CSIF_S2C_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N2_TOTAL_NUMBER (CSIF_S2C_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N3_TOTAL_NUMBER (CSIF_S2C_N3_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N4_TOTAL_NUMBER (CSIF_S2C_N4_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N5_TOTAL_NUMBER (CSIF_S2C_N5_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N6_TOTAL_NUMBER (CSIF_S2C_N6_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N7_TOTAL_NUMBER (CSIF_S2C_N7_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N8_TOTAL_NUMBER (CSIF_S2C_N8_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N9_TOTAL_NUMBER (CSIF_S2C_N9_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N10_TOTAL_NUMBER (CSIF_S2C_N10_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N11_TOTAL_NUMBER (CSIF_S2C_N11_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N12_TOTAL_NUMBER (CSIF_S2C_N12_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N13_TOTAL_NUMBER (CSIF_S2C_N13_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N14_TOTAL_NUMBER (CSIF_S2C_N14_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N15_TOTAL_NUMBER (CSIF_S2C_N15_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N16_TOTAL_NUMBER (CSIF_S2C_N16_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N17_TOTAL_NUMBER (CSIF_S2C_N17_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N18_TOTAL_NUMBER (CSIF_S2C_N18_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N19_TOTAL_NUMBER (CSIF_S2C_N19_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N20_TOTAL_NUMBER (CSIF_S2C_N20_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N21_TOTAL_NUMBER (CSIF_S2C_N21_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N22_TOTAL_NUMBER (CSIF_S2C_N22_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N23_TOTAL_NUMBER (CSIF_S2C_N23_TOTAL_NUMBER_ENUM)
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+#define CSIF_MAILBOX_TOTAL_NUM (CSIF_MAILBOX_SW_TOTAL_NUMBER)
+#define CSIF_MAILBOX_C2S_NUM (CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER)
+#define CSIF_MAILBOX_S2C_NUM (CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER)
diff --git a/common/interface/driver/sys_drv/csif/csif_zi_register.h b/common/interface/driver/sys_drv/csif/csif_zi_register.h
new file mode 100644
index 0000000..311284f
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/csif_zi_register.h
@@ -0,0 +1,53 @@
+/**
+ * @brief register csif zi region
+ * Users could register zi region for each mode with the following format
+ * inner_brp_csif_zi_init_table_MODE(start_addr, byte_size)
+ *
+ * csif memory region from start_addr to start_addr+size-1 will be ZI init
+ * where
+ * MODE is boot_up / abort / wake_up
+ * start_addr and size should be 4-bye alignment
+ *
+ * boot_up - first boot-up and sleep resume
+ * inner_csif_zi_init_table_boot_up(addr, byte_size)
+ *
+ * abort - sleep/dormant abort
+ * inner_csif_zi_init_table_abort(addr, byte_size)
+ *
+ * wake_up - dormant wake-up
+ * inner_csif_zi_init_table_wake_up(addr, byte_size)
+ *
+ * ddl - dynamic download finish
+ * inner_csif_zi_init_table_ddl(addr, byte_size)
+ *
+ * Please do NOT add `;` in the line end, it would cause compile error
+ *
+ * MODULE_csif_zi_init_table_MODE(start_addr, byte_size); // Error!!!
+ *
+ *
+ **/
+
+#if !defined(__MSONIC_BASIC_LOAD__)
+/*
+Register ZI region here for default load
+*/
+//inner_brp_csif_zi_init_table_boot_up(SS_DEFAULT_DUMMY_ARR, sizeof(SS_DEFAULT_ARRAY))
+/*
+example:
+
+inner_csif_zi_init_table_boot_up(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+inner_csif_zi_init_table_abort(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+inner_csif_zi_init_table_wake_up(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+inner_csif_zi_init_table_ddl(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+*/
+#elif defined(__CSIF_DRV_TEST__)
+
+inner_brp_csif_zi_init_table_boot_up(CSIF_MEMORY_BASE, 8)
+inner_brp_csif_zi_init_table_boot_up(CSIF_MEMORY_BASE+9, 14)
+inner_brp_csif_zi_init_table_boot_up(CSIF_MEMORY_BASE+26, 7)
+inner_brp_csif_zi_init_table_boot_up(CSIF_MEMORY_BASE+34, 1)
+inner_brp_csif_zi_init_table_boot_up(CSIF_MEMORY_BASE+39, 3)
+//defined(__SS_BASIC_LOAD__), zi nothing
+#else
+
+#endif
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n0.h b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n0.h
new file mode 100644
index 0000000..8795917
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n0.h
@@ -0,0 +1,40 @@
+// C2S_IRQ_n0
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( NL1_SLM_CTRL_MAILBOX_Lisr_Rx0_Cmd_Receive , N0_ID0, CSIF_TRUE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID30, CSIF_FALSE, 30)
+#if defined(__SONIC_DYNAMIC_PMU_ENABLE__)
+M_CSIF_C2S_INFO( LISR_pmu_dynamic_control_counter, SS_SONIC_PMU_DYNAMIC_CONTROL_COUNTER_ID, CSIF_TRUE, 31)
+#else
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID31, CSIF_FALSE, 31)
+#endif
+
+
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n1.h b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n1.h
new file mode 100644
index 0000000..8cfdcbc
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n1.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n1
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( NL1_SLM_CTRL_MAILBOX_Lisr_Tx_Cmd_Receive , N1_ID0, CSIF_TRUE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n2.h b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n2.h
new file mode 100644
index 0000000..7ea05a2
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n2.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n2
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n3.h b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n3.h
new file mode 100644
index 0000000..c9ca3fb
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_c2s_isr_config_n3.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n3
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( ulsp_ut_handler , N3_ID31, CSIF_TRUE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_dsp_err_isr_config.h b/common/interface/driver/sys_drv/csif/mt6297/csif_dsp_err_isr_config.h
new file mode 100644
index 0000000..bff2597
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_dsp_err_isr_config.h
@@ -0,0 +1,28 @@
+ //CSIF err handler code
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ0_OVFL, 0)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ1_OVFL, 1)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ2_OVFL, 2)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ3_OVFL, 3)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ4_OVFL, 4)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ5_OVFL, 5)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ0_OVFL, 6)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ1_OVFL, 7)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ2_OVFL, 8)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ3_OVFL, 9)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_MPU0_ERR, 10)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_MPU1_ERR, 11)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_DSM_W_UNDEF, 12)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_DSM_R_UNDEF, 13)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_DSR_W_UNDEF, 14)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_DSR_R_UNDEF, 15)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_MPU0_CFG_ERR, 16)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , DSP_MPU1_CFG_ERR, 17)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , L1_MPU0_CFG_ERR, 18)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , L1_MPU1_CFG_ERR, 19)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX0_ERR, 20)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX1_ERR, 21)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX2_ERR, 22)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX3_ERR, 23)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX4_ERR, 24)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX5_ERR, 25)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , OLPDET_ERR, 26)
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_l1_err_isr_config.h b/common/interface/driver/sys_drv/csif/mt6297/csif_l1_err_isr_config.h
new file mode 100644
index 0000000..5ca1fee
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_l1_err_isr_config.h
@@ -0,0 +1,28 @@
+ //CSIF err handler code
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ0_OVFL, 0)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ1_OVFL, 1)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ2_OVFL, 2)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ3_OVFL, 3)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ4_OVFL, 4)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ5_OVFL, 5)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ0_OVFL, 6)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ1_OVFL, 7)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ2_OVFL, 8)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ3_OVFL, 9)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_MPU0_ERR, 10)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_MPU1_ERR, 11)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_DSM_W_UNDEF, 12)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_DSM_R_UNDEF, 13)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_DSR_W_UNDEF, 14)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_DSR_R_UNDEF, 15)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , DSP_MPU0_CFG_ERR, 16)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , DSP_MPU1_CFG_ERR, 17)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_MPU0_CFG_ERR, 18)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , L1_MPU1_CFG_ERR, 19)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX0_ERR, 20)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX1_ERR, 21)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX2_ERR, 22)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX3_ERR, 23)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX4_ERR, 24)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX5_ERR, 25)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , OLPDET_ERR, 26)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_mailbox_config.h b/common/interface/driver/sys_drv/csif/mt6297/csif_mailbox_config.h
new file mode 100644
index 0000000..821129f
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_mailbox_config.h
@@ -0,0 +1,27 @@
+//********************Mailbox HW definition ***********************//
+//************* User MUST NOT modify this table *******************//
+// size(entries) HW_ID
+M_CSIF_MAILBOX_HW_INFO(256, HW_ID0)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID1)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID2)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID3)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID4)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID5)
+//************* User MUST NOT modify this table *******************//
+//*****************************************************************//
+
+
+//************* User register mailbox on this table ***************//
+//************* Shoalin -> Mcore mailbox
+// code HW_ID (map to HW Info above)
+M_CSIF_MAILBOX_C2S_INFO(C2S_ID0, HW_ID0)
+M_CSIF_MAILBOX_C2S_INFO(C2S_ID1, HW_ID1)
+// enum will be CSIF_MAILBOX_C2S_$code
+//************* Mcore -> Shaolin mailbox
+// code HW_ID (map to HW Info above)
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID0, HW_ID2)
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID1, HW_ID3)
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID2, HW_ID4)
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID3, HW_ID5)
+// enum will be CSIF_MAILBOX_S2C_$code
+//***********User register mailbox on this table*******************//
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_memory_config.h b/common/interface/driver/sys_drv/csif/mt6297/csif_memory_config.h
new file mode 100644
index 0000000..c336820
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_memory_config.h
@@ -0,0 +1,3 @@
+// user_id mem_start(Byte addr), mem_size(Byte addr)
+M_CSIF_MEMORY_INFO(L1_Shaolin, HW_ID2)
+M_CSIF_MEMORY_INFO(MSP_mcore0, HW_ID3)
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n0.h b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n0.h
new file mode 100644
index 0000000..6ff1030
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n0.h
@@ -0,0 +1,40 @@
+// S2C_IRQ_n0
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( sonic_deactivate_cb_n0 , N0_ID0, CSIF_TRUE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID1, CSIF_FALSE, 1)
+#if defined(__NR_ENABLE__) || defined(__MSONIC__)
+M_CSIF_S2C_INFO( NL1_FWK_LISR_DCI_IRQ_MB2_Entry , N0_ID2, CSIF_TRUE, 2)
+#else
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID2, CSIF_FALSE, 2)
+#endif
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n1.h b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n1.h
new file mode 100644
index 0000000..5d37ddd
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n1.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n1
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( upp_handle_tb_cb , UPP_DRV, CSIF_TRUE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID31, CSIF_FALSE, 31)
+
+
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n2.h b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n2.h
new file mode 100644
index 0000000..8c98fd7
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n2.h
@@ -0,0 +1,40 @@
+// S2C_IRQ_n2
+ //CSIF handler code irq_ovfl_allowed
+#if defined(__NR_ENABLE__) || defined(__MSONIC__)
+M_CSIF_S2C_INFO( NL1_FWK_LISR_DCI_IRQ_MB1_Entry , N2_ID0, CSIF_TRUE, 0)
+#else
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID0, CSIF_FALSE, 0)
+#endif
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n3.h b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n3.h
new file mode 100644
index 0000000..7a5d9ba
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n3.h
@@ -0,0 +1,40 @@
+// S2C_IRQ_n3
+ //CSIF handler code irq_ovfl_allowed
+#if defined(__NR_ENABLE__) || defined(__MSONIC__)
+M_CSIF_S2C_INFO( NL1_FWK_LISR_DCI_IRQ_MB1_Entry , N3_ID0, CSIF_TRUE, 0)
+#else
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID0, CSIF_FALSE, 0)
+#endif
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n4.h b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n4.h
new file mode 100644
index 0000000..e9d9f99
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n4.h
@@ -0,0 +1,40 @@
+// S2C_IRQ_N4
+ //CSIF handler code irq_ovfl_allowed
+#if defined(__NR_ENABLE__) || defined(__MSONIC__)
+M_CSIF_S2C_INFO( NL1_FWK_LISR_DCI_IRQ_MB1_Entry , N4_ID0, CSIF_TRUE, 0)
+#else
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID0, CSIF_FALSE, 0)
+#endif
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n5.h b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n5.h
new file mode 100644
index 0000000..4aea503
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297/csif_s2c_isr_config_n5.h
@@ -0,0 +1,40 @@
+// S2C_IRQ_n5
+ //CSIF handler code irq_ovfl_allowed
+#if defined(__NR_ENABLE__) || defined(__MSONIC__)
+M_CSIF_S2C_INFO( NL1_FWK_LISR_DCI_IRQ_MB1_Entry , N5_ID0, CSIF_TRUE, 0)
+#else
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID0, CSIF_FALSE, 0)
+#endif
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n0.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n0.h
new file mode 100644
index 0000000..6919bf0
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n0.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n0
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N0_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n1.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n1.h
new file mode 100644
index 0000000..08d5279
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n1.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n1
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N1_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n2.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n2.h
new file mode 100644
index 0000000..7ea05a2
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n2.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n2
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N2_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n3.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n3.h
new file mode 100644
index 0000000..fb2a676
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n3.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n3
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N3_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n4.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n4.h
new file mode 100644
index 0000000..91a4907
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n4.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n4
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N4_ID31, CSIF_FALSE, 31)
+
+
+
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n5.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n5.h
new file mode 100644
index 0000000..d0566aa
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n5.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n5
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N5_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n6.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n6.h
new file mode 100644
index 0000000..fb03b4c
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n6.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n6
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N6_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n7.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n7.h
new file mode 100644
index 0000000..dabe3e1
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_c2s_isr_config_n7.h
@@ -0,0 +1,37 @@
+// C2S_IRQ_n7
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID0, CSIF_FALSE, 0)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID1, CSIF_FALSE, 1)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID2, CSIF_FALSE, 2)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID3, CSIF_FALSE, 3)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID4, CSIF_FALSE, 4)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID5, CSIF_FALSE, 5)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID6, CSIF_FALSE, 6)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID7, CSIF_FALSE, 7)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID8, CSIF_FALSE, 8)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID9, CSIF_FALSE, 9)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID10, CSIF_FALSE, 10)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID11, CSIF_FALSE, 11)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID12, CSIF_FALSE, 12)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID13, CSIF_FALSE, 13)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID14, CSIF_FALSE, 14)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID15, CSIF_FALSE, 15)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID16, CSIF_FALSE, 16)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID17, CSIF_FALSE, 17)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID18, CSIF_FALSE, 18)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID19, CSIF_FALSE, 19)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID20, CSIF_FALSE, 20)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID21, CSIF_FALSE, 21)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID22, CSIF_FALSE, 22)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID23, CSIF_FALSE, 23)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID24, CSIF_FALSE, 24)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID25, CSIF_FALSE, 25)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID26, CSIF_FALSE, 26)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID27, CSIF_FALSE, 27)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID28, CSIF_FALSE, 28)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID29, CSIF_FALSE, 29)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID30, CSIF_FALSE, 30)
+M_CSIF_C2S_INFO( CSIF_Invalid , N7_ID31, CSIF_FALSE, 31)
+
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_dsp_err_isr_config.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_dsp_err_isr_config.h
new file mode 100644
index 0000000..e0ea738
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_dsp_err_isr_config.h
@@ -0,0 +1,39 @@
+ //CSIF err handler code
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ0_OVFL, 0)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ1_OVFL, 1)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ2_OVFL, 2)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ3_OVFL, 3)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ4_OVFL, 4)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ5_OVFL, 5)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ6_OVFL, 6)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ7_OVFL, 7)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ8_OVFL, 8)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ9_OVFL, 9)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ10_OVFL, 10)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ11_OVFL, 11)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ12_OVFL, 12)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ13_OVFL, 13)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ14_OVFL, 14)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , S2C_IRQ15_OVFL, 15)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ0_OVFL, 16)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ1_OVFL, 17)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ2_OVFL, 18)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ3_OVFL, 19)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ4_OVFL, 20)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ5_OVFL, 21)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ6_OVFL, 22)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , C2S_IRQ7_OVFL, 23)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX0_ERR, 24)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX1_ERR, 25)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX2_ERR, 26)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX3_ERR, 27)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX4_ERR, 28)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX5_ERR, 29)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX6_ERR, 30)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX7_ERR, 31)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX8_ERR, 32)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX9_ERR, 33)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX10_ERR, 34)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX11_ERR, 35)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , MAILBOX12_ERR, 36)
+M_CSIF_DSP_ERR_INFO( CSIF_Invalid , OLPDET_ERR, 37)
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_l1_err_isr_config.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_l1_err_isr_config.h
new file mode 100644
index 0000000..fb214a2
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_l1_err_isr_config.h
@@ -0,0 +1,39 @@
+ //CSIF err handler code
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ0_OVFL, 0)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ1_OVFL, 1)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ2_OVFL, 2)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ3_OVFL, 3)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ4_OVFL, 4)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ5_OVFL, 5)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ6_OVFL, 6)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ7_OVFL, 7)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ8_OVFL, 8)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ9_OVFL, 9)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ10_OVFL, 10)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ11_OVFL, 11)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ12_OVFL, 12)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ13_OVFL, 13)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ14_OVFL, 14)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , S2C_IRQ15_OVFL, 15)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ0_OVFL, 16)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ1_OVFL, 17)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ2_OVFL, 18)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ3_OVFL, 19)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ4_OVFL, 20)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ5_OVFL, 21)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ6_OVFL, 22)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , C2S_IRQ7_OVFL, 23)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX0_ERR, 24)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX1_ERR, 25)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX2_ERR, 26)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX3_ERR, 27)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX4_ERR, 28)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX5_ERR, 29)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX6_ERR, 30)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX7_ERR, 31)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX8_ERR, 32)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX9_ERR, 33)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX10_ERR, 34)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX11_ERR, 35)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , MAILBOX12_ERR, 36)
+M_CSIF_L1_ERR_INFO( CSIF_Invalid , OLPDET_ERR, 37)
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_mailbox_config.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_mailbox_config.h
new file mode 100644
index 0000000..e6ce3ab
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_mailbox_config.h
@@ -0,0 +1,41 @@
+//********************Mailbox HW definition ***********************//
+//************* User MUST NOT modify this table *******************//
+// size(entries) HW_ID
+M_CSIF_MAILBOX_HW_INFO(256, HW_ID0)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID1)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID2)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID3)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID4)
+M_CSIF_MAILBOX_HW_INFO(64, HW_ID5)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID6)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID7)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID8)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID9)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID10)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID11)
+M_CSIF_MAILBOX_HW_INFO(32, HW_ID12)
+//************* User MUST NOT modify this table *******************//
+//*****************************************************************//
+
+
+//************* User register mailbox on this table ***************//
+//************* Shoalin -> Mcore mailbox
+// code HW_ID (map to HW Info above)
+M_CSIF_MAILBOX_C2S_INFO(C2S_ID0, HW_ID0) // 256
+M_CSIF_MAILBOX_C2S_INFO(C2S_ID1, HW_ID1) // 64
+M_CSIF_MAILBOX_C2S_INFO(C2S_ID2, HW_ID2) // 64
+M_CSIF_MAILBOX_C2S_INFO(C2S_ID3, HW_ID3) // 64
+// enum will be CSIF_MAILBOX_C2S_$code
+//************* Mcore -> Shaolin mailbox
+// code HW_ID (map to HW Info above)
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID0, HW_ID4) // 64
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID1, HW_ID5) // 64
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID2, HW_ID6) // 32
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID3, HW_ID7) // 32
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID4, HW_ID8) // 32
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID5, HW_ID9) // 32
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID6, HW_ID10) // 32
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID7, HW_ID11) // 32
+M_CSIF_MAILBOX_S2C_INFO(S2C_ID8, HW_ID12) // 32
+// enum will be CSIF_MAILBOX_S2C_$code
+//***********User register mailbox on this table*******************//
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_ring_buffer_index.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_ring_buffer_index.h
new file mode 100644
index 0000000..89b54fe
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_ring_buffer_index.h
@@ -0,0 +1,22 @@
+// RING_BUFFER_INDEX
+ //code
+M_CSIF_RING_BUFFER_INFO( DSP_SINGLE_API_RECORD , 0 )
+M_CSIF_RING_BUFFER_INFO( DSP_MULTIPLE_API_RECORD , 1 )
+M_CSIF_RING_BUFFER_INFO( DSP_MULTIPLE_API_IDX , 2 )
+M_CSIF_RING_BUFFER_INFO( ID3 , 3 )
+M_CSIF_RING_BUFFER_INFO( ID4 , 4 )
+M_CSIF_RING_BUFFER_INFO( ID5 , 5 )
+M_CSIF_RING_BUFFER_INFO( ID6 , 6 )
+M_CSIF_RING_BUFFER_INFO( ID7 , 7 )
+M_CSIF_RING_BUFFER_INFO( ID8 , 8 )
+M_CSIF_RING_BUFFER_INFO( ID9 , 9 )
+M_CSIF_RING_BUFFER_INFO( ID10 , 10)
+M_CSIF_RING_BUFFER_INFO( ID11 , 11)
+M_CSIF_RING_BUFFER_INFO( ID12 , 12)
+M_CSIF_RING_BUFFER_INFO( ID13 , 13)
+M_CSIF_RING_BUFFER_INFO( ID14 , 14)
+M_CSIF_RING_BUFFER_INFO( ID15 , 15)
+M_CSIF_RING_BUFFER_INFO( ID16 , 16)
+M_CSIF_RING_BUFFER_INFO( ID17 , 17)
+M_CSIF_RING_BUFFER_INFO( ID18 , 18)
+M_CSIF_RING_BUFFER_INFO( ID19 , 19)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n16.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n16.h
new file mode 100644
index 0000000..7cec231
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n16.h
@@ -0,0 +1,3 @@
+// S2C_HW_IRQ_n16
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N16_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n17.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n17.h
new file mode 100644
index 0000000..54c4bbb
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n17.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_n17
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N17_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n18.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n18.h
new file mode 100644
index 0000000..6b15a64
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n18.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_n18
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N18_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n19.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n19.h
new file mode 100644
index 0000000..40594ba
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n19.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_n19
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N19_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n20.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n20.h
new file mode 100644
index 0000000..1be665b
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n20.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_N20
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N20_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n21.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n21.h
new file mode 100644
index 0000000..efcb4ac
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n21.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_n21
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N21_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n22.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n22.h
new file mode 100644
index 0000000..ec800b6
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n22.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_n22
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N22_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n23.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n23.h
new file mode 100644
index 0000000..b190d99
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_hw_isr_config_n23.h
@@ -0,0 +1,3 @@
+// S2C_HWIRQ_n23
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N23_ID0, CSIF_FALSE, 0)
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n0.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n0.h
new file mode 100644
index 0000000..5b80e5c
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n0.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n0
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N0_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n1.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n1.h
new file mode 100644
index 0000000..8c15da2
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n1.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n1
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N1_ID31, CSIF_FALSE, 31)
+
+
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n10.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n10.h
new file mode 100644
index 0000000..469b95f
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n10.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_N10
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N10_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n11.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n11.h
new file mode 100644
index 0000000..679af16
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n11.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n11
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N11_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n12.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n12.h
new file mode 100644
index 0000000..81c88a8
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n12.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n12
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N12_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n13.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n13.h
new file mode 100644
index 0000000..0485a2f
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n13.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n13
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N13_ID31, CSIF_FALSE, 31)
+
+
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n14.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n14.h
new file mode 100644
index 0000000..cba01d8
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n14.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n14
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N14_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n15.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n15.h
new file mode 100644
index 0000000..fa12ddd
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n15.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n15
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N15_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n2.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n2.h
new file mode 100644
index 0000000..782efee
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n2.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n2
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N2_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n3.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n3.h
new file mode 100644
index 0000000..6848bba
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n3.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n3
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N3_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n4.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n4.h
new file mode 100644
index 0000000..346d023
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n4.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_N4
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N4_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n5.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n5.h
new file mode 100644
index 0000000..5a826c0
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n5.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n5
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N5_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n6.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n6.h
new file mode 100644
index 0000000..e7dafd3
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n6.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n6
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N6_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n7.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n7.h
new file mode 100644
index 0000000..b058c59
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n7.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n7
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N7_ID31, CSIF_FALSE, 31)
+
+
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n8.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n8.h
new file mode 100644
index 0000000..575aab8
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n8.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n8
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N8_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n9.h b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n9.h
new file mode 100644
index 0000000..fbc1360
--- /dev/null
+++ b/common/interface/driver/sys_drv/csif/mt6297p/csif_s2c_isr_config_n9.h
@@ -0,0 +1,36 @@
+// S2C_IRQ_n9
+ //CSIF handler code irq_ovfl_allowed
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID0, CSIF_FALSE, 0)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID1, CSIF_FALSE, 1)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID2, CSIF_FALSE, 2)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID3, CSIF_FALSE, 3)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID4, CSIF_FALSE, 4)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID5, CSIF_FALSE, 5)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID6, CSIF_FALSE, 6)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID7, CSIF_FALSE, 7)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID8, CSIF_FALSE, 8)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID9, CSIF_FALSE, 9)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID10, CSIF_FALSE, 10)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID11, CSIF_FALSE, 11)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID12, CSIF_FALSE, 12)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID13, CSIF_FALSE, 13)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID14, CSIF_FALSE, 14)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID15, CSIF_FALSE, 15)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID16, CSIF_FALSE, 16)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID17, CSIF_FALSE, 17)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID18, CSIF_FALSE, 18)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID19, CSIF_FALSE, 19)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID20, CSIF_FALSE, 20)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID21, CSIF_FALSE, 21)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID22, CSIF_FALSE, 22)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID23, CSIF_FALSE, 23)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID24, CSIF_FALSE, 24)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID25, CSIF_FALSE, 25)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID26, CSIF_FALSE, 26)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID27, CSIF_FALSE, 27)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID28, CSIF_FALSE, 28)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID29, CSIF_FALSE, 29)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID30, CSIF_FALSE, 30)
+M_CSIF_S2C_INFO( CSIF_Invalid , N9_ID31, CSIF_FALSE, 31)
+
+
\ No newline at end of file
diff --git a/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_brp.h b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_brp.h
new file mode 100644
index 0000000..b4b6bdd
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_brp.h
@@ -0,0 +1,142 @@
+// 0
+// HBRP IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP0_HSPA_SERV_SCCH)
+irq_entry_function(top_c2m_isr_serv_scch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// HBRP IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP1_HSPA_AGCH)
+irq_entry_function(top_c2m_isr_agch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// HBRP IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP2_HSPA_NC_SCCH)
+irq_entry_function(top_c2m_isr_nc_scch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// HBRP IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// HBRP IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_SS_TRIGGER_DDL)
+irq_entry_function(ddl_brp_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_T2F_CMD)
+irq_entry_function(LISR_BRP_lte_pos_td2fd_cmd)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_ABORT)
+irq_entry_function(LISR_lte_pos_abort)
+irq_auto_eoi(CUIF_TRUE)
+
+
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_CELL0_CMD)
+irq_entry_function(LISR_BRP_lte_pos_cell0)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_CELL1_CMD)
+irq_entry_function(LISR_BRP_lte_pos_cell1)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+#if defined(__USIP_DYNAMIC_PMU_ENABLE__)
+irq_index(CUIF_C2U_BRP_PMU_DYNAMIC_MODIFY)
+irq_entry_function(PMU_Dynamic_Modify_Callback_BRP)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_BRP_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+#if defined(__MD95__)
+/*
+ Register an IRQ for ST team to pass filter write flag,
+ this IRQ should be masked in uSIP init flow,
+ uSIP only query IRQ status not serve it.
+*/
+irq_index(CUIF_C2U_BRP_LOG_FILTER_WRITE_FLAG)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_BRP_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_fec_wbrp.h b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_fec_wbrp.h
new file mode 100644
index 0000000..575b285
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_fec_wbrp.h
@@ -0,0 +1,310 @@
+// 0
+// FEC IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC0)
+irq_entry_function(FEC_TPC_C2U_CB_CAL_DL_P0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FEC IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC1)
+irq_entry_function(FEC_TPC_C2U_CB_CAL_DL_P1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(__DSP_CODEBASE_MT6295__)
+// 2
+// FEC IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC2)
+irq_entry_function(FEC_TPC_C2U_CB_TX_INIT_P0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FEC IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC3)
+irq_entry_function(FEC_TPC_C2U_CB_TX_INIT_P1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#elif defined(__DSP_CODEBASE_MT6293__)
+// 2
+// FEC IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC2)
+irq_entry_function(FEC_TPC_C2U_CB_TX_INIT_END_P0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FEC IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC3)
+irq_entry_function(FEC_TPC_C2U_CB_TX_INIT_END_P1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+// 4
+// FEC IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC4)
+irq_entry_function(FEC_WTX_C2U_IRQ_DL_EMI)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FEC IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(__DSP_CODEBASE_MT6295__)
+// 6
+// FEC IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC6)
+irq_entry_function(FEC_TPC_C2U_CB_TX_END_P0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FEC IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC7)
+irq_entry_function(FEC_TPC_C2U_CB_TX_END_P1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(__DSP_CODEBASE_MT6293__)
+// 6
+// FEC IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FEC IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+// 8
+// FEC IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FEC IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_C2K0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// C2K IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_C2K1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// C2K IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_C2K2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_C2K3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// WBRP IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP0_INI_TICK)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// WBRP IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP1_CC0_STATIC_CFG_OK)
+irq_entry_function(isr_s2f_cc0_static_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// WBRP IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP2_CC1_STATIC_CFG_OK)
+irq_entry_function(isr_s2f_cc1_static_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// WBRP IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP3_BCHSFN_STATIC_CFG_OK)
+irq_entry_function(isr_s2f_bchsfn_static_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// WBRP IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP4_CC0_CFG_OK)
+irq_entry_function(isr_s2f_cc0_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// WBRP IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP5_CC1_CFG_OK)
+irq_entry_function(isr_s2f_cc1_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// WBRP IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP6_CC0_GUIDED_CFG_OK)
+irq_entry_function(isr_s2f_cc0_guided_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// WBRP IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP7_CC1_GUIDED_CFG_OK)
+irq_entry_function(isr_s2f_cc1_guided_cfg_ok_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// WBRP IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP8_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// WBRP IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP9_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// WBRP IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_WBRP10_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_TX_SS_TRIGGER_DDL)
+irq_entry_function(ddl_fec_tx_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+// RESERVE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RX_SS_TRIGGER_DDL)
+irq_entry_function(ddl_fec_rx_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+// RESERVE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+#if defined(__USIP_DYNAMIC_PMU_ENABLE__)
+irq_index(CUIF_C2U_FEC_WBRP_PMU_DYNAMIC_MODIFY)
+irq_entry_function(PMU_Dynamic_Modify_Callback_FEC)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_FEC_WBRP_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 30
+// RESERVE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+// RESERVE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+#if defined(__MD95__)
+/*
+ Register an IRQ for ST team to pass filter write flag,
+ this IRQ should be masked in uSIP init flow,
+ uSIP only query IRQ status not serve it.
+*/
+irq_index(CUIF_C2U_FEC_WBRP_LOG_FILTER_WRITE_FLAG)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_FEC_WBRP_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_inner.h b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_inner.h
new file mode 100644
index 0000000..bb4ffea
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_inner.h
@@ -0,0 +1,222 @@
+/* inner callback */
+// 0
+// INNER IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// INNER IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 2
+// INNER IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 3
+// INNER IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 4
+// INNER IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 5
+// INNER IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// INNER IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER6)
+irq_entry_function(LISR_lte_inner_termination_tick)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// INNER IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// INNER IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER8_C2K_SCHD)
+irq_entry_function(LISR_c2k_c2uirq)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// INNER IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// INNER IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER10_TDSCDMA_SCHD)
+irq_entry_function(LISR_tdscdma_c2uirq)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// INNER IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER11_TDSCDMA_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// INNER IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER12_WCDMA_INIT_TICK)
+irq_entry_function(C2U_IRQ_wcdma_init_tick)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// INNER IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_SS_TRIGGER_DDL_OR_GDMA_DONE)
+irq_entry_function(ddl_inner_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_CANT_DO_LTE)
+irq_entry_function(inner_can_not_do_lte)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_CAN_DO_LTE)
+irq_entry_function(inner_can_do_lte)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+#if defined(__USIP_DYNAMIC_PMU_ENABLE__)
+irq_index(CUIF_C2U_INNER_PMU_DYNAMIC_MODIFY)
+irq_entry_function(PMU_Dynamic_Modify_Callback_INNER)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_INNER_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+#if defined(__MD95__)
+/*
+ Register an IRQ for ST team to pass filter write flag,
+ this IRQ should be masked in uSIP init flow,
+ uSIP only query IRQ status not serve it.
+*/
+irq_index(CUIF_C2U_INNER_LOG_FILTER_WRITE_FLAG)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_INNER_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_speech.h b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_speech.h
new file mode 100644
index 0000000..6151e2e
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_speech.h
@@ -0,0 +1,97 @@
+// 0
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SRST)
+irq_entry_function(SPH_SRstLisrHdlr)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SEND)
+irq_entry_function(SPH_SEndLisrHdlr)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_FSM_SEND)
+irq_entry_function(SPH_SOffLisrHdlr)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SS_2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// RESERVE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+#if defined(__USIP_DYNAMIC_PMU_ENABLE__)
+irq_index(CUIF_C2U_SPEECH_PMU_DYNAMIC_MODIFY)
+irq_entry_function(PMU_Dynamic_Modify_Callback_SPEECH)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_SPEECH_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 7
+// RESERVE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// RESERVE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// RESERVE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+#if defined(__MD95__)
+/*
+ Register an IRQ for ST team to pass filter write flag,
+ this IRQ should be masked in uSIP init flow,
+ uSIP only query IRQ status not serve it.
+*/
+irq_index(CUIF_C2U_SPEECH_LOG_FILTER_WRITE_FLAG)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#else
+irq_index(CUIF_C2U_SPEECH_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/cuif_common_def.h b/common/interface/driver/sys_drv/cuif/cuif_common_def.h
new file mode 100644
index 0000000..a4178b2
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/cuif_common_def.h
@@ -0,0 +1,479 @@
+/*******************************************
+* please DO NOT include this file
+* this file is for mcu/dsp cuif driver include only
+************************************************/
+
+/*******************************************************************************
+ * Enums
+ *******************************************************************************/
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(index) index,
+#define irq_name(name)
+#define irq_entry_function(fun)
+#define irq_auto_eoi(eoi)
+
+/* U2C */
+
+#if defined(__DSP_CODEBASE_MT6293__)
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N0_Enum{
+ #include "mt6293/cuif_u2c_isr_config_n0.h"
+ CUIF_U2C_N0_TOTAL_NUMBER
+}CUIF_U2C_N0_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N1_Enum{
+ #include "mt6293/cuif_u2c_isr_config_n1.h"
+ CUIF_U2C_N1_TOTAL_NUMBER
+}CUIF_U2C_N1_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N2_Enum{
+ #include "mt6293/cuif_u2c_isr_config_n2.h"
+ CUIF_U2C_N2_TOTAL_NUMBER
+}CUIF_U2C_N2_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N3_Enum{
+ #include "mt6293/cuif_u2c_isr_config_n3.h"
+ CUIF_U2C_N3_TOTAL_NUMBER
+}CUIF_U2C_N3_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N4_Enum{
+ #include "mt6293/cuif_u2c_isr_config_n4.h"
+ CUIF_U2C_N4_TOTAL_NUMBER
+}CUIF_U2C_N4_Code_t;
+
+#elif defined(__DSP_CODEBASE_MT6295__)
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N0_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n0.h"
+ CUIF_U2C_N0_TOTAL_NUMBER
+}CUIF_U2C_N0_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N1_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n1.h"
+ CUIF_U2C_N1_TOTAL_NUMBER
+}CUIF_U2C_N1_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N2_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n2.h"
+ CUIF_U2C_N2_TOTAL_NUMBER
+}CUIF_U2C_N2_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N3_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n3.h"
+ CUIF_U2C_N3_TOTAL_NUMBER
+}CUIF_U2C_N3_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N4_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n4.h"
+ CUIF_U2C_N4_TOTAL_NUMBER
+}CUIF_U2C_N4_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N5_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n5.h"
+ CUIF_U2C_N5_TOTAL_NUMBER
+}CUIF_U2C_N5_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N6_Enum{
+ #include "mt6295/cuif_u2c_isr_config_n6.h"
+ CUIF_U2C_N6_TOTAL_NUMBER
+}CUIF_U2C_N6_Code_t;
+
+#elif defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N0_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n0.h"
+ CUIF_U2C_N0_TOTAL_NUMBER
+}CUIF_U2C_N0_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N1_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n1.h"
+ CUIF_U2C_N1_TOTAL_NUMBER
+}CUIF_U2C_N1_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N2_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n2.h"
+ CUIF_U2C_N2_TOTAL_NUMBER
+}CUIF_U2C_N2_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N3_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n3.h"
+ CUIF_U2C_N3_TOTAL_NUMBER
+}CUIF_U2C_N3_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N4_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n4.h"
+ CUIF_U2C_N4_TOTAL_NUMBER
+}CUIF_U2C_N4_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N5_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n5.h"
+ CUIF_U2C_N5_TOTAL_NUMBER
+}CUIF_U2C_N5_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N6_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n6.h"
+ CUIF_U2C_N6_TOTAL_NUMBER
+}CUIF_U2C_N6_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N7_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n7.h"
+ CUIF_U2C_N7_TOTAL_NUMBER
+}CUIF_U2C_N7_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N8_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n8.h"
+ CUIF_U2C_N8_TOTAL_NUMBER
+}CUIF_U2C_N8_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N9_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n9.h"
+ CUIF_U2C_N9_TOTAL_NUMBER
+}CUIF_U2C_N9_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N10_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n10.h"
+ CUIF_U2C_N10_TOTAL_NUMBER
+}CUIF_U2C_N10_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N11_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n11.h"
+ CUIF_U2C_N11_TOTAL_NUMBER
+}CUIF_U2C_N11_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N12_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n12.h"
+ CUIF_U2C_N12_TOTAL_NUMBER
+}CUIF_U2C_N12_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N13_Enum{
+ #include "mt6297/cuif_u2c_isr_config_n13.h"
+ CUIF_U2C_N13_TOTAL_NUMBER
+}CUIF_U2C_N13_Code_t;
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N0_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n0.h"
+ CUIF_U2C_N0_TOTAL_NUMBER
+}CUIF_U2C_N0_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N1_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n1.h"
+ CUIF_U2C_N1_TOTAL_NUMBER
+}CUIF_U2C_N1_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N2_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n2.h"
+ CUIF_U2C_N2_TOTAL_NUMBER
+}CUIF_U2C_N2_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N3_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n3.h"
+ CUIF_U2C_N3_TOTAL_NUMBER
+}CUIF_U2C_N3_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N4_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n4.h"
+ CUIF_U2C_N4_TOTAL_NUMBER
+}CUIF_U2C_N4_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N5_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n5.h"
+ CUIF_U2C_N5_TOTAL_NUMBER
+}CUIF_U2C_N5_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N6_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n6.h"
+ CUIF_U2C_N6_TOTAL_NUMBER
+}CUIF_U2C_N6_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N7_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n7.h"
+ CUIF_U2C_N7_TOTAL_NUMBER
+}CUIF_U2C_N7_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N8_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n8.h"
+ CUIF_U2C_N8_TOTAL_NUMBER
+}CUIF_U2C_N8_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N9_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n9.h"
+ CUIF_U2C_N9_TOTAL_NUMBER
+}CUIF_U2C_N9_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N10_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n10.h"
+ CUIF_U2C_N10_TOTAL_NUMBER
+}CUIF_U2C_N10_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N11_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n11.h"
+ CUIF_U2C_N11_TOTAL_NUMBER
+}CUIF_U2C_N11_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N12_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n12.h"
+ CUIF_U2C_N12_TOTAL_NUMBER
+}CUIF_U2C_N12_Code_t;
+
+typedef enum CUIF_U2C_InterruptHandlerCode_N13_Enum{
+ #include "mt6297p/cuif_u2c_isr_config_n13.h"
+ CUIF_U2C_N13_TOTAL_NUMBER
+}CUIF_U2C_N13_Code_t;
+
+#else
+
+#error "Not support this generation !!!!"
+
+#endif
+
+/* C2U */
+#if defined(__DSP_CODEBASE_MT6293__) || defined(__DSP_CODEBASE_MT6295__)
+
+typedef enum CUIF_C2U_InterruptHandlerCode_INNER_Enum{
+ #include "cuif_c2u_isr_config_inner.h"
+ CUIF_C2U_INNER_TOTAL_NUMBER
+}CUIF_C2U_INNER_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_OUTER_Enum{
+ #include "cuif_c2u_isr_config_brp.h"
+ CUIF_C2U_OUTER_TOTAL_NUMBER
+}CUIF_C2U_OUTER_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_FEC_Enum{
+ #include "cuif_c2u_isr_config_fec_wbrp.h"
+ CUIF_C2U_FEC_TOTAL_NUMBER
+}CUIF_C2U_FEC_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_SPEECH_Enum{
+ #include "cuif_c2u_isr_config_speech.h"
+ CUIF_C2U_SPEECH_TOTAL_NUMBER
+}CUIF_C2U_SPEECH_Code_t;
+
+#elif defined(__DSP_CODEBASE_MT6297__) || defined(__DSP_CODEBASE_MT6297P__)
+
+#if defined(__DSP_CODEBASE_MT6297__) && defined(__DSP_RESUME_USIP2_FEATURE__)
+typedef enum CUIF_C2U_InterruptHandlerCode_INNER_DUAL_Enum{
+ #include "mt6297_c2u/cuif_c2u_isr_config_inner_dual.h"
+ CUIF_C2U_INNER_DUAL_TOTAL_NUMBER
+}CUIF_C2U_INNER_DUAL_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_OUTER_DUAL_Enum{
+ #include "mt6297_c2u/cuif_c2u_isr_config_brp_dual.h"
+ CUIF_C2U_OUTER_DUAL_TOTAL_NUMBER
+}CUIF_C2U_OUTER_DUAL_Code_t;
+#endif
+
+typedef enum CUIF_C2U_InterruptHandlerCode_INNER_Enum{
+ #include "mt6297_c2u/cuif_c2u_isr_config_inner.h"
+ CUIF_C2U_INNER_TOTAL_NUMBER
+}CUIF_C2U_INNER_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_OUTER_Enum{
+ #include "mt6297_c2u/cuif_c2u_isr_config_brp.h"
+ CUIF_C2U_OUTER_TOTAL_NUMBER
+}CUIF_C2U_OUTER_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_FEC_Enum{
+ #include "mt6297_c2u/cuif_c2u_isr_config_fec_wbrp.h"
+ CUIF_C2U_FEC_TOTAL_NUMBER
+}CUIF_C2U_FEC_Code_t;
+
+typedef enum CUIF_C2U_InterruptHandlerCode_SPEECH_Enum{
+ #include "mt6297_c2u/cuif_c2u_isr_config_speech.h"
+ CUIF_C2U_SPEECH_TOTAL_NUMBER
+}CUIF_C2U_SPEECH_Code_t;
+
+#else
+
+#error "Not support this generation !!!!"
+
+#endif
+
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(index)
+#define irq_name(name)
+#define irq_entry_function(func)
+#define irq_auto_eoi(eoi)
+
+/* module enum */
+typedef enum CUIF_Module_Index_Enum{
+#if defined(__DSP_CODEBASE_MT6297__) || defined(__DSP_CODEBASE_MT6297P__)
+ CUIF_ENUM_INNER,
+ CUIF_ENUM_OUTER,
+ #if defined(__DSP_RESUME_USIP2_FEATURE__)
+ CUIF_ENUM_INNER_DUAL,
+ CUIF_ENUM_OUTER_DUAL,
+ #endif
+ CUIF_ENUM_SPEECH,
+ CUIF_ENUM_FEC,
+#else /* __DSP_CODEBASE_MT6297__ */
+ CUIF_ENUM_INNER,
+ CUIF_ENUM_OUTER,
+ CUIF_ENUM_FEC,
+ CUIF_ENUM_SPEECH,
+#endif
+ CUIF_ENUM_ALL_USIP_INT_NUM
+}CUIF_MODULE_INDEX;
+
+/* CUIF MCU Int enum */
+typedef enum CUIF_MCU_Int_Enum{
+ CUIF_ENUM_N0,
+ CUIF_ENUM_N1,
+ CUIF_ENUM_N2,
+ CUIF_ENUM_N3,
+ CUIF_ENUM_N4,
+#if defined(__DSP_CODEBASE_MT6295__)
+ CUIF_ENUM_N5,
+ CUIF_ENUM_N6,
+#elif defined(__DSP_CODEBASE_MT6297__) || defined(__DSP_CODEBASE_MT6297P__)
+ CUIF_ENUM_N5,
+ CUIF_ENUM_N6,
+ CUIF_ENUM_N7,
+ CUIF_ENUM_N8,
+ CUIF_ENUM_N9,
+ CUIF_ENUM_N10,
+ CUIF_ENUM_N11,
+ CUIF_ENUM_N12,
+ CUIF_ENUM_N13,
+#endif
+#if defined(__DSP_CODEBASE_MT6293__) || defined(__DSP_CODEBASE_MT6295__)
+ CUIF_ENUM_WAKEUP,
+#else
+ CUIF_ENUM_WAKEUP_LEGACY_DUMMY,
+#endif
+ CUIF_ENUM_ALL_MCU_INT_NUM
+}CUIF_MCU_INT;
+
+#if defined(__DSP_CODEBASE_MT6297__) || defined(__DSP_CODEBASE_MT6297P__)
+/* CUIF MCU WAKEUP-Int enum */
+typedef enum CUIF_MCU_WAKEUP_Int_Enum{
+ CUIF_ENUM_WAKEUP,
+ CUIF_ENUM_ALL_MCU_WAKEUP_INT_NUM
+}CUIF_MCU_WAKEUP_INT;
+#endif
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+
+#if defined(__DSP_CODEBASE_MT6293__) || defined(__DSP_CODEBASE_MT6295__)
+
+#define CUIF_NUM_INTERRUPT_INNER_SOURCES (25)
+#define CUIF_NUM_INTERRUPT_OUTER_SOURCES (15)
+#define CUIF_NUM_INTERRUPT_FEC_SOURCES (32)
+#define CUIF_NUM_INTERRUPT_SPEECH_SOURCES (10)
+
+#elif defined(__DSP_CODEBASE_MT6297__) || defined(__DSP_CODEBASE_MT6297P__)
+
+#define CUIF_NUM_INTERRUPT_INNER_SOURCES (23)
+#define CUIF_NUM_INTERRUPT_OUTER_SOURCES (21)
+#define CUIF_NUM_INTERRUPT_FEC_SOURCES (17)
+#define CUIF_NUM_INTERRUPT_SPEECH_SOURCES (17)
+/* For suspended uSIP2 usage */
+#if defined(__DSP_RESUME_USIP2_FEATURE__)
+#define CUIF_NUM_INTERRUPT_INNER_DUAL_SOURCES (25)
+#define CUIF_NUM_INTERRUPT_OUTER_DUAL_SOURCES (15)
+#endif
+
+#endif
+
+#if defined(__DSP_CODEBASE_MT6293__)
+
+#define CUIF_MCU_INT_N0_SOURCES (27)
+#define CUIF_MCU_INT_N1_SOURCES (17)
+#define CUIF_MCU_INT_N2_SOURCES (11)
+#define CUIF_MCU_INT_N3_SOURCES (32)
+#define CUIF_MCU_INT_N4_SOURCES (21)
+#define CUIF_MCU_INT_WAKEUP_SOURCES (4)
+
+#elif defined(__DSP_CODEBASE_MT6295__)
+
+#define CUIF_MCU_INT_N0_SOURCES (28)
+#define CUIF_MCU_INT_N1_SOURCES (16)
+#define CUIF_MCU_INT_N2_SOURCES (11)
+#define CUIF_MCU_INT_N3_SOURCES (32)
+#define CUIF_MCU_INT_N4_SOURCES (16)
+#define CUIF_MCU_INT_N5_SOURCES (14)
+#define CUIF_MCU_INT_N6_SOURCES (14)
+#define CUIF_MCU_INT_WAKEUP_SOURCES (6)
+
+#elif defined(__DSP_CODEBASE_MT6297__)
+
+#if defined(MT6297) //APOLLO
+#define CUIF_MCU_INT_N0_SOURCES (18)
+#define CUIF_MCU_INT_N1_SOURCES (14)
+#define CUIF_MCU_INT_N2_SOURCES (12)
+#define CUIF_MCU_INT_N3_SOURCES (22)
+#define CUIF_MCU_INT_N4_SOURCES (14)
+#define CUIF_MCU_INT_N5_SOURCES (14)
+#define CUIF_MCU_INT_N6_SOURCES (22)
+#define CUIF_MCU_INT_N7_SOURCES (14)
+#define CUIF_MCU_INT_N8_SOURCES (14)
+#define CUIF_MCU_INT_N9_SOURCES (14)
+#define CUIF_MCU_INT_N10_SOURCES (14)
+#define CUIF_MCU_INT_N11_SOURCES (14)
+#define CUIF_MCU_INT_N12_SOURCES (11)
+#define CUIF_MCU_INT_N13_SOURCES (18)
+#define CUIF_MCU_INT_WAKEUP_SOURCES (6)
+#elif defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)||defined(__MD97__) //MT6885
+#define CUIF_MCU_INT_N0_SOURCES (23)
+#define CUIF_MCU_INT_N1_SOURCES (18)
+#define CUIF_MCU_INT_N2_SOURCES (14)
+#define CUIF_MCU_INT_N3_SOURCES (24)
+#define CUIF_MCU_INT_N4_SOURCES (16)
+#define CUIF_MCU_INT_N5_SOURCES (18)
+#define CUIF_MCU_INT_N6_SOURCES (24)
+#define CUIF_MCU_INT_N7_SOURCES (16)
+#define CUIF_MCU_INT_N8_SOURCES (16)
+#define CUIF_MCU_INT_N9_SOURCES (16)
+#define CUIF_MCU_INT_N10_SOURCES (16)
+#define CUIF_MCU_INT_N11_SOURCES (16)
+#define CUIF_MCU_INT_N12_SOURCES (13)
+#define CUIF_MCU_INT_N13_SOURCES (20)
+#define CUIF_MCU_INT_WAKEUP_SOURCES (6)
+#endif
+
+#elif defined(__DSP_CODEBASE_MT6297P__)
+
+#if defined(MERCURY) || defined(CHIPID_MERCURY) //MERCURY
+#define CUIF_MCU_INT_N0_SOURCES (23)
+#define CUIF_MCU_INT_N1_SOURCES (18)
+#define CUIF_MCU_INT_N2_SOURCES (17)
+#define CUIF_MCU_INT_N3_SOURCES (30)
+#define CUIF_MCU_INT_N4_SOURCES (18)
+#define CUIF_MCU_INT_N5_SOURCES (18)
+#define CUIF_MCU_INT_N6_SOURCES (24)
+#define CUIF_MCU_INT_N7_SOURCES (18)
+#define CUIF_MCU_INT_N8_SOURCES (18)
+#define CUIF_MCU_INT_N9_SOURCES (18)
+#define CUIF_MCU_INT_N10_SOURCES (18)
+#define CUIF_MCU_INT_N11_SOURCES (16)
+#define CUIF_MCU_INT_N12_SOURCES (16)
+#define CUIF_MCU_INT_N13_SOURCES (20)
+#define CUIF_MCU_INT_WAKEUP_SOURCES (6)
+#endif
+
+#endif
+
+
+/* get cuif IRQ limit number by module enum*/
+/* e.g. GET_MODULE_IRQ_LIMIT_NUMBER(INNER) => CUIF_NUM_INTERRUPT_INNER_SOURCES */
+#define POSTFIX(mID, pos) mID##pos
+#define PREFIX(mID, pre) POSTFIX(pre##mID, _SOURCES)
+#define GET_MODULE_IRQ_LIMIT_NUMBER(mID) PREFIX(mID, CUIF_NUM_INTERRUPT_)
+
+/* e.g. GET_MCU_INT_IRQ_LIMIT_NUMBER(N0) => CUIF_MCU_INT_N0_SOURCES */
+#define GET_MCU_INT_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CUIF_MCU_INT_)
+
+
diff --git a/common/interface/driver/sys_drv/cuif/cuif_zi_register.h b/common/interface/driver/sys_drv/cuif/cuif_zi_register.h
new file mode 100644
index 0000000..b008aef
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/cuif_zi_register.h
@@ -0,0 +1,225 @@
+/**
+ * @brief register cuif zi region
+ * Users could register zi region for each mode with the following format
+ * inner_cuif_zi_init_table_MODE(start_addr, byte_size)
+ * brp_cuif_zi_init_table_MODE(start_addr, byte_size)
+ * fec_wbrp_cuif_zi_init_table_MODE(start_addr, byte_size)
+ * speech_cuif_zi_init_table_MODE(start_addr, byte_size)
+ *
+ * cuif memory region from start_addr to start_addr+size-1 will be ZI init
+ * where
+ * MODE is boot_up / abort / wake_up
+ * start_addr and size should be 4-bye alignment
+ *
+ * boot_up - first boot-up and sleep resume
+ * inner_cuif_zi_init_table_boot_up(addr, byte_size)
+ * brp_cuif_zi_init_table_boot_up(addr, byte_size)
+ * fec_wbrp_cuif_zi_init_table_boot_up(addr, byte_size)
+ * speech_cuif_zi_init_table_boot_up(addr, byte_size)
+ *
+ * abort - sleep/dormant abort
+ * inner_cuif_zi_init_table_abort(addr, byte_size)
+ * brp_cuif_zi_init_table_abort(addr, byte_size)
+ * fec_wbrp_cuif_zi_init_table_abort(addr, byte_size)
+ * speech_cuif_zi_init_table_abort(addr, byte_size)
+ *
+ * wake_up - dormant wake-up
+ * inner_cuif_zi_init_table_wake_up(addr, byte_size)
+ * brp_cuif_zi_init_table_wake_up(addr, byte_size)
+ * fec_wbrp_cuif_zi_init_table_wake_up(addr, byte_size)
+ * speech_cuif_zi_init_table_wake_up(addr, byte_size)
+ *
+ * ddl - dynamic download finish
+ * inner_cuif_zi_init_table_ddl(addr, byte_size)
+ * brp_cuif_zi_init_table_ddl(addr, byte_size)
+ * fec_wbrp_cuif_zi_init_table_ddl(addr, byte_size)
+ * speech_cuif_zi_init_table_ddl(addr, byte_size)
+ *
+ * Please do NOT add `;` in the line end, it would cause compile error
+ *
+ * MODULE_cuif_zi_init_table_MODE(start_addr, byte_size); // Error!!!
+ *
+ *
+ **/
+#if !defined(__USIP_CUIF_ZI_INIT_TEST__)
+
+#if !defined(__USIP_BASIC_LOAD__)
+/*
+Register ZI region here for default load
+Please contact file owner to chek-in code
+*/
+inner_cuif_zi_init_table_boot_up(CUIF_LTE_ALL_REGS_BASE, sizeof(CUIF_LTE_ALL_REGS))
+
+inner_cuif_zi_init_table_boot_up(CUIF_WCDMA_INNER_ALL_PTR_FOR_ZI, sizeof(CUIF_WCDMA_INNER_ALL_REGS) * INNER_LTE_ALL_CC_NUM)
+
+#if defined(__DSP_CODEBASE_MT6295__) || defined(__DSP_CODEBASE_MT6293__)
+fec_wbrp_cuif_zi_init_table_boot_up(FEC_WBRP_FEC_REGION_BASE, sizeof(CUIF_FEC_region))
+fec_wbrp_cuif_zi_init_table_boot_up(FEC_WBRP_WR99_CUIF, sizeof(WR99_CUIF_REGS))
+#if defined(__DSP_CODEBASE_MT6295__)
+fec_wbrp_cuif_zi_init_table_boot_up(FEC_WBRP_FEC_C_TX_INFO, sizeof(FEC_C_TX_INFO_t))
+fec_wbrp_cuif_zi_init_table_boot_up(FEC_WBRP_FEC_C_RX_INFO, sizeof(FEC_C_RX_INFO_t))
+#endif
+#endif
+
+speech_cuif_zi_init_table_boot_up(SPEECH_CUIF_REGION, sizeof(CUIF_Speech_Region_t))
+
+/*
+example:
+
+inner_cuif_zi_init_table_boot_up(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+inner_cuif_zi_init_table_abort(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+inner_cuif_zi_init_table_wake_up(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+inner_cuif_zi_init_table_ddl(INNER_SS_DBGINFO, sizeof(SS_DBGInfo))
+
+brp_cuif_zi_init_table_boot_up(BRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+brp_cuif_zi_init_table_abort(BRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+brp_cuif_zi_init_table_wake_up(BRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+brp_cuif_zi_init_table_ddl(BRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+
+fec_wbrp_cuif_zi_init_table_boot_up(FEC_WBRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+fec_wbrp_cuif_zi_init_table_abort(FEC_WBRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+fec_wbrp_cuif_zi_init_table_wake_up(FEC_WBRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+fec_wbrp_cuif_zi_init_table_ddl(FEC_WBRP_SS_DBGINFO, sizeof(SS_DBGInfo))
+
+speech_cuif_zi_init_table_boot_up(SPEECH_SS_DBGINFO, sizeof(SS_DBGInfo))
+speech_cuif_zi_init_table_abort(SPEECH_SS_DBGINFO, sizeof(SS_DBGInfo))
+speech_cuif_zi_init_table_wake_up(SPEECH_SS_DBGINFO, sizeof(SS_DBGInfo))
+speech_cuif_zi_init_table_ddl(SPEECH_SS_DBGINFO, sizeof(SS_DBGInfo))
+
+*/
+
+#else
+
+//defined(__USIP_BASIC_LOAD__), zi nothing
+
+#endif
+
+#else
+// defined(__USIP_CUIF_ZI_INIT_TEST__)
+#if 1
+
+inner_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE, 8)
+inner_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+9, 14)
+inner_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+26, 7)
+inner_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+34, 1)
+inner_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+39, 3)
+
+inner_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE, 8)
+inner_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+9, 14)
+inner_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+26, 7)
+inner_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+34, 1)
+inner_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+39, 3)
+
+inner_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE, 8)
+inner_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+9, 14)
+inner_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+26, 7)
+inner_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+34, 1)
+inner_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+39, 3)
+
+brp_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE, 8)
+brp_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+9, 14)
+brp_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+26, 7)
+brp_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+34, 1)
+brp_cuif_zi_init_table_boot_up(CUIF_INNER_BRP_BASE+39, 3)
+
+brp_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE, 8)
+brp_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+9, 14)
+brp_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+26, 7)
+brp_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+34, 1)
+brp_cuif_zi_init_table_abort(CUIF_INNER_BRP_BASE+39, 3)
+
+brp_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE, 8)
+brp_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+9, 14)
+brp_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+26, 7)
+brp_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+34, 1)
+brp_cuif_zi_init_table_wake_up(CUIF_INNER_BRP_BASE+39, 3)
+
+
+#if defined(__DSP_CODEBASE_MT6295__) || defined(__DSP_CODEBASE_MT6293__)
+fec_wbrp_cuif_zi_init_table_boot_up(CUIF_FEC_WBRP_BASE, 8)
+fec_wbrp_cuif_zi_init_table_boot_up(CUIF_FEC_WBRP_BASE+9, 14)
+fec_wbrp_cuif_zi_init_table_boot_up(CUIF_FEC_WBRP_BASE+26, 7)
+fec_wbrp_cuif_zi_init_table_boot_up(CUIF_FEC_WBRP_BASE+34, 1)
+fec_wbrp_cuif_zi_init_table_boot_up(CUIF_FEC_WBRP_BASE+39, 3)
+
+fec_wbrp_cuif_zi_init_table_abort(CUIF_FEC_WBRP_BASE, 8)
+fec_wbrp_cuif_zi_init_table_abort(CUIF_FEC_WBRP_BASE+9, 14)
+fec_wbrp_cuif_zi_init_table_abort(CUIF_FEC_WBRP_BASE+26, 7)
+fec_wbrp_cuif_zi_init_table_abort(CUIF_FEC_WBRP_BASE+34, 1)
+fec_wbrp_cuif_zi_init_table_abort(CUIF_FEC_WBRP_BASE+39, 3)
+
+fec_wbrp_cuif_zi_init_table_wake_up(CUIF_FEC_WBRP_BASE, 8)
+fec_wbrp_cuif_zi_init_table_wake_up(CUIF_FEC_WBRP_BASE+9, 14)
+fec_wbrp_cuif_zi_init_table_wake_up(CUIF_FEC_WBRP_BASE+26, 7)
+fec_wbrp_cuif_zi_init_table_wake_up(CUIF_FEC_WBRP_BASE+34, 1)
+fec_wbrp_cuif_zi_init_table_wake_up(CUIF_FEC_WBRP_BASE+39, 3)
+#endif
+
+
+speech_cuif_zi_init_table_boot_up(CUIF_SPEECH_BASE, 8)
+speech_cuif_zi_init_table_boot_up(CUIF_SPEECH_BASE+9, 14)
+speech_cuif_zi_init_table_boot_up(CUIF_SPEECH_BASE+26, 7)
+speech_cuif_zi_init_table_boot_up(CUIF_SPEECH_BASE+34, 1)
+speech_cuif_zi_init_table_boot_up(CUIF_SPEECH_BASE+39, 3)
+
+speech_cuif_zi_init_table_abort(CUIF_SPEECH_BASE, 8)
+speech_cuif_zi_init_table_abort(CUIF_SPEECH_BASE+9, 14)
+speech_cuif_zi_init_table_abort(CUIF_SPEECH_BASE+26, 7)
+speech_cuif_zi_init_table_abort(CUIF_SPEECH_BASE+34, 1)
+speech_cuif_zi_init_table_abort(CUIF_SPEECH_BASE+39, 3)
+
+speech_cuif_zi_init_table_wake_up(CUIF_SPEECH_BASE, 8)
+speech_cuif_zi_init_table_wake_up(CUIF_SPEECH_BASE+9, 14)
+speech_cuif_zi_init_table_wake_up(CUIF_SPEECH_BASE+26, 7)
+speech_cuif_zi_init_table_wake_up(CUIF_SPEECH_BASE+34, 1)
+speech_cuif_zi_init_table_wake_up(CUIF_SPEECH_BASE+39, 3)
+
+
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#endif
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n0.h b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..91f1d0b
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,211 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(EL1D_POS_Meas_Td2fd_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(EL1D_POS_Meas_Abort_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(EL1D_POS_Meas_Percell_0_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(EL1D_POS_Meas_Percell_1_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+//LTE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+//LTE IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_U2C_ULTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_U2C_DLTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_U2C_ULHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_HEAD)
+irq_entry_function(CUIF_U2C_DLHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_AUX)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_CLEAR_INNER_DDL_PROTECTION_DONE)
+irq_entry_function(ddl_clear_inner_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_CAN_DO_LTE)
+irq_entry_function(set_4g_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n1.h b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..fa4be29
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,136 @@
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve for ddr-en feature, plz don't use it
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve for ddr-en feature, plz don't use it
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve for ddr-en feature, plz don't use it
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve for ddr-en feature, plz don't use it
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n2.h b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..b4769ea
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,98 @@
+// 0
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleCeIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 1
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleJdIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 2
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_C3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n3.h b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..b897ca4
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,245 @@
+// 0
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W5_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n4.h b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..fc49ff5
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6293/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,163 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(EL1D_RxDspRpt_AFC_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n0.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..553b34f
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,217 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(EL1D_POS_Meas_Td2fd_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(EL1D_POS_Meas_Abort_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(EL1D_POS_Meas_Percell_0_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(EL1D_POS_Meas_Percell_1_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_U2C_ULTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_U2C_DLTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_U2C_ULHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_HEAD)
+irq_entry_function(CUIF_U2C_DLHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_AUX)
+irq_entry_function(CUIF_U2C_SPEECH_AUX_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_MM_TAIL)
+irq_entry_function(CUIF_U2C_MMTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n1.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..6632932
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,127 @@
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PING)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PONG)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_CLEAR_INNER_DDL_PROTECTION_DONE)
+irq_entry_function(ddl_clear_inner_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_CAN_DO_LTE)
+irq_entry_function(set_4g_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n2.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..b4769ea
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,98 @@
+// 0
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleCeIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 1
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleJdIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 2
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_C3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n3.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..b897ca4
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,245 @@
+// 0
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W5_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n4.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..d610b75
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,127 @@
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(EL1D_RxDspRpt_AFC_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(firstboot_check_cuif_connect_n4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n5.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n5.h
new file mode 100644
index 0000000..0e5617a
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n5.h
@@ -0,0 +1,106 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n6.h b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..23db6dd
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6295/cuif_u2c_isr_config_n6.h
@@ -0,0 +1,106 @@
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n0.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..315f0af
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,321 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(EL1D_POS_Meas_Td2fd_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(EL1D_POS_Meas_Abort_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(EL1D_POS_Meas_Percell_0_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3: reserved for ULSP on-demand logging lending from POS
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(EL1D_POS_Meas_Percell_1_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_U2C_ULTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_U2C_DLTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_U2C_ULHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_HEAD)
+irq_entry_function(CUIF_U2C_DLHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_AUX)
+irq_entry_function(CUIF_U2C_SPEECH_AUX_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_MM_TAIL)
+irq_entry_function(CUIF_U2C_MMTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(dhl_ulsp_dump_dsp_long_dump)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(dhl_ulsp_dump_dsp_short_dump)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)|| defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(EL1D_POS_Meas_Td2fd_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(EL1D_POS_Meas_Abort_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(EL1D_POS_Meas_Percell_0_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3: reserved for ULSP on-demand logging lending from POS
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(EL1D_POS_Meas_Percell_1_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_U2C_ULTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_U2C_DLTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_U2C_ULHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_HEAD)
+irq_entry_function(CUIF_U2C_DLHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_AUX)
+irq_entry_function(CUIF_U2C_SPEECH_AUX_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_MM_TAIL)
+irq_entry_function(CUIF_U2C_MMTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(dhl_ulsp_dump_dsp_long_dump)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(dhl_ulsp_dump_dsp_short_dump)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// SS IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// SS IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n1.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..e0637ad
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,246 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PING)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PONG)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_CLEAR_INNER_DDL_PROTECTION_DONE)
+irq_entry_function(ddl_clear_inner_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_CAN_DO_LTE)
+irq_entry_function(set_4g_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)|| defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PING)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PONG)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_CLEAR_INNER_DDL_PROTECTION_DONE)
+irq_entry_function(ddl_clear_inner_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_CAN_DO_LTE)
+irq_entry_function(set_4g_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n10.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n10.h
new file mode 100644
index 0000000..2713ba1
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n10.h
@@ -0,0 +1,230 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)|| defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n11.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n11.h
new file mode 100644
index 0000000..950d363
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n11.h
@@ -0,0 +1,221 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)|| defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+// 14
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n12.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n12.h
new file mode 100644
index 0000000..369bfa7
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n12.h
@@ -0,0 +1,170 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833) || defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n13.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n13.h
new file mode 100644
index 0000000..cc634d4
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n13.h
@@ -0,0 +1,268 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833) || defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n2.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..7f64e3a
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,218 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleCeIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 7
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleJdIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 8
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833) || defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleCeIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 7
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleJdIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 8
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n3.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..ae12414
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,358 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) ||defined(MT6853) ||defined(MT6833) || defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n4.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..d93affc
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,230 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE AFC IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(EL1D_RxDspRpt_AFC_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE AFC IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE AFC IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// LTE AFC IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833) || defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE AFC IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(EL1D_RxDspRpt_AFC_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE AFC IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE AFC IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// LTE AFC IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n5.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n5.h
new file mode 100644
index 0000000..d5d46f9
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n5.h
@@ -0,0 +1,246 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833) || defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n6.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..f05d75d
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n6.h
@@ -0,0 +1,358 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833) || defined(__MD97__)//MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n7.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n7.h
new file mode 100644
index 0000000..a93b38d
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n7.h
@@ -0,0 +1,230 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)|| defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n8.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n8.h
new file mode 100644
index 0000000..17e10a0
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n8.h
@@ -0,0 +1,230 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885) || defined(MT6873) || defined(MT6873) || defined(MT6853) ||defined(MT6833)|| defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n9.h b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n9.h
new file mode 100644
index 0000000..df7fccd
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/cuif_u2c_isr_config_n9.h
@@ -0,0 +1,230 @@
+#if defined(MT6297) //APOLLO
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#elif defined(MT6885) || defined(MT6885)|| defined(MT6873) || defined(MT6873) ||defined(MT6853) ||defined(MT6833)|| defined(__MD97__) //MT6885
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n10.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n10.h
new file mode 100644
index 0000000..fdda90b
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n10.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n11.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n11.h
new file mode 100644
index 0000000..5a0c61d
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n11.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n12.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n12.h
new file mode 100644
index 0000000..0bd6f2a
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n12.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n13.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n13.h
new file mode 100644
index 0000000..0fbdb20
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n13.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n14.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n14.h
new file mode 100644
index 0000000..9720b04
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n14.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N14_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n15.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n15.h
new file mode 100644
index 0000000..57870e7
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n15.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N15_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n16.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n16.h
new file mode 100644
index 0000000..a6759b0
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n16.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N16_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n17.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n17.h
new file mode 100644
index 0000000..2d2a6c8
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n17.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N17_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n18.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n18.h
new file mode 100644
index 0000000..e776a9b
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n18.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N18_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n19.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n19.h
new file mode 100644
index 0000000..96da239
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n19.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N19_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n20.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n20.h
new file mode 100644
index 0000000..dd3a55e
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n20.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N20_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n21.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n21.h
new file mode 100644
index 0000000..841296f
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n21.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N21_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n22.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n22.h
new file mode 100644
index 0000000..85d93ac
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n22.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N22_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n23.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n23.h
new file mode 100644
index 0000000..69095c2
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n23.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N23_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n6.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..cd34086
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n6.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n7.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n7.h
new file mode 100644
index 0000000..2d64029
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n7.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n8.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n8.h
new file mode 100644
index 0000000..64c25c7
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n8.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n9.h b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n9.h
new file mode 100644
index 0000000..daadeb0
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297/shcuif_u2c_isr_config_n9.h
@@ -0,0 +1,64 @@
+// 0
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE0)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(SHCUIF_DefaultISR)
+irq_auto_eoi(SHCUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_brp.h b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_brp.h
new file mode 100644
index 0000000..ad9b45f
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_brp.h
@@ -0,0 +1,173 @@
+// 0
+// HBRP IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP0_HSPA_SERV_SCCH)
+irq_entry_function(top_c2m_isr_serv_scch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// HBRP IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP1_HSPA_AGCH)
+irq_entry_function(top_c2m_isr_agch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// HBRP IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP2_HSPA_NC_SCCH)
+irq_entry_function(top_c2m_isr_nc_scch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// HBRP IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// HBRP IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_SS_TRIGGER_DDL)
+irq_entry_function(ddl_brp_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_T2F_CMD)
+irq_entry_function(LISR_BRP_lte_pos_td2fd_cmd)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_ABORT)
+irq_entry_function(LISR_lte_pos_abort)
+irq_auto_eoi(CUIF_TRUE)
+
+
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_CELL0_CMD)
+irq_entry_function(LISR_BRP_lte_pos_cell0)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_POS_CELL1_CMD)
+irq_entry_function(LISR_BRP_lte_pos_cell1)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// ULSP IRQ
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_ULSP_UT)
+irq_entry_function(ulsp_ut_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_brp_dual.h b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_brp_dual.h
new file mode 100644
index 0000000..2c83035
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_brp_dual.h
@@ -0,0 +1,125 @@
+// 0
+// HBRP IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP_DUAL0_HSPA_SERV_SCCH)
+irq_entry_function(top_c2m_isr_serv_scch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// HBRP IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP_DUAL1_HSPA_AGCH)
+irq_entry_function(top_c2m_isr_agch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// HBRP IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP_DUAL2_HSPA_NC_SCCH)
+irq_entry_function(top_c2m_isr_nc_scch_proc)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// HBRP IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP_DUAL3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// HBRP IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_HBRP_DUAL4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_DUAL_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_DUAL_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_DUAL_SS_TRIGGER_DDL)
+irq_entry_function(ddl_brp_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_DUAL_POS_T2F_CMD)
+irq_entry_function(LISR_BRP_lte_pos_td2fd_cmd)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_DUAL_POS_ABORT)
+irq_entry_function(LISR_lte_pos_abort)
+irq_auto_eoi(CUIF_TRUE)
+
+
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_DUAL_POS_CELL0_CMD)
+irq_entry_function(LISR_BRP_lte_pos_cell0)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_DUAL_POS_CELL1_CMD)
+irq_entry_function(LISR_BRP_lte_pos_cell1)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_DUAL_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_DUAL_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_BRP_DUAL_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_fec_wbrp.h b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_fec_wbrp.h
new file mode 100644
index 0000000..2966749
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_fec_wbrp.h
@@ -0,0 +1,136 @@
+// 0
+// FEC IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FEC IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FEC IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FEC IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FEC IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FEC IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FEC IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FEC IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FEC IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_FEC8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_TX_SS_TRIGGER_DDL)
+irq_entry_function(ddl_fec_tx_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// RESERVE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RX_SS_TRIGGER_DDL)
+irq_entry_function(ddl_fec_rx_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// RESERVE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RESEARVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// RESERVE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RESEARVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// RESERVE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RESEARVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// RESERVE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_FEC_WBRP_RESEARVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
diff --git a/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_inner.h b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_inner.h
new file mode 100644
index 0000000..f9ce286
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_inner.h
@@ -0,0 +1,189 @@
+/* inner callback */
+// 0
+// INNER IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// INNER IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 2
+// INNER IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 3
+// INNER IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 4
+// INNER IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 5
+// INNER IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// INNER IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER6)
+irq_entry_function(LISR_lte_inner_termination_tick)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// INNER IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// INNER IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER8_C2K_SCHD)
+irq_entry_function(LISR_c2k_c2uirq)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// INNER IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// INNER IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER10_TDSCDMA_SCHD)
+irq_entry_function(LISR_tdscdma_c2uirq)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// INNER IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER11_TDSCDMA_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// INNER IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER12_WCDMA_INIT_TICK)
+irq_entry_function(C2U_IRQ_wcdma_init_tick)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// INNER IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_SS_TRIGGER_DDL_OR_GDMA_DONE)
+irq_entry_function(ddl_inner_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_CANT_DO_LTE)
+irq_entry_function(inner_can_not_do_lte)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_CAN_DO_LTE)
+irq_entry_function(inner_can_do_lte)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// ULSP IRQ
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_ULSP_UT)
+irq_entry_function(ulsp_ut_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_inner_dual.h b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_inner_dual.h
new file mode 100644
index 0000000..9f56bf8
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_inner_dual.h
@@ -0,0 +1,212 @@
+/* inner callback */
+// 0
+// INNER IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// INNER IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 2
+// INNER IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 3
+// INNER IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 4
+// INNER IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+
+/************************* Core ISR Configure END ******************/
+
+// 5
+// INNER IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// INNER IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL6)
+irq_entry_function(LISR_lte_inner_termination_tick)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// INNER IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// INNER IRQ 8
+/************************* Core ISR Configure Begin ****************/
+//Masked in usip2
+#if defined(__CORE_USIP0__)
+irq_index(CUIF_C2U_INNER_INNER_DUAL8_C2K_SCHD)
+irq_entry_function(LISR_c2k_c2uirq)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 9
+// INNER IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// INNER IRQ 10
+/************************* Core ISR Configure Begin ****************/
+#if defined(__CORE_USIP0__)
+irq_index(CUIF_C2U_INNER_INNER_DUAL10_TDSCDMA_SCHD)
+irq_entry_function(LISR_tdscdma_c2uirq)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 11
+// INNER IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL11_TDSCDMA_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// INNER IRQ 12
+/************************* Core ISR Configure Begin ****************/
+#if defined(__CORE_USIP0__)
+irq_index(CUIF_C2U_INNER_INNER_DUAL12_WCDMA_INIT_TICK)
+irq_entry_function(C2U_IRQ_wcdma_init_tick)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 13
+// INNER IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_INNER_DUAL13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_SS_TRIGGER_DDL_OR_GDMA_DONE)
+irq_entry_function(ddl_inner_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_CANT_DO_LTE)
+irq_entry_function(inner_can_not_do_lte)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_CAN_DO_LTE)
+irq_entry_function(inner_can_do_lte)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_INNER_DUAL_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_speech.h b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_speech.h
new file mode 100644
index 0000000..83fe620
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297_c2u/cuif_c2u_isr_config_speech.h
@@ -0,0 +1,136 @@
+// 0
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SRST)
+irq_entry_function(SPH_SRstLisrHdlr)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SEND)
+irq_entry_function(SPH_SEndLisrHdlr)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_FSM_SEND)
+irq_entry_function(SPH_SOffLisrHdlr)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SS_DEACTIVATE)
+irq_entry_function(dsp_deactivate_callback)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SS_INIT_ACTIVATE)
+irq_entry_function(fill_bootup_pattern_after_cuifhandshake)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_SS_2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// RESERVE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// RESERVE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// RESERVE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// RESERVE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// RESERVE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// RESERVE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// RESERVE IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// RESERVE IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// RESERVE IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// RESERVE IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// ULSP IRQ
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_C2U_SPEECH_ULSP_UT)
+irq_entry_function(ulsp_ut_handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n0.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..9e45852
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,184 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY) //
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(EL1D_POS_Meas_Td2fd_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(EL1D_POS_Meas_Abort_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(EL1D_POS_Meas_Percell_0_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3: reserved for ULSP on-demand logging lending from POS
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(EL1D_POS_Meas_Percell_1_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_U2C_ULTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_U2C_DLTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_U2C_ULHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_HEAD)
+irq_entry_function(CUIF_U2C_DLHead_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_AUX)
+irq_entry_function(CUIF_U2C_SPEECH_AUX_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_MM_TAIL)
+irq_entry_function(CUIF_U2C_MMTail_ISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(dhl_ulsp_dump_dsp_long_dump)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(dhl_ulsp_dump_dsp_short_dump)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// SS IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// SS IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#endif
+
+
+
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n1.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..dc7d8c7
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PING)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_BRP_DCI_RESULT_READY_PONG)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_CLEAR_INNER_DDL_PROTECTION_DONE)
+irq_entry_function(ddl_clear_inner_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_CAN_DO_LTE)
+irq_entry_function(set_4g_ddl_protection_done)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n10.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n10.h
new file mode 100644
index 0000000..544d0b1
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n10.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n11.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n11.h
new file mode 100644
index 0000000..2aa1f25
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n11.h
@@ -0,0 +1,123 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+// 14
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n12.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n12.h
new file mode 100644
index 0000000..fc9381c
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n12.h
@@ -0,0 +1,114 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n13.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n13.h
new file mode 100644
index 0000000..0c8fd00
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n13.h
@@ -0,0 +1,142 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n2.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..1d2a0aa
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,142 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleCeIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 7
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+#ifdef __UMTS_TDD128_MODE__
+irq_entry_function(InrTop_HandleJdIrq)
+irq_auto_eoi(CUIF_FALSE)
+#else
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+#endif
+/************************* Core ISR Configure END ******************/
+
+// 8
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n3.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..3ad2778
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,236 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(UL1D_RXBRP_Interrupt_Handler)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n4.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..b0e0929
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE AFC IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(EL1D_RxDspRpt_AFC_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE AFC IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE AFC IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// LTE AFC IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n5.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n5.h
new file mode 100644
index 0000000..4feda96
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n5.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(EL1D_RxDspRpt_FWS_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n6.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..26f37ce
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n6.h
@@ -0,0 +1,188 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n7.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n7.h
new file mode 100644
index 0000000..e607c49
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n7.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n8.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n8.h
new file mode 100644
index 0000000..f411016
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n8.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n9.h b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n9.h
new file mode 100644
index 0000000..383e839
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/mt6297p/cuif_u2c_isr_config_n9.h
@@ -0,0 +1,140 @@
+#if defined(MERCURY) || defined(CHIPID_MERCURY)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE DCI IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_L0)
+irq_entry_function(EL1D_RxDspRpt_DCI_IRQ_Handler)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/common/interface/driver/sys_drv/cuif/shcuif_common_def.h b/common/interface/driver/sys_drv/cuif/shcuif_common_def.h
new file mode 100644
index 0000000..a72afbf
--- /dev/null
+++ b/common/interface/driver/sys_drv/cuif/shcuif_common_def.h
@@ -0,0 +1,181 @@
+/*******************************************
+* please DO NOT include this file
+* this file is for mcu/dsp shcuif driver include only
+************************************************/
+
+/*******************************************************************************
+ * Enums
+ *******************************************************************************/
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(index) index,
+#define irq_name(name)
+#define irq_entry_function(fun)
+#define irq_auto_eoi(eoi)
+
+/* U2C */
+
+#if defined(__DSP_CODEBASE_MT6297__)
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N6_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n6.h"
+ SHCUIF_U2C_N6_TOTAL_NUMBER
+}SHCUIF_U2C_N6_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N7_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n7.h"
+ SHCUIF_U2C_N7_TOTAL_NUMBER
+}SHCUIF_U2C_N7_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N8_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n8.h"
+ SHCUIF_U2C_N8_TOTAL_NUMBER
+}SHCUIF_U2C_N8_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N9_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n9.h"
+ SHCUIF_U2C_N9_TOTAL_NUMBER
+}SHCUIF_U2C_N9_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N10_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n10.h"
+ SHCUIF_U2C_N10_TOTAL_NUMBER
+}SHCUIF_U2C_N10_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N11_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n11.h"
+ SHCUIF_U2C_N11_TOTAL_NUMBER
+}SHCUIF_U2C_N11_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N12_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n12.h"
+ SHCUIF_U2C_N12_TOTAL_NUMBER
+}SHCUIF_U2C_N12_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N13_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n13.h"
+ SHCUIF_U2C_N13_TOTAL_NUMBER
+}SHCUIF_U2C_N13_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N14_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n14.h"
+ SHCUIF_U2C_N14_TOTAL_NUMBER
+}SHCUIF_U2C_N14_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N15_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n15.h"
+ SHCUIF_U2C_N15_TOTAL_NUMBER
+}SHCUIF_U2C_N15_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N16_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n16.h"
+ SHCUIF_U2C_N16_TOTAL_NUMBER
+}SHCUIF_U2C_N16_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N17_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n17.h"
+ SHCUIF_U2C_N17_TOTAL_NUMBER
+}SHCUIF_U2C_N17_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N18_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n18.h"
+ SHCUIF_U2C_N18_TOTAL_NUMBER
+}SHCUIF_U2C_N18_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N19_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n19.h"
+ SHCUIF_U2C_N19_TOTAL_NUMBER
+}SHCUIF_U2C_N19_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N20_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n20.h"
+ SHCUIF_U2C_N20_TOTAL_NUMBER
+}SHCUIF_U2C_N20_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N21_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n21.h"
+ SHCUIF_U2C_N21_TOTAL_NUMBER
+}SHCUIF_U2C_N21_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N22_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n22.h"
+ SHCUIF_U2C_N22_TOTAL_NUMBER
+}SHCUIF_U2C_N22_Code_t;
+
+typedef enum SHCUIF_U2C_InterruptHandlerCode_N23_Enum{
+ #include "mt6297/shcuif_u2c_isr_config_n23.h"
+ SHCUIF_U2C_N23_TOTAL_NUMBER
+}SHCUIF_U2C_N23_Code_t;
+
+#else
+ #error "Not support this generation !!!!"
+#endif
+
+/* SHCUIF MCU Int enum */
+typedef enum SHCUIF_MCU_Int_Enum{
+ SHCUIF_ENUM_N6,
+ SHCUIF_ENUM_N7,
+ SHCUIF_ENUM_N8,
+ SHCUIF_ENUM_N9,
+ SHCUIF_ENUM_N10,
+ SHCUIF_ENUM_N11,
+ SHCUIF_ENUM_N12,
+ SHCUIF_ENUM_N13,
+ SHCUIF_ENUM_N14,
+ SHCUIF_ENUM_N15,
+ SHCUIF_ENUM_N16,
+ SHCUIF_ENUM_N17,
+ SHCUIF_ENUM_N18,
+ SHCUIF_ENUM_N19,
+ SHCUIF_ENUM_N20,
+ SHCUIF_ENUM_N21,
+ SHCUIF_ENUM_N22,
+ SHCUIF_ENUM_N23,
+ SHCUIF_ENUM_ALL_MCU_INT_NUM
+}SHCUIF_MCU_INT;
+
+typedef enum SHCUIF_INT_MASK_Enum{
+ SHCUIF_ENUM_AND_OP,
+ SHCUIF_ENUM_OR_OP,
+ SHCUIF_ENUM_ALL_INT_MASK_OP
+}SHCUIF_INT_MASK_OP_t;
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+
+
+#define SHCUIF_MCU_INT_N6_SOURCES (8)
+#define SHCUIF_MCU_INT_N7_SOURCES (8)
+#define SHCUIF_MCU_INT_N8_SOURCES (8)
+#define SHCUIF_MCU_INT_N9_SOURCES (8)
+#define SHCUIF_MCU_INT_N10_SOURCES (8)
+#define SHCUIF_MCU_INT_N11_SOURCES (8)
+#define SHCUIF_MCU_INT_N12_SOURCES (8)
+#define SHCUIF_MCU_INT_N13_SOURCES (8)
+#define SHCUIF_MCU_INT_N14_SOURCES (8)
+#define SHCUIF_MCU_INT_N15_SOURCES (8)
+#define SHCUIF_MCU_INT_N16_SOURCES (8)
+#define SHCUIF_MCU_INT_N17_SOURCES (8)
+#define SHCUIF_MCU_INT_N18_SOURCES (8)
+#define SHCUIF_MCU_INT_N19_SOURCES (8)
+#define SHCUIF_MCU_INT_N20_SOURCES (8)
+#define SHCUIF_MCU_INT_N21_SOURCES (8)
+#define SHCUIF_MCU_INT_N22_SOURCES (8)
+#define SHCUIF_MCU_INT_N23_SOURCES (8)
+
+
+/* get shcuif IRQ limit number by module enum*/
+/* e.g. GET_MODULE_IRQ_LIMIT_NUMBER(INNER) => SHCUIF_NUM_INTERRUPT_INNER_SOURCES */
+
+#define SHCUIF_POSTFIX(mID, pos) mID##pos
+#define SHCUIF_PREFIX(mID, pre) SHCUIF_POSTFIX(pre##mID, _SOURCES)
+#define SHCUIF_GET_MODULE_IRQ_LIMIT_NUMBER(mID) SHCUIF_PREFIX(mID, SHCUIF_NUM_INTERRUPT_)
+
+/* e.g. GET_MCU_SHCUIF_INT_IRQ_LIMIT_NUMBER(N0) => SHCUIF_MCU_INT_N0_SOURCES */
+#define GET_MCU_SHCUIF_INT_IRQ_LIMIT_NUMBER(nID) SHCUIF_PREFIX(nID, SHCUIF_MCU_INT_)
+
+
diff --git a/common/interface/modem/external/ps_inter_core_public.h b/common/interface/modem/external/ps_inter_core_public.h
new file mode 100644
index 0000000..432ccf4
--- /dev/null
+++ b/common/interface/modem/external/ps_inter_core_public.h
@@ -0,0 +1,95 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ps_inter_core_public.h
+ *
+ * Project:
+ * --------
+ *
+ * Description:
+ * ------------
+ * This file contains inter core definitions.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *****************************************************************************/
+
+#ifndef __PS_INTER_CORE_PUBLIC_H__
+#define __PS_INTER_CORE_PUBLIC_H__
+
+/*****************************************************************************
+* Operator ID definition
+*****************************************************************************/
+typedef enum
+{
+ OPERATOR_ID_DCM, // Docomo
+ OPERATOR_ID_TMO, // TMO
+ OPERATOR_ID_VZW, // Verizon Wireless
+ OPERATOR_ID_CMCC, // CMCC
+ OPERATOR_ID_SKT, // SK Telecom
+ OPERATOR_ID_CU, // China Unicom
+ OPERATOR_ID_ATT, // AT&T
+ OPERATOR_ID_LGUP, // LG U+
+ OPERATOR_ID_RJIL, // Reliance Jio Infocomm Limited
+ OPERATOR_ID_KDDI, // KDDI
+ OPERATOR_ID_SPRINT, // Sprint
+ OPERATOR_ID_CT, // China Telecom
+ OPERATOR_ID_FIRSTNET, // FirstNet
+ OPERATOR_ID_CUSTOM_HSR_NW, // Custom HSR network
+ OPERATOR_ID_AIRTEL, // Airtel
+ OPERATOR_ID_DTAC, // DTAC
+ OPERATOR_ID_SMARTFREN, // Smartfren
+ OPERATOR_ID_TWM, // TWM
+ OPERATOR_ID_TESTSIM, // TESTSIM
+ OPERATOR_ID_NOKIA_OYJ, // Nokia Oyj
+ OPERATOR_ID_SMARTONE, // SmarTone
+ OPERATOR_ID_FET, // FET, Taiwan
+ OPERATOR_ID_PLUS, // Plus, Poland
+ OPERATOR_ID_BOUYGUES, // Bouygues, France
+ OPERATOR_ID_OPTUS, // Optus, Australia
+ OPERATOR_ID_USCC, // U.S. Cellular
+ OPERATOR_ID_RKT, // RAKUTEN, JP
+
+// Please add new operator ID's before OPERATOR_ID_OTHER
+ OPERATOR_ID_OTHER // Other operator
+} operator_id_enum;
+
+#endif /* _PS_INTER_CORE_PUBLIC_H_ */
diff --git a/common/interface/modem/mt6297/common/nr/external/5g/nl2_brp_struct.h b/common/interface/modem/mt6297/common/nr/external/5g/nl2_brp_struct.h
new file mode 100644
index 0000000..ca24b28
--- /dev/null
+++ b/common/interface/modem/mt6297/common/nr/external/5g/nl2_brp_struct.h
@@ -0,0 +1,69 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef NL2_BRP_STRUCT_H
+#define NL2_BRP_STRUCT_H
+
+/********************************************
+ * TYPE DEFINITIONS & ENUMS *
+ ********************************************/
+
+typedef union {
+ struct {
+ kal_uint32 tbs:18; // [17:0], the field is used for DL TB size
+ kal_uint32 _reserved0:1; // [18:18]
+ kal_uint32 dci_format:1; // [19:19], 0: DCI format 1_0; 1: DCI format 1_1
+ kal_uint32 mcs_c_rnti:1; // [20:20], flag, value 1 if it's mcs-c-rnti, otherwise value 0
+ kal_uint32 pucch_k1_ind:3; // [23:21], K1 indicator from DCI field "pdsch-to-HARQ feedback timing indicator"
+ kal_uint32 slot_num:5; // [28:24]
+ kal_uint32 tg_id:2; // [30:29], NL1 tick group ID.
+ kal_uint32 frame_num_b0:1; // [31:31]s
+ } b;
+ kal_uint32 w32;
+} BRP_L2_INTF_GP_LOW;
+
+typedef union {
+ struct {
+ kal_uint32 frame_num_b9_1:9; // [8:0]
+ kal_uint32 sub_frame_num:4; // [12:9]
+ kal_uint32 _reserved0:19; // [31:13]
+ } b;
+ kal_uint32 w32;
+} BRP_L2_INTF_GP_HIGH;
+
+
+
+#endif /* NL2_BRP_STRUCT_H */
+
diff --git a/common/interface/modem/mt6297/common/nr/external/5g/nl2_nl1_struct.h b/common/interface/modem/mt6297/common/nr/external/5g/nl2_nl1_struct.h
new file mode 100644
index 0000000..da9fb00
--- /dev/null
+++ b/common/interface/modem/mt6297/common/nr/external/5g/nl2_nl1_struct.h
@@ -0,0 +1,617 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _NL2_NL1_STRUCT_H
+#define _NL2_NL1_STRUCT_H
+
+// include dependency headers
+//#include "kal_public_api.h" //it will inlcude in nl1_comm_inter_core_public.h
+#include "nl1_comm_inter_core_public.h"
+
+/********************************************
+ * MACROS *
+ ********************************************/
+#define NMAC_NL1_UL_TOTAL_TB_SIZE_NO_UPDATE 0xFFFFFFFF
+#define NMAC_NL1_HARQ_ID_CLOSE_ALL 0xFF
+#define NMAC_NL1_DL_HARQ_CLOSE_ALL_BMP 0xFFFF
+#define NMAC_NL1_MAX_SR_RESOURCE_CONFIG_NUM 8
+#define NMAC_MAX_CG_NUM_FOR_LCP_RESTRICT (2)
+#define NMAC_MAX_BEARER_NUM (32)
+#define NRLC_NL1_MAX_REPORTED_CELL_NUM (10)
+#define NRLC_NL1_MAX_IDC_GAP_CELL_NUM NL1_MAX_CC_NUM
+
+/********************************************
+ * TYPE DEFINITIONS & ENUMS *
+ ********************************************/
+typedef enum
+{
+ NL1_POWER_ON_CAUSE_IDLE_SCH_OPEN,
+ NL1_POWER_ON_CAUSE_DRX_AWAKE,
+ NL1_POWER_ON_CAUSE_ENTER_META,
+ NL1_POWER_ON_CAUSE_NOT_SPECIFIED
+} nl1_power_on_cause_e;
+
+typedef enum
+{
+ NL1_POWER_OFF_CAUSE_IDLE_SCH_CLOSE,
+ NL1_POWER_OFF_CAUSE_DRX_SLP,
+ NL1_POWER_OFF_CAUSE_LEAVE_META,
+ NL1_POWER_OFF_CAUSE_NOT_SPECIFIED
+} nl1_power_off_cause_e;
+
+typedef enum
+{
+ NMAC_SCS_15K,
+ NMAC_SCS_30K,
+ NMAC_SCS_60K,
+ NMAC_SCS_120K,
+ NMAC_SCS_240K,
+ NMAC_SCS_480K
+
+} nmac_scs_idx_e;
+
+typedef enum
+{
+ NL1_PHY_CONFIG_CHG_CAUSE_RRC_CONFIG,
+ NL1_PHY_CONFIG_CHG_CAUSE_BWP_SWITCH,
+
+ NL1_PHY_CONFIG_CHG_CAUSE_NUM,
+} nl1_phy_config_chg_cause_e;
+
+typedef enum
+{
+ NRLCUL_NL1_GAMING_STATUS_INVALID = 0,
+ NRLCUL_NL1_GAMING_STATUS_NEW = 1,
+ NRLCUL_NL1_GAMING_STATUS_LONG_GOOD = 2,
+ NRLCUL_NL1_GAMING_STATUS_GOOD = 3,
+ NRLCUL_NL1_GAMING_STATUS_BAD = 4,
+ NRLCUL_NL1_GAMING_STATUS_VERY_BAD = 5,
+ NRLCUL_NL1_GAMING_STATUS_LONG_VERY_BAD = 6,
+ NRLCUL_NL1_GAMING_STATUS_NUM = 7
+} nrlcul_nl1_gaming_status_e;
+
+typedef enum
+{
+ NRLCUL_NL1_GAMING_MCG = 0,
+ NRLCUL_NL1_GAMING_SCG = 1,
+ NRLCUL_NL1_GAMING_HISTORICAL = 2
+} nrlcul_nl1_gaming_cell_group_e;
+
+typedef enum
+{
+ NRLCDL_NL1_IDC_GAP_STATUS_UNUSED_CC = 0,
+ NRLCDL_NL1_IDC_GAP_STATUS_OFF = 1,
+ NRLCDL_NL1_IDC_GAP_STATUS_ON = 2
+} nrlcdl_nl1_idc_gap_status_e;
+
+typedef enum
+{
+ NMAC_NL1_MSG3_FLUSH_CAUSE_RA_INIT,
+ NMAC_NL1_MSG3_FLUSH_CAUSE_RA_COMPLETE,
+ NMAC_NL1_MSG3_FLUSH_CAUSE_RA_ABORT,
+
+ NMAC_NL1_MSG3_FLUSH_CAUSE_NUM
+} nmac_nl1_flush_msg3_cause_e;
+
+typedef enum
+{
+ NMAC_NL1_DL_HARQ_CLOSE_CAUSE_SCELL_DEACTIVATE,
+
+ NMAC_NL1_DL_HARQ_CLOSE_CAUSE_NUM
+} nmac_nl1_dl_harq_close_cause_e;
+
+typedef enum
+{
+ NMAC_NL1_DEFENSE_GAP_ACTION_CAUSE_INVALID_GRANT,
+ NMAC_NL1_DEFENSE_GAP_ACTION_CAUSE_LEAVE_MEAS_GAP,
+ NMAC_NL1_DEFENSE_GAP_ACTION_CAUSE_POSSIBLE_DCI_IN_MEAS_GAP,
+} nmac_nl1_defense_gap_action_cause_e;
+
+/* MSG_ID_NRLCUL_NL1_GAMING_CELL_INFO_NTF */
+typedef struct
+{
+ kal_uint16 pci;
+ kal_uint16 rsvd;
+ kal_uint32 narfcn;
+ nrlcul_nl1_gaming_status_e cell_status;
+ nrlcul_nl1_gaming_cell_group_e cell_group;
+} nrlcul_nl1_gaming_cell_info_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_num;
+ kal_uint16 rsvd;
+ nrlcul_nl1_gaming_cell_info_struct cell_info[NRLC_NL1_MAX_REPORTED_CELL_NUM];
+} nrlcul_nl1_gaming_cell_info_ntf_struct;
+
+/* MSG_ID_NMAC_NL1_MAC_RESET_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_group_id;
+} nmac_nl1_mac_reset_req_struct;
+
+/* MSG_ID_NMAC_NL1_DL_HARQ_RESET_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 sim_idx;
+ kal_uint8 cg_id;
+ kal_uint8 cc_idx;
+ kal_uint16 harq_id_bmp;
+} nmac_nl1_dl_harq_reset_req_struct;
+
+/* MSG_ID_NMAC_NL1_MAC_RESET_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nmac_nl1_mac_reset_cnf_struct;
+
+/* MSG_ID_NMAC_NL1_HARQ_CLOSE_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_group_id;
+ kal_uint8 ul_cc_bitmap;
+ kal_uint8 harq_id; /// For closing single HARQ, in 'ul_cc_bitmap' only 1 bit can be set.
+ kal_bool flush_msg3;
+ nmac_nl1_flush_msg3_cause_e flush_msg3_cause;
+} nmac_nl1_harq_close_ind_struct;
+
+/* MSG_ID_NMAC_NL1_DL_HARQ_CLOSE_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cg_id_bmp; // For gen97: MCG = CG0, SCG = CG1; LSB: CG0
+ kal_uint8 cc_id_bmp; // LSB: CC0
+ kal_uint16 harq_id_bmp; // LSB: HARQ#0
+ nmac_nl1_dl_harq_close_cause_e dl_harq_close_cause;
+} nmac_nl1_dl_harq_close_ind_struct;
+
+/* MSG_ID_NMAC_NL1_SR_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 log_ch_id;
+ kal_uint8 sr_id;
+ kal_uint8 CCCH[6]; ///< CCCH SDU size can be > 48 bits, this field may only contained first 6 bytes of CCCH SDU
+ kal_uint8 CCCH_len;
+ kal_uint32 potential_msg3_size; ///< this field is unused, only kept for xl1sim compatibility
+ kal_uint32 timestamp;
+ kal_bool si_request;
+ kal_bool fast_recovery;
+} nmac_nl1_sr_req_struct;
+
+/* MSG_ID_NMAC_NL1_MAC_SWITCH_VIRTUAL_CONNECTED_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nmac_nl1_mac_switch_virtual_connected_req_struct;
+
+/* MSG_ID_NMAC_NL1_MAC_SWITCH_VIRTUAL_CONNECTED_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nmac_nl1_mac_switch_virtual_connected_cnf_struct;
+
+/* MSG_ID_NMAC_NL1_SPS_START_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 sim_index;
+ kal_uint8 cell_group_id;
+} nmac_nl1_sps_start_ind_struct;
+
+/* MSG_ID_NMAC_NL1_SPS_END_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 sim_index;
+ kal_uint8 cell_group_id;
+} nmac_nl1_sps_end_ind_struct;
+
+/* MSG_ID_NMAC_NL1_UL_TOTAL_TB_SIZE_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 total_tb_size_mcg;
+ kal_uint32 total_tb_size_scg;
+} nmac_nl1_total_tb_size_ind_struct;
+
+typedef enum
+{
+ NL1_USER_SUB6_CG0,
+ NL1_USER_SUB6_CG1,
+ NL1_USER_MMW,
+ NL1_USER_NUM
+} nl1_power_user_e;
+
+/* MSG_ID_NL2POW_NL1_L2COPRO_POWER_ON_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_power_on_cause_e cause;
+ nl1_power_user_e user_id;
+} nl1_nl2pow_l2copro_power_on_ind_struct;
+
+/* MSG_ID_NL2POW_NL1_L2COPRO_POWER_OFF_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_power_off_cause_e cause;
+ nl1_power_user_e user_id;
+} nl1_nl2pow_l2copro_power_off_ind_struct;
+
+/* To indicate event time */
+typedef struct
+{
+ kal_uint16 sfn;
+ kal_uint8 subframe;
+ kal_uint8 slot;
+} nmac_nl1_event_time_struct;
+
+/* MSG_ID_NMAC_NL1_RA_START_IND (NR ICD RACH attempt start) */
+typedef struct
+{
+ kal_uint16 c_rnti;
+ kal_uint8 preamble_ra_idx; // ra-ssb-OccasionMaskIndex ?
+ kal_uint8 reason;
+ kal_bool contention;
+ kal_uint16 msg3_size;
+ kal_uint8 ueid[6];
+ kal_bool preamble_grp_chosen;
+
+ /*** RA parameters in RRC configuration used ***/
+ kal_int16 preamble_init_pwr;
+ kal_uint8 step_pwr;
+ kal_uint8 max_preamble_attempt;
+ kal_uint8 p_max;
+ kal_uint8 delta_preamble_pwr_msg3;
+ kal_uint8 cr_timer;
+ kal_uint8 grp_b_pwr_offset;
+ kal_uint8 grp_a_preamble_idx;
+ kal_uint8 grp_b_preamble_idx;
+ kal_uint8 grp_a_sel_threshold;
+ kal_uint8 rar_window_size;
+ /*** RA parameters in RRC configuration used ***/
+
+ nmac_nl1_event_time_struct event_time;
+} nmac_nl1_ra_start_ind_struct;
+
+/* MSG_ID_NMAC_NL1_RA_FINISH_IND (NR ICD RACH attempt complete) */
+typedef struct
+{
+ kal_uint8 attempt_counter;
+ kal_uint8 result;
+ kal_bool is_contention_based;
+ kal_uint8 rach_msg;
+ kal_uint8 preamble_idx;
+ kal_uint32 msg3_grant;
+ kal_uint16 ta_value;
+ kal_bool rar_success;
+ kal_uint16 tc_rnti;
+ kal_uint16 pci;
+ kal_uint32 arfcn;
+ kal_uint16 backoff_time;
+ kal_uint16 ra_rnti;
+ kal_uint8 preamble_pwr_offset;
+ kal_uint8 last_tx_pwr;
+ nmac_nl1_event_time_struct ra_start_time;
+ nmac_nl1_event_time_struct ra_finish_time;
+} nmac_nl1_ra_finish_ind_struct;
+
+typedef struct
+{
+ nmac_nl1_event_time_struct msg2_latency;
+ nmac_nl1_event_time_struct rach_delay;
+} nmac_nl1_ra_delay_ind_struct;
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nmac_nl1_ra_start_ind_struct ra_start_t;
+ nmac_nl1_ra_finish_ind_struct ra_finish_t;
+ nmac_nl1_ra_delay_ind_struct ra_delay_t;
+ kal_uint32 first_prach_tx_rtos_time;
+} nmac_nl1_ra_icd_info_ind_struct;
+/* MSG_ID_NMAC_NL1_TIMER_STATUS_IND (NR ICD Timer Status) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 mac_timer_name;
+ kal_uint8 timer_status;
+ nmac_nl1_event_time_struct event_time;
+} nmac_nl1_timer_status_ind_struct;
+
+/* MSG_ID_NMAC_NL1_TIMING_ADVANCE_IND (NR ICD Timing Advance) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 ta_timer_len;
+ kal_uint8 timing_advance;
+ nmac_nl1_event_time_struct event_time;
+} nmac_nl1_timing_advance_ind_struct;
+
+/* MSG_ID_NMAC_NL1_SR_MAX_IND (NR ICD SR TX MAX) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 sr_index;
+ kal_uint8 sr_tx_count;
+} nmac_nl1_sr_max_ind_struct;
+
+/* MSG_ID_NMAC_NL1_SR_TX_IND (NR ICD SR TX) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 sr_index;
+ kal_uint8 sr_tx_count;
+ kal_uint8 cell_group_id;
+} nmac_nl1_sr_tx_ind_struct;
+
+/* MSG_ID_NMAC_NL1_CA_IND (NR ICD Carrier Aggregation) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_scell_activated;
+ kal_uint8 num_ca;
+ kal_uint32 cell_index_bitmap;
+ kal_uint8 cell_group_id;
+ nmac_nl1_event_time_struct event_time;
+} nmac_nl1_ca_ind_struct;
+
+/* MSG_ID_NMAC_NL1_DRX_ICD_INFO_IND (NR ICD DRX Status) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nmac_nl1_event_time_struct event_time;
+ nmac_nl1_event_time_struct next_on_time;
+ //kal_uint8 cg_id; // prepare for NRDC
+ kal_bool b_drx_status_valid;
+ kal_bool is_drx_active;
+ kal_bool b_drx_cycle_type_valid;
+ kal_bool is_long_cycle;
+ kal_bool b_drx_inact_tmr_status_valid;
+ kal_bool is_inact_tmr_start;
+ kal_uint8 ref_scs;
+} nmac_nl1_drx_status_ind_struct;
+
+/* MSG_ID_NMAC_NL1_P_SI_TB_IND (NR ICD 4.4 DL TB) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 transport_channel;
+ kal_uint32 frame;
+ kal_uint32 sf;
+ kal_uint32 rnti;
+ kal_uint32 tb_size;
+} nmac_nl1_p_si_tb_ind_struct;
+
+/* MSG_ID_NMAC_NL1_SERVING_CELL_INFO_IND (Thermal Control) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_idx;
+ NL1_BAND_E band;
+ kal_bool is_mcg;
+ kal_bool is_spcell;
+ kal_bool is_activated;
+ kal_bool is_dl_only;
+} nmac_nl1_serving_cell_info_ind_struct;
+
+/* MSG_ID_NMAC_NL1_THERMAL_CTRL_NTF (Thermal Control) */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_tmc_session;
+ kal_bool is_tmc_scg_disable;
+ kal_uint32 serv_cell_tmc_bmp;
+} nmac_nl1_thermal_ctrl_ntf_struct;
+
+typedef struct
+{
+ kal_bool is_on_duration_timer_ms; // 0: 1/32 ms, 1: ms
+ kal_uint16 drx_on_duration_timer;
+ kal_uint16 drx_inactivity_timer;
+ kal_uint16 drx_retransmission_timer_dl;
+ kal_uint16 drx_retransmission_timer_ul;
+ kal_uint16 drx_start_offset;
+ kal_uint8 drx_slot_offset;
+ kal_uint8 drx_harq_rtt_timer_dl;
+ kal_uint8 drx_harq_rtt_timer_ul;
+ kal_bool drx_short_cycle_config_valid;
+ kal_uint8 drx_short_cycle_timer;
+ kal_uint16 drx_short_cycle;
+ kal_uint16 drx_long_cycle;
+} nmac_nl1_drx_config_struct;
+
+typedef struct
+{
+ kal_uint8 sr_id; // 0-7, scheduling request ID, NOT scheduling request resource ID
+ kal_uint16 sr_periodicity; // Fill in 1 if periodicity < 1ms
+ kal_uint16 sr_offset; // Fill in 0 if periodicity < 1ms
+} nmac_nl1_sr_resource_config_struct;
+
+/* MSG_ID_NMAC_NL1_PHY_CONFIG_INFO_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cg_id;
+ nl1_phy_config_chg_cause_e chg_cause;
+ kal_bool is_drx_config_valid;
+ nmac_nl1_drx_config_struct drx_config;
+ kal_uint8 num_sr_resource_config;
+ nmac_nl1_sr_resource_config_struct sr_resource_config[NMAC_NL1_MAX_SR_RESOURCE_CONFIG_NUM]; // SR resource config of the active UL BWP
+} nmac_nl1_phy_config_info_ind_struct;
+
+//MSG_ID_NMAC_NL1_BUCKET_STATUS_UPDATE_RSP
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 cg_id;
+ kal_bool nmacce_in_next;
+ kal_uint32 bucket_bitmap[2];
+} nmac_nl1_bucket_status_update_rsp_struct;
+
+
+//MSG_ID_NMAC_NL1_BUCKET_EXIST_DATA_RSP
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rb_idx;
+ kal_uint8 rlc_idx;
+} nmac_nl1_bucket_exist_data_rsp_struct;
+
+typedef struct
+{
+ /** The number of allowed subcarrier spacing, if number > 0 means lcp restriction is configured */
+ kal_uint8 allowed_scs_num;
+
+ /** The list of allowed subcarrier spacing */
+ nmac_scs_idx_e allowed_scs_list[5];
+
+ /** If value is KAL_TRUE, only the configured max pusch_dura is allowed */
+ kal_bool is_max_pusch_dura_valid;
+
+ /** The max allowed pusch duration, unit: us */
+ kal_uint32 max_pusch_dura;
+
+ /** If value is KAL_TRUE means lcp restriction is configured, only type1 grant is allowed to transmit data */
+ kal_bool cfg_grant_type1_allowed;
+
+ /** The number of allowed serving cells, if number > 0 means lcp restriction is configured */
+ kal_uint8 allowed_cell_num;
+
+ /** The list of allowed serving cells */
+ kal_uint8 allowed_cell_list[32];
+} lcpr_params_struct;
+
+typedef struct
+{
+ kal_uint8 rb_idx;
+ kal_uint8 rlc_idx;
+ kal_bool is_rb_valid;
+ lcpr_params_struct lcpr_para;
+} rb_lcpr_info_struct;
+
+//MSG_ID_NRLCUL_NL1_LCPR_PARAM_RSP
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 num_lcp_restrict_params[NMAC_MAX_CG_NUM_FOR_LCP_RESTRICT];
+ rb_lcpr_info_struct lcp_restrict_params[NMAC_MAX_CG_NUM_FOR_LCP_RESTRICT][NMAC_MAX_BEARER_NUM];
+} nrlcul_nl1_lcpr_param_rsp_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_num;
+ kal_uint16 rsvd;
+ nrlcdl_nl1_idc_gap_status_e cell_status[NRLC_NL1_MAX_IDC_GAP_CELL_NUM];
+} nrlcdl_nl1_idc_gap_ind_struct;
+
+typedef struct
+{
+ kal_uint8 allowed_scs_num;
+ nmac_scs_idx_e allowed_scs_list[5];
+ kal_bool is_max_pusch_dura_valid;
+ kal_uint32 max_pusch_dura;
+ kal_bool cfg_grant_type1_allowed;
+ kal_uint8 allowed_cell_num;
+ kal_uint8 allowed_cell_list[8];
+} nl1_nmac_lcp_params_struct;
+
+typedef struct
+{
+ kal_uint8 rb_idx;
+ kal_uint8 rlc_idx;
+ kal_bool is_rb_valid;
+ nl1_nmac_lcp_params_struct lcpr_para;
+} nl1_nmac_lcp_info_struct;
+
+typedef struct
+{
+ kal_uint8 num_lcp_restrict_params;
+ nl1_nmac_lcp_info_struct lcp_restrict_params[NMAC_MAX_BEARER_NUM];
+} nl1_nmac_lcp_msg_struct;
+
+/* MSG_ID_NMAC_NL1_LEAVE_GEMINI_GAP_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 gemini_gap_legnth;
+} nl1_mac_leave_gemini_gap_ind_struct;
+
+/* MSG_ID_NMAC_NL1_LEAVE_IDC_GAP_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cg_idx; // cell group index, this can be ignored(with fixed value) in Gen97, but needed in Gen98 for NN-DC
+ kal_uint32 idc_tx_gap_length; // unit: ms
+} nmac_nl1_leave_idc_gap_ind_struct;
+
+/* MSG_ID_NMAC_NL1_RA_COMPLETE_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cg_id;
+ NL1_TX_RA_EVENT_E ra_event;
+} nl1_nmac_ra_complete_ind_struct;
+
+/* MSG_ID_NMAC_NL1_DEFENSE_GAP_ACTION_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nmac_nl1_defense_gap_action_cause_e cause;
+} nmac_nl1_defense_gap_action_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool gemini_gap_state;
+} enpdcp_nl1_gemini_gap_state_ind_struct;
+/********************************************
+ * VARIABLES *
+ ********************************************/
+
+// only extern variables are allowed in header
+
+
+
+#endif /* _NL2_NL1_STRUCT_H */
+
diff --git a/common/interface/modem/mt6297/common/nr/external/5g/nrrc_nl1_struct.h b/common/interface/modem/mt6297/common/nr/external/5g/nrrc_nl1_struct.h
new file mode 100644
index 0000000..80abd76
--- /dev/null
+++ b/common/interface/modem/mt6297/common/nr/external/5g/nrrc_nl1_struct.h
@@ -0,0 +1,7000 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * nrrc_nl1_struct.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ * Messages and common definitions for NRRC - NL1 interface
+ *
+ * Note: See NRRC - NL1 SAP Design Specification for details.
+ *
+ * Author:
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 14 2022 bingking.li
+ * [MOLY00801474] ¡¾½Ó¿ÚÐèÇó¡¿-ÓÅѡСÇøÊÍ·ÅÕýʽpatch°üº¬NR+LTE
+ *
+ * .
+ *
+ * 06 17 2022 bingking.li
+ * [MOLY00778775] NR->NRºÍNR->LTEÇл»ÓÅ»¯Âñµãµ¼ÈëM80
+ *
+ * 06 15 2022 golden.yang
+ * [MOLY00804069] [FOCUS][4N SQC-Lite][W2204][Gen97][MT6855][Pavie][S0][5G][SA][CTC][FT][1st Round][Hangzhou][N78][HW][LiveNW][TC-MF_IOTFT-02010]
+ *
+ * .
+ * nrrc_nl1 Struct change
+ *
+ * 05 27 2022 kiwi.zhang
+ * [MOLY00856678] [ZM32][VZW test] modem crash on MOLY.NR15.R3.MD700.MP.V39.P20
+ *
+ * .
+ *
+ * 05 10 2022 tina.ma
+ * [MOLY00715364] [Bwb210616-162]?????1????????LTE?SA???????
+ *
+ * .
+ *
+ * 04 28 2022 serena.xing
+ * [MOLY00807313] [MOTO][Austin]How to customize NR band SCS capability from Modem?
+ *
+ * 04 15 2022 gavin.zhang
+ * [MOLY00681329] 1546071?21041??network??????DVT??????????????????SA????CMCC+CU?SA?+IMS??2????MT??3???????3/50?
+ *
+ * .
+ *
+ * 02 18 2022 dayang.liu
+ * [MOLY00776084] [Clone from ALPS05822944 to check in N2L part]vivo SA weak signal optimization requirement
+ *
+ * .
+ *
+ * 02 11 2022 dayang.liu
+ * [MOLY00673985] ?21041??SA?????????a2-Threshold??
+ *
+ * .
+ *
+ * 02 10 2022 tina.ma
+ * [MOLY00802929] [Colgin][Lab]Control plane RRC Connection Setup Latency Optimization
+ *
+ * .
+ *
+ * 01 25 2022 yanfeng.xu
+ * [MOLY00673839] ?21041??SA?????????q-RxLevMin/q-QualMin???
+ *
+ * 01 24 2022 dayang.liu
+ * [MOLY00685316] ???????? ??A3/A4/A5 ?????????????SA cell?????????.
+ *
+ * 01 17 2022 dayang.liu
+ * [MOLY00713183] NR->NR?NR->LTE????
+ *
+ * MD700 NL1.
+ *
+ * 01 14 2022 tom.wu
+ * [MOLY00714329] [MT6833][Palmer][SQC][S migration][CMCC][DT][8.20.20.10][PCT][5GMM][SA][N41][TCID:7.1.1.1.3] Test Case Fail
+ *
+ * .
+ *
+ * 01 12 2022 kiwi.zhang
+ * [MOLY00734793] [MT6877][Montrose][Joint Test][IODT][SA][CTC][FT][LiveNW][BWP][Beijing][HW][Xicheng District][CTC-FT-JT-BWP-1.1.4][1st Round]Always EE,Externel (EE),0,0,99,/data/vendor/core/,1,modem,[ASSERT] file:mcu/interface/service/asn1_common/asn_common.c line:835
+ *
+ * .merge cl:18794084
+ *
+ * 01 12 2022 tina.ma
+ * [MOLY00746116] [Gen97][4N SQC-Lite][W2144][W2148][MT6893][Petrus-P][R3][S0][SQC excluded][Internal][India][Delhi][SIM1:VI][SIM2: VI][LiveNW][MTI-MTS] [Fatal error(ASSERT_CUSTOM_ADDR)] err_code1:0x00000053 err_code2:0x9148C900 err_code3:0x902A6AB4
+ *
+ * [MOLY00693870] [Gen99] EVDO removal development
+ *
+ * .
+ *
+ * 01 07 2022 tom.wu
+ * [MOLY00684482] [MT6893][Petrus-P][Performance Test][SA][CT][Guangzhou][6.3.1 TC-FPET-01003][21H1 CT Chip Benchmark]Petrus-P Call fail
+ *
+ * .
+ *
+ * 10 18 2021 sean.han
+ * [MOLY00572177] Bar cell????
+ *
+ * .
+ *
+ * 07 27 2021 aric.chiu
+ * [MOLY00661485] [Gen97][Gemini] SA+SA measurement sharing
+ *
+ * [MOLY00661485]
+ * measurement sharing interface (NR15.R3.MD700.MP) (SWRD)
+ * [EWSP0000285664]
+ *
+ * 04 29 2021 dayang.liu
+ * [MOLY00648096] [By FAST][Auto][MT6833][Palmer][R0][R3][India][Delhi][In-house][Basic][MDST][Amarisoft][MTI-MTS][Gen 97][4N SQC-Lite][W2116][SIM1:00101][SIM2:IND-JIO][SWIFT_STRESS][ASSERT] file:mcu/protocol/as_multimode/rsva/rsvas/src/rsvas_utils.c line:299
+ *
+ * .
+ *
+ * 03 23 2021 sean.han
+ * [MOLY00576678] ???????SA??????
+ *
+ * .
+ *
+ * 03 17 2021 tina.ma
+ * [MOLY00619309] [MT6853][Mouton][IODT][Huawei][Lab][SH][NSA][SUL][N78+N80]NSA SUL UE not response reconfig complete when attach on SUL
+ *
+ * .
+ *
+ * 03 16 2021 tina.ma
+ * [MOLY00625293] [MT6853][Mouton][IODT][Huawei][Lab][SH][SA][N28_700M_VOICE][UL CG]UE tx power abnormal when NW not configure p0-nominalwithoutgrant
+ *
+ * .
+ *
+ * 12 21 2020 dayang.liu
+ * [MOLY00588181] [M80] ????AT&T lwm2m??????????object????Srxlev??????????????????????
+ * MD700 yanfeng.
+ *
+ * 11 10 2020 helen.hsieh
+ * [MOLY00589182] [Gen97][MP7][Memory reduction] Stage V - LTE POS preempt LTE/NR HARQ buffer
+ *
+ * .
+ *
+ * 10 22 2020 wayne-wc.chen
+ * [MOLY00574622] [Gen97][Gemini][DSDA] SA autonomous 2T/1T switch feature
+ *
+ * [R3.MP] Gemini mode update - RSVAS/NRRC/NL1 interface (SWRD)
+ *
+ * 09 30 2020 helen.hsieh
+ * [MOLY00524739] SA ¥\¯Óɬ¤Æ±µ¤f»Ý¨D??
+ *
+ * .
+ *
+ * 09 23 2020 gary.liu
+ * [MOLY00567882] [MT6875][Margaux][Q0][MP6][SQC][Globe][WW FT][Philippines][Manila][IMS][VoLTE][5GMM][NSA][TCID: FREE_TEST][Moving] EE ASSERT after power up in 5G Area
+ *
+ * refine EDNC release flow to make NL1 release first
+ *
+ * 09 18 2020 dayang.liu
+ * [MOLY00554348] [Colgin] cell measure and white cell lock feature development
+ * .
+ *
+ * 09 18 2020 yi-han.chung
+ * [MOLY00568855] [Gen97] VzW SA Data Retry Implementation
+ *
+ * VGMM-NRRC and NRRC-NL1 interface (nrrc_msgid.h, nrrc_nl1_struct.h)
+ *
+ * 09 10 2020 gary.liu
+ * [MOLY00557983] [IODT][MT6875][Margaux][Q0][MP6][SQC][CMCC][PCT][5GMM][SA][N41][DT][8.20.10.20][TCID:7.1.1.2.4] Test Case Fail
+ *
+ * add disable_nl1_early_terminate
+ *
+ * 09 07 2020 david.tang
+ * [MOLY00560914] interface - nrrc report cgi notify
+ *
+ * 08 28 2020 gary.liu
+ * [MOLY00557933] [MT6873][MT6875][Margaux][MP6][NR][Full Stack][RRM][CMX500][SA_n41A, TC 0.1.1.3.A-1] PUSCH CRC fail because beta offset is wrong
+ *
+ * remove beta valid flag
+ * [EWSP0000146066]
+ *
+ * 08 18 2020 gary.liu
+ * [MOLY00555440] [Blocking][MT6873][Margaux][MP6][IODT][Huawei][Lab][Shanghai][SA][SUL][R3 Official] UE abnormal after receive reconfiguration during attach
+ * add serving_cell_config_applied in nl1_carrier_info_ul_struct
+ * [EWSP0000143840]
+ *
+ * 08 10 2020 gary.liu
+ * [MOLY00548902] [Blocking issue][MT6885][Petrus][MP6][SQC][IODT][Huawei][Lab][Shanghai][SRS CC Switch]The N78C DL Tput is only 800M when UE report SRS CC switch capability
+ *
+ * add field to check UL CC precisely
+ * [EWSP0000137436]
+ *
+ * 07 20 2020 tero.miettinen
+ * [MOLY00517264] ????????Framework??????sample code
+ *
+ * 07 17 2020 lorenz.lin
+ * [MOLY00520469] [5G] Add MISC (0x0A) / LTE fallback Message (0x62).
+ * [MEAS]ENDC deactivation enhancement (SWRD).
+ *
+ * 07 17 2020 meng-hsuan.lin
+ * [MOLY00534361] ¡i19420¡j¡iUK¡j¡iEE¡j¡iFT¡j¡iEVT¡jDUT can't always stay on NR while activating small data in the background
+ *
+ * .[CSR] header change for auto gap[EWSP0000133337]
+ *
+ * 06 30 2020 tim.lu
+ * [MOLY00535029] [Gen97][MP5] NR-SA mode sniffer type 1 submit R3 CR
+ * DSP sniffer development
+ *
+ * 06 29 2020 yi-han.chung
+ * [MOLY00534637] [Gen97] EM/ICD check in for DMF feature
+ *
+ * interface for first PWS
+ *
+ * 06 19 2020 tim.lu
+ * [MOLY00534712] [MT6853][Mouton][MT6190][R3][MP5][Q0][SQC][China][Shantou][5GMM][NSA][Internal][FT][NSA Self-Cer][TCID:NSA_Self-Cer_FT_02_002][CU+CMCC][error times:1][Fatal error(MPU_NOT_ALLOW)] err_code1:0x0000001D err_code2:0x90CE30BE err_code3:0x29D0DF20
+ * [EWSP0000125162]NRRC-NL1 interface
+ *
+ * 06 12 2020 gary.liu
+ * [MOLY00530609] ¥Ó?patch¡G¦bMT6885¥¥x¤W¡A¦bALPS04856680ªº?ªG¤W¼W¥[5G¨î¦¡
+ * [R3]
+ * add central frequency and bandwidth
+ *
+ * 05 19 2020 tim.lu
+ * [MOLY00522503] [MT6885][Petrus][SQC][MP3][HQ][SA][5G RTD][SA_DL_Joint_CA]Modem warning : [1][MOD_NL1] nr_rx_dspcmd_ext_csif_dl.c #1086
+ * [EWSP0000112628]Uplink Tx direct current report
+ *
+ * 05 12 2020 sh.pan
+ * [MOLY00520112] [WW FT][MT6873][Margaux][Q0][MP2][SQC][VDF][FT][UK][London][NSA][TCID:Free Test]MTK speed test cannot dispaly RSSI value
+ *
+ * .
+ *
+ * 05 11 2020 gary.liu
+ * [MOLY00517839] [Pre sanity][MT6875][Margaux][CI0 Sanity][NR15.R3.MP][SA_NSA][2020-04-26] MODEM WARNING = [1705] ltxhwctrl.c #3259
+ * (1) srs port number in nl1_carrier_info_ul_bwp_struct
+ * (2) remove sn_change
+ * (3) remove transaction id
+ * [EWSP0000111502]
+ *
+ * 05 11 2020 gary.liu
+ * [MOLY00517839] [Pre sanity][MT6875][Margaux][CI0 Sanity][NR15.R3.MP][SA_NSA][2020-04-26] MODEM WARNING = [1705] ltxhwctrl.c #3259
+ * SAP update
+ * (1) srs port number in nl1_carrier_info_ul_bwp_struct
+ * (2) remove sn_change
+ * (3) remove transaction id
+ * [EWSP0000111502]
+ *
+ * 05 07 2020 tim.lu
+ * [MOLY00514833] [MT6873][Petrus][MP2][IODT][Huawei][Lab][Shanghai][NSA][SUL][Basic Function]SUL ON SA,[core3,vpe2,tc4(vpe11)] Assert fail: nr_tx_pusch_mac_h.c 834 - (LISR)NL1 DCI L2 Gen TB
+ * [EWSP0000108599]pusch & pdsch config common valid.
+ *
+ * 04 30 2020 jung-ching.hsieh
+ * [MOLY00518552] [MT6875][Margaux][NR][MP5][ML1S][SMW][CM] Fatal Error (0x1d, 0x90f60c1c, 0x27173cc4) - NL1MOB, Caller Address: 0x90f60c1c Product: NR15
+ *
+ * [MOLY00518552][MT6875][Margaux][NR][MP5][ML1S][SMW][CM] Fatal Error (0x1d, 0x90f60c1c, 0x27173cc4) - NL1MOB, Caller Address: 0x90f60c1c Product: NR15[EWSP0000107332]
+ *
+ * 04 07 2020 gary.liu
+ * [MOLY00510229] [MT6875][Margaux][CI0 Sanity][VMOLY.0316.DEV][2020-04-02_2130] ASSERT = [1][core0,vpe0,tc0(vpe0)] Assert fail: nr_rfcc_rfdb.c 2637 0x91c526e8 0x0 0x0 - NL1 _
+ * (1) add SMTC reference cell (2) add serving_cell_config_applied
+ *
+ * [EWSP0000098279]
+ * [EWSP0000099738]
+ *
+ * 04 01 2020 jutta.liuska
+ * [MOLY00505210] [MT6885][Petrus][MP2][IODT][Huawei][Lab][Shanghai][SA][CA]UE do not response ReconfigurationComplete message after network reconfigure sCell
+ * Removed ul_config_valid from nl1_serving_cell_config_idle_struct
+ *
+ * 03 18 2020 gary.liu
+ * [MOLY00504941] [MT6875][Margaux][Q0][MP3][SQC][CTC][5G][FT][China][Shenzhen][SA]Modem Warning: +EWARNING: [1][1724] nr_txdfe.c #1906;
+ * add peer sim info
+ * [EWSP0000091532]
+ *
+ * 03 17 2020 jung-ching.hsieh
+ * [MOLY00500200][MT6885][Petrus][MP1][IODT][Ericsson][FOA][Suzhou][SA]4G5 redirection problem analysis [EWSP0000091580]
+ *
+ * 02 07 2020 plum.tseng
+ * [MOLY00496701] [VMOLY][ERRC&NRRC][Capability] Gemini status sync between ERRC&NRRC
+ *
+ * (OA) add SBP_GEMINI_REPORT_FULL_CAPABILITY.
+ *
+ * 02 07 2020 chiaoyi.hu
+ * [MOLY00463911] [NL1][RFD] modify path of mcu/dsp common header file (phase2) - SWRD/VMOLY - [EWSP0000081151]
+ *
+ * 12 09 2019 jutta.liuska
+ * [MOLY00448654] [6297][NRRC] Implementation for VoNR capabilities and enhancements
+ * VoNR enhancements to NRRC_NL1_CONNECTED_CONFIG_REQ and NRRC_NL1_IDLE_CONFIG_REQ
+ *
+ * 12 09 2019 gary.liu
+ * [MOLY00463840] [Gen97] ENDC band combination capability check
+ * ENDC band check dev
+ * [EWSP0000066378]
+ *
+ * 12 09 2019 lawrence.chen
+ * [MOLY00442131]Non-cell defining header refine to support multiple next SSB and skip range.
+ * [EWSP0000067456]
+ *
+ * 12 06 2019 elle.sun
+ * [MOLY00463908] [NL1MOB] early camping lost and UT coverage
+ *
+ * [NRRC NL1] early camping lost.
+ *
+ * 12 04 2019 jutta.liuska
+ * [MOLY00448654] [6297][NRRC] Implementation for VoNR capabilities and enhancements
+ * VoNR enhancements, added NRRC_NL1_VONR_STATUS_REQ/CNF
+ *
+ * 12 04 2019 modulo.lin
+ * [MOLY00441289] [VMOLY][GNSS] NL1 development
+ * [EWSP0000064888][SWRD] GNSS IF
+ *
+ * 12 04 2019 modulo.lin
+ * [MOLY00441289] [VMOLY][GNSS] NL1 development
+ * GNSS IF
+ *
+ * 12 03 2019 yi-han.chung
+ * [MOLY00449577] [MT6297][NRRC] IDLE development
+ *
+ * OA domain files
+ *
+ * 11 22 2019 jutta.liuska
+ * [MOLY00460560] [IODT][MT6885][Petrus][MP1][ZTE][Lab][5GSM][China][Xian][F60]Assert fail: Line 1984 Code 0x1ff 0x0 0x0 Filename: coresonic/msonic/modem/slm/nr/nr_ctrl/src/nr_slm_ctrl.c
+ * Correction for position in burst
+ *
+ * 11 04 2019 gary.liu
+ * [MOLY00456998] [FT Focus][MT6885][Petrus][MP1][SQC][FDD_FT][5GMM][BJ][HUAWEI][NSA][CU CCP][TCID:7.6.1][DSP-MSONIC0] [EX-1] Assert fail: Line 413 Code 0x0 0x0 0x0 Filename: coresonic/msonic/modem/tx/nr/tx/src/nr_tx_database
+ * Added pucch_config_common_valid [EWSP0000057369]
+ *
+ * 10 11 2019 jutta.liuska
+ * [MOLY00448647] [6297][NRRC] Too small size for NRRC_NL1_CONNECTED_CONFIG_REQ trace
+ * Improvements to CONNECTED_CONFIG_REQ tracing
+ *
+ * 09 26 2019 gary.liu
+ * [MOLY00443062] [Gemini] SA+L DR-DSDS/DSDA
+ * [GEMINI] DS-DR-DA dev
+ *
+ * 09 26 2019 gary.liu
+ * [MOLY00443062] [Gemini] SA+L DR-DSDS/DSDA
+ * [GEMINI] DS-DR-DA dev
+ *
+ * 09 24 2019 po-yu.huang
+ * [MOLY00441807] [MT6297][CBRS]NR Channel lock
+ *
+ * NRRC/NL1 interface
+ *
+ * 09 24 2019 tsung-ming.lee
+ * [MOLY00442663] [Gen97][NR][NSA][SA] NBR_CELL_INFO report
+ *
+ * -nl1 msg id.
+ *
+ * 09 18 2019 modulo.lin
+ * [MOLY00441289] [VMOLY][GNSS] NL1 development
+ * [SWRD][NL1] Add GNSS msg id (EWSP0000044271)
+ *
+ * 09 18 2019 pc.chou
+ * [MOLY00438888] [Gen97][NR] Special HO.
+ *
+ * [EWSP0000043334][NL1][CTRL] Add nrrc interf.
+ *
+ * 09 11 2019 david.tang
+ * [MOLY00439289] [NR][SAP] upgrade NRRC-NL1 SAP to v37.18
+ * .[EWSP0000039414 / EWSP0000041730][NR] SAP update to v37.18 (2019JUN)
+ *
+ * 09 11 2019 sh.pan
+ * [MOLY00437977] [Gen97][NR] Connected PLMN List with trick NW release
+ *
+ * .Connected plmn list add special_report in report_ind - interface
+ *
+ * 09 11 2019 po-yu.huang
+ * [MOLY00438411] [Gen97][MEAS] 3GPP 2019 MAR/JUN Spec upgrade
+ *
+ * .
+ *
+ * 09 06 2019 shao-kai.hsu
+ * [MOLY00435743] [Gen97][MPC][CSR] Remove unused NRRC NL1 SAP
+ * . [EWSP0000039182]
+ *
+ * 09 03 2019 po-yu.huang
+ * [MOLY00434747] [Gen97] NRRC MEAS trace peer display enhancement
+ *
+ * .
+ *
+ * 08 19 2019 lawrence.chen
+ * [MOLY00432786] NRRC_NL1_CONNECTED_CONFIGUE_REQ handle with pointer way
+ *
+ * Support new NRRC_NL1_CONNECTED_CONFIG_REQ ilm in ML1S.[EWSP0000034951]
+ *
+ * 08 19 2019 lawrence.chen
+ * [MOLY00432786] NRRC_NL1_CONNECTED_CONFIGUE_REQ handle with pointer way
+ * Support new NRRC_NL1_CONNECTED_CONFIG_REQ ilm in ML1S.[EWSP0000034951]
+ *
+ * 08 15 2019 jung-ching.hsieh
+ * [MOLY00428281] [0724Patched][TOP Issue][MT6297][Apollo][IODT][MP1][ZTE][FT][5GSM][China][Guangzhou][CMRI][NSA]08/02_i??i??i??i??i??}i??i??_10.3/10.4_MCGi??Oi??i??/SCGi??i??? KPI Check
+ * NRRC interface for reporting dev[EWSP0000033919]
+ *
+ * 08 15 2019 elle.sun
+ * [MOLY00427072] [Gen97][NSA] Deactivate ENDC feature
+ *
+ * QA part (MEAS/NL1MOB).
+ *
+ * 08 09 2019 jutta.liuska
+ * [MOLY00414048] [MT6297][Apollo][IODT][MP0.5][Huawei][FT][5GSM][China][Hangzhou][CMRI][NSA][Log Inspection][10.8 NSA?LTE only????-??(mobility: NSA/LTE only switch)]@0615@???_NSA handover to LTE succeed 8 times;reest 12 times;LTE to NSA all reest
+ * Increased metadata buffer size
+ *
+ * 08 08 2019 gary.liu
+ * [MOLY00374407] [VMOLY][NL1 CTRL][GEMINI][DEV]
+ *
+ * DR RFDB dev
+ * [EWSP0000031797]
+ *
+ * 08 08 2019 david.tang
+ * [MOLY00429023] [NR][SAP] update NRRC-NL1 SAP to v37.0
+ * .[EWSP0000032004][NR][SAP] update NRRC-NL1 SAP to v37.0
+ *
+ * 06 20 2019 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * V35.0 update
+ * [EWSP0000019345]
+ *
+ * 06 19 2019 charles.hsu
+ * [MOLY00411320] [xL1SIM] Support dynamic allocation for sub-struct pointer in primitive data
+ * [xL1SIM]Fix the struct naming by mapping to MSG ID name[EWSP0000018939].
+ *
+ * 06 06 2019 jutta.liuska
+ * [MOLY00393223] [6297][NRRC] Additional implementation for basic feature set
+ * Added metadata to NRRC_NL1_CONNECTED_CONFIG_REQ message for tracing purposes
+ *
+ * 06 04 2019 charles.hsu
+ * [MOLY00411320] [xL1SIM] Support dynamic allocation for sub-struct pointer in primitive data
+ * [xL1SIM] Support dynamic allocation for sub-struct pointer in primitive data. [EWSP0000014904]
+ *
+ * 06 04 2019 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * add nrrc_nl1_cell_info_ind
+ * [EWSP0000014945]
+ *
+ * 05 30 2019 gary.liu
+ * [MOLY00402003] [VMOLY] GEMINI N+L DSDS
+ * Gemini DEV
+ * [EWSP0000013838]
+ *
+ * 05 23 2019 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * add skipUplinkTxDynamc
+ * [EWSP0000011946]
+ *
+ * 05 08 2019 gary.liu
+ * [MOLY00374407] [VMOLY][NL1 CTRL][GEMINI][DEV]
+ * add gemini interface
+ * [EWSP0000008546]
+ * [[Sanity DailyCBr][MT6297][VMOLY][2019-05-07][2100] Sanity Test Result : Pass]
+ *
+ * 05 08 2019 pc.chou
+ * [MOLY00395411] [NR][NL1] General development. [EWSP0000009188] Update NRRC_NL1_CONFIG_REQ to have dynamic arrays with flag = __CONNECTED_CONFIG_POINTER__.
+ *
+ * 04 26 2019 jung-ching.hsieh
+ * [MOLY00361582] 97 MPC New Files
+ * specific_meas_fix
+ *
+ * 04 26 2019 jung-ching.hsieh
+ * [MOLY00361582] 97 MPC New Files
+ * specific_meas_handle [EWSP0000007006]
+ *
+ * 04 18 2019 meng-hsuan.lin
+ * [MOLY00400273] [Gen97][NRRC][SEARCH]Remove "To be removed" fields in NRRC-NL1 interface
+ *
+ * .[EWSP0000005503]
+ *
+ * 04 11 2019 hyper.wang
+ * [MOLY00395830] [MT6297][Apollo][PreSQC][MP0.5][FT][India][Delhi][Vodafone][5GMM][SIM1][FDD][MDST][Auto][TTL] [1][core2,vpe0,tc0(vpe6)] Fatal Error (0x844, 0x2a4c69b8, 0xcccccccc) - NRRC (EWSP0000003631)
+ *
+ * .
+ *
+ * 03 20 2019 gary.liu
+ * [MOLY00391112] [GEN97][VMOLY][NR][SPEC] SAP migration 2018-DEC version
+ * change compile option [EWSP0000001836]
+ *
+ * 03 20 2019 gary.liu
+ * [MOLY00391112] [GEN97][VMOLY][NR][SPEC] SAP migration 2018-DEC version
+ *
+ * change define 2018-DEC for DSP
+ * [EWSP0000001836]
+ *
+ * 03 18 2019 gary.liu
+ * [MOLY00391112] [GEN97][VMOLY][NR][SPEC] SAP migration 2018-DEC version
+ * update to v26.0 + 2018DEC channel management part [ ERS00031550 ]
+ *
+ * 03 13 2019 kuan-ting.lee
+ * [MOLY00389020] [Top issue][MT6297][Phone Call][NSA FullStack][Huawei MWC Demo][Shanghai][5G]Fatal Error (0x1d, 0x90a296ae, 0x90a296a4) - NL1MOB, Caller Address: 0x90a296ae
+ * Add speed_state_scale_factors.[ERS00031248]
+ *
+ * 03 12 2019 mickey.chang
+ * [MOLY00377021] [Gen97][NL1][CTRL]
+ * roll back.
+ *
+ * 03 05 2019 jack.chu
+ * [MOLY00388632] [MT6297][TOP Issue][CMCC][NSIOT][IODT][HQ][KS][N41][SA][TC1.1] RA fail
+ *
+ * .
+ *
+ * 02 12 2019 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .NRRC-NL1 interface renaming
+ *
+ * 01 29 2019 kun-hao.yeh
+ * [MOLY00312152] 97 MPC New Files
+ * [7287760][ERS00028598]: Code Base + ERS ID
+ * redirection\reestablish development
+ *
+ * 01 24 2019 gary.liu
+ * [MOLY00373938] [MT6297][Phone Call][SA FullStack][KS] SSB_BW=BWP_BW
+ * add kssb to BCCH_IND
+ * [ERS00028479]
+ *
+ * 01 19 2019 hyper.wang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development: Change NRRC/NL1 SAP (ERS00027984)
+ *
+ * .
+ *
+ * 01 16 2019 hyper.wang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development (ERS00027563)
+ *
+ * .
+ *
+ * 01 15 2019 hyper.wang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development (ERS00027543)
+ *
+ * .
+ *
+ * 01 11 2019 tereasa.huang
+ * [MOLY00363450] [6297][NRRC] MEAS development
+ * [NRRC][MEAS] RCGI (OA domain).
+ *
+ * 01 10 2019 pc.chou
+ * [MOLY00359240] [NR][NL1] General development. [ERS00027134] Add bcch_cnf nrrc/nl1 interface.
+ *
+ * 01 10 2019 kun-hao.yeh
+ * [MOLY00312152] 97 MPC New Files
+ * [7151675][ERS00027105]: Code Base + ERS ID
+ * redirect + reestablishment SAP v1 finalize
+ *
+ * 01 07 2019 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * Reduce memory in MSG_ID_NRRC_NL1_SCG_FAIL_MEAS_REPORT_CNF
+ *
+ * 01 01 2019 hyper.wang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * [MOLY00350599] [NL1] Development
+ * Change SAP of PS_REQ and CCS_REQ (ERS00026340)
+ * .
+ *
+ * 12 24 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * add GEMINI interface
+ * [ERS00025818]
+ *
+ * 11 28 2018 tereasa.huang
+ * [MOLY00363450] [6297][NRRC] MEAS development
+ * [MEAS] SA dev (OA domain).
+ *
+ * 11 28 2018 hyper.wang
+ * [MOLY00350599] [NL1] Development (ERS00023240)
+ * Change pbch_measurement_enable to measurement_enable in CCS_REQ
+ *
+ * 11 26 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * change interface for slot format combinations
+ *
+ * 11 23 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * add more BCCH interface
+ * [ERS00022868 ]
+ *
+ * 11 21 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * remove dl_frequency_info_idle_struct and replace by dl_frequency_info_struct
+ * [ERS00022324 ]
+ *
+ * 11 20 2018 hyper.wang
+ * [MOLY00350599] [NL1] Development (ERS00022368)
+ * Add new fields in NRRC/NL1 SAP
+ *
+ * 11 17 2018 hyper.wang
+ * [MOLY00350599] [NL1] Development (ERS00022124)
+ * Add new fields in SAP
+ *
+ * 11 16 2018 yi-han.chung
+ * [MOLY00346944] [Gen97][NRRC] IDLE development
+ *
+ * interface of redirect_meas
+ *
+ * 11 16 2018 otto.liu
+ * [MOLY00361682] [Gen97][ERRC-CEL] SA CBr3 Merge to VMOLY.FPGA.SEP.DEV
+ *
+ * .
+ *
+ * 11 15 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * fix nl1_nr_time_struct
+ * [ERS00021936 ]
+ *
+ * 11 14 2018 lawrence.chen
+ * [MOLY00336299] nl1 code change for ml1s
+ * Refine the partial ilm length.
+ *
+ * 11 13 2018 otto.liu
+ * [MOLY00361682] [Gen97][ERRC-CEL] SA CBr3 Merge to VMOLY.FPGA.SEP.DEV
+ *
+ * NL1 Paging Porting
+ *
+ * 11 07 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * MOdify measurement define value
+ *
+ * 11 06 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * add virtaul mode BACKGROUND_BCCH
+ *
+ * 11 06 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * add virtaul mode BCCH
+ *
+ * 10 31 2018 tereasa.huang
+ * [MOLY00361742] [NRRC][MEAS] CBr3 to VMOLY.FPGA.SEP.DEV
+ * [NRRC][MEAS] Update sap to fix build error.
+ *
+ * 10 31 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * fix build error
+ *
+ * 10 30 2018 chih-chien.lin
+ * [MOLY00361633] [Gen97][NL1-MOB] SA CBr3 Merge to VMOLY.FPGA.SEP.DEV
+ * resel_in_nl1(interface)
+ *
+ * 10 30 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * merge SAP V14.0
+ *
+ * 10 29 2018 jack.chu
+ * [MOLY00361637] [NRRC][SI] CBr3 to VMOLY.FPGA.SEP.DEV
+ *
+ * NRRC-NL1 SAP
+ *
+ * 10 29 2018 ming.shen
+ * [MOLY00361599] [NRRC][BACKGROUND] CBr3 to VMOLY.FPGA.SEP.DEV - others
+ *
+ * 10 18 2018 lawrence.chen
+ * [MOLY00358265] [6297][NR][ML1S][Debugging][CONN-TX_01] Test case failed @ waiting for MSG_ID_CONNECTED_CONFIG_CNF since MSG_ID_CONNECTED_CONFIG_REQ is not injected
+ * Change partial connected config ilm size.
+ *
+ * 10 17 2018 lawrence.chen
+ * [MOLY00358265] [6297][NR][ML1S][Debugging][CONN-TX_01] Test case failed @ waiting for MSG_ID_CONNECTED_CONFIG_CNF since MSG_ID_CONNECTED_CONFIG_REQ is not injected
+ * ML1S large message refine .
+ *
+ * 10 17 2018 gary.liu
+ * [MOLY00348017] [VMOLY][xl1sim]
+ * add transaction id in connected_config_req [ERS00017972]
+ *
+ * 10 09 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * [ERS00016803]change BWP num define
+ *
+ * 10 02 2018 johnny.chiang
+ * [MOLY00330334] [UMOLYE] 97 NR META Development
+ *
+ * .cbr to Vmoly patch back
+ *
+ * 09 28 2018 chialin.wu
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * .use EXT CSIF to declare TX DB
+ *
+ * 09 27 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ * .PBCH for CSR
+ *
+ * 09 21 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * fix SAP
+ *
+ * 09 21 2018 gary.liu
+ * [MOLY00353380] [VMOLY][GEN97][NR] NRRC_NL1 SAP upgrade to V11.2
+ * update SAP to V11.2
+ *
+ * 09 20 2018 kuan-ting.lee
+ * [MOLY00312152] 97 MPC New Files
+ * 1 EN-DC gap config update.
+ * 2. NR scg intra measurement should not scheduled in gap from lte
+ * 3. NRRC NL1 interface fixed
+ *
+ * 09 10 2018 jung-ching.hsieh
+ * [MOLY00312152] 97 MPC New Files
+ * VMOLY_COMM_FILE
+ *
+ * 09 06 2018 gary.liu
+ * [MOLY00350973] [VMOLY][NL1 CTRL][DEV]
+ * [MOLY00348017] [VMOLY][xl1sim]
+ *
+ * update SAP
+ *
+ * 08 30 2018 pei-xuan.qiu
+ * [MOLY00349204] [6297][NL1] CSR development
+ * merge from 97DEV CL6260680, CL6259521, CL6233704, CL6232733, CL6224932, CL6218816 and CL6202232
+ *
+ * 08 30 2018 gary.liu
+ * [MOLY00348952] [Gen97]June Version ASN.1 migration patch back
+ * update nrrc nl1 struct from f10 to f20
+ *
+ * 08 30 2018 lawrence.chen
+ * [MOLY00336299] nl1 code change for ml1s
+ * Sync to Gen97 Dev.
+ *
+ * 08 30 2018 kun-hao.yeh
+ * [MOLY00312152] 97 MPC New Files
+ * rx pbch sync
+ *
+ * 08 28 2018 kuan-ting.lee
+ * [MOLY00312152] 97 MPC New Files
+ * Add reselection parameters..
+ *
+ * 08 28 2018 yulern.chu
+ * [MOLY00309990] [Gen97][EL1D] FWK development
+ * [NR] create nl1_comm_internal_inter_core_public.h (part I)
+ *
+ * 08 27 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * remove compile option after nrrc_nl1_struct is resolved
+ *
+ * 08 27 2018 chialin.wu
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * .update random_access_req/ random_access_cnf
+ *
+ * 08 20 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ * patch back
+ *
+ * 08 20 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * coding style modification
+ *
+ * 08 20 2018 chih-chien.lin
+ * [MOLY00346970] [NR][NL1] NRRC-NL1 Interface
+ * Modify size of LTE/NR exclude list
+ *
+ * 08 17 2018 kuan-ting.lee
+ * [MOLY00312152] 97 MPC New Files
+ * add redirect interface.
+ *
+ * 08 17 2018 gary.liu
+ * [MOLY00324237] [UMOLYE][GEN97][DEV][NL1] development
+ * [NRRC NL1 SAP] remove compile option for msg size too large issue
+ *
+ * 08 14 2018 johnny.chiang
+ * [MOLY00330334] [UMOLYE] 97 NR META Development
+ *
+ * .
+ *
+ * 08 14 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .update NRRC-NL1 interface
+ *
+ * 08 14 2018 johnny.chiang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .
+ *
+ * 08 13 2018 lawrence.chen
+ * [MOLY00336299] nl1 code change for ml1s
+ * Partial ilm message handle for ML1S.
+ *
+ * 08 10 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * [nr_ctrl][dev]
+ * 1. bwp rf cfg chng
+ * 2. update dc_type in nl1 status api
+ * 3. add trace
+ *
+ * 08 09 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * update NRRC-NL1 interface
+ *
+ * 08 08 2018 elle.sun
+ * [MOLY00330398] [6297][NRRC] MEAS development - GTEST
+ *
+ * 1. header separation in nr_mpc_mob_meas_context.h
+ * 2. migration from CBr W1827p2_NL1MOB (till CL6059208).
+ * a. add gtest files for nl1 mob
+ * b. nl1 mob bug fix and xl1 sim warning fix
+ * c. nrrc meas mofification for nl1 mob gtest
+ * d. nrrc meas case fix and add nrrc meas case
+ * e. reomve option __NL1MOB_CSI_RS__ in nl1 mob.
+ * f. modify nrrc meas cases with new msg api.
+ *
+ * 08 03 2018 fox.yang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * mCore migration, fix MoDIS build error
+ *
+ * 08 03 2018 fox.yang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * mCore migration
+ *
+ * 08 01 2018 makoto.chang
+ * [MOLY00334051] [UMOLYE]Add trace for schduler
+ *
+ * 07 31 2018 fox.yang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * rollback CL 6074288
+ *
+ * 07 24 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_ctrl development
+ *
+ * [nr_ctrl][dev]
+ * 1. rlm config in ctrl task
+ *
+ * 07 24 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * [nr_ctrl][dev]
+ * 1. rlm config in ctrl task
+ *
+ * 07 23 2018 gary.liu
+ * [MOLY00318009] [UMOLYE][xl1sim] development
+ * [NL1] RRC_L1_SAP update
+ *
+ * 07 20 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) fix SIB enum value.
+ *
+ * 07 20 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) seamless switch -RX PART1.
+ *
+ * 07 17 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ *
+ * (UMOLYE.97.DEV) SAP fix.
+ *
+ * 07 17 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) SAP fix.
+ *
+ * 07 17 2018 aric.chiu
+ * [MOLY00314614] [UMOLYE][TRUNK][UMOLYE][NL1_MPC]
+ * [nrrc-nl1] update gap config according to sap.
+ *
+ * 07 17 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ * Fix
+ * 1. coding convention
+ * 2. typo in NL1_MPC_COMM_MOB_Cell_Result_From_Cell_Beam_Consolidate
+ * 3. Change NL1MOB_MEAS_RESULT_INVALID to NL1MOB_MEAS_RESULT_S16_INVALID with kal_int16 conversion
+ *
+ * 07 10 2018 aric.chiu
+ * [MOLY00314614] [UMOLYE][TRUNK][UMOLYE][NL1_MPC]
+ * add cell reselection and camping lost according to nrrc-nl1 sap.
+ *
+ * 07 06 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ *
+ * NRRC MEAS message size reduction and NL1MOB code check-in
+ *
+ * 07 06 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) RRC-L1 interface fix.
+ *
+ * 07 05 2018 gary.liu
+ * [MOLY00318009] [UMOLYE][xl1sim] development
+ *
+ * [xl1sim] patch for ILM size too large (connected_cfg_req)
+ *
+ * 07 03 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) temp define.
+ *
+ * 07 03 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) 1.scell RFDB/RCT/RRC config part 2. 2. NRRC-NL1 struct fix
+ *
+ * 07 02 2018 yulern.chu
+ * [MOLY00309235] [NL1] FWK development
+ * [NL1][xl1sim] change NONE definition
+ *
+ * 07 02 2018 yulern.chu
+ * [MOLY00336467] [NL1] remove the duplicated definition for rrc
+ * [NL1] add inlcude path for nrrc_nl1_struct.h
+ *
+ * 06 29 2018 mars.chang
+ * [MOLY00331434] [MT6297] NL1TST Common modify
+ *
+ * 1st NL1TST check in
+ *
+ * 06 29 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) SAP fix.
+ *
+ * 06 27 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) rrc-l1 interface change (v4.1).
+ *
+ * 06 27 2018 johnny.chiang
+ * [MOLY00330334] [UMOLYE] 97 NR META Development
+ *
+ * .seamless switch xl1sim test case
+ *
+ * 06 25 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * [MOLY00312192]
+ * ps dev patch back - 0622
+ *
+>>>> ORIGINAL //UMOLYE/DEV/UMOLYE.GEN97.DEV/mcu/interface/l1/nl1/5g/nrrc_nl1_struct.h#49
+==== THEIRS //UMOLYE/DEV/UMOLYE.GEN97.DEV/mcu/interface/l1/nl1/5g/nrrc_nl1_struct.h#51
+ * 06 25 2018 johnny.chiang
+ * [MOLY00330334] [UMOLYE] 97 NR META Development
+ *
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .fix build error
+ *
+ * 06 25 2018 johnny.chiang
+ * [MOLY00330334] [UMOLYE] 97 NR META Development
+ *
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .fix build error
+ *
+ * 06 25 2018 johnny.chiang
+==== YOURS //ws_meng-hsuan.lin_MTKSWAWT212_105/UMOLYE/DEV/UMOLYE.GEN97.DEV/mcu/interface/l1/nl1/5g/nrrc_nl1_struct.h
+ * 06 22 2018 meng-hsuan.lin
+<<<<
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .crb to official branch patch back
+ *
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * [MOLY00312192]
+ * ps dev patch back
+ *
+ * 06 20 2018 hannu.huusko
+ * [MOLY00334179] [Gen97][KS-IODT][5G][R15_ENDC_ATT_3_1] Divide by zero in nl1_tx_ra_nmac_preamble_resource_selection() line 184.
+ * [UESIM] Remove MCG config from NRRC_NL1_CONNECTED_CONFIG_REQ
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: NO]
+ * [Group CL list: 5845994]
+ *
+ * 06 20 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * [nr_ctrl][dev]
+ * 1. bcch crc ng
+ * 2. wait bmp
+ * 3. fix csr abort rpt handle
+ * 4. bcch idle state fix ==> due to wait_si_bmp set sequence wrong
+ *
+ * 06 19 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * SAP fix.
+ *
+ * 06 19 2018 johnny.chiang
+ * [MOLY00330334] [UMOLYE] 97 NR META Development
+ *
+ * .
+ *
+ * 06 11 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) RRC SAP fix.
+ *
+ * 06 09 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * fix element size in rach_config_dedicated and fix SRS PER_SET typo
+ *
+ * 06 08 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * [MOLY00312192]
+ * ps dev patch back
+ *
+ * 06 08 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * [nr_ctrl][dev]
+ * 1. modify ch_chng for idle_config, conn_config
+ *
+ * 06 07 2018 johnny.chiang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .add narfcn for ccs ind
+ *
+ * 06 04 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV)SAP BCCH update.
+ *
+ * 06 04 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) RRC-L1 idle SAP update.
+ *
+ * 06 04 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) 1 RRC reconfig. flow 2. SAP update.
+ *
+ * 06 01 2018 ali.su
+ * [MOLY00330385] SAP interface
+ * (UMOLYE.97.DEV) update to SAP 0.31.
+ *
+ * 05 31 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * [MOLY00312192]
+ * .97 PS patch back
+ *
+ * 05 31 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV)1. mapping RMSI BW/FREQ. 2. SCS in SCS
+ *
+ * 05 31 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * . Update according to latest SAP
+ *
+ * 05 29 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) use xl1sim to enable some rrc-l1struct.
+ *
+ * 05 29 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * [MOLY00312192]
+ * power scan rename
+ *
+ * 05 29 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * 1. Update nl1_meas_config_struct and nrrc_nl1_meas_report_ind_struct based on new SAP
+ * 2. update nrrc_meas_get_nl1_config_para()
+ * 3. update nrrc_meas_del_meas_id_update()
+ * 4. update TODO in nrrc_meas_scg_meas_get_fail_meas_report_req_handler()
+ *
+ * 05 28 2018 chialin.wu
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * .update srs code
+ *
+ * 05 28 2018 johnny.chiang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .
+ *
+ * 05 28 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) 1. SCS command 2. RFCC/DL_CHNG update 3. location and bandwidth mapping 4. IDLE_CONFIG_REQ handling.
+ *
+ * 05 22 2018 yu-chun.chen
+ * [MOLY00327043] [6297][NL1] L1 TX development
+ * sync with 5648422/5650504
+ *
+ * 05 22 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_ctrl development
+ *
+ * [nr_ctrl][dev]
+ * 1. scs prepare cmd in next_flow
+ * 2. stop bcch
+ *
+ * 05 22 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_ctrl development
+ *
+ * [nr_ctrl][dev]
+ * 1. scs prepare cmd in next_flow
+ * 2. stop bcch
+ *
+ * 05 15 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * [nr_ctrl][dev]
+ * bcch modification - part 2
+ *
+ * 05 14 2018 meng-hsuan.lin
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .rrc ind
+ *
+ * 05 14 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * temp to reduce size
+ *
+ * 05 13 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * update TX part structure
+ *
+ * 05 13 2018 johnny.chiang
+ * [MOLY00312192] [UMOLYA] 97 CSR Development
+ *
+ * .
+ *
+ * 05 10 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) fix struct.
+ *
+ * 05 09 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * update TX part RRC config
+ *
+ * 05 09 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * refine idle_config_req related definition
+ *
+ * 05 09 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE.97.DEV) include official nrrc_nl1_struct.h.
+ *
+ * 05 08 2018 ali.su
+ * [MOLY00318700] [6297][NL1] L1 RX Scheduler development
+ * (UMOLYE_97_DEV) update nrrc_nl1_connected_config_req.
+ *
+ * 05 08 2018 yr.chiang
+ * [MOLY00317721] [6297][NR] L1 TX dev.
+ * refine nrrc_nl1_struct definition
+ *
+ * 05 08 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * fix target build error: decrease connect_config size
+ *
+ * 05 08 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * fix merge error - re-definition
+ *
+ * 05 08 2018 andy-me.chiang
+ * [MOLY00320746] [NR][NL1][CTRL] ctrl_task development
+ * merge from yu-chun's CBr: CL 5589256
+ *
+ * 05 08 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * .
+ *
+ * 05 08 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * .Temp solution for too big size of NRRC_NL1_CONNECTED_CONFIG_REQ
+ *
+ * 05 08 2018 sam.tsai
+ * [MOLY00316475] [6297][NRRC] MEAS development
+ * .
+ *
+ * 05 02 2018 antti.kaisto
+ * [MOLY00309859] [6297][NRRC] CONFIG module EN-DC implementation
+ * NRRC CONFIG: Some message sending functions enabled. (GEN97.DEV)
+ *
+ * 04 27 2018 claud.li
+ * [MOLY00316750] [6297][NRRC] SCG development
+ * [SCG] SCG DEV basic procedures (Gen97 DEV)
+ *
+ * 04 26 2018 hannu.huusko
+ * [MOLY00308815] [6297][NRRC] MAIN module implementation
+ * [NRRC-NL1] Empty set RAT and deactivate structure definitions
+ *
+ * 03 27 2018 sakari.niemela
+ * [MOLY00309859] [6297][NRRC] CONFIG module EN-DC implementation
+ * Introduced Channel Configuration structures in NRRC - NL1 interface
+ *
+ ****************************************************************************/
+
+#ifndef _NRRC_NL1_STRUCT_H
+#define _NRRC_NL1_STRUCT_H
+
+// TEMP for build 2018DEC:
+// 1. Need to remove when upgrade to SAP 37.18 done.
+// 2. Remove the usage of USE_VER_XXXXXXX
+// check spec version
+#if defined(__MSONIC__)
+ #undef MD_SPEC_2018SEP
+ #define MD_SPEC_2018SEP 0
+ #undef MD_SPEC_2018DEC
+ #define MD_SPEC_2018DEC 1
+ #undef MD_SPEC_2019JUN
+ #define MD_SPEC_2019JUN 2
+
+ #undef CUR_MD_SPEC
+ #if defined(__NR_3GPP_SPEC_2019JUN__)
+ #define USE_VER_2019JUN
+ #define CUR_MD_SPEC 2
+ #elif defined(__NR_3GPP_SPEC_2018DEC__)
+ #define USE_VER_2018DEC
+ #define CUR_MD_SPEC 1
+ #elif defined(__NR_3GPP_SPEC_2018SEP__)
+ #define USE_VER_2018SEP
+ #define CUR_MD_SPEC 0
+ #endif
+#else
+ #if(CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ #define USE_VER_2019JUN
+ #elif(CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ #define USE_VER_2018DEC
+ #else
+ #define USE_VER_2018SEP
+ #endif
+#endif
+// end-TEMP for build 2018DEC
+
+#include "../../../../../external/ps_inter_core_public.h"
+#include "../custom/nl1_comm_inter_core_public.h"
+#include "../custom/nl1_comm_inter_core_wrapper_general_type.h"
+#include "../custom/nl1_comm_inter_core_ue_capability.h"
+/********************************************
+ * 1. Common Structures and Enumerations *
+ ********************************************/
+
+// needs to be removed onece ALL NL1 modules have removed this in their code
+typedef enum
+{
+ NL1_SUBCARRIER_SPACING_15_KHZ,
+ NL1_SUBCARRIER_SPACING_30_KHZ,
+ NL1_SUBCARRIER_SPACING_60_KHZ,
+ NL1_SUBCARRIER_SPACING_120_KHZ,
+ NL1_SUBCARRIER_SPACING_240_KHZ
+} nl1_subcarrier_spacing_enum;
+
+typedef struct
+{
+ kal_uint32 dl_arfcn;
+ kal_uint16 frequency_band;
+} nl1_nr_dl_freq_struct;
+
+typedef struct
+{
+ kal_uint16 dl_frequency_band; // value: 1~1024.
+ kal_uint32 ssb_arfcn;
+ kal_uint16 pci;
+ NR_SCS_TYPE_E subcarrier_spacing_ssb;
+} nl1_nr_cell_struct;
+
+typedef struct
+{
+ kal_uint32 dl_earfcn;
+ kal_uint16 pci;
+} nl1_lte_cell_struct;
+
+typedef struct
+{
+ kal_uint16 systemFrameNumber; // Target SF of the cell.
+ kal_uint8 subFrameNumber; // Target SFN of the cell.
+} nl1_nr_time_struct;
+
+/********************************************
+ * 2. Set RAT *
+ ********************************************/
+
+/* MSG_ID_NRRC_NL1_SET_RAT_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_rf_on;
+ kal_bool is_active_rat;
+ kal_uint8 supported_rats_bitmap; // bit1: LTE, bit2: WCDMA, bit3: TDSCDMA, bit4: GSM.
+} nrrc_nl1_set_rat_req_struct;
+
+/* MSG_ID_NRRC_NL1_SET_RAT_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_set_rat_cnf_struct;
+
+/********************************************
+ * 3. Cell Search *
+ ********************************************/
+
+
+/********************************************
+ * 4. System Information Reception *
+ ********************************************/
+#define NRRC_NL1_MAX_SI_MESSAGE 32
+#define NRRC_NL1_MAX_SI_RAW_DATA_LENGTH_BYTE 372 // TBD
+#define NRRC_NL1_CGI_LIST_SIZE 12
+#define NRRC_NL1_CGI_CELL_ID_ARRAY_SIZE 5
+#ifndef UNIT_TEST
+#define NRRC_NL1_MAX_NR_BAR_LIST_FREQ_NUM (8)
+#define NRRC_NL1_MAX_NR_BAR_LIST_CELL_NUM (16)
+#else
+#define NRRC_NL1_MAX_NR_BAR_LIST_FREQ_NUM (4)
+#define NRRC_NL1_MAX_NR_BAR_LIST_CELL_NUM (6)
+#endif
+
+typedef enum
+{
+ NL1_SI_RECEPTION_COMMAND_START =0,
+ NL1_SI_RECEPTION_COMMAND_STOP =1
+} nl1_si_reception_command_enum;
+
+typedef enum
+{
+ NL1_REQUESTED_SI_MIB =1,
+ NL1_REQUESTED_SI_SIB1 =2,
+ NL1_REQUESTED_SI_MIB_SIB1 =3,
+ NL1_REQUESTED_SI_SI_MESSAGES =4,
+ NL1_REQUESTED_SI_MIB_SI_MESSAGES =5,
+ NL1_REQUESTED_SI_SIB1_SI_MESSAGES =6,
+ NL1_REQUESTED_SI_MIB_SIB1_SI_MESSAGES =7
+} nl1_requested_si_enum;
+
+typedef enum
+{
+ NL1_SI_PERIODICITY_RF8 =0,
+ NL1_SI_PERIODICITY_RF16 =1,
+ NL1_SI_PERIODICITY_RF32 =2,
+ NL1_SI_PERIODICITY_RF64 =3,
+ NL1_SI_PERIODICITY_RF128 =4,
+ NL1_SI_PERIODICITY_RF256 =5,
+ NL1_SI_PERIODICITY_RF512 =6
+} nl1_si_periodicity_enum;
+
+typedef enum
+{
+ NL1_SI_TYPE_SI_1 =0,
+ NL1_SI_TYPE_SI_2 =1,
+ NL1_SI_TYPE_SI_3 =2,
+ NL1_SI_TYPE_SI_4 =3,
+ NL1_SI_TYPE_SI_5 =4,
+ NL1_SI_TYPE_SI_6 =5,
+ NL1_SI_TYPE_SI_7 =6,
+ NL1_SI_TYPE_SI_8 =7,
+ NL1_SI_TYPE_SI_9 =8,
+ NL1_SI_TYPE_SI_10 =9,
+ NL1_SI_TYPE_SI_11 =10,
+ NL1_SI_TYPE_SI_12 =11,
+ NL1_SI_TYPE_SI_13 =12,
+ NL1_SI_TYPE_SI_14 =13,
+ NL1_SI_TYPE_SI_15 =14,
+ NL1_SI_TYPE_SI_16 =15,
+ NL1_SI_TYPE_SI_17 =16,
+ NL1_SI_TYPE_SI_18 =17,
+ NL1_SI_TYPE_SI_19 =18,
+ NL1_SI_TYPE_SI_20 =19,
+ NL1_SI_TYPE_SI_21 =20,
+ NL1_SI_TYPE_SI_22 =21,
+ NL1_SI_TYPE_SI_23 =22,
+ NL1_SI_TYPE_SI_24 =23,
+ NL1_SI_TYPE_SI_25 =24,
+ NL1_SI_TYPE_SI_26 =25,
+ NL1_SI_TYPE_SI_27 =26,
+ NL1_SI_TYPE_SI_28 =27,
+ NL1_SI_TYPE_SI_29 =28,
+ NL1_SI_TYPE_SI_30 =29,
+ NL1_SI_TYPE_SI_31 =30,
+ NL1_SI_TYPE_SI_32 =31,
+ NL1_SI_TYPE_SI_33 =32, // reflects to SIB1, only used in NRRc_NL1_BCCH_IND.
+ NL1_SI_TYPE_SI_SIB1 = NL1_SI_TYPE_SI_33, // reflects to SIB1, only used in Ctrl task internal.
+ NL1_SI_TYPE_SI_MIB =33 // reflects to MIB, only used in Ctrl task internal.
+} nl1_si_type_enum;
+
+typedef enum
+{
+ NL1_SUB_CARRIER_SPACING_COMMON_INVALID =0,
+ NL1_SUB_CARRIER_SPACING_COMMON_SCS15OR60 =1,
+ NL1_SUB_CARRIER_SPACING_COMMON_SCS30OR120 =2
+} nl1_subcarrier_spacing_common_enum;
+
+typedef enum
+{
+ NL1_DMRS_TYPE_A_POSITION_2 = 0,
+ NL1_DMRS_TYPE_A_POSITION_3 = 1
+} nl1_dmrs_type_a_position_enum;
+
+typedef enum
+{
+ NRRC_CELL_BARRED_INVALID =0,
+ NRRC_CELL_BARRED_BARRED =1,
+ NRRC_CELL_BARRED_NOTBARRED =2
+} nrrc_cell_barred_enum;
+
+typedef enum
+{
+ NRRC_INTRA_FREQ_RESELECTION_INVALID =0,
+ NRRC_INTRA_FREQ_RESELECTION_ALLOWED =1,
+ NRRC_INTRA_FREQ_RESELECTION_NOTALLOWED =2
+} nrrc_intra_freq_reselection_enum;
+
+typedef enum
+{
+ NL1_CELL_RESEL_PRIORITY_LOWEST = 0,
+ NL1_CELL_RESEL_PRIORITY_0 = 1,
+ NL1_CELL_RESEL_PRIORITY_0_DOT_2 = 2,
+ NL1_CELL_RESEL_PRIORITY_0_DOT_4 = 3,
+ NL1_CELL_RESEL_PRIORITY_0_DOT_6 = 4,
+ NL1_CELL_RESEL_PRIORITY_0_DOT_8 = 5,
+ NL1_CELL_RESEL_PRIORITY_1 = 6,
+ NL1_CELL_RESEL_PRIORITY_1_DOT_2 = 7,
+ NL1_CELL_RESEL_PRIORITY_1_DOT_4 = 8,
+ NL1_CELL_RESEL_PRIORITY_1_DOT_6 = 9,
+ NL1_CELL_RESEL_PRIORITY_1_DOT_8 = 10,
+ NL1_CELL_RESEL_PRIORITY_2 = 11,
+ NL1_CELL_RESEL_PRIORITY_2_DOT_2 = 12,
+ NL1_CELL_RESEL_PRIORITY_2_DOT_4 = 13,
+ NL1_CELL_RESEL_PRIORITY_2_DOT_6 = 14,
+ NL1_CELL_RESEL_PRIORITY_2_DOT_8 = 15,
+ NL1_CELL_RESEL_PRIORITY_3 = 16,
+ NL1_CELL_RESEL_PRIORITY_3_DOT_2 = 17,
+ NL1_CELL_RESEL_PRIORITY_3_DOT_4 = 18,
+ NL1_CELL_RESEL_PRIORITY_3_DOT_6 = 19,
+ NL1_CELL_RESEL_PRIORITY_3_DOT_8 = 20,
+ NL1_CELL_RESEL_PRIORITY_4 = 21,
+ NL1_CELL_RESEL_PRIORITY_4_DOT_2 = 22,
+ NL1_CELL_RESEL_PRIORITY_4_DOT_4 = 23,
+ NL1_CELL_RESEL_PRIORITY_4_DOT_6 = 24,
+ NL1_CELL_RESEL_PRIORITY_4_DOT_8 = 25,
+ NL1_CELL_RESEL_PRIORITY_5 = 26,
+ NL1_CELL_RESEL_PRIORITY_5_DOT_2 = 27,
+ NL1_CELL_RESEL_PRIORITY_5_DOT_4 = 28,
+ NL1_CELL_RESEL_PRIORITY_5_DOT_6 = 29,
+ NL1_CELL_RESEL_PRIORITY_5_DOT_8 = 30,
+ NL1_CELL_RESEL_PRIORITY_6 = 31,
+ NL1_CELL_RESEL_PRIORITY_6_DOT_2 = 32,
+ NL1_CELL_RESEL_PRIORITY_6_DOT_4 = 33,
+ NL1_CELL_RESEL_PRIORITY_6_DOT_6 = 34,
+ NL1_CELL_RESEL_PRIORITY_6_DOT_8 = 35,
+ NL1_CELL_RESEL_PRIORITY_7 = 36,
+ NL1_CELL_RESEL_PRIORITY_7_DOT_2 = 37,
+ NL1_CELL_RESEL_PRIORITY_7_DOT_4 = 38,
+ NL1_CELL_RESEL_PRIORITY_7_DOT_6 = 39,
+ NL1_CELL_RESEL_PRIORITY_7_DOT_8 = 40,
+ NL1_CELL_RESEL_PRIORITY_HIGHEST = 41 // For LTE_PREFER
+} nl1_cell_resel_priority_enum;
+
+typedef enum
+{
+ NL1_SPEED_STATE_SCALE_FACTOR_0_DOT_25 = 0,
+ NL1_SPEED_STATE_SCALE_FACTOR_0_DOT_5 = 1,
+ NL1_SPEED_STATE_SCALE_FACTOR_0_DOT_75 = 2,
+ NL1_SPEED_STATE_SCALE_FACTOR_1_DOT_0 = 3
+} nl1_speed_state_scale_factor_enum;
+
+typedef enum
+{
+ NL1_REPORT_CONFIG_REPORT_TYPE_PERIODICAL = 0,
+ NL1_REPORT_CONFIG_REPORT_TYPE_EVENT = 1,
+ NL1_REPORT_CONFIG_REPORT_TYPE_REPORT_CGI = 2
+} nl1_report_config_report_type_enum;
+
+typedef enum
+{
+ NL1_REPORT_CONFIG_INTER_RAT_EVENT_ID_B1 = 0,
+ NL1_REPORT_CONFIG_INTER_RAT_EVENT_ID_B2 = 1
+} nl1_report_config_inter_rat_event_id_enum;
+
+typedef enum
+{
+ NL1_BCCH_RECV_LOW_PRIORITY = 0,
+ NL1_BCCH_RECV_HIGH_PRIORITY = 1
+}nl1_bcch_receiving_priority_enum;
+
+typedef enum
+{
+ NL1_BCCH_RECV_SUCCESS = 0,
+ NL1_BCCH_RECV_CRCNG = 1,
+ NL1_BCCH_RECV_NO_SIB1 = 2,
+ NL1_BCCH_RECV_GEMINI_GAP_NOT_ALLOW = 3,
+ NL1_BCCH_RECV_MIB_SHARING_NOT_SUPPORT = 4
+}nl1_bcch_receiving_result_enum;
+
+typedef enum
+{
+ NL1_NON_CELL_DEFINING_SSB_TYPE_INVALID = 0,
+ NL1_NON_CELL_DEFINING_SSB_TYPE_NEXT_SSB = 1,
+ NL1_NON_CELL_DEFINING_SSB_TYPE_SKIP_FREQ_RANGE = 2,
+}nl1_non_cell_defining_ssb_info_type_enum;
+
+typedef enum{
+ NL1_SPECIAL_REPORT_NONE = 0,
+ NL1_SPECIAL_REPORT_FAKEA2 = 1
+}nl1_special_report_enum;
+
+typedef enum{
+ NL1_GEMINI_SHARE_OFF,
+ NL1_GEMINI_SHARE_ON_DIFF_ARFCN,
+ NL1_GEMINI_SHARE_ON_SAME_ARFCN_DIFF_PCI,
+ NL1_GEMINI_SHARE_ON_SAME_ARFCN_SAME_PCI
+}nl1_gemini_share_enum;
+
+typedef enum
+{
+ NL1_RX_SCHED_GAP_TYPE_NON_AUTO_GAP,
+ NL1_RX_SCHED_GAP_TYPE_AUTO_GAP
+} nl1_rx_sched_gap_type_enum;
+
+typedef struct
+{
+ kal_uint32 begin;
+ kal_uint32 end;
+} nl1_freq_range_struct;
+
+typedef union
+{
+ kal_uint32 next_ssb;
+ nl1_freq_range_struct skip_freq_range;
+}nl1_non_cell_defining_ssb_info_union;
+
+typedef struct
+{
+ kal_uint8 control_resource_set_zero;
+ kal_uint8 search_space_zero;
+} nl1_pdcch_config_sib1_struct;
+
+typedef struct
+{
+ nl1_si_periodicity_enum si_periodicity;
+ nl1_si_type_enum si_type;
+ kal_bool keep_receiving;
+ kal_bool is_sib9;
+ kal_bool is_first_sib6_sib7_sib8;
+} nl1_si_message_scheduling_info_struct;
+
+typedef struct
+{
+ kal_uint8 scheduling_info_num;
+ nl1_si_message_scheduling_info_struct scheduling_info_list[NRRC_NL1_MAX_SI_MESSAGE];
+ kal_uint16 si_window_length;
+} nl1_si_scheduling_info_struct;
+
+typedef struct
+{
+ kal_uint8 systemFrameNumber;
+ nl1_subcarrier_spacing_common_enum subcarrierSpacingCommon;
+ kal_uint8 ssb_SubcarrierOffset;
+ nl1_dmrs_type_a_position_enum dmrs_TypeA_position;
+ nl1_pdcch_config_sib1_struct pdcch_ConfigSIB1;
+ nrrc_cell_barred_enum cellBarred;
+ nrrc_intra_freq_reselection_enum intraFreqReselection;
+ kal_bool spare;
+ /* Kssb is not part of MIB but it is used in to the calculation of reference point A
+ * e.g. See nrrc_config_l1l2_handle_frequency_info_dl_sib() for details */
+ kal_uint8 kssb;
+} nl1_mib_data_struct;
+
+typedef struct
+{
+ kal_uint8 mcc_1; // range: 0 ~ 9
+ kal_uint8 mcc_2; // range: 0 ~ 9
+ kal_uint8 mcc_3; // range: 0 ~ 9
+ kal_uint8 mnc_1; // range: 0 ~ 9
+ kal_uint8 mnc_2; // range: 0 ~ 9
+ kal_bool mnc3_valid; // valid flag for mnc_3
+ kal_uint8 mnc_3; // range: 0 ~ 9
+} nl1_plmn_id_struct;
+
+typedef struct
+{
+ nl1_plmn_id_struct plmn_id;
+ kal_uint8 cell_identity[NRRC_NL1_CGI_CELL_ID_ARRAY_SIZE]; // cell identity is bit string of 36 bits. The MSB of cell_identity[0] is the first bit, and so no.
+} nl1_cgi_struct;
+
+typedef struct
+{
+ kal_uint8 cgi_num; // range: 1~NRRC_NL1_CGI_LIST_SIZE
+ nl1_cgi_struct cgi_list[NRRC_NL1_CGI_LIST_SIZE];
+} nl1_cgi_info_struct;
+
+typedef struct
+{
+ kal_uint32 frc;
+ kal_uint64 scnt;
+ nl1_nr_time_struct cell_time;
+} nl1_sib9_time_struct;
+
+/* MSG_ID_NRRC_NL1_BCCH_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_si_reception_command_enum command;
+ nl1_nr_cell_struct cell;
+ kal_uint8 tid;
+ nl1_requested_si_enum requested_system_information;
+ nl1_si_scheduling_info_struct si_scheduling_info;
+ nl1_bcch_receiving_priority_enum bcch_receiving_priority;
+ kal_uint16 limit_si_rx_len;
+ kal_uint16 limit_si_rx_period;
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ nl1_rx_sched_gap_type_enum gap_type;
+#endif
+ kal_bool disable_nl1_early_terminate;
+} nrrc_nl1_bcch_req_struct;
+
+/* MSG_ID_NRRC_NL1_BCCH_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+ nl1_bcch_receiving_result_enum bcch_rcv_result;
+ kal_bool is_ssb_info_valid;
+ nl1_non_cell_defining_ssb_info_type_enum non_cell_defining_ssb_info_type;
+ nl1_non_cell_defining_ssb_info_union non_cell_defining_ssb_info;
+} nrrc_nl1_bcch_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_BCCH_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_nr_cell_struct cell;
+ kal_uint8 tid;
+ kal_bool is_bch;
+ nl1_nr_time_struct receive_nr_time;
+ nl1_si_type_enum si_type;
+ nl1_mib_data_struct mib_data;
+ kal_uint8 encoded_system_information[NRRC_NL1_MAX_SI_RAW_DATA_LENGTH_BYTE]; // size TBD
+ kal_uint16 encoded_system_information_length;
+ nl1_sib9_time_struct sib9_time;
+} nrrc_nl1_bcch_ind_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_BCCH_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_si_reception_command_enum command;
+ nl1_nr_cell_struct cell;
+ kal_uint8 tid;
+ nl1_requested_si_enum requested_system_information;
+ nl1_si_scheduling_info_struct si_scheduling_info;
+ nl1_bcch_receiving_priority_enum bcch_receiving_priority;
+ kal_uint16 limit_si_rx_len;
+ kal_uint16 limit_si_rx_period;
+} nrrc_nl1_background_bcch_req_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_BCCH_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+ nl1_bcch_receiving_result_enum bcch_rcv_result;
+ kal_bool is_ssb_info_valid;
+ nl1_non_cell_defining_ssb_info_type_enum non_cell_defining_ssb_info_type;
+ nl1_non_cell_defining_ssb_info_union non_cell_defining_ssb_info;
+} nrrc_nl1_background_bcch_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_BCCH_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_nr_cell_struct cell;
+ kal_uint8 tid;
+ kal_bool is_bch;
+ nl1_nr_time_struct receive_nr_time;
+ nl1_si_type_enum si_type;
+ nl1_mib_data_struct mib_data;
+ kal_uint8 encoded_system_information[NRRC_NL1_MAX_SI_RAW_DATA_LENGTH_BYTE]; // size TBD
+ kal_uint16 encoded_system_information_length;
+} nrrc_nl1_background_bcch_ind_struct;
+
+/* MSG_ID_NRRC_NL1_SIB9_FRAME_SYNC_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_sib9_time_struct sib9_time;
+} nrrc_nl1_sib9_frame_sync_req_struct;
+
+/* MSG_ID_NRRC_NL1_SIB9_FRAME_SYNC_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_valid;
+ kal_uint64 sib9_time_diff; // valid when is_valid is TRUE. unit: micro second
+} nrrc_nl1_sib9_frame_sync_cnf_struct;
+
+/********************************************
+ * 5. Channel Configuration *
+ ********************************************/
+
+/* Constants for masking nrrc_nl1_idle_config_req_struct.reconfig_bitmap */
+#define NL1_IDLE_CONFIG_REQ_STRUCT_CONFIG_BITMAP_SERVING_CELL_CONFIG 0x00000001
+#define NL1_IDLE_CONFIG_REQ_STRUCT_CONFIG_BITMAP_MAC_CONFIG 0x00000002
+#define NL1_IDLE_CONFIG_REQ_STRUCT_CONFIG_BITMAP_CELL_RESEL_PARAMS 0x00000004
+#define NL1_IDLE_CONFIG_REQ_STRUCT_CONFIG_BITMAP_NR_EXCLUDE_LIST 0x00000008
+#define NL1_IDLE_CONFIG_REQ_STRUCT_CONFIG_BITMAP_LTE_EXCLUDE_LIST 0x00000010
+
+/* Constants for masking nrrc_nl1_connected_config_req_struct.reconfig_bitmap */
+#define NL1_CONNECTED_CONFIG_REQ_STRUCT_CONFIG_BITMAP_MCG_CONFIG 0x00000001
+#define NL1_CONNECTED_CONFIG_REQ_STRUCT_CONFIG_BITMAP_SCG_CONFIG 0x00000002
+#define NL1_CONNECTED_CONFIG_REQ_STRUCT_CONFIG_BITMAP_MEAS_CONFIG 0x00000004
+
+/* Constants for masking nl1_mcg_config_struct.reconfig_bitmap */
+#define NL1_MCG_CONFIG_STRUCT_CONFIG_BITMAP_MAC_CELL_GROUP_CONFIG 0x00000001
+#define NL1_MCG_CONFIG_STRUCT_CONFIG_BITMAP_PHYSICAL_CELL_GROUP_CONFIG 0x00000002
+#define NL1_MCG_CONFIG_STRUCT_CONFIG_BITMAP_PCELL_CONFIG 0x00000004
+#define NL1_MCG_CONFIG_STRUCT_CONFIG_BITMAP_PCCH_BCCH_CONFIG 0x00000008
+#define NL1_MCG_CONFIG_STRUCT_CONFIG_BITMAP_SCELL_CONFIG 0x00000010
+
+
+/* Constants for masking nl1_scg_config_struct.reconfig_bitmap */
+#define NL1_SCG_CONFIG_STRUCT_CONFIG_BITMAP_MAC_CELL_GROUP_CONFIG 0x00000001
+#define NL1_SCG_CONFIG_STRUCT_CONFIG_BITMAP_PHYSICAL_CELL_GROUP_CONFIG 0x00000002
+#define NL1_SCG_CONFIG_STRUCT_CONFIG_BITMAP_PSCELL_CONFIG 0x00000004
+#define NL1_SCG_CONFIG_STRUCT_CONFIG_BITMAP_SCELL_CONFIG 0x00000008
+
+/* Constants for masking nl1_primary_cell_config_struct.reconfig_bitmap */
+#define NL1_PRIMARY_CELL_CONFIG_STRUCT_CONFIG_BITMAP_SERVING_CELL_CONFIG 0x00000001
+#define NL1_PRIMARY_CELL_CONFIG_STRUCT_CONFIG_BITMAP_RLF_TIMERS_AND_CONSTANTS 0x00000002
+/*Notes:
+ * The RLM bitmap/rlmInSyncOutOfSyncThreshold is removed from SAP(37.18) because no BLER pair#1 will be used in R15.(R2-1906094)
+ * But the rlmInSyncOutOfSyncThreshold field for 2nd pair of BLER for RLM would be discussed in R16.
+ * For maintenance, keep the RLM bitmap and rlmInSyncOutOfSyncThreshold field in codes for future use.
+ */
+#define NL1_PRIMARY_CELL_CONFIG_STRUCT_CONFIG_BITMAP_RLM_IN_SYNC_OUT_OF_SYNC 0x00000004
+
+/* Constants for masking nl1_scell_config_struct.reconfig_bitmap */
+#define NL1_SCELL_CONFIG_STRUCT_CONFIG_BITMAP_SERVING_CELL_CONFIG 0x00000001
+#define NL1_SCELL_CONFIG_STRUCT_CONFIG_BITMAP_SCELL_DEACTIVATION_TIMER 0x00000002
+#define NL1_SCELL_CONFIG_STRUCT_CONFIG_BITMAP_PATHLOSS_REFERENCE_LINKING 0x00000004
+
+/* Constants for masking nl1_serving_cell_config_struct.reconfig_bitmap */
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_DL_FREQUENCY_INFO 0x00000001
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_DL_BWP_INFO 0x00000002
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_UL_CONFIG 0x00000004
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_SUL_CONFIG 0x00000008
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_BASIC_PHY_PARAMS 0x00000010
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_TDD_UL_DL_CONFIG 0x00000020
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_BWP_INACTIVITY_TIMER 0x00000040
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_PDCCH_SERVING_CELL_CONFIG 0x00000080
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_PDSCH_SERVING_CELL_CONFIG 0x00000100
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_CSI_MEAS_CONFIG 0x00000200
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_CROSS_CARRIER_SCHEDULING_CONFIG 0x00000400
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_TAG_ID 0x00000800
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+//remove definition
+#else
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_UE_BEAM_LOCK_FUNCTION 0x00001000
+#endif
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_SERVING_CELL_MEAS_OBJECT_ID 0x00002000
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_UE_SPECIFIC_BANDWIDTH_AND_LOCATION 0x00004000
+#elif (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+#define NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_UE_SPECIFIC_CARRIERS 0x00004000
+#endif
+
+
+/* Constants for masking nl1_dl_bwp_struct.reconfig_bitmap */
+#define NL1_DL_BWP_STRUCT_CONFIG_BITMAP_GENERIC_PARAMS 0x00000001
+#define NL1_DL_BWP_STRUCT_CONFIG_BITMAP_PDCCH_CONFIG 0x00000002
+#define NL1_DL_BWP_STRUCT_CONFIG_BITMAP_PDSCH_CONFIG 0x00000004
+#define NL1_DL_BWP_STRUCT_CONFIG_BITMAP_SPS_CONFIG 0x00000008
+#define NL1_DL_BWP_STRUCT_CONFIG_BITMAP_RADIO_LINK_MONITORING_CONFIG 0x00000010
+#define NL1_DL_BWP_STRUCT_CONFIG_BITMAP_ALL (NL1_DL_BWP_STRUCT_CONFIG_BITMAP_GENERIC_PARAMS | NL1_DL_BWP_STRUCT_CONFIG_BITMAP_PDCCH_CONFIG | \
+ NL1_DL_BWP_STRUCT_CONFIG_BITMAP_PDSCH_CONFIG | NL1_DL_BWP_STRUCT_CONFIG_BITMAP_SPS_CONFIG | \
+ NL1_DL_BWP_STRUCT_CONFIG_BITMAP_RADIO_LINK_MONITORING_CONFIG)
+
+/* Constants for masking nl1_ul_config_struct.reconfig_bitmap */
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_UL_FREQUENCY_INFO 0x00000001
+#else
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_UL_FREQUNCEY_INFO 0x00000001
+#endif
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_UL_BWP_INFO 0x00000002
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_PUSCH_SERVING_CELL_CONFIG 0x00000004
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_SRS_CARRIER_SWITCHING 0x00000008
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_POWER_BOOST_PI2_BPSK 0x00000010
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_UE_SPECIFIC_BANDWIDTH_AND_LOCATION 0x00000020
+#elif (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_POWER_BOOST_PI2_BPSK 0x00000010
+#define NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_UE_SPECIFIC_CARRIERS 0x00000020
+#endif
+
+
+
+/* Constants for masking nl1_ul_bwp_struct.reconfig_bitmap */
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_GENERIC_PARAMS 0x00000001
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_RACH_CONFIG 0x00000002
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_PUCCH_CONFIG 0x00000004
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_PUSCH_CONFIG 0x00000008
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_CONFIGURED_GRANT_CONFIG 0x00000010
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_SRS_CONFIG 0x00000020
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_BEAM_FAILURE_RECOVERY_CONFIG 0x00000040
+#define NL1_UL_BWP_STRUCT_CONFIG_BITMAP_ALL (NL1_UL_BWP_STRUCT_CONFIG_BITMAP_GENERIC_PARAMS | NL1_UL_BWP_STRUCT_CONFIG_BITMAP_RACH_CONFIG | \
+ NL1_UL_BWP_STRUCT_CONFIG_BITMAP_PUCCH_CONFIG | NL1_UL_BWP_STRUCT_CONFIG_BITMAP_PUSCH_CONFIG | \
+ NL1_UL_BWP_STRUCT_CONFIG_BITMAP_CONFIGURED_GRANT_CONFIG | NL1_UL_BWP_STRUCT_CONFIG_BITMAP_SRS_CONFIG | \
+ NL1_UL_BWP_STRUCT_CONFIG_BITMAP_BEAM_FAILURE_RECOVERY_CONFIG)
+
+#define NL1_MAX_SERVING_CELL_NUM 32 // maxNrofServingCells
+#define NL1_MAX_BWP_NUM 4 // maxNrofBWPs
+
+#define NL1_TDD_UL_DL_SLOT_CONFIG_ALL_DL_SYMBOLS 0xFF
+#define NL1_TDD_UL_DL_SLOT_CONFIG_ALL_UL_SYMBOLS 0xFF
+
+#define NL1_MAC_TIME_ALIGNMENT_TIMER_INFINITY 0xFFFF
+#define NL1_MAC_PHR_PERIODIC_TIMER_INFINITY 0xFFFF
+#define NL1_MAC_PHR_TX_POWER_FACTOR_CHANGE_INFINITY 0xFF
+#define NL1_RA_PREAMBLES_GROUP_B_POWER_OFFSET_MINUS_INFINITY 0xFF
+#define NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE 5
+#define NL1_ADDITIONAL_DL_BWP_LIST_SIZE 4
+#define NL1_ADDITIONAL_UL_BWP_LIST_SIZE 4
+#define NL1_SR_CONFIG_LIST_SIZE 8
+#define NL1_TA_CONFIG_LIST_SIZE 4
+#define NL1_RA_SSB_RESOURCES_LIST_SIZE 64
+#define NL1_RA_CSIRS_RESOURCES_LIST_SIZE 96
+#define NL1_RA_OCCASION_LIST_SIZE 64
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+#define NL1_PUCCH_RESOURCES_LIST_SIZE 128 // maxNrofPUCCH-Resources
+#else
+#define NL1_PUCCH_RESOURCES_LIST_SIZE 56 // maxNrofPUCCH-Resources
+#endif
+#define NL1_PUCCH_SPATIAL_RELATION_INFO_LIST_SIZE 8
+#define NL1_PUSCH_P0_ALPHASET_LIST_SIZE 30
+#define NL1_PUSCH_SRI_PUSCH_PC_LIST_SIZE 16
+#define NL1_SRS_RESOURCE_SET_LIST_SIZE 16
+#define NL1_SRS_RESOURCE_PER_SET_LIST_SIZE 16
+#define NL1_SRS_RESOURCE_LIST_SIZE 64
+#define NL1_BFR_CANDIDATE_BEAM_RS_LIST_NUM 16
+#define NL1_CSI_REPORT_CONFIG_LIST_SIZE 48
+#define NL1_SCELL_CONFIG_LIST_SIZE 1
+#define NRRC_NL1_MAX_SERVING_CELL_NUM (NL1_SCELL_CONFIG_LIST_SIZE+1) //Spec. maxNrofServingCells 32
+
+#define NL1_PUCCH_RESOURCES_PER_SET_LIST_SIZE 32 // maxNrofPUCCH-ResourcesPerSet
+#define NL1_PUCCH_P0_PER_SET_LIST_SIZE 8 // maxNrofPUCCH-P0-PerSet
+#define NL1_PUCCH_PATHLOSS_REF_RS_LIST_SIZE 4 // maxNrofPUCCH-PathlossReferenceRSs
+#define NL1_PUCCH_HOPPING_ID_BIT_STRING_LIST_SIZE 2
+#define NL1_PUCCH_RESOURCES_SET_LIST_SIZE 4 // maxNrofPUCCH-ResourceSets
+#define NL1_PUCCH_MULTI_CSI_RESOURCES_LIST_SIZE 2
+#define NL1_PUCCH_DL_DATA_TO_UL_ACK_LIST_SIZE 8
+#define NL1_PTRS_UPLINK_FREQ_DENSITY_LIST_SIZE 2
+#define NL1_PTRS_UPLINK_TIME_DENSITY_LIST_SIZE 3
+#define NL1_PTRS_UPLINK_SAMPLE_DENSITY_LIST_SIZE 5
+#define NL1_UCI_ON_PUSCH_BETA_OFFSETS_LIST_SIZE 4
+#define NL1_PUSCH_PATHLOSS_REF_RS_LIST_SIZE 4 // maxNrofPUSCH-PathlossReferenceRSs
+#define NL1_PUSCH_UL_ALLOCATION_LIST_SIZE 16 // maxNrofUL-Allocations
+#define NL1_PUSCH_FREQ_HOPPING_OFFSET_LIST_SIZE 4
+#define NL1_UL_GRANT_FREQ_DOMAIN_ALLOC_BIT_STRING_LIST_SIZE 3
+#define NL1_SRS_CC_SET_INDEX_LIST_SIZE 4
+#define NL1_TDD_UL_DL_SLOT_CONFIG_LIST_SIZE 320 // maxNrofSlots
+#define NL1_CSI_RS_MAPPING_FREQ_DOMAIN_ALLOC_BIT_STRING_LIST_SIZE 2
+#define NL1_NZP_CSI_RS_RESOURCES_PER_SET_LIST_SIZE 64 // maxNrofNZP-CSI-RS-ResourcesPerSet
+#define NL1_CSI_IM_RS_RESOURCES_PER_SET_LIST_SIZE 8 // maxNrofCSI-IM-ResourcesPerSet
+#define NL1_CSI_SSB_RESOURCES_PER_SET_LIST_SIZE 64 // maxNrofCSI-SSB-ResourcePerSet
+#define NL1_NZP_CSI_RS_RESOURCES_SET_LIST_SIZE 16 // maxNrofNZP-CSI-RS-ResourceSetsPerConfig
+#define NL1_CSI_SSB_RESOURCES_SET_LIST_SIZE 1 // maxNrofCSI-SSB-ResourceSetsPerConfig
+#define NL1_CSI_IM_RESOURCES_SET_LIST_SIZE 16 // maxNrofCSI-IM-ResourceSetsPerConfig
+#define NL1_CSI_REPORT_SPS_ON_PUSCH_SLOT_OFFSET_LIST_SIZE 16
+#define NL1_CSI_REPORT_APERIODIC_SLOT_OFFSET_LIST_SIZE 16
+#define NL1_CODEBOOK_TYPE_I_SINGLE_PANEL_SUBSET_RESTRICTION_BIT_STRING_LIST_SIZE 32
+#define NL1_CODEBOOK_TYPE_I_SINGLE_PANEL_SUBSET_RESTRICTION_I2_BIT_STRING_LIST_SIZE 2
+#define NL1_CODEBOOK_TYPE_I_MULTI_PANEL_SUBSET_RESTRICTION_BIT_STRING_LIST_SIZE 16
+#define NL1_CODEBOOK_TYPE_II_SUBSET_RESTRICTION_BIT_STRING_LIST_SIZE 18
+#define NL1_CSI_RPT_NON_PMI_PORT_INDEX_LIST_SIZE 8
+#define NL1_CSI_RPT_NON_PMI_PORT_IND_RANK_LIST_SIZE 8 // PortIndexFor8Ranks
+#define NL1_CSI_RPT_NON_PMI_PORT_INDICATION_LIST_SIZE 128 // maxNrofNZP-CSI-RS-ResourcesPerConfig
+#define NL1_CSI_RPT_SUBBANDS_BIT_STRING_LIST_SIZE 3
+#define NL1_CSI_ASSOCIATED_RPT_QCL_INFO_LIST_SIZE 16
+#define NL1_CSI_RPT_APERIODIC_TRIGGER_STATE_ASSOC_REPORT_CONFIG_INFO_LIST_SIZE 16 // maxNrofReportConfigPerAperiodicTrigger
+#define NL1_CSI_RPT_APERIODIC_TRIGGER_STATE_LIST_SIZE 128 // maxNrOfCSI-AperiodicTriggers
+#define NL1_NZP_CSI_RS_RESOURCE_LIST_SIZE 192 // maxNrofNZP-CSI-RS-Resources
+#define NL1_NZP_CSI_RS_RESOURCE_SET_LIST_SIZE 64 // maxNrofNZP-CSI-RS-ResourceSets
+#define NL1_CSI_IM_RESOURCE_LIST_SIZE 32 // maxNrofCSI-IM-Resources
+#define NL1_CSI_IM_RESOURCE_SET_LIST_SIZE 64 // maxNrofCSI-IM-ResourceSets
+#define NL1_CSI_SSB_RESOURCE_LIST_SIZE 64 // maxNrofCSI-SSB-ResourceSetsResources
+#define NL1_CSI_RESOURCE_CONFIG_LIST_SIZE 112 // maxNrofCSI-ResourceConfigurations
+#define NL1_CSI_SPS_ON_PUSCH_TRIGGER_STATE_LIST_SIZE 64 // maxNrOfSemiPersistentPUSCH-Triggers
+#define NL1_CONTROL_RESOURCE_SET_FREQ_DOMAIN_RESOURCE_BIT_STRING_LIST_SIZE 6
+#define NL1_PDCCH_TCI_STATE_LIST_SIZE 64// maxNrofTCI-StatesPDCCH
+#define NL1_CONTROL_RESOURCE_SET_PDCCH_DMRS_SCRAMB_ID_BIT_STRING_LIST_SIZE 2
+#define NL1_MONITORING_SYMBOLS_WITHIN_SLOT_BIT_STRING_LIST_SIZE 2
+#define NL1_SLOT_FORMAT_COMBINATIONS_LIST_SIZE 512
+#define NL1_COMMON_CONTROL_RESOURCE_SET_LIST_SIZE 2
+#define NL1_PDCCH_COMMON_SEARCH_SPACE_LIST_SIZE 4
+#define NL1_UE_SPECIFIC_CONTROL_RESOURCE_SET_LIST_SIZE 3
+#define NL1_UE_SPECIFIC_SEARCH_SPACE_LIST_SIZE 10
+#define NL1_PTRS_PDSCH_EPRE_RATIO_LIST_SIZE 2
+#define NL1_PTRS_DL_FREQ_DENSITY_LIST_SIZE 2
+#define NL1_PTRS_DL_TIME_DENSITY_LIST_SIZE 3
+#define NL1_DMRS_GROUP_1_BIT_STRING_LIST_SIZE 2
+#define NL1_DMRS_GROUP_2_BIT_STRING_LIST_SIZE 2
+#define NL1_RATE_MATCH_SLOT_PATTERN_LIST_SIZE 5
+#define NL1_RATE_MATCH_PATTERN_RESOURCE_BLOCK_BIT_STRING_LIST_SIZE 35
+#define NL1_RATE_MATCH_PATTERN_SYMBOLS_IN_RESOURCE_BLOCK_BIT_STRING_LIST_SIZE 4
+#define NL1_DL_ALLOCATION_LIST_SIZE 16 // maxNrofDL-Allocations
+#define NL1_TCI_STATE_LIST_SIZE 128 // NL1_PDCCH_TCI_STATE_LIST_SIZE
+#define NL1_RATE_MATCH_PATTERN_BIT_STRING_LIST_SIZE 4 // maxNrofRateMatchPatterns
+#define NL1_RATE_MATCH_PATTERN_GROUP_LIST_SIZE 8
+#define NL1_ZP_CSI_RS_RESOURCE_LIST_SIZE 32 // maxNrofZP-CSI-RS-Resources
+#define NL1_ZP_CSI_RS_RESOURCE_PER_SET_LIST_SIZE 16 // maxNrofZP-CSI-RS-ResourcespERsET
+#define NL1_ZP_CSI_RS_RESOURCE_SET_LIST_SIZE 16 // maxNrofZP-CSI-RS-Sets
+#define NL1_SSB_POSITIONS_IN_BURST_BIT_STRING_LIST_SIZE 8
+#define NL1_EUTRA_MBSFN_SUBFRAME_ALLOCATION_BIT_STRING_LIST_SIZE 3
+#define NL1_EUTRA_MBSFN_SUBFRAME_CONFIG_LIST_SIZE 8 // maxMBSFN-Allocations
+#define NL1_FAILURE_DETECTION_RESOURCE_LIST_SIZE 8
+#define NL1_SRS_CARRIER_SWITCHING_TRIGGER_LIST_SIZE 32
+#define NL1_CONNECTED_CONFIG_PARTIAL_REQ_RAW_DATA_LENGTH 16250 //65536 - 4 - 4 - 4 - 1 - (65574 i??V 65531)
+#define NL1_CSI_PUCCH_RESOURCE_LIST_SIZE 4
+#define NL1_UPLINK_TX_DIRECT_CURRENT_CELL_SIZE 32
+#define NL1_PCCH_CONFIG_FIRST_PDCCH_MONITORING_OCCASIONS_LIST_SIZE 4
+#define NL1_PCCH_CONFIG_IDLE_S_TMSI_5G_SIZE 6
+#define NL1_PCCH_CONFIG_IDLE_I_RNTI_SIZE 5
+#define NL1_SRS_TPC_PDCCH_TRIGGER_LIST_SIZE 32
+#define NL1_SRS_RESOURCE_SET_APERIODIC_SRS_RESOURCE_TRIGGER_LIST_SIZE 3
+#define NL1_SRS_TPC_PDCCH_SRS_CC_SET_INDEX_LIST_SIZE 4
+#if defined(__CONNECTED_CONFIG_POINTER__)
+#define NL1_TRACING_METADATA_SIZE 300
+#endif /* (__CONNECTED_CONFIG_POINTER__) */
+
+/********************************************
+ * 6. Cell Search and Measurement *
+ ********************************************/
+
+/*** meas_config related - Start ***/
+/* Spec. maxNrofMeasId 64 */
+#define NR_MAX_MEAS_ID_NUM 64
+
+/* Spec. maxNrofObjectId 64
+ The number of measurement object stored in NL1 can be reduced from 64 to 33:
+ - X NR intra-frequency layers
+ - Current assumption is 4 (or could be aligned to NRRC_NL1_MAX_SERVING_CELL_NUM)
+ - 16 NR inter-frequency layers
+ - The number is based on CMCC requirements from LTE experience.
+ - 13 inter-RAT carrier layers.
+ - UE should be able to measure at least 13 carrier layers based on the requirement in 38.133. */
+#define NR_MAX_MEAS_OBJECT_ID_NUM 33
+
+/* Spec. maxReportConfigId 64 */
+#define NR_MAX_REPORT_CONFIG_ID_NUM 64
+/* Spec. maxNrofPCIsPerSMTC 64 */
+#define NR_MAX_PCI_PER_SMTC 64
+/* Spec. maxNrofCSI-RS-CellsRRM 96 */
+//#define NR_MAX_CSI_RS_CELL_RRM_NUM 96
+/* Spec. maxNrofCSI-RS-ResourcesRRM 96 */
+#define NR_MAX_CSI_RS_RESOURCE_RRM_NUM 96
+
+/* Spec. maxNrofSS-BlocksToAverage 16 */
+#define NR_MAX_SS_BLOCK_TO_AVERAGE_NUM 16
+/* Spec. maxNrofCSI-RS-ResourcesToAverage 16 */
+#define NR_MAX_CSi_RS_RESOURCE_TO_AVERAGE_NUM 16
+/* Spec. maxNrofCellMeas 16 for IDLE */
+#define NR_MAX_CELL_MEAS_NUM 16
+/* Spec. maxNrofPCI-Ranges 16 for IDLE */
+#define NR_MAX_PCI_RANGE_NUM 16
+/* Spec. maxNrofCellMeas 32 for Report */
+#define NR_MAX_REPORT_CELL_MEAS_NUM 32
+/* Spec. maxNrofPCI-RangeElements 8 for Report */
+#define NR_MAX_REPORT_PCI_RANGE_NUM 8
+/* Spec. maxNrofIndexesToReport 32 */
+#define NR_MAX_INDEX_TO_REPORT_NUM 32
+/* Spec. maxNrofQuantityConfig 2 */
+#define NR_MAX_QUANTITY_CONFIG_NUM 2
+/* Spec. SSB-ToMeasure: longBitmap 64 bits */
+#define NRRC_NL1_SSB_TO_MEASURE_MAX_BYTE 8
+/* Spec. frequencyDomainAllocation row2 12 bits */
+#define NL1_MEAS_OBJECT_NR_CSI_RS_RESOURCE_FREQUENCY_DOMAIN_ALLOCATION_MAX_BYTE 2
+/* Spec. maxCellMeasEUTRA 32 */
+#define NRRC_NL1_MAX_EUTRA_CELL_MEAS_NUM 32
+/* Spec. bit number range 1..80 */
+#define NRRC_NL1_SS_RSSI_MEASUREMENT_SLOTS_MAX_BYTE 10
+
+#define NL1_MEAS_CH_LOCK_NR_MAX_NUM (32)
+
+/* Maximum number of EAS channel lock info saved in MRS */
+#define NL1_MEAS_CH_LOCK_EAS_MAX_NUM (32)
+
+#define NR_MAX_NR_NCELL_NUM 21
+#define NR_MAX_LTE_NCELL_NUM 8
+
+#define NR_IDLE_MAX_NR_FREQ_NUM (8)
+#define NR_IDLE_MAX_EUTRA_FREQ_NUM (8)
+
+
+#define NL1_S_NON_INTRA_SEARCH_P_INFINITY (0xFF)
+#define NL1_Q_QUAL_MIN_MINUS_INFINITY (0x7F)
+#define NL1_Q_OFFSET_TEMP_INFINITY (0xFF)
+
+#define NL1_MAX_REPORT_NBR_CELL_INFO_NUM (32)
+#define NRRC_NL1_CELL_INFO_IND_SERVING_MAX_BEAM_NUM (8)
+#define NRRC_NL1_CELL_INFO_IND_NEIGHBOR_MAX_BEAM_NUM (4)
+
+#define NL1_MAX_PS_FREQ_INFO_LIST_NUM (64)
+#define NL1_MAX_PS_RESULT_LIST_NUM (128)
+
+#define NL1_MAX_CCS_FREQ_INFO_LIST_NUM NL1_MAX_PS_RESULT_LIST_NUM
+#define NL1_MAX_EXCLUDED_CELL_NUM (4)
+#define NL1_MAX_DETECTED_CELL_BEAM_LIST_NUM (20)
+#define NL1_MAX_FREQ_LIST_NUM (18)
+#define NL1_MAX_MEAS_CELL_NUM (20)
+#define NL1_MAX_MEAS_CELL_BEAM_NUM (8)
+#define NL1_MAX_NR_EXCLUDE_LIST_FREQ_NUM (8)
+#define NL1_MAX_NR_EXCLUDE_LIST_CELL_NUM (16)
+#define NL1_MAX_LTE_EXCLUDE_LIST_FREQ_NUM (8)
+#define NL1_MAX_LTE_EXCLUDE_LIST_CELL_NUM (8)
+
+#define NL1_THRESHOLD_PER_BAND_LIST_MAX_BAND_NUM (9)
+
+typedef enum
+{
+ NL1_RRC_PS_CMD_START = 0,
+ NL1_RRC_PS_CMD_STOP = 1
+} nl1_ps_command_enum;
+
+typedef enum
+{
+ NL1_RRC_PS_PURPOSE_NR = 0,
+ NL1_RRC_PS_PURPOSE_NR_RSSI_SNIFFER = 1,
+ NL1_RRC_PS_PURPOSE_UMTS_LTE_NR = 2,
+ NL1_RRC_PS_PURPOSE_LTE_NR = 3,
+ NL1_RRC_PS_PURPOSE_UMTS_LTE = 4,
+ NL1_RRC_PS_PURPOSE_SPECTRUM_SENSING = 5
+} nl1_ps_purpose_enum;
+
+typedef enum
+{
+ NL1_RRC_PS_SBBW_COARSE = 0,
+ NL1_RRC_PS_SBBW_FINE = 1
+} nl1_ps_subband_width_type_enum;
+
+typedef enum
+{
+ NL1_RRC_CCS_CMD_START = 0,
+ NL1_RRC_CCS_CMD_RESUME = 1,
+ NL1_RRC_CCS_CMD_STOP = 2
+} nl1_ccs_command_enum;
+
+typedef enum
+{
+ NL1_RRC_CCS_SEARCH_SPEED_MODE = 0,
+ NL1_RRC_CCS_SEARCH_ACCURACY_MODE = 1
+}nl1_ccs_search_mode_enum;
+
+typedef enum
+{
+ NL1_RRC_CELL_DETECTED_SUSPEND = 0,
+ NL1_RRC_CELL_DETECTED = 1,
+ NL1_RRC_FREQ_RANGE_SEARCHED = 2
+} nl1_ccs_status_enum;
+
+typedef enum
+{
+ NL1_REDIR_MEAS_COMMAND_START = 0,
+ NL1_REDIR_MEAS_COMMAND_STOP = 1
+} nl1_redir_meas_command_enum;
+
+typedef enum
+{
+ NL1_REEST_MEAS_COMMAND_START = 0,
+ NL1_REEST_MEAS_COMMAND_STOP = 1
+} nl1_reest_meas_command_enum;
+
+typedef enum
+{
+ NL1_CCS_NO_PATTERN = 0,
+ NL1_CCS_PATTERN_HIGH_PRIORITY = 1,
+ NL1_CCS_PATTERN_MIDDLE_PRIORITY = 2,
+ NL1_CCS_PATTERN_LOW_PRIORITY = 3
+} nl1_ccs_virtual_pattern_priority_enum;
+
+typedef enum
+{
+ NL1_PS_NO_PATTERN = 0,
+ NL1_PS_PATTERN_HIGH_PRIORITY = 1,
+ NL1_PS_PATTERN_MIDDLE_PRIORITY = 2,
+ NL1_PS_PATTERN_LOW_PRIORITY = 3
+} nl1_ps_virtual_pattern_priority_enum;
+
+typedef enum
+{
+ NL1_PS_SCAN_MODE_SPEED_MODE = 0,
+ NL1_PS_SCAN_MODE_NORMAL_MODE = 1,
+ NL1_PS_SCAN_MODE_ACCURACY_MODE = 2
+}nl1_ps_scan_mode_enum;
+
+typedef struct
+{
+ kal_uint32 nrarfcn;
+ kal_uint16 pci;
+ kal_uint8 ssb_periodicity;
+} nl1_cell_info_struct;
+
+typedef struct
+{
+ kal_uint16 band;
+ nl1_freq_range_struct freq_range;
+} nl1_ps_freq_info_struct;
+
+typedef struct
+{
+ kal_uint16 band;
+ nl1_freq_range_struct freq_range;
+ NR_SCS_TYPE_E ssb_scs;
+ kal_uint8 smtc_1_period; // 0xFF means invalid
+ kal_uint8 smtc_2_period; // 0xFF means invalid
+} nl1_ccs_freq_info_struct;
+
+typedef struct
+{
+ kal_uint16 band;
+ kal_uint32 nrarfcn;
+ NR_SCS_TYPE_E ssb_scs;
+} nl1_freq_info_struct;
+
+
+typedef struct
+{
+ kal_uint8 periodicity;
+ kal_uint8 offset;
+} nl1_primary_ssb_mtc_periodicity_and_offset_struct;
+
+typedef struct
+{
+ nl1_primary_ssb_mtc_periodicity_and_offset_struct periodicity_and_offset;
+ kal_uint8 duration;
+} nl1_primary_ssb_mtc_struct;
+
+
+typedef struct
+{
+ kal_uint32 begin;
+ kal_uint32 end;
+ kal_int16 rssi;
+} nl1_ps_result_struct;
+
+typedef struct
+{
+ kal_uint16 band;
+ kal_uint32 nrarfcn;
+ kal_uint16 pci;
+ kal_uint8 cell_beam_index;
+ NR_SCS_TYPE_E ssb_scs;
+ kal_uint32 cs_verification_result;
+ kal_int16 ss_rsrp; // unit: QdBm
+ kal_int16 ss_rsrq; // unit: QdB
+ kal_int16 ss_sinr; // unit: QdB
+ kal_int8 pbch_quality;
+} nl1_ccs_result_struct;
+
+typedef struct
+{
+ kal_uint32 cell_beam_index;
+ kal_int16 ss_rsrp; // unit: QdBm
+ kal_int16 ss_rsrq; // unit: QdB
+ kal_int16 ss_sinr; // unit: QdB
+ kal_int8 pbch_quality;
+} nl1_cell_beam_result_struct;
+
+typedef struct
+{
+ kal_uint16 pci;
+ kal_uint8 cell_beam_num;
+ nl1_cell_beam_result_struct cell_beam[NL1_MAX_MEAS_CELL_BEAM_NUM];
+ kal_int16 ss_sinr;
+} nl1_cell_result_struct;
+
+typedef struct
+{
+ kal_uint32 narfcn;
+ NR_SCS_TYPE_E ssb_scs;
+ kal_uint64 offset;
+ kal_uint8 cell_num;
+ nl1_cell_result_struct cell[NL1_MAX_MEAS_CELL_NUM];
+} nl1_freq_result_struct;
+
+
+/* MSG_ID_NRRC_NL1_POWER_SCAN_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_ps_command_enum command;
+ kal_uint8 tid;
+ nl1_ps_virtual_pattern_priority_enum nl1_ps_pattern;
+
+ nl1_ps_purpose_enum purpose;
+ kal_uint8 interval;
+ nl1_ps_subband_width_type_enum subband_width_type;
+ kal_int16 rssi_threshold;
+ nl1_ps_scan_mode_enum scan_mode;
+ kal_uint16 freq_info_list_num;
+ nl1_ps_freq_info_struct freq_info_list[NL1_MAX_PS_FREQ_INFO_LIST_NUM];
+} nrrc_nl1_power_scan_req_struct;
+
+/* MSG_ID_NRRC_NL1_POWER_SCAN_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 power_scan_rslt_list_num;
+ nl1_ps_result_struct power_scan_rslt_list[NL1_MAX_PS_RESULT_LIST_NUM];
+ kal_uint16 band_list[NL1_MAX_PS_RESULT_LIST_NUM];
+ kal_uint8 tid;
+} nrrc_nl1_power_scan_ind_struct;
+
+/* MSG_ID_NRRC_NL1_POWER_SCAN_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 power_scan_rslt_list_num;
+ nl1_ps_result_struct power_scan_rslt_list[NL1_MAX_PS_RESULT_LIST_NUM];
+ kal_uint16 band_list[NL1_MAX_PS_RESULT_LIST_NUM];
+ kal_uint8 tid;
+} nrrc_nl1_power_scan_cnf_struct;
+
+typedef struct
+{
+ kal_uint8 next_ssb_num;
+ nl1_freq_info_struct next_ssb[NL1_MAX_DETECTED_CELL_BEAM_LIST_NUM];
+ kal_uint8 skip_freq_range_list_num;
+ nl1_freq_range_struct skip_freq_range[NL1_MAX_DETECTED_CELL_BEAM_LIST_NUM];
+}nl1_non_cell_defining_ssb_info_for_ccs_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_POWER_SCAN_REQ */
+typedef nrrc_nl1_power_scan_req_struct nrrc_nl1_background_power_scan_req_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_POWER_SCAN_IND */
+typedef nrrc_nl1_power_scan_ind_struct nrrc_nl1_background_power_scan_ind_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_POWER_SCAN_CNF */
+typedef nrrc_nl1_power_scan_cnf_struct nrrc_nl1_background_power_scan_cnf_struct;
+
+
+/* MSG_ID_NRRC_NL1_NORMAL_CONTINUOUS_CARRIER_SEARCH_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_ccs_command_enum command;
+ kal_uint8 tid;
+ nl1_ccs_virtual_pattern_priority_enum nl1_ccs_pattern;
+
+ nl1_ccs_search_mode_enum search_mode; // valid when command == START
+ kal_uint16 freq_info_list_num; // valid when command == START
+ nl1_ccs_freq_info_struct freq_info_list[NL1_MAX_CCS_FREQ_INFO_LIST_NUM]; // valid when command == START
+ kal_bool is_force_search_order; // valid when command == START
+ kal_bool is_suspend_after_cell_found; // valid when command == START
+ kal_bool measurement_enable; // valid when command == START
+ kal_uint8 report_cell_num; // valid when command == START
+
+ kal_uint8 excluded_cell_list_num; // valid when command == RESUME
+ nl1_cell_info_struct excluded_cell_list[NL1_MAX_EXCLUDED_CELL_NUM]; // valid when command == RESUME
+ nl1_non_cell_defining_ssb_info_for_ccs_struct non_cell_defining_ssb_info; // valid when command == RESUME
+ nl1_rx_sched_gap_type_enum gap_type; // Specifies if auto gaps are to be used for the search or not
+} nrrc_nl1_continuous_carrier_search_req_struct;
+
+/* MSG_ID_NRRC_NL1_NORMAL_CONTINUOUS_CARRIER_SEARCH_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_ccs_status_enum search_status;
+ kal_uint16 freq_info_list_num;
+ kal_bool is_searched_in_freq_info_list[NL1_MAX_CCS_FREQ_INFO_LIST_NUM];
+ kal_uint8 detected_cell_list_num;
+ nl1_ccs_result_struct detected_cell_list[NL1_MAX_DETECTED_CELL_BEAM_LIST_NUM];
+ kal_uint8 tid;
+} nrrc_nl1_continuous_carrier_search_ind_struct;
+
+/* MSG_ID_NRRC_NL1_NORMAL_CONTINUOUS_CARRIER_SEARCH_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 freq_info_list_num;
+ kal_bool is_searched_in_freq_info_list[NL1_MAX_CCS_FREQ_INFO_LIST_NUM];
+ kal_uint8 tid;
+} nrrc_nl1_continuous_carrier_search_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_CONTINUOUS_CARRIER_SEARCH_REQ */
+typedef nrrc_nl1_continuous_carrier_search_req_struct nrrc_nl1_background_continuous_carrier_search_req_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_CONTINUOUS_CARRIER_SEARCH_IND */
+typedef nrrc_nl1_continuous_carrier_search_ind_struct nrrc_nl1_background_continuous_carrier_search_ind_struct;
+
+/* MSG_ID_NRRC_NL1_BACKGROUND_CONTINUOUS_CARRIER_SEARCH_CNF */
+typedef nrrc_nl1_continuous_carrier_search_cnf_struct nrrc_nl1_background_continuous_carrier_search_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_ccs_freq_info_struct search_parameters;
+} nrrc_nl1_cell_detect_with_auto_gap_needed_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool auto_gaps_available; // Specifies if auto gaps are available or not.
+} nrrc_nl1_cell_detect_with_auto_gap_needed_rsp_struct;
+
+typedef enum
+{
+ NL1_MEAS_OBJECT_TYPE_INVALID,
+ NL1_MEAS_OBJECT_TYPE_NR,
+ NL1_MEAS_OBJECT_TYPE_EUTRA,
+ NL1_MEAS_OBJECT_TYPE_MAX_NUM
+} nl1_meas_object_type_enum;
+
+typedef enum
+{
+ NL1_REPORT_CONFIG_TYPE_INVALID,
+ NL1_REPORT_CONFIG_TYPE_NR,
+ NL1_REPORT_CONFIG_TYPE_INTER_RAT,
+ NL1_REPORT_CONFIG_TYPE_MAX_NUM
+} nl1_report_config_type_enum;
+
+typedef enum
+{
+ NL1_REPORT_CONFIG_NR_RS_TYPE_SSB,
+ NL1_REPORT_CONFIG_NR_RS_TYPE_CSI_RS,
+ NL1_REPORT_CONFIG_NR_RS_TYPE_MAX_NUM
+} nl1_report_config_nr_rs_type_enum;
+
+typedef enum
+{
+ NL1_REPORT_INTERVAL_MS120,
+ NL1_REPORT_INTERVAL_MS240,
+ NL1_REPORT_INTERVAL_MS480,
+ NL1_REPORT_INTERVAL_MS640,
+ NL1_REPORT_INTERVAL_MS1024,
+ NL1_REPORT_INTERVAL_MS2048,
+ NL1_REPORT_INTERVAL_MS5120,
+ NL1_REPORT_INTERVAL_MS10240,
+ NL1_REPORT_INTERVAL_MS20480,
+ NL1_REPORT_INTERVAL_MS40960,
+ NL1_REPORT_INTERVAL_MIN1,
+ NL1_REPORT_INTERVAL_MIN6,
+ NL1_REPORT_INTERVAL_MIN12,
+ NL1_REPORT_INTERVAL_MIN30,
+ NL1_REPORT_INTERVAL_MAX_NUM
+} nl1_report_interval_enum;
+
+typedef enum
+{
+ NL1_REPORT_CONFIG_TRIGGER_QUANTITY_RSRP = 0,
+ NL1_REPORT_CONFIG_TRIGGER_QUANTITY_RSRQ = 1,
+ NL1_REPORT_CONFIG_TRIGGER_QUANTITY_SINR = 2
+} nl1_report_config_trigger_quantity_enum;
+
+typedef enum
+{
+ NL1_REPORT_CONFIG_NR_EVENT_ID_A1,
+ NL1_REPORT_CONFIG_NR_EVENT_ID_A2,
+ NL1_REPORT_CONFIG_NR_EVENT_ID_A3,
+ NL1_REPORT_CONFIG_NR_EVENT_ID_A4,
+ NL1_REPORT_CONFIG_NR_EVENT_ID_A5,
+ NL1_REPORT_CONFIG_NR_EVENT_ID_A6,
+ NL1_REPORT_CONFIG_NR_EVENT_ID_MAX_NUM
+} nl1_report_config_nr_event_id_enum;
+
+typedef enum
+{
+ NL1_S_MEASURE_CONFIG_RSRP_SSB,
+ NL1_S_MEASURE_CONFIG_RSRP_CSI_RS,
+ NL1_S_MEASURE_CONFIG_RSRP_MAX_NUM
+} nl1_s_measure_config_rsrp_enum;
+
+typedef enum
+{
+ NL1_MEAS_GAP_SHARING_SCHEME_00,
+ NL1_MEAS_GAP_SHARING_SCHEME_01,
+ NL1_MEAS_GAP_SHARING_SCHEME_10,
+ NL1_MEAS_GAP_SHARING_SCHEME_11
+} nl1_meas_gap_sharing_scheme_enum;
+
+typedef enum
+{
+ NL1_EUTRA_ALLOWED_MEAS_BANDWIDTH_6 = 0,
+ NL1_EUTRA_ALLOWED_MEAS_BANDWIDTH_15 = 1,
+ NL1_EUTRA_ALLOWED_MEAS_BANDWIDTH_25 = 2,
+ NL1_EUTRA_ALLOWED_MEAS_BANDWIDTH_50 = 3,
+ NL1_EUTRA_ALLOWED_MEAS_BANDWIDTH_75 = 4,
+ NL1_EUTRA_ALLOWED_MEAS_BANDWIDTH_100 = 5
+} nl1_eutra_allowed_meas_bandwidth_enum;
+
+typedef enum
+{
+ NL1_MEAS_RESULT_NEIGH_CELLS_TYPE_INVALID = 0,
+ NL1_MEAS_RESULT_NEIGH_CELLS_TYPE_NR = 1,
+ NL1_MEAS_RESULT_NEIGH_CELLS_TYPE_EUTRA = 2
+} nl1_meas_result_neigh_cells_type_enum;
+
+typedef enum {
+ NL1_TRACE_REPORT_TYPE_PERIODICAL_NR,
+ NL1_TRACE_REPORT_TYPE_EVENT_A1,
+ NL1_TRACE_REPORT_TYPE_EVENT_A2,
+ NL1_TRACE_REPORT_TYPE_EVENT_A3,
+ NL1_TRACE_REPORT_TYPE_EVENT_A4,
+ NL1_TRACE_REPORT_TYPE_EVENT_A5,
+ NL1_TRACE_REPORT_TYPE_EVENT_A6,
+ NL1_TRACE_REPORT_TYPE_PERIODICAL_EUTRA,
+ NL1_TRACE_REPORT_TYPE_EVENT_B1,
+ NL1_TRACE_REPORT_TYPE_EVENT_B2
+} nl1_trace_report_type_enum;
+
+/*** meas_config related - End ***/
+
+typedef enum
+{
+ NL1_RADIO_LINK_MONITORING_PURPOSE_BEAM_FAILURE = 0,
+ NL1_RADIO_LINK_MONITORING_PURPOSE_RLF = 1,
+ NL1_RADIO_LINK_MONITORING_PURPOSE_BOTH = 2
+} nl1_radio_link_monitoring_purpose_enum;
+
+typedef enum
+{
+ NL1_PDSCH_HARQ_ACK_CODEBOOK_SEMI_STATIC = 0,
+ NL1_PDSCH_HARQ_ACK_CODEBOOK_DYNAMIC = 1
+} nl1_pdsch_harq_ack_codebook_enum;
+
+typedef enum
+{
+ NL1_SCELL_MODIFICATION_STATUS_NO_CHANGE = 0,
+ NL1_SCELL_MODIFICATION_STATUS_ADD = 1,
+ NL1_SCELL_MODIFICATION_STATUS_REL_AND_ADD = 2,
+ NL1_SCELL_MODIFICATION_STATUS_RECONFIG = 3
+} nl1_scell_modification_status_enum;
+
+typedef enum
+{
+ NL1_PATHLOSS_REFERENCE_LINKING_PRIMARY_CELL = 0,
+ NL1_PATHLOSS_REFERENCE_LINKING_SCELL = 1
+} nl1_pathloss_reference_linking_enum;
+
+typedef enum
+{
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_0_DOT_5_MS = 0,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_0_DOT_625_MS = 1,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_1_MS = 2,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_1_DOT_25_MS = 3,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_2_MS = 4,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_2_DOT_5_MS = 5,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_3_MS = 6,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_4_MS = 7,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_5_MS = 8,
+ NL1_DL_UL_TRANSMISSION_PERIODICITY_10_MS = 9
+} nl1_dl_ul_transmission_periodicity_enum;
+
+typedef enum
+{
+ NL1_RACH_RESTRICTED_SET_UNRESTRICTED = 0,
+ NL1_RACH_RESTRICTED_SET_TYPE_A = 1,
+ NL1_RACH_RESTRICTED_SET_TYPE_B = 2
+} nl1_rach_restricted_set_enum;
+
+typedef enum
+{
+ NL1_SSB_PER_RACH_OCCASION_ONE_EIGHTH = 0,
+ NL1_SSB_PER_RACH_OCCASION_ONE_FOURTH = 1,
+ NL1_SSB_PER_RACH_OCCASION_ONE_HALF = 2,
+ NL1_SSB_PER_RACH_OCCASION_ONE = 3,
+ NL1_SSB_PER_RACH_OCCASION_TWO = 4,
+ NL1_SSB_PER_RACH_OCCASION_FOUR = 5,
+ NL1_SSB_PER_RACH_OCCASION_EIGHT = 6,
+ NL1_SSB_PER_RACH_OCCASION_SIXTEEN = 7
+}nl1_ssb_per_rach_occasion_enum;
+
+typedef enum
+{
+ NL1_PUCCH_SPATIAL_RELATION_INFO_REFERENCE_SIGNAL_SSB = 0,
+ NL1_PUCCH_SPATIAL_RELATION_INFO_REFERENCE_SIGNAL_CSI_RS = 1,
+ NL1_PUCCH_SPATIAL_RELATION_INFO_REFERENCE_SIGNAL_SRS = 2
+} nl1_pucch_spatial_relation_info_reference_signal_enum;
+
+typedef enum
+{
+ NL1_PUSCH_RESOURCE_ALLOCATION_TYPE_0 = 0,
+ NL1_PUSCH_RESOURCE_ALLOCATION_TYPE_1 = 1,
+ NL1_PUSCH_RESOURCE_ALLOCATION_DYNAMIC_SWITCH = 2
+} nl1_pusch_resource_allocation_enum;
+
+typedef enum
+{
+ NL1_PUSCH_MAPPING_TYPE_A = 0,
+ NL1_PUSCH_MAPPING_TYPE_B = 1
+} nl1_pusch_mapping_type_enum;
+
+typedef enum
+{
+ NL1_PUSCH_CODEBOOK_SUBSET_FULLY_AND_PARTIAL_AND_NON_COHERENT = 0,
+ NL1_PUSCH_CODEBOOK_SUBSET_PARTIAL_AND_NON_COHERENT = 1,
+ NL1_PUSCH_CODEBOOK_SUBSET_NON_COHERENT = 2
+} nl1_pusch_codebook_subset_enum;
+
+typedef enum
+{
+ NL1_SRS_SWITCH_FROM_CARRIER_SUL = 0,
+ NL1_SRS_SWITCH_FROM_CARRIER_NUL = 1
+}nl1_srs_switch_from_carrier_enum;
+
+typedef enum
+{
+ NL1_SRS_RESOURCE_TYPE_APERIODIC = 0,
+ NL1_SRS_RESOURCE_TYPE_SEMI_PERSISTENT = 1,
+ NL1_SRS_RESOURCE_TYPE_PERIODIC = 2
+} nl1_srs_resource_type_enum;
+
+typedef enum
+{
+ NL1_SRS_RESOURCE_SET_USAGE_BEAM_MANAGEMENT = 0,
+ NL1_SRS_RESOURCE_SET_USAGE_CODEBOOK = 1,
+ NL1_SRS_RESOURCE_SET_USAGE_NON_CODEBOOK = 2,
+ NL1_SRS_RESOURCE_SET_USAGE_ANTENNA_SWITCHING = 3
+} nl1_srs_resource_set_usage_enum;
+
+typedef enum
+{
+ NL1_SRS_POWER_CONTROL_ADJUSTMENT_STATE_SAME_AS_FCI1 = 0,
+ NL1_SRS_POWER_CONTROL_ADJUSTMENT_STATE_SAME_AS_FCI2 = 1,
+ NL1_SRS_POWER_CONTROL_ADJUSTMENT_STATE_SEPERATE_CLOSED_LOOP = 2
+} nl1_srs_power_control_adjustment_state_enum;
+
+typedef enum
+{
+ NL1_SRS_SPATIAL_RELATION_INFO_REFERENCE_SIGNAL_SSB = 0,
+ NL1_SRS_SPATIAL_RELATION_INFO_REFERENCE_SIGNAL_CSI_RS = 1,
+ NL1_SRS_SPATIAL_RELATION_INFO_REFERENCE_SIGNAL_SRS = 2
+} nl1_srs_spatial_relation_info_reference_signal_enum;
+
+typedef enum
+{
+ NL1_CSI_RS_RESOURCE_FREQ_DOMAIN_ALLOCATION_ROW_1 = 0,
+ NL1_CSI_RS_RESOURCE_FREQ_DOMAIN_ALLOCATION_ROW_2 = 1,
+ NL1_CSI_RS_RESOURCE_FREQ_DOMAIN_ALLOCATION_ROW_4 = 2,
+ NL1_CSI_RS_RESOURCE_FREQ_DOMAIN_ALLOCATION_ROW_OTHER = 3
+} nl1_csi_rs_resource_freq_domain_allocation_row_enum;
+
+typedef enum
+{
+ NL1_CSI_RS_RESOURCE_CDM_TYPE_NO_CDM = 0,
+ NL1_CSI_RS_RESOURCE_CDM_TYPE_FD_CDM2 = 1,
+ NL1_CSI_RS_RESOURCE_CDM_TYPE_CDM4_FD2_TD2 = 2,
+ NL1_CSI_RS_RESOURCE_CDM_TYPE_CDM8_FD2_TD4 = 3
+} nl1_csi_rs_resource_cdm_type_enum;
+
+typedef enum
+{
+ NL1_CSI_RS_RESOURCE_DENSITY_0_DOT_5_EVEN_PRBS = 0,
+ NL1_CSI_RS_RESOURCE_DENSITY_0_DOT_5_ODD_PRBS = 1,
+ NL1_CSI_RS_RESOURCE_DENSITY_1 = 2,
+ NL1_CSI_RS_RESOURCE_DENSITY_3 = 3
+} nl1_csi_rs_resource_density_enum;
+
+typedef enum
+{
+ NL1_CSI_RESOURCE_CONFIG_TYPE_APERIODIC = 0,
+ NL1_CSI_RESOURCE_CONFIG_TYPE_SEMI_PERIODIC = 1,
+ NL1_CSI_RESOURCE_CONFIG_TYPE_PERIODIC = 2
+} nl1_csi_resource_config_type_enum;
+
+typedef enum
+{
+ NL1_CSI_REPORT_CONFIG_TYPE_PERIODIC = 0,
+ NL1_CSI_REPORT_CONFIG_TYPE_SEMI_PERSISTENT_ON_PUCCH = 1,
+ NL1_CSI_REPORT_CONFIG_TYPE_SEMI_PERSISTENT_ON_PUSCH = 2,
+ NL1_CSI_REPORT_CONFIG_TYPE_APERIODIC = 3
+} nl1_csi_report_config_type_enum;
+
+typedef enum
+{
+ NL1_CSI_REPORT_QUANTITY_NONE = 0,
+ NL1_CSI_REPORT_QUANTITY_CRI_RI_PMI_CQI = 1,
+ NL1_CSI_REPORT_QUANTITY_CRI_RI_I1 = 2,
+ NL1_CSI_REPORT_QUANTITY_CRI_RI_I1_CQI = 3,
+ NL1_CSI_REPORT_QUANTITY_CRI_RI_CQI = 4,
+ NL1_CSI_REPORT_QUANTITY_CRI_RSRP = 5,
+ NL1_CSI_REPORT_QUANTITY_SSB_INDEX_RSRP = 6,
+ NL1_CSI_REPORT_QUANTITY_CRI_RI_LI_PMI_CQI = 7
+
+} nl1_csi_report_quantity_enum;
+
+typedef enum
+{
+ NL1_CODEBOOK_TYPE_I_SINGLE_PANEL = 0,
+ NL1_CODEBOOK_TYPE_I_MULTI_PANEL = 1,
+ NL1_CODEBOOK_TYPE_II = 2,
+ NL1_CODEBOOK_TYPE_II_PORT_SELECTION = 3
+} nl1_codebook_type_enum;
+
+typedef enum
+{
+ NL1_CSI_REPORT_BLER_TARGET_O_DOT_1 = 0
+} nl1_csi_report_bler_target_enum;
+
+typedef enum
+{
+ NL1_CONTROL_RESOURCE_SET_PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE =0,
+ NL1_CONTROL_RESOURCE_SET_PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS =1
+} nl1_control_resource_set_precoder_granularity_enum;
+
+typedef enum
+{
+ NL1_PDSCH_MAPPING_TYPE_A = 0,
+ NL1_PDSCH_MAPPING_TYPE_B = 1
+} nl1_pdsch_mapping_type_enum;
+
+typedef enum
+{
+ NL1_QCL_INFO_REFERENCE_SIGNAL_CSI_RS = 0,
+ NL1_QCL_INFO_REFERENCE_SIGNAL_SSB = 1
+} nl1_qcl_info_reference_signal_enum;
+
+typedef enum
+{
+ NL1_QCL_TYPE_A = 0,
+ NL1_QCL_TYPE_B = 1,
+ NL1_QCL_TYPE_C = 2,
+ NL1_QCL_TYPE_D = 3
+} nl1_qcl_type_enum;
+
+typedef enum
+{
+ NL1_PDSCH_RESOURCE_ALLOCATION_TYPE_0 = 0,
+ NL1_PDSCH_RESOURCE_ALLOCATION_TYPE_1 = 1,
+ NL1_PDSCH_RESOURCE_ALLOCATION_DYNAMIC_SWITCH = 2
+} nl1_pdsch_resource_allocation_enum;
+
+typedef enum
+{
+ NL1_PDSCH_PRB_BUNDLE_SIZE_N2 = 0,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_N4 = 1,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_WIDEBAND = 2
+} nl1_pdsch_prb_bundle_size_enum;
+
+typedef enum
+{
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET1_N2 = 0,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET1_N4 = 1,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET1_WIDEBAND = 2,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET1_N2_WIDEBAND = 3,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET1_N4_WIDEBAND = 4
+} nl1_pdsch_prb_bundle_size_set1_enum;
+
+typedef enum
+{
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET2_N2 = 0,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET2_N4 = 1,
+ NL1_PDSCH_PRB_BUNDLE_SIZE_SET2_WIDEBAND = 2
+} nl1_pdsch_prb_bundle_size_set2_enum;
+
+typedef enum //20180529
+{
+ NL1_X_OVERHEAD_0 = 0,
+ NL1_X_OVERHEAD_6 = 1,
+ NL1_X_OVERHEAD_12 = 2,
+ NL1_X_OVERHEAD_18 = 3
+} nl1_x_overhead_enum;
+
+typedef enum //20180529
+{
+ NL1_VRB_TO_PRB_INTERLEAVER_2 = 0,
+ NL1_VRB_TO_PRB_INTERLEAVER_4 = 1
+} nl1_vrb_to_prb_interleaver_enum;
+
+typedef enum //20180529
+{
+ NL1_PUSCH_RBG_SIZE_CONFIG_1 = 0,
+ NL1_PUSCH_RBG_SIZE_CONFIG_2 = 1
+} nl1_pusch_rbg_size_enum;
+
+typedef enum //20180529
+{
+ NL1_PDSCH_RBG_SIZE_CONFIG_1 = 0,
+ NL1_PDSCH_RBG_SIZE_CONFIG_2 = 1
+} nl1_pdsch_rbg_size_enum;
+
+typedef enum //20180529
+{
+ NL1_PUSCH_MCS_TABLE_64_QAM = 0,
+ NL1_PUSCH_MCS_TABLE_256_QAM = 1,
+ NL1_PUSCH_MCS_TABLE_64_QAM_LOW_SE = 2
+} nl1_pusch_mcs_table_enum;
+
+typedef enum //20180529
+{
+ NL1_PDSCH_MCS_TABLE_64_QAM = 0,
+ NL1_PDSCH_MCS_TABLE_256_QAM = 1,
+ NL1_PDSCH_MCS_TABLE_64_QAM_LOW_SE = 2
+} nl1_pdsch_mcs_table_enum;
+
+typedef enum //20180529
+{
+ NL1_SRS_TPC_PDCCH_GROUP_TYPE_A = 0,
+ NL1_SRS_TPC_PDCCH_GROUP_TYPE_B = 1
+} nl1_srs_tpc_pdcch_group_type_enum;
+
+typedef enum //20180529
+{
+ NL1_EUTRA_BANDWIDTH_6 = 0,
+ NL1_EUTRA_BANDWIDTH_15 = 1,
+ NL1_EUTRA_BANDWIDTH_25 = 2,
+ NL1_EUTRA_BANDWIDTH_50 = 3,
+ NL1_EUTRA_BANDWIDTH_75 = 4,
+ NL1_EUTRA_BANDWIDTH_100 = 5
+} nl1_eutra_bandwidth_enum;
+
+typedef enum //20180529
+{
+ NL1_EUTRA_CRS_PORTS_NUM_1 = 0,
+ NL1_EUTRA_CRS_PORTS_NUM_2 = 1,
+ NL1_EUTRA_CRS_PORTS_NUM_4 = 2
+} nl1_eutra_crs_ports_num_enum;
+
+typedef enum //20180529
+{
+ NL1_EUTRA_MBSFN_RADIO_FRAME_ALLOCATION_PERIOD_1 = 0,
+ NL1_EUTRA_MBSFN_RADIO_FRAME_ALLOCATION_PERIOD_2 = 1,
+ NL1_EUTRA_MBSFN_RADIO_FRAME_ALLOCATION_PERIOD_4 = 2,
+ NL1_EUTRA_MBSFN_RADIO_FRAME_ALLOCATION_PERIOD_8 = 3,
+ NL1_EUTRA_MBSFN_RADIO_FRAME_ALLOCATION_PERIOD_16 = 4,
+ NL1_EUTRA_MBSFN_RADIO_FRAME_ALLOCATION_PERIOD_32 = 5
+} nl1_eutra_mbsfn_radio_frame_allocation_period_enum;
+
+typedef enum //20180529
+{
+ NL1_EUTRA_MBSFN_SUBFRAME_ALLOCATION_TYPE_ONE_FRAME = 0,
+ NL1_EUTRA_MBSFN_SUBFRAME_ALLOCATION_TYPE_FOUR_FRAMES = 1
+} nl1_eutra_mbsfn_subframe_allocation_type_enum;
+
+typedef enum //20180529
+{
+ NL1_PUSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_2 = 0,
+ NL1_PUSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_4 = 1,
+ NL1_PUSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_6 = 2,
+ NL1_PUSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_8 = 3
+} nl1_pusch_max_code_block_groups_per_tb_enum;
+
+typedef enum //20180529
+{
+ NL1_AGGREGATION_FACTOR_1 = 0,
+ NL1_AGGREGATION_FACTOR_2 = 1,
+ NL1_AGGREGATION_FACTOR_4 = 2,
+ NL1_AGGREGATION_FACTOR_8 = 3
+} nl1_aggregation_factor_enum;
+
+typedef enum //20180529
+{
+ NL1_PDSCH_MAX_CODE_WORDS_BY_DCI_1 = 0,
+ NL1_PDSCH_MAX_CODE_WORDS_BY_DCI_2 = 1
+} nl1_pdsch_max_code_words_by_dci_enum;
+
+typedef enum //20180529
+{
+ NL1_PDSCH_PRB_BUNDLING_TYPE_STATIC = 0,
+ NL1_PDSCH_PRB_BUNDLING_TYPE_DYNAMIC = 1
+} nl1_pdsch_prb_bundling_type_enum;
+
+typedef enum //20180529
+{
+ NL1_DMRS_TYPE_1 = 0,
+ NL1_DMRS_TYPE_2 = 1
+} nl1_dmrs_type_enum;
+
+typedef enum //20180529
+{
+ NL1_DMRS_MAX_LENGTH_1 = 0,
+ NL1_DMRS_MAX_LENGTH_2 = 1
+} nl1_dmrs_max_length_enum;
+
+typedef enum //20180529
+{
+ NL1_RATE_MATCH_PATTERN_TYPE_BITMAPS = 0,
+ NL1_RATE_MATCH_PATTERN_TYPE_CONTROL_RESOURCE_SET = 1
+} nl1_rate_match_pattern_type_enum;
+
+typedef enum //20180529
+{
+ NL1_TCI_STATE_PTRS_PORTS_NUM_1 = 0,
+ NL1_TCI_STATE_PTRS_PORTS_NUM_2 = 1
+} nl1_tci_state_ptrs_ports_num_enum;
+
+typedef enum //20180529
+{
+ NL1_MAC_DRX_ON_DURATION_TIMER_UNIT_1_DIV_32_MS = 0,
+ NL1_MAC_DRX_ON_DURATION_TIMER_UNIT_MS = 1
+} nl1_mac_drx_on_duration_timer_unit_enum;
+
+typedef enum //20180529
+{
+ NL1_SRS_PORT_NUM_1 = 0,
+ NL1_SRS_PORT_NUM_2 = 1,
+ NL1_SRS_PORT_NUM_4 = 2
+} nl1_srs_port_num_enum;
+
+typedef enum //20180529
+{
+ NL1_PDSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_2 = 0,
+ NL1_PDSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_4 = 1,
+ NL1_PDSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_6 = 2,
+ NL1_PDSCH_MAX_CODE_BLOCK_GROUPS_PER_TB_8 = 3
+} nl1_pdsch_max_code_block_groups_per_tb_enum;
+
+typedef enum //20180529
+{
+ NL1_PUSCH_TX_CONFIG_TYPE_CODEBOOK = 0,
+ NL1_PUSCH_TX_CONFIG_TYPE_NON_CODEBOOK = 1
+} nl1_pusch_tx_config_type_enum;
+
+typedef enum //20180808
+{
+ NL1_N_TA_OFFSET_0 = 0,
+ NL1_N_TA_OFFSET_25600 = 1,
+ NL1_N_TA_OFFSET_39936 = 2
+} nl1_n_timing_advance_offset_enum;
+
+typedef enum //20181008
+{
+ NL1_PCCH_CONFIG_N_ONE_T = 0,
+ NL1_PCCH_CONFIG_N_HALF_T = 1,
+ NL1_PCCH_CONFIG_N_QUARTER_T = 2,
+ NL1_PCCH_CONFIG_N_ONE_EIGHTH_T = 3,
+ NL1_PCCH_CONFIG_N_ONE_SIXTEENTH_T = 4
+}nl1_pcch_config_n_enum;
+
+typedef enum
+{
+ NL1_SSB_POSITIONS_IN_BURST_BITMAP_LENGTH_SHORT = 0,
+ NL1_SSB_POSITIONS_IN_BURST_BITMAP_LENGTH_MEDIUM = 1,
+ NL1_SSB_POSITIONS_IN_BURST_BITMAP_LENGTH_LONG = 2,
+ NL1_SSB_POSITIONS_IN_BURST_BITMAP_LENGTH_SHORT_OR_MEDIUM = 3
+}nl1_ssb_positions_in_burst_bitmap_length_enum;
+
+typedef enum
+{
+ NL1_CONTROL_RESOURCE_SET_REG_BUNDLE_SIZE_2 = 0,
+ NL1_CONTROL_RESOURCE_SET_REG_BUNDLE_SIZE_3 = 1,
+ NL1_CONTROL_RESOURCE_SET_REG_BUNDLE_SIZE_6 = 2
+}nl1_control_resource_set_reg_bundle_size_enum;
+
+typedef enum
+{
+ NL1_CONTROL_RESOURCE_SET_INTERLEAVER_SIZE_2 = 0,
+ NL1_CONTROL_RESOURCE_SET_INTERLEAVER_SIZE_3 = 1,
+ NL1_CONTROL_RESOURCE_SET_INTERLEAVER_SIZE_6 = 2
+}nl1_control_resource_set_interleaver_size_enum;
+
+typedef enum
+{
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_1_SLOT = 0,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_2_SLOTS = 1,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_4_SLOTS = 2,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_5_SLOTS = 3,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_8_SLOTS = 4,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_10_SLOTS = 5,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_16_SLOTS = 6,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_20_SLOTS = 7,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_40_SLOTS = 8,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_80_SLOTS = 9,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_160_SLOTS = 10,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_320_SLOTS = 11,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_640_SLOTS = 12,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_1280_SLOTS = 13,
+ NL1_SEARCH_SPACE_MONITORING_SLOT_PERIODICITY_2560_SLOTS = 14
+}nl1_search_space_monitoring_slot_periodicity_enum;
+
+typedef enum
+{
+ NL1_DOWNLINK_PREEMPTION_TIME_FREQUENCY_SET_0 = 0,
+ NL1_DOWNLINK_PREEMPTION_TIME_FREQUENCY_SET_1 = 1
+}nl1_downlink_preemption_time_frequency_set_enum;
+
+typedef enum
+{
+ NL1_RATE_MATCH_PATTERN_SYMBOLS_IN_RB_ONE_SLOT = 0,
+ NL1_RATE_MATCH_PATTERN_SYMBOLS_IN_RB_TWO_SLOTS = 1
+}nl1_rate_match_pattern_symbols_in_rb_enum;
+
+typedef enum
+{
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_1_SLOT = 0,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_2_SLOTS = 1,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_4_SLOTS = 2,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_5_SLOTS = 3,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_8_SLOTS = 4,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_10_SLOTS = 5,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_20_SLOTS = 6,
+ NL1_RATE_MATCH_PATTERN_PERIODICITY_40_SLOTS = 7
+}nl1_rate_match_pattern_periodicity_enum;
+
+typedef enum
+{
+ NL1_SPS_PERIODICITY_10_MS = 0,
+ NL1_SPS_PERIODICITY_20_MS = 1,
+ NL1_SPS_PERIODICITY_32_MS = 2,
+ NL1_SPS_PERIODICITY_40_MS = 3,
+ NL1_SPS_PERIODICITY_64_MS = 4,
+ NL1_SPS_PERIODICITY_80_MS = 5,
+ NL1_SPS_PERIODICITY_128_MS = 6,
+ NL1_SPS_PERIODICITY_160_MS = 7,
+ NL1_SPS_PERIODICITY_320_MS = 8,
+ NL1_SPS_PERIODICITY_640_MS = 9
+}nl1_sps_periodicity_enum;
+
+typedef enum
+{
+ NL1_PTRS_UPLINK_CONFIG_TRANSFORM_PRECODER_DISABLED_MAX_PORTS_1 = 0,
+ NL1_PTRS_UPLINK_CONFIG_TRANSFORM_PRECODER_DISABLED_MAX_PORTS_2 = 1
+}nl1_ptrs_uplink_config_transform_precoder_disabled_max_ports_enum;
+
+typedef enum
+{
+ NL1_PUSCH_FREQUENCY_HOPPING_NOT_CONFIG = 0,
+ NL1_PUSCH_FREQUENCY_HOPPING_INTRASLOT = 1,
+ NL1_PUSCH_FREQUENCY_HOPPING_INTERSLOT = 2
+}nl1_pusch_frequency_hopping_enum;
+
+typedef enum
+{
+ NL1_PUSCH_MAX_RANK_1 = 0,
+ NL1_PUSCH_MAX_RANK_2 = 1,
+ NL1_PUSCH_MAX_RANK_3 = 2,
+ NL1_PUSCH_MAX_RANK_4 = 3
+}nl1_pusch_max_rank_enum;
+
+typedef enum
+{
+ NRRC_NL1_VC_ENTER = 0, // Enter Virtual Connected from Connected
+ NRRC_NL1_VC_LEAVE = 1, // Leave Virtual Connected to Connected
+ NRRC_NL1_VC_LEAVE_FAIL = 2 // Virtual Connected leave failure
+}nrrc_nl1_vc_cause_enum;
+
+typedef enum
+{
+ NRRC_NL1_ENHANCEMENT_ENDC_DEACT = 0, // endc deactivate - block all meas report
+ NRRC_NL1_ENHANCEMENT_ENDC_DEACT_WITH_TEST_SIM = 1, // endc deactivate - block all meas report also enable under test sim/mode
+ NRRC_NL1_ENHANCEMENT_ENDC_FAKE_A2 = 2,
+ NRRC_NL1_ENHANCEMENT_SERVCELL_LOW_PRIORITY = 3,
+ NRRC_NL1_ENHANCEMENT_MAX_NUM = 4 // end of enhancement enum
+}nrrc_nl1_enhancement_enum;
+
+typedef enum
+{
+ NRRC_NL1_ENHANCEMENT_ACTION_OFF = 0,
+ NRRC_NL1_ENHANCEMENT_ACTION_ON = 1
+}nrrc_nl1_enhancement_action_enum;
+
+/* MSG_ID_L4C_NRRC_CUSTOM_BAR_LIST_REQ */
+/* action_enum, currently identical sync to nrrc_custom_bar_list_action_enum*/
+typedef enum
+{
+ NL1_CONN_BAR_LIST_INVALID_ACT = 0,
+ NL1_CONN_BAR_LIST_ADD = 1,
+ NL1_CONN_BAR_LIST_DELETE = 2,
+ NL1_CONN_BAR_LIST_QUERY = 3
+}nl1_conn_bar_list_action_enum;
+
+/* cause_enum, currently identical sync to nrrc_custom_bar_cause_enum*/
+typedef enum
+{
+ NL1_CONNECTED_BAR_CAUSE_INVALID = 0, /* None. Initial value. */
+ NL1_CONNECTED_BAR_CAUSE_BLACK_CELL_OOS = 1, /* Custom defined BLACK cell for Pcell OOS triggered, ALPS05362947 */
+ NL1_CONNECTED_BAR_CAUSE_BLACK_CELL_MEAS_TH = 2, /* Custom defined BLACK cells, but temply unbarred when all LTE ncell < threshold, for ALPS05370680*/
+ NL1_CONNECTED_BAR_CAUSE_ALL /* All BAR CAUSE*/
+} NL1_CONNECTED_BAR_CAUSE_TYPE_E;
+
+typedef enum
+{
+ NL1_DMRS_ADDITIONAL_POSITION_0 = 0,
+ NL1_DMRS_ADDITIONAL_POSITION_1 = 1,
+ NL1_DMRS_ADDITIONAL_POSITION_2 = 2,
+ NL1_DMRS_ADDITIONAL_POSITION_3 = 3
+}nl1_dmrs_additional_position_enum;
+
+typedef enum
+{
+ NL1_PTRS_DOWNLINK_RESOURCE_ELEMENT_OFFSET_00 = 0,
+ NL1_PTRS_DOWNLINK_RESOURCE_ELEMENT_OFFSET_01 = 1,
+ NL1_PTRS_DOWNLINK_RESOURCE_ELEMENT_OFFSET_10 = 2,
+ NL1_PTRS_DOWNLINK_RESOURCE_ELEMENT_OFFSET_11 = 3
+}nl1_ptrs_downlink_resource_element_offset_enum;
+
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+typedef enum
+{
+ NL1_X_SCALE_0 = 0,
+ NL1_X_SCALE_6 = 1
+}nl1_x_scale_enum;
+
+typedef enum
+{
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_0 = 0,
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_1 = 1,
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_2 = 2,
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_3 = 3,
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_4 = 4,
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_16 = 5,
+ NL1_NZP_CSI_RS_RESOURCE_SET_APERIODIC_TRIGGERING_OFFSET_24 = 6
+}nl1_nzp_csi_rs_resource_set_aperiodic_triggering_offset_enum;
+#endif
+
+typedef enum
+{
+ NL1_SCELL_SMTC_TIMING_REFERENCE_CELL_SOURCE_PRIMARY_CELL = 0,
+ NL1_SCELL_SMTC_TIMING_REFERENCE_CELL_TARGET_PRIMARY_CELL = 1
+}nl1_scell_smtc_timing_reference_cell_enum;
+
+typedef enum
+{
+ NL1_PRIMARY_CELL_SMTC_TIMING_REFERENCE_CELL_LTE_PCELL = 0,
+ NL1_PRIMARY_CELL_SMTC_TIMING_REFERENCE_CELL_NR_PCELL = 1,
+ NL1_PRIMARY_CELL_SMTC_TIMING_REFERENCE_CELL_NR_PSCELL = 2
+}nl1_primary_cell_smtc_timing_reference_cell_enum;
+
+typedef struct
+{
+ kal_uint16 offset_to_carrier;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ kal_uint16 bandwidth;
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ kal_bool tx_direct_current_location_valid;
+#endif
+ kal_uint16 tx_direct_current_location;
+}nl1_scs_specific_carrier_struct;
+
+typedef struct
+{
+ kal_bool absolute_frequency_ssb_valid;
+ kal_uint32 absolute_frequency_ssb;
+ kal_uint32 absolute_frequency_point_a;
+ kal_uint16 frequency_band;
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+} nl1_dl_frequency_info_struct;
+
+typedef struct
+{
+ kal_uint16 frequency_band;
+ kal_uint32 absolute_frequency_point_a;
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+ kal_uint8 additional_spectrum_emission;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_int8 p_max;
+#else
+ kal_bool pmax_valid;
+ kal_int8 pmax;
+#endif
+ kal_bool frequency_shift_7_dot_5_khz;
+} nl1_ul_frequency_info_struct;
+
+typedef struct
+{
+ kal_uint16 t310;
+ kal_uint8 n310;
+ kal_uint8 n311;
+} nl1_rlf_timers_and_constants_struct;
+
+typedef struct
+{
+ kal_uint8 prach_configuration_index;
+ kal_uint8 msg1_fdm;
+ kal_uint16 msg1_frequency_start;
+ kal_uint8 zero_correlation_zone_config;
+ kal_int16 preamble_received_target_power;
+ kal_uint8 preamble_tx_max;
+ kal_uint8 power_ramping_step;
+ kal_uint8 ra_response_window;
+} nl1_rach_config_generic_struct;
+
+typedef struct
+{
+ kal_uint8 prach_configuration_index;
+ kal_uint8 msg1_fdm;
+ kal_uint16 msg1_frequency_start;
+ kal_uint8 zero_correlation_zone_config;
+}nl1_rach_config_generic_cfra_struct;
+
+typedef struct
+{
+ kal_uint8 ssb_index;
+ kal_uint8 ra_preamble_index;
+} nl1_cfra_ssb_resource_struct;
+
+typedef struct
+{
+ kal_uint8 csi_rs_index;
+ kal_uint8 ra_occasion_num;
+ kal_uint16 ra_occasion_list[NL1_RA_OCCASION_LIST_SIZE];
+ kal_uint8 ra_preamble_index;
+} nl1_cfra_csi_rs_resource_struct;
+
+typedef struct
+{
+ kal_bool is_ssb;
+ kal_uint8 ssb_resource_num;
+ nl1_cfra_ssb_resource_struct ssb_resource_list[NL1_RA_SSB_RESOURCES_LIST_SIZE];
+ kal_uint8 ssb_occasion_mask_index;
+ kal_uint8 csi_rs_resource_num;
+ nl1_cfra_csi_rs_resource_struct csi_rs_resource_list[NL1_RA_CSIRS_RESOURCES_LIST_SIZE];
+ kal_uint8 rsrp_threshold_csi_rs; //only valid when is_ssb = FALSE.
+} nl1_cfra_resources_struct;
+
+typedef struct
+{
+ nl1_rach_config_generic_cfra_struct rach_config_generic;
+ kal_bool ssb_per_rach_occasion_valid;
+ nl1_ssb_per_rach_occasion_enum ssb_per_rach_occasion;
+ kal_uint8 total_number_of_ra_preambles;
+} nl1_cfra_occasions_struct;
+
+typedef struct
+{
+ kal_bool cfra_occasions_valid;
+ nl1_cfra_occasions_struct cfra_occasions;
+ nl1_cfra_resources_struct cfra_resources;
+} nl1_cfra_struct;
+
+typedef struct
+{
+ kal_uint8 power_ramping_step_high_priority;
+ kal_bool scaling_factor_bi_valid;
+ kal_uint8 scaling_factor_bi;
+} nl1_ra_prioritization_struct;
+
+typedef struct
+{
+ kal_bool is_dedicated_rach_config_for_sul;
+ kal_bool cfra_valid;
+ nl1_cfra_struct cfra;
+ kal_bool ra_prioritization_valid;
+ nl1_ra_prioritization_struct ra_prioritization;
+} nl1_rach_config_dedicated_struct;
+
+typedef struct
+{
+ nl1_ssb_per_rach_occasion_enum ssb_per_rach_occasion;
+ kal_uint8 cb_preamble_per_ssb;
+} nl1_ssb_per_rach_and_cb_preamble_per_ssb_struct;
+
+typedef struct
+{
+ kal_uint16 ra_msg3_size_group_a;
+ /* Please use NL1_RA_PREAMBLES_GROUP_B_POWER_OFFSET_MINUS_INFINITY (0xFF) for 'Minus Infinity'. */
+ kal_uint8 message_power_offset_group_b; //minus infinity(0xff), 0,5,8,10,12,15,18
+ kal_uint8 ra_preambles_group_a_num;
+} nl1_ra_preambles_group_b_struct;
+
+typedef struct
+{
+ nl1_rach_config_generic_struct rach_config_generic;
+ kal_uint8 total_number_of_ra_preambles;
+ kal_bool ssb_per_rach_occasion_and_cb_preamble_per_ssb_valid;
+ nl1_ssb_per_rach_and_cb_preamble_per_ssb_struct ssb_per_rach_occasion_and_cb_preamble_per_ssb;
+ kal_bool group_b_valid;
+ nl1_ra_preambles_group_b_struct group_b;
+ kal_uint8 ra_contention_resolution_timer;
+ kal_bool rsrp_threshold_ssb_valid;
+ kal_uint8 rsrp_threshold_ssb;
+ kal_bool sul_rsrp_threshold_valid;
+ kal_uint8 sul_rsrp_threshold;
+ kal_uint16 l_ra;
+ kal_uint16 prach_root_sequence_index;
+ kal_bool msg1_subcarrier_spacing_valid;
+ NR_SCS_TYPE_E msg1_subcarrier_spacing;
+ nl1_rach_restricted_set_enum restricted_set_config;
+ kal_bool msg3_transform_precoder;
+} nl1_rach_config_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_id;
+ kal_uint8 resource_num;
+ kal_uint8 resource_list[NL1_PUCCH_RESOURCES_PER_SET_LIST_SIZE];
+ kal_bool max_payload_minus_1_valid;
+ kal_uint16 max_payload_minus_1;
+} nl1_pucch_resource_set_struct;
+
+typedef struct
+{
+ kal_uint8 resource_id;
+ kal_uint16 starting_prb;
+ kal_bool intra_slot_frequency_hopping;
+ kal_bool second_hop_prb_valid;
+ kal_uint16 second_hop_prb;
+ kal_uint8 format;
+ kal_uint8 initial_cyclic_shift;
+ kal_uint8 symbol_num;
+ kal_uint8 starting_symbol_index;
+ kal_uint8 time_domain_occ;
+ kal_uint8 prb_num;
+ kal_uint8 occ_length;
+ kal_uint8 occ_index;
+} nl1_pucch_resource_struct;
+
+typedef struct
+{
+ kal_bool inter_slot_frequency_hopping;
+ kal_bool additional_dmrs_enabled;
+ kal_uint8 max_code_rate;
+ kal_uint8 slots_num;
+ kal_bool pi_2_bpsk;
+ kal_bool simultaneous_harq_ack_csi;
+} nl1_pucch_format_config_struct;
+
+typedef struct
+{
+ kal_uint8 scheduling_request_resource_id;
+ kal_uint8 scheduling_request_id;
+ kal_bool sr_periodicity_as_symbols;
+ kal_uint16 sr_periodicity;
+ kal_uint16 sr_offset;
+ kal_uint8 resource;
+} nl1_scheduling_reqeust_resource_config_struct;
+
+typedef struct
+{
+ kal_uint8 spatial_relation_info_id;
+ kal_uint8 serv_cell_index;
+ nl1_pucch_spatial_relation_info_reference_signal_enum reference_signal;
+ kal_uint8 reference_signal_id;
+ kal_uint8 uplink_bwp_id;
+ kal_uint8 pathloss_reference_rs_id;
+ kal_uint8 p0_id;
+ kal_uint8 closed_loop_index;
+} nl1_pucch_spatial_relation_info_struct;
+
+typedef struct
+{
+ kal_uint8 p0_id;
+ kal_int8 p0;
+} nl1_pucch_p0_struct;
+
+typedef struct
+{
+ kal_uint8 pathloss_reference_rs_id;
+ kal_bool reference_signal_is_ssb;
+ kal_uint8 id;
+} nl1_pucch_pathloss_reference_rs_struct;
+
+typedef struct
+{
+ kal_bool delta_f_format_0_valid;
+ kal_int8 delta_f_format_0;
+ kal_bool delta_f_format_1_valid;
+ kal_int8 delta_f_format_1;
+ kal_bool delta_f_format_2_valid;
+ kal_int8 delta_f_format_2;
+ kal_bool delta_f_format_3_valid;
+ kal_int8 delta_f_format_3;
+ kal_bool delta_f_format_4_valid;
+ kal_int8 delta_f_format_4;
+ kal_uint8 p0_num;
+ nl1_pucch_p0_struct p0_list[NL1_PUCCH_P0_PER_SET_LIST_SIZE];
+ kal_uint8 pathloss_reference_rs_num;
+ nl1_pucch_pathloss_reference_rs_struct pathloss_reference_rs_list[NL1_PUCCH_PATHLOSS_REF_RS_LIST_SIZE];
+ kal_uint8 power_control_adjustment_states_num;
+} nl1_pucch_power_control_struct;
+
+typedef struct
+{
+ kal_bool pucch_resource_common_valid;
+ kal_uint8 pucch_resource_common;
+ kal_bool pucch_group_hopping_enabled;
+ kal_bool pucch_sequence_hopping_enabled;
+ kal_bool hopping_id_valid;
+ kal_uint16 hopping_id;
+ kal_bool p0_nominal_valid;
+ kal_int16 p0_nominal;
+} nl1_pucch_config_common_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_num;
+ nl1_pucch_resource_set_struct resource_set_list[NL1_PUCCH_RESOURCES_SET_LIST_SIZE];
+ kal_uint8 resource_num;
+ nl1_pucch_resource_struct resource_list[NL1_PUCCH_RESOURCES_LIST_SIZE];
+ kal_bool format_1_config_valid;
+ nl1_pucch_format_config_struct format_1_config;
+ kal_bool format_2_config_valid;
+ nl1_pucch_format_config_struct format_2_config;
+ kal_bool format_3_config_valid;
+ nl1_pucch_format_config_struct format_3_config;
+ kal_bool format_4_config_valid;
+ nl1_pucch_format_config_struct format_4_config;
+ kal_uint8 scheduling_request_resource_num;
+ nl1_scheduling_reqeust_resource_config_struct scheduling_request_resource_list[NL1_SR_CONFIG_LIST_SIZE];
+ kal_uint8 multi_csi_resource_num;
+ kal_uint8 multi_csi_resource_list[NL1_PUCCH_MULTI_CSI_RESOURCES_LIST_SIZE];
+ kal_uint8 dl_data_to_ul_ack_num;
+ kal_uint8 dl_data_to_ul_ack_list[NL1_PUCCH_DL_DATA_TO_UL_ACK_LIST_SIZE];
+ kal_uint8 spatial_relation_info_num;
+ nl1_pucch_spatial_relation_info_struct spatial_relation_info_list[NL1_PUCCH_SPATIAL_RELATION_INFO_LIST_SIZE];
+ kal_bool pucch_power_control_valid;
+ nl1_pucch_power_control_struct pucch_power_control;
+} nl1_pucch_config_dedicated_struct;
+
+typedef struct
+{
+ kal_bool pucch_config_common_valid;
+ nl1_pucch_config_common_struct pucch_config_common;
+ kal_bool pucch_config_dedicated_valid;
+ nl1_pucch_config_dedicated_struct pucch_config_dedicated;
+} nl1_pucch_config_struct;
+
+typedef struct
+{
+ nl1_pusch_max_code_block_groups_per_tb_enum max_code_block_groups_per_transport_block;
+} nl1_pusch_code_block_group_transmission_struct;
+
+typedef struct
+{
+ kal_bool k2_valid;
+ kal_uint8 k2;
+ nl1_pusch_mapping_type_enum mapping_type;
+ kal_uint8 start_symbol_and_length;
+} nl1_pusch_time_domain_resource_allocation_struct;
+
+typedef struct
+{
+ kal_bool frequency_density_valid;
+ kal_uint16 frequency_density[NL1_PTRS_UPLINK_FREQ_DENSITY_LIST_SIZE];
+ kal_bool time_density_valid;
+ kal_uint8 time_density[NL1_PTRS_UPLINK_TIME_DENSITY_LIST_SIZE];
+ nl1_ptrs_uplink_config_transform_precoder_disabled_max_ports_enum max_ports_num;
+ kal_uint8 resource_element_offset;
+ kal_uint8 ptrs_power;
+}nl1_ptrs_uplink_config_transform_precoder_disabled_struct;
+
+typedef struct
+{
+ kal_uint16 sample_density[NL1_PTRS_UPLINK_SAMPLE_DENSITY_LIST_SIZE];
+ kal_uint8 time_density_transform_precoding;
+}nl1_ptrs_uplink_config_transform_precoder_enabled_struct;
+
+typedef struct
+{
+ kal_bool transform_precoder_disabled_valid;
+ nl1_ptrs_uplink_config_transform_precoder_disabled_struct transform_precoder_disabled;
+ kal_bool transform_precoder_enabled_valid;
+ nl1_ptrs_uplink_config_transform_precoder_enabled_struct transform_precoder_enabled;
+} nl1_ptrs_uplink_config_struct;
+
+typedef struct
+{
+ nl1_dmrs_type_enum dmrs_type;
+ nl1_dmrs_additional_position_enum dmrs_additional_position;
+ kal_bool ptrs_config_valid;
+ nl1_ptrs_uplink_config_struct ptrs_config;
+ nl1_dmrs_max_length_enum max_length;
+ kal_bool transform_precoding_disabled;
+ kal_bool scrambling_id_0_valid;
+ kal_uint16 scrambling_id_0;
+ kal_bool scrambling_id_1_valid;
+ kal_uint16 scrambling_id_1;
+ kal_bool transform_precoding_enabled;
+ kal_bool npusch_identity_valid;
+ kal_uint16 npusch_identity;
+ kal_bool sequence_group_hopping_disabled;
+ kal_bool sequence_hopping_enabled;
+} nl1_dmrs_uplink_config_struct;
+
+typedef struct
+{
+ kal_uint8 beta_offset_ack_index_1;
+ kal_uint8 beta_offset_ack_index_2;
+ kal_uint8 beta_offset_ack_index_3;
+ kal_uint8 beta_offset_csi_part_1_index_1;
+ kal_uint8 beta_offset_csi_part_1_index_2;
+ kal_uint8 beta_offset_csi_part_2_index_1;
+ kal_uint8 beta_offset_csi_part_2_index_2;
+} nl1_pusch_beta_offsets_struct;
+
+typedef struct
+{
+ kal_bool is_dynamic;
+ kal_uint8 beta_offsets_num;
+ nl1_pusch_beta_offsets_struct beta_offsets_list[NL1_UCI_ON_PUSCH_BETA_OFFSETS_LIST_SIZE];
+} nl1_uci_on_pusch_beta_offsets_struct;
+
+typedef struct
+{
+ nl1_uci_on_pusch_beta_offsets_struct beta_offsets;
+ kal_uint8 scaling_factor;
+} nl1_uci_on_pusch_struct;
+
+typedef struct
+{
+ kal_bool is_dynamic;
+ kal_uint8 beta_offsets_num;
+ nl1_pusch_beta_offsets_struct beta_offsets_list[NL1_UCI_ON_PUSCH_BETA_OFFSETS_LIST_SIZE];
+} nl1_configured_grant_uci_on_pusch_struct;
+
+typedef struct
+{
+ kal_uint8 p0_pusch_alphaset_id;
+ kal_bool p0_valid;
+ kal_int8 p0;
+ kal_uint8 alpha;
+} nl1_pusch_p0_alphaset_struct;
+
+typedef struct
+{
+ kal_uint8 pathloss_reference_rs_id;
+ kal_bool reference_signal_is_ssb;
+ kal_uint8 id;
+} nl1_pusch_pathloss_reference_rs_struct;
+
+typedef struct
+{
+ kal_uint8 sri_pusch_power_control_id;
+ kal_uint8 pathloss_rs_id;
+ kal_uint8 alphaset_id;
+ kal_uint8 closed_loop_index;
+} nl1_sri_pusch_power_control_struct;
+
+typedef struct
+{
+ kal_bool accumulation_enabled;
+ kal_uint8 msg3_alpha;
+ kal_bool p0_nominal_without_grant_valid;
+ kal_int16 p0_nominal_without_grant;
+ kal_uint8 p0_pusch_alphaset_num;
+ nl1_pusch_p0_alphaset_struct p0_pusch_alphaset_list[NL1_PUSCH_P0_ALPHASET_LIST_SIZE];
+ kal_uint8 pathloss_reference_rs_num;
+ nl1_pusch_pathloss_reference_rs_struct pathloss_reference_rs_list[NL1_PUSCH_PATHLOSS_REF_RS_LIST_SIZE];
+ kal_uint8 power_control_adjustment_states_num;
+ kal_bool delta_mcs_enabled;
+ kal_uint8 sri_pusch_power_control_num;
+ nl1_sri_pusch_power_control_struct sri_pusch_power_control_list[NL1_PUSCH_SRI_PUSCH_PC_LIST_SIZE];
+} nl1_pusch_power_control_struct;
+
+typedef struct
+{
+ kal_bool code_block_group_transmission_valid;
+ nl1_pusch_code_block_group_transmission_struct code_block_group_transmission;
+ kal_bool limited_buffer_rate_matching_enabled;
+ nl1_x_overhead_enum x_overhead;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_bool max_mimo_layers_valid;
+ kal_uint8 max_mimo_layers;
+ kal_bool processing_type_2_enabled;
+#endif
+} nl1_pusch_serving_cell_config_struct;
+
+typedef struct
+{
+ kal_bool group_hopping_enabled_transform_precoding;
+ kal_uint8 time_domain_allocation_num;
+ nl1_pusch_time_domain_resource_allocation_struct time_domain_allocation_list[NL1_PUSCH_UL_ALLOCATION_LIST_SIZE];
+ kal_bool msg3_delta_preamble_valid;
+ kal_int8 msg3_delta_preamble;
+ kal_bool p0_nominal_with_grant_valid;
+ kal_int16 p0_nominal_with_grant;
+} nl1_pusch_config_common_struct;
+
+typedef struct
+{
+ kal_bool data_scrambling_identity_valid;
+ kal_uint16 data_scrambling_identity;
+ kal_bool tx_config_type_valid;
+ nl1_pusch_tx_config_type_enum tx_config_type;
+ kal_bool dmrs_uplink_config_for_mapping_type_a_valid;
+ nl1_dmrs_uplink_config_struct dmrs_uplink_config_for_mapping_type_a;
+ kal_bool dmrs_uplink_config_for_mapping_type_b_valid;
+ nl1_dmrs_uplink_config_struct dmrs_uplink_config_for_mapping_type_b;
+ kal_bool power_control_valid;
+ nl1_pusch_power_control_struct power_control;
+ nl1_pusch_frequency_hopping_enum frequency_hopping;
+ kal_uint8 frequency_hopping_offset_num;
+ kal_uint16 frequency_hopping_offset_list[NL1_PUSCH_FREQ_HOPPING_OFFSET_LIST_SIZE];
+ nl1_pusch_resource_allocation_enum resource_allocation;
+ kal_uint8 time_domain_allocation_num;
+ nl1_pusch_time_domain_resource_allocation_struct time_domain_allocation_list[NL1_PUSCH_UL_ALLOCATION_LIST_SIZE];
+ nl1_aggregation_factor_enum aggregation_factor;
+ nl1_pusch_mcs_table_enum mcs_table;
+ nl1_pusch_mcs_table_enum mcs_table_transform_precoder;
+ kal_bool transform_precoder_valid;
+ kal_bool transform_precoder;
+ nl1_pusch_codebook_subset_enum codebook_subset;
+ nl1_pusch_max_rank_enum max_rank;
+ nl1_pusch_rbg_size_enum rbg_size;
+ kal_bool uci_on_pusch_valid;
+ nl1_uci_on_pusch_struct uci_on_pusch;
+ kal_bool tp_pi2_bpsk;
+} nl1_pusch_config_dedicated_struct;
+
+typedef struct
+{
+ kal_bool pusch_config_common_valid;
+ nl1_pusch_config_common_struct pusch_config_common;
+ kal_bool pusch_config_dedicated_valid;
+ nl1_pusch_config_dedicated_struct pusch_config_dedicated;
+} nl1_pusch_config_struct;
+
+typedef struct
+{
+ kal_uint16 time_domain_offset;
+ kal_uint8 time_domain_allocation;
+ kal_uint8 frequency_domain_allocation[NL1_UL_GRANT_FREQ_DOMAIN_ALLOC_BIT_STRING_LIST_SIZE];
+ kal_uint8 antenna_port;
+ kal_uint8 dmrs_seq_initialization;
+ kal_uint8 precoding_and_number_of_layers;
+ kal_bool srs_resource_indicator_valid;
+ kal_uint8 srs_resource_indicator;
+ kal_uint8 mcs_and_tbs;
+ kal_bool frequency_hopping_offset_valid;
+ kal_uint16 frequency_hopping_offset;
+ kal_uint8 pathloss_reference_index;
+} nl1_rrc_configured_ul_grant_struct;
+
+typedef struct
+{
+ nl1_pusch_frequency_hopping_enum frequency_hopping;
+ nl1_dmrs_uplink_config_struct dmrs_uplink_config;
+ nl1_pusch_mcs_table_enum mcs_table;
+ nl1_pusch_mcs_table_enum mcs_table_transform_precoder;
+ kal_bool uci_on_pusch_valid;
+ nl1_configured_grant_uci_on_pusch_struct uci_on_pusch;
+ nl1_pusch_resource_allocation_enum resource_allocation;
+ nl1_pusch_rbg_size_enum rbg_size;
+ kal_uint8 power_control_loop;
+ kal_uint8 p0_alpha;
+ kal_bool transform_precoder_valid;
+ kal_bool transform_precoder;
+ kal_uint8 harq_process_num;
+ kal_uint8 rep_k;
+ kal_uint8 rep_k_rv;
+ kal_uint32 periodicity;
+ kal_bool configured_grant_timer_valid;
+ kal_uint8 configured_grant_timer;
+ kal_bool rrc_configured_ul_grant_valid;
+ nl1_rrc_configured_ul_grant_struct rrc_configured_ul_grant;
+} nl1_configured_grant_config_struct;
+
+typedef struct
+{
+ kal_bool is_ssb_pathloss_reference_rs;
+ kal_uint8 id_of_pathloss_reference_rs;
+}nl1_srs_resource_set_pathloss_reference_rs_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_id;
+ kal_uint8 resource_id_num;
+ kal_uint8 resource_id_list[NL1_SRS_RESOURCE_PER_SET_LIST_SIZE];
+ nl1_srs_resource_type_enum resource_type;
+ kal_uint8 aperiodic_srs_resource_trigger_num;
+ kal_uint8 aperiodic_srs_resource_trigger_list[NL1_SRS_RESOURCE_SET_APERIODIC_SRS_RESOURCE_TRIGGER_LIST_SIZE];
+ kal_bool csi_rs_valid;
+ kal_uint8 csi_rs;
+ kal_uint8 slot_offset;
+ nl1_srs_resource_set_usage_enum usage;
+ kal_uint8 alpha;
+ kal_int16 p0;
+ kal_bool pathloss_reference_rs_valid;
+ nl1_srs_resource_set_pathloss_reference_rs_struct pathloss_reference_rs;
+ nl1_srs_power_control_adjustment_state_enum power_control_adjustment_state;
+} nl1_srs_resource_set_struct;
+
+typedef struct
+{
+ kal_uint16 periodicity;
+ kal_uint16 offset;
+} nl1_srs_resource_periodicity_and_offset_struct;
+
+typedef struct
+{
+ kal_bool serv_cell_index_valid;
+ kal_uint8 serv_cell_index;
+ nl1_srs_spatial_relation_info_reference_signal_enum reference_signal;
+ kal_uint8 id;
+ kal_uint8 uplink_bwp_id;
+} nl1_srs_spatial_relation_info_struct;
+
+typedef struct
+{
+ kal_uint8 resource_id;
+ nl1_srs_port_num_enum srs_port_num;
+ kal_bool ptrs_port_index_valid;
+ kal_uint8 ptrs_port_index;
+ kal_uint8 transmission_comb;
+ kal_uint8 transmission_comb_offset;
+ kal_uint8 cyclic_shift;
+ kal_uint8 resource_mapping_start_position;
+ kal_uint8 symbol_num;
+ kal_uint8 repetition_factor;
+ kal_uint8 freq_domain_position;
+ kal_uint16 freq_domain_shift;
+ kal_uint8 frequency_hopping_c_srs;
+ kal_uint8 frequency_hopping_b_srs;
+ kal_uint8 frequency_hopping_b_hop;
+ kal_bool group_hopping_enabled;
+ kal_bool sequence_hopping_enabled;
+ nl1_srs_resource_type_enum resource_type;
+ nl1_srs_resource_periodicity_and_offset_struct periodicity_and_offset;
+ kal_uint16 sequence_id;
+ kal_bool spatial_relation_info_valid;
+ nl1_srs_spatial_relation_info_struct spatial_relation_info;
+} nl1_srs_resource_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_num;
+ nl1_srs_resource_set_struct resource_set_list[NL1_SRS_RESOURCE_SET_LIST_SIZE];
+ kal_uint8 resource_num;
+ nl1_srs_resource_struct resource_list[NL1_SRS_RESOURCE_LIST_SIZE];
+ kal_bool accumulation_enabled;
+} nl1_srs_config_struct;
+
+typedef struct
+{
+ kal_uint8 cc_set_index;
+ kal_uint8 cc_index_in_one_cc_set;
+} nl1_srs_cc_set_index_struct;
+
+typedef struct
+{
+ kal_uint8 cc_set_index_num;
+ nl1_srs_cc_set_index_struct cc_set_index_list[NL1_SRS_TPC_PDCCH_SRS_CC_SET_INDEX_LIST_SIZE];
+} nl1_srs_tpc_pdcch_config_struct;
+
+typedef struct
+{
+ nl1_srs_tpc_pdcch_group_type_enum srs_tpc_pdcch_group_type;
+ kal_uint8 trigger_num;
+ nl1_srs_tpc_pdcch_config_struct trigger_list[NL1_SRS_TPC_PDCCH_TRIGGER_LIST_SIZE];
+} nl1_srs_tpc_pdcch_group_struct;
+
+typedef struct
+{
+ kal_bool starting_bit_of_format_2_3_valid;
+ kal_uint8 starting_bit_of_format_2_3;
+ kal_bool field_type_format_2_3_valid;
+ kal_uint8 field_type_format_2_3;
+ kal_bool starting_bit_of_format_2_3_sul_valid;
+ kal_uint8 starting_bit_of_format_2_3_sul;
+} nl1_srs_tpc_command_config_struct;
+
+typedef struct
+{
+ kal_bool is_ssb;
+ kal_uint8 id;
+ kal_uint8 ra_occasion_num;
+ kal_uint16 ra_occasion_list[NL1_RA_OCCASION_LIST_SIZE];
+ kal_bool ra_preamble_index_valid;
+ kal_uint8 ra_preamble_index;
+} nl1_beam_failure_recovery_candidate_beam_rs_struct;
+
+typedef struct
+{
+ kal_bool root_sequence_index_valid;
+ kal_uint8 root_sequence_index;
+ kal_bool rach_config_valid;
+ nl1_rach_config_generic_struct rach_config;
+ kal_bool rsrp_threshold_ssb_valid;
+ kal_uint8 rsrp_threshold_ssb;
+ kal_uint8 candidate_beam_rs_num;
+ nl1_beam_failure_recovery_candidate_beam_rs_struct candidate_beam_rs_list[NL1_BFR_CANDIDATE_BEAM_RS_LIST_NUM];
+ kal_bool ssb_per_rach_occasion_valid;
+ nl1_ssb_per_rach_occasion_enum ssb_per_rach_occasion;
+ kal_bool ra_ssb_occasion_mask_index_valid;
+ kal_uint8 ra_ssb_occasion_mask_index;
+ kal_bool recovery_search_space_valid;
+ kal_uint8 recovery_search_space;
+ kal_bool ra_prioritization_valid;
+ nl1_ra_prioritization_struct ra_prioritization;
+ kal_bool beam_failure_recovery_timer_valid;
+ kal_uint8 beam_failure_recovery_timer;
+ kal_bool msg1_subcarrier_spacing_valid;
+ NR_SCS_TYPE_E msg1_subcarrier_spacing;
+} nl1_beam_failure_recovery_config_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ /* Please use NL1_UL_BWP_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: Generic param
+ * Bit1: RACH
+ * Bit2: PUCCH
+ * Bit3: PUSCH
+ * Bit4: Configured grant
+ * Bit5: SRS
+ * Bit6: BFR
+ */
+ kal_uint32 reconfig_bitmap;
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+ kal_bool rach_config_valid;
+ nl1_rach_config_struct rach_config;
+ kal_bool pucch_config_valid;
+ nl1_pucch_config_struct pucch_config;
+ kal_bool pusch_config_valid;
+ nl1_pusch_config_struct pusch_config;
+ kal_bool configured_grant_config_valid;
+ nl1_configured_grant_config_struct configured_grant_config;
+ kal_bool srs_config_valid;
+ nl1_srs_config_struct srs_config;
+ kal_bool beam_failure_recovery_config_valid;
+ nl1_beam_failure_recovery_config_struct beam_failure_recovery_config;
+} nl1_ul_bwp_struct;
+
+typedef struct
+{
+ kal_bool srs_switch_from_serv_cell_index_valid;
+ kal_uint8 srs_switch_from_serv_cell_index;
+ nl1_srs_switch_from_carrier_enum srs_switch_from_carrier;
+ kal_bool srs_tpc_pdcch_group_valid;
+ nl1_srs_tpc_pdcch_group_struct srs_tpc_pdcch_group;
+ kal_uint8 monitoring_cells_num;
+ kal_uint8 monitoring_cells_list[NL1_MAX_SERVING_CELL_NUM];
+} nl1_srs_carrier_switching_struct;
+
+typedef struct
+{
+ kal_bool serving_cell_config_applied;
+ /* Please use NL1_UL_CONFIG_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: UL frequency
+ * Bit1: UL BWP info
+ * Bit2: PUSCH serving cell
+ * Bit3: SRS carrier switching
+ * Bit4: power boost pi2 bpsk
+ * Bit5: UE specific carriers for different numerologies
+ */
+ kal_uint32 reconfig_bitmap;
+ nl1_ul_frequency_info_struct ul_frequency_info;
+ nl1_ul_bwp_struct initial_ul_bwp;
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ kal_uint8 additional_ul_bwp_list_num;
+ nl1_ul_bwp_struct *p_additional_ul_bwp_list;
+#else
+ kal_uint8 additional_ul_bwp_num;
+ nl1_ul_bwp_struct additional_ul_bwp_list[NL1_ADDITIONAL_UL_BWP_LIST_SIZE];
+#endif
+ kal_bool first_active_ul_bwp_id_valid;
+ kal_uint8 first_active_ul_bwp_id;
+ kal_bool pusch_serving_cell_config_valid;
+ nl1_pusch_serving_cell_config_struct pusch_serving_cell_config;
+ kal_bool srs_carrier_switching_valid;
+ nl1_srs_carrier_switching_struct srs_carrier_switching;
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ kal_bool power_boost_pi2_bpsk_valid;
+ kal_bool power_boost_pi2_bpsk;
+ kal_uint8 ul_channel_bw_per_scs_num;
+ nl1_scs_specific_carrier_struct ul_channel_bw_per_scs_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#elif (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_bool power_boost_pi2_bpsk_valid;
+ kal_bool power_boost_pi2_bpsk;
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#endif
+} nl1_ul_config_struct;
+
+typedef struct
+{
+ kal_uint16 slot_index;
+ kal_uint8 num_dl_symbols; // range: 0~13, NL1_TDD_UL_DL_SLOT_CONFIG_ALL_DL_SYMBOLS
+ kal_uint8 num_ul_symbols; // range: 0~13, NL1_TDD_UL_DL_SLOT_CONFIG_ALL_UL_SYMBOLS
+} nl1_tdd_ul_dl_slot_config_struct;
+
+typedef struct // 20180529
+{
+ kal_uint16 slot_specific_config_num;
+ nl1_tdd_ul_dl_slot_config_struct slot_specific_config_list[NL1_TDD_UL_DL_SLOT_CONFIG_LIST_SIZE];
+} nl1_tdd_ul_dl_config_dedicated_struct;
+
+typedef struct{
+ kal_uint8 first_pdcch_monitoring_occasions_num;
+ kal_uint16 first_pdcch_monitoring_occasions_list[NL1_PCCH_CONFIG_FIRST_PDCCH_MONITORING_OCCASIONS_LIST_SIZE];
+}nl1_first_pdcch_monitoring_occasion_of_po_struct;
+
+typedef struct
+{
+ kal_uint16 default_paging_cycle;
+ nl1_pcch_config_n_enum n;
+ kal_uint8 pf_offset;
+ kal_uint8 ns;
+ kal_bool first_pdcch_monitoring_occasion_of_po_valid;
+ nl1_first_pdcch_monitoring_occasion_of_po_struct first_pdcch_monitoring_occasion_of_po;
+} nl1_pcch_config_struct;
+
+typedef struct
+{
+ nl1_pcch_config_struct pcch_config;
+ kal_bool ue_specific_paging_cycle_valid;
+ kal_uint16 ue_specific_paging_cycle;
+ kal_bool s_tmsi_5g_valid;
+ kal_uint8 s_tmsi_5g[NL1_PCCH_CONFIG_IDLE_S_TMSI_5G_SIZE];
+ kal_bool i_rnti_valid;
+ kal_uint8 i_rnti[NL1_PCCH_CONFIG_IDLE_I_RNTI_SIZE];
+} nl1_pcch_config_idle_struct;
+
+typedef struct
+{
+ kal_uint8 modification_period_coefficient;
+} nl1_bcch_config_struct;
+
+typedef struct
+{
+ kal_uint16 starting_prb;
+ kal_uint16 prb_num;
+} nl1_csi_freq_occupation_struct;
+
+typedef struct
+{
+ nl1_csi_rs_resource_freq_domain_allocation_row_enum freq_domain_allocation_row;
+ kal_uint8 freq_domain_allocation[NL1_CSI_RS_MAPPING_FREQ_DOMAIN_ALLOC_BIT_STRING_LIST_SIZE];
+ kal_uint8 ports_num;
+ kal_uint8 first_symbol_in_time_domain;
+ kal_bool first_symbol_in_time_domain_2_valid;
+ kal_uint8 first_symbol_in_time_domain_2;
+ nl1_csi_rs_resource_cdm_type_enum cdm_type;
+ nl1_csi_rs_resource_density_enum density;
+ nl1_csi_freq_occupation_struct freq_band;
+} nl1_csi_rs_resource_mapping_struct;
+
+typedef struct
+{
+ kal_uint16 periodicity;
+ kal_uint16 offset;
+} nl1_csi_resource_periodicity_and_offset_struct;
+
+typedef struct
+{
+ kal_uint8 resource_id;
+ nl1_csi_rs_resource_mapping_struct resource_mapping;
+ kal_int8 power_control_offset;
+ kal_bool power_control_offset_ss_valid;
+ kal_int8 power_control_offset_ss;
+ kal_uint16 scrambling_id;
+ kal_bool periodicity_and_offset_valid;
+ nl1_csi_resource_periodicity_and_offset_struct periodicity_and_offset;
+ kal_bool qcl_info_periodic_csi_rs_valid;
+ kal_uint8 qcl_info_periodic_csi_rs;
+} nl1_nzp_csi_rs_resource_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_id;
+ kal_uint8 resource_num;
+ kal_uint8 resource_list[NL1_NZP_CSI_RS_RESOURCES_PER_SET_LIST_SIZE];
+ kal_bool repetition;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ nl1_nzp_csi_rs_resource_set_aperiodic_triggering_offset_enum aperiodic_triggering_offset;
+#else
+ kal_uint8 aperiodic_triggering_offset;
+#endif
+ kal_bool trs_info;
+} nl1_nzp_csi_rs_resource_set_struct;
+
+typedef struct
+{
+ kal_uint8 pattern_type;
+ kal_uint8 subcarrier_location;
+ kal_uint8 symbol_location;
+} nl1_csi_im_resource_element_pattern_struct;
+
+typedef struct
+{
+ kal_uint8 resource_id;
+ kal_bool resource_element_pattern_valid;
+ nl1_csi_im_resource_element_pattern_struct pattern;
+ kal_bool freq_band_valid;
+ nl1_csi_freq_occupation_struct freq_band;
+ kal_bool periodicity_and_offset_valid;
+ nl1_csi_resource_periodicity_and_offset_struct periodicity_and_offset;
+} nl1_csi_im_resource_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_id;
+ kal_uint8 resource_num;
+ kal_uint8 resource_list[NL1_CSI_IM_RS_RESOURCES_PER_SET_LIST_SIZE];
+} nl1_csi_im_resource_set_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_id;
+ kal_uint8 resource_num;
+ kal_uint8 resource_list[NL1_CSI_SSB_RESOURCES_PER_SET_LIST_SIZE];
+} nl1_csi_ssb_resource_set_struct;
+
+typedef struct
+{
+ kal_uint8 resource_config_id;
+ kal_uint8 nzp_csi_rs_resource_set_num;
+ kal_uint8 nzp_csi_rs_resource_set_list[NL1_NZP_CSI_RS_RESOURCES_SET_LIST_SIZE];
+ kal_uint8 csi_ssb_resource_set_num;
+ kal_uint8 csi_ssb_resource_set_list[NL1_CSI_SSB_RESOURCES_SET_LIST_SIZE];
+ kal_uint8 csi_im_resource_set_num;
+ kal_uint8 csi_im_resource_set_list[NL1_CSI_IM_RESOURCES_SET_LIST_SIZE];
+ kal_uint8 bwp_id;
+ nl1_csi_resource_config_type_enum type;
+} nl1_csi_resource_config_struct;
+
+typedef struct
+{
+ kal_uint16 periodicity;
+ kal_uint16 offset;
+} nl1_csi_report_periodicity_and_offset_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ kal_uint8 resource_id;
+} nl1_csi_pucch_resource_struct ;
+
+typedef struct
+{
+ nl1_csi_report_periodicity_and_offset_struct slot_config;
+ kal_uint8 pucch_csi_resource_num;
+ nl1_csi_pucch_resource_struct pucch_csi_resource_list[NL1_CSI_PUCCH_RESOURCE_LIST_SIZE];
+} nl1_csi_report_config_pucch_struct;
+
+typedef struct
+{
+ kal_uint16 report_slot_config;
+ kal_uint8 slot_offset_num;
+ kal_uint8 slot_offset_list[NL1_CSI_REPORT_SPS_ON_PUSCH_SLOT_OFFSET_LIST_SIZE];
+ kal_uint8 p0_alpha;
+} nl1_csi_report_config_semi_persistent_on_pusch_struct;
+
+typedef struct
+{
+ kal_uint8 slot_offset_num;
+ kal_uint8 slot_offset_list[NL1_CSI_REPORT_APERIODIC_SLOT_OFFSET_LIST_SIZE];
+} nl1_csi_report_config_aperiodic_struct;
+
+typedef struct
+{
+ kal_bool more_than_two_antenna_ports;
+ kal_uint8 n1;
+ kal_uint8 n2;
+ kal_uint8 codebook_subset_restriction[NL1_CODEBOOK_TYPE_I_SINGLE_PANEL_SUBSET_RESTRICTION_BIT_STRING_LIST_SIZE];
+ kal_bool codebook_subset_restriction_i2_valid;
+ kal_uint8 codebook_subset_restriction_i2[NL1_CODEBOOK_TYPE_I_SINGLE_PANEL_SUBSET_RESTRICTION_I2_BIT_STRING_LIST_SIZE];
+ kal_uint8 ri_restriction;
+ kal_uint8 codebook_mode;
+} nl1_codebook_type_i_single_panel_struct;
+
+typedef struct
+{
+ kal_uint8 ng;
+ kal_uint8 n1;
+ kal_uint8 n2;
+ kal_uint8 codebook_subset_restriction[NL1_CODEBOOK_TYPE_I_MULTI_PANEL_SUBSET_RESTRICTION_BIT_STRING_LIST_SIZE];
+ kal_uint8 ri_restriction;
+ kal_uint8 codebook_mode;
+} nl1_codebook_type_i_multi_panel_struct;
+
+typedef struct
+{
+ kal_uint8 n1;
+ kal_uint8 n2;
+ kal_uint8 codebook_subset_restriction[NL1_CODEBOOK_TYPE_II_SUBSET_RESTRICTION_BIT_STRING_LIST_SIZE];
+ kal_uint8 ri_restriction;
+ kal_uint8 phase_alphabet_size;
+ kal_bool subband_amplitude;
+ kal_uint8 number_of_beams;
+} nl1_codebook_type_ii_struct;
+
+typedef struct
+{
+ kal_bool sampling_size_valid;
+ kal_uint8 sampling_size;
+ kal_uint8 ri_restriction;
+ kal_uint8 phase_alphabet_size;
+ kal_bool subband_amplitude;
+ kal_uint8 number_of_beams;
+} nl1_codebook_type_ii_port_selection_struct;
+
+typedef struct
+{
+ nl1_codebook_type_enum codebook_type;
+ nl1_codebook_type_i_single_panel_struct type_i_single_panel;
+ nl1_codebook_type_i_multi_panel_struct type_i_multi_panel;
+ nl1_codebook_type_ii_struct type_ii;
+ nl1_codebook_type_ii_port_selection_struct type_ii_port_selection;
+} nl1_codebook_config_struct;
+
+typedef struct
+{
+ kal_uint8 port_index_num;
+ kal_uint8 port_index_list[NL1_CSI_RPT_NON_PMI_PORT_INDEX_LIST_SIZE];
+} nl1_csi_report_non_pmi_port_index_list_struct;
+
+typedef struct
+{
+ kal_uint8 rank_num;
+ nl1_csi_report_non_pmi_port_index_list_struct rank_list[NL1_CSI_RPT_NON_PMI_PORT_IND_RANK_LIST_SIZE];
+} nl1_csi_report_non_pmi_port_indication_struct;
+
+typedef struct
+{
+ kal_uint8 report_config_id;
+ kal_uint8 carrier;
+ kal_uint8 resources_for_channel_measurements;
+ kal_bool csi_im_resources_for_interference_measurements_valid;
+ kal_uint8 csi_im_resources_for_interference_measurements;
+ kal_bool nzp_csi_rs_resources_for_interference_measurements_valid;
+ kal_uint8 nzp_csi_rs_resources_for_interference_measurements;
+ nl1_csi_report_config_type_enum report_config_type;
+ nl1_csi_report_config_pucch_struct pucch;
+ nl1_csi_report_config_semi_persistent_on_pusch_struct semi_persistent_on_pusch;
+ nl1_csi_report_config_aperiodic_struct aperiodic;
+ nl1_csi_report_quantity_enum report_quantity;
+ kal_bool pdsch_bundle_size_valid;
+ kal_uint8 pdsch_bundle_size;
+ kal_bool wideband_cqi_valid;
+ kal_bool wideband_cqi;
+ kal_bool wideband_pmi_valid;
+ kal_bool wideband_pmi;
+ kal_uint8 subbands_num;
+ kal_uint8 subbands[NL1_CSI_RPT_SUBBANDS_BIT_STRING_LIST_SIZE];
+ kal_bool time_domain_meas_restriction_for_channel_measurements;
+ kal_bool time_domain_meas_restriction_for_interference_measurements;
+ kal_bool codebook_config_valid;
+ nl1_codebook_config_struct codebook_config;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+#else
+ kal_bool cqi_per_report_num_valid;
+ kal_uint8 cqi_per_report_num;
+#endif
+ kal_bool group_based_beam_reporting_enabled;
+ kal_uint8 reported_rs_num;
+ kal_bool cqi_table_valid;
+ kal_uint8 cqi_table;
+ kal_uint8 subband_size;
+ kal_uint8 non_pmi_port_indication_num;
+ nl1_csi_report_non_pmi_port_indication_struct non_pmi_port_indication_list[NL1_CSI_RPT_NON_PMI_PORT_INDICATION_LIST_SIZE];
+} nl1_csi_report_config_struct;
+
+typedef struct
+{
+ kal_uint8 report_config_id;
+ kal_bool resource_type_for_channel_measurements_is_nzp_csi_rs;
+ kal_uint8 nzp_csi_rs_resource_set_index_for_channel_measurements;
+ kal_uint8 qcl_info_num;
+ kal_uint8 qcl_info_list[NL1_CSI_ASSOCIATED_RPT_QCL_INFO_LIST_SIZE];
+ kal_uint8 csi_ssb_resource_set_index_for_channel_measurements;
+ kal_bool csi_im_resource_set_index_for_interference_measurements_valid;
+ kal_uint8 csi_im_resource_set_index_for_interference_measurements;
+ kal_bool nzp_csi_rs_resource_set_index_for_interference_measurements_valid;
+ kal_uint8 nzp_csi_rs_resource_set_index_for_interference_measurements;
+} nl1_csi_associated_report_config_info_struct;
+
+typedef struct
+{
+ kal_uint8 associated_report_config_info_num;
+ nl1_csi_associated_report_config_info_struct associated_report_config_info_list[NL1_CSI_RPT_APERIODIC_TRIGGER_STATE_ASSOC_REPORT_CONFIG_INFO_LIST_SIZE];
+} nl1_csi_aperiodic_trigger_state_struct;
+
+typedef struct
+{
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ kal_uint8 nzp_csi_rs_resource_list_num;
+ nl1_nzp_csi_rs_resource_struct *p_nzp_csi_rs_resource_list;
+ kal_uint8 nzp_csi_rs_resource_set_list_num;
+ nl1_nzp_csi_rs_resource_set_struct *p_nzp_csi_rs_resource_set_list;
+ kal_uint8 csi_im_resource_num;
+ nl1_csi_im_resource_struct csi_im_resource_list[NL1_CSI_IM_RESOURCE_LIST_SIZE];
+ kal_uint8 csi_im_resource_set_num;
+ nl1_csi_im_resource_set_struct csi_im_resource_set_list[NL1_CSI_IM_RESOURCE_SET_LIST_SIZE];
+ kal_uint8 csi_ssb_resource_set_list_num;
+ nl1_csi_ssb_resource_set_struct *p_csi_ssb_resource_set_list;
+ kal_uint8 csi_resource_config_list_num;
+ nl1_csi_resource_config_struct *p_csi_resource_config_list;
+ kal_uint8 csi_report_config_list_num;
+ nl1_csi_report_config_struct *p_csi_report_config_list;
+ kal_bool report_trigger_size_valid;
+ kal_uint8 report_trigger_size;
+ kal_uint8 aperiodic_trigger_state_list_num;
+ nl1_csi_aperiodic_trigger_state_struct *p_aperiodic_trigger_state_list;
+ kal_uint8 semi_persistent_on_pusch_trigger_state_num;
+ kal_uint8 semi_persistent_on_pusch_trigger_state_list[NL1_CSI_SPS_ON_PUSCH_TRIGGER_STATE_LIST_SIZE];
+#else
+ kal_uint8 nzp_csi_rs_resource_num;
+ nl1_nzp_csi_rs_resource_struct nzp_csi_rs_resource_list[NL1_NZP_CSI_RS_RESOURCE_LIST_SIZE];
+ kal_uint8 nzp_csi_rs_resource_set_num;
+ nl1_nzp_csi_rs_resource_set_struct nzp_csi_rs_resource_set_list[NL1_NZP_CSI_RS_RESOURCE_SET_LIST_SIZE];
+ kal_uint8 csi_im_resource_num;
+ nl1_csi_im_resource_struct csi_im_resource_list[NL1_CSI_IM_RESOURCE_LIST_SIZE];
+ kal_uint8 csi_im_resource_set_num;
+ nl1_csi_im_resource_set_struct csi_im_resource_set_list[NL1_CSI_IM_RESOURCE_SET_LIST_SIZE];
+ kal_uint8 csi_ssb_resource_set_num;
+ nl1_csi_ssb_resource_set_struct csi_ssb_resource_set_list[NL1_CSI_SSB_RESOURCE_LIST_SIZE];
+ kal_uint8 csi_resource_config_num;
+ nl1_csi_resource_config_struct csi_resource_config_list[NL1_CSI_RESOURCE_CONFIG_LIST_SIZE];
+ kal_uint8 csi_report_config_num;
+ nl1_csi_report_config_struct csi_report_config_list[NL1_CSI_REPORT_CONFIG_LIST_SIZE];
+ kal_bool report_trigger_size_valid;
+ kal_uint8 report_trigger_size;
+ kal_uint8 aperiodic_trigger_state_num;
+ nl1_csi_aperiodic_trigger_state_struct aperiodic_trigger_state_list[NL1_CSI_RPT_APERIODIC_TRIGGER_STATE_LIST_SIZE];
+ kal_uint8 semi_persistent_on_pusch_trigger_state_num;
+ kal_uint8 semi_persistent_on_pusch_trigger_state_list[NL1_CSI_SPS_ON_PUSCH_TRIGGER_STATE_LIST_SIZE];
+#endif
+} nl1_csi_meas_config_struct;
+
+typedef struct
+{
+ nl1_pdsch_max_code_block_groups_per_tb_enum max_code_block_groups_per_transport_block;
+ kal_bool code_block_group_flush_indicator;
+} nl1_pdsch_code_block_group_transmission_struct;
+
+typedef struct
+{
+ kal_uint8 control_resource_set_id;
+ kal_uint8 freq_domain_resources[NL1_CONTROL_RESOURCE_SET_FREQ_DOMAIN_RESOURCE_BIT_STRING_LIST_SIZE];
+ kal_uint8 duration;
+ kal_bool is_cce_reg_mapping_interleaved;
+ nl1_control_resource_set_reg_bundle_size_enum reg_bundle_size;
+ nl1_control_resource_set_interleaver_size_enum interleaver_size;
+ kal_bool shift_index_valid;
+ kal_uint16 shift_index;
+ nl1_control_resource_set_precoder_granularity_enum precoder_granularity;
+ kal_uint8 pdcch_tci_states_num;
+ kal_uint8 pdcch_tci_states_list[NL1_PDCCH_TCI_STATE_LIST_SIZE];
+ kal_bool is_tci_present_in_dci;
+ kal_bool pdcch_dmrs_scrambling_id_valid;
+ kal_uint16 pdcch_dmrs_scrambling_id;
+
+} nl1_control_resource_set_struct;
+
+typedef struct
+{
+ kal_uint8 search_space_id;
+ kal_uint8 control_resource_set_id;
+ nl1_search_space_monitoring_slot_periodicity_enum monitoring_slot_periodicity; //1,2,4,5,8,10,16,20,40,80,160,320,640,1280,2560
+ kal_uint16 monitoring_slot_offset;
+ kal_uint16 duration;
+ kal_uint8 monitoring_symbols_within_slot[NL1_MONITORING_SYMBOLS_WITHIN_SLOT_BIT_STRING_LIST_SIZE];
+ kal_uint8 candidate_num_for_aggregation_level_1;
+ kal_uint8 candidate_num_for_aggregation_level_2;
+ kal_uint8 candidate_num_for_aggregation_level_4;
+ kal_uint8 candidate_num_for_aggregation_level_8;
+ kal_uint8 candidate_num_for_aggregation_level_16;
+ kal_bool is_css;
+ kal_bool monitor_dci_format_0_0_and_1_0;
+ kal_bool monitor_dci_format_0_1_and_1_1;
+ kal_bool monitor_dci_format_2_0;
+ kal_uint8 dci_format_2_0_candidate_num_for_aggregation_level_1;
+ kal_uint8 dci_format_2_0_candidate_num_for_aggregation_level_2;
+ kal_uint8 dci_format_2_0_candidate_num_for_aggregation_level_4;
+ kal_uint8 dci_format_2_0_candidate_num_for_aggregation_level_8;
+ kal_uint8 dci_format_2_0_candidate_num_for_aggregation_level_16;
+ kal_bool monitor_dci_format_2_1;
+ kal_bool monitor_dci_format_2_2;
+ kal_bool monitor_dci_format_2_3;
+ kal_uint8 dci_format_2_3_monitoring_periodicity;
+ kal_uint8 dci_format_2_3_candidate_num;
+} nl1_search_space_struct;
+
+typedef struct
+{
+ kal_uint8 serv_cell_index;
+ kal_uint8 position_in_dci;
+} nl1_int_config_per_cell_struct;
+
+typedef struct
+{
+ kal_uint16 int_rnti;
+ nl1_downlink_preemption_time_frequency_set_enum time_frequency_set;
+ kal_uint8 dci_payload_size;
+ kal_uint8 int_config_per_cell_num;
+ nl1_int_config_per_cell_struct int_config_per_cell_list[NL1_MAX_SERVING_CELL_NUM];
+} nl1_downlink_preemption_config_struct;
+
+//20180529
+typedef struct
+{
+ kal_uint8 serv_cell_index;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ kal_bool subcarrier_spacing_2_valid;
+ NR_SCS_TYPE_E subcarrier_spacing_2;
+ kal_uint8 position_in_dci;
+ kal_uint16 slot_format_num;
+ kal_uint16 slot_format_combination_id_list[NL1_SLOT_FORMAT_COMBINATIONS_LIST_SIZE];
+ kal_uint8 slot_format_list[NL1_SLOT_FORMAT_COMBINATIONS_LIST_SIZE];
+} nl1_slot_format_combinations_struct;
+
+typedef struct
+{
+ kal_uint16 sfi_rnti;
+ kal_uint16 dci_payload_size;
+} nl1_slot_format_indicator_struct;
+
+typedef struct
+{
+ kal_uint8 serv_cell_index;
+ nl1_slot_format_combinations_struct slot_format_combinations;
+} nl1_slot_format_combinations_per_cell_struct;
+
+typedef struct
+{
+ kal_bool tpc_index_valid;
+ kal_uint8 tpc_index;
+ kal_bool tpc_index_sul_valid;
+ kal_uint8 tpc_index_sul;
+ kal_bool target_cell_valid;
+ kal_uint8 target_cell;
+} nl1_pusch_tpc_command_config_struct;
+
+typedef struct
+{
+ kal_bool tpc_index_pcell_valid;
+ kal_uint8 tpc_index_pcell;
+ kal_bool tpc_index_pucch_scell_valid;
+ kal_uint8 tpc_index_pucch_scell;
+} nl1_pucch_tpc_command_config_struct;
+
+typedef struct
+{
+ kal_bool control_resource_set_zero_valid;
+ kal_uint8 control_resource_set_zero;
+ kal_bool common_control_resource_set_valid;
+ nl1_control_resource_set_struct common_control_resource_set;
+ kal_bool search_space_zero_valid;
+ kal_uint8 search_space_zero;
+ kal_uint8 common_search_space_num;
+ nl1_search_space_struct common_search_space_list[NL1_PDCCH_COMMON_SEARCH_SPACE_LIST_SIZE];
+ kal_bool sib1_search_space_id_valid;
+ kal_uint8 sib1_search_space_id;
+ kal_bool other_si_search_space_id_valid;
+ kal_uint8 other_si_search_space_id;
+ kal_bool paging_search_space_id_valid;
+ kal_uint8 paging_search_space_id;
+ kal_bool ra_search_space_id_valid;
+ kal_uint8 ra_search_space_id;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_bool first_pdcch_monitoring_occasion_of_po_valid;
+ nl1_first_pdcch_monitoring_occasion_of_po_struct first_pdcch_monitoring_occasion_of_po;
+#endif
+} nl1_pdcch_config_common_struct;
+
+typedef struct
+{
+ kal_uint8 ue_specific_control_resource_set_num;
+ nl1_control_resource_set_struct ue_specific_control_resource_set_list[NL1_UE_SPECIFIC_CONTROL_RESOURCE_SET_LIST_SIZE];
+ kal_uint8 ue_specific_search_space_num;
+ nl1_search_space_struct ue_specific_search_space_list[NL1_UE_SPECIFIC_SEARCH_SPACE_LIST_SIZE];
+ kal_bool downlink_preemption_config_valid;
+ nl1_downlink_preemption_config_struct downlink_preemption_config;
+ kal_bool pusch_tpc_command_config_valid;
+ nl1_pusch_tpc_command_config_struct pusch_tpc_command_config;
+ kal_bool pucch_tpc_command_config_valid;
+ nl1_pucch_tpc_command_config_struct pucch_tpc_command_config;
+ kal_bool srs_tpc_command_config_valid;
+ nl1_srs_tpc_command_config_struct srs_tpc_command_config;
+} nl1_pdcch_config_dedicated_struct;
+
+typedef struct
+{
+ kal_bool slot_format_indicator_valid;
+ nl1_slot_format_indicator_struct slot_format_indicator;
+ kal_bool slot_format_combinations_valid;
+ nl1_slot_format_combinations_struct slot_format_combinations;
+}nl1_pdcch_serving_cell_config_struct;
+
+typedef struct
+{
+ kal_bool pdcch_config_common_valid;
+ nl1_pdcch_config_common_struct pdcch_config_common;
+ kal_bool pdcch_config_dedicated_valid;
+ nl1_pdcch_config_dedicated_struct pdcch_config_dedicated;
+} nl1_pdcch_config_struct;
+
+typedef struct
+{
+ kal_uint8 k0;
+ nl1_pdsch_mapping_type_enum mapping_type;
+ kal_uint8 start_symbol_and_length;
+} nl1_pdsch_time_domain_resource_allocation_struct;
+
+typedef struct
+{
+ kal_bool frequency_density_valid;
+ kal_uint16 frequency_density[NL1_PTRS_DL_FREQ_DENSITY_LIST_SIZE];
+ kal_bool time_density_valid;
+ kal_uint16 time_density[NL1_PTRS_DL_TIME_DENSITY_LIST_SIZE];
+ kal_uint8 epre_ratio;
+ nl1_ptrs_downlink_resource_element_offset_enum resource_element_offset;
+} nl1_ptrs_downlink_config_struct;
+
+typedef struct
+{
+ nl1_dmrs_type_enum dmrs_type;
+ nl1_dmrs_additional_position_enum dmrs_additional_position;
+ nl1_dmrs_max_length_enum max_length;
+ kal_bool scrambling_id_0_valid;
+ kal_uint16 scrambling_id_0;
+ kal_bool scrambling_id_1_valid;
+ kal_uint16 scrambling_id_1;
+ kal_bool ptrs_config_valid;
+ nl1_ptrs_downlink_config_struct ptrs_config;
+} nl1_dmrs_downlink_config_struct;
+
+typedef struct
+{
+ kal_bool serv_cell_index_valid;
+ kal_uint8 serv_cell_index;
+ kal_bool bwp_id_valid;
+ kal_uint8 bwp_id;
+ nl1_qcl_info_reference_signal_enum reference_signal;
+ kal_uint8 id;
+ nl1_qcl_type_enum qcl_type;
+} nl1_qcl_info_struct;
+
+typedef struct
+{
+ kal_uint8 tci_state_id;
+ nl1_qcl_info_struct qcl_type_1;
+ kal_bool qcl_type_2_valid;
+ nl1_qcl_info_struct qcl_type_2;
+} nl1_tci_state_struct;
+
+typedef struct
+{
+ nl1_rate_match_pattern_periodicity_enum periodicity; //2,4,5,8,10,20,40
+ kal_uint8 slot_pattern[NL1_RATE_MATCH_SLOT_PATTERN_LIST_SIZE];
+} nl1_rate_match_periodicity_and_pattern_struct;
+
+typedef struct
+{
+ kal_uint8 rate_match_pattern_id;
+ nl1_rate_match_pattern_type_enum pattern_type;
+ kal_uint8 resource_blocks[NL1_RATE_MATCH_PATTERN_RESOURCE_BLOCK_BIT_STRING_LIST_SIZE];
+ nl1_rate_match_pattern_symbols_in_rb_enum symbols_in_resource_block_num;
+ kal_uint8 symbols_in_resource_block[NL1_RATE_MATCH_PATTERN_SYMBOLS_IN_RESOURCE_BLOCK_BIT_STRING_LIST_SIZE];
+ nl1_rate_match_periodicity_and_pattern_struct periodicity_and_pattern;
+ kal_uint8 control_resource_set_id;
+ NR_SCS_TYPE_E subcarrier_spacing;
+} nl1_rate_match_pattern_struct;
+
+typedef struct
+{
+ kal_bool is_cell_level_id;
+ kal_uint8 rate_match_pattern_id;
+} nl1_rate_match_pattern_group_struct;
+
+typedef struct
+{
+ kal_uint8 resource_id;
+ nl1_csi_rs_resource_mapping_struct resource_mapping;
+ kal_bool periodicity_and_offset_valid;
+ nl1_csi_resource_periodicity_and_offset_struct periodicity_and_offset;
+} nl1_zp_csi_rs_resource_struct;
+
+typedef struct
+{
+ kal_uint8 resource_set_id;
+ kal_uint8 resource_num;
+ kal_uint8 resource_list[NL1_ZP_CSI_RS_RESOURCE_PER_SET_LIST_SIZE];
+} nl1_zp_csi_rs_resource_set_struct;
+
+typedef struct
+{
+ kal_uint8 time_domain_allocation_num;
+ nl1_pdsch_time_domain_resource_allocation_struct time_domain_allocation_list[NL1_DL_ALLOCATION_LIST_SIZE];
+} nl1_pdsch_config_common_struct;
+
+typedef struct
+{
+ kal_bool data_scrambling_identity_valid;
+ kal_uint16 data_scrambling_identity;
+ kal_bool dmrs_downlink_config_for_mapping_type_a_valid;
+ nl1_dmrs_downlink_config_struct dmrs_downlink_config_for_mapping_type_a;
+ kal_bool dmrs_downlink_config_for_mapping_type_b_valid;
+ nl1_dmrs_downlink_config_struct dmrs_downlink_config_for_mapping_type_b;
+ kal_uint8 tci_state_num;
+ nl1_tci_state_struct tci_state_list[NL1_TCI_STATE_LIST_SIZE];
+ kal_bool vrb_to_prb_interleaver_valid;
+ nl1_vrb_to_prb_interleaver_enum vrb_to_prb_interleaver;
+ nl1_pdsch_resource_allocation_enum resource_allocation;
+ kal_uint8 time_domain_allocation_num;
+ nl1_pdsch_time_domain_resource_allocation_struct time_domain_allocation_list[NL1_DL_ALLOCATION_LIST_SIZE];
+ nl1_aggregation_factor_enum aggregation_factor;
+ kal_uint8 rate_match_pattern_num;
+ nl1_rate_match_pattern_struct rate_match_pattern_list[NL1_RATE_MATCH_PATTERN_BIT_STRING_LIST_SIZE];
+ kal_uint8 group_1_rate_match_pattern_num;
+ nl1_rate_match_pattern_group_struct group_1_rate_match_pattern_list[NL1_RATE_MATCH_PATTERN_GROUP_LIST_SIZE];
+ kal_uint8 group_2_rate_match_pattern_num;
+ nl1_rate_match_pattern_group_struct group_2_rate_match_pattern_list[NL1_RATE_MATCH_PATTERN_GROUP_LIST_SIZE];
+ nl1_pdsch_rbg_size_enum rbg_size;
+ nl1_pdsch_mcs_table_enum mcs_table;
+ kal_bool max_code_words_scheduled_by_dci_valid;
+ nl1_pdsch_max_code_words_by_dci_enum max_code_words_scheduled_by_dci;
+ nl1_pdsch_prb_bundling_type_enum prb_bundling_type;
+ nl1_pdsch_prb_bundle_size_enum prb_bundle_size;
+ nl1_pdsch_prb_bundle_size_set1_enum prb_bundle_size_set_1;
+ nl1_pdsch_prb_bundle_size_set2_enum prb_bundle_size_set_2;
+ kal_uint8 zp_csi_rs_resource_num;
+ nl1_zp_csi_rs_resource_struct zp_csi_rs_resource_list[NL1_ZP_CSI_RS_RESOURCE_LIST_SIZE];
+ kal_uint8 aperiodic_zp_csi_rs_resource_set_num;
+ nl1_zp_csi_rs_resource_set_struct aperiodic_zp_csi_rs_resource_set_list[NL1_ZP_CSI_RS_RESOURCE_SET_LIST_SIZE];
+ kal_uint8 semi_persistent_zp_csi_rs_resource_set_num;
+ nl1_zp_csi_rs_resource_set_struct semi_persistent_zp_csi_rs_resource_set_list[NL1_ZP_CSI_RS_RESOURCE_SET_LIST_SIZE];
+ kal_bool periodic_zp_csi_rs_resource_set_valid;
+ nl1_zp_csi_rs_resource_set_struct periodic_zp_csi_rs_resource_set;
+} nl1_pdsch_config_dedicated_struct;
+
+typedef struct
+{
+ kal_bool pdsch_config_common_valid;
+ nl1_pdsch_config_common_struct pdsch_config_common;
+ kal_bool pdsch_config_dedicated_valid;
+ nl1_pdsch_config_dedicated_struct pdsch_config_dedicated;
+} nl1_pdsch_config_struct;
+
+typedef struct
+{
+ kal_bool code_block_group_transmission_valid;
+ nl1_pdsch_code_block_group_transmission_struct code_block_group_transmission;
+ nl1_x_overhead_enum x_overhead;
+ kal_uint8 pdsch_harq_processes_num;
+ kal_bool pucch_cell_valid;
+ kal_uint8 pucch_cell;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_bool max_mimo_layers_valid;
+ kal_uint8 max_mimo_layers;
+ kal_bool processing_type_2_enabled;
+#endif
+} nl1_pdsch_serving_cell_config_struct;
+
+typedef struct
+{
+ nl1_sps_periodicity_enum periodicity;
+ kal_uint8 harq_process_num;
+ kal_bool n1_pucch_an_valid;
+ kal_uint8 n1_pucch_an;
+ kal_bool mcs_table_valid;
+ nl1_pdsch_mcs_table_enum mcs_table;
+} nl1_sps_config_struct;
+
+typedef struct
+{
+ kal_uint8 rlm_rs_id;
+ nl1_radio_link_monitoring_purpose_enum purpose;
+ kal_bool is_ssb;
+ kal_uint8 reference_signal_id;
+} nl1_radio_link_monitoring_rs_struct;
+
+typedef struct
+{
+ kal_uint8 failure_detection_resource_num;
+ nl1_radio_link_monitoring_rs_struct failure_detection_resource_list[NL1_FAILURE_DETECTION_RESOURCE_LIST_SIZE];
+ kal_bool beam_failure_instance_max_count_valid;
+ kal_uint8 beam_failure_instance_max_count;
+ kal_bool beam_failure_detection_timer_valid;
+ kal_uint8 beam_failure_detection_timer;
+} nl1_radio_link_monitoring_config_struct;
+
+typedef struct
+{
+ kal_uint8 in_one_group;
+ kal_uint8 group_presence;
+} nl1_ssb_positions_in_burst_idle_struct;
+
+typedef struct
+{
+ nl1_ssb_positions_in_burst_bitmap_length_enum length;
+ kal_uint8 ssb_positions_in_burst[NL1_SSB_POSITIONS_IN_BURST_BIT_STRING_LIST_SIZE];
+} nl1_ssb_positions_in_burst_struct;
+
+typedef struct
+{
+ nl1_eutra_mbsfn_radio_frame_allocation_period_enum radio_frame_allocation_period;
+ kal_uint8 radio_frame_allocation_offset;
+ nl1_eutra_mbsfn_subframe_allocation_type_enum subframe_allocation_1_type;
+ kal_uint8 subframe_allocation_1[NL1_EUTRA_MBSFN_SUBFRAME_ALLOCATION_BIT_STRING_LIST_SIZE];
+ kal_bool subframe_allocation_2_valid;
+ nl1_eutra_mbsfn_subframe_allocation_type_enum subframe_allocation_2_type;
+ kal_uint8 subframe_allocation_2;
+} nl1_eutra_mbsfn_subframe_config_struct;
+
+typedef struct
+{
+ kal_uint16 dl_earfcn;
+ nl1_eutra_bandwidth_enum bandwidth;
+ kal_uint8 mbsfn_subframe_config_num;
+ nl1_eutra_mbsfn_subframe_config_struct mbsfn_subframe_config_list[NL1_EUTRA_MBSFN_SUBFRAME_CONFIG_LIST_SIZE];
+ nl1_eutra_crs_ports_num_enum crs_ports_num;
+ kal_uint8 v_shift;
+} nl1_rate_match_pattern_lte_crs_struct;
+
+typedef struct
+{
+ kal_bool scheduled_by_other_cell;
+ kal_bool is_cif_present;
+ kal_uint8 scheduling_cell;
+ kal_uint8 cif_in_scheduling_cell;
+} nl1_cross_carrier_scheduling_config_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ /* Please use NL1_DL_BWP_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: Generic param
+ * Bit1: PDCCH
+ * Bit2: PDSCH
+ * Bit3: SPS
+ * Bit4: RLM
+ */
+ kal_uint32 reconfig_bitmap;
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+ kal_bool pdcch_config_valid;
+ nl1_pdcch_config_struct pdcch_config;
+ kal_bool pdsch_config_valid;
+ nl1_pdsch_config_struct pdsch_config;
+ kal_bool sps_config_valid;
+ nl1_sps_config_struct sps_config;
+ kal_bool radio_link_monitoring_config_valid;
+ nl1_radio_link_monitoring_config_struct radio_link_monitoring_config;
+} nl1_dl_bwp_struct;
+
+typedef struct
+{
+ nl1_dl_ul_transmission_periodicity_enum dl_ul_transmission_periodicity;
+ kal_uint16 dl_slots_num;
+ kal_uint8 dl_symbols_num;
+ kal_uint16 ul_slots_num;
+ kal_uint8 ul_symbols_num;
+}nl1_tdd_ul_dl_pattern_struct;
+
+typedef struct
+{
+ NR_SCS_TYPE_E reference_subcarrier_spacing;
+ nl1_tdd_ul_dl_pattern_struct pattern_1;
+ kal_bool pattern_2_valid;
+ nl1_tdd_ul_dl_pattern_struct pattern_2;
+} nl1_tdd_ul_dl_config_common_struct;
+
+typedef struct
+{
+ kal_bool tdd_ul_dl_config_common_valid;
+ nl1_tdd_ul_dl_config_common_struct tdd_ul_dl_config_common;
+ kal_bool tdd_ul_dl_config_dedicated_valid;
+ nl1_tdd_ul_dl_config_dedicated_struct tdd_ul_dl_config_dedicated;
+} nl1_tdd_ul_dl_config_struct;
+
+typedef struct
+{
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+ kal_bool pdcch_config_valid;
+ nl1_pdcch_config_common_struct pdcch_config;
+ kal_bool pdsch_config_valid;
+ nl1_pdsch_config_common_struct pdsch_config;
+} nl1_dl_bwp_idle_struct;
+
+typedef struct
+{
+ kal_uint16 pci;
+ /* Please use NL1_SERVING_CELL_CONFIG_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * bit0: DL frequency info
+ * bit1: DL BWP info
+ * bit2: UL configuration
+ * bit3: SUL configuration
+ * bit4: Basic physical layer param
+ * bit5: TDD UL/DL configraution
+ * bit6: BWP inactivity timer
+ * bit7: PDCCH serving cell configuration
+ * bit8: PDSCH serving cell configuration
+ * bit9: CSI measurement configuration
+ * bit10: Cross carrier scheduling configuration
+ * bit11: TAG ID
+ * bit12: UE beam lock
+ * bit13: Serving cell meas object ID
+ * bit14: UE specific carriers for different numerologies
+ */
+ kal_uint32 reconfig_bitmap;
+ nl1_dl_frequency_info_struct dl_frequency_info;
+ nl1_dl_bwp_struct initial_dl_bwp;
+ kal_bool ul_config_valid;
+ nl1_ul_config_struct ul_config;
+ kal_bool sul_config_valid;
+ nl1_ul_config_struct sul_config;
+ kal_bool n_timing_advance_offset_valid;
+ nl1_n_timing_advance_offset_enum n_timing_advance_offset;
+ nl1_ssb_positions_in_burst_struct ssb_positions_in_burst;
+ kal_uint16 ssb_periodicity;
+ nl1_dmrs_type_a_position_enum dmrs_type_a_position;
+ kal_bool lte_crs_to_match_around_valid;
+ nl1_rate_match_pattern_lte_crs_struct lte_crs_to_match_around;
+ kal_uint8 rate_match_pattern_num;
+ nl1_rate_match_pattern_struct rate_match_pattern_list[NL1_RATE_MATCH_PATTERN_BIT_STRING_LIST_SIZE];
+ NR_SCS_TYPE_E subcarrier_spacing_ssb;
+ kal_int8 ss_pbch_block_power;
+ kal_bool tdd_ul_dl_config_valid;
+ nl1_tdd_ul_dl_config_struct tdd_ul_dl_config;
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ kal_uint8 additional_dl_bwp_list_num;
+ nl1_dl_bwp_struct *p_additional_dl_bwp_list;
+#else
+ kal_uint8 additional_dl_bwp_num;
+ nl1_dl_bwp_struct additional_dl_bwp_list[NL1_ADDITIONAL_DL_BWP_LIST_SIZE];
+#endif
+ kal_bool first_active_dl_bwp_id_valid;
+ kal_uint8 first_active_dl_bwp_id;
+ kal_bool bwp_inactivity_timer_valid;
+ kal_uint16 bwp_inactivity_timer;
+ kal_bool default_dl_bwp_id_valid;
+ kal_uint8 default_dl_bwp_id;
+ kal_bool pdcch_serving_cell_config_valid;
+ nl1_pdcch_serving_cell_config_struct pdcch_serving_cell_config;
+ kal_bool pdsch_serving_cell_config_valid;
+ nl1_pdsch_serving_cell_config_struct pdsch_serving_cell_config;
+ kal_bool csi_meas_config_valid;
+ nl1_csi_meas_config_struct csi_meas_config;
+ kal_bool cross_carrier_scheduling_config_valid;
+ nl1_cross_carrier_scheduling_config_struct cross_carrier_scheduling_config;
+ kal_uint8 tag_id;
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ //remove struct element
+#else
+ kal_bool ue_beam_lock_function_valid;
+ kal_bool ue_beam_lock_function;
+#endif
+ kal_bool serving_cell_meas_object_id_valid;
+ kal_uint8 serving_cell_meas_object_id;
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ kal_uint8 dl_channel_bw_per_scs_num;
+ nl1_scs_specific_carrier_struct dl_channel_bw_per_scs_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#elif (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#endif
+} nl1_serving_cell_config_struct;
+
+typedef struct
+{
+ kal_uint8 serv_cell_index;
+ kal_bool is_reconfiguration_with_sync;
+ kal_uint16 c_rnti;
+ kal_bool rach_config_dedicated_valid;
+ nl1_rach_config_dedicated_struct rach_config_dedicated;
+ kal_bool smtc_valid;
+ nl1_primary_ssb_mtc_struct smtc;
+ nl1_primary_cell_smtc_timing_reference_cell_enum smtc_timing_reference_cell;
+ /* Please use NL1_PRIMARY_CELL_CONFIG_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: Serving cell configuration
+ * Bit1: RLF timers and constants
+ * Bit2: RLM in-sync/out-of-sync threshold
+ */
+ kal_uint32 reconfig_bitmap;
+ nl1_serving_cell_config_struct serving_cell_config;
+ nl1_rlf_timers_and_constants_struct rlf_timers_and_constants;
+ /*Notes:
+ * The RLM bitmap/rlmInSyncOutOfSyncThreshold is removed from SAP(37.18) because no BLER pair#1 will be used in R15.(R2-1906094)
+ * But the rlmInSyncOutOfSyncThreshold field for 2nd pair of BLER for RLM would be discussed in R16.
+ * For maintenance, keep the RLM bitmap and rlmInSyncOutOfSyncThreshold field in codes for future use.
+ */
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_bool rlm_in_sync_out_of_sync_threshold_valid;
+#endif
+ kal_uint8 rlm_in_sync_out_of_sync_threshold;
+} nl1_primary_cell_config_struct;
+
+typedef struct
+{
+ nl1_scell_modification_status_enum modification_status;
+ kal_uint8 scell_index;
+ kal_bool smtc_valid;
+ nl1_primary_ssb_mtc_struct smtc;
+ nl1_scell_smtc_timing_reference_cell_enum smtc_timing_reference_cell;
+ /* Please use NL1_SCELL_CONFIG_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: serving cell configuration
+ * BIt1: Scell deactivation timer
+ * BIt2: Pathloss reference linking
+ */
+ kal_uint32 reconfig_bitmap;
+ nl1_serving_cell_config_struct serving_cell_config;
+ kal_bool scell_deactivation_timer_valid;
+ kal_uint16 scell_deactivation_timer;
+ kal_bool pathloss_reference_linking_valid;
+ nl1_pathloss_reference_linking_enum pathloss_reference_linking;
+} nl1_scell_config_struct;
+
+/**
+ * The following section for generic NR carrier list structures
+ */
+typedef struct
+{
+ kal_uint32 dl_freq; // in kHz
+ kal_uint32 dl_bw; // in kHz
+ kal_uint32 ul_freq; // in kHz, value 0 means not valid
+ kal_uint32 ul_bw; // in kHz, value 0 means not valid
+ kal_uint32 sul_freq; // in kHz, value 0 means not valid
+ kal_uint32 sul_bw; // in kHz, value 0 means not valid
+} nl1_freq_and_bw_info_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+} nl1_carrier_info_dl_bwp_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+ kal_bool max_rank_valid;
+ nl1_pusch_max_rank_enum max_rank;
+ kal_uint8 srs_resource_num;
+ nl1_srs_port_num_enum srs_port_num_list[NL1_SRS_RESOURCE_LIST_SIZE];
+ kal_bool pusch_config_dedicated_valid;
+ kal_bool pucch_config_valid;
+} nl1_carrier_info_ul_bwp_struct;
+
+typedef struct
+{
+ kal_bool serving_cell_config_applied;
+ kal_uint16 frequency_band;
+ kal_uint32 absolute_frequency_point_a;
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+ kal_bool frequency_shift_7_dot_5_khz;
+ nl1_carrier_info_ul_bwp_struct initial_ul_bwp;
+ kal_uint8 additional_ul_bwp_num;
+ nl1_carrier_info_ul_bwp_struct additional_ul_bwp_list[NL1_ADDITIONAL_UL_BWP_LIST_SIZE];
+ kal_bool max_mimo_layers_valid;
+ kal_uint8 max_mimo_layers;
+ kal_uint8 ul_channel_bw_per_scs_num;
+ nl1_scs_specific_carrier_struct ul_channel_bw_per_scs_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+ kal_bool srs_carrier_switching_valid;
+ kal_bool srs_switch_from_serv_cell_index_valid;
+} nl1_carrier_info_ul_struct;
+
+typedef struct
+{
+ nl1_dl_frequency_info_struct dl_frequency_info;
+ nl1_carrier_info_dl_bwp_struct initial_dl_bwp;
+
+ kal_bool ul_config_valid;
+ nl1_carrier_info_ul_struct ul_config;
+ kal_bool sul_config_valid;
+ nl1_carrier_info_ul_struct sul_config;
+
+ NR_SCS_TYPE_E subcarrier_spacing_ssb;
+ kal_uint8 additional_dl_bwp_num;
+ nl1_carrier_info_dl_bwp_struct additional_dl_bwp_list[NL1_ADDITIONAL_DL_BWP_LIST_SIZE];
+ kal_bool max_mimo_layers_valid;
+ kal_uint8 max_mimo_layers;
+ kal_uint8 dl_channel_bw_per_scs_num;
+ nl1_scs_specific_carrier_struct dl_channel_bw_per_scs_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+ nl1_tdd_ul_dl_config_struct* p_tdd_ul_dl_config;
+ kal_uint8 serv_cell_index;
+} nl1_carrier_info_struct;
+
+typedef struct
+{
+ NR_SCS_TYPE_E scs;
+ kal_uint32 bw; /* in kHz */
+} nl1_carrier_bw_scs_info_struct;
+
+typedef struct
+{
+ kal_uint16 dl_frequency_band;
+ kal_uint8 dl_scs_info_num;
+ nl1_carrier_bw_scs_info_struct dl_scs_info_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+} nl1_carrier_bw_info_struct;
+
+typedef struct
+{
+ kal_uint8 carrier_bw_info_num;
+ nl1_carrier_bw_info_struct carrier_bw_info_list[NRRC_NL1_MAX_SERVING_CELL_NUM];
+} nl1_carrier_bw_info_list_struct;
+
+//#ifdef __GEMINI__
+/**
+ * The following section for DSDA defined structures
+ */
+typedef struct
+{
+ kal_uint8 bwp_id;
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+} nl1_dl_bwp_dsda_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+} nl1_ul_bwp_dsda_struct;
+
+typedef struct
+{
+ nl1_ul_frequency_info_struct ul_frequency_info;
+ nl1_ul_bwp_dsda_struct initial_ul_bwp;
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ kal_uint8 additional_ul_bwp_list_num;
+ nl1_ul_bwp_dsda_struct *p_additional_ul_bwp_list;
+#else
+ kal_uint8 additional_ul_bwp_num;
+ nl1_ul_bwp_dsda_struct additional_ul_bwp_list[NL1_ADDITIONAL_UL_BWP_LIST_SIZE];
+#endif
+
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ kal_uint8 ul_channel_bw_per_scs_num;
+ nl1_scs_specific_carrier_struct ul_channel_bw_per_scs_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#elif (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#endif
+} nl1_ul_config_dsda_struct;
+
+typedef struct
+{
+ nl1_dl_frequency_info_struct dl_frequency_info;
+ nl1_dl_bwp_dsda_struct initial_dl_bwp;
+
+ kal_bool ul_config_valid;
+ nl1_ul_config_dsda_struct ul_config;
+ kal_bool sul_config_valid;
+ nl1_ul_config_dsda_struct sul_config;
+
+ NR_SCS_TYPE_E subcarrier_spacing_ssb;
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ kal_uint8 additional_dl_bwp_list_num;
+ nl1_dl_bwp_dsda_struct *p_additional_dl_bwp_list;
+#else
+ kal_uint8 additional_dl_bwp_num;
+ nl1_dl_bwp_dsda_struct additional_dl_bwp_list[NL1_ADDITIONAL_DL_BWP_LIST_SIZE];
+#endif
+
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ kal_uint8 dl_channel_bw_per_scs_num;
+ nl1_scs_specific_carrier_struct dl_channel_bw_per_scs_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#elif (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_uint8 scs_specific_carrier_num;
+ nl1_scs_specific_carrier_struct scs_specific_carrier_list[NL1_SCS_SPECIFIC_CARRIER_LIST_SIZE];
+#endif
+} nl1_serving_cell_config_dsda_struct;
+
+typedef struct
+{
+ kal_uint8 serv_cell_index;
+ kal_bool is_reconfiguration_with_sync;
+ nl1_serving_cell_config_dsda_struct serving_cell_config;
+} nl1_primary_cell_config_dsda_struct;
+
+typedef struct
+{
+ kal_uint8 scell_index;
+ nl1_serving_cell_config_dsda_struct serving_cell_config;
+} nl1_scell_config_dsda_struct;
+//#endif /* __GEMINI__ */
+
+/*** meas_config related - Start ***/
+typedef struct
+{
+ kal_uint8 meas_object_index; /* Range: 0..32(NR_MAX_MEAS_OBJECT_ID_NUM-1), INVALID: 0xFF */
+ kal_uint8 report_config_index; /* Range: 0..63, INVALID: 0xFF */
+} nl1_meas_id_struct;
+
+typedef struct
+{
+ /* Range: 4(short bitmap for sub 3 GHz),8(medium bitmap for 3-6 GHz),
+ 64(long bitmap for above 6 GHz) */
+ kal_uint8 bits_num;
+ kal_uint8 bitmap[NRRC_NL1_SSB_TO_MEASURE_MAX_BYTE];
+} nl1_ssb_to_measure_struct;
+
+typedef struct
+{
+ kal_uint8 periodicity; /* Range: 5(sf5),10(sf10),20(sf20),40(sf40),80(sf80),160(sf160) */
+ kal_uint8 offset; /* Range: 0..159 */
+} nl1_meas_object_nr_smtc_1_periodicity_and_offset_struct;
+
+typedef struct
+{
+ kal_uint8 pci_num; /* Range: 0..NR_MAX_PCI_PER_SMTC */
+ kal_uint16 pci_list[NR_MAX_PCI_PER_SMTC]; /* Range: 0..1007 */
+ kal_uint8 periodicity; /* Range: 5(sf5),10(sf10),20(sf20),40(sf40),80(sf80) */
+} nl1_secondary_ssb_mtc_struct;
+
+typedef struct
+{
+ kal_uint8 bits_num; /* Range: 1..80 */
+ kal_uint8 measurement_slots_bitmap[NRRC_NL1_SS_RSSI_MEASUREMENT_SLOTS_MAX_BYTE];
+ kal_uint8 end_symbol; /* Range: 0..3. */
+} nl1_ss_rssi_measurement_struct;
+
+typedef struct
+{
+ kal_bool ssb_to_measure_valid;
+ nl1_ssb_to_measure_struct ssb_to_measure;
+ kal_bool derive_ssb_index_from_cell; /* Indicates whether the UE can utilize serving cell timing to derive the index of SS block transmitted by neighbour cell */
+ kal_bool ss_rssi_measurement_valid;
+ nl1_ss_rssi_measurement_struct ss_rssi_measurement;
+} nl1_meas_object_nr_ssb_config_mobility_struct;
+
+typedef struct
+{
+ kal_uint16 prb_num; /* Range: 24,48,96,192,264. Allowed size of the measurement BW in PRBs */
+ kal_uint16 start_prb; /* Range: 0..2169. Starting PRB index of the measurement bandwidth */
+} nl1_meas_object_nr_csi_rs_measurement_bw_struct;
+
+typedef struct
+{
+ kal_uint8 ssb_index; /* Range: 0..63 */
+ kal_bool is_quasi_colocated;
+} nl1_meas_object_nr_csi_rs_resource_associated_ssb_struct;
+
+typedef struct
+{
+ kal_uint8 row; /* Range: 4(row1),12(row2). INVALID: 0 */
+ kal_uint8 bitmap[NL1_MEAS_OBJECT_NR_CSI_RS_RESOURCE_FREQUENCY_DOMAIN_ALLOCATION_MAX_BYTE];
+} nl1_meas_object_nr_csi_rs_resource_frequency_domain_allocation_struct;
+
+typedef struct
+{
+ kal_uint8 csi_rs_index; /* Range: 0..NR_MAX_CSI_RS_RESOURCE_RRM_NUM-1 */
+ /* [MEAS Size Reduction] From CSI-RS-CellMobility */
+ kal_uint16 cell_id; /* Range: 0..1007 */
+ nl1_meas_object_nr_csi_rs_measurement_bw_struct csi_rs_measurements_bw;
+ kal_bool density_valid;
+ kal_uint8 density; /* Range: 1(d1),3(d3). Frequency domain density for the 1-port CSI-RS for L3 mobility */
+ /* periodicity and slot offset for periodic/semi-persistent CSI-RS */
+ kal_uint8 periodicity; /* Range: 4,5,10,20,40 */
+ kal_uint16 offset; /* Range: 0..319 */
+ /* Each CSI-RS resource may be associated with one SSB. If such SSB is indicated, the NW also indicates whether the UE may assume
+ quasi-colocation of this SSB with this CSI-RS resource. */
+ kal_bool associated_ssb_valid;
+ nl1_meas_object_nr_csi_rs_resource_associated_ssb_struct associated_ssb; /* Valid when is_associatedSSB_valid set to KAL_TRUE */
+ /* Frequency domain allocation within a physical resource block */
+ nl1_meas_object_nr_csi_rs_resource_frequency_domain_allocation_struct frequency_domain_allocation;
+ /* Time domain allocation within a physical resource block. The field indicates the first OFDM symbol in the PRB used for CSI-RS */
+ kal_uint8 first_ofdm_symbol_in_time_domain; /* Range: 0..13 */
+ /* Scrambling ID for CSI-RS */
+ kal_uint16 sequence_generation_config; /* Range: 0..1023 */
+} nl1_meas_object_nr_csi_rs_resource_mobility_struct;
+
+#if 0 // [MEAS Size Reduction] merge to nl1_meas_object_nr_csi_rs_resource_mobility_struct
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef struct
+{
+ NR_SCS_TYPE_E subcarrier_spacing;
+
+ /* [MEAS Size Reduction] Merge 2-dimension arrary (96*96) to 1-dimension (96) */
+ kal_uint8 csi_rs_resource_num; /* Range: 1..NR_MAX_CSI_RS_RESOURCE_RRM_NUM */
+ nl1_meas_object_nr_csi_rs_resource_mobility_struct csi_rs_resource_list[NR_MAX_CSI_RS_RESOURCE_RRM_NUM];
+ kal_bool ref_serv_cell_index_valid;
+ kal_uint8 ref_serv_cell_index;
+} nl1_meas_object_nr_csi_rs_resource_config_mobility_struct;
+
+typedef struct
+{
+ kal_bool ssb_config_mobility_valid;
+ nl1_meas_object_nr_ssb_config_mobility_struct ssb_config_mobility; /* Valid when ssb_config_mobility_valid set to KAL_TRUE */
+
+ kal_bool csi_rs_resource_config_mobility_valid;
+ nl1_meas_object_nr_csi_rs_resource_config_mobility_struct csi_rs_resource_config_mobility; /* Valid when is_csi_rs_ResourceConfigMobility_valid set to KAL_TRUE */
+} nl1_meas_object_nr_rs_config_struct;
+
+typedef struct
+{
+ kal_uint8 threshold_rsrp; /* Range: 0..127, INVALID: 0xFF */
+ kal_uint8 threshold_rsrq; /* Range: 0..127, INVALID: 0xFF */
+ kal_uint8 threshold_sinr; /* Range: 0..127, INVALID: 0xFF */
+} nl1_nr_threshold_struct;
+
+typedef struct
+{
+ kal_int8 rsrp_offset_ssb; /* Range: -24..24 */
+ kal_int8 rsrq_offset_ssb; /* Range: -24..24 */
+ kal_int8 sinr_offset_ssb; /* Range: -24..24 */
+ kal_int8 rsrp_offset_csi_rs; /* Range: -24..24 */
+ kal_int8 rsrq_offset_csi_rs; /* Range: -24..24 */
+ kal_int8 sinr_offset_csi_rs; /* Range: -24..24 */
+} nl1_meas_object_nr_q_offset_range_list_struct;
+
+typedef struct
+{
+ kal_uint16 pci; /* Range: 0..1007 */
+ nl1_meas_object_nr_q_offset_range_list_struct cell_individual_offset;
+} nl1_meas_object_nr_cell_struct;
+
+typedef struct
+{
+ kal_uint16 start; /* Range: 0..1007, INVALID: 0xFFFF */
+ kal_uint16 range; /* Range: 1,4,8,12,16,24,32,48,64,84,96,128,168,252,504,1008. INVALID: 0 */
+} nl1_pci_range_struct;
+
+typedef struct
+{
+ kal_uint32 ssb_frequency; /* INVALID: 0xFFFFFFFF */
+ kal_uint16 ssb_frequency_band;
+ kal_bool ssb_subcarrier_spacing_valid;
+ NR_SCS_TYPE_E ssb_subcarrier_spacing;
+ kal_bool smtc_1_valid;
+ nl1_primary_ssb_mtc_struct smtc_1; /* Periodicity and offset of the measurement window in which to receive SS/PBCH blocks */
+ kal_bool smtc_2_valid;
+ nl1_secondary_ssb_mtc_struct smtc_2; /* Secondary measurement timing confguration for explicitly signalled PCIs. It uses the offset and duration from smtc_1. It is supported only for intra-frequency measurements in RRC CONNECTED. */
+ kal_uint32 ref_freq_csi_rs; /* INVALID: 0xFFFFFFFF */
+ /* RS configuration (e.g. SMTC window, CSI-RS resource, etc.) */
+ nl1_meas_object_nr_rs_config_struct reference_signal_config;
+ /* Consolidation of L1 measurements per RS index */
+ nl1_nr_threshold_struct abs_thresh_ss_blocks_consolidation;
+ nl1_nr_threshold_struct abs_thresh_csi_rs_consolidation;
+ /* Config for cell measurement derivation */
+ kal_uint8 ss_blocks_to_average_num; /* Range: 2..16(NR_MAX_SS_BLOCK_TO_AVERAGE_NUM), INVALID: 0 */
+ kal_uint8 csi_rs_resources_to_average_num; /* Range: 2..16(MAX_CSi_RS_RESOURCE_TO_AVERAGE_NUM), INVALID: 0 */
+ /* Filter coefficients applicable to this measurement object */
+ kal_uint8 quantity_config_index; /* Range: 1..2(NR_MAX_QUANTITY_CONFIG_NUM) */
+ /* Frequency-specific offsets */
+ nl1_meas_object_nr_q_offset_range_list_struct offset_mo;
+ /* cell list */
+ kal_uint8 cell_num; /* Range: 0..NR_MAX_REPORT_CELL_MEAS_NUM */
+ nl1_meas_object_nr_cell_struct cell_list[NR_MAX_REPORT_CELL_MEAS_NUM];
+ /* black cell list */
+ kal_bool black_cell_range_list_valid;
+ nl1_pci_range_struct black_cell_range_list[NR_MAX_REPORT_PCI_RANGE_NUM]; /* Valid when is_black_cell_list_range_valid set to KAL_TRUE */
+ /* white cell list */
+ kal_bool white_cell_range_list_valid;
+ nl1_pci_range_struct white_cell_range_list[NR_MAX_REPORT_PCI_RANGE_NUM]; /* Valid when is_white_cell_list_range_valid set to KAL_TRUE */
+ kal_bool meas_cycle_scell_valid;
+ kal_uint16 meas_cycle_scell;
+} nl1_meas_object_nr_struct;
+
+typedef struct
+{
+ kal_uint16 pci; /* Range: 0..1007 */
+ kal_int8 cell_individual_offset; /* Range: -24..24 */
+} nl1_meas_object_eutra_cell_struct;
+
+typedef struct
+{
+ kal_uint32 carrier_freq; /* INVALID: 0xFFFFFFFF */
+ nl1_eutra_allowed_meas_bandwidth_enum allowed_meas_bandwidth;
+
+ kal_uint8 cell_num; /* Range: 0..NRRC_NL1_MAX_EUTRA_CELL_MEAS_NUM */
+ nl1_meas_object_eutra_cell_struct cell_list[NRRC_NL1_MAX_EUTRA_CELL_MEAS_NUM];
+
+ kal_bool black_cell_range_list_valid;
+ nl1_pci_range_struct black_cell_range_list[NRRC_NL1_MAX_EUTRA_CELL_MEAS_NUM]; /* Valid when is_black_cell_list_range_valid set to KAL_TRUE */
+
+ kal_bool presence_antenna_port_1;
+ kal_int8 q_offset_range; /* Frequency-specific offsets (Range: -24..24) */
+ kal_bool wideband_rsrq_meas; /* can be 'True' only when 'allowed_meas_bandwidth' is '50 resource blocks' or larger. */
+} nl1_meas_object_eutra_struct;
+
+typedef struct
+{
+ nl1_meas_object_type_enum meas_object_type;
+ /* Indicate to NL1 if this is a NR object and measurement should be performed on it
+ Set to KAL_TRUE when all of the following conditions are met
+ - meas_object_type is NL1_MEAS_OBJECT_TYPE_NR (i.e. not NL1_MEAS_OBJECT_TYPE_INVALID or NL1_MEAS_OBJECT_TYPE_EUTRA)
+ - At least be linked to one valid meas id which is not to report CGI */
+ kal_bool is_valid_nr_object;
+ kal_bool is_serving_cell_mo;
+ kal_uint8 meas_object_id; // 1..63
+ union
+ {
+ nl1_meas_object_nr_struct nr_meas_object;
+ nl1_meas_object_eutra_struct eutra_meas_object;
+ } meas_object;
+} nl1_meas_object_struct;
+
+typedef struct
+{
+ kal_bool rsrp;
+ kal_bool rsrq;
+ kal_bool sinr;
+} nl1_report_quantity_struct;
+
+typedef struct
+{
+ nl1_report_config_nr_rs_type_enum rs_type;
+ /* Common reporting config (at least to periodical and eventTriggered) */
+ nl1_report_interval_enum report_interval;
+ kal_uint8 report_amount; /* Range: 1,2,4,8,16,32,64,0xFF(infinity) */
+ /* Cell reporting configuration */
+ nl1_report_quantity_struct report_quantity_cell;
+ kal_uint8 max_report_cells; /* Range: 1..NRRC_NL1_MAX_CELL_REPORT_NUM */
+ /* RS index reporting configuration */
+ kal_bool report_quantity_rs_indexes_valid;
+ nl1_report_quantity_struct report_quantity_rs_indexes; /* Valid when report_quantity_rs_indexes_valid set to KAL_TRUE */
+ kal_bool max_report_rs_indexes_valid;
+ kal_uint8 max_report_rs_indexes; /* Range: 1..NR_MAX_INDEX_TO_REPORT_NUM */
+ kal_bool include_beam_measurements;
+ kal_bool use_white_cell_list;
+} nl1_report_config_nr_periodical_report_config_struct;
+
+typedef struct
+{
+ kal_uint16 cell_for_which_to_report_cgi; /* PCI of NR cell for which to report CGI. Range: 0 - 1007 */
+} nl1_report_config_nr_report_cgi_config_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_enum trigger_quantity_type;
+ /* RSRP - range 0..127
+ RSRQ - range 0..127
+ SINR - range 0..127 */
+ kal_uint8 trigger_quantity;
+} nl1_report_config_trigger_quantity_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_struct a1_threshold;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+} nl1_report_config_nr_event_a1_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_struct a2_threshold;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+} nl1_report_config_nr_event_a2_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_enum trigger_quantity_offset_type;
+ kal_int8 trigger_quantity_offset;
+} nl1_report_config_nr_trigger_quantity_offset_struct;
+
+typedef struct
+{
+ nl1_report_config_nr_trigger_quantity_offset_struct a3_offset;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+ kal_bool use_white_cell_list;
+} nl1_report_config_nr_event_a3_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_struct a4_threshold;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+ kal_bool use_white_cell_list; /* MANDATORY */
+} nl1_report_config_nr_event_a4_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_struct a5_threshold_1;
+ nl1_report_config_trigger_quantity_struct a5_threshold_2;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+ kal_bool use_white_cell_list;
+} nl1_report_config_nr_event_a5_struct;
+
+typedef struct
+{
+ nl1_report_config_nr_trigger_quantity_offset_struct a6_offset;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+ kal_bool use_white_cell_list;
+} nl1_report_config_nr_event_a6_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_struct b1_threshold;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+} nl1_report_config_inter_rat_event_b1_struct;
+
+typedef struct
+{
+ nl1_report_config_trigger_quantity_struct b2_threshold_1;
+ nl1_report_config_trigger_quantity_struct b2_threshold_2;
+ kal_bool report_on_leave;
+ kal_uint8 hysteresis; /* Range: 0..30. The actual value is field value * 0.5 dB. */
+ kal_uint16 time_to_trigger; /* Range: 0,40,64,80,100,128,160,256,320,480,512,640,1024,1280,2560,5120 */
+} nl1_report_config_inter_rat_event_b2_struct;
+
+typedef union
+{
+ nl1_report_config_nr_event_a1_struct a1;
+ nl1_report_config_nr_event_a2_struct a2;
+ nl1_report_config_nr_event_a3_struct a3;
+ nl1_report_config_nr_event_a4_struct a4;
+ nl1_report_config_nr_event_a5_struct a5;
+ nl1_report_config_nr_event_a6_struct a6;
+} nl1_report_config_nr_event_union;
+
+typedef union
+{
+ nl1_report_config_inter_rat_event_b1_struct b1;
+ nl1_report_config_inter_rat_event_b2_struct b2;
+} nl1_report_config_inter_rat_event_union;
+
+typedef struct
+{
+ nl1_report_config_nr_event_id_enum event_id;
+ nl1_report_config_nr_event_union event;
+ nl1_report_config_nr_rs_type_enum rs_type; /* MANDATORY */
+ /* Common reporting config (at least to periodical and eventTriggered) */
+ nl1_report_interval_enum report_interval;
+ kal_uint8 report_amount; /* Range: 1,2,4,8,16,32,64,0xFF(infinity) */
+ /* Cell reporting configuration */
+ nl1_report_quantity_struct report_quantity_cell;
+ kal_uint8 max_report_cells; /* Range: 1..NRRC_NL1_MAX_CELL_REPORT_NUM */
+ /* RS index reporting configuration */
+ kal_bool report_quantity_rs_indexes_valid;
+ nl1_report_quantity_struct report_quantity_rs_indexes; /* Valid when report_quantity_rs_indexes_valid set to KAL_TRUE */
+ kal_bool max_report_rs_indexes_valid;
+ kal_uint8 max_report_rs_indexes; /* Range: 1..NR_MAX_INDEX_TO_REPORT_NUM */
+ kal_bool include_beam_measurements;
+ /* If configured the UE includes the best neighbour cells per serving frequency */
+ kal_bool report_add_neigh_meas;
+} nl1_report_config_nr_event_trigger_config_struct;
+
+typedef struct
+{
+ nl1_report_config_report_type_enum report_type;
+
+ union
+ {
+ nl1_report_config_nr_periodical_report_config_struct periodical_report_config;
+ nl1_report_config_nr_event_trigger_config_struct event_trigger_config;
+ nl1_report_config_nr_report_cgi_config_struct report_cgi_config;
+ } report_config_nr;
+} nl1_report_config_nr_struct;
+
+typedef struct
+{
+ nl1_report_interval_enum report_interval;
+ kal_uint8 report_amount;
+ nl1_report_quantity_struct report_quantity;
+ kal_uint8 max_report_cells;
+
+} nl1_report_config_inter_rat_periodical_report_config_struct;
+
+typedef struct
+{
+ nl1_report_config_inter_rat_event_id_enum event_id;
+ nl1_report_config_inter_rat_event_union event;
+ nl1_report_config_nr_rs_type_enum rs_type;
+ nl1_report_interval_enum report_interval;
+ kal_uint8 report_amount;
+ nl1_report_quantity_struct report_quantity;
+ kal_uint8 max_report_cells;
+
+} nl1_report_config_inter_rat_event_trigger_config_struct;
+
+typedef struct
+{
+ kal_uint16 cell_for_which_to_report_cgi;
+} nl1_report_config_inter_rat_report_cgi_eutra_config_struct;
+
+typedef union
+{
+ nl1_report_config_inter_rat_periodical_report_config_struct periodical_report_config;
+ nl1_report_config_inter_rat_event_trigger_config_struct event_trigger_config;
+ nl1_report_config_inter_rat_report_cgi_eutra_config_struct report_cgi_config;
+
+} nl1_report_config_inter_rat_union;
+
+typedef struct
+{
+ nl1_report_config_report_type_enum report_type;
+ nl1_report_config_inter_rat_union report_config_inter_rat;
+} nl1_report_config_inter_rat_struct;
+
+
+typedef struct
+{
+ nl1_report_config_type_enum report_config_type;
+
+ union
+ {
+ nl1_report_config_nr_struct nr_report_config;
+ nl1_report_config_inter_rat_struct inter_rat_report_config;
+ } report_config;
+} nl1_report_config_struct;
+
+typedef struct
+{
+ nl1_s_measure_config_rsrp_enum config_rsrp_type;
+ kal_uint8 rsrp_range; /* SSB 0..124. CSI_RS 0..124 */
+} nl1_s_measure_config_struct;
+
+typedef struct
+{
+ /* SS Block based L3 filter configurations */
+ kal_uint8 ssb_filter_coefficient_rsrp;
+ kal_uint8 ssb_filter_coefficient_rsrq;
+ kal_uint8 ssb_filter_coefficient_sinr;
+ /* CSI-RS basedL3 filter configurations */
+ kal_uint8 csi_rs_filter_coefficient_rsrp;
+ kal_uint8 csi_rs_filter_coefficient_rsrq;
+ kal_uint8 csi_rs_filter_coefficient_sinr;
+} nl1_quantity_config_nr_rs_struct;
+
+typedef struct
+{
+ nl1_quantity_config_nr_rs_struct quantity_config_cell;
+ kal_bool quantity_config_rs_index_valid;
+ nl1_quantity_config_nr_rs_struct quantity_config_rs_index; /* Valid when quantity_config_rs_index_valid set to KAL_TRUE */
+} nl1_quantity_config_nr_struct;
+
+typedef struct
+{
+ kal_uint8 filter_coefficient_rsrp;
+ kal_uint8 filter_coefficient_rsrq;
+ kal_uint8 filter_coefficient_sinr;
+} nl1_quantity_config_eutra_struct;
+
+typedef struct
+{
+ kal_uint8 quantity_config_nr_num;
+ nl1_quantity_config_nr_struct quantity_config_nr_list[NR_MAX_QUANTITY_CONFIG_NUM];
+ kal_bool quantity_config_eutra_valid;
+ nl1_quantity_config_eutra_struct quantity_config_eutra;
+} nl1_quantity_config_struct;
+
+typedef struct
+{
+ kal_uint8 gap_offset; /* Range: 0..159 */
+ kal_uint8 gap_length; /* Range: 15, 30, 35, 40, 55, 60. The actual value is parameter value divided by 10, e.g. value 35 means 3.5ms. */
+ kal_uint8 gap_repetition_period; /* Range: 20, 40, 80, 160 */
+ kal_uint8 gap_timing_advance; /* Range: 0, 25, 50. The actual value is parameter value divided by 100, e.g. value 25 means 0.25ms.*/
+} nl1_gap_config_struct;
+
+typedef struct
+{
+ kal_bool gap_fr2_valid;
+ nl1_gap_config_struct gap_fr2;
+ kal_bool gap_fr1_valid;
+ nl1_gap_config_struct gap_fr1;
+ kal_bool gap_ue_valid;
+ nl1_gap_config_struct gap_ue;
+} nl1_meas_gap_config_struct;
+
+typedef struct
+{
+ kal_bool gap_sharing_fr2_valid;
+ nl1_meas_gap_sharing_scheme_enum gap_sharing_fr2;
+ kal_bool gap_sharing_fr1_valid;
+ nl1_meas_gap_sharing_scheme_enum gap_sharing_fr1;
+ kal_bool gap_sharing_ue_valid;
+ nl1_meas_gap_sharing_scheme_enum gap_sharing_ue;
+} nl1_meas_gap_sharing_config_struct;
+
+typedef struct
+{
+ kal_uint16 nr_band_indicator;
+ kal_uint32 nr_dl_arfcn;
+ kal_uint16 pci;
+ NR_SCS_TYPE_E scs;
+} nl1_meas_ch_lock_nras_info_struct;
+
+typedef struct
+{
+ kal_bool nras_info_valid;
+ kal_uint8 nras_info_num;
+ nl1_meas_ch_lock_nras_info_struct nras_info_list[NL1_MEAS_CH_LOCK_NR_MAX_NUM];
+} nl1_meas_channel_lock_info_struct;
+
+typedef struct
+{
+ kal_uint32 earfcn;
+ kal_uint16 eas_pci;
+} nl1_meas_ch_lock_eas_info_struct;
+
+typedef struct
+{
+ kal_bool eas_info_valid;
+ kal_uint8 eas_info_num;
+ nl1_meas_ch_lock_eas_info_struct eas_info_list[NL1_MEAS_CH_LOCK_EAS_MAX_NUM];
+} nl1_meas_eas_channel_lock_info_struct;
+
+/* NRRC-NL1MOB related NVRAM parameters,
+ * Included by nrrc_nvram_editor.h*/
+
+typedef struct
+{
+ kal_uint8 ctrl_bmp;
+ kal_int16 srv_rsrp_th; //qdBm
+ kal_int16 srv_rsrq_th; //qdB
+ kal_int16 srv_sinr_th; //qdB
+ kal_int16 nbr_rsrp_th; //qdBm
+ kal_int16 nbr_rsrq_th; //qdB
+ kal_int16 nbr_sinr_th; //qdB
+} nl1_custom_pcell_ncell_threshold_struct;
+
+typedef struct
+{
+ kal_uint16 band;
+ kal_int16 rsrp_th; //qdBm
+ kal_int16 rsrq_th; //qdB
+ kal_int16 sinr_th; //qdB
+} nl1_custom_threshold_per_band_struct;
+
+typedef struct
+{
+ nl1_custom_threshold_per_band_struct per_band_threshold[NL1_THRESHOLD_PER_BAND_LIST_MAX_BAND_NUM];
+} nl1_custom_threshold_per_band_list_struct;
+
+typedef struct
+{
+ kal_int16 rsrp_th;
+ kal_int16 rsrq_th;
+} custom_nrrc_l4c_custom_bar_threshold_struct;
+
+typedef struct
+{
+ kal_uint8 ctrl_bmp;
+ kal_uint16 ping_pong_cell_bar_time; //second
+ kal_uint16 ping_pong_cell_monitor_period; //second
+ kal_uint8 ping_pong_hit_count_threshold;
+} nl1_custom_ping_pong_parameter_struct;
+
+typedef struct
+{
+ kal_uint8 adj_method;//default 0: to more strict; otherwise 1: to relax
+ kal_int16 rsrq_th;//default -15 db; (as sib1 qqualmin)
+ kal_int16 qrxlevmin_good;//default -57 (-114dbm = -456qdbm)
+ kal_int16 qrxlevmin_bad;//default -52 (-104dbm = -416qdbm)
+} custom_qrxlevmin_adjust_struct;
+
+typedef struct
+{
+ kal_uint8 ctrl_bmp;
+ kal_int16 srv_rsrp_th;
+ kal_int16 srv_rsrq_th;
+ kal_int16 srv_sinr_th;
+ kal_int16 good_a2_rsrp_th;
+ kal_int16 bad_a2_rsrp_th;
+} nl1_custom_pcell_a2_threshold_struct;
+
+typedef struct
+{
+ kal_uint16 band;
+ kal_int16 srv_rsrp_th;
+ kal_int16 srv_rsrq_th;
+ kal_int16 srv_sinr_th;
+ kal_int16 good_a2_rsrp_th;
+ kal_int16 bad_a2_rsrp_th;
+} nl1_custom_pcell_a2_threshold_per_band_struct;
+
+typedef struct
+{
+ nl1_custom_pcell_a2_threshold_per_band_struct per_band_threshold[NL1_THRESHOLD_PER_BAND_LIST_MAX_BAND_NUM];
+} nl1_custom_pcell_a2_threshold_per_band_list_struct;
+
+typedef struct
+{
+ kal_int16 sinr_th; //default -40 qdb
+ kal_uint8 timer_th; //default 60 seconds
+ kal_uint8 sinr_hys; //default 8qdb
+} nl1_custom_poor_sinr_threshold_struct;
+
+typedef struct
+{
+ kal_uint8 ctrl_bmp;
+ kal_uint8 rpt_rsrp_offset; //qdBm, rsrp offset range: 0~40 qdBm
+ kal_int16 rsrp_th_for_offset; //qdBm
+ kal_int16 rsrq_th_for_offset; //qdB
+ kal_int16 sinr_th_for_offset; //qdB
+ kal_int16 rsrp_th_for_ignore_rpt; //qdBm
+ kal_int16 rsrq_th_for_ignore_rpt; //qdB
+ kal_int16 sinr_th_for_ignore_rpt; //qdB
+} nl1_custom_prefer_cell_meas_report_threshold_struct;
+
+typedef struct
+{
+ /*all NRRC MEAS/NL1MOB directly related thresholds*/
+ custom_nrrc_l4c_custom_bar_threshold_struct l4c_cus_bar_th;
+ custom_qrxlevmin_adjust_struct cus_qrxlevmin_adj;
+ nl1_custom_pcell_ncell_threshold_struct A3A4A5_ignore_th;
+ nl1_custom_pcell_ncell_threshold_struct A3A4A5_force_th;
+ nl1_custom_pcell_ncell_threshold_struct lte_B1_B2_ignore_th;
+ nl1_custom_threshold_per_band_list_struct lte_B1_B2_ignore_th_serv_per_band_list;
+ nl1_custom_pcell_ncell_threshold_struct lte_B1_B2_force_th;
+ nl1_custom_threshold_per_band_list_struct lte_B1_B2_force_th_serv_per_band_list;
+ nl1_custom_pcell_ncell_threshold_struct nr_to_lte_resel_ignore_th;
+ nl1_custom_pcell_ncell_threshold_struct nr_to_lte_resel_force_th;
+ kal_uint16 custom_enh_ind_update_period;
+ nl1_custom_ping_pong_parameter_struct ping_pong_parameter;
+ nl1_custom_pcell_a2_threshold_struct a2_adjust_th;
+ nl1_custom_pcell_a2_threshold_per_band_list_struct a2_adjust_th_per_band_list;
+ nl1_custom_poor_sinr_threshold_struct cus_poor_sinr_th;
+ nl1_custom_prefer_cell_meas_report_threshold_struct A3A4A5_prefer_cell;
+} custom_nrrc_meas_nl1mob_performance;
+
+typedef struct
+{
+ /* Measurement identities */
+ nl1_meas_id_struct meas_id_list[NR_MAX_MEAS_ID_NUM];
+ kal_uint64 meas_id_modify_bitmap; /* To remove the measurement reporting entry for modified meas id */
+ /* Measurement objects */
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_uint8 meas_obj_list_num;
+#endif
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ nl1_meas_object_struct *p_meas_obj_list;
+#else
+ nl1_meas_object_struct meas_obj_list[NR_MAX_MEAS_OBJECT_ID_NUM];
+#endif
+ kal_uint64 meas_object_modify_bitmap; /* To reset the measurement result for modified meas object */
+ kal_uint64 meas_object_black_cell_list_modify_bitmap; /* Indicate meas object's black cell list is modified */
+ /* Reporting configurations */
+ nl1_report_config_struct report_config_list[NR_MAX_REPORT_CONFIG_ID_NUM];
+ /* s-Measure config */
+ kal_bool s_measure_config_valid;
+ nl1_s_measure_config_struct s_measure_config; /* Valid when s_measure_config_valid set to KAL_TRUE */
+ /* Quantity config */
+ kal_bool quantity_config_valid;
+ nl1_quantity_config_struct quantity_config;
+ /* Meas gap config */
+ kal_bool meas_gap_config_valid;
+ nl1_meas_gap_config_struct meas_gap_config;
+ /* Meas gap Sharing config */
+ kal_bool meas_gap_sharing_config_valid;
+ nl1_meas_gap_sharing_config_struct meas_gap_sharing_config;
+ kal_bool is_eutra_ho_to_nr_ongoing;
+ /* connected Related NVRAM param*/
+ custom_nrrc_meas_nl1mob_performance cur_nvm_meas_mob_performance;
+} nl1_ue_meas_config_struct;
+
+typedef struct
+{
+ kal_uint8 serv_cell_index;
+ kal_uint32 dl_arfcn;
+ kal_uint16 pci;
+ kal_bool serving_cell_meas_object_id_valid;
+ kal_uint8 serving_cell_meas_object_id;
+} nl1_meas_serving_info_struct;
+
+typedef struct
+{
+ kal_bool pcell_valid;
+ nl1_meas_serving_info_struct pcell;
+ kal_bool pscell_valid;
+ nl1_meas_serving_info_struct pscell;
+ kal_uint8 secondary_cell_num;
+ nl1_meas_serving_info_struct secondary_cell_list[NL1_SCELL_CONFIG_LIST_SIZE];
+} nl1_meas_serving_info_list_struct;
+
+typedef struct
+{
+ kal_uint8 tid;
+ kal_bool del_meas_config;
+ nl1_ue_meas_config_struct meas_config;
+ nl1_meas_serving_info_list_struct serving_info_list;
+ nl1_meas_channel_lock_info_struct channel_lock_info;
+ nl1_meas_eas_channel_lock_info_struct eas_channel_lock_info;
+} nl1_meas_config_struct;
+/*** meas_config related - End ***/
+
+
+typedef struct
+{
+ nl1_speed_state_scale_factor_enum sf_medium;
+ nl1_speed_state_scale_factor_enum sf_high;
+} nl1_speed_state_scale_factors_struct;
+
+
+typedef struct
+{
+ kal_uint8 s_non_intra_search_p;
+ kal_uint8 s_non_intra_search_q;
+ kal_uint8 thresh_serving_low_p;
+ kal_bool thresh_serving_low_q_valid;
+ kal_uint8 thresh_serving_low_q;
+ nl1_cell_resel_priority_enum priority;
+} nl1_cell_resel_serving_freq_info_struct;
+
+typedef struct
+{
+ kal_uint16 pci;
+ kal_int8 q_offset_s_n;
+ kal_bool q_rxlev_min_offset_cell_valid;
+ kal_uint8 q_rxlev_min_offset_cell;
+ kal_bool q_qual_min_offset_cell_valid;
+ kal_uint8 q_qual_min_offset_cell;
+ kal_uint8 q_offset_temp;
+} nl1_cell_resel_ncell_struct;
+
+
+typedef struct
+{
+ kal_int16 q_rxlev_min;
+ kal_int8 q_qual_min;
+ kal_uint8 s_intra_search_p;
+ kal_uint8 s_intra_search_q;
+ kal_uint8 t_resel_nr;
+ kal_bool t_resel_nr_sf_valid;
+ nl1_speed_state_scale_factors_struct t_resel_nr_sf;
+ kal_int8 p_compensation;
+ kal_bool smtc_valid;
+ nl1_primary_ssb_mtc_struct smtc;
+ kal_bool ss_rssi_measurement_valid;
+ nl1_ss_rssi_measurement_struct ss_rssi_measurement;
+ kal_bool ssb_to_measure_valid;
+ nl1_ssb_to_measure_struct ssb_to_measure;
+ kal_bool derive_ssb_index_from_cell;
+ kal_uint8 intra_freq_ncell_num;
+ nl1_cell_resel_ncell_struct intra_freq_ncell_list[NR_MAX_NR_NCELL_NUM];
+ kal_uint8 intra_freq_black_cell_range_num;
+ nl1_pci_range_struct intra_freq_black_cell_range_list[NR_MAX_PCI_RANGE_NUM];
+} nl1_cell_resel_intra_freq_info_struct;
+
+typedef struct
+{
+ nl1_nr_dl_freq_struct dl_carrier_freq;
+ kal_bool num_of_ss_blocks_to_average_valid;
+ kal_uint8 num_of_ss_blocks_to_average;
+ kal_bool abs_thresh_ss_blocks_consolidation_valid;
+ nl1_nr_threshold_struct abs_thresh_ss_blocks_consolidation;
+ kal_bool smtc_valid;
+ nl1_primary_ssb_mtc_struct smtc;
+ NR_SCS_TYPE_E subcarrier_spacing_ssb;
+ kal_bool ssb_to_measure_valid;
+ nl1_ssb_to_measure_struct ssb_to_measure;
+ kal_bool derive_ssb_index_from_cell;
+ kal_bool ss_rssi_measurement_valid;
+ nl1_ss_rssi_measurement_struct ss_rssi_measurement;
+ kal_int16 q_rxlev_min;
+ kal_int8 q_qual_min;
+ kal_int8 p_compensation;
+ kal_uint8 t_resel_nr;
+ kal_bool t_resel_nr_sf_valid;
+ nl1_speed_state_scale_factors_struct t_resel_nr_sf;
+ kal_uint8 thresh_x_high_p;
+ kal_uint8 thresh_x_low_p;
+ kal_uint8 thresh_x_high_q;
+ kal_uint8 thresh_x_low_q;
+ kal_bool priority_valid;
+ nl1_cell_resel_priority_enum priority;
+ kal_int8 q_offset_frequency;
+ kal_uint8 inter_freq_ncell_num;
+ nl1_cell_resel_ncell_struct inter_freq_ncell_list[NR_MAX_NR_NCELL_NUM];
+ kal_uint8 inter_freq_black_cell_range_num;
+ nl1_pci_range_struct inter_freq_black_cell_range_list[NR_MAX_PCI_RANGE_NUM];
+} nl1_cell_resel_inter_freq_carrier_freq_struct;
+
+typedef struct
+{
+ kal_uint8 inter_freq_carrier_freq_num;
+ nl1_cell_resel_inter_freq_carrier_freq_struct inter_freq_carrier_freq_list[NR_IDLE_MAX_NR_FREQ_NUM];
+} nl1_cell_resel_inter_freq_info_struct;
+
+typedef struct
+{
+ kal_uint16 pci;
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ //remove struct element
+#else
+ kal_int8 q_offset_s_n;
+#endif
+ kal_bool q_rxlev_min_offset_cell_valid;
+ kal_uint8 q_rxlev_min_offset_cell;
+ kal_bool q_qual_min_offset_cell_valid;
+ kal_uint8 q_qual_min_offset_cell;
+} nl1_cell_resel_eutra_ncell_struct;
+
+typedef struct
+{
+ kal_uint32 dl_earfcn;
+ kal_uint8 eutra_neighbour_num;
+ nl1_cell_resel_eutra_ncell_struct eutra_ncell_list[NR_MAX_LTE_NCELL_NUM];
+ kal_uint8 eutra_black_cell_range_num;
+ nl1_pci_range_struct eutra_black_cell_range_list[NR_MAX_PCI_RANGE_NUM];
+ nl1_eutra_allowed_meas_bandwidth_enum allowed_meas_bandwidth;
+ kal_bool presence_antenna_port_1;
+ kal_bool priority_valid;
+ nl1_cell_resel_priority_enum priority;
+ kal_uint8 thresh_x_high_p;
+ kal_uint8 thresh_x_low_p;
+ kal_int16 q_rxlev_min;
+ kal_int8 q_qual_min;
+ kal_int8 p_compensation;
+ kal_uint8 thresh_x_high_q;
+ kal_uint8 thresh_x_low_q;
+} nl1_cell_resel_eutra_carrier_freq_struct;
+
+typedef struct
+{
+ kal_uint8 eutra_carrier_freq_num;
+ nl1_cell_resel_eutra_carrier_freq_struct eutra_carrier_freq_list[NR_IDLE_MAX_EUTRA_FREQ_NUM];
+ kal_uint8 t_resel_eutra;
+ kal_bool t_resel_eutra_sf_valid;
+ nl1_speed_state_scale_factors_struct t_resel_eutra_sf;
+} nl1_cell_resel_eutra_info_struct;
+
+typedef struct
+{
+ kal_uint16 t_evaluation;
+ kal_uint16 t_hyst_normal;
+ kal_uint8 n_cell_change_medium;
+ kal_uint8 n_cell_change_high;
+ kal_int8 q_hyst_sf_medium;
+ kal_int8 q_hyst_sf_high;
+} nl1_speed_state_reselection_parameters_struct;
+
+typedef struct
+{
+ kal_bool num_of_ss_blocks_to_average_valid;
+ kal_uint8 num_of_ss_blocks_to_average;
+ kal_bool abs_thresh_ss_blocks_consolidation_valid;
+ nl1_nr_threshold_struct abs_thresh_ss_blocks_consolidation;
+ kal_bool range_to_best_cell_valid;
+ kal_int8 range_to_best_cell;
+ kal_uint8 q_hyst;
+ kal_bool speed_state_reselection_parameters_valid;
+ nl1_speed_state_reselection_parameters_struct speed_state_reselection_parameters;
+ nl1_cell_resel_serving_freq_info_struct serving_freq_info;
+ nl1_cell_resel_intra_freq_info_struct intra_freq_info;
+ kal_bool inter_freq_info_valid;
+ nl1_cell_resel_inter_freq_info_struct inter_freq_info;
+ kal_bool eutra_info_valid;
+ nl1_cell_resel_eutra_info_struct eutra_info;
+ kal_bool ims_emergency_recovery;
+} nl1_cell_resel_params_struct;
+
+typedef struct
+{
+ kal_uint8 frequency_num;
+ nl1_nr_dl_freq_struct frequency_list[NL1_MAX_NR_EXCLUDE_LIST_FREQ_NUM];
+ kal_uint8 cell_num;
+ nl1_nr_cell_struct cell_list[NL1_MAX_NR_EXCLUDE_LIST_CELL_NUM];
+} nl1_nr_exclude_list_struct;
+
+typedef struct
+{
+ kal_uint8 frequency_num;
+ kal_uint32 frequency_list[NL1_MAX_LTE_EXCLUDE_LIST_FREQ_NUM];
+ kal_uint8 cell_num;
+ nl1_lte_cell_struct cell_list[NL1_MAX_LTE_EXCLUDE_LIST_CELL_NUM];
+} nl1_lte_exclude_list_struct;
+
+typedef struct
+{
+ kal_uint16 drx_short_cycle;
+ kal_uint8 drx_short_cycle_timer;
+} nl1_mac_drx_short_cycle_config_struct;
+
+typedef struct
+{
+ nl1_mac_drx_on_duration_timer_unit_enum drx_on_duration_timer_unit;
+ kal_uint16 drx_on_duration_timer;
+ kal_uint16 drx_inactivity_timer;
+ kal_uint8 drx_harq_rtt_timer_dl;
+ kal_uint8 drx_harq_rtt_timer_ul;
+ kal_uint16 drx_retransmission_timer_dl;
+ kal_uint16 drx_retransmission_timer_ul;
+ kal_uint16 drx_long_cycle;
+ kal_uint16 drx_start_offset;
+ kal_bool drx_short_cycle_config_valid;
+ nl1_mac_drx_short_cycle_config_struct drx_short_cycle_config;
+ kal_uint8 drx_slot_offset;
+} nl1_mac_drx_config_struct;
+
+typedef struct
+{
+ kal_uint8 scheduling_request_id;
+ kal_uint8 sr_prohibit_timer;
+ kal_uint16 sr_trans_max;
+} nl1_mac_sr_config_struct;
+
+typedef struct
+{
+ kal_uint8 tag_id;
+ /* Please use NL1_MAC_TIME_ALIGNMENT_TIMER_INFINITY for 'Infinity'. */
+ kal_uint16 time_alignment_timer;
+} nl1_mac_tag_config_struct;
+
+typedef struct
+{
+ /* Please use NL1_MAC_PHR_PERIODIC_TIMER_INFINITY for 'Infinity'. */
+ kal_uint16 phr_periodic_timer;
+ kal_uint16 phr_prohibit_timer;
+ /* Please use NL1_MAC_PHR_TX_POWER_FACTOR_CHANGE_INFINITY for 'Infinity'. */
+ kal_uint8 phr_tx_power_factor_change;
+ kal_bool multiple_phr;
+ kal_bool phr_type2_other_cell;
+ kal_bool is_phr_mode_other_cg_real;
+} nl1_mac_phr_config_struct;
+
+typedef struct
+{
+ kal_bool drx_config_valid;
+ nl1_mac_drx_config_struct drx_config;
+ kal_uint8 sr_config_num;
+ nl1_mac_sr_config_struct sr_config_list[NL1_SR_CONFIG_LIST_SIZE];
+ kal_uint8 tag_config_num;
+ nl1_mac_tag_config_struct tag_config_list[NL1_TA_CONFIG_LIST_SIZE];
+ kal_bool phr_config_valid;
+ nl1_mac_phr_config_struct phr_config;
+ kal_bool skip_uplink_tx_dynamic;
+ kal_bool csi_mask;
+} nl1_mac_cell_group_config_struct;
+
+typedef struct
+{
+ kal_bool harq_ack_spatial_bundling_pucch;
+ kal_bool harq_ack_spatial_bundling_pusch;
+ kal_bool p_nr_fr1_valid;
+ kal_int8 p_nr_fr1;
+ nl1_pdsch_harq_ack_codebook_enum pdsch_harq_ack_codebook;
+ kal_bool tpc_srs_rnti_valid;
+ kal_uint16 tpc_srs_rnti;
+ kal_bool tpc_pucch_rnti_valid;
+ kal_uint16 tpc_pucch_rnti;
+ kal_bool tpc_pusch_rnti_valid;
+ kal_uint16 tpc_pusch_rnti;
+ kal_bool sp_csi_rnti_valid;
+ kal_uint16 sp_csi_rnti;
+ kal_bool cs_rnti_valid;
+ kal_uint16 cs_rnti;
+ kal_bool mcs_c_rnti_valid;
+ kal_uint16 mcs_c_rnti;
+ kal_bool p_ue_fr1_valid;
+ kal_int8 p_ue_fr1;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ nl1_x_scale_enum x_scale;
+#endif
+} nl1_physical_cell_group_config_struct;
+
+typedef struct
+{
+ kal_bool report_uplink_tx_direct_current;
+ /* Please use NL1_MCG_CONFIG_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: MAC cell group
+ * Bit1: Physical cell group
+ * Bit2: PCell configuration
+ * Bit3: PCCH/BCCH configuration
+ * Bit4: SCell configuration
+ */
+ kal_uint32 reconfig_bitmap;
+ nl1_mac_cell_group_config_struct mac_cell_group_config;
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+ kal_bool physical_cell_group_config_valid;
+#endif
+ nl1_physical_cell_group_config_struct physical_cell_group_config;
+ nl1_primary_cell_config_struct pcell_config;
+ kal_bool pcch_config_valid;
+ nl1_pcch_config_struct pcch_config;
+ kal_bool bcch_config_valid;
+ nl1_bcch_config_struct bcch_config;
+ kal_uint8 scell_num;
+ nl1_scell_config_struct scell_list[NL1_SCELL_CONFIG_LIST_SIZE];
+} nl1_mcg_config_struct;
+
+typedef struct
+{
+ kal_bool release_and_add;
+ kal_bool report_uplink_tx_direct_current;
+ /* Please use NL1_SCG_CONFIG_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit0: MAC cell group
+ * Bit1: Physical cell group
+ * Bit2: PSCell configuration
+ * Bit3: SCell configuration
+ */
+ kal_uint32 reconfig_bitmap;
+ nl1_mac_cell_group_config_struct mac_cell_group_config;
+ nl1_physical_cell_group_config_struct physical_cell_group_config;
+ nl1_primary_cell_config_struct pscell_config;
+ kal_uint8 scell_num;
+ nl1_scell_config_struct scell_list[NL1_SCELL_CONFIG_LIST_SIZE];
+} nl1_scg_config_struct;
+
+typedef struct
+{
+ kal_uint16 location_and_bandwidth;
+ NR_SCS_TYPE_E subcarrier_spacing;
+ NL1_CP_TYPE_E cyclic_prefix;
+ kal_bool rach_config_valid;
+ nl1_rach_config_struct rach_config;
+ kal_bool pucch_config_valid;
+ nl1_pucch_config_common_struct pucch_config;
+ kal_bool pusch_config_valid;
+ nl1_pusch_config_common_struct pusch_config;
+} nl1_ul_bwp_idle_struct;
+
+typedef struct
+{
+ nl1_ul_frequency_info_struct ul_frequency_info;
+ nl1_ul_bwp_idle_struct initial_ul_bwp;
+ kal_uint16 time_alignment_timer_common;
+} nl1_ul_config_idle_struct;
+
+typedef struct
+{
+ kal_uint16 pci;
+ nl1_dl_frequency_info_struct dl_frequency_info;
+ nl1_dl_bwp_idle_struct initial_dl_bwp;
+ nl1_bcch_config_struct bcch_config;
+ nl1_pcch_config_idle_struct pcch_config;
+ nl1_ul_config_idle_struct ul_config;
+ kal_bool sul_config_valid;
+ nl1_ul_config_idle_struct sul_config;
+ kal_bool n_timing_advance_offset_valid;
+ nl1_n_timing_advance_offset_enum n_timing_advance_offset;
+ nl1_ssb_positions_in_burst_idle_struct ssb_positions_in_burst;
+ kal_uint16 ssb_periodicity;
+ kal_bool tdd_ul_dl_config_valid;
+ nl1_tdd_ul_dl_config_common_struct tdd_ul_dl_config;
+ NR_SCS_TYPE_E subcarrier_spacing_ssb;
+ kal_int8 ss_pbch_block_power;
+} nl1_serving_cell_config_idle_struct;
+
+typedef struct
+{
+ kal_uint8 bwp_id;
+ kal_bool shift_7_dot_5_khz;
+ kal_uint16 tx_direct_current_location;
+}nl1_uplink_tx_direct_current_bwp_struct;
+
+typedef struct
+{
+ kal_uint8 cell_group_id;
+ kal_uint8 serv_cell_index;
+ kal_uint8 ul_bwp_num;
+ nl1_uplink_tx_direct_current_bwp_struct ul_bwp_list[NL1_MAX_BWP_NUM];
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ kal_uint8 sul_bwp_num;
+ nl1_uplink_tx_direct_current_bwp_struct sul_bwp_list[NL1_MAX_BWP_NUM];
+#endif
+}nl1_uplink_tx_direct_current_cell_struct;
+
+typedef struct
+{
+ nl1_nr_cell_struct serving_cell_info;
+ kal_int16 q_rxlev_min;
+ kal_int8 q_qual_min;
+ kal_uint8 q_offset_temp;
+ kal_int8 p_compensation;
+ kal_uint16 drx_cycle;
+} nl1_cell_selection_params_struct;
+
+typedef enum
+{
+ NL1_RAT_INVALID = 0,
+ NL1_RAT_NR = 1,
+ NL1_RAT_LTE = 2,
+ NL1_RAT_LTE_NR = 3,
+ NL1_RAT_UMTS = 4,
+ NL1_RAT_GSM = 5,
+ NL1_RAT_C2K = 6,
+ NL1_RAT_1xRTT = 7,
+ NL1_RAT_HRPD = 8
+} nl1_rat_enum;
+
+typedef struct
+{
+ kal_uint8 peer_sim_index;
+ nl1_rat_enum peer_sim_rat;
+}nrrc_nl1_peer_sim_info_struct;
+
+/* MSG_ID_NRRC_NL1_IDLE_CONFIG_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_cgi_info_struct cgi_info;
+ kal_bool selected_plmn_valid;
+ nl1_plmn_id_struct selected_plmn;
+ operator_id_enum operator_id;
+ /* Please use NL1_IDLE_CONFIG_REQ_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ kal_uint32 reconfig_bitmap; //bit0: serving cell config, bit1: MAC config, bit2: cell reselection/cell_resel parameters, bit3: NR exclude list, bit4: LTE exclued list.
+ nl1_serving_cell_config_idle_struct serving_cell_config;
+ nl1_mac_cell_group_config_struct mac_config;
+ nl1_cell_selection_params_struct cell_selection_params; // Cell selection parameters of the serving cell.
+ kal_bool cell_resel_params_valid;
+ nl1_cell_resel_params_struct cell_resel_params;
+ nl1_nr_exclude_list_struct nr_exclude_list;
+ nl1_lte_exclude_list_struct lte_exclude_list;
+ nrrc_nl1_peer_sim_info_struct peer_sim_info;
+} nrrc_nl1_idle_config_req_struct;
+
+/* MSG_ID_NRRC_NL1_IDLE_CONFIG_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_idle_config_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_CONNECTED_CONFIG_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+#if defined(__CONNECTED_CONFIG_POINTER__)
+ kal_uint8 tracing_metadata[NL1_TRACING_METADATA_SIZE];
+#endif /* (__CONNECTED_CONFIG_POINTER__) */
+ kal_bool is_mr_dc;
+ kal_bool joint_mr_dc_rf_config;
+ kal_bool suspend_meas_reporting;
+ kal_bool cgi_info_valid; // This flag valid only when mcg_config_valid = TRUE
+ nl1_cgi_info_struct cgi_info;
+ kal_bool selected_plmn_valid;
+ nl1_plmn_id_struct selected_plmn;
+ operator_id_enum operator_id;
+ /* Please use NL1_CONNECTED_CONFIG_REQ_STRUCT_CONFIG_BITMAP_XXX values for masking reconfig_bitmap. */
+ /*
+ * Bit 0: MCG config
+ * Bit 1: SCG config
+ * Bit 2: Measurement config
+ */
+ kal_uint32 reconfig_bitmap;
+ kal_bool mcg_config_valid;
+ nl1_mcg_config_struct mcg_config;
+ kal_bool scg_config_valid;
+ nl1_scg_config_struct scg_config;
+ kal_bool meas_config_valid;
+ nl1_meas_config_struct meas_config;
+ nrrc_nl1_peer_sim_info_struct peer_sim_info;
+} nrrc_nl1_connected_config_req_struct;
+
+typedef struct
+{
+ kal_uint32 narfcn;
+ NR_SCS_TYPE_E ssb_scs;
+} nl1_specific_meas_freq_info_struct;
+
+/* NRRC_NL1_SPECIFIC_MEAS_RESULT_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; //The transaction id of getting measurement result.
+ nl1_nr_cell_struct cell; //Indicate the target cell that NRRC needs to obtain measurement results.//Restrictions: only valid when i??freq_list_num?is zero
+ kal_uint8 freq_list_num; //The number of frequencies in the freq_list
+ nl1_specific_meas_freq_info_struct freq_list[NL1_MAX_FREQ_LIST_NUM]; ///Indicate the frequencies that NRRC needs to obtain measurement results.
+} nrrc_nl1_specific_meas_result_req_struct;
+
+/* NRRC_NL1_SPECIFIC_MEAS_RESULT_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; //The transaction id of getting measurement result, and it should be corresponding to the request.
+ kal_uint8 freq_list_num; //The number of frequencies in the freq_list
+ nl1_freq_result_struct freq_list[NL1_MAX_FREQ_LIST_NUM]; ///Indicate the frequencies that NRRC needs to obtain measurement results.
+} nrrc_nl1_specific_meas_result_cnf_struct;
+
+
+/* MSG_ID_NRRC_NL1_CONNECTED_CONFIG_PARTIAL_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 start_offset; // offset to the original message structure for the start position of this split message
+ kal_uint32 end_offset; // offset to the original message structure for the end position of this split message
+ kal_uint8 buffer[NL1_CONNECTED_CONFIG_PARTIAL_REQ_RAW_DATA_LENGTH]; // control buffer for partial message
+ kal_bool end_flag; // TRUE means this is the last split ilm
+} nrrc_nl1_connected_config_partial_req_struct;
+
+/* MSG_ID_NRRC_NL1_CONNECTED_CONFIG_INDIRECT_DATA_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_dl_bwp_struct additional_dl_bwp_list[NL1_ADDITIONAL_DL_BWP_LIST_SIZE];
+ nl1_ul_bwp_struct ul_additional_ul_bwp_list[NL1_ADDITIONAL_UL_BWP_LIST_SIZE];
+ nl1_nzp_csi_rs_resource_struct nzp_csi_rs_resource_list[NL1_NZP_CSI_RS_RESOURCE_LIST_SIZE];
+ nl1_nzp_csi_rs_resource_set_struct nzp_csi_rs_resource_set_list[NL1_NZP_CSI_RS_RESOURCE_SET_LIST_SIZE];
+ nl1_csi_ssb_resource_set_struct csi_ssb_resource_set_list[NL1_CSI_SSB_RESOURCE_LIST_SIZE];
+ nl1_csi_resource_config_struct csi_resource_config_list[NL1_CSI_RESOURCE_CONFIG_LIST_SIZE];
+ nl1_csi_report_config_struct csi_report_config_list[NL1_CSI_REPORT_CONFIG_LIST_SIZE];
+ nl1_csi_aperiodic_trigger_state_struct aperiodic_trigger_state_list[NL1_CSI_RPT_APERIODIC_TRIGGER_STATE_LIST_SIZE];
+ nl1_meas_object_struct meas_obj_list[NR_MAX_MEAS_OBJECT_ID_NUM];
+} nrrc_nl1_connected_config_indirect_data_req_struct;
+
+/* MSG_ID_NRRC_NL1_CONNECTED_CONFIG_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 uplink_tx_direct_current_num;
+ nl1_uplink_tx_direct_current_cell_struct uplink_tx_direct_current_list[NL1_UPLINK_TX_DIRECT_CURRENT_CELL_SIZE];
+ kal_bool is_ra_required;
+} nrrc_nl1_connected_config_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nrrc_nl1_vc_cause_enum vc_cause;
+}nrrc_nl1_switch_virtual_connected_req_struct;
+
+/* MSG_ID_NRRC_NL1_PUCCH_SRS_RELEASE_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_group_id;
+ kal_uint8 tag_id;
+} nrrc_nl1_pucch_srs_release_ind_struct;
+
+typedef struct
+{
+ kal_uint32 narfcn;
+ NR_SCS_TYPE_E ssb_scs;
+ kal_uint16 band;
+ nl1_primary_ssb_mtc_struct smtc_1;
+ kal_bool smtc_2_valid;
+ nl1_secondary_ssb_mtc_struct smtc_2;
+} nl1_redir_reestablish_meas_freq_info_struct;
+
+/* NRRC_NL1_REDIRECT_MEAS_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_redir_meas_command_enum command;
+ kal_uint8 freq_list_num;
+ nl1_redir_reestablish_meas_freq_info_struct freq_list[NL1_MAX_FREQ_LIST_NUM];
+ kal_uint8 tid;
+ kal_bool is_4G5; //redirect from LTE to NR
+} nrrc_nl1_redirect_meas_req_struct;
+
+/* NRRC_NL1_REDIRECT_MEAS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+ kal_uint8 freq_list_num;
+ kal_bool searched_freq_list[NL1_MAX_FREQ_LIST_NUM];
+ kal_uint8 detected_cell_list_num;
+ nl1_ccs_result_struct detected_cell_list[NL1_MAX_DETECTED_CELL_BEAM_LIST_NUM];
+} nrrc_nl1_redirect_meas_ind_struct;
+
+/* NRRC_NL1_REDIRECT_MEAS_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+} nrrc_nl1_redirect_meas_cnf_struct;
+
+/* NRRC_NL1_REESTABLISH_MEAS_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_reest_meas_command_enum command;
+ kal_uint8 freq_list_num;
+ nl1_redir_reestablish_meas_freq_info_struct freq_list[NL1_MAX_FREQ_LIST_NUM];
+ kal_uint8 tid;
+} nrrc_nl1_reestablish_meas_req_struct;
+
+/* NRRC_NL1_REESTABLISH_MEAS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+ kal_uint8 freq_list_num;
+ kal_bool searched_freq_list[NL1_MAX_FREQ_LIST_NUM];
+ kal_uint8 detected_cell_list_num;
+ nl1_ccs_result_struct detected_cell_list[NL1_MAX_DETECTED_CELL_BEAM_LIST_NUM];
+} nrrc_nl1_reestablish_meas_ind_struct;
+
+
+/* NRRC_NL1_REESTABLISH_MEAS_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+} nrrc_nl1_reestablish_meas_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nrrc_nl1_enhancement_enum enhancement;
+ nrrc_nl1_enhancement_action_enum action;
+}nrrc_nl1_enhancement_ntf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ custom_nrrc_meas_nl1mob_performance meas_mob_nvram;
+}nrrc_nl1_mob_nvram_para_update_req_struct;
+
+/*MSG_ID_NRRC_NL1_CONN_BAR_LIST_CTRL_REQ*/
+typedef struct
+{
+ nl1_nr_dl_freq_struct bar_nr_freq;
+ NL1_CONNECTED_BAR_CAUSE_TYPE_E freq_bar_cause;
+ kal_uint32 bar_time;/*Unit: Sec*/
+}nl1_connected_nr_freq_bar_info_strcut;
+
+typedef struct
+{
+ nl1_nr_cell_struct bar_nr_cell;
+ NL1_CONNECTED_BAR_CAUSE_TYPE_E cell_bar_cause;
+ kal_uint32 bar_time;
+}nl1_connected_nr_cell_bar_info_strcut;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid;
+
+ nl1_conn_bar_list_action_enum action;
+ NL1_CONNECTED_BAR_CAUSE_TYPE_E bar_cause;
+
+ kal_uint8 frequency_num;
+ nl1_connected_nr_freq_bar_info_strcut frequency_list[NRRC_NL1_MAX_NR_BAR_LIST_FREQ_NUM];
+
+ kal_uint8 cell_num;
+ nl1_connected_nr_cell_bar_info_strcut cell_list[NRRC_NL1_MAX_NR_BAR_LIST_CELL_NUM];
+} nrrc_nl1_conn_bar_list_ctrl_req_struct;
+
+/*MSG_ID_NRRC_NL1_CONN_BAR_LIST_CTRL_CNF*/
+typedef nrrc_nl1_conn_bar_list_ctrl_req_struct nrrc_nl1_conn_bar_list_ctrl_cnf_struct;//currently the same due to action=query
+
+/* MSG_ID_NRRC_NL1_PLMN_STATUS_UPDATE_NTF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ /*currently, only PLMN_SEL needed, and no further status enum/flag is added*/
+} nrrc_nl1_plmn_status_update_ntf_struct;
+
+/* MSG_ID_NRRC_NL1_CUSTOM_BAR_LIST_CLEAR_NTF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_custom_bar_list_clear_ntf_struct;
+
+
+/********************************************
+ * 6. Cell Reselection and Camping Lost *
+ * Detection *
+ ********************************************/
+#define NUM_OF_CANDIDATE_CELLS (16)
+
+typedef enum
+{
+ NL1_CAMPING_LOST_CAUSE_NORMAL_OOS,
+ NL1_CAMPING_LOST_CAUSE_GEMINI
+} nl1_camping_lost_cause_enum;
+
+typedef struct
+{
+ nl1_rat_enum target_rat;
+ nl1_nr_cell_struct target_nr_cell;
+ kal_int16 rsrp;
+ kal_int16 rsrq;
+ nl1_lte_cell_struct target_lte_cell;
+} nl1_candidate_cell_struct;
+
+/* MSG_ID_NRRC_NL1_RESELECTION_NEEDED_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 candidate_cell_num;
+ nl1_candidate_cell_struct candidate_cell_list[NUM_OF_CANDIDATE_CELLS];
+ kal_uint8 abort_nr_cell_num;
+ nl1_nr_cell_struct abort_nr_cell_list[NUM_OF_CANDIDATE_CELLS];
+ nl1_nr_cell_struct pcell_info;
+ kal_int16 pcell_ss_rsrp;
+ kal_int16 pcell_ss_rsrq;
+ kal_int16 pcell_srxlev;
+ kal_int16 pcell_squal;
+} nrrc_nl1_reselection_needed_ind_struct;
+
+/* MSG_ID_NRRC_NL1_CAMPING_LOST_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_camping_lost_cause_enum cause;
+} nrrc_nl1_camping_lost_ind_struct;
+
+/* MSG_ID_NRRC_NL1_EARLY_CAMPING_LOST_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_early_camping_lost_ind_struct;
+
+/********************************************
+ * 7. Paging Reception *
+ ********************************************/
+typedef enum
+{
+ NL1_PAGING_UE_IDENTITY_5G_S_TMSI,
+ NL1_PAGING_UE_IDENTITY_I_RNTI
+}nl1_paging_ue_identity_enum;
+
+
+/* MSG_ID_NRRC_NL1_PAGING_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_paging_ue_identity_enum ue_identity;
+ kal_bool access_type_present;
+} nrrc_nl1_paging_ind_struct;
+
+/* MSG_ID_NRRC_NL1_BCCH_MOD_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 time_to_modification_period_boundary;
+ nl1_nr_cell_struct cell;
+} nrrc_nl1_bcch_mod_ind_struct;
+
+/* MSG_ID_NRRC_NL1_PWS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_nr_cell_struct cell;
+} nrrc_nl1_pws_ind_struct;
+
+/********************************************
+ * 8. Random Access *
+ ********************************************/
+
+typedef enum
+{
+ NL1_RANDOM_ACCESS_TYPE_NORMAL = 0,
+ NL1_RANDOM_ACCESS_TYPE_SI_REQ_MSG1 = 1,
+ NL1_RANDOM_ACCESS_TYPE_INVALID = 0xFF
+} nl1_random_access_type_enum;
+
+typedef enum
+{
+ NL1_RANDOM_ACCESS_FAILURE_CAUSE_NORMAL_FAILURE = 0,
+ NL1_RANDOM_ACCESS_FAILURE_CAUSE_SI_REQUEST_CONFIG_NOT_AVAILABLE_FOR_CARRIER = 1
+} nl1_random_access_failure_cause_enum;
+
+typedef struct
+{
+ kal_uint8 ra_preamble_start_index;
+ kal_uint8 min_ra_preamble_start_index;
+ kal_bool ra_association_period_index_valid;
+ kal_uint8 ra_association_period_index;
+ kal_bool ra_ssb_occasion_mask_index_valid;
+ kal_uint8 ra_ssb_occasion_mask_index;
+}nl1_random_access_si_request_resources_struct;
+
+typedef struct
+{
+ nl1_rach_config_generic_struct rach_config_si;
+ nl1_ssb_per_rach_occasion_enum ssb_per_rach_occasion;
+}nl1_random_access_si_request_rach_occasions_struct;
+
+typedef struct
+{
+ kal_bool rach_occasions_valid;
+ nl1_random_access_si_request_rach_occasions_struct rach_occasions;
+ kal_bool si_request_period_valid;
+ kal_uint8 si_request_period;
+ nl1_random_access_si_request_resources_struct si_request_resources;
+}nl1_random_access_si_request_config_struct;
+
+/* MSG_ID_NRRC_NL1_RANDOM_ACCESS_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_random_access_type_enum type;
+ kal_bool si_request_config_valid;
+ nl1_random_access_si_request_config_struct si_request_config;
+ kal_bool si_request_config_sul_valid;
+ nl1_random_access_si_request_config_struct si_request_config_sul;
+} nrrc_nl1_random_access_req_struct;
+
+/* MSG_ID_NRRC_NL1_RANDOM_ACCESS_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_random_access_type_enum type;
+ kal_bool success;
+ nl1_random_access_failure_cause_enum failure_cause;
+ kal_bool success_on_nul;
+} nrrc_nl1_random_access_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_RANDOM_ACCESS_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success;
+ kal_bool c_rnti_valid;
+ kal_uint16 c_rnti;
+} nrrc_nl1_random_access_ind_struct;
+
+/********************************************
+ * 9. Background Procedures *
+ ********************************************/
+/* typedef nrrc_nl1_background_pbch_meas_result_ind_struct is moved to 13. PBCH */
+
+/********************************************
+ * 10. Measurement Reporting *
+ ********************************************/
+
+/* Spec. maxCellReport 8 */
+#define NRRC_NL1_MAX_CELL_REPORT_NUM 8
+/* Spec. maxFreq 8 */
+#define NRRC_NL1_MAX_FREQ_NUM 8
+/* Spec. maxNrofSSBs 64 */
+/* Spec. maxNrofCSI-RS 64 */
+#define NRRC_NL1_MAX_INDEXES_TO_REPORT_2_NUM (NL1_MAX_CELL_BEAM_NUM_PER_FREQ)
+
+/* MSG_ID_NRRC_NL1_CELL_POWER_LEVEL_IND */
+#define NR_INVALID_SIGNAL_VALUE 0x7fff
+#define NR_INVALID_RSSI_VALUE 1
+
+/* MSG_ID_NRRC_NL1_CELL_POWER_LEVEL_IND */
+typedef enum
+{
+ NRRC_NL1_SIGNAL_NORMAL_REPORT = 0,
+ NRRC_NL1_SIGNAL_INITIAL_REPORT = 1,
+ NRRC_NL1_SIGNAL_THRESHOLD_CROSS_REPORT = 2
+} nrrc_nl1_signal_report_type_enum;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_connected_mode;
+
+ kal_int32 ssRsrp_in_qdbm;
+ kal_int32 ssRsrq_in_qdb;
+ kal_int32 ssSinr_in_qdb;
+ kal_int32 ssRssi_in_qdbm;
+
+ kal_int32 csiRsrp_in_qdbm;
+ kal_int32 csiRsrq_in_qdb;
+ kal_int32 csiSinr_in_qdb;
+
+ kal_uint16 serv_nr_band;
+
+ nrrc_nl1_signal_report_type_enum signal_report_type;
+ kal_uint8 thres_cross_signal_type;
+
+ kal_int16 ssSrxlev_in_qdb;
+ kal_int16 ssSqual_in_qdb;
+} nrrc_nl1_cell_power_level_ind_struct;
+
+typedef struct
+{
+ kal_uint8 rsrp; /* Range: 0..127, INVALID: 0xFF */
+ kal_uint8 rsrq; /* Range: 0..127, INVALID: 0xFF */
+ kal_uint8 sinr; /* Range: 0..127, INVALID: 0xFF */
+} nl1_meas_quantity_results_struct;
+
+typedef struct
+{
+ kal_bool is_results_ssb_cell_valid;
+ nl1_meas_quantity_results_struct results_ssb_cell; /* Valid when is_results_ssb_cell_valid set to KAL_TRUE */
+
+ kal_bool is_results_csi_rs_cell_valid;
+ nl1_meas_quantity_results_struct results_csi_rs_cell; /* Valid when is_results_csi_rs_cell_valid set to KAL_TRUE */
+} nl1_meas_result_nr_meas_result_cell_results_struct;
+
+typedef struct
+{
+ kal_uint8 ssb_index; /* Range: 0..63 */
+ kal_bool is_ssb_results_valid;
+ nl1_meas_quantity_results_struct ssb_results; /* Valid when is_ssb_results_valid set to KAL_TRUE */
+} nl1_meas_results_per_ssb_index_struct;
+
+typedef struct
+{
+ kal_uint8 elements_num; /* Range: 1..NRRC_NL1_MAX_INDEXES_TO_REPORT_2_NUM */
+ nl1_meas_results_per_ssb_index_struct element[NRRC_NL1_MAX_INDEXES_TO_REPORT_2_NUM];
+} nl1_meas_results_per_ssb_index_list_struct;
+
+typedef struct
+{
+ kal_uint8 csi_rs_index; /* Range: 0..95, INVALID: 0xFF */
+ kal_bool is_csi_rs_results_valid;
+ nl1_meas_quantity_results_struct csi_rs_results; /* Valid when is_csi_rs_results_valid set to KAL_TRUE */
+} nl1_meas_results_per_csi_rs_index_struct;
+
+typedef struct
+{
+ kal_uint8 elements_num; /* Range: 1..NRRC_NL1_MAX_INDEXES_TO_REPORT_2_NUM */
+ nl1_meas_results_per_csi_rs_index_struct element[NRRC_NL1_MAX_INDEXES_TO_REPORT_2_NUM];
+} nl1_meas_results_per_csi_rs_index_list_struct;
+
+typedef struct
+{
+ kal_bool is_results_ssb_indexes_valid;
+ nl1_meas_results_per_ssb_index_list_struct results_ssb_indexes; /* Valid when is_results_ssb_indexes_valid set to KAL_TRUE */
+
+ kal_bool is_results_csi_rs_indexes_valid;
+ nl1_meas_results_per_csi_rs_index_list_struct results_csi_rs_indexes; /* Valid when is_results_csi_rs_indexes_valid set to KAL_TRUE */
+} nl1_meas_result_nr_meas_result_rs_index_results_struct;
+
+typedef struct
+{
+ nl1_meas_result_nr_meas_result_cell_results_struct cell_results;
+ nl1_meas_result_nr_meas_result_rs_index_results_struct rs_index_results;
+} nl1_meas_result_nr_meas_result_struct;
+
+typedef struct
+{
+ kal_uint16 pci; /* Range: 0..1007 */
+ nl1_meas_result_nr_meas_result_struct meas_result;
+} nl1_meas_result_nr_struct;
+
+typedef struct
+{
+ kal_uint8 serv_cell_id; /* Range: 0..31. Value 0 applies for the PCell */
+ nl1_meas_result_nr_struct meas_result_serving_cell;
+ kal_bool meas_result_best_neigh_cell_valid;
+ nl1_meas_result_nr_struct meas_result_best_neigh_cell;
+} nl1_meas_result_serv_mo_struct;
+
+typedef struct
+{
+ kal_uint8 element_num; /* Range: 1..NRRC_NL1_MAX_SERVING_CELL_NUM */
+ nl1_meas_result_serv_mo_struct element[NRRC_NL1_MAX_SERVING_CELL_NUM];
+} nl1_meas_result_serv_mo_list_struct;
+
+typedef struct
+{
+ kal_uint8 elements_num; /* Range: 1..NRRC_NL1_MAX_CELL_REPORT_NUM, INVALID: 0 */
+ nl1_meas_result_nr_struct meas_result_list_nr[NRRC_NL1_MAX_CELL_REPORT_NUM];
+} nl1_meas_result_list_nr_struct;
+
+typedef struct
+{
+ kal_uint16 pci; /* Range: 0..1007 */
+ nl1_meas_quantity_results_struct meas_result;
+} nl1_meas_result_eutra_struct;
+
+typedef struct
+{
+ kal_uint8 meas_result_num; /* Range: 1..NRRC_NL1_MAX_CELL_REPORT_NUM, INVALID: 0 */
+ nl1_meas_result_eutra_struct meas_result_list[NRRC_NL1_MAX_CELL_REPORT_NUM];
+} nl1_meas_result_list_eutra_struct;
+
+typedef struct
+{
+ /* For trace peer display */
+ kal_uint32 report_narfcn; /* NARFAN of measObject link to measId */
+ nl1_trace_report_type_enum report_type;
+ kal_uint32 pcell_narfcn; /* common for pcell/pscell */
+ kal_uint16 pcell_pci; /* common for pcell/pscell */
+ kal_uint8 pcell_serv_cell_id; /* common for pcell/pscell */
+ kal_uint32 scell_narfcn;
+ kal_uint16 scell_pci;
+ kal_uint8 scell_serv_cell_id;
+} nl1_meas_result_extra_info;
+
+typedef struct
+{
+ nl1_meas_result_serv_mo_list_struct meas_result_serving_mo_list;
+ nl1_meas_result_neigh_cells_type_enum meas_result_neigh_cells_type;
+ union
+ {
+ nl1_meas_result_list_nr_struct meas_result_list_nr;
+ nl1_meas_result_list_eutra_struct meas_result_list_eutra;
+ } meas_result_neigh_cells;
+ nl1_meas_result_extra_info meas_result_extra_info; /* info not directly used in measurement report */
+} nl1_meas_result_struct;
+
+/* MSG_ID_NRRC_NL1_MEAS_REPORT_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid;
+ kal_uint8 meas_id; /* Range: 1..64 */
+ nl1_meas_result_struct meas_result;
+ /* Specify if this is the lats measurement report for a periodical measurement identity */
+ kal_bool is_last_periodic_report;
+ nl1_special_report_enum special_report;
+} nrrc_nl1_meas_report_ind_struct;
+
+/* MSG_ID_NRRC_NL1_GET_SERV_MEAS_RESULT_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+} nrrc_nl1_get_serv_meas_result_req_struct;
+
+/* MSG_ID_NRRC_NL1_GET_SERV_MEAS_RESULT_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 element_num; /* Range: 1..NRRC_NL1_MAX_SERVING_CELL_NUM */
+ nl1_meas_result_serv_mo_struct element[NRRC_NL1_MAX_SERVING_CELL_NUM];
+} nrrc_nl1_get_serv_meas_result_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_SCG_FAIL_MEAS_REPORT_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_scg_fail_meas_report_req_struct;
+
+typedef struct
+{
+ kal_uint32 ssb_frequency;
+ kal_uint32 ref_freq_csi_rs;
+ kal_bool meas_result_serving_cell_valid;
+ nl1_meas_result_nr_struct meas_result_serving_cell;
+ kal_bool meas_result_neigh_cell_list_nr_valid;
+ nl1_meas_result_list_nr_struct meas_result_neigh_cell_list_nr;
+} nl1_meas_result_to_nr_struct;
+
+typedef struct
+{
+ kal_uint8 elements_num; /* Range: 1..NRRC_NL1_MAX_FREQ_NUM */
+ /* Total size is larger than 100000 so change to allocate ctrl buffer for each element entry when needed */
+ nl1_meas_result_to_nr_struct *p_element[NRRC_NL1_MAX_FREQ_NUM];
+} nl1_meas_result_list_to_nr_struct;
+
+typedef struct
+{
+ kal_bool meas_result_per_mo_list_valid;
+ nl1_meas_result_list_to_nr_struct meas_result_per_mo_list;
+} nl1_meas_result_scg_failure_struct;
+
+/* MSG_ID_NRRC_NL1_SCG_FAIL_MEAS_REPORT_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool nl1_scg_fail_meas_report_valid;
+ nl1_meas_result_scg_failure_struct nl1_scg_fail_meas_report;
+} nrrc_nl1_scg_fail_meas_report_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_REPORT_CGI_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ nl1_rat_enum rat_type; /* It's for 4G or 5G report CGI; */
+ kal_bool rptcgi_start; /* TRUE: start-report-cgi ; FALSE: stop-report-cgi */
+} nrrc_nl1_report_cgi_req_struct;
+
+/********************************************
+ * 11. Radio Link Failure *
+ ********************************************/
+typedef enum
+{
+ NL1_RLF_EVENT_T310_EXPIRY = 0,
+ NL1_RLF_EVENT_RA_PROBLEM = 1
+} nl1_rlf_event_enum;
+
+/* MSG_ID_NRRC_NL1_RLF_IND */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 cell_group_id;
+ nl1_rlf_event_enum rlf_event;
+} nrrc_nl1_rlf_ind_struct;
+
+/********************************************
+ * 12. Deactivation *
+ ********************************************/
+
+/* MSG_ID_NRRC_NL1_DEACTIVATE_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_lte_nr_rel;
+ kal_uint8 lte_nr_rel_tid;
+} nrrc_nl1_deactivate_req_struct;
+
+/* MSG_ID_NRRC_NL1_DEACTIVATE_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_deactivate_cnf_struct;
+
+/********************************************
+ * 13. PBCH *
+ ********************************************/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_nr_cell_struct cell;
+ kal_int16 dmrs_sss_rsrp; // unit: QdBm
+ kal_int16 dmrs_sss_rsrq; // unit: QdB
+ kal_int16 dmrs_sss_sinr; // unit: QdB
+
+ kal_int16 pbch_ss_rsrp; // To be removed
+ kal_int16 pbch_ss_rsrq; // To be removed
+ kal_int16 pbch_ss_sinr; // To be removed
+} nrrc_nl1_pbch_meas_result_ind_struct;
+
+typedef nrrc_nl1_pbch_meas_result_ind_struct nrrc_nl1_background_pbch_meas_result_ind_struct;
+
+/********************************************
+ * 14. VoNR *
+ ********************************************/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_vonr_ongoing;
+}nrrc_nl1_vonr_status_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nrrc_nl1_vonr_status_cnf_struct;
+
+/********************************************
+ * 15. SA Silence *
+ ********************************************/
+/* MSG_ID_NRRC_NL1_SA_SILENCE_CTRL_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool sa_silence_on;
+} nrrc_nl1_sa_silence_ctrl_req_struct;
+
+/* MSG_ID_NRRC_NL1_SA_SILENCE_CTRL_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_sa_silence_ctrl_cnf_struct;
+
+/********************************************
+ * GEMINI *
+ ********************************************/
+typedef enum
+{
+ NRRC_PRO_CH_BCCH = 0,
+ NRRC_PRO_CH_PCH = 1,
+ NRRC_PRO_CH_SCH = 2,
+ NRRC_PRO_CH_MEAS = 3,
+ NRRC_PRO_CH_CSR = 4,
+ NRRC_PRO_CH_DL_CHNG = 5,
+ NRRC_PRO_CH_RA = 6,
+ NRRC_PRO_CH_MAX = 7
+}nrrc_nl1_pro_ch_enum;
+
+typedef enum
+{
+ NL1_HANDOVER_EVENT_SUCCESS = 0,
+ NL1_HANDOVER_EVENT_FAILURE = 1,
+ NL1_HANDOVER_EVENT_HO_TO_NR_SUCCESS = 2
+}nl1_handover_event_enum;
+
+typedef enum
+{
+ NL1_VONR_ENH_DO_RELEASE_SEARCH = 0,
+ NL1_VONR_ENH_RA_ERROR_ENH = 1
+}nl1_vonr_enhancement_enum;
+
+#define NRRC_PRO_CH_ALL_BMP ((0x1 << NRRC_PRO_CH_MAX)-1)
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 channel_mask;
+}nrrc_nl1_channel_protect_start_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 channel_mask;
+}nrrc_nl1_channel_protect_stop_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool in_virtual_mode;
+ kal_bool ps_pattern_valid;
+ nl1_ps_virtual_pattern_priority_enum ps_pattern;
+ kal_bool ccs_pattern_valid;
+ nl1_ccs_virtual_pattern_priority_enum ccs_pattern;
+ kal_uint16 limit_si_rx_len;
+ kal_uint16 limit_si_rx_period;
+ kal_uint16 limit_bg_si_rx_len;
+ kal_uint16 limit_bg_si_rx_period;
+ kal_bool gemini_gap_allowed;
+}nrrc_nl1_virtual_mode_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_virtual_mode_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_enter_dsda;
+} nrrc_nl1_gemini_mode_update_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+} nrrc_nl1_gemini_mode_update_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nrrc_nl1_leave_vc_success_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_gemini_share_enum share_status;
+ kal_bool is_meas_share_on;
+ kal_bool is_paging_share_on;
+ kal_uint8 connected_protocol_index; // Index of the SIM in RRC_CONNECTED (connected SIM index)
+ nl1_nr_cell_struct connected_sim_pcell; // Specify Pcell of the SIM in RRC_CONNECTED
+}nrrc_nl1_gemini_share_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nrrc_nl1_gemini_share_cnf_struct;
+
+typedef struct
+{
+ kal_bool rsrp_valid;
+ kal_uint8 rsrp;
+ kal_bool rsrq_valid;
+ kal_uint8 rsrq;
+ kal_bool sinr_valid;
+ kal_uint8 sinr;
+}nl1_nr_cell_info_meas_results_struct;
+
+typedef struct
+{
+ kal_uint8 ssb_id;
+ kal_bool is_rsrp_valid;
+ kal_uint8 rsrp;
+}nl1_nr_cell_info_ssb_info_struct;
+
+typedef struct
+{
+ nl1_nr_cell_struct serving_cell;
+ kal_uint32 center_arfcn;
+ kal_uint32 cell_bandwidth;
+ kal_bool ssb_meas_results_valid;
+ nl1_nr_cell_info_meas_results_struct ssb_meas_results;
+ kal_bool csi_rs_meas_results_valid;
+ nl1_nr_cell_info_meas_results_struct csi_rs_meas_results;
+ kal_bool timing_advance_valid;
+ kal_uint16 timing_advance;
+ kal_uint8 ssb_num;
+ nl1_nr_cell_info_ssb_info_struct ssb_list[8];
+}nl1_nr_cell_info_serving_cell_struct;
+
+typedef struct
+{
+ nl1_nr_cell_struct neighbour_cell;
+ kal_bool ssb_meas_results_valid;
+ nl1_nr_cell_info_meas_results_struct ssb_meas_results;
+ kal_bool csi_rs_meas_results_valid;
+ nl1_nr_cell_info_meas_results_struct csi_rs_meas_results;
+ kal_uint8 ssb_num;
+ nl1_nr_cell_info_ssb_info_struct ssb_list[4];
+}nl1_nr_cell_info_neighbour_cell_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 serving_cell_num;
+ nl1_nr_cell_info_serving_cell_struct serving_cell_list[NL1_MAX_SERVING_CELL_NUM];
+ kal_uint8 neighbour_cell_num;
+ nl1_nr_cell_info_neighbour_cell_struct neighbour_cell_list[NL1_MAX_REPORT_NBR_CELL_INFO_NUM];
+}nrrc_nl1_cell_info_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_handover_event_enum handover_event;
+}nrrc_nl1_handover_event_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_vonr_enhancement_enum vonr_enhancement_type; // Specifies which VoNR enhancement status do NRRC want to query.
+}nrrc_nl1_enhancement_query_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ nl1_vonr_enhancement_enum vonr_enhancement_type; // Specifies the VoNR enhancement status which NRRC wants to query. Should be the same query type in NRRC_NL1_ENHANCEMENT_QUERY_REQ
+ kal_bool enhancement_status; //Specifies the status of this enhancement.
+}nrrc_nl1_enhancement_query_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_DSP_SNIFFER_REQ */
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nrrc_nl1_dsp_sniffer_req_struct;
+
+/* MSG_ID_NRRC_NL1_DSP_SNIFFER_CNF */
+typedef struct
+{
+ LOCAL_PARA_HDR
+}nrrc_nl1_dsp_sniffer_cnf_struct;
+
+/* MSG_ID_NRRC_NL1_CELL_POWER_THRESHOLD_CONFIG_NTF */
+#define NRRC_NL1_POWER_THRESHOLD_NUM 16
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 ssRsrp_threshold_num;
+ kal_uint8 ssRsrq_threshold_num;
+ kal_uint8 ssSinr_threshold_num;
+ kal_int16 ssRsrp_threshold[NRRC_NL1_POWER_THRESHOLD_NUM];
+ kal_int16 ssRsrq_threshold[NRRC_NL1_POWER_THRESHOLD_NUM];
+ kal_int16 ssSinr_threshold[NRRC_NL1_POWER_THRESHOLD_NUM];
+ kal_uint32 timer;
+}nrrc_nl1_cell_power_threshold_config_ntf_struct;
+
+/* MSG_ID_NL1_NRRC_DVFS_CONTROL_MSG */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool pullUp;
+}nl1_nrrc_dvfs_control_msg_struct;
+
+typedef struct
+{
+ kal_int16 rsrp_threshold;
+ kal_int16 rsrq_threshold;
+ kal_int16 sinr_threshold;
+}custom_nrrc_nl1_hst_cell_power_threshold_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ custom_nrrc_nl1_hst_cell_power_threshold_struct hst_power_thresh;
+}nrrc_nl1_hst_enhance_config_req_struct;
+
+#if defined(__XL1SIM__) && defined(__CONNECTED_CONFIG_POINTER__)
+
+typedef struct
+{
+ nl1_dl_bwp_struct additional_dl_bwp_list[NL1_ADDITIONAL_DL_BWP_LIST_SIZE];
+} nrrc_nl1_additional_dl_bwp_struct;
+
+typedef struct
+{
+ nl1_ul_bwp_struct additional_ul_bwp_list[NL1_ADDITIONAL_UL_BWP_LIST_SIZE];
+} nrrc_nl1_additional_ul_bwp_struct;
+
+typedef struct
+{
+ nl1_meas_object_struct meas_obj_list[NR_MAX_MEAS_OBJECT_ID_NUM];
+} nrrc_nl1_meas_object_struct;
+
+typedef struct
+{
+ nl1_nzp_csi_rs_resource_struct nzp_csi_rs_resource_list[NL1_NZP_CSI_RS_RESOURCE_LIST_SIZE];
+} nrrc_nl1_nzp_csi_rs_resource_struct;
+
+typedef struct
+{
+ nl1_nzp_csi_rs_resource_set_struct nzp_csi_rs_resource_set_list[NL1_NZP_CSI_RS_RESOURCE_SET_LIST_SIZE];
+} nrrc_nl1_nzp_csi_rs_resource_set_struct;
+
+typedef struct
+{
+ nl1_csi_ssb_resource_set_struct csi_ssb_resource_set_list[NL1_CSI_SSB_RESOURCE_LIST_SIZE];
+} nrrc_nl1_csi_ssb_resource_set_struct;
+
+typedef struct
+{
+ nl1_csi_resource_config_struct csi_resource_config_list[NL1_CSI_RESOURCE_CONFIG_LIST_SIZE];
+} nrrc_nl1_csi_resource_config_struct;
+
+typedef struct
+{
+ nl1_csi_report_config_struct csi_report_config_list[NL1_CSI_REPORT_CONFIG_LIST_SIZE];
+} nrrc_nl1_csi_report_config_struct;
+
+typedef struct
+{
+ nl1_csi_aperiodic_trigger_state_struct aperiodic_trigger_state_list[NL1_CSI_RPT_APERIODIC_TRIGGER_STATE_LIST_SIZE];
+} nrrc_nl1_csi_aperiodic_trigger_state_struct;
+
+#endif /* defined(__XL1SIM__) && defined(__CONNECTED_CONFIG_POINTER__) */
+
+#endif /* _NRRC_NL1_STRUCT_H */
diff --git a/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_public.h b/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_public.h
new file mode 100644
index 0000000..08b309a
--- /dev/null
+++ b/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_public.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/* Doxygene header ***********************************************************
+ *
+ * @file nl1_comm_inter_core_public.h
+ * @brief NL1 PUBLIC header file.
+ * @details Put those interfaces be used by other layers (non-NL1) here. \n
+ * Please make sure non-NL1 users can build pass w/o including other NL1 header files. \n
+ * It depends that we might need different public header files to serve different users.
+ * @addtogroup NL1
+ * @{
+ *//***************************************************************************/
+
+#ifndef __NL1_COMM_INTER_CORE_PUBLIC_H__
+#define __NL1_COMM_INTER_CORE_PUBLIC_H__
+#include "nl1_comm_inter_core_wrapper_general_type.h"
+
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_INTER_FREQ_MEAS_OBJECT_NUM
+ * @details
+ * @date 2018.06.25
+ * @owner aric.chiu
+*******************************************************************************/
+#define NL1_MAX_INTER_FREQ_MEAS_OBJECT_NUM (16)
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_CELL_BEAM_NUM_PER_FREQ
+ * @details
+ * @date 2018.06.25
+ * @owner aric.chiu
+*******************************************************************************/
+#define NL1_MAX_CELL_BEAM_NUM_PER_FREQ (20)
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_CELL_NUM_PER_FREQ
+ * @details
+ * @date 2018.06.25
+ * @owner aric.chiu
+*******************************************************************************/
+#define NL1_MAX_CELL_NUM_PER_FREQ (8)
+
+/*********************************************************************************
+ * @brief Number of NL1 database layers to store Gemini SIM dependent info from NL1's view.
+ * @details 1) MAX_NR_NUM
+ * Global definition for all modem modules that indicates
+ * the number of SIMs that support NR.
+ *
+ * Value Project
+ * ------------------------------------------
+ * 1 Non-Gemini projects with NR built. (No definition of __GEMINI__)
+ * 2 N+L DSDS -- There exists 2 SIMs that support NR: SIM1 & SIM2.
+ * PS guarantees that at any time only one SIM would leave RF_OFF state at NR protocol stack L4.
+ * 2 N+N DSDS -- There exists 2 SIMs that support NR: SIM1 & SIM2.
+ * PS can control both SIM1 & SIM2 to leave RF_OFF state at NR protocol stack L4 at the same time.
+ *
+ * 2) NL1_SIM_DB_NUM
+ * NL1 internal definition that indicates the number of database layers for Gemini SIM dependent info.
+ * Ideally this equal MAX_NR_NUM. However, for implementation simplicity (considering Gen93/95 experience),
+ * Set the value to be 2 or larger.
+ *
+ * 3) NL1_MAX_NR_NUM
+ * NL1 internal definition of MAX_NR_NUM. Its value is the same as MAX_NR_NUM except that
+ * the value is 1 when MAX_NR_NUM is not defined. This is for the case that the value is used to define an array size
+ * when NR is not built.
+ * @date 2018.12.20
+ * @owner Chang-Kuan.Lin
+*******************************************************************************/
+#ifdef MAX_NR_NUM // Definition in MCU: /mcu/make/common/rule_def/common_def.mak
+ #if MAX_NR_NUM < 2 // For non-Gemini projects.
+#define NL1_SIM_DB_NUM (2) // Gen93/95 experience: always build loads with __GEMINI__ for customers.
+ #else // For normal Gemini use.
+#define NL1_SIM_DB_NUM (MAX_NR_NUM)// Follow the global definition. Should be 2 or larger.
+ #if MAX_NR_NUM > 2
+#error "NL1 does not support MAX_NR_NUM > 2. Need to evaluate NL1 design on both MCU & DSP sides."
+ #endif
+ #endif
+#else // When NR is not buit.
+#define NL1_SIM_DB_NUM (2) // Follow the mainly used value currently.
+#endif
+
+#ifdef MAX_NR_NUM
+#define NL1_MAX_NR_NUM (MAX_NR_NUM)
+#else
+#define NL1_MAX_NR_NUM (1)
+#endif
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_DL_SCELL_CC_NUM
+ * @details Indicate the max number of carrier components (CC) supported for DL.
+ * @date 2018.03.08
+ * @owner yungli.cheng
+*******************************************************************************/
+#if defined(MT6297)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(MT6885)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(MERCURY)
+#define NL1_MAX_DL_SCELL_CC_NUM (8)
+#elif defined(MT6873)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(MT6853)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(CHIP10992)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(MT6833)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(MT6877)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#elif defined(MT6855)
+#define NL1_MAX_DL_SCELL_CC_NUM (1)
+#else
+#error "Please check CC number for DL on this chip"
+#endif
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_CC_NUM
+ * @details Indicate the max number of carrier components (CC) supported for DL.
+ * @date 2018.03.08
+ * @owner yungli.cheng
+*******************************************************************************/
+#define NL1_MAX_CC_NUM (NL1_MAX_DL_SCELL_CC_NUM + 1)
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_DL_CC_NUM
+ * @details Indicate the max number of carrier components (CC) supported for DL.
+ * @date 2018.03.08
+ * @owner yungli.cheng
+*******************************************************************************/
+#define NL1_MAX_DL_CC_NUM (NL1_MAX_CC_NUM)
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_UL_SCELL_CC_NUM
+ * @details Indicate the max number of secondary carrier components (CC) supported for UL.
+ * @date 2018.03.08
+ * @owner cheng-long.wu
+*******************************************************************************/
+#if defined(MT6297)
+#define NL1_MAX_UL_SCELL_CC_NUM (0)
+#elif defined(MT6885)
+#define NL1_MAX_UL_SCELL_CC_NUM (1)
+#elif defined(MERCURY)
+#define NL1_MAX_UL_SCELL_CC_NUM (4)
+#elif defined(MT6873)
+#define NL1_MAX_UL_SCELL_CC_NUM (1)
+#elif defined(MT6853)
+#define NL1_MAX_UL_SCELL_CC_NUM (1)
+#elif defined(CHIP10992)
+#define NL1_MAX_UL_SCELL_CC_NUM (1)
+#elif defined(MT6833)
+#define NL1_MAX_UL_SCELL_CC_NUM (1)
+#elif defined(MT6877)
+#define NL1_MAX_UL_SCELL_CC_NUM (1)
+#elif defined(MT6855)
+#define NL1_MAX_UL_SCELL_CC_NUM (0)
+#else
+#error "Please check CC number for UL on this chip"
+#endif
+
+/*****************************************************************************//**
+ * @brief NL1_MAX_UL_CC_NUM
+ * @details Indicate the max number of secondary carrier components (CC) supported for UL.
+ * @date 2018.03.08
+ * @owner cheng-long.wu
+*******************************************************************************/
+#define NL1_MAX_UL_CC_NUM (NL1_MAX_UL_SCELL_CC_NUM + 1)
+
+/*******************************************************************************
+ * @brief NR_SCS_TYPE_E
+ * @details
+ * @date 2018.06.06
+ * @owner che-shuo.chang
+*******************************************************************************/
+typedef enum
+{
+ NR_SCS_15 = 0,
+ NR_SCS_30 = 1,
+ NR_SCS_60 = 2,
+ NR_SCS_120 = 3,
+ NR_SCS_240 = 4,
+ NR_SCS_TYPE_NUM,
+ NR_SCS_UNKNOWN = 0xFF
+} NR_SCS_TYPE_E;
+
+/*******************************************************************************
+ * @brief NR_FREQ_RANGE_E
+ * @details
+ * @date 2018.09.19
+ * @owner albert-yp.liu
+*******************************************************************************/
+typedef enum
+{
+ NR_FR_1 = 0,
+ NR_FR_2,
+ NR_FR_MIXED, // Please don't use NR_FR_MIXED. It will be removed later.
+ NR_FR_MAX,
+ NR_FR_INVALID = 0xFF
+} NR_FREQ_RANGE_E;
+
+typedef enum
+{
+ NR_BIT_FR_NONE = 0x0,
+ NR_BIT_FR_1 = (0x1 << NR_FR_1),
+ NR_BIT_FR_2 = (0x1 << NR_FR_2),
+ NR_BIT_FR_1_FR_2 = (NR_BIT_FR_1 | NR_BIT_FR_2),
+} NR_BIT_FREQ_RANGE_E;
+
+/*******************************************************************************
+ * @brief NR_DC_TYPE_E
+ * @details
+ * @date 2018.09.19
+ * @owner albert-yp.liu
+*******************************************************************************/
+typedef enum
+{
+ NR_DC_TYPE_STD_ALONE,
+ NR_DC_TYPE_INTRA_ENDC,
+ NR_DC_TYPE_INTER_ENDC,
+ NR_DC_TYPE_INTRA_NNDC,
+ NR_DC_TYPE_INTER_NNDC,
+ NR_DC_TYPE_MAX
+} NR_DC_TYPE_E;
+
+/*****************************************************************************//**
+ * @brief NL1_BAND_E
+ * @details
+ * @date 2018.06.06
+ * @owner che-shuo.chang
+*******************************************************************************/
+typedef enum
+{
+ NL1_BAND_INVALID = 0 ,
+ NL1_BAND_1 = 1 ,
+ NL1_BAND_2 = 2 ,
+ NL1_BAND_3 = 3 ,
+ NL1_BAND_4 = 4 ,
+ NL1_BAND_5 = 5 ,
+ NL1_BAND_6 = 6 ,
+ NL1_BAND_7 = 7 ,
+ NL1_BAND_8 = 8 ,
+ NL1_BAND_9 = 9 ,
+ NL1_BAND_10 = 10,
+ NL1_BAND_11 = 11,
+ NL1_BAND_12 = 12,
+ NL1_BAND_13 = 13,
+ NL1_BAND_14 = 14,
+ NL1_BAND_15 = 15,
+ NL1_BAND_16 = 16,
+ NL1_BAND_17 = 17,
+ NL1_BAND_18 = 18,
+ NL1_BAND_19 = 19,
+ NL1_BAND_20 = 20,
+ NL1_BAND_21 = 21,
+ NL1_BAND_22 = 22,
+ NL1_BAND_23 = 23,
+ NL1_BAND_24 = 24,
+ NL1_BAND_25 = 25,
+ NL1_BAND_26 = 26,
+ NL1_BAND_27 = 27,
+ NL1_BAND_28 = 28,
+ NL1_BAND_29 = 29,
+ NL1_BAND_30 = 30,
+ NL1_BAND_31 = 31,
+ NL1_BAND_32 = 32,
+ NL1_BAND_33 = 33,
+ NL1_BAND_34 = 34,
+ NL1_BAND_35 = 35,
+ NL1_BAND_36 = 36,
+ NL1_BAND_37 = 37,
+ NL1_BAND_38 = 38,
+ NL1_BAND_39 = 39,
+ NL1_BAND_40 = 40,
+ NL1_BAND_41 = 41,
+ NL1_BAND_42 = 42,
+ NL1_BAND_43 = 43,
+ NL1_BAND_44 = 44,
+ NL1_BAND_45 = 45,
+ NL1_BAND_46 = 46,
+ NL1_BAND_47 = 47,
+ NL1_BAND_48 = 48,
+ NL1_BAND_49 = 49,
+ NL1_BAND_50 = 50,
+ NL1_BAND_51 = 51,
+ NL1_BAND_52 = 52,
+ NL1_BAND_53 = 53,
+ NL1_BAND_54 = 54,
+ NL1_BAND_55 = 55,
+ NL1_BAND_56 = 56,
+ NL1_BAND_57 = 57,
+ NL1_BAND_58 = 58,
+ NL1_BAND_59 = 59,
+ NL1_BAND_60 = 60,
+ NL1_BAND_61 = 61,
+ NL1_BAND_62 = 62,
+ NL1_BAND_63 = 63,
+ NL1_BAND_64 = 64,
+ NL1_BAND_65 = 65,
+ NL1_BAND_66 = 66,
+ NL1_BAND_67 = 67,
+ NL1_BAND_68 = 68,
+ NL1_BAND_69 = 69,
+ NL1_BAND_70 = 70,
+ NL1_BAND_71 = 71,
+ NL1_BAND_72 = 72,
+ NL1_BAND_73 = 73,
+ NL1_BAND_74 = 74,
+ NL1_BAND_75 = 75,
+ NL1_BAND_76 = 76,
+ NL1_BAND_77 = 77,
+ NL1_BAND_78 = 78,
+ NL1_BAND_79 = 79,
+ NL1_BAND_80 = 80,
+ NL1_BAND_81 = 81,
+ NL1_BAND_82 = 82,
+ NL1_BAND_83 = 83,
+ NL1_BAND_84 = 84,
+ NL1_BAND_85 = 85,
+ NL1_BAND_86 = 86,
+ NL1_BAND_87 = 87,
+ NL1_BAND_88 = 88,
+ NL1_BAND_89 = 89,
+ NL1_BAND_90 = 90,
+ NL1_BAND_91 = 91,
+ NL1_BAND_92 = 92,
+ NL1_BAND_93 = 93,
+ NL1_BAND_94 = 94,
+ /* ADD NEW BAND DEFINITION HERE */
+ NL1_BAND_TYPE_NUM
+} NL1_BAND_E;
+
+/*****************************************************************************//**
+ * @brief NL1_CAP_ALL_BAND
+ * @details Inidcate that all bands are supported
+ * @date 2020.05.05
+ * @owner jeff-cy.lin
+*******************************************************************************/
+#define NL1_CAP_ALL_BAND (NL1_BAND_INVALID)
+
+/*****************************************************************************//**
+ * @brief NL1_MEAS_RESULT_RULE_E
+ * @details
+ * @date 2018.06.25
+ * @owner aric.chiu
+*******************************************************************************/
+typedef enum
+{
+ NL1_MEAS_RESULT_RULE_VALID = 0, ///< The frequency is measured as normal.
+ NL1_MEAS_RESULT_RULE_NO_GAP, ///< The frequency is not measured since there is no gap.
+ NL1_MEAS_RESULT_RULE_NO_CAPABILITY, ///< The frequency is not measured since NL1_CSM is not able to measured due to capability limitation.
+ NL1_MEAS_RESULT_RULE_MAX
+} NL1_MEAS_RESULT_RULE_E;
+
+/*****************************************************************************//**
+ * @brief NL1_CP_TYPE_E
+ * @details
+ * @date 2018.06.06
+ * @owner che-shuo.chang
+*******************************************************************************/
+typedef enum
+{
+ NL1_CP_NORMAL,
+ NL1_CP_EXTENDED,
+ NL1_CP_TYPE_NUM,
+ NL1_CP_UNKNOWN
+} NL1_CP_TYPE_E;
+
+/*****************************************************************************//**
+* @brief NL1_TX_RA_EVENT_E
+* @details
+* @date 2020.01.03
+* @owner ching-wen.huang
+*******************************************************************************/
+typedef enum
+{
+ NL1_TX_RA_EVENT_NULL,
+ NL1_TX_RA_EVENT_UL,
+ NL1_TX_RA_EVENT_PDCCH_ORDER,
+ NL1_TX_RA_EVENT_CCCH,
+ NL1_TX_RA_EVENT_BEAM_FAILURE,
+ NL1_TX_RA_EVENT_SI_REQUEST,
+ NL1_TX_RA_EVENT_SCG_MODIFY,
+ NL1_TX_RA_EVENT_ABORT,
+} NL1_TX_RA_EVENT_E;
+
+/* Inject cmd API for new dump IQ data feature */
+extern void NL1_RX_Api_SlmCmd_Set_Dsp_Inject_Cmd( kal_uint8 id, kal_uint8 val );
+
+#endif /* #define __NL1_COMM_INTER_CORE_PUBLIC_H__ */
+
+/* Doxygene end of defgroup header!!! **********************************//**@}*/
diff --git a/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_ue_capability.h b/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_ue_capability.h
new file mode 100644
index 0000000..e44d529
--- /dev/null
+++ b/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_ue_capability.h
@@ -0,0 +1,410 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/* Doxygene header *********************************************************//**
+ *
+ * @file nl1_comm_inter_core_ue_capability.h
+ * @brief Public definitions for NR UE capabilities
+ * @details Public definitions for NR UE capabilities
+ * @addtogroup NL1
+ * @{
+ *//***************************************************************************/
+
+#ifndef __NL1_COMM_INTER_CORE_UE_CAPABILITY_H__
+#define __NL1_COMM_INTER_CORE_UE_CAPABILITY_H__
+
+/*******************************************************************************
+* #include
+*******************************************************************************/
+
+////////// End #include //////////
+
+
+/*******************************************************************************
+* #define
+* - All chars are "capital"
+* - Use NL1_ or module name (e.g., "RX_" as prefix)
+* - Enclosed by "( )" to avoid ambiguity
+*******************************************************************************/
+#define NL1_CAP_UINT8_INVALID (0xFF)
+#define NL1_CAP_UINT16_INVALID (0xFFFF)
+#define NL1_CAP_UINT32_INVALID (0xFFFFFFFF)
+#define NL1_CAP_INT8_INVALID (0x80)
+#define NL1_CAP_INT16_INVALID (0x8000)
+#define NL1_CAP_INT32_INVALID (0x80000000)
+#define NL1_CAP_BITMAP_INVALID (0x0)
+
+////////// End #define //////////
+
+
+/*******************************************************************************
+* typedef
+* - enum
+* - Use module name (e.g., "RX_" as prefix)
+* - Add postfix with "_E"
+* - Element Naming
+* - All chars are "capital"
+* - Words are separated by underline "_"
+* - Use enum name as prefix (remove "_E")
+* - struct
+* - Use module name (e.g., "RX_" as prefix)
+* - Add postfix with "_T"
+* - Element Naming
+* - All chars are "lowercase"
+* - Words are separated by underline "_"
+*******************************************************************************/
+typedef enum
+{
+ NL1_CAP_NOT_SUPPORT,
+ NL1_CAP_SUPPORT,
+ NL1_CAP_INVALID
+} NL1_CAP_SUPPORT_STATUS_E;
+
+typedef enum
+{
+ NL1_CAP_BWP_SWITCH_DELAY_TYPE1,
+ NL1_CAP_BWP_SWITCH_DELAY_TYPE2,
+ NL1_CAP_BWP_SWITCH_DELAY_INVALID
+} NL1_CAP_BWP_SWITCH_DELAY_E;
+
+typedef enum
+{
+ NL1_CAP_DMRS_TYPE1,
+ NL1_CAP_DMRS_TYPE1_AND_2,
+ NL1_CAP_DMRS_TYPE_INVALID
+} NL1_CAP_DMRS_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_PDSCH_RE_MAP_FR1_N_10,
+ NL1_CAP_PDSCH_RE_MAP_FR1_N_20,
+ NL1_CAP_PDSCH_RE_MAP_FR1_INVALID
+} NL1_CAP_PDSCH_RE_MAP_FR1_E;
+
+typedef enum
+{
+ NL1_CAP_PDSCH_RE_MAP_FR2_N_6,
+ NL1_CAP_PDSCH_RE_MAP_FR2_N_20,
+ NL1_CAP_PDSCH_RE_MAP_FR2_INVALID
+} NL1_CAP_PDSCH_RE_MAP_FR2_E;
+
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+typedef enum
+{
+ NL1_CAP_PUSCH_NON_COHERENT,
+ NL1_CAP_PUSCH_PARTIAL_COHERENT,
+ NL1_CAP_PUSCH_PARTIAL_NON_COHERENT, // TODO: PARTIAL_NON_COHERENT is SEP only and should be removed
+ NL1_CAP_PUSCH_FULL_COHERENT,
+ NL1_CAP_PUSCH_TRAN_COHERENCE_TYPE_INVALID
+} NL1_CAP_PUSCH_TRAN_COHERENCE_TYPE_E;
+#else
+typedef enum
+{
+ NL1_CAP_PUSCH_NON_COHERENT,
+ NL1_CAP_PUSCH_PARTIAL_NON_COHERENT,
+ NL1_CAP_PUSCH_FULL_COHERENT,
+ NL1_CAP_PUSCH_TRAN_COHERENCE_TYPE_INVALID
+} NL1_CAP_PUSCH_TRAN_COHERENCE_TYPE_E;
+#endif
+
+typedef enum
+{
+ NL1_CAP_FREQ_SEPARAT_CLASS_1,
+ NL1_CAP_FREQ_SEPARAT_CLASS_2,
+ NL1_CAP_FREQ_SEPARAT_CLASS_3,
+ NL1_CAP_FREQ_SEPARAT_CLASS_INVALID
+} NL1_CAP_FREQ_SEPARAT_CLASS_E;
+
+typedef enum
+{
+ NL1_CAP_SCALING_FACTOR_F0P4,
+ NL1_CAP_SCALING_FACTOR_F0P75,
+ NL1_CAP_SCALING_FACTOR_F0P8,
+ NL1_CAP_SCALING_FACTOR_INVALID
+} NL1_CAP_SCALING_FACTOR_E;
+
+typedef enum
+{
+ NL1_CAP_WITHOUT_DCIGAP,
+ NL1_CAP_WITH_DCIGAP,
+ NL1_CAP_PDCCH_MONITOR_OCASION_INVALID
+} NL1_CAP_PDCCH_MONITOR_OCCASION_E;
+
+typedef enum
+{
+ NL1_CAP_CODEBOOK_MODE1,
+ NL1_CAP_CODEBOOK_MODE2,
+ NL1_CAP_CODEBOOK_MODE1_AND_MODE2,
+ NL1_CAP_CODEBOOK_MODE_INVALID
+} NL1_CAP_SUPPORTED_CODE_BOOK_MODE_E;
+
+typedef enum
+{
+ NL1_CAP_WINDBAND,
+ NL1_CAP_WIDEBAND_AND_SUBBAND,
+ NL1_CAP_AMPLITUDE_SCALE_TYPE_INVALID
+} NL1_CAP_AMPLITUDE_SCALE_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_SCS_15KHZ,
+ NL1_CAP_SCS_30KHZ,
+ NL1_CAP_SCS_60KHZ,
+ NL1_CAP_SCS_120KHZ,
+ NL1_CAP_SCS_240KHZ,
+ NL1_CAP_SCS_INVALID
+} NL1_CAP_SUBCARRIER_SPACING_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_BW5,
+ NL1_CAP_BW10,
+ NL1_CAP_BW15,
+ NL1_CAP_BW20,
+ NL1_CAP_BW25,
+ NL1_CAP_BW30,
+ NL1_CAP_BW40,
+ NL1_CAP_BW50,
+ NL1_CAP_BW60,
+ NL1_CAP_BW80,
+ NL1_CAP_BW100,
+ NL1_CAP_BW200,
+ NL1_CAP_BW400,
+ NL1_CAP_BW_INVALID
+} NL1_CAP_BW_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_DL_TWO_LAYER,
+ NL1_CAP_DL_FOUR_LAYER,
+ NL1_CAP_DL_EIGHT_LAYER,
+ NL1_CAP_DL_MIMO_LAYER_TYPE_INVALID,
+ NL1_CAP_DL_MIMO_INVALID = NL1_CAP_DL_MIMO_LAYER_TYPE_INVALID,
+} NL1_CAP_DL_MIMO_LAYER_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_UL_ONE_LAYER,
+ NL1_CAP_UL_TWO_LAYER,
+ NL1_CAP_UL_FOUR_LAYER,
+ NL1_CAP_UL_MIMO_LAYER_TYPE_INVALID,
+ NL1_CAP_UL_MIMO_INVALID = NL1_CAP_UL_MIMO_LAYER_TYPE_INVALID,
+} NL1_CAP_UL_MIMO_LAYER_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_BPSK_HALF_PI,
+ NL1_CAP_BPSK,
+ NL1_CAP_QPSK,
+ NL1_CAP_16QAM,
+ NL1_CAP_64QAM,
+ NL1_CAP_256QAM,
+ NL1_CAP_MODULATION_ORDER_TYPE_INVALID
+} NL1_CAP_MODULATION_ORDER_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_T1R2,
+ NL1_CAP_T1R4,
+ NL1_CAP_T2R4,
+ NL1_CAP_T1R4_T2R4,
+ NL1_CAP_TR_EQUAL,
+ NL1_CAP_TX_SRS_SWITCH_TYPE_INVALID
+} NL1_CAP_TX_SRS_SWITCH_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_POWER_CLASS_1,
+ NL1_CAP_POWER_CLASS_2,
+ NL1_CAP_POWER_CLASS_3,
+ NL1_CAP_POWER_CLASS_4,
+#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ NL1_CAP_POWER_CLASS_1dot5,
+ NL1_CAP_POWER_CLASS_5,
+#endif //(CUR_MD_SPEC >= MD_SPEC_2019JUN)
+ NL1_CAP_UE_CA_POWER_CLASS_TYPE_INVALID
+} NL1_CAP_UE_CA_POWER_CLASS_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_UL_SHARING_TDM,
+ NL1_CAP_UL_SHARING_FDM,
+ NL1_CAP_UL_SHARING_TDM_FDM,
+ NL1_CAP_UL_SHARING_EUTRA_NR_TYPE_INVALID
+} NL1_CAP_UL_SHARING_EUTRA_NR_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_UL_SWITCH_TIME_EUTRA_NR_TYPE1,
+ NL1_CAP_UL_SWITCH_TIME_EUTRA_NR_TYPE2,
+ NL1_CAP_UL_SWITCH_TIME_EUTRA_NR_TYPE_INVALID
+} NL1_CAP_UL_SWITCH_TIME_EUTRA_NR_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_CSI_RS_DENSITY_ONE,
+ NL1_CAP_CSI_RS_DENSITY_THREE,
+ NL1_CAP_CSI_RS_DENSITY_ONE_AND_THREE,
+ NL1_CAP_CSI_RS_DENSITY_TYPE_INVALID
+} NL1_CAP_SUPPORT_CSI_RS_DENSITY_TYPE_E;
+
+
+typedef enum
+{
+ NL1_CAP_NR_BW_CLAS_A,
+ NL1_CAP_NR_BW_CLAS_B,
+ NL1_CAP_NR_BW_CLAS_C,
+ NL1_CAP_NR_BW_CLAS_D,
+ NL1_CAP_NR_BW_CLAS_E,
+ NL1_CAP_NR_BW_CLAS_F,
+ NL1_CAP_NR_BW_CLAS_G,
+ NL1_CAP_NR_BW_CLAS_H,
+ NL1_CAP_NR_BW_CLAS_I,
+ NL1_CAP_NR_BW_CLAS_J,
+ NL1_CAP_NR_BW_CLAS_K,
+ NL1_CAP_NR_BW_CLAS_L,
+ NL1_CAP_NR_BW_CLAS_M,
+ NL1_CAP_NR_BW_CLAS_N,
+ NL1_CAP_NR_BW_CLAS_O,
+ NL1_CAP_NR_BW_CLAS_P,
+ NL1_CAP_NR_BW_CLAS_Q,
+ NL1_CAP_NR_BW_CLAS_INVALID,
+ NL1_CAP_NR_BW_CLAS_MAX,
+}NL1_CAP_NR_BW_CLASS_TYPE_E;
+
+typedef enum
+{
+ NL1_CAP_EUTRA_BW_CLAS_A,
+ NL1_CAP_EUTRA_BW_CLAS_B,
+ NL1_CAP_EUTRA_BW_CLAS_C,
+ NL1_CAP_EUTRA_BW_CLAS_D,
+ NL1_CAP_EUTRA_BW_CLAS_E,
+ NL1_CAP_EUTRA_BW_CLAS_F,
+ NL1_CAP_EUTRA_BW_CLAS_INVALID,
+ NL1_CAP_EUTRA_BW_CLAS_MAX,
+}NL1_CAP_EUTRA_BW_CLASS_TYPE_E;
+
+#if (CUR_MD_SPEC >= MD_SPEC_2018DEC)
+
+typedef enum
+{
+ NL1_CAP_INTRA_BAND_ENDC_NON_CONTIGUOUS,
+ NL1_CAP_INTRA_BAND_ENDC_BOTH,
+ NL1_CAP_INTRA_BAND_ENDC_INVALID
+}NL1_CAP_INTRA_BAND_ENDC_SUPPORT_V1540_E;
+
+typedef enum
+{
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N0,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N0_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N1,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N1_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N2,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N2_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N3,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N3_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N4,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N4_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N5_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N6,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N6_DOT5,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_N7,
+ NL1_CAP_SWITCH_TIME_DL_EUTRA_INVALID
+}NL1_CAP_SWITCH_TIME_DL_EUTRA_E;
+
+typedef enum
+{
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N0,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N0_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N1,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N1_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N2,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N2_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N3,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N3_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N4,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N4_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N5_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N6,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N6_DOT5,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_N7,
+ NL1_CAP_SWITCH_TIME_UL_EUTRA_INVALID
+}NL1_CAP_SWITCH_TIME_UL_EUTRA_E;
+
+typedef enum
+{
+ NL1_CAP_SRS_TX_PORT_SWITCH_T1R2,
+ NL1_CAP_SRS_TX_PORT_SWITCH_T1R4,
+ NL1_CAP_SRS_TX_PORT_SWITCH_T2R4,
+ NL1_CAP_SRS_TX_PORT_SWITCH_T1R4_T2R4,
+ NL1_CAP_SRS_TX_PORT_SWITCH_T1R1,
+ NL1_CAP_SRS_TX_PORT_SWITCH_T2R2,
+ NL1_CAP_SRS_TX_PORT_SWITCH_T4R4,
+ NL1_CAP_SRS_TX_PORT_SWITCH_NOT_SUPPORTED
+}NL1_CAP_SRS_TX_PORT_SWITCH_E;
+
+typedef enum
+{
+ NL1_CAP_PDCCH_MONITOR_ANY_OCCA_WITH_SPAN_GAP_SET1,
+ NL1_CAP_PDCCH_MONITOR_ANY_OCCA_WITH_SPAN_GAP_SET2,
+ NL1_CAP_PDCCH_MONITOR_ANY_OCCA_WITH_SPAN_GAP_SET3,
+ NL1_CAP_PDCCH_MONITOR_ANY_OCCA_WITH_SPAN_GAP_INVALID
+}NL1_CAP_PDCCH_MONITOR_ANY_OCCA_WITH_SPAN_GAP_E;
+
+typedef enum
+{
+ NL1_CAP_FALLBACK_SC,
+ NL1_CAP_FALLBACK_CAP1_ONLY,
+ NL1_CAP_FALLBACK_INVALID
+}NL1_CAP_FALLBACK_E;
+
+#endif
+
+typedef enum
+{
+ NL1_CAP_FULL_CAPABILITY,
+ NL1_CAP_GEMINI_DATA_SIM,
+ NL1_CAP_GEMINI_NON_DATA_SIM,
+ NL1_CAP_QUERY_OPTION_MAX_NUM
+}NL1_CAP_QUERY_OPTION_E;
+////////// End typedef //////////
+
+
+#endif /* #define __NL1_COMM_INTER_CORE_UE_CAPABILITY_H__ */
+
+
+/* Doxygene end of defgroup header!!! **********************************//**@}*/
diff --git a/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_wrapper_general_type.h b/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_wrapper_general_type.h
new file mode 100644
index 0000000..b53246a
--- /dev/null
+++ b/common/interface/modem/mt6297/common/nr/external/custom/nl1_comm_inter_core_wrapper_general_type.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/* Doxygene header ***********************************************************
+ *
+ * @file nl1_comm_inter_core_public.h
+ * @brief NL1 PUBLIC header file.
+ * @details Put those interfaces be used by other layers (non-NL1) here. \n
+ * Please make sure non-NL1 users can build pass w/o including other NL1 header files. \n
+ * It depends that we might need different public header files to serve different users.
+ * @addtogroup NL1
+ * @{
+ *//***************************************************************************/
+
+#ifndef __NL1_COMM_INTER_CORE_WRAPPER_GERNERAL_TYPE_H__
+#define __NL1_COMM_INTER_CORE_WRAPPER_GERNERAL_TYPE_H__
+
+#if defined(__MSONIC__)
+#include "kal_public.h"
+#elif defined(__MIPS_I7200__) || defined(__MIPS_IA__) || defined(L1_SIM)
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#else
+#error "Please check CPU type option!"
+#endif
+
+#endif /* #define __NL1_COMM_INTER_CORE_WRAPPER_GERNERAL_TYPE_H__ */
+
+/* Doxygene end of defgroup header!!! **********************************//**@}*/
diff --git a/common/interface/modem/public/lte_capability_public.h b/common/interface/modem/public/lte_capability_public.h
new file mode 100644
index 0000000..7024a48
--- /dev/null
+++ b/common/interface/modem/public/lte_capability_public.h
@@ -0,0 +1,66 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+#ifndef __LTE_CAPABILITY_PUBLIC_H__
+#define __LTE_CAPABILITY_PUBLIC_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * #define
+ ******************************************************************************/
+
+// Temp define for MP5
+#define __MT6297_MP5__ (0)
+#define __MT6297_MP5_AND_LATER__ (__MT6297_MP5__)
+
+// CCIM_CCH/CCIM_CRS capability define, owner: LTE fw inner team
+// Beyand cat12, consider CCs with 4RX ability
+#define ERRC_CCIM_CCH_CRS_MAX_NUM_CC_BEYAND_CAT12 (3)
+// CAT12 and below, consider max 3CC 2RX case
+#define ERRC_CCIM_CCH_CRS_MAX_NUM_CC (3)
+
+// CCIM_CCH and CCIM_CRS_API for ERRC report
+#define ERRC_GET_CCIM_CCH_INFO_BEYAND_CAT12(dL_CC_NUM) (((dL_CC_NUM) == 256) ? 1 : (((dL_CC_NUM) < ERRC_CCIM_CCH_CRS_MAX_NUM_CC_BEYAND_CAT12) ? (dL_CC_NUM) : ERRC_CCIM_CCH_CRS_MAX_NUM_CC_BEYAND_CAT12 ))
+#define ERRC_GET_CCIM_CCH_INFO(dL_CC_NUM) (((dL_CC_NUM) == 256) ? 1 : (((dL_CC_NUM) < ERRC_CCIM_CCH_CRS_MAX_NUM_CC) ? (dL_CC_NUM) : ERRC_CCIM_CCH_CRS_MAX_NUM_CC ))
+
+#define ERRC_GET_CCIM_CRS_INFO_BEYAND_CAT12(dL_CC_NUM) (((dL_CC_NUM) == 256) ? 1 : (((dL_CC_NUM) < ERRC_CCIM_CCH_CRS_MAX_NUM_CC_BEYAND_CAT12) ? (dL_CC_NUM) : ERRC_CCIM_CCH_CRS_MAX_NUM_CC_BEYAND_CAT12 ))
+#define ERRC_GET_CCIM_CRS_INFO(dL_CC_NUM) (((dL_CC_NUM) == 256) ? 1 : (((dL_CC_NUM) < ERRC_CCIM_CCH_CRS_MAX_NUM_CC) ? (dL_CC_NUM) : ERRC_CCIM_CCH_CRS_MAX_NUM_CC ))
+
+
+#endif /* #define __LTE_CAPABILITY_PUBLIC_H__ */
diff --git a/common/interface/modem/public/lte_rf_public.h b/common/interface/modem/public/lte_rf_public.h
new file mode 100644
index 0000000..4969d98
--- /dev/null
+++ b/common/interface/modem/public/lte_rf_public.h
@@ -0,0 +1,661 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup LTE_RF_PUBLIC
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file lte_rf_public.h
+ * @author Chester-WY Chen (MTK09580)
+ * @date 2016.09.29
+ * @brief LTE RF common define for DSP and MCU
+ * @details provide public/common information in
+ ******************************************************************************/
+
+#ifndef __LTE_RF_PUBLIC_H__
+#define __LTE_RF_PUBLIC_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * #define
+ ******************************************************************************/
+
+#define EL1D_RF_ID_MT6176 0x00000001
+#define EL1D_RF_ID_MT6179 0x00000002
+#define EL1D_RF_ID_MT6177L 0x00000004
+#define EL1D_RF_ID_MT6177M 0x00000008
+#define EL1D_RF_ID_TRINITYE1 0x00000010
+#define EL1D_RF_ID_TRINITYL 0x00000020
+#define EL1D_RF_ID_TRINITYE2 0x00000040
+#define EL1D_RF_ID_TRINITYLE2 0x00000080
+#define EL1D_RF_ID_TRINITY2L 0x00000100
+#define EL1D_RF_ID_COLUMBUSE1 0x00000200
+
+#if (defined __MD93__)
+/** LTE Common definition */
+//need to find a proper place to put this macro under external folder(ask MMRF)
+#define RF_MAX(m,n) (((m)>(n))?(m):(n))
+//wilson: to-do, need to review this setting based on the global SKU design
+#define LTE_BIT_MASK_BUFFER_SIZE (64/32) // support 64 band at max
+//#define LTE_SPEC_SUPPORT_BAND_NUM (25)
+#define LTE_TARGET_MAX_SUPPORT_BAND_NUM (25)
+#define LTE_TARGET_MAX_HPUE_SUPPORT_BAND_NUM (1)
+#define LTE_TARGET_CCA_SUPPORT_COMB_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM*2) //1 band can have RX_xC_TX_xC, RX_xC_TX_xA(No class D case, RX_xD_TX_xC, RX_xD_TX_xA, )
+#define LTE_MAX_SUPPORT_BAND_NUM (58 + 1) // LTEBandNone
+//wilson:to-do fix it after modifying MIPI freq assert check
+//#define LTE_MAX_SUPPORT_BAND_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + 1) // LTEBandNone
+
+// Filter Mode Feature
+#define LTE_FILTER_MAX_SUPPORT_BAND_NUM 5
+
+/** RF FE Feature related definition */
+// Spilt band Feature
+#define LTE_ERF_SPLIT_BAND 5 //How many bands need to split? Band28/Band41/Reserved
+#define LTE_ERF_MAX_SPLIT_PART 3 //Split to at most 3 parts
+
+
+//for Zion(6177M)
+#if defined(MT6177M_LTE_RF) || defined(__FEC_MT6177M_RF__)
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + (LTE_ERF_MAX_SPLIT_PART-1) * ( LTE_ERF_SPLIT_BAND - 1))
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_FILTER_MAX_SUPPORT_BAND_NUM + (LTE_ERF_MAX_SPLIT_PART-1) * ( LTE_ERF_SPLIT_BAND - 1))
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+
+#define LTE_ROUTE_TBL_SIZE_MAX ( LTE_TARGET_MAX_SUPPORT_BAND_NUM + 1 ) // single band + B44 alternative route
+#define LTE_ROUTE2_TBL_SIZE_MAX ( 1 ) // no CA support in MT6177M
+#define LTE_ROUTE_TX_TBL_SIZE_MAX ( LTE_TARGET_MAX_SUPPORT_BAND_NUM + 1 ) // single band + B44 alternative route
+#define LTE_USAGE_TBL_SIZE_MAX LTE_MAX_RX_TX_LINKAGE_NUM
+
+// Enable DL/UL RF CA support only for Merlot with 6177M
+#if (defined(__MT6177M_RFCCA_SUPPORT__) || defined(__FEC_MT6177M_RF__)) && defined(MT6761)
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#else
+#define IS_LTE_RF_DL_CA_SUPPORT 0
+#define IS_LTE_RF_UL_CA_SUPPORT 0
+#endif
+
+//for Bianco(6177L)
+#else
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (160) //80*2
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+
+#define LTE_ROUTE_TBL_SIZE_MAX ( 88 ) // number of single-band*4(88)
+#define LTE_ROUTE2_TBL_SIZE_MAX ( 22 ) // number of single-band*1(22), (Only 11 band support NCCA in 3GPP spec, and NCCA may have TWO RF route.)
+#define LTE_ROUTE_TX_TBL_SIZE_MAX (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2) // number of single-band*3(66)
+#define LTE_USAGE_TBL_SIZE_MAX LTE_MAX_RX_TX_LINKAGE_NUM
+
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+
+#endif
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+#elif (defined __MD95__)
+/********************************************************************************************************************
+ * !!!! [KH] the following defines come from 95DEV, need to refine and co-exsited with the above defines !!!! **
+*********************************************************************************************************************/
+#define LTE_BIT_MASK_BUFFER_SIZE (64/32) // support 64 band at max
+
+#define LTE_TARGET_SUPPORT_BAND_NUM_MAX (25)
+#define LTE_ROUTE_TX_TBL_SIZE_MAX (LTE_TARGET_SUPPORT_BAND_NUM_MAX * 2) // number of single-band*2(50)
+
+/** LTE Common definition */
+//need to find a proper place to put this macro under external folder(ask MMRF)
+#define RF_MAX(m,n) (((m)>(n))?(m):(n))
+//#define LTE_SPEC_SUPPORT_BAND_NUM (25)
+#define LTE_TARGET_MAX_SUPPORT_BAND_NUM LTE_TARGET_SUPPORT_BAND_NUM_MAX
+#define LTE_TARGET_MAX_HPUE_SUPPORT_BAND_NUM (1)
+#define LTE_TARGET_CCA_SUPPORT_COMB_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM*2) //1 band can have RX_xC_TX_xC, RX_xC_TX_xA(No class D case, RX_xD_TX_xC, RX_xD_TX_xA, )
+#define LTE_MAX_SUPPORT_BAND_NUM (58 + 1) // LTEBandNone
+
+/** RF FE Feature related definition */
+// Spilt band Feature
+#define LTE_ERF_SPLIT_BAND 5 //How many bands need to split? Band28/Band41/Reserved
+#define LTE_ERF_MAX_SPLIT_PART 3 //Split to at most 3 parts
+
+//for Trinity E1 &L
+//todo: If DSP needs to use the define as below, they need to add their compile option (like __FEC_MT6177M_RF__ in 93).
+ #if defined(TRINITYE1_LTE_RF) || defined(MT6190_LTE_RF) || defined(MT6190T_LTE_RF) || defined(MT6190M_LTE_RF) || defined(MT6195_LTE_RF)
+
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#define IS_LTE_RF_DL_MIMO_SUPPORT (1)
+
+/**********************************************************************************************************
+ * Route/Usage table size Define *
+ * *
+ * Formula of table size calculation: (XXX_Band_Num * YYY_Route_Per_Band + YYY_Route_Extra) *
+ * *
+ * LTE_TARGET_MAX_SUPPORT_BAND_NUM (25) *
+ * LTE_TARGET_MAX_SUPPORT_RX_4X4_BAND_NUM (10) *
+ * LTE_TARGET_MAX_SUPPORT_NCCA_BAND_NUM (11) *
+ * *
+ * LTE_RX_FE_ROUTE_PER_BAND (3) LTE_RX_FE_ROUTE_EXTRA (13) *
+ * LTE_RX_FE_4X4_ROUTE_PER_BAND (2) LTE_RX_FE_4X4_ROUTE_EXTRA (0) *
+ * LTE_TX_FE_ROUTE_PER_BAND (2) LTE_TX_FE_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_COMP_ROUTE_PER_BAND (3) LTE_RX_TYPE1_COMP_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_COMP_ROUTE_PER_BAND (2) LTE_RX_TYPE2_COMP_ROUTE_EXTRA (0) *
+ * LTE_TX_COMP_ROUTE_PER_BAND (2) LTE_TX_COMP_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_TOTAL_ROUTE_PER_BAND (3) LTE_RX_TYPE1_TOTAL_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE2_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE3_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE3_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE4_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE4_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_TX_TOTAL_ROUTE_PER_BAND (2) LTE_TX_TOTAL_ROUTE_EXTRA (0) *
+ **********************************************************************************************************/
+
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_4X4_NUM (20)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+
+#define LTE_MAX_RX_TYPE1_COMP_ROUTE_NUM (88)
+#define LTE_MAX_RX_TYPE2_COMP_ROUTE_NUM (22)
+#define LTE_MAX_TX_COMP_ROUTE_NUM (50)
+
+#define EL1D_ROUTE_TBL_SIZE_MAX (88)
+#define EL1D_ROUTE2_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE3_TBL_SIZE_MAX (50)
+#define EL1D_ROUTE4_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE_TX_TBL_SIZE_MAX LTE_ROUTE_TX_TBL_SIZE_MAX
+
+/* MAX_SUPPORT_CA_BAND_NUM = TOTAL_HW_COMBINATION(1SRX_MIMO_CFG, 2SRX_ALL_CFG, 3SRX_ALL_CFG, 4SRX_ALL_CFG) */
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (300)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+ /* where the last element is for end pattern for linkage parsing flow.*/
+#define EL1D_USAGE_TBL_SIZE_MAX (LTE_MAX_RX_TX_LINKAGE_NUM)
+
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+//CCA Capability API use
+#define LTE_TX_FE_ROUTE_PER_BAND_MAX (10)
+#define LTE_TX_COMP_ROUTE_PER_BAND_MAX (10)
+
+#elif defined(MT6185M_LTE_RF) || defined(MT6186_LTE_RF)|| defined(MT6186M_LTE_RF)
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#define IS_LTE_RF_DL_MIMO_SUPPORT (1)
+
+/**********************************************************************************************************
+ * Route/Usage table size Define *
+ * *
+ * Formula of table size calculation: (XXX_Band_Num * YYY_Route_Per_Band + YYY_Route_Extra) *
+ * *
+ * LTE_TARGET_MAX_SUPPORT_BAND_NUM (25) *
+ * LTE_TARGET_MAX_SUPPORT_RX_4X4_BAND_NUM (10) *
+ * LTE_TARGET_MAX_SUPPORT_NCCA_BAND_NUM (11) *
+ * *
+ * LTE_RX_FE_ROUTE_PER_BAND (3) LTE_RX_FE_ROUTE_EXTRA (13) *
+ * LTE_RX_FE_4X4_ROUTE_PER_BAND (2) LTE_RX_FE_4X4_ROUTE_EXTRA (0) *
+ * LTE_TX_FE_ROUTE_PER_BAND (2) LTE_TX_FE_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_COMP_ROUTE_PER_BAND (3) LTE_RX_TYPE1_COMP_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_COMP_ROUTE_PER_BAND (2) LTE_RX_TYPE2_COMP_ROUTE_EXTRA (0) *
+ * LTE_TX_COMP_ROUTE_PER_BAND (2) LTE_TX_COMP_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_TOTAL_ROUTE_PER_BAND (3) LTE_RX_TYPE1_TOTAL_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE2_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE3_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE3_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE4_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE4_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_TX_TOTAL_ROUTE_PER_BAND (2) LTE_TX_TOTAL_ROUTE_EXTRA (0) *
+ **********************************************************************************************************/
+
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_4X4_NUM (20)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+
+#define LTE_MAX_RX_TYPE1_COMP_ROUTE_NUM (88)
+#define LTE_MAX_RX_TYPE2_COMP_ROUTE_NUM (22)
+#define LTE_MAX_TX_COMP_ROUTE_NUM (50)
+
+#define EL1D_ROUTE_TBL_SIZE_MAX (88)
+#define EL1D_ROUTE2_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE3_TBL_SIZE_MAX (50)
+#define EL1D_ROUTE4_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE_TX_TBL_SIZE_MAX LTE_ROUTE_TX_TBL_SIZE_MAX
+
+/* MAX_SUPPORT_CA_BAND_NUM = TOTAL_HW_COMBINATION(1SRX_MIMO_CFG, 2SRX_ALL_CFG, 3SRX_ALL_CFG, 4SRX_ALL_CFG) */
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (300)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+ /* where the last element is for end pattern for linkage parsing flow.*/
+#define EL1D_USAGE_TBL_SIZE_MAX (LTE_MAX_RX_TX_LINKAGE_NUM)
+
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+//CCA Capability API use
+#define LTE_TX_FE_ROUTE_PER_BAND_MAX (10)
+#define LTE_TX_COMP_ROUTE_PER_BAND_MAX (10)
+#else
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#define IS_LTE_RF_DL_MIMO_SUPPORT (1)
+
+/**********************************************************************************************************
+ * Route/Usage table size Define *
+ * *
+ * Formula of table size calculation: (XXX_Band_Num * YYY_Route_Per_Band + YYY_Route_Extra) *
+ * *
+ * LTE_TARGET_MAX_SUPPORT_BAND_NUM (25) *
+ * LTE_TARGET_MAX_SUPPORT_RX_4X4_BAND_NUM (10) *
+ * LTE_TARGET_MAX_SUPPORT_NCCA_BAND_NUM (11) *
+ * *
+ * LTE_RX_FE_ROUTE_PER_BAND (3) LTE_RX_FE_ROUTE_EXTRA (13) *
+ * LTE_RX_FE_4X4_ROUTE_PER_BAND (2) LTE_RX_FE_4X4_ROUTE_EXTRA (0) *
+ * LTE_TX_FE_ROUTE_PER_BAND (2) LTE_TX_FE_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_COMP_ROUTE_PER_BAND (3) LTE_RX_TYPE1_COMP_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_COMP_ROUTE_PER_BAND (2) LTE_RX_TYPE2_COMP_ROUTE_EXTRA (0) *
+ * LTE_TX_COMP_ROUTE_PER_BAND (2) LTE_TX_COMP_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_TOTAL_ROUTE_PER_BAND (3) LTE_RX_TYPE1_TOTAL_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE2_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE3_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE3_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE4_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE4_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_TX_TOTAL_ROUTE_PER_BAND (2) LTE_TX_TOTAL_ROUTE_EXTRA (0) *
+ **********************************************************************************************************/
+
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_4X4_NUM (20)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+
+#define LTE_MAX_RX_TYPE1_COMP_ROUTE_NUM (88)
+#define LTE_MAX_RX_TYPE2_COMP_ROUTE_NUM (22)
+#define LTE_MAX_TX_COMP_ROUTE_NUM (50)
+
+#define EL1D_ROUTE_TBL_SIZE_MAX (88)
+#define EL1D_ROUTE2_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE3_TBL_SIZE_MAX (50)
+#define EL1D_ROUTE4_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE_TX_TBL_SIZE_MAX LTE_ROUTE_TX_TBL_SIZE_MAX
+
+/* MAX_SUPPORT_CA_BAND_NUM = TOTAL_HW_COMBINATION(1SRX_MIMO_CFG, 2SRX_ALL_CFG, 3SRX_ALL_CFG, 4SRX_ALL_CFG) */
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (300)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+ /* where the last element is for end pattern for linkage parsing flow.*/
+#define EL1D_USAGE_TBL_SIZE_MAX (LTE_MAX_RX_TX_LINKAGE_NUM)
+
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+//CCA Capability API use
+#define LTE_TX_FE_ROUTE_PER_BAND_MAX (10)
+#define LTE_TX_COMP_ROUTE_PER_BAND_MAX (10)
+#endif
+
+#elif (defined __MD97__)||(defined __MD97P__)
+/********************************************************************************************************************
+ * !!!! [KH] the following defines come from 95DEV, need to refine and co-exsited with the above defines !!!! **
+*********************************************************************************************************************/
+#define LTE_BIT_MASK_BUFFER_SIZE (96/32) // support 96 band at max
+#if defined(__SINGLE_BAND_NUM_EXTENDED__)
+#define LTE_TARGET_SUPPORT_BAND_NUM_MAX (35)
+#else
+#define LTE_TARGET_SUPPORT_BAND_NUM_MAX (25)
+#endif
+#define LTE_ROUTE_TX_TBL_SIZE_MAX (LTE_TARGET_SUPPORT_BAND_NUM_MAX * 2) // number of single-band*2(50)
+
+/** LTE Common definition */
+//need to find a proper place to put this macro under external folder(ask MMRF)
+#define RF_MAX(m,n) (((m)>(n))?(m):(n))
+//#define LTE_SPEC_SUPPORT_BAND_NUM (25)
+#define LTE_TARGET_MAX_SUPPORT_BAND_NUM LTE_TARGET_SUPPORT_BAND_NUM_MAX
+#define LTE_TARGET_MAX_HPUE_SUPPORT_BAND_NUM (1)
+#define LTE_TARGET_CCA_SUPPORT_COMB_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM*2) //1 band can have RX_xC_TX_xC, RX_xC_TX_xA(No class D case, RX_xD_TX_xC, RX_xD_TX_xA, )
+#define LTE_MAX_SUPPORT_BAND_NUM (58 + 1) // LTEBandNone
+
+/** RF FE Feature related definition */
+// Spilt band Feature
+#define LTE_ERF_SPLIT_BAND 5 //How many bands need to split? Band28/Band41/Reserved
+#define LTE_ERF_MAX_SPLIT_PART 3 //Split to at most 3 parts
+
+//for Trinity E1 &L
+//todo: If DSP needs to use the define as below, they need to add their compile option (like __FEC_MT6177M_RF__ in 93).
+ #if defined(TRINITYE1_LTE_RF) || defined(MT6190_LTE_RF) || defined(MT6190T_LTE_RF) || defined(MT6190M_LTE_RF) || defined(MT6195_LTE_RF)
+
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#define IS_LTE_RF_DL_MIMO_SUPPORT (1)
+
+/**********************************************************************************************************
+ * Route/Usage table size Define *
+ * *
+ * Formula of table size calculation: (XXX_Band_Num * YYY_Route_Per_Band + YYY_Route_Extra) *
+ * *
+ * LTE_TARGET_MAX_SUPPORT_BAND_NUM (25) *
+ * LTE_TARGET_MAX_SUPPORT_RX_4X4_BAND_NUM (10) *
+ * LTE_TARGET_MAX_SUPPORT_NCCA_BAND_NUM (11) *
+ * *
+ * LTE_RX_FE_ROUTE_PER_BAND (3) LTE_RX_FE_ROUTE_EXTRA (13) *
+ * LTE_RX_FE_4X4_ROUTE_PER_BAND (2) LTE_RX_FE_4X4_ROUTE_EXTRA (0) *
+ * LTE_TX_FE_ROUTE_PER_BAND (2) LTE_TX_FE_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_COMP_ROUTE_PER_BAND (3) LTE_RX_TYPE1_COMP_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_COMP_ROUTE_PER_BAND (2) LTE_RX_TYPE2_COMP_ROUTE_EXTRA (0) *
+ * LTE_TX_COMP_ROUTE_PER_BAND (2) LTE_TX_COMP_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_TOTAL_ROUTE_PER_BAND (3) LTE_RX_TYPE1_TOTAL_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE2_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE3_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE3_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE4_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE4_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_TX_TOTAL_ROUTE_PER_BAND (2) LTE_TX_TOTAL_ROUTE_EXTRA (0) *
+ **********************************************************************************************************/
+
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_4X4_NUM (20)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+
+#define LTE_MAX_RX_TYPE1_COMP_ROUTE_NUM (88)
+#define LTE_MAX_RX_TYPE2_COMP_ROUTE_NUM (22)
+#define LTE_MAX_TX_COMP_ROUTE_NUM (50)
+
+#define EL1D_ROUTE_TBL_SIZE_MAX (88)
+#define EL1D_ROUTE2_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE3_TBL_SIZE_MAX (50)
+#define EL1D_ROUTE4_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE_TX_TBL_SIZE_MAX LTE_ROUTE_TX_TBL_SIZE_MAX
+
+/* MAX_SUPPORT_CA_BAND_NUM = TOTAL_HW_COMBINATION(1SRX_MIMO_CFG, 2SRX_ALL_CFG, 3SRX_ALL_CFG, 4SRX_ALL_CFG) */
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (300)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+#define EL1D_USAGE_TBL_SIZE_MAX (LTE_MAX_RX_TX_LINKAGE_NUM)
+
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+//CCA Capability API use
+#define LTE_TX_FE_ROUTE_PER_BAND_MAX (10)
+#define LTE_TX_COMP_ROUTE_PER_BAND_MAX (10)
+
+ #elif defined(MT6185M_LTE_RF)
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#define IS_LTE_RF_DL_MIMO_SUPPORT (1)
+
+/**********************************************************************************************************
+ * Route/Usage table size Define *
+ * *
+ * Formula of table size calculation: (XXX_Band_Num * YYY_Route_Per_Band + YYY_Route_Extra) *
+ * *
+ * LTE_TARGET_MAX_SUPPORT_BAND_NUM (25) *
+ * LTE_TARGET_MAX_SUPPORT_RX_4X4_BAND_NUM (10) *
+ * LTE_TARGET_MAX_SUPPORT_NCCA_BAND_NUM (11) *
+ * *
+ * LTE_RX_FE_ROUTE_PER_BAND (3) LTE_RX_FE_ROUTE_EXTRA (13) *
+ * LTE_RX_FE_4X4_ROUTE_PER_BAND (2) LTE_RX_FE_4X4_ROUTE_EXTRA (0) *
+ * LTE_TX_FE_ROUTE_PER_BAND (2) LTE_TX_FE_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_COMP_ROUTE_PER_BAND (3) LTE_RX_TYPE1_COMP_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_COMP_ROUTE_PER_BAND (2) LTE_RX_TYPE2_COMP_ROUTE_EXTRA (0) *
+ * LTE_TX_COMP_ROUTE_PER_BAND (2) LTE_TX_COMP_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_TOTAL_ROUTE_PER_BAND (3) LTE_RX_TYPE1_TOTAL_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE2_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE3_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE3_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE4_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE4_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_TX_TOTAL_ROUTE_PER_BAND (2) LTE_TX_TOTAL_ROUTE_EXTRA (0) *
+ **********************************************************************************************************/
+
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_4X4_NUM (20)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+
+#define LTE_MAX_RX_TYPE1_COMP_ROUTE_NUM (88)
+#define LTE_MAX_RX_TYPE2_COMP_ROUTE_NUM (22)
+#define LTE_MAX_TX_COMP_ROUTE_NUM (50)
+
+#define EL1D_ROUTE_TBL_SIZE_MAX (88)
+#define EL1D_ROUTE2_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE3_TBL_SIZE_MAX (50)
+#define EL1D_ROUTE4_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE_TX_TBL_SIZE_MAX LTE_ROUTE_TX_TBL_SIZE_MAX
+
+/* MAX_SUPPORT_CA_BAND_NUM = TOTAL_HW_COMBINATION(1SRX_MIMO_CFG, 2SRX_ALL_CFG, 3SRX_ALL_CFG, 4SRX_ALL_CFG) */
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (300)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+#define EL1D_USAGE_TBL_SIZE_MAX (LTE_MAX_RX_TX_LINKAGE_NUM)
+
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+//CCA Capability API use
+#define LTE_TX_FE_ROUTE_PER_BAND_MAX (10)
+#define LTE_TX_COMP_ROUTE_PER_BAND_MAX (10)
+ #else
+#define IS_LTE_RF_DL_CA_SUPPORT 1
+#define IS_LTE_RF_UL_CA_SUPPORT 1
+#define IS_LTE_RF_DL_MIMO_SUPPORT (1)
+
+/**********************************************************************************************************
+ * Route/Usage table size Define *
+ * *
+ * Formula of table size calculation: (XXX_Band_Num * YYY_Route_Per_Band + YYY_Route_Extra) *
+ * *
+ * LTE_TARGET_MAX_SUPPORT_BAND_NUM (25) *
+ * LTE_TARGET_MAX_SUPPORT_RX_4X4_BAND_NUM (10) *
+ * LTE_TARGET_MAX_SUPPORT_NCCA_BAND_NUM (11) *
+ * *
+ * LTE_RX_FE_ROUTE_PER_BAND (3) LTE_RX_FE_ROUTE_EXTRA (13) *
+ * LTE_RX_FE_4X4_ROUTE_PER_BAND (2) LTE_RX_FE_4X4_ROUTE_EXTRA (0) *
+ * LTE_TX_FE_ROUTE_PER_BAND (2) LTE_TX_FE_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_COMP_ROUTE_PER_BAND (3) LTE_RX_TYPE1_COMP_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_COMP_ROUTE_PER_BAND (2) LTE_RX_TYPE2_COMP_ROUTE_EXTRA (0) *
+ * LTE_TX_COMP_ROUTE_PER_BAND (2) LTE_TX_COMP_ROUTE_EXTRA (0) *
+ * *
+ * LTE_RX_TYPE1_TOTAL_ROUTE_PER_BAND (3) LTE_RX_TYPE1_TOTAL_ROUTE_EXTRA (13) *
+ * LTE_RX_TYPE2_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE2_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE3_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE3_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_RX_TYPE4_TOTAL_ROUTE_PER_BAND (2) LTE_RX_TYPE4_TOTAL_ROUTE_EXTRA (0) *
+ * LTE_TX_TOTAL_ROUTE_PER_BAND (2) LTE_TX_TOTAL_ROUTE_EXTRA (0) *
+ **********************************************************************************************************/
+
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM (88)
+#define LTE_MAX_SUPPORT_RX_FE_ROUTE_4X4_NUM (20)
+#define LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM * 2)
+
+#define LTE_MAX_RX_TYPE1_COMP_ROUTE_NUM (88)
+#define LTE_MAX_RX_TYPE2_COMP_ROUTE_NUM (22)
+#define LTE_MAX_TX_COMP_ROUTE_NUM (50)
+
+#define EL1D_ROUTE_TBL_SIZE_MAX (88)
+#define EL1D_ROUTE2_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE3_TBL_SIZE_MAX (50)
+#define EL1D_ROUTE4_TBL_SIZE_MAX (22)
+#define EL1D_ROUTE_TX_TBL_SIZE_MAX LTE_ROUTE_TX_TBL_SIZE_MAX
+
+/* MAX_SUPPORT_CA_BAND_NUM = TOTAL_HW_COMBINATION(1SRX_MIMO_CFG, 2SRX_ALL_CFG, 3SRX_ALL_CFG, 4SRX_ALL_CFG) */
+#define LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM (300)
+#define LTE_MAX_RX_TX_LINKAGE_NUM (LTE_TARGET_MAX_SUPPORT_BAND_NUM + LTE_TARGET_MAX_SUPPORT_CA_BAND_NUM)
+#define EL1D_USAGE_TBL_SIZE_MAX (LTE_MAX_RX_TX_LINKAGE_NUM)
+
+#define LTE_MAX_SUPPORT_FE_ROUTE_NUM RF_MAX((LTE_MAX_SUPPORT_RX_FE_ROUTE_NUM), (LTE_MAX_SUPPORT_TX_FE_ROUTE_NUM))
+
+//CCA Capability API use
+#define LTE_TX_FE_ROUTE_PER_BAND_MAX (10)
+#define LTE_TX_COMP_ROUTE_PER_BAND_MAX (10)
+ #endif
+
+#else
+#error "Should define at least a kind of BB being used."
+#endif
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Constant
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variables (Extern)
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global Functions Prototype (Interface)
+ ******************************************************************************/
+
+#endif /*__LTE_RF_PUBLIC_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/common/interface/modem/public/nr_rf_public.h b/common/interface/modem/public/nr_rf_public.h
new file mode 100644
index 0000000..9e6c812
--- /dev/null
+++ b/common/interface/modem/public/nr_rf_public.h
@@ -0,0 +1,111 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup NR_RF_PUBLIC
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file nr_rf_public.h
+ * @author Wei-Han Tseng (MTK09272)
+ * @date 2018.09.16
+ * @brief NR RF common define for DSP and MCU
+ * @details provide public/common information in
+ ******************************************************************************/
+
+#ifndef __NR_RF_PUBLIC_H__
+#define __NR_RF_PUBLIC_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * #define
+ ******************************************************************************/
+
+#define NL1_RF_ID_MT6176 0x00000001
+#define NL1_RF_ID_MT6179 0x00000002
+#define NL1_RF_ID_MT6177L 0x00000004
+#define NL1_RF_ID_MT6177M 0x00000008
+#define NL1_RF_ID_TRINITYE1 0x00000010
+#define NL1_RF_ID_TRINITYL 0x00000020
+#define NL1_RF_ID_TRINITYE2 0x00000040
+#define NL1_RF_ID_TRINITYLE2 0x00000080
+#define NL1_RF_ID_TRINITY2L 0x00000100
+#define NL1_RF_ID_COLUMBUS 0x00000200
+
+#if (defined __MD97__) || (defined __MD97P__)
+
+#else
+#error "Should define at least a kind of BB being used."
+#endif
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Constant
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variables (Extern)
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global Functions Prototype (Interface)
+ ******************************************************************************/
+
+#endif /*__NR_RF_PUBLIC_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/common/interface/service/dsp_control/L1_module_registration.h b/common/interface/service/dsp_control/L1_module_registration.h
new file mode 100644
index 0000000..5eca5db
--- /dev/null
+++ b/common/interface/service/dsp_control/L1_module_registration.h
@@ -0,0 +1,37 @@
+
+/*****************************************
+* Prototype
+* L1_MODULE_REGISTER(module_name, which_WFI, dsp_firmware_used_by_the_module, deactivate_irq_mode_callback)
+*
+* Parameter
+* module_name: please add L1_MODULE_ as prefix.
+* which_WFI: U2C_WFI_LTE_AFC, U2C_WFI_LTE_DCI, U2C_WFI_TDD, U2C_WFI_FDD, U2C_WFI_FDD_C2K, U2C_WFI_SPEECH, U2C_WFI_SS, M2C_WFI_SS, S2C_WFI_SS
+* If a L1 module need to set wfi of two or more dsp cores, please use "|" to connect them.
+* dsp_firmware_used_by_the_module: please refernce to dsp_firmware_registration.h and add _BIT as postfix.
+* If a L1 module need to use two or more dsp firmwares, please use "|" to connect them.
+* deactivate_irq_mode_callback: Callback function name for deactivate irq mode. If you do not need to do anything after receive wfi, please register "Default_deactivate_irq_callback" as callback function.
+*
+* Example
+* L1_MODULE_REGISTER(L1_MODULE_xxxxx, U2C_WFI_LTE_AFC, DSP_FW_INNER_BIT|DSP_FW_BRP_BIT, Default_deactivate_irq_callback) //There is no space between "dsp_firmware_used_by_the_module" and "|".
+* L1_MODULE_REGISTER(L1_MODULE_ABC, M2C_WFI_SS|S2C_WFI_SS, DSP_FW_SS4_BIT|DSP_FW_SS5_BIT, Default_deactivate_irq_callback) //There is no space between "which_WFI" and "|".
+*
+* Limitation
+* One dsp firmware can only be used by one L1 module.
+* The callback function of deactivate irq mode can not contain any argument and return value.
+*****************************************/
+L1_MODULE_REGISTER(L1_MODULE_SS_USIP, U2C_WFI_SS, DSP_FW_SS_USIP_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_SS_RAKE, M2C_WFI_SS, DSP_FW_SS_RAKE_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_SS_SONIC, S2C_WFI_SS, DSP_FW_SS_SONIC_BIT, Default_deactivate_irq_callback)
+
+L1_MODULE_REGISTER(L1_MODULE_GSM, U2C_WFI_SS, DSP_FW_GSM_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_FDD_RAKE, M2C_WFI_SS, DSP_FW_RAKE_FDD_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_FDD_INNER, U2C_WFI_SS, DSP_FW_INNER_FDD_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_FDD_BRP, U2C_WFI_SS, DSP_FW_BRP_FDD_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_C2K_1XRTT_RAKE,M2C_WFI_SS, DSP_FW_RAKE_C2K_1XRTT_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_C2K_EVDO_RAKE, M2C_WFI_SS, DSP_FW_RAKE_C2K_EVDO_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_C2K_INNER, U2C_WFI_SS, DSP_FW_INNER_C2K_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_LTE_RX, U2C_WFI_SS, DSP_FW_INNER_LTE_BIT|DSP_FW_INNER_LTE_CSI_BIT|DSP_FW_BRP_LTE_BIT|DSP_FW_BRP_LTE_CSI_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_LTE_CMP, U2C_WFI_SS, DSP_FW_INNER_LTE_CM_BIT|DSP_FW_INNER_LTE_POS_BIT|DSP_FW_BRP_LTE_NCM_BIT|DSP_FW_BRP_LTE_POS_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_NR, S2C_WFI_SS, DSP_FW_NR_IQDUMP_BIT|DSP_FW_NR_SLM_TG0_FR1_BIT|DSP_FW_NR_SLM_TG1_FR1_BIT|DSP_FW_NR_SLM_TG2_FR1_BIT|DSP_FW_NR_SLM_TG0_FR2_BIT|DSP_FW_NR_SLM_TG1_FR2_BIT|DSP_FW_NR_SLM_TG2_FR2_BIT|DSP_FW_NR_SLM_TG0_NONFR_BIT|DSP_FW_NR_SLM_TG1_NONFR_BIT|DSP_FW_NR_SLM_TG2_NONFR_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_SPEECH, U2C_WFI_SPEECH, DSP_FW_SPEECH_BIT, Default_deactivate_irq_callback)
+L1_MODULE_REGISTER(L1_MODULE_TDSCDMA, U2C_WFI_TDD, DSP_FW_INNER_TDSCDMA_BIT|DSP_FW_INNER_TDSCDMA_MEAS_BIT, Default_deactivate_irq_callback)
diff --git a/common/interface/service/dsp_control/dsp_control_public.h b/common/interface/service/dsp_control/dsp_control_public.h
new file mode 100644
index 0000000..fa5a707
--- /dev/null
+++ b/common/interface/service/dsp_control/dsp_control_public.h
@@ -0,0 +1,524 @@
+#ifndef _DSP_CONTROL_PUBLIC_H_
+#define _DSP_CONTROL_PUBLIC_H_
+
+#if defined(__MD97__) || defined(__MD97P__)
+
+/***** Common Definition *****/
+#define RAKE_CONTROL_STATUS RAKE_BOOTDONECHECK_RETVALUE
+#define USIP_CONTROL_STATUS uSIP_BOOTDONECHECK_RETVALUE
+
+/***************************************************************/
+/********* Common Macro ****************************************/
+/***************************************************************/
+#define CORE_ID_INIT_VALUE 0xDC11DC11
+#define USIP_VIC_ENABLE_FILL 0x20170526
+#define USIP_VIC_ENABLE_CLEAR 0x0
+
+/***************************************************************/
+/********* Common Enum ***************************************/
+/***************************************************************/
+/* RAT user Enum */
+typedef enum{
+ DSP_CTRL_RAT_LTE,
+ DSP_CTRL_RAT_WCDMA,
+ DSP_CTRL_RAT_C2K,
+ DSP_CTRL_RAT_TDSCDMA,
+ DSP_CTRL_RAT_SPEECH,
+ DSP_CTRL_RAT_NR,
+ DSP_CTRL_RAT_NUM
+} DSP_CTRL_RAT_ENUM;
+
+/* Core Enum */
+typedef enum{
+ DSP_CONTROL_USIP0_INNER,
+ DSP_CONTROL_USIP0_BRP,
+ DSP_CONTROL_USIP1_SPEECH,
+ DSP_CONTROL_USIP1_FEC,
+ DSP_CONTROL_RAKE,
+ DSP_CONTROL_SONIC,
+ DSP_CONTROL_CDIF_CORE_NUM
+} DSP_CDIF_CORE_ENUM;
+
+/* Idle Flag Enum */
+typedef enum{
+ DSP_CONTROL_IDLE,
+ DSP_CONTROL_BUSY
+} DSP_CONTROL_IDLE_FLAG_STATUS;
+
+#define DSP_THREAD_STATUS DSP_CONTROL_IDLE_FLAG_STATUS
+
+/* Sleep Flow Branch */
+typedef enum{
+ DSP_DORMANT_FLOW,
+ DSP_ABORT_FLOW,
+ DSP_WAKEUP_FLOW,
+ DSP_CTRL_FLOW_NUM
+} DSP_SLEEP_CTRL_FLOW_TYPE_BRANCH;
+
+typedef enum{
+ CMIFZI_EN,
+ CMIFZI_DIS
+} CMIFZI_CTRL;
+
+typedef enum{
+ DDL_WAY_IS_BY_CORE = 0x0A0A0A0A,
+ DDL_WAY_IS_BY_GDMA = 0x0B0B0B0B,
+ DDL_WAY_DEFAULT = 0x0C0C0C0C
+} DDL_WAY;
+
+typedef enum {
+ DDL_STATUS_INIT = 0x0A000000,
+ DDL_STATUS_ONGOING = 0x0B000000,
+ DDL_STATUS_DONE = 0x0C000000,
+ DDL_STATUS_GDMA_DONE=0x0D000000,
+ DDL_STATUS_RE_DDL =0x0E000000,
+ DDL_MODE_NOT_SUPPORT_LTE = 0x0AAA0000,
+ DDL_MODE_WAIT_RESPONSE_CLR_DDL_PROTECTION = 0x0BBB0000,
+ DDL_STATUS_DEFAULT = 0x0ABC0000
+}DDL_STATUS;
+
+typedef enum {
+ DDL_MODE_START=0x0,
+
+ //BRP
+ DDL_MODE_BRP_LTE=0x1, // should be the first
+ DDL_MODE_BRP_FDD=0x2,
+ DDL_MODE_BRP_END=0x3,
+
+ //FEC-TX
+ DDL_MODE_FEC_TX_C2K =0x4, // should be the first
+ DDL_MODE_FEC_TX_WCDMA=0x5,
+ DDL_MODE_FEC_TX_LTE =0x6,
+ DDL_MODE_FEC_TX_END =0x7,
+
+ //FEC-RX
+ DDL_MODE_FEC_RX_C2K =0x8, // should be the first
+ DDL_MODE_FEC_RX_WCDMA=0x9,
+ DDL_MODE_FEC_RX_END =0xA,
+
+ //SCQ16
+ DDL_MODE_SCQ16_LTE=0xB, // should be the first
+ DDL_MODE_SCQ16_FDD=0xC,
+ DDL_MODE_SCQ16_TDD=0xD,
+ DDL_MODE_SCQ16_C2K=0xE,
+ DDL_MODE_SCQ16_END=0xF,
+
+ //RAKE
+ DDL_MODE_RAKE_FDD=0x10, // should be the first
+ DDL_MODE_RAKE_C2K=0x11,
+ DDL_MODE_RAKE_LTE=0x12,
+ DDL_MODE_RAKE_END=0x13,
+
+ DDL_MODE_END=0x14,
+
+ DDL_MODE_NUM=0x15,
+ DDL_MODE_DEFAULT = 0x6214,
+ DDL_MODE_MAX = 0xFFFF,
+} DDL_MODE;
+
+typedef enum {
+ SCQ16_LP_COMMON,
+ SCQ16_LP_LTE,
+ SCQ16_LP_FDD,
+ SCQ16_LP_TDD,
+ SCQ16_LP_C2K,
+ SCQ16_LP_NUM
+} SCQ16_LOW_POWER_REGION;
+
+#define DDL_MODE_BRP_START (DDL_MODE_BRP_LTE)
+#define DDL_MODE_FEC_TX_START (DDL_MODE_FEC_TX_C2K)
+#define DDL_MODE_FEC_RX_START (DDL_MODE_FEC_RX_C2K)
+#define DDL_MODE_SCQ16_START (DDL_MODE_SCQ16_LTE)
+#define DDL_MODE_RAKE_START (DDL_MODE_RAKE_FDD)
+
+
+/***************************************************************/
+/********* Extern logger Registration callback ****/
+/***************************************************************/
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#undef RAKEAPI_USERNAME
+#define USIPAPI_USERNAME_INNER(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define USIPAPI_USERNAME_BRP(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define USIPAPI_USERNAME_FEC(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define USIPAPI_USERNAME_SPEECH(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define RAKEAPI_USERNAME(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define SONICAPI_USERNAME(func) extern void func(DSP_CDIF_CORE_ENUM);
+
+#include "usip_inner_logger_registation.h"
+#include "usip_brp_logger_registation.h"
+#include "usip_fec_logger_registation.h"
+#include "usip_speech_logger_registation.h"
+#include "rake_logger_registation.h"
+#include "sonic_logger_registation.h"
+/***************************************************************/
+/********* Enum for logger Registration callback ****/
+/***************************************************************/
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#undef RAKEAPI_USERNAME
+#undef SONICAPI_USERNAME
+
+#define USIPAPI_USERNAME_INNER(func) USIP_DEACTIVATE_INNER_CB_##func,
+typedef enum{
+ #include "usip_inner_logger_registation.h"
+ USIP_INNER_DEACTIVATE_CB_SIZE
+} USIP_INNER_DEACTIVATE_CB_ENUM;
+
+#define USIPAPI_USERNAME_BRP(func) USIP_DEACTIVATE_BRP_CB_##func,
+typedef enum{
+ #include "usip_brp_logger_registation.h"
+ USIP_BRP_DEACTIVATE_CB_SIZE
+} USIP_BRP_DEACTIVATE_CB_ENUM;
+
+#define USIPAPI_USERNAME_FEC(func) USIP_DEACTIVATE_FEC_CB_##func,
+typedef enum{
+ #include "usip_fec_logger_registation.h"
+ USIP_FEC_DEACTIVATE_CB_SIZE
+} USIP_FEC_DEACTIVATE_CB_ENUM;
+
+#define USIPAPI_USERNAME_SPEECH(func) USIP_DEACTIVATE_SPEECH_CB_##func,
+typedef enum{
+ #include "usip_speech_logger_registation.h"
+ USIP_SPEECH_DEACTIVATE_CB_SIZE
+} USIP_SPEECH_DEACTIVATE_CB_ENUM;
+
+#define RAKEAPI_USERNAME(func) RAKE_DEACTIVATE_CB_##func,
+typedef enum{
+ #include "rake_logger_registation.h"
+ RAKE_DEACTIVATE_CB_SIZE
+} RAKE_DEACTIVATE_CB_ENUM;
+
+#define SONICAPI_USERNAME(func) SONIC_DEACTIVATE_CB_##func,
+typedef enum{
+ #include "sonic_logger_registation.h"
+ SONIC_DEACTIVATE_CB_SIZE
+} SONIC_DEACTIVATE_CB_ENUM;
+
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#undef RAKEAPI_USERNAME
+#undef SONICAPI_USERNAME
+
+/***************************************************************/
+/********* Enum for dsp firmware registration ****/
+/***************************************************************/
+#undef DSP_FW_REGISTER
+#define DSP_FW_REGISTER(name, thread) name,
+
+typedef enum{
+ #include "dsp_firmware_registration.h"
+ DSP_FW_REGISTRATION_NUM
+} DSP_FIRMWARE_REGISTRATION;
+
+#undef DSP_FW_REGISTER
+#define DSP_FW_REGISTER(name, thread) name##_BIT = (1 << name),
+
+typedef enum{
+ #include "dsp_firmware_registration.h"
+ DSP_FW_REGISTRATION_DUMMY
+} DSP_FIRMWARE_REGISTRATION_BIT;
+
+#undef DSP_FW_REGISTER
+/***************************************************************/
+/********* Enum for L1 module registration ****/
+/***************************************************************/
+#undef L1_MODULE_REGISTER
+#define L1_MODULE_REGISTER(name, wfi, firmware, cb) name,
+
+typedef enum{
+ #include "L1_module_registration.h"
+ L1_MODULE_REGISTRATION_NUM,
+ DEFAULT_L1_MODULE
+} L1_MODULE_REGISTRATION;
+
+#undef L1_MODULE_REGISTER
+#define L1_MODULE_REGISTER(name, wfi, firmware, cb) name##_BIT = (1 << name),
+
+typedef enum{
+ #include "L1_module_registration.h"
+ L1_MODULE_REGISTRATION_DUMMY
+} L1_MODULE_REGISTRATION_BIT;
+
+#undef L1_MODULE_REGISTER
+
+typedef enum {
+ DSP_CONTROL_CUIF_ENUM_N0,
+ DSP_CONTROL_CUIF_ENUM_N1,
+ DSP_CONTROL_CUIF_ENUM_N2,
+ DSP_CONTROL_CUIF_ENUM_N3,
+ DSP_CONTROL_CUIF_ENUM_N4,
+ DSP_CONTROL_CUIF_ENUM_N5,
+ DSP_CONTROL_CUIF_ENUM_N6,
+ DSP_CONTROL_CUIF_ENUM_N7,
+ DSP_CONTROL_CUIF_ENUM_N8,
+ DSP_CONTROL_CUIF_ENUM_N9,
+ DSP_CONTROL_CUIF_ENUM_N10,
+ DSP_CONTROL_CUIF_ENUM_N11,
+ DSP_CONTROL_CUIF_ENUM_N12,
+ DSP_CONTROL_CUIF_ENUM_N13,
+ DSP_CONTROL_CUIF_ALL_NUM
+}DSP_CONTROL_CUIF_ENUM;
+
+#define U2C_WFI_LTE_AFC (0x1 << DSP_CONTROL_CUIF_ENUM_N4)
+#define U2C_WFI_LTE_DCI (0x1 << DSP_CONTROL_CUIF_ENUM_N1)
+#define U2C_WFI_TDD (0x1 << DSP_CONTROL_CUIF_ENUM_N2)
+#define U2C_WFI_FDD (0x1 << DSP_CONTROL_CUIF_ENUM_N3)
+#define U2C_WFI_FDD_C2K (0x1 << DSP_CONTROL_CUIF_ENUM_N13)
+#define U2C_WFI_SPEECH (0x1 << DSP_CONTROL_CUIF_ENUM_N0)
+#define U2C_WFI_SS (0x1 << DSP_CONTROL_CUIF_ENUM_N6)
+#define M2C_WFI_SS (0x1 << 31)
+#define S2C_WFI_SS (0x1 << 30)
+
+
+typedef enum{
+ DSP_CTRL_INIT,
+ DSP_CTRL_ACTIVATE_NOTDONE,
+ DSP_CTRL_ACTIVATE_DONE,
+ DSP_CTRL_DEACTIVATE_NOTDONE,
+ DSP_CTRL_DEACTIVATE_DONE
+}DSP_CONTROL_STATUS;
+
+#else //defined(__MD97__) || defined(__MD97P__)
+/************************************************************__MD95__********************************/
+
+/***** Common Definition *****/
+#define RAKE_CONTROL_STATUS RAKE_BOOTDONECHECK_RETVALUE
+#define USIP_CONTROL_STATUS uSIP_BOOTDONECHECK_RETVALUE
+
+/***************************************************************/
+/********* Common Macro ***************************************/
+/***************************************************************/
+#define CORE_ID_INIT_VALUE 0xDC11DC11
+#define USIP_VIC_ENABLE_FILL 0x20170526
+#define USIP_VIC_ENABLE_CLEAR 0x0
+
+/***************************************************************/
+/********* Common Enum ***************************************/
+/***************************************************************/
+/* RAT user Enum */
+typedef enum{
+ DSP_CTRL_RAT_LTE,
+ DSP_CTRL_RAT_WCDMA,
+ DSP_CTRL_RAT_C2K,
+ DSP_CTRL_RAT_TDSCDMA,
+ DSP_CTRL_RAT_SPEECH,
+ DSP_CTRL_RAT_NUM
+} DSP_CTRL_RAT_ENUM;
+
+/* Core Enum */
+typedef enum{
+ DSP_CONTROL_USIP0_INNER,
+ DSP_CONTROL_USIP0_BRP,
+ DSP_CONTROL_USIP1_FEC,
+ DSP_CONTROL_USIP1_SPEECH,
+ DSP_CONTROL_RAKE,
+ DSP_CONTROL_CDIF_CORE_NUM
+} DSP_CDIF_CORE_ENUM;
+
+/* Idle Flag Enum */
+typedef enum{
+ DSP_CONTROL_IDLE,
+ DSP_CONTROL_BUSY
+} DSP_CONTROL_IDLE_FLAG_STATUS;
+
+#define DSP_THREAD_STATUS DSP_CONTROL_IDLE_FLAG_STATUS
+
+/* Sleep Flow Branch */
+typedef enum{
+ DSP_DORMANT_FLOW,
+ DSP_ABORT_FLOW,
+ DSP_WAKEUP_FLOW,
+ DSP_CTRL_FLOW_NUM
+} DSP_SLEEP_CTRL_FLOW_TYPE_BRANCH;
+
+typedef enum{
+ CMIFZI_EN,
+ CMIFZI_DIS
+} CMIFZI_CTRL;
+
+typedef enum{
+ DDL_WAY_IS_BY_CORE = 0x0A0A0A0A,
+ DDL_WAY_IS_BY_GDMA = 0x0B0B0B0B,
+ DDL_WAY_DEFAULT = 0x0C0C0C0C
+} DDL_WAY;
+
+typedef enum {
+ DDL_STATUS_INIT = 0x0A000000,
+ DDL_STATUS_ONGOING = 0x0B000000,
+ DDL_STATUS_DONE = 0x0C000000,
+ DDL_STATUS_GDMA_DONE=0x0D000000,
+ DDL_STATUS_RE_DDL =0x0E000000,
+ DDL_MODE_NOT_SUPPORT_LTE = 0x0AAA0000,
+ DDL_MODE_WAIT_RESPONSE_CLR_DDL_PROTECTION = 0x0BBB0000,
+ DDL_STATUS_DEFAULT = 0x0ABC0000
+}DDL_STATUS;
+
+typedef enum {
+ DDL_MODE_START=0x0,
+
+ //BRP
+ DDL_MODE_BRP_LTE=0x1, // should be the first
+ DDL_MODE_BRP_FDD=0x2,
+ DDL_MODE_BRP_END=0x3,
+
+ //FEC-TX
+ DDL_MODE_FEC_TX_C2K =0x4, // should be the first
+ DDL_MODE_FEC_TX_WCDMA=0x5,
+ DDL_MODE_FEC_TX_LTE =0x6,
+ DDL_MODE_FEC_TX_END =0x7,
+
+ //FEC-RX
+ DDL_MODE_FEC_RX_C2K =0x8, // should be the first
+ DDL_MODE_FEC_RX_WCDMA=0x9,
+ DDL_MODE_FEC_RX_END =0xA,
+
+ //SCQ16
+ DDL_MODE_SCQ16_LTE=0xB, // should be the first
+ DDL_MODE_SCQ16_FDD=0xC,
+ DDL_MODE_SCQ16_TDD=0xD,
+ DDL_MODE_SCQ16_C2K=0xE,
+ DDL_MODE_SCQ16_END=0xF,
+
+ //RAKE
+ DDL_MODE_RAKE_FDD=0x10, // should be the first
+ DDL_MODE_RAKE_C2K=0x11,
+ DDL_MODE_RAKE_LTE=0x12,
+ DDL_MODE_RAKE_END=0x13,
+
+ DDL_MODE_END=0x14,
+
+ DDL_MODE_NUM=0x15,
+ DDL_MODE_DEFAULT = 0x6214,
+ DDL_MODE_MAX = 0xFFFF,
+} DDL_MODE;
+
+#define DDL_MODE_BRP_START (DDL_MODE_BRP_LTE)
+#define DDL_MODE_FEC_TX_START (DDL_MODE_FEC_TX_C2K)
+#define DDL_MODE_FEC_RX_START (DDL_MODE_FEC_RX_C2K)
+#define DDL_MODE_SCQ16_START (DDL_MODE_SCQ16_LTE)
+#define DDL_MODE_RAKE_START (DDL_MODE_RAKE_FDD)
+
+/***************************************************************/
+/********* Enum for User Registration for Use Record of API ****/
+/***************************************************************/
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#define USIPAPI_USERNAME_INNER(name) name,
+#define USIPAPI_USERNAME_BRP(name) name,
+#define USIPAPI_USERNAME_FEC(name) name,
+#define USIPAPI_USERNAME_SPEECH(name) name,
+
+typedef enum{
+ #include "usip_inner_api_user_registation.h"
+ uSIP_INNER_API_USE_NUM
+} uSIP_API_USER_INNER;
+
+typedef enum{
+ #include "usip_brp_api_user_registation.h"
+ uSIP_BRP_API_USE_NUM
+} uSIP_API_USER_BRP;
+
+typedef enum{
+ #include "usip_fec_api_user_registation.h"
+ uSIP_FEC_API_USE_NUM
+} uSIP_API_USER_FEC;
+
+typedef enum{
+ #include "usip_speech_api_user_registation.h"
+ uSIP_SPEECH_API_USE_NUM
+} uSIP_API_USER_SPEECH;
+
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+
+/***************************************************************/
+/********* Enum for User Registration for Use Record of API ****/
+/***************************************************************/
+#undef RAKEAPI_USERNAME
+#define RAKEAPI_USERNAME(name) name,
+
+typedef enum{
+ #include "rake_api_user_registation.h"
+ RAKE_API_USE_NUM
+} RAKE_API_USER;
+
+#undef RAKEAPI_USERNAME
+
+/***************************************************************/
+/********* Extern logger Registration callback ****/
+/***************************************************************/
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#undef RAKEAPI_USERNAME
+#define USIPAPI_USERNAME_INNER(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define USIPAPI_USERNAME_BRP(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define USIPAPI_USERNAME_FEC(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define USIPAPI_USERNAME_SPEECH(func) extern void func(DSP_CDIF_CORE_ENUM);
+#define RAKEAPI_USERNAME(func) extern void func(DSP_CDIF_CORE_ENUM);
+
+#include "usip_inner_logger_registation.h"
+#include "usip_brp_logger_registation.h"
+#include "usip_fec_logger_registation.h"
+#include "usip_speech_logger_registation.h"
+#include "rake_logger_registation.h"
+
+/***************************************************************/
+/********* Enum for logger Registration callback ****/
+/***************************************************************/
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#undef RAKEAPI_USERNAME
+
+#define USIPAPI_USERNAME_INNER(func) USIP_DEACTIVATE_INNER_CB_##func,
+typedef enum{
+ #include "usip_inner_logger_registation.h"
+ USIP_INNER_DEACTIVATE_CB_SIZE
+} USIP_INNER_DEACTIVATE_CB_ENUM;
+
+#define USIPAPI_USERNAME_BRP(func) USIP_DEACTIVATE_BRP_CB_##func,
+typedef enum{
+ #include "usip_brp_logger_registation.h"
+ USIP_BRP_DEACTIVATE_CB_SIZE
+} USIP_BRP_DEACTIVATE_CB_ENUM;
+
+#define USIPAPI_USERNAME_FEC(func) USIP_DEACTIVATE_FEC_CB_##func,
+typedef enum{
+ #include "usip_fec_logger_registation.h"
+ USIP_FEC_DEACTIVATE_CB_SIZE
+} USIP_FEC_DEACTIVATE_CB_ENUM;
+
+#define USIPAPI_USERNAME_SPEECH(func) USIP_DEACTIVATE_SPEECH_CB_##func,
+typedef enum{
+ #include "usip_speech_logger_registation.h"
+ USIP_SPEECH_DEACTIVATE_CB_SIZE
+} USIP_SPEECH_DEACTIVATE_CB_ENUM;
+
+#define RAKEAPI_USERNAME(func) RAKE_DEACTIVATE_CB_##func,
+typedef enum{
+ #include "rake_logger_registation.h"
+ RAKE_DEACTIVATE_CB_SIZE
+} RAKE_DEACTIVATE_CB_ENUM;
+
+#undef USIPAPI_USERNAME_INNER
+#undef USIPAPI_USERNAME_BRP
+#undef USIPAPI_USERNAME_FEC
+#undef USIPAPI_USERNAME_SPEECH
+#undef RAKEAPI_USERNAME
+
+#endif //defined(__MD97__) || defined(__MD97P__)
+#endif /* _DSP_CONTROL_PUBLIC_H_ */
diff --git a/common/interface/service/dsp_control/dsp_firmware_registration.h b/common/interface/service/dsp_control/dsp_firmware_registration.h
new file mode 100644
index 0000000..49d276e
--- /dev/null
+++ b/common/interface/service/dsp_control/dsp_firmware_registration.h
@@ -0,0 +1,49 @@
+
+/*****************************************
+* Prototype
+* DSP_FW_REGISTER(firmware_name, located_thread)
+*
+* Parameter
+* firmware_name: please add DSP_FW_ as prefix.
+* located_thread: DSP_CTRL_USIP0_THREAD0, DSP_CTRL_USIP0_THREAD1, DSP_CTRL_USIP1_THREAD0, DSP_CTRL_USIP1_THREAD1, DSP_CTRL_RAKE, DSP_CTRL_SONIC
+* If a dsp firmware is located on two or more threads, please use "|" to connect them.
+*
+* Example
+* DSP_FW_REGISTER(DSP_FW_xxxxx, DSP_CTRL_USIP0_THREAD0|DSP_CTRL_USIP0_THREAD1) //There is no space between "located_thread" and "|".
+*
+* Limitation
+* One dsp firmware can only be used by one L1 module.
+*****************************************/
+DSP_FW_REGISTER(DSP_FW_SS_USIP, DSP_CTRL_USIP0_THREAD0|DSP_CTRL_USIP0_THREAD1|DSP_CTRL_USIP1_THREAD0)
+DSP_FW_REGISTER(DSP_FW_SS_RAKE, DSP_CTRL_RAKE)
+DSP_FW_REGISTER(DSP_FW_SS_SONIC, DSP_CTRL_SONIC)
+
+DSP_FW_REGISTER(DSP_FW_RAKE_FDD, DSP_CTRL_RAKE)
+DSP_FW_REGISTER(DSP_FW_RAKE_C2K_1XRTT, DSP_CTRL_RAKE)
+DSP_FW_REGISTER(DSP_FW_RAKE_C2K_EVDO, DSP_CTRL_RAKE)
+DSP_FW_REGISTER(DSP_FW_INNER_LTE, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_FDD, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_TDSCDMA, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_C2K, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_LTE_CM, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_LTE_POS, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_LTE_CSI, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_INNER_TDSCDMA_MEAS, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_GSM, DSP_CTRL_USIP0_THREAD0)
+DSP_FW_REGISTER(DSP_FW_BRP_FDD, DSP_CTRL_USIP0_THREAD1)
+DSP_FW_REGISTER(DSP_FW_BRP_LTE, DSP_CTRL_USIP0_THREAD1)
+DSP_FW_REGISTER(DSP_FW_BRP_LTE_NCM, DSP_CTRL_USIP0_THREAD1)
+DSP_FW_REGISTER(DSP_FW_BRP_LTE_POS, DSP_CTRL_USIP0_THREAD1)
+DSP_FW_REGISTER(DSP_FW_BRP_LTE_CSI, DSP_CTRL_USIP0_THREAD1)
+
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG0_FR1,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG1_FR1,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG2_FR1,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG0_FR2,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG1_FR2,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG2_FR2,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG0_NONFR,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG1_NONFR,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_SLM_TG2_NONFR,DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_NR_IQDUMP, DSP_CTRL_SONIC)
+DSP_FW_REGISTER(DSP_FW_SPEECH, DSP_CTRL_USIP1_THREAD0)
diff --git a/common/interface/service/dsp_control/dummy.h b/common/interface/service/dsp_control/dummy.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/common/interface/service/dsp_control/dummy.h
diff --git a/common/interface/service/dsp_control/rake_api_user_registation.h b/common/interface/service/dsp_control/rake_api_user_registation.h
new file mode 100644
index 0000000..0779839
--- /dev/null
+++ b/common/interface/service/dsp_control/rake_api_user_registation.h
@@ -0,0 +1,15 @@
+#ifndef RAKE_API_USER_REGISTRATION_H
+#define RAKE_API_USER_REGISTRATION_H
+
+/*****************************************
+* Prototype
+* RAKEAPI_USERNAME(DSP_CTRL_RAKE_XXXXX)
+*****************************************/
+RAKEAPI_USERNAME(RAKE_SS1_INIT) // This should be removed after el1d modify the code
+RAKEAPI_USERNAME(DSP_CTRL_RAKE_SS1_INIT)
+RAKEAPI_USERNAME(DSP_CTRL_RAKE_SS1_LOADER)
+RAKEAPI_USERNAME(DSP_CTRL_RAKE_FDD)
+RAKEAPI_USERNAME(DSP_CTRL_RAKE_C2K_1XRTT)
+RAKEAPI_USERNAME(DSP_CTRL_RAKE_C2K_EVDO)
+RAKEAPI_USERNAME(DSP_CTRL_RAKE_LTE)
+#endif /* RAKE_API_USER_REGISTRATION_H */
diff --git a/common/interface/service/dsp_control/rake_ddl_idle_check.h b/common/interface/service/dsp_control/rake_ddl_idle_check.h
new file mode 100644
index 0000000..26898bc
--- /dev/null
+++ b/common/interface/service/dsp_control/rake_ddl_idle_check.h
@@ -0,0 +1,15 @@
+#ifndef _RAKE_DDL_IDLE_CHECK_H_
+#define _RAKE_DDL_IDLE_CHECK_H_
+
+/*****************************************
+* Prototype
+* DDL_IDLE_CHECK(DSP_CTRL_RAKE_XXXXX)
+*****************************************/
+
+/* Usage notice
+ * 1. In rake_api_user_registation.h, users registers the DDL-users
+ * 2. In rake_ddl_idle_check.h, it lists idle-check-list. The users listed shall be in idle.
+ */
+DDL_IDLE_CHECK(DSP_CTRL_RAKE_LTE)
+
+#endif //_RAKE_DDL_IDLE_CHECK_H_
diff --git a/common/interface/service/dsp_control/rake_logger_registation.h b/common/interface/service/dsp_control/rake_logger_registation.h
new file mode 100644
index 0000000..e607ab0
--- /dev/null
+++ b/common/interface/service/dsp_control/rake_logger_registation.h
@@ -0,0 +1,9 @@
+/*****************************************
+* Prototype
+* RAKEAPI_USERNAME(DSP_CTRL_RAKE_XXXXX)
+*****************************************/
+
+#if !defined(__MAUI_BASIC__)
+RAKEAPI_USERNAME(ulsp_check_dsp_buffer_before_dormant)
+#endif
+
diff --git a/common/interface/service/dsp_control/sonic_control_public.h b/common/interface/service/dsp_control/sonic_control_public.h
new file mode 100644
index 0000000..50b93bf
--- /dev/null
+++ b/common/interface/service/dsp_control/sonic_control_public.h
@@ -0,0 +1,21 @@
+#ifndef _SONIC_CONTROL_PUBLIC_H_
+#define _SONIC_CONTROL_PUBLIC_H_
+
+
+/****************************************/
+/* Sleep Flow use */
+/****************************************/
+#define SONIC_BOOT_DONE_PATTERN 0x97FB97FB
+#define SONIC_DORMANT_DONE_PATTERN 0x97BD97BD
+#define SONIC_DORMANT_FLOW_PATTERN 0xFB97BD97 // boot done to backup done
+#define SONIC_ABORT_FLOW_PATTERN 0xBD97FB97 // Abort to boot done
+#define SONIC_WAKEUP_FLOW_PATTERN 0x2B97FB97 // 2nd boot to boot done
+
+#define SONIC_FIRST_BOOT_PROGRESS_PREFIX 0xFB000000 // first boot
+#define SONIC_DORMANT_PROGRESS_PREFIX 0xBD000000 // dormant backup
+#define SONIC_ABORT_PROGRESS_PREFIX 0xAB000000 // abort
+#define SONIC_WAKEUP_PROGRESS_PREFIX 0x2B000000 // second boot
+
+
+
+#endif /*_SONIC_CONTROL_PUBLIC_H_*/
diff --git a/common/interface/service/dsp_control/sonic_logger_registation.h b/common/interface/service/dsp_control/sonic_logger_registation.h
new file mode 100644
index 0000000..af96b58
--- /dev/null
+++ b/common/interface/service/dsp_control/sonic_logger_registation.h
@@ -0,0 +1,8 @@
+/**********************************************
+* Prototype
+* SONICAPI_USERNAME(DSP_CTRL_SONIC_XXXXX)
+**********************************************/
+
+#if !defined(__MAUI_BASIC__)
+
+#endif
diff --git a/common/interface/service/dsp_control/usip_brp_api_user_registation.h b/common/interface/service/dsp_control/usip_brp_api_user_registation.h
new file mode 100644
index 0000000..a56d7f2
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_brp_api_user_registation.h
@@ -0,0 +1,17 @@
+#ifndef USIP_BRP_API_USER_REGISTRATION_H
+#define USIP_BRP_API_USER_REGISTRATION_H
+
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_XXXXX)
+*****************************************/
+USIPAPI_USERNAME_BRP(uSIP_BRP_SS1_INIT) // This should be removed after el1d modify the code
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_SS1_INIT)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_SS1_LOADER)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_FDD)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_LTE)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_LTE_NCM)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_LTE_POS)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_LTE_CSI)
+USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_TDSCDMA)
+#endif /* USIP_BRP_API_USER_REGISTRATION_H */
diff --git a/common/interface/service/dsp_control/usip_brp_ddl_idle_check.h b/common/interface/service/dsp_control/usip_brp_ddl_idle_check.h
new file mode 100644
index 0000000..a5702df
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_brp_ddl_idle_check.h
@@ -0,0 +1,17 @@
+#ifndef _USIP_BRP_DDL_IDLE_CHECK_H_
+#define _USIP_BRP_DDL_IDLE_CHECK_H_
+
+/*****************************************
+* Prototype
+* DDL_IDLE_CHECK(DSP_CTRL_USIP_BRP_XXXXX)
+*****************************************/
+
+/* Usage notice
+ * 1. In usip_brp_api_user_registation.h, users registers the DDL-users
+ * 2. In usip_brp_ddl_idle_check.h, it lists idle-check-list. The users listed shall be in idle.
+ */
+
+DDL_IDLE_CHECK(DSP_CTRL_USIP_BRP_FDD)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_BRP_LTE)
+
+#endif // _USIP_BRP_DDL_IDLE_CHECK_H_
diff --git a/common/interface/service/dsp_control/usip_brp_logger_registation.h b/common/interface/service/dsp_control/usip_brp_logger_registation.h
new file mode 100644
index 0000000..5ee7ba9
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_brp_logger_registation.h
@@ -0,0 +1,8 @@
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_BRP(DSP_CTRL_USIP_BRP_XXXXX)
+*****************************************/
+
+#if !defined(__MAUI_BASIC__)
+USIPAPI_USERNAME_BRP(ulsp_check_dsp_buffer_before_dormant)
+#endif
diff --git a/common/interface/service/dsp_control/usip_fec_api_user_registation.h b/common/interface/service/dsp_control/usip_fec_api_user_registation.h
new file mode 100644
index 0000000..adf9409
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_fec_api_user_registation.h
@@ -0,0 +1,23 @@
+#ifndef USIP_FEC_API_USER_REGISTRATION_H
+#define USIP_FEC_API_USER_REGISTRATION_H
+
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_XXXXX)
+*****************************************/
+USIPAPI_USERNAME_FEC(uSIP_FEC_SS1_INIT) // This should be removed after el1d modify the code
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_SS1_INIT)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_SS1_LOADER)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_FDD)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_LTE)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_LTE_TX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_LTE_RX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_FDD_TX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_FDD_RX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_C2K_1XRTT_RX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_C2K_1XRTT_TX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_C2K_EVDO_RX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_C2K_EVDO_TX)
+USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_LTE_TX_CORE0)
+
+#endif /* USIP_FEC_API_USER_REGISTRATION_H */
diff --git a/common/interface/service/dsp_control/usip_fec_logger_registation.h b/common/interface/service/dsp_control/usip_fec_logger_registation.h
new file mode 100644
index 0000000..c8ba10b
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_fec_logger_registation.h
@@ -0,0 +1,8 @@
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_FEC(DSP_CTRL_USIP_FEC_XXXXX)
+*****************************************/
+
+#if !defined(__MAUI_BASIC__)
+USIPAPI_USERNAME_FEC(ulsp_check_dsp_buffer_before_dormant)
+#endif
diff --git a/common/interface/service/dsp_control/usip_fec_rx_ddl_idle_check.h b/common/interface/service/dsp_control/usip_fec_rx_ddl_idle_check.h
new file mode 100644
index 0000000..2ff2798
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_fec_rx_ddl_idle_check.h
@@ -0,0 +1,17 @@
+#ifndef _USIP_FEC_RX_DDL_IDLE_CHECK_H_
+#define _USIP_FEC_RX_DDL_IDLE_CHECK_H_
+
+/*****************************************
+* Prototype
+* DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_XXXXX)
+*****************************************/
+
+/* Usage notice
+ * 1. In usip_fec_api_user_registation.h, users registers the DDL-users
+ * 2. In usip_fec_rx_ddl_idle_check.h, it lists idle-check-list. The users listed shall be in idle.
+ */
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_FDD_RX)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_C2K_1XRTT_RX)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_C2K_EVDO_RX)
+
+#endif //_USIP_FEC_RX_DDL_IDLE_CHECK_H_
diff --git a/common/interface/service/dsp_control/usip_fec_tx_ddl_idle_check.h b/common/interface/service/dsp_control/usip_fec_tx_ddl_idle_check.h
new file mode 100644
index 0000000..247d9d6
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_fec_tx_ddl_idle_check.h
@@ -0,0 +1,18 @@
+#ifndef _USIP_FEC_TX_DDL_IDLE_CHECK_H_
+#define _USIP_FEC_TX_DDL_IDLE_CHECK_H_
+
+/*****************************************
+* Prototype
+* DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_XXXXX)
+*****************************************/
+
+/* Usage notice
+ * 1. In usip_fec_api_user_registation.h, users registers the DDL-users
+ * 2. In usip_fec_tx_ddl_idle_check.h, it lists idle-check-list. The users listed shall be in idle.
+ */
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_LTE_TX)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_FDD_TX)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_C2K_1XRTT_TX)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_FEC_C2K_EVDO_TX)
+
+#endif //_USIP_FEC_TX_DDL_IDLE_CHECK_H_
diff --git a/common/interface/service/dsp_control/usip_inner_api_user_registation.h b/common/interface/service/dsp_control/usip_inner_api_user_registation.h
new file mode 100644
index 0000000..12bbb57
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_inner_api_user_registation.h
@@ -0,0 +1,26 @@
+#ifndef USIP_INNER_API_USER_REGISTRATION_H
+#define USIP_INNER_API_USER_REGISTRATION_H
+
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_XXXXX)
+*****************************************/
+
+/* Usage notice
+ * 1. In usip_inner_api_user_registeration.h, users registers the DDL-users
+ * 2. In usip_inner_ddl_idle_check.h, it lists idle-check-list. The users listed shall be in idle.
+ */
+
+USIPAPI_USERNAME_INNER(uSIP_INNER_SS1_INIT) // This should be removed after el1d modify the code
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_SS1_INIT)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_SS1_LOADER)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_LTE)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_WCDMA)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_TDSCDMA)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_C2K)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_LTE_CM) // the ID is just occupied due to necessity of DSP cosim verification. Therefore, L1 doesn't have to take care of it actually.
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_LTE_POS) // the ID is just occupied due to necessity of DSP cosim verification. Therefore, L1 doesn't have to take care of it actually.
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_LTE_CSI) // the ID is just occupied due to necessity of DSP cosim verification. Therefore, L1 doesn't have to take care of it actually.
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_TDSCDMA_MEAS)
+USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_GSM)
+#endif /* USIP_INNER_API_USER_REGISTRATION_H */
diff --git a/common/interface/service/dsp_control/usip_inner_ddl_idle_check.h b/common/interface/service/dsp_control/usip_inner_ddl_idle_check.h
new file mode 100644
index 0000000..42c14ef
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_inner_ddl_idle_check.h
@@ -0,0 +1,21 @@
+#ifndef _USIP_INNER_DDL_IDLE_CHECK_H_
+#define _USIP_INNER_DDL_IDLE_CHECK_H_
+
+/*****************************************
+* Prototype
+* DDL_IDLE_CHECK(DSP_CTRL_USIP_INNER_XXXXX)
+*****************************************/
+
+/* Usage notice
+ * 1. In usip_inner_api_user_registation.h, users registers the DDL-users
+ * 2. In usip_inner_ddl_idle_check.h, it lists idle-check-list. The users listed shall be in idle.
+ */
+
+
+// Leo: before running DDL, LWTC 4 users must be in idle
+DDL_IDLE_CHECK(DSP_CTRL_USIP_INNER_LTE)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_INNER_WCDMA)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_INNER_TDSCDMA)
+DDL_IDLE_CHECK(DSP_CTRL_USIP_INNER_C2K)
+
+#endif // _USIP_INNER_DDL_IDLE_CHECK_H_
diff --git a/common/interface/service/dsp_control/usip_inner_logger_registation.h b/common/interface/service/dsp_control/usip_inner_logger_registation.h
new file mode 100644
index 0000000..24f0392
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_inner_logger_registation.h
@@ -0,0 +1,8 @@
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_INNER(DSP_CTRL_USIP_INNER_XXXXX)
+*****************************************/
+
+#if !defined(__MAUI_BASIC__)
+USIPAPI_USERNAME_INNER(ulsp_check_dsp_buffer_before_dormant)
+#endif
diff --git a/common/interface/service/dsp_control/usip_speech_api_user_registation.h b/common/interface/service/dsp_control/usip_speech_api_user_registation.h
new file mode 100644
index 0000000..cbc0349
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_speech_api_user_registation.h
@@ -0,0 +1,11 @@
+#ifndef USIP_SPEECH_API_USER_REGISTRATION_H
+#define USIP_SPEECH_API_USER_REGISTRATION_H
+
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_SPEECH(DSP_CTRL_USIP_SPEECH_XXXXX)
+*****************************************/
+USIPAPI_USERNAME_SPEECH(uSIP_SPEECH_SS1_INIT) // This should be removed after el1d modify the code
+USIPAPI_USERNAME_SPEECH(DSP_CTRL_USIP_SPEECH_SS1_INIT)
+USIPAPI_USERNAME_SPEECH(DSP_CTRL_USIP_SPEECH)
+#endif /* USIP_SPEECH_API_USER_REGISTRATION_H */
diff --git a/common/interface/service/dsp_control/usip_speech_logger_registation.h b/common/interface/service/dsp_control/usip_speech_logger_registation.h
new file mode 100644
index 0000000..2269f60
--- /dev/null
+++ b/common/interface/service/dsp_control/usip_speech_logger_registation.h
@@ -0,0 +1,8 @@
+/*****************************************
+* Prototype
+* USIPAPI_USERNAME_SPEECH(DSP_CTRL_USIP_SPEECH_XXXXX)
+*****************************************/
+
+#if !defined(__MAUI_BASIC__)
+USIPAPI_USERNAME_SPEECH(ulsp_check_dsp_buffer_before_dormant)
+#endif