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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/auxadc/inc/adc_hw.h b/mcu/driver/devdrv/auxadc/inc/adc_hw.h
new file mode 100644
index 0000000..7e4cdd8
--- /dev/null
+++ b/mcu/driver/devdrv/auxadc/inc/adc_hw.h
@@ -0,0 +1,416 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for adc driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADC_HW_H
+#define _ADC_HW_H
+#include "drv_features_adc.h"
+#include "drvpdn.h"
+
+#if defined(DRV_ADC_6236_SERIES)
+/*
+MT6236 BASE=0x801c_0000
+Check bit of ADC (1b) *(BASE+0x0020)[13]=[333]
+ADC_B (6b) *(BASE+0x0020)[12:7]=[332:327]
+ADC_A (7b) *(BASE+0x0020)[6:0]=[326:320]
+*/
+#define EFUSE_ADC_BASE 0x801c0020
+#define EFUSE_ADC_A 0x801c0020
+#define EFUSE_ADC_B 0x801c0020
+#define EFUSE_ADC_ENABLE 0x2000
+#define EFUSE_ADC_A_MASK 0x7F
+#define EFUSE_ADC_B_MASK 0x1F80
+#define EFUSE_ADC_A_SHIFT 0
+#define EFUSE_ADC_B_SHIFT 7
+
+#elif defined(DRV_ADC_6252_SERIES)
+/*
+MT6252 BASE=0x8000_0000
+Check bit of ADC (1b), *(BASE+0x0020)[13]=[333]
+ADC_B (6b), *(BASE+0x0020)[12:7]=[332:327]
+ADC_A (7b), *(BASE+0x0020)[6:0]=[326:320]
+*/
+#define EFUSE_ADC_BASE 0x80000020
+#define EFUSE_ADC_A 0x80000020
+#define EFUSE_ADC_B 0x80000020
+#define EFUSE_ADC_ENABLE 0x2000
+#define EFUSE_ADC_A_MASK 0x7F
+#define EFUSE_ADC_B_MASK 0x1F80
+#define EFUSE_ADC_A_SHIFT 0
+#define EFUSE_ADC_B_SHIFT 7
+
+#elif defined(DRV_ADC_6251_SERIES)
+
+#define EFUSE_ADC_BASE 0x80000100
+#define EFUSE_ADC_A 0x80000100
+#define EFUSE_ADC_B 0x80000100
+#define EFUSE_ADC_ENABLE 0x0002
+#define EFUSE_ADC_A_MASK 0x7FC00
+#define EFUSE_ADC_B_MASK 0x3FC
+#define EFUSE_ADC_A_SHIFT 10
+#define EFUSE_ADC_B_SHIFT 2
+
+#elif defined(DRV_ADC_6256_SERIES)
+
+#define EFUSE_ADC_BASE 0x80000100
+#define EFUSE_ADC_A 0x80000100
+#define EFUSE_ADC_B 0x80000100
+#define EFUSE_ADC_ENABLE 0x0002
+#define EFUSE_ADC_A_MASK 0x7FC00
+#define EFUSE_ADC_B_MASK 0x3FC
+#define EFUSE_ADC_A_SHIFT 10
+#define EFUSE_ADC_B_SHIFT 2
+
+#elif defined(DRV_ADC_6575_SERIES)
+
+#define EFUSE_ADC_BASE 0xC1019040
+#define EFUSE_ADC_ENABLE 0x0
+#define EFUSE_O_VBG 0xC1019040
+#define EFUSE_O_VBG_MASK 0x1FF00
+#define EFUSE_O_VBG_SHIFT 0x8
+#define EFUSE_ADC_OE 0xC1019044
+#define EFUSE_ADC_OE_MASK 0xFF
+#define EFUSE_ADC_OE_SHIFT 0
+#define EFUSE_ADC_GE 0xC1019048
+#define EFUSE_ADC_GE_MASK 0xFF
+#define EFUSE_ADC_GE_SHIFT 0
+
+#define TS_CON1 0xC0007804
+#define TS_CON2 0xC0007808
+
+#elif defined(DRV_ADC_6250_SERIES) // 10 bits ADC
+
+#define EFUSE_ADC_BASE 0xA01C0200
+#define EFUSE_ADC_A 0xA01C0200
+#define EFUSE_ADC_B 0xA01C0200
+#define EFUSE_ADC_ENABLE 0x0002
+#define EFUSE_ADC_A_MASK 0x1FC00 // 7 bits
+#define EFUSE_ADC_B_MASK 0xFC // 6 bits
+#define EFUSE_ADC_A_SHIFT 10
+#define EFUSE_ADC_B_SHIFT 2
+
+
+#else
+/*
+1. Check bit of ADC (1b), *(0x80000020)[18]=[210]
+2. ADC_B (6b), *(0x80000020)[17:12]=[209:204]
+3. ADC_A (7b), *(0x80000020)[11:5]=[203:197]
+*/
+#define EFUSE_ADC_BASE 0x80000020
+#define EFUSE_ADC_A 0x80000020
+#define EFUSE_ADC_B 0x80000020
+#define EFUSE_ADC_ENABLE 0x40000
+#define EFUSE_ADC_A_MASK 0xFE0
+#define EFUSE_ADC_B_MASK 0x3F000
+#define EFUSE_ADC_A_SHIFT 5
+#define EFUSE_ADC_B_SHIFT 12
+
+#endif
+
+#if defined(DRV_ADC_LIMIT_REG) || defined(FPGA)
+#if !defined(DRV_ADC_OFF)
+ /*******************
+ * GPADC Registers *
+ *******************/
+ #define AUXADC_DATA (AUXADC_base+0x0000) /* Sampled data */
+ #define AUXADC_CTRL (AUXADC_base+0x0004) /* Control of A/D Converter */
+ #define AUXADC_STAT (AUXADC_base+0x0008) /* A/D Status..reg=0,if write AUXADC_CTRL reg*/
+ #define AUXADC_CTRL2 (AUXADC_base+0x000c) /* Special Control of A/D Converter */
+
+ #define AUXADC_STAT_RDY 0x0001 /*ADC ready*/
+
+ #define AUXADC_CTRL2_CALI 0x0001 /*ADC Calibration*/
+ #define AUXADC_CTRL2_MON 0x0020 /*DACMON*/
+ #define AUXADC_CTRL2_BYP 0x0040 /*DACBYP*/
+#endif // #if !defined(DRV_ADC_OFF)
+
+ /*ADC pin selection, ADC phy. channel*/
+
+ #define ADC_MAX_CHANNEL 5
+ #define ADC_ERR_CHANNEL_NO 50
+#endif /*(DRV_ADC_LIMIT_REG,FPGA)*/
+/*************************************************************************/
+#if defined(DRV_ADC_BASIC_REG)
+#if !defined(DRV_ADC_OFF)
+ #define AUXADC_SYNC (AUXADC_base+0x0000)
+ #define AUXADC_IMM (AUXADC_base+0x0004)
+#if defined(DRV_ADC_6575_SERIES)
+ #define AUXADC_CON1_SET (AUXADC_base+0x0008)
+ #define AUXADC_CON1_CLR (AUXADC_base+0x000C)
+ #define AUXADC_SYN (AUXADC_base+0x0010)
+ #define AUXADC_CON (AUXADC_base+0x0014)
+ #define AUXADC_DAT(_line) (AUXADC_base+0x0018+(4*_line))
+#endif
+
+#if defined(DRV_ADC_6256_SERIES)
+ #define AUX_CON2 (PLL_base+0x1708)
+#else
+ #define AUX_CON2 (ABBSYS_base+0x8708)
+#endif
+
+#if defined(DRV_ADC_6250_SERIES)
+
+ #define ABBA_WR_PATH0 (ABBSYS_base + 0x0)
+ #define ABB_WR_PATH0 (ABB_D_base + 0x0010)
+ #define ABB_AUX_CON0 (ABB_D_base + 0x0028)
+ #define ABB_RSV_CON1 (ABB_D_base + 0x0004)
+ #define AUXADC_TS_CON (AUXADC_base + 0x0058)
+
+
+ #define ABBA_AUX_PWDB 0x0100
+ #define F26M_CLK_EN 0x8000
+ #define AUX_PWDB 0x0100
+ #define AUX_FIFO_CLK_EN 0x8000
+ #define AUX_FIFO_EN 0x0080
+ #define AUXADC_FSM_CTRL 0x0040
+ #define AUXADC_26M_CLK_CTRL 0x0004
+ #define AUXADC_TP_SPL 0x0001
+#endif
+
+ /*AUXADC_SYNC*/
+ #define AUXADC_SYNC_CHAN(_line) (0x0001<<_line) /*Time event 1*/
+
+ /*AUXADC_IMM*/
+ #define AUXADC_IMM_CHAN(_line) (0x0001<<_line)
+
+ /*AUXADC_SYN*/
+ #define AUXADC_SYN_BIT (0x0001) /*Time event 0*/
+
+ /*AUXADC_CON*/
+ #define AUXADC_CON_RUN (0x0001)
+#ifndef DRV_ADC_NO_TEST_DACMON
+ #define AUXADC_CON_CALI_MASK (0x007c)
+ #define AUXADC_CON_TESTDACMON (0x0080)
+#endif // #ifndef DRV_ADC_NO_TEST_DACMON
+#if defined(DRV_ADC_SW_RESET)
+ #define AUXADC_CON_SW_RESET (0x0080)
+#endif // #if defined(DRV_ADC_SW_RESET)
+ #define AUXADC_CON_AUTOCLR0 (0x0100)
+ #define AUXADC_CON_AUTOCLR1 (0x0200)
+ #define AUXADC_CON_PUWAIT_EN (0x0800)
+ #define AUXADC_CON_AUTOSET (0x8000)
+#endif // #if !defined(DRV_ADC_OFF)
+
+
+ #define ADC_ERR_CHANNEL_NO 50
+#endif /*(MT6205B,MT6218)*/
+
+#if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
+#if !defined(DRV_ADC_OFF)
+ #if defined(DRV_ADC_TDMA_EVENT_REG_POS1)
+ #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1c0)
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1c4)
+ #elif defined(DRV_ADC_TDMA_EVENT_REG_POS2)
+ #define AUXADC_TDMA_EVENT0 (TDMA_base+0x400)
+
+ #if defined(MT6229_S00)
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x400)/*HW bug*/
+ #else
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x404)/**/
+ #endif
+
+ #else
+ #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1b0)
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1b4)
+ #endif
+
+ #if defined(DRV_ADC_TDMA_EN_REG_POS1)
+ #define AUXADC_TDMA_EN (TDMA_base+0x16C)
+ #else
+ #define AUXADC_TDMA_EN (TDMA_base+0x164)
+ #endif
+ /*AUXADC_TDMA_EN*/
+ #define AUXADC_TDMA_EN_EVT0 (0x0001)
+ #define AUXADC_TDMA_EN_EVT1 (0x0002)
+#endif // #if !defined(DRV_ADC_OFF)
+#endif // #if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
+
+
+#if defined(__OLD_PDN_ARCH__)
+#if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON0)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON0_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON0)
+ #define ADC_CG_PDN_CON_BIT (CG_CON0_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+
+#elif defined(ADC_CG_PDN_CON1) // #if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON1)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON1_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON1)
+ #define ADC_CG_PDN_CON_BIT (CG_CON1_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+#elif defined(ADC_CG_PDN_CON3) // #if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON3)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON3_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON3)
+ #define ADC_CG_PDN_CON_BIT (CG_CON3_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+#else // #if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON2)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON2_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON2)
+ #define ADC_CG_PDN_CON_BIT (CG_CON2_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+#endif // #if defined(ADC_CG_PDN_CON0)
+#endif // #if defined(__OLD_PDN_ARCH__)
+
+
+#if defined(DRV_ADC_NOT_EXIST)
+ #define ADC_ERR_CHANNEL_NO 50
+#endif // #if defined(DRV_ADC_NOT_EXIST)
+
+#if !defined(DRV_ADC_OFF)
+#if !defined(ADC_MAX_CHANNEL)
+ #define ADC_MAX_CHANNEL 1
+ #define ADC_ERR_CHANNEL_NO 50
+#endif // #if defined(DRV_ADC_NOT_EXIST)
+#endif // #if !defined(DRV_ADC_OFF)
+
+#endif /*_ADC_HW_H*/
+
diff --git a/mcu/driver/devdrv/auxadc/inc/adc_sw.h b/mcu/driver/devdrv/auxadc/inc/adc_sw.h
new file mode 100644
index 0000000..0a59d17
--- /dev/null
+++ b/mcu/driver/devdrv/auxadc/inc/adc_sw.h
@@ -0,0 +1,245 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for adc driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADC_SW_H
+#define _ADC_SW_H
+
+#include "drv_features_adc.h"
+#include "adc_hw.h"
+#include "adc_cali.h"
+
+typedef struct {
+ double ADC_ISENSE_RESISTANCE_FACTOR; /*1/0.4*/
+ ADC_CALIDATA adc_cali_param; /*ratio = adc_volt_factor/100*/
+ kal_uint16 adc_volt_factor[ADC_MAX_CHANNEL];
+}adc_customized_struct;
+
+typedef struct {
+ kal_int32 TEMPV2;
+ kal_int32 TEMPA12;
+ kal_int32 TEMPA23;
+ kal_int32 TEMPM12;
+ kal_int32 TEMPM23;
+ kal_int32 TEMPSCALE;
+} VolToTempStruct;
+
+typedef enum {
+ vbat_adc_channel=0,
+ visense_adc_channel,
+ vbattmp_adc_channel,
+ battype_adc_channel,
+ vcharger_adc_channel,
+ pcbtmp_adc_channel,
+ aux_adc_channel,
+ chr_usb_adc_channel,
+ otg_vbus_adc_channel,
+ rftmp_adc_channel
+} adc_channel_type;
+
+
+/*************************************************************************/
+#if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
+// Define to perform ADC race condition check when processing critical data process
+#define ADC_RACE_CONDITION_CHECK
+// Define to remove IRQ mask/restore for ADC measurement
+#define ADC_REMOVE_IRQMASK
+#endif // #if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
+
+#if defined(ADC_RACE_CONDITION_CHECK)
+extern kal_bool gADC_RC_Check;
+// MoDIS parser skip start
+// The following two APIs are private APIs, NOT exported as public APIs
+extern void ADCRCCheckAndLock(void);
+extern void ADCRCRelease(void);
+// MoDIS parser skip end
+#endif // #if defined(ADC_RACE_CONDITION_CHECK)
+
+#if defined(ADC_REMOVE_IRQMASK)
+#define ADCSAVEANDSETIRQMASK(mask) {}
+#define ADCRESTOREIRQMASK(mask) {}
+#else // #if defined(ADC_REMOVE_IRQMASK)
+#define ADCSAVEANDSETIRQMASK(mask) {mask = SaveAndSetIRQMask();}
+#define ADCRESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#endif // #if defined(ADC_REMOVE_IRQMASK)
+
+extern void dbg_print(char *fmt,...);
+
+/*************************************************************************/
+// MoDIS parser skip start
+// The following APIs are private APIs
+extern kal_uint16 ADC_GetData(kal_uint8 sel);
+// adc.c
+extern kal_int32 adc_measureVoltage(kal_uint8 chann, double *adc_value);
+extern void adc_read_calibration_data(void);
+extern kal_uint16 ADC_IMM_Data(kal_uint16 channel);
+extern kal_uint16 ADC_SYNC_Data(kal_uint16 channel);
+extern void ADC_Init(void);
+extern void adc_pwrdown_enable(void);
+extern void adc_pwrdown_disable(void);
+extern kal_uint32 ADC_GetData2Meta(kal_uint8 sel, kal_uint16 meacount);
+extern kal_uint32 ADC_GetMeaData(kal_uint8 sel, kal_uint16 meacount);
+extern void ADC_IMM_Data_on_Booting(kal_uint32 channel, kal_uint32 counts, kal_uint16 * data);
+extern kal_int16 ADC_GetImmTemp(kal_uint8 chann);
+extern kal_int16 ADC_GetPhysicalChannel(kal_uint16 adcname);
+
+// MoDIS parser skip end
+
+#if !defined(DRV_ADC_OFF)
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
+#define DRV_ADC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_ADC_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_ADC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_ADC_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_ADC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_ADC_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_ADC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_ADC_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_ADC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_ADC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_ADC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_ADC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_ADC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_ADC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_ADC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_ADC_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_ADC_Reg(addr) DRV_Reg(addr)
+#define DRV_ADC_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_ADC_Reg32(addr) DRV_Reg32(addr)
+#define DRV_ADC_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_ADC_Reg8(addr) DRV_Reg8(addr)
+#define DRV_ADC_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_ADC_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_ADC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_ADC_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_ADC_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_ADC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_ADC_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_ADC_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_ADC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
+
+#else //!defined(DRV_ADC_OFF)
+
+#define DRV_ADC_WriteReg(addr,data)
+#define DRV_ADC_Reg(addr) drv_dummy_return()
+#define DRV_ADC_WriteReg32(addr,data)
+#define DRV_ADC_Reg32(addr) drv_dummy_return()
+#define DRV_ADC_WriteReg8(addr,data)
+#define DRV_ADC_Reg8(addr) drv_dummy_return()
+#define DRV_ADC_ClearBits(addr,data)
+#define DRV_ADC_SetBits(addr,data)
+#define DRV_ADC_SetData(addr, bitmask, value)
+#define DRV_ADC_ClearBits32(addr,data)
+#define DRV_ADC_SetBits32(addr,data)
+#define DRV_ADC_SetData32(addr, bitmask, value)
+#define DRV_ADC_ClearBits8(addr,data)
+#define DRV_ADC_SetBits8(addr,data)
+#define DRV_ADC_SetData8(addr, bitmask, value)
+
+#endif //!defined(DRV_ADC_OFF)
+
+#endif /*_ADC_SW_H*/
+
diff --git a/mcu/driver/devdrv/auxadc/src/adc.c b/mcu/driver/devdrv/auxadc/src/adc.c
new file mode 100644
index 0000000..e6eb48d
--- /dev/null
+++ b/mcu/driver/devdrv/auxadc/src/adc.c
@@ -0,0 +1,1025 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the auxiliary ADC driver and adaption layer.
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#include "drv_features.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+#include "adc_hw.h"
+#include "adc_sw.h"
+#include "kal_public_api.h"
+#include "syscomp_config.h"
+#include "dcl.h"
+
+// For RHR ADD
+#include "adc_channel.h"
+#include "init.h"
+
+#include "nvram_struct.h"
+#include "nvram_enums.h"
+// #include "nvram_data_items.h" //violate MSBB rule, also seems to be useless
+#include "nvram_interface.h"
+#include "adc_nvram_def.h"
+
+#if !defined(DRV_ADC_OFF)
+#include "cust_temp_det_ntc_cfg.h"
+
+extern kal_bool adc_sync_mode_on;
+extern kal_uint16 adc_imm_mode_cnt;
+extern kal_uint32 adc_sche_rw_status;
+
+#define BASE_ADDR_AUXADC (0xB6F2F000)
+
+#define AUXADC_CON0 (BASE_ADDR_AUXADC + 0x000)
+#define AUXADC_CON1 (BASE_ADDR_AUXADC + 0x004)
+#define AUXADC_CON1_SET (BASE_ADDR_AUXADC + 0x008)
+#define AUXADC_CON1_CLR (BASE_ADDR_AUXADC + 0x00C)
+#define AUXADC_CON2 (BASE_ADDR_AUXADC + 0x010)
+
+#define AUXADC_DAT(n) (BASE_ADDR_AUXADC + 0x014 + (n*4))
+
+#define AUXADC_DAT0 (BASE_ADDR_AUXADC + 0x014)
+#define AUXADC_DAT1 (BASE_ADDR_AUXADC + 0x018)
+#define AUXADC_DAT2 (BASE_ADDR_AUXADC + 0x01C)
+#define AUXADC_DAT3 (BASE_ADDR_AUXADC + 0x020)
+#define AUXADC_DAT4 (BASE_ADDR_AUXADC + 0x024)
+#define AUXADC_DAT5 (BASE_ADDR_AUXADC + 0x028)
+#define AUXADC_DET_VOLT (BASE_ADDR_AUXADC + 0x084)
+#define AUXADC_DET_SEL (BASE_ADDR_AUXADC + 0x088)
+#define AUXADC_DET_PERIOD (BASE_ADDR_AUXADC + 0x08C)
+#define AUXADC_DET_DEBT (BASE_ADDR_AUXADC + 0x090)
+#define AUXADC_MISC (BASE_ADDR_AUXADC + 0x094)
+#define AUXADC_SAMPLE_LIST (BASE_ADDR_AUXADC + 0x09C)
+#define AUXADC_TST (BASE_ADDR_AUXADC + 0x0A4)
+#define AUXADC_SPL_EN (BASE_ADDR_AUXADC + 0x0B0)
+#define AUXADC_SPL_CFG0 (BASE_ADDR_AUXADC + 0x0B4)
+#define AUXADC_SPL_CFG1 (BASE_ADDR_AUXADC + 0x0B8)
+#define AUXADC_SPL_CFG2 (BASE_ADDR_AUXADC + 0x0BC)
+#define AUXADC_SADC_CON (BASE_ADDR_AUXADC + 0x300)
+
+extern const kal_uint8 ADC_VBAT;
+extern const kal_uint8 ADC_VISENSE;
+extern const kal_uint8 ADC_VCHARGER;
+
+#define ADC_AUTO_SAMPLE_MODE_EN /* to enable auto sample mode */
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+adc_customized_struct adc_customized_para =
+{
+ ADC_ISENSE_FACTOR,
+ {
+ {
+#if(ADC_MAX_CHANNEL >= 1)
+ ADC_CALIBRATION_SLOPE_CH0
+#endif
+#if(ADC_MAX_CHANNEL >= 2)
+ ,ADC_CALIBRATION_SLOPE_CH1
+#endif
+#if(ADC_MAX_CHANNEL >= 3)
+ ,ADC_CALIBRATION_SLOPE_CH2
+#endif
+#if(ADC_MAX_CHANNEL >= 4)
+ ,ADC_CALIBRATION_SLOPE_CH3
+#endif
+#if(ADC_MAX_CHANNEL >= 5)
+ ,ADC_CALIBRATION_SLOPE_CH4
+#endif
+#if(ADC_MAX_CHANNEL >= 6)
+ ,ADC_CALIBRATION_SLOPE_CH5
+#endif
+ },
+ {
+#if(ADC_MAX_CHANNEL >= 1)
+ ADC_CALIBRATION_OFFSET_CH0
+#endif
+#if(ADC_MAX_CHANNEL >= 2)
+ ,ADC_CALIBRATION_OFFSET_CH1
+#endif
+#if(ADC_MAX_CHANNEL >= 3)
+ ,ADC_CALIBRATION_OFFSET_CH2
+#endif
+#if(ADC_MAX_CHANNEL >= 4)
+ ,ADC_CALIBRATION_OFFSET_CH3
+#endif
+#if(ADC_MAX_CHANNEL >= 5)
+ ,ADC_CALIBRATION_OFFSET_CH4
+#endif
+ }
+ },
+ {
+#if(ADC_MAX_CHANNEL >= 1)
+ ADC_VOLT_FACTOR_CH0
+#endif
+#if(ADC_MAX_CHANNEL >= 2)
+ ,ADC_VOLT_FACTOR_CH1
+#endif
+#if(ADC_MAX_CHANNEL >= 3)
+ ,ADC_VOLT_FACTOR_CH2
+#endif
+#if(ADC_MAX_CHANNEL >= 4)
+ ,ADC_VOLT_FACTOR_CH3
+#endif
+#if(ADC_MAX_CHANNEL >= 5)
+ ,ADC_VOLT_FACTOR_CH4
+#endif
+ }
+};
+
+typedef struct {
+ kal_uint32 Channel;
+ kal_uint32 Pull_Vdd;
+ kal_uint32 Pull_Res;
+ NTC_RT *Rt_Tbl;
+ kal_uint32 Rt_Tbl_Ent;
+} TMP_DET_SETTING;
+
+TMP_DET_SETTING auxadc_tmp_det_setting[2]; /*= {
+ {Pmic_Ntc_ADC_Chan, Pmic_Ntc_Pull_Vdd, Pmic_Ntc_Pull_Res, Pmic_Ntc_Rt_Table, Pmic_Ntc_Rt_Table_Ent},
+ {Asic_Ntc_ADC_Chan, Asic_Ntc_Pull_Vdd, Asic_Ntc_Pull_Res, Asic_Ntc_Rt_Table, Asic_Ntc_Rt_Table_Ent},
+};*/
+
+kal_uint32 auxadc_tmp_det_setting_ent = sizeof(auxadc_tmp_det_setting)/sizeof(auxadc_tmp_det_setting[0]);
+
+
+/*
+* FUNCTION
+* adc_read_calibration_data_inform
+*
+* DESCRIPTION
+* This function is to set adc calibration data from NVRAM
+*
+* CALLS
+*
+* PARAMETERS
+* lim_ptr: adc calibration data, send from NVRAM
+*
+* RETURNS
+* void
+*
+* GLOBALS AFFECTED
+* None
+*/
+void adc_read_calibration_data(void)
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+ int i;
+
+ /* No calibration needed, so ... */
+ for (i = 0; i < ADC_MAX_CHANNEL; i++) {
+ adc_customized_para.adc_cali_param.ADCSlope[i] = 1800000/4096;
+ adc_customized_para.adc_cali_param.ADCOffset[i] = 0;
+ }
+#endif
+}
+
+
+/*
+* FUNCTION
+* ADC_GetData
+*
+* DESCRIPTION
+* This function is to run ADC, and obtain the measured data
+*
+* CALLS
+*
+* PARAMETERS
+* sel : selection of input signal source(0-4)
+*
+* RETURNS
+* return the value of ADC output
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+/*must add power on function before this function*/
+#define ADC_MEA_TIMES 5
+#define ADC_MEA_TMO_MS 20 /* 16T(4~5us) per channel */
+kal_uint16 ADC_GetData(kal_uint8 chIdx)
+{
+ volatile kal_uint32 auxData[ADC_MEA_TIMES], sum = 0;
+ kal_uint32 i;
+ volatile kal_uint32 start_time;
+
+#if defined(ADC_AUTO_SAMPLE_MODE_EN)
+ for (i = 0; i < ADC_MEA_TIMES; i++) {
+ start_time = drv_get_current_time();
+ while(1)
+ {
+ /* Get ADC data */
+ auxData[i] = DRV_Reg32(AUXADC_DAT(chIdx));
+
+ /* Check if RDY bit is set */
+ if ((auxData[i] & (1 << 12))) {
+ break;
+ }
+
+ /* According to Designer's comment, RDY will be set after 16T */
+ if (drv_get_duration_ms(start_time) > ADC_MEA_TMO_MS) {
+ tst_sys_trace("Error: Wait ADC Data RDY Timeout!!!\r\n");
+ break;
+ }
+ }
+
+ auxData[i] &= ~(1<<12);
+ sum += auxData[i];
+ }
+#else
+ /* Select the ADC channel */
+ DRV_SetBits32(AUXADC_CON1, (1 << chIdx));
+
+ for (i = 0; i < ADC_MEA_TIMES; i++) {
+ /* Set the immediate mode */
+ DRV_SetBits32(AUXADC_CON1_SET, (1 << chIdx));
+
+ /* Get ADC data */
+ start_time = drv_get_current_time();
+ auxData[i] = DRV_Reg32(AUXADC_DAT(chIdx));
+ while((!(auxData[i] & (1 << 12))) && (drv_get_duration_ms(start_time) <= ADC_MEA_TMO_MS))
+ {
+ auxData[i] = DRV_Reg32(AUXADC_DAT(chIdx));
+ }
+ auxData[i] &= ~(1<<12);
+ sum += auxData[i];
+
+ /* Clear the immediate mode */
+ DRV_SetBits32(AUXADC_CON1_CLR, (1 << chIdx));
+ }
+
+ /* De-select the ADC channel */
+ DRV_ClearBits32(AUXADC_CON1, (1 << chIdx));
+#endif
+
+ sum = sum / ADC_MEA_TIMES;
+
+ dbg_print("[ADC] %s: chn = %d, result = %X\r\n", __FUNCTION__, chIdx, sum);
+ return (kal_uint16)sum;
+}
+
+/*
+* FUNCTION
+* ADC_GetMeaData
+*
+* DESCRIPTION
+* This function is to run ADC, and obtain the average value of measured data
+* Note that: This function only called before other tasks are running.
+*
+* CALLS
+*
+* PARAMETERS
+* sel : selection of input signal source(0-4)
+* meacount: measure count
+*
+* RETURNS
+* return the average value of ADC output
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_uint32 ADC_GetMeaData(kal_uint8 sel, kal_uint16 meacount)
+{
+ kal_uint32 index;
+ kal_uint32 sum = 0;
+
+ for(index = meacount; index != 0; index--)
+ {
+ sum += (kal_uint32)ADC_GetData(sel);
+ }
+
+ return sum;
+}
+
+/*
+* FUNCTION
+* ADC_GetData2Meta
+*
+* DESCRIPTION
+* This function is called by META, and return the sum value.
+*
+* CALLS
+*
+* PARAMETERS
+* sel : selection of input signal source(0-4)
+* meacount: measure count
+*
+* RETURNS
+* return the average value of ADC output
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_uint32 ADC_GetData2Meta(kal_uint8 sel, kal_uint16 meacount)
+{
+ kal_uint32 index;
+ kal_uint32 sum = 0;
+
+ for(index = meacount; index != 0; index--)
+ {
+ sum += (kal_uint32)ADC_GetData(sel);
+ }
+
+ dbg_print("[ADC] %s: %X\r\n", __FUNCTION__, sum);
+
+ return sum;
+}
+
+void ADC_Init(void)
+{
+ /* Enable source clock */
+ DRV_ClearBits32(0xB6F2D208, (1 << 0));
+
+ /* Change AUXADC from 1.5V to 1.8V */
+ DRV_WriteReg32(0xB6F2F300, DRV_Reg32(0xB6F2F300)|(1<<12));
+
+#if defined(ADC_AUTO_SAMPLE_MODE_EN)
+ /* Enable auto-sample mode */
+ DRV_WriteReg32(AUXADC_CON0, 0x3F);
+
+ /* Enable immediate mode */
+ DRV_WriteReg32(AUXADC_CON1, 0x3F);
+#endif
+
+ /* Initilize global variable */
+ auxadc_tmp_det_setting[0].Channel = Pmic_Ntc_ADC_Chan;
+ auxadc_tmp_det_setting[0].Pull_Vdd = Pmic_Ntc_Pull_Vdd;
+ auxadc_tmp_det_setting[0].Pull_Res = Pmic_Ntc_Pull_Res;
+ auxadc_tmp_det_setting[0].Rt_Tbl = Pmic_Ntc_Rt_Table;
+ auxadc_tmp_det_setting[0].Rt_Tbl_Ent= Pmic_Ntc_Rt_Table_Ent;
+
+ auxadc_tmp_det_setting[1].Channel = Asic_Ntc_ADC_Chan;
+ auxadc_tmp_det_setting[1].Pull_Vdd = Asic_Ntc_Pull_Vdd;
+ auxadc_tmp_det_setting[1].Pull_Res = Asic_Ntc_Pull_Res;
+ auxadc_tmp_det_setting[1].Rt_Tbl = Asic_Ntc_Rt_Table;
+ auxadc_tmp_det_setting[1].Rt_Tbl_Ent= Asic_Ntc_Rt_Table_Ent;
+}
+
+/*
+* FUNCTION
+* adc_adc2vol
+*
+* DESCRIPTION
+* This function is to translate ADC value to voltage.(uV)
+*
+* CALLS
+*
+* PARAMETERS
+* chann: ADC channel.
+* adcVoltage: ADC value
+*
+* RETURNS
+* voltage value(uV)
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_int32 adc_adc2vol(kal_uint8 chann, double adcVoltage)
+{
+ double result;
+
+ if(chann >= ADC_MAX_CHANNEL)
+ ASSERT(0);
+
+ /* Need get the Adc voltage firstly, or does the cali-data contain the conversion ??? */
+
+ /* Do Calibration */
+ result = (double)((adcVoltage*(double)adc_customized_para.adc_cali_param.ADCSlope[chann]) +
+ (double)adc_customized_para.adc_cali_param.ADCOffset[chann]);
+
+ return (kal_int32)result;
+ //return (kal_int32)(result/PMIC_ADC_FACTOR_VBAT*volt_factor);
+}
+
+/*
+* FUNCTION
+* adc_measureVoltage
+*
+* DESCRIPTION
+* This function is to measure voltage of specific channel
+*
+* CALLS
+* Call this API after Drv_Init_Phase1() -->Drv_Customize_Init() --> Finish adc_customized_para initial
+*
+* PARAMETERS
+* chann: ADC channel.
+*
+* RETURNS
+* voltage value(uV)
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_int32 adc_measureVoltage(kal_uint8 chann, double *adc_value)
+{
+ *adc_value = (double)ADC_GetData(chann);
+ return adc_adc2vol(chann, *adc_value);
+}
+
+/*
+* FUNCTION
+* ADC_Volt2Temp
+*
+* DESCRIPTION
+* This function is to translate voltage to temperatrure
+*
+* CALLS
+*
+* PARAMETERS
+* chIdx : AUXADC Channel
+* uVolt : Calibrated Voltage Value, unit (uV)
+*
+* RETURNS
+* temperature(m'C)
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_int32 ADC_Volt2Temp(kal_uint8 chIdx, kal_uint32 uVolt)
+{
+ TMP_DET_SETTING *setting = (TMP_DET_SETTING *)NULL;
+ NTC_RT *rt1 = (NTC_RT *)NULL;
+ NTC_RT *rt2 = (NTC_RT *)NULL;
+ double slope;
+ double ntc_res;
+ kal_int32 ntc_tmp = 0;
+ int i;
+
+ for (i = 0; i < auxadc_tmp_det_setting_ent; i++) {
+ setting = &auxadc_tmp_det_setting[i];
+ if (setting->Channel == chIdx)
+ break;
+ }
+
+ if (i == auxadc_tmp_det_setting_ent) {
+ /* No setting found */
+ return 0;
+ }
+
+ ASSERT(uVolt <= setting->Pull_Vdd);
+
+ if (uVolt < setting->Pull_Vdd) {
+ ntc_res = ((double)uVolt)*setting->Pull_Res/(setting->Pull_Vdd-uVolt);
+ } else {
+ /* pull up too small, or temperature too low */
+ ntc_res = (double)0x0FFFFFFF; /* 268M ohm */
+ }
+
+ ASSERT(setting->Rt_Tbl_Ent >= 2);
+
+ for (i = 0; i < setting->Rt_Tbl_Ent-1; i++) {
+ rt1 = &setting->Rt_Tbl[i]; /* lower temp, bigger res */
+ rt2 = &setting->Rt_Tbl[i+1]; /* higher temp, smaller res */
+
+ if (ntc_res >= rt1->uRes) /* temp too low */
+ break;
+
+ if (rt2->uRes <= ntc_res) /* temp in range */
+ break;
+ }
+
+ ASSERT(rt2->iTemp > rt1->iTemp);
+ ASSERT(rt1->uRes > rt2->uRes);
+
+ /* slope should be negative */
+ slope = ((double)(rt1->iTemp - rt2->iTemp)) / ((double)(rt1->uRes - rt2->uRes));
+
+ ntc_tmp = rt2->iTemp*1000 + (kal_int32)(slope*(ntc_res - rt2->uRes)*1000);
+
+ return ntc_tmp;
+}
+
+
+/*
+* FUNCTION
+* ADC_GetImmTemp
+*
+* DESCRIPTION
+* This function is to get immediate temperature of specific channel
+*
+* CALLS
+* adc_measureVoltage
+* adc_Volt2Temp
+*
+* PARAMETERS
+* chann: ADC channel.
+*
+* RETURNS
+* immediate temperature(C)
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_int16 ADC_GetImmTemp(kal_uint8 chann)
+{
+ double adc_value;
+ kal_uint32 uVolt;
+
+
+ ASSERT(chann < ADC_MAX_CHANNEL);
+
+ uVolt = adc_measureVoltage(chann, &adc_value);
+
+ return ADC_Volt2Temp(chann, uVolt)/1000;
+}
+
+
+/*
+* FUNCTION
+* ADC_GetPhysicalChannel
+*
+* DESCRIPTION
+* This function is to get physical AUXADC Channel ID
+*
+* CALLS
+*
+*
+* PARAMETERS
+* adcname: ADC channel name.
+*
+* RETURNS
+* <0 means error
+* >=0 means AUXADC Channel ID
+*
+* GLOBALS AFFECTED
+* None
+*/
+kal_int16 ADC_GetPhysicalChannel(kal_uint16 adcname)
+{
+ kal_int16 iPhyChan = -1;
+
+ if (adcname == DCL_MDTMP_ADC_CHANNEL) {
+ iPhyChan = Asic_Ntc_ADC_Chan;
+ } else if (adcname == DCL_PMICTMP_ADC_CHANNEL) {
+ iPhyChan = Pmic_Ntc_ADC_Chan;
+ } else {
+ iPhyChan = -1;
+ //ASSERT(0);
+ }
+
+ return iPhyChan;
+}
+
+#else /* !defined(DRV_ADC_OFF) */
+
+#endif
+
diff --git a/mcu/driver/devdrv/auxadc/src/dcl_adc.c b/mcu/driver/devdrv/auxadc/src/dcl_adc.c
new file mode 100644
index 0000000..2f9bb49
--- /dev/null
+++ b/mcu/driver/devdrv/auxadc/src/dcl_adc.c
@@ -0,0 +1,1106 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_adc.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines DCL (Driver Common Layer) of the ADC driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "drv_features.h"
+#include "drv_comm.h"
+#include "syscomp_config.h" /*MOD_BMT*/
+#include "kal_public_defs.h" //MSBB change #include "stack_msgs.h"
+#include "stacklib.h" /* Basic type for dll, evshed, stacktimer */
+#include "stacklib.h" /* Basic type for dll, evshed, stacktimer */
+//#include "event_shed.h" /* Event scheduler */
+//#include "stack_timer.h" /*Timer*/
+#include "adc_hw.h"
+#include "adc_sw.h"
+#include "kal_public_api.h"
+#include "dcl.h"
+#include "nvram_interface.h"
+#include "adc_nvram_def.h"
+
+#if !defined(DRV_ADC_OFF)
+
+// Variables for DCL
+#define DCL_ADC_DEV_MAGIC_NUM (0x20000000) //do not use MAGIC NUM, because it is not used in old API and callback function
+#define MAX_DCL_ADC_HANDLE (120)
+#define MAX_DCL_ADC_SCHE_ID (30)
+
+typedef struct{
+ DCL_HANDLE handle;
+#if !defined(DRV_DISABLE_SAP_ID)
+ DCL_UINT32 adc_sap_id;
+#endif
+// DCL_UINT8 adc_sche_id;
+// DCL_BOOL active;
+ kal_timer_func_ptr measure_cb;
+ PFN_DCLSADC_COMPLETE_CALLBACK complete_cb;
+}dcl_adc_sche_mgr;
+
+static kal_bool fgHADCInit = KAL_FALSE;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
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+/* under construction !*/
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+/* under construction !*/
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+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if !defined(DRV_DISABLE_SAP_ID)
+/* under construction !*/
+ #endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+
+DCL_STATUS DclSADC_Initialize(void){return STATUS_OK;}
+DCL_HANDLE DclSADC_Open(DCL_DEV dev, DCL_FLAGS flags){return STATUS_OK;}
+DCL_STATUS DclSADC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){return STATUS_OK;}
+DCL_STATUS DclSADC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){return STATUS_OK;}
+DCL_STATUS DclSADC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure){return STATUS_OK;}
+DCL_STATUS DclSADC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback){return STATUS_OK;}
+DCL_STATUS DclSADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data){return STATUS_OK;}
+DCL_STATUS DclSADC_Close(DCL_HANDLE handle){return STATUS_OK;}
+
+#endif
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+#define MAX_DCL_HADC_HANDLE (1)
+
+
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_Initialize
+*
+* DESCRIPTION
+* This function is to initialize Hardware ADC module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern nvram_ltable_entry_struct logical_data_item_table_adc[];
+extern void thermal_prot_init();
+DCL_STATUS DclHADC_Initialize(void){
+
+ dbg_print("[ADC] %s\r\n", __FUNCTION__);
+
+ if(fgHADCInit == KAL_FALSE)
+ {
+ nvram_ltable_register(logical_data_item_table_adc);
+
+ ADC_Init();
+
+ fgHADCInit = KAL_TRUE;
+ }
+
+ thermal_prot_init();
+
+ return STATUS_OK;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_Open
+*
+* DESCRIPTION
+* This function is to open the Hardware ADC module and return a handle
+*
+* PARAMETERS
+* dev: only valid for Hardware DCL_ADC
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed
+* Other value: A valid handle
+*
+*************************************************************************/
+static kal_bool fgHADCOpen = KAL_FALSE;
+DCL_HANDLE DclHADC_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+ if (!fgHADCOpen) {
+ adc_read_calibration_data();
+ fgHADCOpen = KAL_TRUE;
+ }
+
+ if( ( dev != DCL_ADC ) || (fgHADCInit == KAL_FALSE))
+ {
+ ASSERT(0);
+ return DCL_HANDLE_INVALID; // Incorrecr device ID
+ }
+
+ return DCL_ADC_DEV_MAGIC_NUM;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclHADC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclHADC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_Configure
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclHADC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclHADC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_Control
+*
+* DESCRIPTION
+* This function is to send command to control the Hardware ADC module.
+*
+* PARAMETERS
+* handle: A valid handle return by DclHADC_Open()
+* cmd: A control command for ADC module
+* 1. ADC_CMD_IMM_MEASURE: to perform a immediate mode measurement (Register control only, not include power setting)
+* 2. ADC_CMD_SYNC_MEASURE: to perform a sync mode measurement (Register control only, not include power setting)
+* 3. ADC_CMD_TDMA_SYNC_SETUP: to setup TDMA sync mode parameters
+* 4. ADC_CMD_POWER: to turn on/off ADC module power
+* data: The data of the control command
+* 1. ADC_CMD_IMM_MEASURE: pointer to a ADC_CTRL_IMM_MEASURE_T structure
+* 2. ADC_CMD_SYNC_MEASURE: pointer to a ADC_CTRL_SYNC_MEASURE_T structure
+* 3. ADC_CMD_TDMA_SYNC_SETUP: pointer to a ADC_CTRL_TDMA_SYNC_SETUP_T structure
+* 4. ADC_CMD_POWER: pointer to a ADC_CTRL_POWER_T structure
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+kal_bool dcl_hadc_power_state = KAL_FALSE;
+DCL_STATUS DclHADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ switch (cmd)
+ {
+ case ADC_CMD_IMM_MEASURE:
+ {
+ #if 1
+ ADC_CTRL_IMM_MEASURE_T *prIMMMeasure;
+ prIMMMeasure = &(data->rADCImmMeasure);
+ prIMMMeasure->u2ADCValue = (DCL_UINT16)adc_measureVoltage(prIMMMeasure->u2Channel,
+ (double *)&prIMMMeasure->u2ADCValue);
+ #endif
+
+ return STATUS_OK;
+ }
+ case ADC_CMD_SYNC_MEASURE:
+ {
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+
+ return STATUS_OK;
+ }
+ case ADC_CMD_TDMA_SYNC_SETUP:
+ {
+ #if 0//defined(DRV_ADC_FULL_FUNC)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #else // #if defined(DRV_ADC_FULL_FUNC)
+
+ // Not supported
+ return STATUS_INVALID_CMD;
+ #endif
+ }
+ case ADC_CMD_POWER:
+ {
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+
+ return STATUS_OK;
+ }
+ case ADC_CMD_GET_DATA_2_META:
+ {
+ ADC_CTRL_GET_DATA_2_META_T *prGetData2Meta;
+ prGetData2Meta = &(data->rADCGetData2Meta);
+
+ prGetData2Meta->u4ADCData = ADC_GetData2Meta(prGetData2Meta->u1Channel, prGetData2Meta->u2MeaCount);
+ return STATUS_OK;
+ }
+ case ADC_CMD_GET_DATA:
+ {
+ ADC_CTRL_GET_DATA_T *prGetData;
+ prGetData = &(data->rADCGetData);
+
+ prGetData->u4ADCData = ADC_GetData(prGetData->u1Channel);
+ return STATUS_OK;
+ }
+ case ADC_CMD_GET_META_DATA:
+ {
+ ADC_CTRL_GET_META_DATA_T *prGetMetaData;
+ prGetMetaData = &(data->rADCGetMetaData);
+
+ prGetMetaData->u4ADCData = ADC_GetMeaData(prGetMetaData->u1Channel, prGetMetaData->u2MeaCount);
+ return STATUS_OK;
+ }
+ case ADC_CMD_GET_MAX_PHYSICAL_CH:
+ {
+ ADC_CTRL_GET_MAX_PHYSICAL_CH_T *prGetMaxPhyCh;
+ prGetMaxPhyCh = &(data->rADCGetMaxPhyCh);
+
+ prGetMaxPhyCh->u4Adc_max_ch = ADC_MAX_CHANNEL;
+ return STATUS_OK;
+ }
+ case ADC_CMD_GET_IMM_DATA_ON_BOOTING:
+ {
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+
+ return STATUS_OK;
+ }
+ case ADC_CMD_GET_TEMP:
+ {
+ ADC_CTRL_GET_TEMP_T *prGetTemp;
+ prGetTemp = &(data->rGetTempData);
+
+ prGetTemp->i2Temp = ADC_GetImmTemp(prGetTemp->u2Channel);
+
+ return STATUS_OK;
+ }
+
+ case ADC_CMD_GET_PHYSICAL_CHANNEL:
+ {
+ ADC_CTRL_GET_PHYSICAL_CHANNEL_T *prGetChannel;
+ kal_int16 iChannel;
+
+ prGetChannel = &(data->rADCGetPhyChannel);
+ iChannel = ADC_GetPhysicalChannel(prGetChannel->u2AdcName);
+
+ if (iChannel >= 0) {
+ prGetChannel->u1AdcPhyCh = (DCL_UINT8)iChannel;
+ return STATUS_OK;
+ } else {
+ prGetChannel->u1AdcPhyCh = 0;
+ return STATUS_INVALID_DEVICE;
+ }
+ }
+
+ default:
+ return STATUS_INVALID_CMD;
+ }
+ //return STATUS_FAIL;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_Close
+*
+* DESCRIPTION
+* This function is to close the Hardware ADC module.
+*
+* PARAMETERS
+* handle: the returned handle value of HDclADC_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclHADC_Close(DCL_HANDLE handle)
+{
+// DCL_UINT32 savedMask;
+
+ // Error check
+// if (dcl_hadc_handle_count == 0){
+// ASSERT(0);
+// return STATUS_NOT_OPENED;
+// }
+
+ // Extract handle idx
+
+// savedMask = SaveAndSetIRQMask();
+// dcl_hadc_handle_count --;
+// RestoreIRQMask(savedMask);
+// fgHADCInit = KAL_FALSE;
+
+ return STATUS_OK;
+}
+
+// Only empty APIs
+#else // DRV_ADC_OFF is defined
+DCL_STATUS DclSADC_Initialize(void){return STATUS_OK;}
+DCL_HANDLE DclSADC_Open(DCL_DEV dev, DCL_FLAGS flags){return STATUS_OK;}
+DCL_STATUS DclSADC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){return STATUS_OK;}
+DCL_STATUS DclSADC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){return STATUS_OK;}
+DCL_STATUS DclSADC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure){return STATUS_OK;}
+DCL_STATUS DclSADC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback){return STATUS_OK;}
+DCL_STATUS DclSADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data){return STATUS_OK;}
+DCL_STATUS DclSADC_Close(DCL_HANDLE handle){return STATUS_OK;}
+DCL_STATUS DclHADC_Initialize(void) {return STATUS_OK; }
+DCL_HANDLE DclHADC_Open(DCL_DEV dev, DCL_FLAGS flags){return STATUS_OK;}
+DCL_STATUS DclHADC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){return STATUS_OK;}
+DCL_STATUS DclHADC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){return STATUS_OK;}
+DCL_STATUS DclHADC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure){return STATUS_OK;}
+DCL_STATUS DclHADC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback){return STATUS_OK;}
+DCL_STATUS DclHADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data){return STATUS_OK;}
+DCL_STATUS DclHADC_Close(DCL_HANDLE handle){return STATUS_OK;}
+#endif // #if defined(DRV_ADC_OFF)
+
diff --git a/mcu/driver/devdrv/auxadc/src/drv_thermal_protect.c b/mcu/driver/devdrv/auxadc/src/drv_thermal_protect.c
new file mode 100644
index 0000000..baeae33
--- /dev/null
+++ b/mcu/driver/devdrv/auxadc/src/drv_thermal_protect.c
@@ -0,0 +1,558 @@
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "dcl.h"
+#include "kal_trace.h"
+#include "drv_thermal_protect.h"
+#include "drv_emi.h"
+#include "drv_features.h"
+
+#if !defined(DRV_ADC_OFF)
+#define DRV_THERMAL_PROTECT
+#endif
+
+/****** To Enable Phase 1 Mechanism **********/
+#define THERMAL_PROTECT_RESET_MD
+
+/****** To Enable Phase 2 Mechanism **********/
+#define THERMAL_PROTECT_AIRPLANE_MODE
+
+#if defined(DRV_THERMAL_PROTECT) && defined(__MTK_TARGET__)
+
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE)
+#include "md_sap.h" // mcu/interface/sap
+#include "l4_msgid.h" // mcu/interface/sap/md/
+#include "rmmi_struct.h" // mcu/interface/modem/general
+#endif
+
+// For phase2, don't start detection before AP side setting threshold
+#define NO_THRESHOLD_SETTING ((kal_int16)0xA22A) // magic number => will not monitor the sensor
+#define DEFAULT_THERMAL_THLD (NO_THRESHOLD_SETTING) // !!!Important
+
+/* MS to TICK convertion */
+#define MSEC_PER_TIMER_TICK (10)
+#define MSEC_TO_TIMER_TICKS(ms) ((ms)/(MSEC_PER_TIMER_TICK))
+
+/* 3--30C, 4-Reserved, 5--85C, 6--95C, 7--105C */
+#define MAX_DRAM_REFRESH_RATE (7)
+#define DRAM_REFRESH_RATE_THLD (7)
+
+/* To avoid continuously reset due to temperature cannot cool down immediately */
+#define INIT_DETECT_INTERVAL (600) /* max 65,535 ticks */
+
+/* For debug purpose */
+//#define DEBUG_PERIOD_SAMPLE
+#define SAMPLE_INTERVAL_SECOND (10)
+
+typedef struct {
+ kal_uint32 detect_timer1;
+ kal_uint32 detect_timer2;
+ kal_uint32 polling_interval;
+
+#if defined(DEBUG_PERIOD_SAMPLE)
+ kal_uint32 sample_timer;
+ kal_uint32 sample_interval;
+ kal_uint32 reset_limit;
+#endif
+ kal_int16 threshold[thermal_sensor_num];
+ kal_int16 warn_temp[thermal_sensor_num];
+} thermal_prot_cb;
+
+static thermal_prot_cb g_thermal_prot_cb = {0, 0, 0};
+
+
+/**********************************************************************
+ * Imported APIs implemented in other Files
+ ***********************************************************************/
+extern void dbg_print(char *fmt, ...);
+extern kal_int32 vsnprintf( kal_char *str, kal_uint32 size, const kal_char *fmt,
+ va_list ap );
+
+
+/**********************************************************************
+ * Internal APIs called in this File
+ ***********************************************************************/
+static kal_int32 thermal_prot_print(trace_class_enum level, const char *fmt, ...)
+{
+ static kal_char dbg_buff[256];
+ kal_int32 ret;
+ va_list args;
+
+ va_start(args, fmt);
+ ret = vsnprintf(dbg_buff, 256, fmt, args);
+ va_end(args);
+
+ dbg_print(dbg_buff);
+ dhl_print(level, DHL_USER_FLAG_NONE, MOD_SYSTEM, dbg_buff);
+
+ return ret;
+}
+
+#if defined(THERMAL_PROTECT_RESET_MD) || defined(THERMAL_PROTECT_AIRPLANE_MODE) || defined(DEBUG_PERIOD_SAMPLE)
+static kal_bool thermal_prot_start_timer(kal_uint32 handle,kal_uint32 msecs, void (*timer_callback)(void *),void *parameter)
+{
+ SGPT_CTRL_START_T ctrlVariable;
+ DCL_STATUS status;
+
+ ctrlVariable.u2Tick = (kal_uint16)MSEC_TO_TIMER_TICKS(msecs);
+ ctrlVariable.pfCallback = timer_callback;
+ ctrlVariable.vPara = parameter;
+ status = DclSGPT_Control(handle, SGPT_CMD_START, (DCL_CTRL_DATA_T *)&ctrlVariable);
+
+ return (status==STATUS_OK)?KAL_TRUE : KAL_FALSE;
+}
+
+static kal_bool thermal_prot_stop_timer(kal_uint32 handle)
+{
+ DCL_STATUS status;
+
+ status = DclSGPT_Control(handle, SGPT_CMD_STOP, 0);
+
+ return (status==STATUS_OK)?KAL_TRUE : KAL_FALSE;
+}
+
+static kal_uint32 thermal_prot_create_timer()
+{
+ return DclSGPT_Open(DCL_GPT_CB, 0);
+}
+#endif
+
+
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE) || defined(DEBUG_PERIOD_SAMPLE)
+static kal_int32 thermal_prot_get_auxadc_tmp(kal_uint16 adc_name, kal_int16 *p_temp)
+{
+ DCL_HANDLE adc_handle;
+ ADC_CTRL_GET_PHYSICAL_CHANNEL_T getChannel;
+ ADC_CTRL_GET_TEMP_T getTemp;
+ DCL_STATUS sts;
+
+ if (p_temp == NULL)
+ return -1;
+
+ adc_handle = DclHADC_Open(DCL_ADC, FLAGS_NONE);
+ if (adc_handle == DCL_HANDLE_INVALID) {
+ return -1;
+ }
+
+ getChannel.u2AdcName = adc_name;
+ sts = DclHADC_Control(adc_handle, ADC_CMD_GET_PHYSICAL_CHANNEL, (DCL_CTRL_DATA_T *)&getChannel);
+ if (sts != STATUS_OK) {
+ return -1;
+ }
+
+ getTemp.u2Channel = getChannel.u1AdcPhyCh;
+ sts = DclHADC_Control(adc_handle, ADC_CMD_GET_TEMP, (DCL_CTRL_DATA_T *)&getTemp);
+ if (sts != STATUS_OK) {
+ return -1;
+ }
+
+ DclHADC_Close(adc_handle);
+
+ *p_temp = getTemp.i2Temp;
+
+ if (getTemp.i2Temp > 300 || getTemp.i2Temp < -100) {
+ /* it can happen when AUXADC or Themister is not configured correctly (not mounted) */
+ return -1;
+ }
+
+ return 0;
+}
+#endif
+
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE)
+/***************************************************************************
+In this protect mode (Phase2),
+
+MD will monitor thermal info every 1 second,
+If overrun detected, inform AP with AT command to let AP set airplane mode
+
+Currently, three sensors will be monitored:
+1. DRAM Refresh Rate
+2. 6290M NTC (AUXADC0)
+3. PA NTC (AUXADC1)
+
+AP Side can set the threshold for each sensor.
+*****************************************************************************/
+static void thermal_prot_detect_timer2_callback(void *parameter);
+kal_bool thermal_prot_set_threshold(thermal_sensor_type sensor_type, kal_int16 threshold)
+{
+ if (sensor_type >= thermal_sensor_num) {
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] invalid sensor type %d [%s]\r\n", sensor_type, __FUNCTION__);
+ return KAL_FALSE;
+ }
+
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] sensor_type:%d threshold:%d [%s]\r\n", sensor_type, threshold, __FUNCTION__);
+
+ g_thermal_prot_cb.threshold[sensor_type] = threshold;
+ g_thermal_prot_cb.warn_temp[sensor_type] = threshold*90/100;
+
+ /* stop detect timer first */
+ thermal_prot_stop_timer(g_thermal_prot_cb.detect_timer2);
+
+ /* then call timer callback directly, this will check sensors immediately and restart timer if needed */
+ thermal_prot_detect_timer2_callback(NULL);
+
+ return KAL_TRUE;
+}
+
+static void thermal_prot_phase2_action(thermal_sensor_type sensor, kal_int16 temp)
+{
+ atci_thermal_event_report_ind_struct *local_ptr = NULL;
+
+ local_ptr = (atci_thermal_event_report_ind_struct *)
+ construct_local_para(sizeof(atci_thermal_event_report_ind_struct), TD_RESET);
+
+ local_ptr->type = (kal_uint8)sensor;
+ local_ptr->value = temp;
+
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] %s %d %d\r\n", __FUNCTION__, sensor, temp);
+ msg_send6((module_type)MOD_SYSTEM, (module_type)MOD_ATCI, ATCI_SAP,
+ (msg_type)MSG_ID_ATCI_THERMAL_EVENT_REPORT_IND,
+ (local_para_struct *)local_ptr,
+ (peer_buff_struct*)NULL);
+}
+
+static kal_int32 thermal_prot_phase2_handle()
+{
+ kal_int16 temp;
+ kal_int16 threshold;
+ kal_int32 ret;
+ static kal_int32 count = 0;
+ kal_int32 next_interval = 0;
+
+ count++;
+
+ /* Monitor DRAM Refresh Rate */
+ threshold = g_thermal_prot_cb.threshold[thermal_sensor_dram];
+ if (threshold != NO_THRESHOLD_SETTING) {
+ temp = emi_get_dram_temp();
+ if (temp >= threshold) {
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] DRAM SENOR Exceeds Threshold (%d)\r\n", threshold);
+ thermal_prot_phase2_action(thermal_sensor_dram, temp);
+ return 0;
+ }
+ if (temp >= g_thermal_prot_cb.warn_temp[thermal_sensor_dram]) {
+ /* print log if exceeds 90% */
+ if ((count%2) == 0)
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] DRAM SENOR Temp %d\r\n", temp);
+ }
+ next_interval = 1000;
+ }
+
+ /* Monitor MD NTC Temperature */
+ threshold = g_thermal_prot_cb.threshold[thermal_sensor_md_ntc];
+ if (threshold != NO_THRESHOLD_SETTING) {
+ ret = thermal_prot_get_auxadc_tmp(DCL_MDTMP_ADC_CHANNEL, &temp);
+ if (ret == 0 && temp >= threshold) {
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] MD_NTC SENOR Exceeds Threshold (%d)\r\n", threshold);
+ thermal_prot_phase2_action(thermal_sensor_md_ntc, temp);
+ return 0;
+ }
+ if (ret == 0 && temp >= g_thermal_prot_cb.warn_temp[thermal_sensor_md_ntc]) {
+ /* print log if exceeds 90% */
+ if ((count%2) == 0)
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] MD_NTC SENOR Temp %d\r\n", temp);
+ }
+ next_interval = 1000;
+ }
+
+ /* Monitor PMIC/B7_PA NTC Temperature */
+ threshold = g_thermal_prot_cb.threshold[thermal_sensor_pa_ntc];
+ if (threshold != NO_THRESHOLD_SETTING) {
+ ret = thermal_prot_get_auxadc_tmp(DCL_PMICTMP_ADC_CHANNEL, &temp);
+ if (ret == 0 && temp >= threshold) {
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] PA_NTC SENOR Exceeds Threshold (%d)\r\n", threshold);
+ thermal_prot_phase2_action(thermal_sensor_pa_ntc, temp);
+ return 0;
+ }
+ if (ret == 0 && temp >= g_thermal_prot_cb.warn_temp[thermal_sensor_pa_ntc]) {
+ /* print log if exceeds 90% */
+ if ((count%2) == 0)
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] PA_NTC SENOR Temp %d\r\n", temp);
+ }
+ next_interval = 1000;
+ }
+
+ return next_interval;
+}
+
+static void thermal_prot_detect_timer2_callback(void *parameter)
+{
+ kal_int32 next_interval = 0;
+
+ next_interval = thermal_prot_phase2_handle();
+
+ if (next_interval != 0) {
+ /* not overrun, restart timer to do next polling */
+ thermal_prot_start_timer(g_thermal_prot_cb.detect_timer2, next_interval, thermal_prot_detect_timer2_callback, NULL);
+ }
+}
+#endif
+
+#ifdef THERMAL_PROTECT_RESET_MD
+/***************************************************************************
+In this protect mode (Phase1),
+
+MD will monitor DRAM Refresh Rate periodically,
+If overrun detected, inform AP to RESET MD
+Threshold setting: 3b'111
+
+*****************************************************************************/
+static void thermal_prot_phase1_action()
+{
+ DCL_HANDLE wdt_handle;
+
+ wdt_handle = DclWDT_Open(DCL_WDT, 0);
+ DclWDT_Control(wdt_handle, WDT_CMD_ABN_RESET, 0);
+ DclWDT_Close(wdt_handle);
+}
+
+static kal_int32 thermal_prot_phase1_handle()
+{
+ static kal_uint32 last_high_rate = 0xFFFFFFFF;
+ static kal_int32 check_cnt = 0;
+ kal_uint32 dram_ref_rate = 0;
+ kal_uint32 dram_ref_thld = 0;
+ kal_uint32 next_interval = 100;
+
+ dram_ref_rate = emi_get_dram_refresh_rate();
+ if (dram_ref_rate > MAX_DRAM_REFRESH_RATE) {
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] dram refresh rate is %d, exceeds max(%d)\r\n", dram_ref_rate, MAX_DRAM_REFRESH_RATE);
+ return 0;
+ }
+
+ dram_ref_thld = DRAM_REFRESH_RATE_THLD;
+
+ if (last_high_rate == 0xFFFFFFFF) {
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] dram refresh rate is %d\r\n", dram_ref_rate);
+ last_high_rate = dram_ref_rate;
+ } else {
+ if (dram_ref_rate > last_high_rate) {
+ /* log immdiately if temperature become higher, have little influence to log amount */
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] dram refresh rate change %d ==> %d\r\n", last_high_rate, dram_ref_rate);
+ last_high_rate = dram_ref_rate;
+ check_cnt = 0;
+ } else if (dram_ref_rate < last_high_rate) {
+ /* check for 10 seconds, to reduce log amount */
+ check_cnt ++;
+ if (check_cnt > 100) {
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] dram refresh rate change %d ==> %d\r\n", last_high_rate, dram_ref_rate);
+ last_high_rate = dram_ref_rate;
+ }
+ } else {
+ /* don't log if no change */
+ ;
+ }
+ }
+
+ /* check if overrun */
+ if (dram_ref_rate >= dram_ref_thld)
+ {
+ thermal_prot_print(TRACE_ERROR, "[Thermal Protection] dram refresh rate reach threshold %d !!!!!!\r\n", dram_ref_thld);
+ thermal_prot_phase1_action();
+ return 0;
+ }
+
+ /* set next timer interval */
+ if (dram_ref_rate < 5) {
+ /* < 90C */
+ next_interval = 1000;
+ } else if (dram_ref_rate < 6) {
+ /* < 100C */
+ static kal_uint32 cnt2_for_log = 0;
+
+ cnt2_for_log ++;
+ if ((cnt2_for_log%10)==0)
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] dram refresh rate is %d \r\n", dram_ref_rate);
+
+ next_interval = 500;
+ } else if (dram_ref_rate < 7) {
+ /* < 105C */
+ static kal_uint32 cnt1_for_log = 0;
+
+ cnt1_for_log ++;
+ if ((cnt1_for_log%10)==0)
+ thermal_prot_print(TRACE_WARNING, "[Thermal Protection] dram refresh rate is %d \r\n", dram_ref_rate);
+
+ next_interval = 200;
+ } else {
+ /* never reach here */
+ next_interval = 200;
+ }
+
+ return next_interval;
+}
+
+static void thermal_prot_detect_timer1_callback(void *parameter)
+{
+ kal_int32 next_interval = 0;
+
+ next_interval = thermal_prot_phase1_handle();
+
+ if (next_interval != 0) {
+ /* not overrun, restart timer to do next polling */
+ thermal_prot_start_timer(g_thermal_prot_cb.detect_timer1, next_interval, thermal_prot_detect_timer1_callback, NULL);
+ }
+}
+#endif
+
+
+#if defined(DEBUG_PERIOD_SAMPLE)
+static void thermal_prot_sample_temp_info()
+{
+ kal_uint32 dram_ref_rate = 0;
+ kal_int16 adc0_temp = -123;
+ kal_int16 adc1_temp = -123;
+ kal_uint16 adc0_name = DCL_MDTMP_ADC_CHANNEL;
+ kal_uint16 adc1_name = DCL_PMICTMP_ADC_CHANNEL;
+ static kal_uint32 times = 0;
+#if !defined(THERMAL_PROTECT_AIRPLANE_MODE)
+ dram_ref_rate = emi_get_dram_refresh_rate();
+#else
+ dram_ref_rate = emi_get_dram_temp();
+#endif
+ thermal_prot_get_auxadc_tmp(adc0_name, &adc0_temp);
+ thermal_prot_get_auxadc_tmp(adc1_name, &adc1_temp);
+
+ times++;
+
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] SAMPLE_DATA: \t%d \t%d \t%d \t%d\r\n",times, dram_ref_rate, adc0_temp, adc1_temp);
+}
+
+static void thermal_prot_sample_timer_callback(void *parameter)
+{
+ static kal_int32 count = 0;
+
+ if ((count%SAMPLE_INTERVAL_SECOND) == 0) {
+ thermal_prot_sample_temp_info();
+ }
+
+ count ++;
+
+ thermal_prot_start_timer(g_thermal_prot_cb.sample_timer, g_thermal_prot_cb.sample_interval, thermal_prot_sample_timer_callback, NULL);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+#endif
+
+static void thermal_prot_init_threshold()
+{
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE)
+ int idx;
+
+ for (idx = 0; idx < thermal_sensor_num; idx++) {
+ // Init default threshold
+ g_thermal_prot_cb.threshold[idx] = DEFAULT_THERMAL_THLD;
+ g_thermal_prot_cb.warn_temp[idx] = DEFAULT_THERMAL_THLD*90/100;
+ }
+#endif
+}
+
+/**********************************************************************
+ * Global APIs called from other Files
+ ***********************************************************************/
+kal_bool thermal_prot_stop()
+{
+ kal_bool ret = KAL_FALSE;
+
+#if defined(THERMAL_PROTECT_RESET_MD)
+ if (g_thermal_prot_cb.detect_timer1 != 0) {
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] %s \r\n", __FUNCTION__);
+ ret = thermal_prot_stop_timer(g_thermal_prot_cb.detect_timer1);
+ }
+#endif
+
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE)
+ if (g_thermal_prot_cb.detect_timer2 != 0) {
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] %s \r\n", __FUNCTION__);
+ ret = thermal_prot_stop_timer(g_thermal_prot_cb.detect_timer2);
+ }
+#endif
+
+#if defined(DEBUG_PERIOD_SAMPLE)
+ if (g_thermal_prot_cb.sample_timer != 0) {
+ ret = thermal_prot_stop_timer(g_thermal_prot_cb.sample_timer);
+ }
+#endif
+
+ return ret;
+}
+
+kal_bool thermal_prot_run()
+{
+ kal_bool ret = KAL_FALSE;
+
+#if defined(THERMAL_PROTECT_RESET_MD)
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] dram refresh rate is %d\r\n", emi_get_dram_refresh_rate());
+ if (g_thermal_prot_cb.detect_timer1 != 0) {
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] %s \r\n", __FUNCTION__);
+ ret = thermal_prot_start_timer(g_thermal_prot_cb.detect_timer1, g_thermal_prot_cb.polling_interval, thermal_prot_detect_timer1_callback, NULL);
+ }
+#endif
+
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE)
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] dram sensor temp is %d\r\n", emi_get_dram_temp());
+ if (g_thermal_prot_cb.detect_timer2 != 0) {
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] %s \r\n", __FUNCTION__);
+ ret = thermal_prot_start_timer(g_thermal_prot_cb.detect_timer2, g_thermal_prot_cb.polling_interval, thermal_prot_detect_timer2_callback, NULL);
+ }
+#endif
+
+#if defined(DEBUG_PERIOD_SAMPLE)
+ if (g_thermal_prot_cb.sample_timer != 0) {
+ ret = thermal_prot_start_timer(g_thermal_prot_cb.sample_timer, g_thermal_prot_cb.sample_interval, thermal_prot_sample_timer_callback, NULL);
+ }
+#endif
+
+ return ret;
+}
+
+void thermal_prot_init()
+{
+ static kal_bool init_done = KAL_FALSE;
+
+ if (init_done == KAL_TRUE)
+ return;
+
+ thermal_prot_print(TRACE_INFO, "[Thermal Protection] %s \r\n", __FUNCTION__);
+
+ thermal_prot_init_threshold();
+
+#if defined(THERMAL_PROTECT_RESET_MD)
+ g_thermal_prot_cb.detect_timer1 = thermal_prot_create_timer();
+#endif
+
+#if defined(THERMAL_PROTECT_AIRPLANE_MODE)
+ g_thermal_prot_cb.detect_timer2 = thermal_prot_create_timer();
+#endif
+
+ if (INIT_DETECT_INTERVAL < MSEC_PER_TIMER_TICK || INIT_DETECT_INTERVAL > 655360)
+ g_thermal_prot_cb.polling_interval = MSEC_PER_TIMER_TICK*10;
+ else
+ g_thermal_prot_cb.polling_interval = INIT_DETECT_INTERVAL;
+
+#if defined(DEBUG_PERIOD_SAMPLE)
+ g_thermal_prot_cb.sample_timer = thermal_prot_create_timer();
+ g_thermal_prot_cb.sample_interval = 1000;
+ g_thermal_prot_cb.reset_limit = 60;
+#endif
+
+ init_done = KAL_TRUE;
+
+ /* just run after init */
+ thermal_prot_run();
+}
+
+#else
+kal_bool thermal_prot_set_threshold(thermal_sensor_type sensor_type, kal_int16 threshold) {return KAL_TRUE;}
+kal_bool thermal_prot_stop() {return KAL_TRUE;}
+kal_bool thermal_prot_run() {return KAL_TRUE;}
+void thermal_prot_init() {;}
+#endif
+
+