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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/cmif/cmif_test/folder_create b/mcu/driver/devdrv/cmif/cmif_test/folder_create
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/folder_create
diff --git a/mcu/driver/devdrv/cmif/cmif_test/inc/cmif_test.h b/mcu/driver/devdrv/cmif/cmif_test/inc/cmif_test.h
new file mode 100644
index 0000000..112a2b4
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/inc/cmif_test.h
@@ -0,0 +1,143 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CMIF_TEST_H__
+#define __CMIF_TEST_H__
+
+#include "ssdvt_typedef.h"
+#include "sync_data.h"
+
+/*******************************************************************************
+* Macros
+*******************************************************************************/
+#if (defined(__CORE_BRP__) || defined(__CORE_DFE__) || defined(__CORE_RAKE__))
+#define SSDVT_CMIF_GET_LSB(b) SSDVT_GET_LSB((b))
+#else /* __CORE_BRP__ || __CORE_DFE__ || __CORE_RAKE__ */
+#define SSDVT_CMIF_CLZ(z) __builtin_clz((z))
+#define SSDVT_CMIF_GET_LSB(b) (31 - SSDVT_CMIF_CLZ((b) & -(b)))
+#endif /* __CORE_BRP__ || __CORE_DFE__ || __CORE_RAKE__ */
+
+
+#define SSDVT_CMIF_EXCHANGE_CLIENT_NUMBER(c) c = (c)?0:1;
+
+/*******************************************************************************
+* CMIF Memory Definition
+*******************************************************************************/
+#define SSDVT_CMIF_INTERRUPT_SIZE 32
+#define SSDVT_CMIF_INTERRUPT_WAIT_LOOP_COUNT 1000
+
+// for the most handsome iger.
+#define SSDVT_CMIF_M2C_WFI_ISR_CHECK_PATTERN 0x39383938
+
+#define SSDVT_UMIF_SYNC_MEM_SIZE 8
+
+#if !defined(__MD32S_SSDVT_RTLCOSIM__)
+#define SSDVT_CMIF_SYNC_MEM_SIZE 8
+#else /* __MD32S_SSDVT_RTLCOSIM__ */
+#define SSDVT_CMIF_SYNC_MEM_SIZE (8 + SSDVT_RTLCOSIM_SIZE)
+#endif /* __MD32S_SSDVT_RTLCOSIM__ */
+
+/*******************************************************************************
+* CMIF Interrupt Register Information
+*******************************************************************************/
+
+/* Check offset, the base is 0x54*/
+#define SSDVT_CMIF_C2M_U3G_CHECK_MEM_OFFSET (0x0)
+#define SSDVT_CMIF_M2C_U3G_CHECK_MEM_OFFSET (0x4)
+#define SSDVT_CMIF_M2C_WFI_CHECK_MEM_OFFSET (0x8)
+#define SSDVT_CMIF_M2C_FPC_1X_CHECK_MEM_OFFSET (0xC)
+#define SSDVT_CMIF_M2C_DO_PD_CHECK_MEM_OFFSET (0x10)
+#define SSDVT_CMIF_M2C_FOE_1X_CHECK_MEM_OFFSET (0x14)
+#define SSDVT_CMIF_U2M_INN_CHECK_MEM_OFFSET (0x18)
+#define SSDVT_CMIF_M2U_INN_CHECK_MEM_OFFSET (0x1C)
+#define SSDVT_CMIF_U2M_OUT_CHECK_MEM_OFFSET (0x20)
+#define SSDVT_CMIF_M2U_OUT_CHECK_MEM_OFFSET (0x24)
+
+/*******************************************************************************
+* Function prototypes
+*******************************************************************************/
+/**
+ * @note CMIF(CR4-MD32) test, it would test CR4 to MD32, MD32 to CR4 and two cores writing concurrently.
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_CMIF_Test(void);
+
+#endif /* __CMIF_TEST_H__ */
diff --git a/mcu/driver/devdrv/cmif/cmif_test/inc/memory_test.h b/mcu/driver/devdrv/cmif/cmif_test/inc/memory_test.h
new file mode 100644
index 0000000..8f583b2
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/inc/memory_test.h
@@ -0,0 +1,316 @@
+#ifndef __MEMORY_TEST_H__
+#define __MEMORY_TEST_H__
+
+#include "ssdvt_typedef.h"
+
+/*******************************************************************************
+* Macros
+*******************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#define SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(value, expect_value) \
+ do{ \
+ if((value) != (expect_value)){ \
+ ERROR_LOOP; \
+ } \
+ }while(0);
+
+/*******************************************************************************
+* Definitions
+*******************************************************************************/
+/* reduce test buffer size in simulation to save simulation time */
+#if defined(__SIMULATION__)
+#define SSDVT_MEM_TEST_BUFFER_SIZE 0x80
+#else
+#define SSDVT_MEM_TEST_BUFFER_SIZE 0x1000
+#endif
+
+/*******************************************************************************
+* Typedefes
+*******************************************************************************/
+typedef enum SSDVT_MEM_TestType_t{
+ SSDVT_MEM_NO_TEST_TYPE = 0x0,
+ SSDVT_MEM_MD32_TEST_TYPE = 0x1,
+ SSDVT_MEM_CMIF_TEST_TYPE = 0x2,
+ SSDVT_MEM_MMIF_TEST_TYPE = 0x3,
+ SSDVT_MEM_MSIF_TEST_TYPE = 0x4
+}SSDVT_MEM_TestType;
+
+typedef struct {
+ ssdvt_uint32_p base_addr; // the begin memory address of xxif
+ ssdvt_uint32 size; // the size of xxif by byte
+ ssdvt_uint32_p sync; // xxif status register
+}SSDVT_MEM_MemInfo;
+
+typedef SSDVT_MEM_MemInfo* SSDVT_MEM_MemInfo_ptr;
+
+typedef void (*SSDVT_MEM_BarrierSyncFun)(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+typedef ssdvt_uint32 (*SSDVT_MEM_TestCaseFun)(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+ssdvt_uint32 SSDVT_MEM_Test();
+
+
+/**
+ * basic test (SRAM base).
+ *
+ * the function would test 0x00000000 and 0xFFFFFFFF.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_basic_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * Full size test (SRAM base).
+ *
+ * the function would write the whole size and check the whole size.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_full_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_half_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/* random test */
+/**
+ * random test.
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_random_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * random test.
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_random_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * random test.
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_random_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/**
+ * Init test (fill with 0x0).
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_init_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+#endif /* __MEMORY_TEST_H__ */
diff --git a/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_header.h b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_header.h
new file mode 100644
index 0000000..97f7106
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_header.h
@@ -0,0 +1,9 @@
+#ifndef __SSDVT_HEADER_H__
+#define __SSDVT_HEADER_H__
+
+#include <stdio.h>
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_util.h"
+
+#endif /* __SSDVT_HEADER_H__ */
diff --git a/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_typedef.h b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_typedef.h
new file mode 100644
index 0000000..847fa22
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_typedef.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * Typedefs.h
+ *
+ * Project:
+ * --------
+ * Device Test
+ *
+ * Description:
+ * ------------
+ * Type definition.
+ *
+ * Author:
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+ /**
+ * @file typedefs.h
+ * @brief this file defines the basic types of SSDVT
+ *
+ */
+#ifndef __SSDVT_TYPEDEF_H__
+#define __SSDVT_TYPEDEF_H__
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef unsigned long int ssdvt_uint32;
+typedef long int ssdvt_int32;
+typedef unsigned short int ssdvt_uint16;
+typedef short int ssdvt_int16;
+typedef unsigned char ssdvt_uint8;
+typedef char ssdvt_int8;
+typedef char ssdvt_char;
+typedef ssdvt_uint32 ssdvt_size_t;
+
+typedef volatile ssdvt_uint8* ssdvt_uint8_p;
+typedef volatile ssdvt_int8* ssdvt_int8_p;
+typedef volatile ssdvt_uint16* ssdvt_uint16_p;
+typedef volatile ssdvt_int16* ssdvt_int16_p;
+typedef volatile ssdvt_uint32* ssdvt_uint32_p;
+typedef volatile ssdvt_int32* ssdvt_int32_p;
+
+#endif /* !__TYPEDEFS_H_ */
+
diff --git a/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_util.h b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_util.h
new file mode 100644
index 0000000..2a143ab
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_util.h
@@ -0,0 +1,106 @@
+#ifndef __SSDVT_UTIL_H__
+#define __SSDVT_UTIL_H__
+
+/*******************************************************************************
+* Included header files
+*******************************************************************************/
+#include "ssdvt_typedef.h"
+
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#define SSDVT_MD32_CHECK (defined(__CORE_BRP__) || defined(__CORE_RAKE__) || defined(__CORE_DFE__))
+
+
+#define NO_DBG /* force to use printf */
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+#if defined(__CORE_BRP__)
+// set base addr
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0x1000 - 0x8)
+#elif defined(__CORE_RAKE__)
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0xC00 - 0x8)
+#elif defined(__CORE_DFE__)
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0x800 - 0x8)
+#else /* __CORE_DFE__ __CORE_RAKE__ __CORE_BRP__ */
+ #error "not support for the md32 processor"
+#endif /* __CORE_DFE__ __CORE_RAKE__ __CORE_BRP__ */
+
+/**
+ * SSDVT_RTLCOSIM_NOTIFICATION_SIZE
+ * - unit: bytes
+ * SSDVT_RTLCOSIMA_STATUS: (*SSDVT_RTLCOSIM_NOTIFICATION_ADDR + 0) : 4 bytes
+ * - 0: Not finish
+ * - 1: Success
+ * - 2: Fail
+ * SSDVT_RTLCOSIM_ERROR_PC: (*SSDVT_RTLCOSIM_NOTIFICATION_ADDR + 4) : 4 bytes
+ * - If test status fails (== 2), the error pc responds the LR
+ */
+#define SSDVT_RTLCOSIM_SIZE 8
+#define SSDVT_RTLCOSIM_STATUS ((volatile ssdvt_uint32 *)(SSDVT_RTLCOSIM_ADDR_BASE+0x0000))
+#define SSDVT_RTLCOSIM_ERROR_PC ((volatile ssdvt_uint32 *)(SSDVT_RTLCOSIM_ADDR_BASE+0x0004))
+#endif /* __MD32S_SSDVT_RTLCOSIM__ */
+
+/*******************************************************************************
+ * Macro
+ *******************************************************************************/
+#define dbg_print(str, args...)
+
+#if !defined(__MD32S_SSDVT_RTLCOSIM__)
+#define ERROR_LOOP \
+ do { \
+ ssdvt_test_fail_notification(); \
+ } while(0);
+
+
+#else /* !__MD32S_SSDVT_RTLCOSIM__ */
+#define ERROR_LOOP \
+ do { \
+ ssdvt_test_fail_notification(); \
+ } while(0);
+#endif /* !__MD32S_SSDVT_RTLCOSIM__ */
+
+#define ERROR_LOOP_MSG(msg) \
+ do { \
+ dbg_print(msg); \
+ ERROR_LOOP \
+ } while(0)
+
+#define SSDVT_ERROR_HANDLER(msg) \
+ do { \
+ while(1); \
+ } while(0)
+
+#define SSDVT_DELAY_LOOP(count) \
+ do { \
+ volatile unsigned int delay; \
+ for (delay = (unsigned int)count; delay != 0; delay--) \
+ /* NOP */ \
+ ; \
+ }while (0)
+
+#define SSDVT_ASSERT_EQ(a, b) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d\n", __FILE__, __LINE__, (a), (b)); \
+ ERROR_LOOP \
+ } \
+ }while(0);
+
+#define SSDVT_ASSERT_EQ_MSG(a, b, msg) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d"msg"\n", __FILE__, __LINE__, (a), (b)); \
+ ERROR_LOOP \
+ } \
+ }while(0);
+
+#define SSDVT_SET_CURRENT_STATUS(status) \
+ do{ \
+ ssdvt_set_current_status((status)); \
+ }while(0)
+
+void ssdvt_set_current_status(ssdvt_uint32 status);
+extern void ssdvt_test_fail_notification();
+extern void ssdvt_test_pass_notification();
+#endif /* __SSDVT_UTIL_H__ */
diff --git a/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_util.h.bak b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_util.h.bak
new file mode 100755
index 0000000..1ffaa7a
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/inc/ssdvt_util.h.bak
@@ -0,0 +1,106 @@
+#ifndef __SSDVT_UTIL_H__
+#define __SSDVT_UTIL_H__
+
+/*******************************************************************************
+* Included header files
+*******************************************************************************/
+#include "ssdvt_typedef.h"
+
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#define SSDVT_MD32_CHECK (defined(__CORE_BRP__) || defined(__CORE_RAKE__) || defined(__CORE_DFE__))
+
+
+#define NO_DBG /* force to use printf */
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+#if defined(__CORE_BRP__)
+// set base addr
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0x1000 - 0x8)
+#elif defined(__CORE_RAKE__)
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0xC00 - 0x8)
+#elif defined(__CORE_DFE__)
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0x800 - 0x8)
+#else /* __CORE_DFE__ __CORE_RAKE__ __CORE_BRP__ */
+ #error "not support for the md32 processor"
+#endif /* __CORE_DFE__ __CORE_RAKE__ __CORE_BRP__ */
+
+/**
+ * SSDVT_RTLCOSIM_NOTIFICATION_SIZE
+ * - unit: bytes
+ * SSDVT_RTLCOSIMA_STATUS: (*SSDVT_RTLCOSIM_NOTIFICATION_ADDR + 0) : 4 bytes
+ * - 0: Not finish
+ * - 1: Success
+ * - 2: Fail
+ * SSDVT_RTLCOSIM_ERROR_PC: (*SSDVT_RTLCOSIM_NOTIFICATION_ADDR + 4) : 4 bytes
+ * - If test status fails (== 2), the error pc responds the LR
+ */
+#define SSDVT_RTLCOSIM_SIZE 8
+#define SSDVT_RTLCOSIM_STATUS ((volatile ssdvt_uint32 *)(SSDVT_RTLCOSIM_ADDR_BASE+0x0000))
+#define SSDVT_RTLCOSIM_ERROR_PC ((volatile ssdvt_uint32 *)(SSDVT_RTLCOSIM_ADDR_BASE+0x0004))
+#endif /* __MD32S_SSDVT_RTLCOSIM__ */
+
+/*******************************************************************************
+ * Macro
+ *******************************************************************************/
+#define dbg_print(str, args...)
+
+#if !defined(__MD32S_SSDVT_RTLCOSIM__)
+#define ERROR_LOOP \
+ do { \
+ ssdvt_test_fail_notification();
+ while(1); \
+ } while(0);
+
+
+#else /* !__MD32S_SSDVT_RTLCOSIM__ */
+#define ERROR_LOOP \
+ do { \
+ while(1); \
+ } while(0);
+#endif /* !__MD32S_SSDVT_RTLCOSIM__ */
+
+#define ERROR_LOOP_MSG(msg) \
+ do { \
+ dbg_print(msg); \
+ ERROR_LOOP \
+ } while(0)
+
+#define SSDVT_ERROR_HANDLER(msg) \
+ do { \
+ while(1); \
+ } while(0)
+
+#define SSDVT_DELAY_LOOP(count) \
+ do { \
+ volatile unsigned int delay; \
+ for (delay = (unsigned int)count; delay != 0; delay--) \
+ /* NOP */ \
+ ; \
+ }while (0)
+
+#define SSDVT_ASSERT_EQ(a, b) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d\n", __FILE__, __LINE__, (a), (b)); \
+ ERROR_LOOP \
+ } \
+ }while(0);
+
+#define SSDVT_ASSERT_EQ_MSG(a, b, msg) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d"msg"\n", __FILE__, __LINE__, (a), (b)); \
+ ERROR_LOOP \
+ } \
+ }while(0);
+
+#define SSDVT_SET_CURRENT_STATUS(status) \
+ do{ \
+ ssdvt_set_current_status((status)); \
+ }while(0)
+
+void ssdvt_set_current_status(ssdvt_uint32 status);
+
+#endif /* __SSDVT_UTIL_H__ */
diff --git a/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test.c b/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test.c
new file mode 100644
index 0000000..08b3c48
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test.c
@@ -0,0 +1,300 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(__SSDVT_CMIF_TEST__)
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+#include "memory_test.h"
+#include "cmif_test.h"
+
+/*******************************************************************************
+* Global vairable
+*******************************************************************************/
+// list all test cases
+SSDVT_MEM_TestCaseFun cmif_test_case[] = {SSDVT_MEM_basic_test_XXIF,
+ SSDVT_MEM_full_size_test_XXIF,
+ SSDVT_MEM_half_size_test_XXIF,
+ SSDVT_MEM_interleave_test_base_8_XXIF,
+ SSDVT_MEM_interleave_test_base_16_XXIF,
+ SSDVT_MEM_interleave_test_base_32_XXIF,
+ SSDVT_MEM_init_test_XXIF,
+ };
+
+ssdvt_uint32 cmif_test_case_size = sizeof(cmif_test_case)/ sizeof(SSDVT_MEM_TestCaseFun);
+ssdvt_uint32 ssdvt_cmif_interrupt_enter = 0xFFFFFFFF;
+ssdvt_uint32 ssdvt_cmif_interrupt_test_case_num;
+
+ssdvt_uint32 ssdvt_cmif_m2c_wfi_interrupt_test_enable = 1;
+
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+extern SSDVT_MEM_TestType ssdvt_mem_test_type;
+extern ssdvt_uint32 ssdvt_mem_test_current_status_base;
+extern ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+
+/*******************************************************************************
+* Function
+*******************************************************************************/
+extern void cmif_test_sync(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+extern void SSDVT_CMIF_InterruptTestInternal_MD32(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+extern void SSDVT_CMIF_InterruptTestInternal_L1CORE(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+
+ssdvt_uint32 cmif_test_internal(ssdvt_uint32 client,
+ const ssdvt_uint32 check_by_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info)
+{
+ // Assume CR4 would initial client with 0.
+ ssdvt_uint32 i;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 1);
+
+ // Start to test
+ dbg_print("cmif test wait for staring...");
+ cmif_test_sync(client, mem_info->sync);
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 2);
+
+ dbg_print("cmif test starts ...");
+ for(i=0; i<cmif_test_case_size; ++i){
+ ssdvt_mem_test_mem_range_num = i + 1;
+ /* Master */
+ SSDVT_CMIF_EXCHANGE_CLIENT_NUMBER(client)
+ (*cmif_test_case[i])(client, check_by_all_client, mem_info, cmif_test_sync, cmif_test_sync);
+
+ /* Slave */
+ SSDVT_CMIF_EXCHANGE_CLIENT_NUMBER(client)
+ (*cmif_test_case[i])(client, check_by_all_client, mem_info, cmif_test_sync, cmif_test_sync);
+ }
+
+ ssdvt_mem_test_mem_range_num = 0x0;
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 3);
+
+ return 0;
+}
+
+void SSDVT_CMIF_RamTest() {
+#if SSDVT_MD32_CHECK
+ /* MD32 side */
+ extern void SSDVT_CMIF_RamTest_MD32();
+ SSDVT_CMIF_RamTest_MD32();
+#else
+ /* CR4 side */
+ extern void SSDVT_CMIF_RamTest_L1CORE();
+ SSDVT_CMIF_RamTest_L1CORE();
+#endif
+}
+
+/*******************************************************************************
+* CMIF Interrupt Test
+*******************************************************************************/
+void SSDVT_CMIF_InterruptTestInternal(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync)
+{
+ // master == 1: send interrupt
+ // master == 0: receive interrupt
+#if SSDVT_MD32_CHECK
+ SSDVT_CMIF_InterruptTestInternal_MD32(master, irq_set, irq_check, sync);
+#else
+ SSDVT_CMIF_InterruptTestInternal_L1CORE(master, irq_set, irq_check, sync);
+#endif
+}
+
+
+void SSDVT_CMIF_InterruptTest()
+{
+#if SSDVT_MD32_CHECK
+ /* MD32 side */
+ extern void SSDVT_CMIF_InterruptTest_MD32();
+ SSDVT_CMIF_InterruptTest_MD32();
+#else
+ /* CR4 side */
+ extern void SSDVT_CMIF_InterruptTest_USIP();
+ SSDVT_CMIF_InterruptTest_USIP();
+#endif
+}
+
+void SSDVT_CMIF_M2CWFIInterruptTest()
+{
+#if SSDVT_MD32_CHECK
+ /* MD32 side */
+ extern void SSDVT_CMIF_M2CWFIInterruptTest_MD32();
+ SSDVT_CMIF_M2CWFIInterruptTest_MD32();
+#else
+ /* CR4 side */
+ extern void SSDVT_CMIF_M2CWFIInterruptTest_L1CORE();
+ SSDVT_CMIF_M2CWFIInterruptTest_L1CORE();
+#endif
+}
+
+void SSDVT_CMIF_TestPreprocess(){
+#if SSDVT_MD32_CHECK
+#if !defined(__CORE_RAKE__)
+ IRQDirectMaskAll();
+#endif /* !__CORE_RAKE__ */
+#endif
+
+#if !SSDVT_MD32_CHECK
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+}
+
+
+void SSDVT_CMIF_TestPostprocess(){
+
+}
+
+
+ssdvt_uint32 SSDVT_CMIF_Test(void)
+{
+ SSDVT_CMIF_TestPreprocess();
+
+ /* Ram test */
+ SSDVT_CMIF_RamTest();
+
+ /* interrupt test*/
+ SSDVT_CMIF_InterruptTest();
+
+ /* M2C WFI Interrupt test case */
+ if(ssdvt_cmif_m2c_wfi_interrupt_test_enable == 1){
+ SSDVT_CMIF_M2CWFIInterruptTest();
+ }
+
+ SSDVT_CMIF_TestPostprocess();
+
+ return 0;
+}
+
+#define SSDVT_CMIF_TEST_SUCCESS_PATTERN 0x39383938
+
+unsigned int ssdvt_cmif_test_success = 0;
+unsigned int ssdvt_cmif_test_enter = 0;
+unsigned int ssdvt_cmif_test_success_while_value = 1;
+
+void SS_MD32_CMIF_TestSuccess(){
+ ssdvt_cmif_test_success = SSDVT_CMIF_TEST_SUCCESS_PATTERN;
+
+ ssdvt_test_pass_notification();
+ while(ssdvt_cmif_test_success_while_value == 1);
+}
+
+void SS_MD32_CMIF_Test(){
+ if(ssdvt_cmif_test_enter == 0x0){
+ ssdvt_cmif_test_enter = 0x1;
+
+ SSDVT_CMIF_Test();
+
+ SS_MD32_CMIF_TestSuccess();
+ }
+}
+#endif /* __SSDVT_CMIF_TEST__ */
+
diff --git a/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test.c.bak b/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test.c.bak
new file mode 100755
index 0000000..cc747e8
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test.c.bak
@@ -0,0 +1,266 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * WS Chao (mtk06215),
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 06 23 2014 ws.chao
+ * [MOLY00070183] [SystemService] MD32-S SSDVT
+ * .
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if (!(SSDVT_MD32_CHECK) || (defined(__SSDVT_CMIF_TEST__) || defined(__SSDVT_MMIF_TEST__)))
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+#include "memory_test.h"
+#include "cmif_test.h"
+
+/*******************************************************************************
+* Global vairable
+*******************************************************************************/
+// list all test cases
+SSDVT_MEM_TestCaseFun cmif_test_case[] = {SSDVT_MEM_basic_test_XXIF,
+ SSDVT_MEM_full_size_test_XXIF,
+ SSDVT_MEM_half_size_test_XXIF,
+ SSDVT_MEM_interleave_test_base_8_XXIF,
+ SSDVT_MEM_interleave_test_base_16_XXIF,
+ SSDVT_MEM_interleave_test_base_32_XXIF,
+ SSDVT_MEM_init_test_XXIF,
+ };
+
+ssdvt_uint32 cmif_test_case_size = sizeof(cmif_test_case)/ sizeof(SSDVT_MEM_TestCaseFun);
+ssdvt_uint32 ssdvt_cmif_interrupt_enter = 0xFFFFFFFF;
+ssdvt_uint32 ssdvt_cmif_interrupt_test_case_num;
+
+ssdvt_uint32 ssdvt_cmif_m2c_wfi_interrupt_test_enable = 1;
+
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+extern SSDVT_MEM_TestType ssdvt_mem_test_type;
+extern ssdvt_uint32 ssdvt_mem_test_current_status_base;
+extern ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+
+/*******************************************************************************
+* Function
+*******************************************************************************/
+extern void cmif_test_sync(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+extern void SSDVT_CMIF_InterruptTestInternal_MD32(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+extern void SSDVT_CMIF_InterruptTestInternal_L1CORE(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+
+ssdvt_uint32 cmif_test_internal(ssdvt_uint32 client,
+ const ssdvt_uint32 check_by_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info)
+{
+ // Assume CR4 would initial client with 0.
+ ssdvt_uint32 i;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 1);
+
+ // Start to test
+ dbg_print("cmif test wait for staring...");
+ cmif_test_sync(client, mem_info->sync);
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 2);
+
+ dbg_print("cmif test starts ...");
+ for(i=0; i<cmif_test_case_size; ++i){
+ /* Master */
+ SSDVT_CMIF_EXCHANGE_CLIENT_NUMBER(client)
+ (*cmif_test_case[i])(client, check_by_all_client, mem_info, cmif_test_sync, cmif_test_sync);
+
+ /* Slave */
+ SSDVT_CMIF_EXCHANGE_CLIENT_NUMBER(client)
+ (*cmif_test_case[i])(client, check_by_all_client, mem_info, cmif_test_sync, cmif_test_sync);
+ }
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 3);
+
+ return 0;
+}
+
+void SSDVT_CMIF_RamTest() {
+#if SSDVT_MD32_CHECK
+ /* MD32 side */
+ extern void SSDVT_CMIF_RamTest_MD32();
+ SSDVT_CMIF_RamTest_MD32();
+#else
+ /* CR4 side */
+ extern void SSDVT_CMIF_RamTest_L1CORE();
+ SSDVT_CMIF_RamTest_L1CORE();
+#endif
+}
+
+/*******************************************************************************
+* CMIF Interrupt Test
+*******************************************************************************/
+void SSDVT_CMIF_InterruptTestInternal(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync)
+{
+ // master == 1: send interrupt
+ // master == 0: receive interrupt
+#if SSDVT_MD32_CHECK
+ SSDVT_CMIF_InterruptTestInternal_MD32(master, irq_set, irq_check, sync);
+#else
+ SSDVT_CMIF_InterruptTestInternal_L1CORE(master, irq_set, irq_check, sync);
+#endif
+}
+
+
+void SSDVT_CMIF_InterruptTest()
+{
+#if SSDVT_MD32_CHECK
+ /* MD32 side */
+ extern void SSDVT_CMIF_InterruptTest_MD32();
+ SSDVT_CMIF_InterruptTest_MD32();
+#else
+ /* CR4 side */
+ extern void SSDVT_CMIF_InterruptTest_L1CORE();
+ SSDVT_CMIF_InterruptTest_L1CORE();
+#endif
+}
+
+void SSDVT_CMIF_M2CWFIInterruptTest()
+{
+#if SSDVT_MD32_CHECK
+ /* MD32 side */
+ extern void SSDVT_CMIF_M2CWFIInterruptTest_MD32();
+ SSDVT_CMIF_M2CWFIInterruptTest_MD32();
+#else
+ /* CR4 side */
+ extern void SSDVT_CMIF_M2CWFIInterruptTest_L1CORE();
+ SSDVT_CMIF_M2CWFIInterruptTest_L1CORE();
+#endif
+}
+
+void SSDVT_CMIF_TestPreprocess(){
+#if SSDVT_MD32_CHECK
+#if !defined(__CORE_RAKE__)
+ IRQDirectMaskAll();
+#endif /* !__CORE_RAKE__ */
+#endif
+
+#if !SSDVT_MD32_CHECK
+ /* Enable md32 clock */
+ (*(volatile ssdvt_uint32*)0xA92B8000) = 0xFFFFFFFF;
+ (*(volatile ssdvt_uint32*)0xA92B8004) = 0xFFFFFFFF;
+ (*(volatile ssdvt_uint32*)0xA92B8008) = 0xFFFFFFFF;
+
+ (*(volatile ssdvt_uint32*)0xA9A00000) = 0xFFFFFFFF;
+
+#endif
+}
+
+
+void SSDVT_CMIF_TestPostprocess(){
+#if !SSDVT_MD32_CHECK
+ extern ssdvt_uint32 SSDVT_CMIF_TEST_BRP_ENABLE;
+ extern ssdvt_uint32 SSDVT_CMIF_TEST_RAKE_ENABLE;
+ if(SSDVT_CMIF_TEST_BRP_ENABLE == 1 && SSDVT_CMIF_TEST_RAKE_ENABLE == 1){
+ /* MMIF help */
+ extern void SSDVT_MMIF_TestMessagePassing();
+ SSDVT_MMIF_TestMessagePassing();
+ }
+#endif
+}
+
+
+ssdvt_uint32 SSDVT_CMIF_Test(void)
+{
+ SSDVT_CMIF_TestPreprocess();
+
+ /* Ram test */
+ //SSDVT_CMIF_RamTest();
+
+ /* interrupt test*/
+ SSDVT_CMIF_InterruptTest();
+
+ /* M2C WFI Interrupt test case */
+ if(ssdvt_cmif_m2c_wfi_interrupt_test_enable == 1){
+ SSDVT_CMIF_M2CWFIInterruptTest();
+ }
+
+ SSDVT_CMIF_TestPostprocess();
+
+ return 0;
+}
+
+#endif /* ((__SSDVT_CMIF_TEST__ || __SSDVT_MMIF_TEST__)) */
+
diff --git a/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test_l1core.c b/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test_l1core.c
new file mode 100644
index 0000000..e2b7e0c
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/src/cmif_test_l1core.c
@@ -0,0 +1,422 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+#include "memory_test.h"
+#include "cmif_test.h"
+#include "intrCtrl.h"
+#include "sync_data.h"
+#include "drv_comm.h"
+#include "dsp_header_define_cmif.h"
+#include "xmif_common_def.h"
+
+
+/*******************************************************************************
+* CR4 only
+*******************************************************************************/
+ssdvt_int32 SSDVT_CMIF_TEST_RAKE_ENABLE = 1;
+
+/* RAKE */
+#define SSDVT_CMIF_CR4_RAKE_SYNC_ADDR ((CMIF_MEM_SS_BASE) + (CMIF_DEF_MEM_TOTAL_SIZE) - (SSDVT_CMIF_SYNC_MEM_SIZE))
+#define SSDVT_CMIF_RAKE_TEST_SIZE ((CMIF_DEF_MEM_TOTAL_SIZE) - (SSDVT_CMIF_SYNC_MEM_SIZE) - (SSDVT_UMIF_SYNC_MEM_SIZE))
+
+/*******************************************************************************
+* Interrrupt Registers
+*******************************************************************************/
+/* CR4 part */
+#define SSDVT_CMIF_M2C_WFI_RAKE_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_WFI_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2C_WFI_RAKE_MASK ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_WFI_RAKE_INTERRUPT_MASK_OFFSET))
+#define SSDVT_CMIF_M2C_WFI_RAKE_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_WFI_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_C2M_U3G_RAKE_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_C2M_U3G_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_C2M_U3G_RAKE_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_C2M_U3G_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_C2M_U3G_RAKE_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_C2M_U3G_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_M2C_U3G_RAKE_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_U3G_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2C_U3G_RAKE_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_U3G_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_M2C_U3G_RAKE_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_U3G_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_M2C_FPC_1X_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_FPC_1X_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2C_FPC_1X_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_FPC_1X_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_M2C_FPC_1X_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_FPC_1X_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_M2C_DO_PD_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_DO_PD_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2C_DO_PD_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_DO_PD_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_M2C_DO_PD_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_DO_PD_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_M2C_FOE_1X_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_FOE_1X_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2C_FOE_1X_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_FOE_1X_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_M2C_FOE_1X_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + CMIF_M2C_FOE_1X_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_U2M_INN_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_U2M_INN_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_U2M_INN_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_U2M_INN_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_U2M_INN_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_U2M_INN_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_M2U_INN_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_M2U_INN_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2U_INN_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_M2U_INN_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_M2U_INN_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_M2U_INN_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_U2M_OUT_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_U2M_OUT_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_U2M_OUT_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_U2M_OUT_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_U2M_OUT_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_U2M_OUT_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_M2U_OUT_STATUS ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_M2U_OUT_RAKE_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CMIF_M2U_OUT_SET ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_M2U_OUT_RAKE_INTERRUPT_SET_OFFSET))
+#define SSDVT_CMIF_M2U_OUT_CLEAN ((volatile ssdvt_uint32*)(CMIF_CTRL_REG_BASE + UMIF_M2U_OUT_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define SSDVT_CMIF_C2M_U3G_RAKE_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_C2M_U3G_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2C_U3G_RAKE_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2C_U3G_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2C_FPC_1X_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2C_FPC_1X_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2C_DO_PD_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2C_DO_PD_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2C_FOE_1X_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2C_FOE_1X_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_U2M_INN_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_U2M_INN_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2U_INN_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2U_INN_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_U2M_OUT_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_U2M_OUT_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2U_OUT_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2U_OUT_CHECK_MEM_OFFSET))
+#define SSDVT_CMIF_M2C_WFI_RAKE_CHECK ((volatile ssdvt_uint32*)(CMIF_MEM_SS_BASE + SSDVT_CMIF_M2C_WFI_CHECK_MEM_OFFSET))
+
+/*******************************************************************************
+* Global variables
+*******************************************************************************/
+/**
+ * define CMIF base address(.base_addr), size(.size) and status register (.sync)
+ */
+// CR4 side
+SSDVT_MEM_MemInfo cmif_cr4_rake = {.base_addr= (ssdvt_uint32_p)CMIF_MEM_SS_BASE,
+ .size= (ssdvt_uint32)SSDVT_CMIF_RAKE_TEST_SIZE,
+ .sync= (ssdvt_uint32_p)SSDVT_CMIF_CR4_RAKE_SYNC_ADDR
+ };
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+extern SSDVT_MEM_TestType ssdvt_mem_test_type;
+extern ssdvt_uint32 ssdvt_mem_test_current_status_base;
+extern ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+extern ssdvt_uint32 ssdvt_cmif_interrupt_test_case_num;
+
+
+/*******************************************************************************
+* Function prototypes
+*******************************************************************************/
+void cmif_test_sync(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+extern ssdvt_uint32 cmif_test_internal(ssdvt_uint32 client,
+ const ssdvt_uint32 check_by_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info);
+
+extern void SSDVT_CMIF_InterruptTestInternal(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+void cmif_test_sync(const ssdvt_uint32 client, const ssdvt_uint32_p sync)
+{
+ // CR4 Part
+ while(sync[1] == 1);
+ sync[1] = 1;
+
+ while(sync[0] == 0);
+ sync[0] = 0;
+}
+
+
+void SSDVT_CMIF_RamTest_L1CORE()
+{
+ ssdvt_mem_test_current_status_base = 0x1000;
+ ssdvt_mem_test_type = SSDVT_MEM_CMIF_TEST_TYPE;
+ ssdvt_mem_test_mem_range_num = 0x0;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base);
+
+ if(SSDVT_CMIF_TEST_RAKE_ENABLE == 1){
+ cmif_test_internal(0, 1, &cmif_cr4_rake);
+ }
+
+ /* reset test type */
+ ssdvt_mem_test_type = SSDVT_MEM_NO_TEST_TYPE;
+ ssdvt_mem_test_current_status_base = 0x0;
+ ssdvt_mem_test_mem_range_num = 0x0;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 0xFF);
+}
+
+/*******************************************************************************
+* CMIF Interrupt Test
+*******************************************************************************/
+
+#define CMIF_REG_READ(addr) *(addr)
+#define CMIF_REG_WRITE(addr, value) do{DRV_WriteReg32(addr, value); MO_Sync();}while(0);
+
+void SSDVT_CMIF_InterruptTestISR_RAKE_U3G()
+{
+ ssdvt_uint32 status;
+ status = CMIF_REG_READ(SSDVT_CMIF_M2C_U3G_RAKE_STATUS);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_U3G_RAKE_CLEAN, status);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_U3G_RAKE_CHECK, SSDVT_CMIF_GET_LSB(status)+1);
+}
+
+void SSDVT_CMIF_InterruptTestISR_FPC_1X()
+{
+ ssdvt_uint32 status;
+ status = CMIF_REG_READ(SSDVT_CMIF_M2C_FPC_1X_STATUS);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_FPC_1X_CLEAN, status);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_FPC_1X_CHECK, SSDVT_CMIF_GET_LSB(status)+1);
+}
+
+void SSDVT_CMIF_InterruptTestISR_DO_PD()
+{
+ ssdvt_uint32 status;
+ status = CMIF_REG_READ(SSDVT_CMIF_M2C_DO_PD_STATUS);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_DO_PD_CLEAN, status);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_DO_PD_CHECK, SSDVT_CMIF_GET_LSB(status)+1);
+}
+
+void SSDVT_CMIF_InterruptTestISR_FOE_1X()
+{
+ ssdvt_uint32 status;
+ status = CMIF_REG_READ(SSDVT_CMIF_M2C_FOE_1X_STATUS);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_FOE_1X_CLEAN, status);
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_FOE_1X_CHECK, SSDVT_CMIF_GET_LSB(status)+1);
+}
+
+#define IRQID_RAKE_CMIF_M2C_IRQ_WFI MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQID_RAKE_CMIF_M2C_IRQ_U3G MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQID_RAKE_CMIF_M2C_IRQ_DO_PD MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+
+void SSDVT_CMIF_InterruptTestRegisterISR_L1CORE()
+{
+ /* CR4 side */
+
+ if(SSDVT_CMIF_TEST_RAKE_ENABLE == 1){
+ // register u3g rake interrupt handler
+ IRQ_Register_LISR(IRQID_RAKE_CMIF_M2C_IRQ_U3G , SSDVT_CMIF_InterruptTestISR_RAKE_U3G, "CMIF_U3G_RAKE");
+ IRQSensitivity(IRQID_RAKE_CMIF_M2C_IRQ_U3G , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_U3G);
+
+ IRQ_Register_LISR(IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X , SSDVT_CMIF_InterruptTestISR_FPC_1X, "CMIF_FPC_1X");
+ IRQSensitivity(IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X);
+
+ IRQ_Register_LISR(IRQID_RAKE_CMIF_M2C_IRQ_DO_PD , SSDVT_CMIF_InterruptTestISR_DO_PD, "CMIF_DO_PD");
+ IRQSensitivity(IRQID_RAKE_CMIF_M2C_IRQ_DO_PD , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_DO_PD);
+
+ IRQ_Register_LISR(IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X , SSDVT_CMIF_InterruptTestISR_FOE_1X, "CMIF_FOE_1X");
+ IRQSensitivity(IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X);
+ }
+}
+
+void SSDVT_CMIF_InterruptTestInternal_L1CORE(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync)
+{
+ // master == 1: send interrupt
+ // master == 0: receive interrupt
+
+ volatile ssdvt_uint32 i;
+ volatile ssdvt_uint32 wait;
+
+ if(master == 1){
+ *(irq_check) = 0xFFFFFFFF;
+
+ // send interrupt
+ for(i=0; i<SSDVT_CMIF_INTERRUPT_SIZE; ++i){
+ SSDVT_SET_CURRENT_STATUS(0xB000 + ssdvt_cmif_interrupt_test_case_num + i);
+ dbg_print(".... send interrupt %d ... ", i);
+
+ // start sync
+ cmif_test_sync(0, sync);
+
+ *(irq_set) = (1 << i);
+
+ wait = SSDVT_CMIF_INTERRUPT_WAIT_LOOP_COUNT;
+ do{
+ wait--;
+ }while(wait != 0 && *(irq_check) != i+1);
+
+ if(*(irq_check) == i+1){
+ dbg_print("success\n");
+ }
+ else{
+ dbg_print("error\n");
+ }
+
+ // end sync
+ cmif_test_sync(0, sync);
+ }
+ }
+ else{
+ // receive interrupt
+ for(i=0; i<SSDVT_CMIF_INTERRUPT_SIZE; ++i){
+ SSDVT_SET_CURRENT_STATUS(0xB000 + ssdvt_cmif_interrupt_test_case_num + i);
+ dbg_print(".... recive interrupt %d ... ", i);
+
+ // start sync
+ cmif_test_sync(0, sync);
+
+ while(*(irq_check) != i+1);
+
+ // check interrupt enter in order
+ SSDVT_ASSERT_EQ(*(irq_check), i+1);
+ dbg_print("success\n");
+
+ // end sync
+ cmif_test_sync(0, sync);
+ }
+ *(irq_check) = 0;
+ }
+}
+
+
+void SSDVT_CMIF_InterruptTest_USIP()
+{
+ // Register ISR
+ SSDVT_CMIF_InterruptTestRegisterISR_L1CORE();
+
+ /* MD32 RAKE */
+ if(SSDVT_CMIF_TEST_RAKE_ENABLE == 1){
+ // send rake u3g interrupt to CR4
+ ssdvt_cmif_interrupt_test_case_num = 0x300;
+ SSDVT_CMIF_InterruptTestInternal(1, SSDVT_CMIF_C2M_U3G_RAKE_SET, SSDVT_CMIF_C2M_U3G_RAKE_CHECK, cmif_cr4_rake.sync);
+
+ // receive rake u3g interrupt from CR4
+ ssdvt_cmif_interrupt_test_case_num = 0x400;
+ SSDVT_CMIF_InterruptTestInternal(0, NULL, SSDVT_CMIF_M2C_U3G_RAKE_CHECK, cmif_cr4_rake.sync);
+
+ // receive rake fpc_1x interrupt from CR4
+ ssdvt_cmif_interrupt_test_case_num = 0x500;
+ SSDVT_CMIF_InterruptTestInternal(0, NULL, SSDVT_CMIF_M2C_FPC_1X_CHECK, cmif_cr4_rake.sync);
+
+ // receive rake do_pd interrupt from CR4
+ ssdvt_cmif_interrupt_test_case_num = 0x600;
+ SSDVT_CMIF_InterruptTestInternal(0, NULL, SSDVT_CMIF_M2C_DO_PD_CHECK, cmif_cr4_rake.sync);
+
+ // receive rake foe_1x interrupt from CR4
+ ssdvt_cmif_interrupt_test_case_num = 0x700;
+ SSDVT_CMIF_InterruptTestInternal(0, NULL, SSDVT_CMIF_M2C_FOE_1X_CHECK, cmif_cr4_rake.sync);
+ }
+}
+
+void SSDVT_CMIF_M2C_WFI_ISR_RAKE(){
+
+ // fill the check status to let l1core and md32 know the test case is pass
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_WFI_RAKE_CHECK, SSDVT_CMIF_M2C_WFI_ISR_CHECK_PATTERN);
+
+ // clean interrupt status
+ CMIF_REG_WRITE(SSDVT_CMIF_M2C_WFI_RAKE_CLEAN, 0x1);
+
+ // send c2m interrupt to to wake up md32
+ CMIF_REG_WRITE(SSDVT_CMIF_C2M_U3G_RAKE_SET, 0x1);
+}
+
+void SSDVT_CMIF_M2CWFIInterruptTestRegisterISR_L1CORE(){
+ // register rake m2c wfi interrupt
+ if(SSDVT_CMIF_TEST_RAKE_ENABLE == 1){
+ IRQ_Register_LISR(IRQID_RAKE_CMIF_M2C_IRQ_WFI, SSDVT_CMIF_M2C_WFI_ISR_RAKE, "CMIF_WFI_RAKE");
+ IRQSensitivity(IRQID_RAKE_CMIF_M2C_IRQ_WFI, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_WFI);
+ }
+}
+
+void SSDVT_CMIF_M2CWFIInterruptTest_L1CORE() {
+ // register m2c wfi interrupt
+ SSDVT_CMIF_M2CWFIInterruptTestRegisterISR_L1CORE();
+
+ // check the rake m2c wfi interrupt
+ if(SSDVT_CMIF_TEST_RAKE_ENABLE == 1){
+ cmif_test_sync(0, cmif_cr4_rake.sync);
+ while(*(SSDVT_CMIF_M2C_WFI_RAKE_CHECK) != SSDVT_CMIF_M2C_WFI_ISR_CHECK_PATTERN) ;
+ }
+}
+
diff --git a/mcu/driver/devdrv/cmif/cmif_test/src/memory_test.c b/mcu/driver/devdrv/cmif/cmif_test/src/memory_test.c
new file mode 100644
index 0000000..1f3ec39
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/src/memory_test.c
@@ -0,0 +1,1674 @@
+#include "ssdvt_header.h"
+#include "ssdvt_typedef.h"
+
+#include "memory_test.h"
+
+#include <stdlib.h>
+
+/*******************************************************************************
+* Macros
+*******************************************************************************/
+#define SSDVT_MEM_RANDOM_TEST_SIZE 128
+#define SSDVT_MEM_RANDOM_TEST_TIMES 1
+
+#define SSDVT_MEM_TEST_BANK2_ALIGIN_ADDR 0x8000
+
+#define SSDVT_MEM_DELAY_LOOP_COUNT 1000
+
+/*******************************************************************************
+* Global variable
+*******************************************************************************/
+SSDVT_MEM_TestType ssdvt_mem_test_type;
+ssdvt_uint32 ssdvt_mem_test_current_status_base;
+ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+
+
+#if !defined(__SIMULATION__)
+/* random test */
+ssdvt_uint32 ssdvt_mem_check_index[SSDVT_MEM_RANDOM_TEST_SIZE]; // check random index
+ssdvt_uint32 ssdvt_mem_check_value[SSDVT_MEM_RANDOM_TEST_SIZE]; // check random value
+ssdvt_uint32 ssdvt_mem_check_test_size;
+#endif /* __SIMULATION__ */
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+
+void write_word_value(const ssdvt_uint32 write_value,
+ const ssdvt_uint32_p x,
+ const ssdvt_uint32 x_size)
+{
+ ssdvt_uint32 i;
+ for(i = 0; i < x_size ; ++i){
+ x[i] = write_value;
+ }
+}
+
+ssdvt_uint32 check_word_value(const ssdvt_uint32 ssdvt_mem_check_value,
+ const ssdvt_uint32_p x,
+ const ssdvt_uint32 x_size)
+{
+ ssdvt_uint32 i;
+ for(i = 0; i < x_size ; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(x[i], ssdvt_mem_check_value);
+ }
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_basic_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync_fun,
+ const SSDVT_MEM_BarrierSyncFun write_sync_fun)
+{
+ /*volatile ssdvt_uint32 i;*/
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 11);
+ /* Write */
+ if(client){
+ write_word_value(0x0, base_32, size_base_32);
+ dbg_print(".... test for 0x0 write \r\n");
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync_fun)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 12);
+ if(check_all_client || !client){
+ dbg_print(".... test for 0x0 read \r\n");
+ check_word_value(0x0, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync_fun)(client, sync);
+ dbg_print("... test for 0x0 success.\r\n");
+
+
+ /** 0xFFFFFFFF*/
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 13);
+ if(client){
+ write_word_value(0xFFFFFFFF, base_32, size_base_32);
+ dbg_print(".... test for 0xFFFFFFFF write \r\n");
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync_fun)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 14);
+ if(check_all_client || !client){
+ dbg_print(".... xxif test for 0xFFFFFFFF read \r\n");
+ check_word_value(0xFFFFFFFF, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync_fun)(client, sync);
+ dbg_print("... mem test for 0xFFFFFFFF success.\r\n");
+
+ dbg_print("... mem basic test: Pass.\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_full_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+
+ volatile ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint16_p base_16 = (ssdvt_uint16_p)xxif->base_addr;
+ const ssdvt_uint8_p base_8 = (ssdvt_uint8_p)xxif->base_addr;
+
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ const ssdvt_uint32 size_base_16 = xxif->size/ sizeof(ssdvt_uint16);
+ const ssdvt_uint32 size_base_8 = xxif->size/ sizeof(ssdvt_uint8);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 pattern_32 = 0;
+ ssdvt_uint16 pattern_16 = 0;
+ ssdvt_uint8 pattern_8 = 0;
+
+
+ /** 0, 1, 2, ... for each byte(1 byte) */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 15);
+ /* Write */
+ if(client){
+ for(i = 0, pattern_8 = 0; i<size_base_8; i++, pattern_8++){
+ base_8[i] = pattern_8;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 16);
+ if(check_all_client || !client){
+ for(i = 0, pattern_8 = 0; i<size_base_8; i++, pattern_8++){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], pattern_8);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0, 1, 2, ... for each byte(1 byte) test success\n");
+
+ /** 0, 1, 2, ... for each half word(2 bytes)*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 17);
+ /* Write */
+ if(client){
+ for(i = 0, pattern_16 = 0; i<size_base_16; i++, pattern_16++){
+ base_16[i] = pattern_16;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 18);
+ if(check_all_client || !client){
+ for(i = 0, pattern_16 = 0; i<size_base_16; i++, pattern_16++){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], pattern_16);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0, 1, 2, ... for each half word(2 bytes) test success\n");
+
+ /** 0, 1, 2, ... for each word(4 bytes)*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 19);
+ /* Write */
+ if(client){
+ for(i = 0, pattern_32 = 0; i<size_base_32; i++, pattern_32++){
+ base_32[i] = pattern_32;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 20);
+ if(check_all_client || !client){
+ for(i = 0, pattern_32 = 0; i<size_base_32; i++, pattern_32++){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], pattern_32);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0, 1, 2, ... for word(4 bytes) test success\n");
+
+ /** 0x5a5a5a5a*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 21);
+ /* Write */
+ if(client){
+ write_word_value(0x5a5a5a5a, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 22);
+ if(check_all_client || !client){
+ check_word_value(0x5a5a5a5a, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x5a5a5a5a test success\n");
+
+ /** 0xa5a5a5a5 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 23);
+ /* Write */
+ if(client){
+ write_word_value(0xa5a5a5a5, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 24);
+ if(check_all_client || !client){
+ check_word_value(0xa5a5a5a5, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa5a5a5a5 test success\n");
+
+ /** 0xa5a5a500 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 25);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 26);
+ if(check_all_client || !client){
+ check_word_value(0xa5a5a500, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa5a5a500 test success\n");
+
+ /** 0xa500a500 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 27);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4+2] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 28);
+ if(check_all_client || !client){
+ check_word_value(0xa500a500, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa500a500 test success\n");
+
+ /** 0xa5000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 29);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4+1] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 30);
+ if(check_all_client || !client){
+ check_word_value(0xa5000000, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa5000000 test success\n");
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 31);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4+3] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 32);
+ if(check_all_client || !client){
+ check_word_value(0x00000000, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x00000000 test success\n");
+
+ /** 0xFFFF0000*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 33);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_16[i*2+1] = 0xFFFF;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+ dbg_print("... 0xFFFF0000 test success\n");
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 34);
+ if(check_all_client || !client){
+ check_word_value(0xFFFF0000, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xFFFF0000 test success\n");
+
+ /** 0xFFFFFFFF*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 35);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_16[i*2] = 0xFFFF;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 36);
+ if(check_all_client || !client){
+ check_word_value(0xFFFFFFFF, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xFFFFFFFF test success\n");
+
+ /** 0x5A for each byte by fibonacci sequence (index: 8, 13, 21, 34 ...) */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 37);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_8; i++){
+ base_8[i] = 0x5A;
+ }
+ for(i=8, j=5; i<size_base_8; k=i, i+=j, j=k){
+ base_8[i] = (ssdvt_uint8)j;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 38);
+ if(check_all_client || !client){
+ for(i=0; i<(ssdvt_uint32)((size_base_8<8)?size_base_8:8); ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x5A);
+ }
+ for(i=8, j=5; i<size_base_8; k=i, i+=j, j=k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], (ssdvt_uint8)j);
+
+ for(k=i+1; k < (i+j) && k < size_base_8; ++k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[k], 0x5A);
+ }
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x5A by fibonacci sequence (index: 8, 13, 21, 34 ...) test success\n");
+
+ /** 0x55AA for each half word by fibonacci sequence (index: 8, 13, 21, 34 ...) */
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 39);
+ if(client){
+ for(i=0; i<size_base_16; i++){
+ base_16[i] = 0x55AA;
+ }
+ for(i=8, j=5; i<size_base_16; k=i, i+=j, j=k){
+ base_16[i] = (ssdvt_uint16)j;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 40);
+ if(check_all_client || !client){
+ for(i=0; i<(ssdvt_uint32)((size_base_16<8)?size_base_16:8); ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x55AA);
+ }
+ for(i=8, j=5; i<size_base_16; k=i, i+=j, j=k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], (ssdvt_uint16)j);
+
+ for(k=i+1; k < (i+j) && k < size_base_16; ++k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[k], 0x55AA);
+ }
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x55AA by fibonacci sequence (index: 8, 13, 21, 34 ...) test success\n");
+
+ /** 0x12345678 for each word by fibonacci sequence (index: 8, 13, 21, 34 ...) */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 41);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; i++){
+ base_32[i] = 0x12345678;
+ }
+ for(i=8, j=5; i<size_base_32; k=i, i+=j, j=k){
+ base_32[i] = (ssdvt_uint32)j;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 42);
+ if(check_all_client || !client){
+ for(i=0; i<(ssdvt_uint32)((size_base_32<8)?size_base_32:8); ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x12345678);
+ }
+ for(i=8, j=5; i<size_base_32; k=i, i+=j, j=k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], (ssdvt_uint32)j);
+
+ for(k=i+1; k < (i+j) && k < size_base_32; ++k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[k], 0x12345678);
+ }
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x12345678 by fibonacci sequence (index: 8, 13, 21, 34 ...) test success\n");
+
+ dbg_print("... full size test: Pass.\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_half_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ /*ssdvt_uint32 i;*/
+
+ const ssdvt_uint32_p base_32 = xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p c1_base_addr = base_32;
+ const ssdvt_uint32 c1_size = size_base_32 / 2;
+ const ssdvt_uint32_p c2_base_addr = base_32 + c1_size;
+ const ssdvt_uint32 c2_size = size_base_32 - c1_size;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 43);
+ /* Write */
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ write_word_value(0x0, c1_base_addr, c1_size);
+ }
+ else{
+ write_word_value(0x0, c2_base_addr, c2_size);
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ write_word_value(0x0, c1_base_addr, c1_size);
+ write_word_value(0x0, c2_base_addr, c2_size);
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 44);
+ check_word_value(0x0, base_32, size_base_32);
+ (*read_sync)(client, sync);
+ dbg_print("... half size: 0x0 + 0x0 test success\n");
+
+ /** 0xFFFFFFFF */
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 45);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ write_word_value(0xFFFFFFFF, c1_base_addr, c1_size);
+ }
+ else{
+ write_word_value(0xFFFFFFFF, c2_base_addr, c2_size);
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ write_word_value(0xFFFFFFFF, c1_base_addr, c1_size);
+ write_word_value(0xFFFFFFFF, c2_base_addr, c2_size);
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 46);
+ check_word_value(0xFFFFFFFF, base_32, size_base_32);
+ (*read_sync)(client, sync);
+ dbg_print("... half size: 0xFFFFFFFF + 0xFFFFFFFF test success\n");
+
+ /** 0xa5a5a5a5 + 0x5a5a5a5a */
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 47);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ write_word_value(0x5a5a5a5a, c1_base_addr, c1_size);
+ }
+ else{
+ write_word_value(0xa5a5a5a5, c2_base_addr, c2_size);
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ write_word_value(0x5a5a5a5a, c1_base_addr, c1_size);
+ write_word_value(0xa5a5a5a5, c2_base_addr, c2_size);
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 48);
+ check_word_value(0x5a5a5a5a, c1_base_addr, c1_size);
+ check_word_value(0xa5a5a5a5, c2_base_addr, c2_size);
+ (*read_sync)(client, sync);
+ dbg_print("... half size: 0x5a5a5a5a + 0xa5a5a5a5 test success\n");
+
+ dbg_print("... half size test: Pass.\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint8_p base_8 = (ssdvt_uint8_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_8 = xxif->size/ sizeof(ssdvt_uint8);
+ ssdvt_uint8 pattern_8 = 0;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** Test for bytes */
+ /** Interleave test for each byte fill with 0x0 */
+ /* Write */
+ /* i: 0 write 0x0 in index 0, 2, 4, ... */
+ /* i: 1 write 0x0 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 49);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+ for(i= 1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 50);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0, ...success\n");
+
+ /** Interlave test for each byte fill with 0xFF */
+ /* Write */
+ /* i: 0 write 0xFF in index 0, 2, 4, ... */
+ /* i: 1 write 0xFF in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 51);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i< size_base_8; i+= 2){
+ base_8[i] = 0xFF;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i< size_base_8; i+= 2){
+ base_8[i] = 0xFF;
+ }
+ for(i= 1; i< size_base_8; i+= 2){
+ base_8[i] = 0xFF;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 52);
+ for(i= 0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0xFF);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0xFF, 0xFF success\n");
+
+ /** Interlave test for each byte fill with 0x5A and 0xA5 */
+ /* Write */
+ /* i: 0 write 0x5A in index 0, 2, 4, ... */
+ /* i: 1 write 0xA5 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 53);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1, pattern_8= (client)?0x5A:0xA5; i< size_base_8; i+=2){
+ base_8[i] = pattern_8;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0, pattern_8= 0x5A; i< size_base_8; i+=2){
+ base_8[i] = pattern_8;
+ }
+ for(i= 1, pattern_8= 0xA5; i< size_base_8; i+=2){
+ base_8[i] = pattern_8;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 54);
+ for(i=0; i< size_base_8; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x5A);
+ }
+ for(i=1; i< size_base_8; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0xA5);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0x5a, 0xa5 success\n");
+
+ /** Interlave test for each byte */
+ /* Write */
+ /* i: 0 write 0, 2, 4, ... in index 0, 2, 4, ... */
+ /* i: 1 write 1, 3, 5, ... in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 55);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_8; i+=2){
+ base_8[i] = (ssdvt_uint8)i;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_8; i+=2){
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for(i= 1; i<size_base_8; i+=2){
+ base_8[i] = (ssdvt_uint8)i;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 56);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], (ssdvt_uint8)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0, 1, 2 ... success\n");
+
+ /* Write in fib seuqences */
+ /* Before fib test, we reset the test memory to zero */
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+ for(i= 1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 50);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("reset the test memory to zero Done\n");
+ /* reset the test memory to zero Done */
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 57);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ for (i= 0; i< (size_base_8<8?size_base_8:8); i++) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ }
+ else{
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_8; ++k){
+ base_8[k] = (ssdvt_uint8)k;
+ }
+ }
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for (i= 0; i< (size_base_8<8?size_base_8:8); i++) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_8; ++k){
+ base_8[k] = (ssdvt_uint8)k;
+ }
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 58);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], (ssdvt_uint8)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: fibonacci sequence success\n");
+
+ dbg_print("... interleave test base 8 bits: Pass.\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint16_p base_16 = (ssdvt_uint16_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_16 = xxif->size/ sizeof(ssdvt_uint16);
+ ssdvt_uint16 pattern_16 = 0;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** Test for bytes */
+ /** Interlave test for each byte fill with 0x0 */
+ /* Write */
+ /* i: 0 write 0x0 in index 0, 2, 4, ... */
+ /* i: 1 write 0x0 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 59);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 60);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0, ...success\n");
+
+ /** Interlave test for each byte fill with 0xFFFF */
+ /* Write */
+ /* i: 0 write 0xFFFF in index 0, 2, 4, ... */
+ /* i: 1 write 0xFFFF in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 61);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = 0xFFFF;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = 0xFFFF;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = 0xFFFF;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 62);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0xFFFF);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0xFFFF, 0xFFFF success\n");
+
+ /** Interlave test for each byte fill with 0x5A and 0xA5 */
+ /* Write */
+ /* i: 0 write 0x5A in index 0, 2, 4, ... */
+ /* i: 1 write 0xA5 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 63);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1, pattern_16= (client)?0x5A5A:0xA5A5; i< size_base_16; i+=2){
+ base_16[i] = pattern_16;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0, pattern_16= 0x5A5A; i< size_base_16; i+=2){
+ base_16[i] = pattern_16;
+ }
+ for(i= 1, pattern_16= 0xA5A5; i< size_base_16; i+=2){
+ base_16[i] = pattern_16;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 64);
+ for(i=0; i< size_base_16; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x5A5A);
+ }
+ for(i=1; i< size_base_16; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0xA5A5);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0x5a5a, 0xa5a5 success\n");
+
+ /** Interlave test for each half word */
+ /* Write */
+ /* i: 0 write 0, 2, 4, ... in index 0, 2, 4, ... */
+ /* i: 1 write 1, 3, 5, ... in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 65);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = (ssdvt_uint16)i;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = (ssdvt_uint16)i;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 66);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], (ssdvt_uint16)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0, 1, 2 ... success\n");
+
+ /* Write in fib seuqences */
+ /* Before test fib sequence, reset the test memory */
+ #if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 60);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("Reset test memory done\n");
+ /* Reset test memory done */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 67);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ for (i= 0; i< (size_base_16<8?size_base_16:8); i++) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ }
+ else{
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_16; ++k){
+ base_16[k] = (ssdvt_uint16)k;
+ }
+ }
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for (i= 0; i< (size_base_16<8?size_base_16:8); i++) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_16; ++k){
+ base_16[k] = (ssdvt_uint16)k;
+ }
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 68);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], (ssdvt_uint16)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: fibonacci sequence success\n");
+
+ dbg_print("... interleave test base 16 bits: Pass.\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ ssdvt_uint32 pattern_32 = 0;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** Test for bytes */
+ /** Interleave test for each byte fill with 0x0 */
+ /* Write */
+ /* i: 0 write 0x0 in index 0, 2, 4, ... */
+ /* i: 1 write 0x0 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 69);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 70);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: 0, ...success\n");
+
+ /** Interleave test for each byte fill with 0xFFFFFFFF */
+ /* Write */
+ /* i: 0 write 0xFFFFFFFF in index 0, 2, 4, ... */
+ /* i: 1 write 0xFFFFFFFF in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 71);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = 0xFFFFFFFF;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = 0xFFFFFFFF;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = 0xFFFFFFFF;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 72);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0xFFFFFFFF);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: 0xFFFFFFFF, 0xFFFFFFFF success\n");
+
+ /** Interlave test for each byte fill with 0x5A and 0xA5 */
+ /* Write */
+ /* i: 0 write 0x5A5A5A5A in index 0, 2, 4, ... */
+ /* i: 1 write 0xA5A5A5A5 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 73);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1, pattern_32= (client)?0x5A5A5A5A:0xA5A5A5A5; i< size_base_32; i+=2){
+ base_32[i] = pattern_32;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0, pattern_32= 0x5A5A5A5A; i< size_base_32; i+=2){
+ base_32[i] = pattern_32;
+ }
+ for(i= 1, pattern_32= 0xA5A5A5A5; i< size_base_32; i+=2){
+ base_32[i] = pattern_32;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 74);
+ for(i=0; i< size_base_32; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x5A5A5A5A);
+ }
+ for(i=1; i< size_base_32; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0xA5A5A5A5);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0x5a5a5a5a, 0xa5a5a5a5 success\n");
+
+ /** Interlave test for each half word */
+ /* Write */
+ /* i: 0 write 0, 2, 4, ... in index 0, 2, 4, ... */
+ /* i: 1 write 1, 3, 5, ... in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 75);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = (ssdvt_uint32)i;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = (ssdvt_uint32)i;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 76);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], (ssdvt_uint32)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: 0, 1, 2 ... success\n");
+
+ /* Write in fib sequences */
+ /* Before test, reset test memory */
+ #if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 70);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("Reset test memory done\n");
+ /* Reset test memory done */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 77);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ for (i= 0; i< (size_base_32<8?size_base_32:8); i++) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ }
+ else{
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_32; ++k){
+ base_32[k] = (ssdvt_uint32)k;
+ }
+ }
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for (i= 0; i< (size_base_32<8?size_base_32:8); i++) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_32; ++k){
+ base_32[k] = (ssdvt_uint32)k;
+ }
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 78);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], (ssdvt_uint32)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: fibonacci sequence success\n");
+
+ dbg_print("... interleave test base 32 bits: Pass.\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_random_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ volatile ssdvt_uint32 i, j;
+ ssdvt_uint32 times;
+
+ const ssdvt_uint8_p base_8 = (ssdvt_uint8_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_8 = xxif->size/ sizeof(ssdvt_uint8);
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 ridx[SSDVT_MEM_RANDOM_TEST_SIZE]; // random index
+ ssdvt_uint8 rvalue[SSDVT_MEM_RANDOM_TEST_SIZE]; // random value
+ ssdvt_uint32 random_test_size = (SSDVT_MEM_RANDOM_TEST_SIZE > size_base_32)? size_base_32: SSDVT_MEM_RANDOM_TEST_SIZE;
+
+ ssdvt_uint32 sidx;
+
+ for(times = 0; times < SSDVT_MEM_RANDOM_TEST_TIMES; ++times){
+ dbg_print("... 8 byte random test %u/%u:\n", times+1, SSDVT_MEM_RANDOM_TEST_TIMES);
+
+ /* Generator index */
+ for(i=0; i< random_test_size; i++){
+ ridx[i] = (rand()+1) % size_base_8;
+ }
+
+ /* Generate value */
+ for(i=0; i< random_test_size; i++){
+ rvalue[i] = (ssdvt_uint8)(rand()+1);
+ }
+
+
+ /* Random Test */
+ /**
+ * Step 1: Send index
+ * Step 2: Send value
+ * Step 3: Check the index and the value
+ **/
+ /* Send index*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 79);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = ridx[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive index */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 80);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ ridx[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Send value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 81);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_8[i] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 82);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ rvalue[i] = base_8[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Random write with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 83);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_8[ridx[i]] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 84);
+ if(check_all_client || !client){
+ /* Generate golden pattern */
+ for(i=0, ssdvt_mem_check_test_size = 0; i<random_test_size; ++i){
+ sidx = i;
+ for(j=0; j<ssdvt_mem_check_test_size; j++){
+ if(ssdvt_mem_check_index[j] == ridx[i]){
+ sidx = j;
+ break;
+ }
+ }
+ if(j == ssdvt_mem_check_test_size){
+ sidx = ssdvt_mem_check_test_size;
+ ssdvt_mem_check_test_size++;
+
+ ssdvt_mem_check_index[sidx] = ridx[i];
+ }
+ ssdvt_mem_check_value[sidx] = rvalue[i];
+ }
+
+ /* check */
+ for(i=0; i<ssdvt_mem_check_test_size; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[ssdvt_mem_check_index[i]], ssdvt_mem_check_value[i]);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ }
+ dbg_print("... memory random test (1 byte) success\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_random_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ volatile ssdvt_uint32 i, j;
+ ssdvt_uint32 times;
+
+ const ssdvt_uint16_p base_16 = (ssdvt_uint16_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_16 = xxif->size/ sizeof(ssdvt_uint16);
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 ridx[SSDVT_MEM_RANDOM_TEST_SIZE]; // random index
+ ssdvt_uint16 rvalue[SSDVT_MEM_RANDOM_TEST_SIZE]; // random value
+ ssdvt_uint32 random_test_size = (SSDVT_MEM_RANDOM_TEST_SIZE > size_base_32)? size_base_32: SSDVT_MEM_RANDOM_TEST_SIZE;
+
+ ssdvt_uint32 sidx;
+
+ srand(91);
+ for(times = 0; times < SSDVT_MEM_RANDOM_TEST_TIMES; ++times){
+ dbg_print("... 16 byte random test %u/%u:\n", times+1, SSDVT_MEM_RANDOM_TEST_TIMES);
+
+ /* Generatr index */
+ for(i=0; i< random_test_size; i++){
+ ridx[i] = (rand() + 1)%size_base_16;
+ }
+
+ /* Generate value */
+ for(i=0; i< random_test_size; i++){
+ rvalue[i] = (ssdvt_uint16)(rand()+1);
+ }
+
+ /* Random Test */
+ /**
+ * Step 1: Send index
+ * Step 2: Send value
+ * Step 3: Check the index and the value
+ **/
+ /* Send index*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 85);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = ridx[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive index */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 86);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ ridx[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Send value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 87);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_16[i] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 88);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ rvalue[i] = base_16[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Random write with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 89);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_16[ridx[i]] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 90);
+ if(check_all_client || !client){
+ /* Generate golden pattern */
+ for(i=0, ssdvt_mem_check_test_size = 0; i<random_test_size; ++i){
+ sidx = i;
+ for(j=0; j<ssdvt_mem_check_test_size; j++){
+ if(ssdvt_mem_check_index[j] == ridx[i]){
+ sidx = j;
+ break;
+ }
+ }
+ if(j == ssdvt_mem_check_test_size){
+ sidx = ssdvt_mem_check_test_size;
+ ssdvt_mem_check_test_size++;
+
+ ssdvt_mem_check_index[sidx] = ridx[i];
+ }
+ ssdvt_mem_check_value[sidx] = rvalue[i];
+ }
+
+ /* check */
+ for(i=0; i<ssdvt_mem_check_test_size; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[ssdvt_mem_check_index[i]], ssdvt_mem_check_value[i]);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ }
+ dbg_print("... memory random test (2 bytes) success\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_random_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ volatile ssdvt_uint32 i, j;
+ ssdvt_uint32 times;
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 ridx[SSDVT_MEM_RANDOM_TEST_SIZE]; // random index
+ ssdvt_uint32 rvalue[SSDVT_MEM_RANDOM_TEST_SIZE]; // random value
+ ssdvt_uint32 random_test_size = (SSDVT_MEM_RANDOM_TEST_SIZE > size_base_32)? size_base_32: SSDVT_MEM_RANDOM_TEST_SIZE;
+
+ ssdvt_uint32 sidx;
+
+ for(times = 0; times < SSDVT_MEM_RANDOM_TEST_TIMES; ++times){
+ dbg_print("... 32 byte random test %u/%u:\n", times+1, SSDVT_MEM_RANDOM_TEST_TIMES);
+
+ /* Generatr index */
+ for(i=0; i< random_test_size; i++){
+ ridx[i] = (rand() + 1) % size_base_32;
+ }
+
+ /* Generate value */
+ for(i=0; i< random_test_size; i++){
+ rvalue[i] = (ssdvt_uint32)(rand()+1);
+ }
+
+
+ /* Random Test */
+ /**
+ * Step 1: Send index
+ * Step 2: Send value
+ * Step 3: Check the index and the value
+ **/
+ /* Send index*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 91);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = ridx[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive index */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 92);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ ridx[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Send value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 93);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 94);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ rvalue[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Random write with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 95);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[ridx[i]] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 96);
+ if(check_all_client || !client){
+ /* Generate golden pattern */
+ for(i=0, ssdvt_mem_check_test_size = 0; i<random_test_size; ++i){
+ sidx = i;
+ for(j=0; j<ssdvt_mem_check_test_size; j++){
+ if(ssdvt_mem_check_index[j] == ridx[i]){
+ sidx = j;
+ break;
+ }
+ }
+ if(j == ssdvt_mem_check_test_size){
+ sidx = ssdvt_mem_check_test_size;
+ ssdvt_mem_check_test_size++;
+
+ ssdvt_mem_check_index[sidx] = ridx[i];
+ }
+ ssdvt_mem_check_value[sidx] = rvalue[i];
+ }
+
+ /* check */
+ for(i=0; i<ssdvt_mem_check_test_size; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[ssdvt_mem_check_index[i]], ssdvt_mem_check_value[i]);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ }
+ dbg_print("... memory random test (4 bytes) success\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_init_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ /*volatile ssdvt_uint32 i;*/
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 97);
+ /* Write */
+ if(client){
+ write_word_value(0x0, base_32, size_base_32);
+ dbg_print("... test init for 0x0 write\r\n");
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 98);
+ if(check_all_client || !client){
+ dbg_print("... test init for 0x0 read \r\n");
+ check_word_value(0x0, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... test init for 0x0 success \r\n");
+
+ return 0;
+}
+
+void SSDVT_MEM_EmptySync(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync)
+{
+}
+
+ssdvt_uint32 SSDVT_MEM_full_size_test(const SSDVT_MEM_MemInfo_ptr mem_info)
+{
+ return SSDVT_MEM_full_size_test_XXIF(1, 1, mem_info, SSDVT_MEM_EmptySync, SSDVT_MEM_EmptySync);
+}
+
+ssdvt_uint32 SSDVT_MEM_basic_test(const SSDVT_MEM_MemInfo_ptr mem_info)
+{
+ return SSDVT_MEM_basic_test_XXIF(1, 1, mem_info, SSDVT_MEM_EmptySync, SSDVT_MEM_EmptySync);
+}
+
+
diff --git a/mcu/driver/devdrv/cmif/cmif_test/src/ssdvt_util.c b/mcu/driver/devdrv/cmif/cmif_test/src/ssdvt_util.c
new file mode 100644
index 0000000..b070bd2
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/cmif_test/src/ssdvt_util.c
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#if defined(__SIMULATION__)
+#define SYSREG_PASS ((volatile ssdvt_uint32 *)(0xe0000004))
+#define SYSREG_FAIL ((volatile ssdvt_uint32 *)(0xe0000008))
+#endif
+
+#define SSDVT_GET_VIC_VEC() SCU_IO_READ(VIC_VEC)
+
+/*******************************************************************************
+ * Global Variable
+ *******************************************************************************/
+ssdvt_uint32 ssdvt_stored_stack_pointer;
+ssdvt_uint32 ssdvt_stored_return_address;
+ssdvt_uint32 ssdvt_current_status;
+
+/*******************************************************************************
+ * Functions
+ *******************************************************************************/
+void ssdvt_test_fail_notification()
+{
+#if defined(__SIMULATION__)
+ *SYSREG_FAIL = 0xDEAD;
+#endif
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+ *SSDVT_RTLCOSIM_ERROR_PC = ssdvt_stored_return_address;
+ *SSDVT_RTLCOSIM_STATUS = 2;
+#endif
+
+ while(1);
+}
+
+void ssdvt_test_pass_notification()
+{
+#if defined(__SIMULATION__)
+ *SYSREG_PASS = 0xABBA;
+#endif
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+ *SSDVT_RTLCOSIM_STATUS = 1;
+#endif
+
+ while(1);
+}
+
+void ssdvt_set_current_status(ssdvt_uint32 status)
+{
+ ssdvt_current_status = status;
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+ *SSDVT_RTLCOSIM_ERROR_PC = status;
+#endif
+}
+
diff --git a/mcu/driver/devdrv/cmif/inc/drv_cmif_l1core.h b/mcu/driver/devdrv/cmif/inc/drv_cmif_l1core.h
new file mode 100644
index 0000000..cf522a1
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/inc/drv_cmif_l1core.h
@@ -0,0 +1,384 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cmif.h
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DRV_CMIF_L1CORE_H__
+#define __DRV_CMIF_L1CORE_H__
+
+#include "drv_cmif.h"
+
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+#include "sync_data.h"
+#include "drv_comm.h"
+
+#define __CMIF_DEBUG__
+
+/*******************************************************************************
+ * Register List
+ *******************************************************************************/
+
+// mcu
+#define CMIF_C2M_U3G_RAKE_STATUS ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_C2M_U3G_RAKE_INTERRUPT_STATUS_OFFSET))
+#define CMIF_C2M_U3G_RAKE_SET ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_C2M_U3G_RAKE_INTERRUPT_SET_OFFSET))
+#define CMIF_M2C_U3G_RAKE_STATUS ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_U3G_RAKE_INTERRUPT_STATUS_OFFSET))
+#define CMIF_M2C_U3G_RAKE_CLEAN ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_U3G_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define CMIF_M2C_FPC_1X_STATUS ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_FPC_1X_RAKE_INTERRUPT_STATUS_OFFSET))
+#define CMIF_M2C_FPC_1X_CLEAN ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_FPC_1X_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define CMIF_M2C_DO_PD_STATUS ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_DO_PD_RAKE_INTERRUPT_STATUS_OFFSET))
+#define CMIF_M2C_DO_PD_CLEAN ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_DO_PD_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+#define CMIF_M2C_FOE_1X_STATUS ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_FOE_1X_RAKE_INTERRUPT_STATUS_OFFSET))
+#define CMIF_M2C_FOE_1X_CLEAN ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_M2C_FOE_1X_RAKE_INTERRUPT_CLEAN_OFFSET))
+
+
+#define CMIF_NEXT_INT_OFFSET (CMIF_M2C_FPC_1X_RAKE_INTERRUPT_STATUS_OFFSET - CMIF_M2C_U3G_RAKE_INTERRUPT_STATUS_OFFSET)
+
+/*******************************************************************************
+ * CMIF Memory Definition
+ *******************************************************************************/
+
+/* MCU side */
+#define CMIF_CR4_RAKE_BASE_ADDR (BASE_MADDR_RAKESYS_CMIF)
+
+
+#define IRQID_RAKE_CMIF_M2C_IRQ_U3G (MD_IRQID_RAKE_CMIF_M2C_IRQ_1)
+#define IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X (MD_IRQID_RAKE_CMIF_FPC_1X_IRQ)
+#define IRQID_RAKE_CMIF_M2C_IRQ_DO_PD (MD_IRQID_RAKE_CMIF_PD_DO_IRQ)
+#define IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X (MD_IRQID_RAKE_CMIF_FOE_1X_IRQ)
+
+#if defined(__MD93__)
+#define CMIF_VPE_NUM (4)
+#elif defined(__MD95__)
+#define CMIF_VPE_NUM (6)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CMIF_VPE_NUM (12)
+#else
+#error "undefined platform"
+#endif
+
+/*******************************************************************************
+ * Typedefs & Macros
+ *******************************************************************************/
+
+
+#define CMIF_REG_READ(addr) *(addr)
+#define CMIF_REG_WRITE(addr, value) do{DRV_WriteReg32(addr, value); MO_Sync();}while(0);
+
+
+#define CMIF_NULL NULL
+#define CMIF_ASSERT(expr, c1, c2, c3) EXT_ASSERT(expr, c1, c2, c3)
+#define CMIF_GET_RETURN_ADDRESS(a) GET_RETURN_ADDRESS(a)
+
+#define CMIF_CLZ(z) __builtin_clz((z))
+#define CMIF_GET_LSB(b) (31 - CMIF_CLZ((b) & -(b)))
+
+
+/* cmif overflow debug info */
+typedef struct{
+ cmif_uint32 time; /**< The calling timestamp */
+ cmif_uint32 interrupt_bit; /**< The overflow bit */
+ cmif_uint32 status_addr; /**< The addr of the status register */
+ cmif_uint32 current_status;/**< The current value of the status register */
+ cmif_uint32 caller; /**< The caller address */
+}CMIF_OverFlowRecord;
+
+/*******************************************************************************
+ * Debug feature
+ *******************************************************************************/
+#if defined(__CMIF_DEBUG__)
+
+#if __CMIF_MD32S_CORE__
+/* MD32 side */
+#define CMIF_DEBUG_API_RECORD_SIZE 8
+#define CMIF_DEBUG_ISR_HANDLE_CODE_SIZE 8
+
+#else /* __CMIF_MD32S_CORE__ */
+
+#define CMIF_DEBUG_API_RECORD_SIZE 16
+#define CMIF_DEBUG_ISR_HANDLE_CODE_SIZE 16
+
+#endif /* __CMIF_MD32S_CORE__ */
+
+
+typedef enum CMIF_DebugInterrupt_enum{
+ CMIF_DEBUG_U3G_INTERRUPT,
+ CMIF_DEBUG_FPC_1X_INTERRUPT,
+ CMIF_DEBUG_DO_PD_INTERRUPT,
+ CMIF_DEBUG_FOE_1X_INTERRUPT
+}CMIF_DebugInterruptType;
+
+typedef struct{
+ cmif_uint32 time;
+ cmif_uint32 code;
+}CMIF_DebugISRRecord;
+
+/** The Ring Buffer */
+typedef struct{
+ CMIF_DebugISRRecord records[CMIF_DEBUG_ISR_HANDLE_CODE_SIZE];
+ cmif_uint32 top_index;
+}CMIF_DebugISRCodeList;
+
+typedef struct{
+ cmif_uint32 time;
+ cmif_uint32 status;
+ cmif_uint32 set_addr; /**< The control register address */
+ cmif_uint32 set_value; /**< The writing value for the control regsiters */
+ cmif_uint32 caller; /**< The caller address */
+}CMIF_DebugRecord;
+
+/** The Ring Buffer */
+typedef struct{
+ CMIF_DebugRecord records[CMIF_DEBUG_API_RECORD_SIZE];
+ kal_atomic_uint32 top_index;
+}CMIF_DebugRecordList;
+
+void cmif_DebugAddRecord(cmif_uint32 status,
+ cmif_uint32 set_addr,
+ cmif_uint32 set_value,
+ cmif_uint32 caller);
+
+void cmif_DebugAddISRHandle(cmif_uint32 code, CMIF_DebugInterruptType isr_type);
+
+
+#endif /* __CMIF_DEBUG__ */
+
+
+
+
+
+#if defined(__MD32S_CMIF_DRV_TEST__)
+
+#define CMIF_MEM_TOTAL_SIZE 0x2000
+
+#define CMIF_DRV_TEST_SYNC_ADDR ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_MEM_TOTAL_SIZE - 8))
+
+
+typedef void (*CMIF_Status_Func_t)(CMIF_Mask_t* mask);
+typedef void (*CMIF_SWI_Func_t)(cmif_uint8 code);
+typedef void (*CMIF_EOI_Func_t)(cmif_uint8 code);
+
+typedef struct{
+ volatile cmif_uint32* send_set;
+ volatile cmif_uint32* send_status;
+ volatile cmif_uint32* receive_clr;
+ volatile cmif_uint32* receive_status;
+ volatile cmif_uint32* sync;
+
+ CMIF_SWI_Func_t send_func;
+ CMIF_Status_Func_t send_stats_func;
+ CMIF_EOI_Func_t receive_clr_func;
+ CMIF_Status_Func_t receive_stats_func;
+
+}CMIF_Ctrl_t;
+
+void CMIF_DriverTestISR_U3G(CMIF_Mask_t* mask);
+void CMIF_DriverTestISR_FPC_1X(CMIF_Mask_t* mask);
+void CMIF_DriverTestISR_DO_PD(CMIF_Mask_t* mask);
+void CMIF_DriverTestISR_FOE_1X(CMIF_Mask_t* mask);
+
+#endif /* __MD32S_CMIF_DRV_TEST__ */
+
+#endif /* __DRV_CMIF_L1CORE_H__ */
+
diff --git a/mcu/driver/devdrv/cmif/mem_access_path_test/inc/mem_access_path_test.h b/mcu/driver/devdrv/cmif/mem_access_path_test/inc/mem_access_path_test.h
new file mode 100644
index 0000000..a7c5fe7
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/mem_access_path_test/inc/mem_access_path_test.h
@@ -0,0 +1,110 @@
+#ifndef __MEM_ACCESS_PATH_TEST_USIP_H__
+#define __MEM_ACCESS_PATH_TEST_USIP_H__
+
+#if defined(MT6763) || defined(MT6739) || defined(MT6771) || defined(MT6765) || defined(MT6761)
+ #if defined(MT6763) || defined(MT6771) || defined(MT6765) || defined(MT6761)
+ #define usip0_itcm_size (0xe000)
+ #elif defined(MT6739)
+ #define usip0_itcm_size (0x18000)
+ #else
+ #error "no configuration for this project!\n"
+ #endif
+
+ #if defined(MT6763) || defined(MT6739) || defined(MT6771) || defined(MT6765) || defined(MT6761)
+ // usip
+ #define usip0_itcm_base (0xA1000000)
+
+ #define usip1_itcm_base (0xA1100000)
+ #define usip1_itcm_size (0xb000)
+
+
+ #define usip0_dtcm_base (0xA1040000)
+ #define usip0_dtcm_size (0xb000)
+
+ #define usip1_dtcm_base (0xA1140000)
+ #define usip1_dtcm_size (0xa000)
+
+ // scq16
+ #define SHARE_PM_base (0xA9800000)
+ #define share_pm_size (0x30000)
+
+ #define SHARE_DM_base (0xA9A00000)
+ #define share_dm_size (0x10000)
+
+ #define PRIVATE_DM0_base (0xAA200000)
+ #define PRIVATE_DM1_base (0xAA600000)
+
+ #define local_dm_size (0x2000)
+
+ // rake
+ #define rake_pm_base (0xac380000)
+ #define rake_pm_size (0x18000)
+
+ #define rake_dm_base (0xac3e0000)
+ #define rake_dm_size (0xc000)
+ #endif
+
+#elif defined(MT6295M) || defined(MT3967) || defined(MT6779)
+ // usip
+ #define usip0_itcm_base (0xA1000000)
+ #define usip0_itcm_size (0x20000)
+ #define usip0_dtcm_base (0xA1040000)
+ #define usip0_dtcm_size (0x14000)
+ #define usip0_l2tcm_base (0xA1400000)
+ #define usip0_l2tcm_size (0x20000)
+
+ #define usip1_itcm_base (0xA1100000)
+ #define usip1_itcm_size (0xE000)
+ #define usip1_dtcm_base (0xA1140000)
+ #define usip1_dtcm_size (0x7C00)
+
+
+ // scq16
+ #define SHARE_PM_base (0xA9800000)
+ #define share_pm_size (0x30000)
+
+ #define SHARE_DM_base (0xA9A00000)
+ #define share_dm_size (0x10000)
+
+ #define PRIVATE_DM0_base (0xAA200000)
+ #define PRIVATE_DM1_base (0xAA600000)
+
+ #define local_dm_size (0x2000)
+
+ // rake
+ #define rake_pm_base (0xac380000)
+ #define rake_pm_size (0x18000)
+
+ #define rake_dm_base (0xac3e0000)
+ #define rake_dm_size (0xc000)
+
+#else
+ #error "no configuration for this project!\n"
+#endif
+
+
+#define access_path_test_size 0x800
+
+// usip
+#define usip0_itcm_end (usip0_itcm_base + usip0_itcm_size)
+#define usip0_dtcm_end (usip0_dtcm_base + usip0_dtcm_size)
+#define usip0_l2tcm_end (usip0_l2tcm_base + usip0_l2tcm_size)
+
+#define usip1_itcm_end (usip1_itcm_base + usip1_itcm_size)
+#define usip1_dtcm_end (usip1_dtcm_base + usip1_dtcm_size)
+
+// scq16
+#define share_pm_end (SHARE_PM_base + share_pm_size)
+#define share_dm_end (SHARE_DM_base + share_dm_size)
+
+
+#define PRIVATE_DM0_end (PRIVATE_DM0_base + local_dm_size)
+#define PRIVATE_DM1_end (PRIVATE_DM1_base + local_dm_size)
+
+// rake
+#define rake_pm_end (rake_pm_base + rake_pm_size)
+#define rake_dm_end (rake_dm_base + rake_dm_size)
+
+extern void SSDVT_MEM_ACCESS_PATH_TEST(void);
+
+#endif //__MEM_ACCESS_PATH_TEST_USIP_H__
diff --git a/mcu/driver/devdrv/cmif/mem_access_path_test/src/mem_access_path_test.c b/mcu/driver/devdrv/cmif/mem_access_path_test/src/mem_access_path_test.c
new file mode 100644
index 0000000..639329d
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/mem_access_path_test/src/mem_access_path_test.c
@@ -0,0 +1,139 @@
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+#include "memory_test.h"
+#include "mem_access_path_test.h"
+
+
+/*******************************************************************************
+* Global variables
+*******************************************************************************/
+
+
+
+
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+extern SSDVT_MEM_TestType ssdvt_mem_test_type;
+extern ssdvt_uint32 ssdvt_mem_test_current_status_base;
+extern ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+
+/*******************************************************************************
+* Function prototypes
+*******************************************************************************/
+extern ssdvt_uint32 SSDVT_MEM_basic_test(const SSDVT_MEM_MemInfo_ptr mem_info);
+extern ssdvt_uint32 SSDVT_MEM_full_size_test(const SSDVT_MEM_MemInfo_ptr mem_info);
+extern void ssdvt_test_pass_notification();
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+
+void SSDVT_MEM_ACCESS_PATH_TEST()
+{
+ /* set test type */
+ dbg_print("Memory Access Path Test : start running\n");
+
+ ssdvt_mem_test_current_status_base = 0xE000;
+ ssdvt_mem_test_type = SSDVT_MEM_MD32_TEST_TYPE;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base);
+
+ typedef ssdvt_uint32 (*SSDVT_MEM_TestSingle)(const SSDVT_MEM_MemInfo_ptr mem_info);
+
+ ssdvt_uint32 i;
+ ssdvt_uint32 midx;
+
+ SSDVT_MEM_TestSingle mem_test_case[] = {
+ SSDVT_MEM_basic_test,
+ SSDVT_MEM_full_size_test,
+ };
+ ssdvt_uint32 mem_test_case_size = sizeof(mem_test_case)/ sizeof(SSDVT_MEM_TestSingle);
+
+
+ /* set memory */
+ SSDVT_MEM_MemInfo mem_info[] = {
+ // [MUST]share pm have to be 0/1 case
+ // share pm begin
+ {(ssdvt_uint32_p)SHARE_PM_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // share pm end
+ {(ssdvt_uint32_p)(share_pm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+#if defined(MT6295M) || defined(MT3967)
+ // usip0 l2tcm begin
+ {(ssdvt_uint32_p)usip0_l2tcm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip0 l2tcm end
+ {(ssdvt_uint32_p)(usip0_l2tcm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+#endif
+ // usip0 itcm begin
+ {(ssdvt_uint32_p)usip0_itcm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip0 itcm end
+ {(ssdvt_uint32_p)(usip0_itcm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip1 itcm begin
+ {(ssdvt_uint32_p)usip1_itcm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip1 itcm end
+ {(ssdvt_uint32_p)(usip1_itcm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip0 dtcm begin
+ {(ssdvt_uint32_p)usip0_dtcm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip0 dtcm end
+ {(ssdvt_uint32_p)(usip0_dtcm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip1 dtcm begin
+ {(ssdvt_uint32_p)usip1_dtcm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // usip1 dtcm end
+ {(ssdvt_uint32_p)(usip1_dtcm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // share dm begin
+ {(ssdvt_uint32_p)SHARE_DM_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // share dm end
+ {(ssdvt_uint32_p)(share_dm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // private dm0 begin
+ {(ssdvt_uint32_p)PRIVATE_DM0_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // private dm0 end
+ {(ssdvt_uint32_p)(PRIVATE_DM0_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // private dm1 begin
+ {(ssdvt_uint32_p)PRIVATE_DM1_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // private dm1 end
+ {(ssdvt_uint32_p)(PRIVATE_DM1_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // rake pm begin
+ {(ssdvt_uint32_p)rake_pm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // rake pm end
+ {(ssdvt_uint32_p)(rake_pm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // rake dm begin
+ {(ssdvt_uint32_p)rake_dm_base, (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ // rake dm end
+ {(ssdvt_uint32_p)(rake_dm_end - access_path_test_size), (ssdvt_uint32)access_path_test_size, (ssdvt_uint32_p)0},
+ };
+ ssdvt_uint32 mem_info_size = sizeof(mem_info)/sizeof(SSDVT_MEM_MemInfo);
+
+ dbg_print("... MD32 memory test: start\n");
+
+
+ /* start to test */
+ for(midx = 0; midx < mem_info_size; ++midx){
+ ssdvt_mem_test_mem_range_num = midx;
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8));
+
+ dbg_print(".... MD32 memory test: %x, size: %d\n", mem_info[midx].base_addr, mem_info[midx].size);
+ for(i=0; i< mem_test_case_size; ++i){
+ // for share pm begin/end, only do basic test, skip byte/half-word address test
+ if ((0 == midx || 1 == midx) && i > 0) {
+ continue;
+ }
+ (*mem_test_case[i])(&mem_info[midx]);
+ }
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 1);
+ }
+
+ dbg_print("... MD32 memory access path test: success \n");
+
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + 0xFFF);
+
+
+ /* reset test type */
+ ssdvt_mem_test_type = SSDVT_MEM_NO_TEST_TYPE;
+ ssdvt_mem_test_current_status_base = 0x0;
+
+ ssdvt_test_pass_notification();
+
+}
+
diff --git a/mcu/driver/devdrv/cmif/src/drv_cmif.c b/mcu/driver/devdrv/cmif/src/drv_cmif.c
new file mode 100644
index 0000000..26dfa91
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/src/drv_cmif.c
@@ -0,0 +1,426 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cmif.c
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "drv_cmif_l1core.h"
+#include "kal_hrt_api.h"
+#include "gen93_proj_config.h"
+
+#if defined(__CMIF_DEBUG__)
+#include "us_timer.h"
+#endif
+
+#if defined(__MD32S_CMIF_DRV_TEST__)
+#include "intrCtrl.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+
+#define dbg_print(str, args...)
+#endif /* __MD32S_CMIF_DRV_TEST__ */
+
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+#if defined(__CMIF_DEBUG__)
+extern CMIF_DebugRecordList cmif_debug_records[CMIF_VPE_NUM];
+#endif
+
+
+#if !defined(__CMIF_DEBUG__)
+void cmif_InterruptHandlerInternal(volatile cmif_uint32* sreg,
+ volatile cmif_uint32* creg,
+ CMIF_InterruptEntryFun* handler,
+ cmif_bool* auto_eoi);
+#else /* __CMIF_DEBUG__ */
+void cmif_InterruptHandlerInternal(volatile cmif_uint32* sreg,
+ volatile cmif_uint32* creg,
+ CMIF_InterruptEntryFun* handler,
+ cmif_bool* auto_eoi,
+ CMIF_DebugInterruptType interrupt_type);
+#endif /* __CMIF_DEBUG__ */
+
+/*******************************************************************************
+ * Functions - Common Part
+ *******************************************************************************/
+void CMIF_DefaultISR(CMIF_Mask_t* mask)
+{
+ // code 1: status register value, code 2: status register addr, code 3: u3g, fpc_1x, do_pd, foe_1x (0~3)
+ CMIF_ASSERT(0, mask->mask31_0,
+ (cmif_uint32)mask->status_reg_addr,
+ ((cmif_uint32)mask->status_reg_addr - (cmif_uint32)CMIF_M2C_U3G_RAKE_STATUS) / CMIF_NEXT_INT_OFFSET);
+
+ //CMIF_ASSERT(0, mask->mask31_0, 0, 0);
+}
+
+#if defined(__CMIF_DEBUG__)
+void cmif_DebugAddRecord(cmif_uint32 status,
+ cmif_uint32 set_addr,
+ cmif_uint32 set_value,
+ cmif_uint32 caller)
+{
+
+ cmif_uint32 save_index = 0;
+ cmif_uint32 vpe_id = kal_get_current_vpe_id();
+ CMIF_ASSERT(vpe_id < CMIF_VPE_NUM, vpe_id, CMIF_VPE_NUM, 0);
+
+ CMIF_DebugRecordList *cmif_debug_records_ptr = &cmif_debug_records[vpe_id];
+
+ /* 93,95 legacey code */
+ /*
+ cmif_uint32 mask;
+
+ mask = kal_hrt_SaveAndSetIRQMask();
+
+ // fetch and add top_index atomically.
+ save_index = cmif_debug_records_ptr->top_index;
+
+ ++(cmif_debug_records_ptr->top_index);
+ if(cmif_debug_records_ptr->top_index == CMIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ cmif_debug_records_ptr->top_index = 0;
+ }
+
+ kal_hrt_RestoreIRQMask(mask);
+ */
+
+ save_index = kal_atomic_inc_circular_index(&(cmif_debug_records_ptr->top_index), CMIF_DEBUG_API_RECORD_SIZE);
+
+ cmif_debug_records_ptr->records[save_index].time = ust_get_current_time();
+ cmif_debug_records_ptr->records[save_index].status = status;
+ cmif_debug_records_ptr->records[save_index].set_addr = set_addr;
+ cmif_debug_records_ptr->records[save_index].set_value = set_value;
+ cmif_debug_records_ptr->records[save_index].caller = caller;
+}
+#endif /* __CMIF_DEBUG__ */
+
+/**
+ * General interrupt handler function
+ *
+ * @param[in] sreg CMIF interrupt status register
+ * @param[in] creg CMIF interrupt clean register
+ * @param[in] handler CMIF user entry function lists
+ * @param[in] core CMIF interrupt core type - BRP, DFE and RAKE (Debug only)
+ * @param[in] interrupt_type CMIF interrupt type - U3G or U4G (Debug only)
+ **/
+#if !defined(__CMIF_DEBUG__)
+void cmif_InterruptHandlerInternal(volatile cmif_uint32* sreg,
+ volatile cmif_uint32* creg,
+ CMIF_InterruptEntryFun* handler,
+ cmif_bool* auto_eoi
+ )
+#else /* __CMIF_DEBUG__ */
+void cmif_InterruptHandlerInternal(volatile cmif_uint32* sreg,
+ volatile cmif_uint32* creg,
+ CMIF_InterruptEntryFun* handler,
+ cmif_bool* auto_eoi,
+ CMIF_DebugInterruptType interrupt_type)
+#endif /* __CMIF_DEBUG__ */
+{
+ cmif_uint32 eidx; // entry function index
+ CMIF_Mask_t cmif_mask;
+#if defined(__CMIF_DEBUG__)
+ cmif_uint32 caller;
+ CMIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CMIF_DEBUG__ */
+
+ // for debug usage
+ cmif_mask.status_reg_addr = (cmif_uint32 *)sreg;
+ // read the sreg to the mask
+ cmif_mask.mask31_0 = CMIF_REG_READ(sreg);
+
+ while(cmif_mask.mask31_0){
+ // find the lsb
+ eidx = CMIF_GET_LSB(cmif_mask.mask31_0);
+
+ // invoke the user register interupt handler function
+ (*handler[eidx])((CMIF_Mask_t *)&cmif_mask);
+
+ // if the `irq_auto_eoi` is CMIF_TRUE, clean the interupt bit
+ if(auto_eoi[eidx] == CMIF_TRUE){
+
+ /* In 6291, JADE CMIF has a clear fail bug */
+ /* This workaround ensure the clear transaction is success */
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ do{
+#endif
+ CMIF_REG_WRITE(creg, 1 << eidx);
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ }while((CMIF_REG_READ(sreg) >> eidx) & 0x1);
+#endif
+
+#if defined(__CMIF_DEBUG__)
+ cmif_DebugAddRecord(cmif_mask.mask31_0, (cmif_uint32)creg, (1 << eidx), caller);
+#endif /* __CMIF_DEBUG__ */
+ }
+
+#if defined(__CMIF_DEBUG__)
+ cmif_DebugAddISRHandle(eidx, interrupt_type);
+#endif /* __CMIF_DEBUG__ */
+
+ // read the sreg to the mask
+ cmif_mask.mask31_0 = CMIF_REG_READ(sreg);
+
+ }
+}
+
+
+/*******************************************************************************
+ * Functions - Driver test
+ *******************************************************************************/
+
+#if defined(__MD32S_CMIF_DRV_TEST__)
+
+extern CMIF_Ctrl_t cmif_ctrl_rake_u3g;
+extern CMIF_Ctrl_t cmif_ctrl_rake_fpc_1x;
+extern CMIF_Ctrl_t cmif_ctrl_rake_do_pd;
+extern CMIF_Ctrl_t cmif_ctrl_rake_foe_1x;
+
+
+extern cmif_uint32 cmif_drvtest_case;
+extern cmif_uint32 cmif_drvtest_prev_irq;
+extern cmif_uint32 cmif_drvtest_irq_test_success;
+
+extern void CMIF_DriverAPIM2CTest(CMIF_Ctrl_t* ctrl);
+extern void CMIF_DriverAPIC2MTest(CMIF_Ctrl_t* ctrl);
+
+extern void CMIF_DriverISRTestC2M(CMIF_Ctrl_t* ctrl, cmif_uint32 case_num);
+extern void CMIF_DriverISRTestM2C(CMIF_Ctrl_t* ctrl, cmif_uint32 case_num);
+
+void cmif_drv_test_sync(CMIF_Ctrl_t* ctrl)
+{
+ volatile cmif_uint32* sync = ctrl->sync;
+
+ while(sync[1] == 1) ;
+ sync[1] = 1;
+
+ while(sync[0] == 0) ;
+ sync[0] = 0;
+}
+
+
+void CMIF_DriverAPITest()
+{
+ CMIF_DriverAPIM2CTest(&cmif_ctrl_rake_u3g);
+ CMIF_DriverAPIC2MTest(&cmif_ctrl_rake_u3g);
+
+ CMIF_DriverAPIM2CTest(&cmif_ctrl_rake_fpc_1x);
+ CMIF_DriverAPIM2CTest(&cmif_ctrl_rake_do_pd);
+ CMIF_DriverAPIM2CTest(&cmif_ctrl_rake_foe_1x);
+}
+
+
+void CMIF_DisableInterrupt()
+{
+ // MCU Part
+ IRQMask(IRQID_RAKE_CMIF_M2C_IRQ_U3G);
+ IRQMask(IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X);
+ IRQMask(IRQID_RAKE_CMIF_M2C_IRQ_DO_PD);
+ IRQMask(IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X);
+}
+
+void CMIF_EnableInterrupt()
+{
+ extern void CMIF_Init();
+ CMIF_Init();
+}
+
+void CMIF_ClearPendingInterrupt()
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+void CMIF_InterruptTest()
+{
+ // test rake u3g
+ CMIF_DriverISRTestC2M(&cmif_ctrl_rake_u3g, 1);
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_u3g, 1);
+
+ CMIF_DriverISRTestC2M(&cmif_ctrl_rake_u3g, 2);
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_u3g, 2);
+
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_fpc_1x, 1);
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_fpc_1x, 2);
+
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_do_pd, 1);
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_do_pd, 2);
+
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_foe_1x, 1);
+ CMIF_DriverISRTestM2C(&cmif_ctrl_rake_foe_1x, 2);
+}
+
+/* how to run cmif driver test ? */
+/* MD32 Side: insert CMIF_DriverTest to basic load function */
+/* CR4 Side: insert CMIF_DriverTest to idle task function */
+
+void CMIF_DriverTest()
+{
+#if __CMIF_MD32S_CORE__
+ extern void CMIF_DriverInitTest();
+ CMIF_DriverInitTest();
+#endif
+
+ CMIF_DisableInterrupt();
+ dbg_print("-- CMIF API Test Start.\n");
+ CMIF_DisableInterrupt();
+ CMIF_DriverAPITest();
+ dbg_print("-- CMIF API Test End.\n");
+
+ dbg_print("-- CMIF Interrupt Start.\n");
+ CMIF_EnableInterrupt();
+ CMIF_InterruptTest();
+ dbg_print("-- CMIF Interrupt End.\n");
+
+ while(1);
+}
+
+#endif /* __MD32S_CMIF_DRV_TEST__ */
+
diff --git a/mcu/driver/devdrv/cmif/src/drv_cmif_l1core.c b/mcu/driver/devdrv/cmif/src/drv_cmif_l1core.c
new file mode 100644
index 0000000..b799d6c
--- /dev/null
+++ b/mcu/driver/devdrv/cmif/src/drv_cmif_l1core.c
@@ -0,0 +1,1142 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * cmif.c
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "drv_cmif_l1core.h"
+
+#include "intrCtrl.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+#include "kal_hrt_api.h"
+#include "kal_internal_api.h"
+
+#include "gen93_proj_config.h"
+
+#include "us_timer.h"
+
+#if defined(__MTK_TARGET__)
+#include "kal_trace.h" // for logging
+static char cmif_fatal_error_trace_buf[128];
+#endif /* __MTK_TARGET__ */
+
+#if defined(__MD97__) && (defined(MT6297_FPGA) && !defined(UMOLYE_COSIM))
+#include "init_comm.h"
+#endif
+
+/*******************************************************************************
+ * Data Structure
+ *******************************************************************************/
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name) extern void fun_name(CMIF_Mask_t*);
+#define irq_auto_eoi(eoi)
+
+#include "cmif_m2c_isr_config_u3g_rake_pre.h"
+#include "cmif_m2c_isr_config_fpc_1x_pre.h"
+#include "cmif_m2c_isr_config_do_pd_pre.h"
+#include "cmif_m2c_isr_config_foe_1x_pre.h"
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name) fun_name,
+#define irq_auto_eoi(eoi)
+
+CMIF_InterruptEntryFun cmif_isr_handler_u3g_rake[] = {
+ #include "cmif_m2c_isr_config_u3g_rake_pre.h"
+};
+
+CMIF_InterruptEntryFun cmif_isr_handler_fpc_1x[] = {
+ #include "cmif_m2c_isr_config_fpc_1x_pre.h"
+};
+
+CMIF_InterruptEntryFun cmif_isr_handler_do_pd[] = {
+ #include "cmif_m2c_isr_config_do_pd_pre.h"
+};
+
+CMIF_InterruptEntryFun cmif_isr_handler_foe_1x[] = {
+ #include "cmif_m2c_isr_config_foe_1x_pre.h"
+};
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name)
+#define irq_auto_eoi(eoi) eoi,
+
+cmif_bool cmif_isr_eoi_u3g_rake[] = {
+ #include "cmif_m2c_isr_config_u3g_rake_pre.h"
+};
+
+cmif_bool cmif_isr_eoi_fpc_1x[] = {
+ #include "cmif_m2c_isr_config_fpc_1x_pre.h"
+};
+
+cmif_bool cmif_isr_eoi_do_pd[] = {
+ #include "cmif_m2c_isr_config_do_pd_pre.h"
+};
+
+cmif_bool cmif_isr_eoi_foe_1x[] = {
+ #include "cmif_m2c_isr_config_foe_1x_pre.h"
+};
+
+
+/*******************************************************************************
+ * Debug
+ *******************************************************************************/
+#if defined(__CMIF_DEBUG__)
+
+CMIF_DebugISRCodeList cmif_debug_isr_handle_u3g;
+CMIF_DebugISRCodeList cmif_debug_isr_handle_fpc_1x;
+CMIF_DebugISRCodeList cmif_debug_isr_handle_do_pd;
+CMIF_DebugISRCodeList cmif_debug_isr_handle_foe_1x;
+
+CMIF_DebugRecordList cmif_debug_records[CMIF_VPE_NUM];
+
+kal_uint32 CMIF_DebugIrqStatus;
+#endif
+
+CMIF_OverFlowRecord cmif_overflow_record[CMIF_VPE_NUM];
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+#if !defined(__CMIF_DEBUG__)
+extern void cmif_InterruptHandlerInternal(volatile cmif_uint32* sreg,
+ volatile cmif_uint32* creg,
+ CMIF_InterruptEntryFun* handler,
+ cmif_bool* auto_eoi);
+#else /* __CMIF_DEBUG__ */
+extern void cmif_InterruptHandlerInternal(volatile cmif_uint32* sreg,
+ volatile cmif_uint32* creg,
+ CMIF_InterruptEntryFun* handler,
+ cmif_bool* auto_eoi,
+ CMIF_DebugInterruptType interrupt_type);
+#endif /* __CMIF_DEBUG__ */
+
+
+void CMIF_InterruptHandler_U3G_RAKE();
+void CMIF_InterruptHandler_FPC_1X();
+void CMIF_InterruptHandler_DO_PD();
+void CMIF_InterruptHandler_FOE_1X();
+extern void wfi_irq_callback_rake();
+
+/*******************************************************************************
+ * Functions - CR4 Part
+ *******************************************************************************/
+#define CMIF_CHECK_ALLOW_POWER_DOWN_OFFSET 0x54
+
+#define CMIF_RAKE_CHECK_ALLOW_POWER_DOWN_STATUS ((volatile cmif_uint32*)(CMIF_CR4_RAKE_BASE_ADDR + CMIF_CHECK_ALLOW_POWER_DOWN_OFFSET))
+
+#define CMIF_MD32_PATTERN_WFI_SEND 0x32DE32DE
+
+cmif_bool CMIF_MD32AllowPowerDown()
+{
+ cmif_uint32 md32_status = 0;
+
+ md32_status = *CMIF_RAKE_CHECK_ALLOW_POWER_DOWN_STATUS;
+
+ if(CMIF_MD32_PATTERN_WFI_SEND == md32_status)
+ {
+ return CMIF_TRUE;
+ }
+ else
+ {
+ return CMIF_FALSE;
+ }
+}
+
+cmif_uint32 CMIF_C2M_STATUS_U3G_READ()
+{
+ cmif_uint32 cmif_u3g_status = 0;
+
+ cmif_u3g_status = *CMIF_C2M_U3G_RAKE_STATUS;
+
+ return cmif_u3g_status;
+}
+
+void CMIF_Init()
+{
+ #if defined(__MD97__)
+ #if defined(MT6297_FPGA) && !defined(UMOLYE_COSIM)
+ HW_PURPOSE cmif_platform_version = PURPOSE_NotSupport;
+ cmif_platform_version = INT_FPGA_PURPOSE();
+ if( cmif_platform_version == FPGA_H1 )
+ return;
+ #endif
+ #endif
+
+ /* For ISR centralization in VMOLY TRUNK, all IRQ ISR Handler and Sensitivity config are in gen9*_isr_config.h */
+ // Unmask u3g rake interrupt handler
+ IRQUnmask(MD_IRQID_RAKE_CMIF_M2C_IRQ_0);
+
+ // Unmask u3g rake interrupt handler
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_U3G);
+
+ // Unmask fpc_1x interrupt handler
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_FPC_1X);
+
+ // Unmask do_pd interrupt handler
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_DO_PD);
+
+ // Unmask foe_1x interrupt handler
+ IRQUnmask(IRQID_RAKE_CMIF_M2C_IRQ_FOE_1X);
+
+}
+
+void CMIF_C2M_STATUS_U3G(CMIF_Mask_t* mask)
+{
+ mask -> mask31_0 = *CMIF_C2M_U3G_RAKE_STATUS;
+}
+
+void CMIF_M2C_STATUS_U3G(CMIF_Mask_t* mask)
+{
+ mask -> mask31_0 = *CMIF_M2C_U3G_RAKE_STATUS;
+}
+
+void CMIF_M2C_STATUS_FPC_1X(CMIF_Mask_t* mask)
+{
+ mask -> mask31_0 = *CMIF_M2C_FPC_1X_STATUS;
+}
+
+void CMIF_M2C_STATUS_DO_PD(CMIF_Mask_t* mask)
+{
+ mask -> mask31_0 = *CMIF_M2C_DO_PD_STATUS;
+}
+
+void CMIF_M2C_STATUS_FOE_1X(CMIF_Mask_t* mask)
+{
+ mask -> mask31_0 = *CMIF_M2C_FOE_1X_STATUS;
+}
+
+void CMIF_C2M_SWI_SW_U3G(CMIF_C2M_U3G_Code_t code)
+{
+ cmif_uint32 caller;
+ CMIF_Mask_t before;
+
+ CMIF_GET_RETURN_ADDRESS(caller);
+ before.mask31_0 = CMIF_REG_READ(CMIF_C2M_U3G_RAKE_STATUS);
+
+ // check the code in the range
+ CMIF_ASSERT(code < CMIF_C2M_U3G_TOTAL_NUMBER_RAKE, code, CMIF_C2M_U3G_TOTAL_NUMBER_RAKE, 0);
+
+ // avoid set the same interrupt again
+ if ((before.mask31_0 >> code) & 0x1)
+ {
+ cmif_uint32 vpe_id = kal_get_current_vpe_id();
+ CMIF_ASSERT(vpe_id < CMIF_VPE_NUM, vpe_id, CMIF_VPE_NUM, 0);
+
+ cmif_overflow_record[vpe_id].time = ust_get_current_time();
+ cmif_overflow_record[vpe_id].interrupt_bit = code;
+ cmif_overflow_record[vpe_id].status_addr = (cmif_uint32)(CMIF_C2M_U3G_RAKE_STATUS);
+ cmif_overflow_record[vpe_id].current_status = before.mask31_0;
+ cmif_overflow_record[vpe_id].caller = caller;
+
+#if defined(__MTK_TARGET__) // print log
+ sprintf(cmif_fatal_error_trace_buf, "CMIF C2M U3G interrupt bit overflow: overflow bit: %d, current status: 0x%x, caller 0x%x", code, before.mask31_0, caller);
+ kal_sys_trace(cmif_fatal_error_trace_buf);
+#endif
+ kal_fatal_error_handler(KAL_ERROR_DSP_INTERRUPT_TRIGGER_INVALID, caller);
+ //CMIF_ASSERT(((CMIF_REG_READ(CMIF_C2M_U3G_RAKE_STATUS) >> code) & 0x1) == 0, CMIF_C2M_U3G_TOTAL_NUMBER_RAKE, code, CMIF_REG_READ(CMIF_C2M_U3G_RAKE_STATUS));
+ }
+
+ // set the status bit to send the interrupt
+ CMIF_REG_WRITE(CMIF_C2M_U3G_RAKE_SET, 1 << code);
+
+#if defined(__CMIF_DEBUG__)
+ CMIF_DebugIrqStatus = *((volatile kal_uint32 *)(CMIF_C2M_U3G_RAKE_STATUS));
+ cmif_DebugAddRecord(before.mask31_0, (cmif_uint32)CMIF_C2M_U3G_RAKE_SET, (1 << code), caller);
+#endif /* __CMIF_DEBUG__ */
+}
+
+void CMIF_M2C_EOI_U3G(CMIF_M2C_U3G_Code_t code)
+{
+#if defined(__CMIF_DRV_SW_WORKAROUND__) || defined(__CMIF_DEBUG__)
+ cmif_uint32 status = 0;
+#endif
+ // check the code in the range
+ CMIF_ASSERT(code < CMIF_M2C_U3G_TOTAL_NUMBER_RAKE, code, CMIF_M2C_U3G_TOTAL_NUMBER_RAKE, 0);
+
+
+#if defined(__CMIF_DEBUG__)
+ cmif_uint32 caller;
+ CMIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CMIF_DEBUG__ */
+
+ /* Add this work around to ensure cmif status is cleared correctly */
+ /* This hardware bug is existed in TK6291, Jade, Everest */
+ /* For C2M IRQ, the same T access will give CR4 higher priority */
+ /* For M2C IRQ, the same T access will give MD32 higher priority */
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ do{
+#endif
+ CMIF_REG_WRITE(CMIF_M2C_U3G_RAKE_CLEAN, 1 << code);
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ status = CMIF_REG_READ(CMIF_M2C_U3G_RAKE_STATUS);
+ }while((status >> code) & 0x1);
+#endif
+
+#if defined(__CMIF_DEBUG__)
+ cmif_DebugAddRecord(status, (cmif_uint32)CMIF_M2C_U3G_RAKE_CLEAN, (1 << code), caller);
+#endif /* __CMIF_DEBUG__ */
+
+}
+
+
+void CMIF_M2C_EOI_FPC_1X(CMIF_M2C_FPC_1X_Code_t code)
+{
+#if defined(__CMIF_DRV_SW_WORKAROUND__) || defined(__CMIF_DEBUG__)
+ cmif_uint32 status = 0;
+#endif
+ // check the code in the range
+ CMIF_ASSERT(code < CMIF_M2C_FPC_1X_TOTAL_NUMBER, code, CMIF_M2C_FPC_1X_TOTAL_NUMBER, 0);
+
+#if defined(__CMIF_DEBUG__)
+ cmif_uint32 caller;
+ CMIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CMIF_DEBUG__ */
+
+ /* Add this work around to ensure cmif status is cleared correctly */
+ /* This hardware bug is existed in TK6291, Jade, Everest */
+ /* For C2M IRQ, the same T access will give CR4 higher priority */
+ /* For M2C IRQ, the same T access will give MD32 higher priority */
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ do{
+#endif
+ CMIF_REG_WRITE(CMIF_M2C_FPC_1X_CLEAN, 1 << code);
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ status = CMIF_REG_READ(CMIF_M2C_FPC_1X_STATUS);
+ }while((status >> code) & 0x1);
+#endif
+
+#if defined(__CMIF_DEBUG__)
+ cmif_DebugAddRecord(status, (cmif_uint32)CMIF_M2C_FPC_1X_CLEAN, (1 << code), caller);
+#endif /* __CMIF_DEBUG__ */
+
+}
+
+
+void CMIF_M2C_EOI_DO_PD(CMIF_M2C_DO_PD_Code_t code)
+{
+#if defined(__CMIF_DRV_SW_WORKAROUND__) || defined(__CMIF_DEBUG__)
+ cmif_uint32 status = 0;
+#endif
+ // check the code in the range
+ CMIF_ASSERT(code < CMIF_M2C_DO_PD_TOTAL_NUMBER, code, CMIF_M2C_DO_PD_TOTAL_NUMBER, 0);
+
+#if defined(__CMIF_DEBUG__)
+ cmif_uint32 caller;
+ CMIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CMIF_DEBUG__ */
+
+ /* Add this work around to ensure cmif status is cleared correctly */
+ /* This hardware bug is existed in TK6291, Jade, Everest */
+ /* For C2M IRQ, the same T access will give CR4 higher priority */
+ /* For M2C IRQ, the same T access will give MD32 higher priority */
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ do{
+#endif
+ CMIF_REG_WRITE(CMIF_M2C_DO_PD_CLEAN, 1 << code);
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ status = CMIF_REG_READ(CMIF_M2C_DO_PD_STATUS);
+ }while((status >> code) & 0x1);
+#endif
+
+#if defined(__CMIF_DEBUG__)
+ cmif_DebugAddRecord(status, (cmif_uint32)CMIF_M2C_DO_PD_CLEAN, (1 << code), caller);
+#endif /* __CMIF_DEBUG__ */
+
+}
+
+
+void CMIF_M2C_EOI_FOE_1X(CMIF_M2C_FOE_1X_Code_t code)
+{
+#if defined(__CMIF_DRV_SW_WORKAROUND__) || defined(__CMIF_DEBUG__)
+ cmif_uint32 status = 0;
+#endif
+
+ // check the code in the range
+ CMIF_ASSERT(code < CMIF_M2C_FOE_1X_TOTAL_NUMBER, code, CMIF_M2C_FOE_1X_TOTAL_NUMBER, 0);
+
+
+#if defined(__CMIF_DEBUG__)
+ cmif_uint32 caller;
+ CMIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CMIF_DEBUG__ */
+
+ /* Add this work around to ensure cmif status is cleared correctly */
+ /* This hardware bug is existed in TK6291, Jade, Everest */
+ /* For C2M IRQ, the same T access will give CR4 higher priority */
+ /* For M2C IRQ, the same T access will give MD32 higher priority */
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ do{
+#endif
+ CMIF_REG_WRITE(CMIF_M2C_FOE_1X_CLEAN, 1 << code);
+#if defined(__CMIF_DRV_SW_WORKAROUND__)
+ status = CMIF_REG_READ(CMIF_M2C_FOE_1X_STATUS);
+ }while((status >> code) & 0x1);
+#endif
+
+#if defined(__CMIF_DEBUG__)
+ cmif_DebugAddRecord(status, (cmif_uint32)CMIF_M2C_FOE_1X_CLEAN, (1 << code), caller);
+#endif /* __CMIF_DEBUG__ */
+
+}
+
+/**
+ * CMIF Interrupt handler: MD32 trigger MCU
+ *
+ **/
+void CMIF_InterruptHandler_U3G_RAKE()
+{
+#if !defined(__CMIF_DEBUG__)
+ cmif_InterruptHandlerInternal(CMIF_M2C_U3G_RAKE_STATUS,
+ CMIF_M2C_U3G_RAKE_CLEAN,
+ cmif_isr_handler_u3g_rake,
+ cmif_isr_eoi_u3g_rake);
+#else /* __CMIF_DEBUG__ */
+ cmif_InterruptHandlerInternal(CMIF_M2C_U3G_RAKE_STATUS,
+ CMIF_M2C_U3G_RAKE_CLEAN,
+ cmif_isr_handler_u3g_rake,
+ cmif_isr_eoi_u3g_rake,
+ CMIF_DEBUG_U3G_INTERRUPT);
+#endif /* __CMIF_DEBUG__ */
+}
+
+/**
+ * CMIF Interrupt handler: MD32 trigger MCU
+ *
+ **/
+void CMIF_InterruptHandler_FPC_1X()
+{
+#if !defined(__CMIF_DEBUG__)
+ cmif_InterruptHandlerInternal(CMIF_M2C_FPC_1X_STATUS,
+ CMIF_M2C_FPC_1X_CLEAN,
+ cmif_isr_handler_fpc_1x,
+ cmif_isr_eoi_fpc_1x);
+#else /* __CMIF_DEBUG__ */
+ cmif_InterruptHandlerInternal(CMIF_M2C_FPC_1X_STATUS,
+ CMIF_M2C_FPC_1X_CLEAN,
+ cmif_isr_handler_fpc_1x,
+ cmif_isr_eoi_fpc_1x,
+ CMIF_DEBUG_FPC_1X_INTERRUPT);
+#endif /* __CMIF_DEBUG__ */
+}
+
+/**
+ * CMIF Interrupt handler: MD32 trigger MCU
+ *
+ **/
+void CMIF_InterruptHandler_DO_PD()
+{
+#if !defined(__CMIF_DEBUG__)
+ cmif_InterruptHandlerInternal(CMIF_M2C_DO_PD_STATUS,
+ CMIF_M2C_DO_PD_CLEAN,
+ cmif_isr_handler_do_pd,
+ cmif_isr_eoi_do_pd);
+#else /* __CMIF_DEBUG__ */
+ cmif_InterruptHandlerInternal(CMIF_M2C_DO_PD_STATUS,
+ CMIF_M2C_DO_PD_CLEAN,
+ cmif_isr_handler_do_pd,
+ cmif_isr_eoi_do_pd,
+ CMIF_DEBUG_DO_PD_INTERRUPT);
+#endif /* __CMIF_DEBUG__ */
+}
+
+
+/**
+ * CMIF Interrupt handler: MD32 trigger MCU
+ *
+ **/
+void CMIF_InterruptHandler_FOE_1X()
+{
+#if !defined(__CMIF_DEBUG__)
+ cmif_InterruptHandlerInternal(CMIF_M2C_FOE_1X_STATUS,
+ CMIF_M2C_FOE_1X_CLEAN,
+ cmif_isr_handler_foe_1x,
+ cmif_isr_eoi_foe_1x);
+#else /* __CMIF_DEBUG__ */
+ cmif_InterruptHandlerInternal(CMIF_M2C_FOE_1X_STATUS,
+ CMIF_M2C_FOE_1X_CLEAN,
+ cmif_isr_handler_foe_1x,
+ cmif_isr_eoi_foe_1x,
+ CMIF_DEBUG_FOE_1X_INTERRUPT);
+#endif /* __CMIF_DEBUG__ */
+}
+
+
+#if defined(__CMIF_DEBUG__)
+void cmif_DebugAddISRHandle(cmif_uint32 code,
+ CMIF_DebugInterruptType isr_type)
+{
+ CMIF_DebugISRCodeList* code_list = CMIF_NULL;
+ cmif_uint32 save_index;
+
+ if(isr_type == CMIF_DEBUG_U3G_INTERRUPT){
+ code_list = &cmif_debug_isr_handle_u3g;
+ }
+ else if(isr_type == CMIF_DEBUG_FPC_1X_INTERRUPT){
+ code_list = &cmif_debug_isr_handle_fpc_1x;
+ }
+ else if(isr_type == CMIF_DEBUG_DO_PD_INTERRUPT){
+ code_list = &cmif_debug_isr_handle_do_pd;
+ }
+ else if(isr_type == CMIF_DEBUG_FOE_1X_INTERRUPT){
+ code_list = &cmif_debug_isr_handle_foe_1x;
+ }
+
+ if(code_list != CMIF_NULL){
+ save_index = code_list -> top_index;
+
+ ++code_list -> top_index;
+ if(code_list -> top_index == CMIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ code_list -> top_index = 0;
+ }
+ code_list->records[save_index].time = ust_get_current_time();
+ code_list->records[save_index].code = code;
+ }
+}
+#endif
+
+
+/*******************************************************************************
+ * Functions - Driver test
+ *******************************************************************************/
+#if defined(__MD32S_CMIF_DRV_TEST__)
+
+#define CMIF_DRV_TEST_ASSERT_EQ(a, b) \
+ do{ \
+ if((a) != (b)){ \
+ while(1); \
+ } \
+ }while(0);
+
+CMIF_Ctrl_t cmif_ctrl_rake_u3g = {
+ .send_set = CMIF_C2M_U3G_RAKE_SET,
+ .send_status = CMIF_C2M_U3G_RAKE_STATUS,
+ .receive_clr = CMIF_M2C_U3G_RAKE_CLEAN,
+ .receive_status = CMIF_M2C_U3G_RAKE_STATUS,
+ .sync = CMIF_DRV_TEST_SYNC_ADDR,
+
+ .send_func = CMIF_C2M_SWI_SW_U3G,
+ .send_stats_func = CMIF_C2M_STATUS_U3G,
+ .receive_clr_func = CMIF_M2C_EOI_U3G,
+ .receive_stats_func = CMIF_M2C_STATUS_U3G,
+};
+
+CMIF_Ctrl_t cmif_ctrl_rake_fpc_1x = {
+ .send_set = CMIF_NULL,
+ .send_status = CMIF_NULL,
+ .receive_clr = CMIF_M2C_FPC_1X_CLEAN,
+ .receive_status = CMIF_M2C_FPC_1X_STATUS,
+ .sync = CMIF_DRV_TEST_SYNC_ADDR,
+
+ .send_func = CMIF_NULL,
+ .send_stats_func = CMIF_NULL,
+ .receive_clr_func = CMIF_M2C_EOI_FPC_1X,
+ .receive_stats_func = CMIF_M2C_STATUS_FPC_1X,
+};
+
+CMIF_Ctrl_t cmif_ctrl_rake_do_pd = {
+ .send_set = CMIF_NULL,
+ .send_status = CMIF_NULL,
+ .receive_clr = CMIF_M2C_DO_PD_CLEAN,
+ .receive_status = CMIF_M2C_DO_PD_STATUS,
+ .sync = CMIF_DRV_TEST_SYNC_ADDR,
+
+ .send_func = CMIF_NULL,
+ .send_stats_func = CMIF_NULL,
+ .receive_clr_func = CMIF_M2C_EOI_DO_PD,
+ .receive_stats_func = CMIF_M2C_STATUS_DO_PD,
+};
+
+CMIF_Ctrl_t cmif_ctrl_rake_foe_1x = {
+ .send_set = CMIF_NULL,
+ .send_status = CMIF_NULL,
+ .receive_clr = CMIF_M2C_FOE_1X_CLEAN,
+ .receive_status = CMIF_M2C_FOE_1X_STATUS,
+ .sync = CMIF_DRV_TEST_SYNC_ADDR,
+
+ .send_func = CMIF_NULL,
+ .send_stats_func = CMIF_NULL,
+ .receive_clr_func = CMIF_M2C_EOI_FOE_1X,
+ .receive_stats_func = CMIF_M2C_STATUS_FOE_1X,
+};
+
+
+
+
+extern void cmif_drv_test_sync(CMIF_Ctrl_t* ctrl);
+extern void CMIF_DisableInterrupt();
+extern void CMIF_EnableInterrupt();
+extern void CMIF_ClearPendingInterrupt();
+
+volatile cmif_uint32 cmif_drvtest_case;
+volatile cmif_uint32 cmif_drvtest_prev_irq;
+volatile cmif_uint32 cmif_drvtest_irq_test_success;
+
+void CMIF_DriverAPIM2CTest(CMIF_Ctrl_t* ctrl)
+{
+ CMIF_Mask_t mask;
+
+ cmif_drv_test_sync(ctrl);
+
+ // 1. Wait for MD32
+
+ cmif_drv_test_sync(ctrl);
+
+ // 2. Check the status and clear the status registers
+
+ (*ctrl->receive_stats_func)(&mask);
+ CMIF_DRV_TEST_ASSERT_EQ(*(ctrl->receive_status), 0x1E);
+ CMIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x1E);
+
+ (*ctrl->receive_clr_func)(1);
+ (*ctrl->receive_clr_func)(2);
+ (*ctrl->receive_clr_func)(3);
+ (*ctrl->receive_clr_func)(4);
+
+ (*ctrl->receive_stats_func)(&mask);
+ CMIF_DRV_TEST_ASSERT_EQ(*(ctrl->receive_status), 0x0);
+ CMIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ cmif_drv_test_sync(ctrl);
+
+ // 3. Wait for MD32
+
+
+ cmif_drv_test_sync(ctrl);
+}
+
+void CMIF_DriverAPIC2MTest(CMIF_Ctrl_t* ctrl)
+{
+ CMIF_Mask_t mask;
+
+ cmif_drv_test_sync(ctrl);
+
+ // 1. set the interrupt bit and check status registers
+ ctrl->send_func(1);
+ ctrl->send_func(2);
+ ctrl->send_func(3);
+ ctrl->send_func(4);
+
+ (*ctrl->send_stats_func)(&mask);
+ CMIF_DRV_TEST_ASSERT_EQ(*(ctrl->send_status), 0x1E);
+ CMIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x1E);
+
+
+ cmif_drv_test_sync(ctrl);
+
+ // 2. Wait for MD32
+
+ cmif_drv_test_sync(ctrl);
+
+ // 3. Check the status regsiters
+ (*ctrl->send_stats_func)(&mask);
+ CMIF_DRV_TEST_ASSERT_EQ(*(ctrl->send_status), 0x0);
+ CMIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ cmif_drv_test_sync(ctrl);
+
+}
+
+void CMIF_DriverISRTestC2M(CMIF_Ctrl_t* ctrl, cmif_uint32 case_num)
+{
+
+ cmif_drvtest_case = case_num;
+
+ cmif_drv_test_sync(ctrl);
+
+ // 1. Wait for MD32
+
+ cmif_drv_test_sync(ctrl);
+
+ // 2. Send interrupt to md32
+ if(cmif_drvtest_case == 1){
+ ctrl->send_func(1);
+ ctrl->send_func(2);
+ ctrl->send_func(3);
+ ctrl->send_func(4);
+ }
+ else if(cmif_drvtest_case == 2){
+ ctrl->send_func(5);
+ ctrl->send_func(6);
+ ctrl->send_func(7);
+ ctrl->send_func(8);
+ }
+
+ cmif_drv_test_sync(ctrl);
+
+ // 3. Wait for MD32
+
+ cmif_drv_test_sync(ctrl);
+}
+
+void CMIF_DriverISRTestM2C(CMIF_Ctrl_t* ctrl, cmif_uint32 case_num)
+{
+ cmif_drvtest_case = case_num;
+
+ cmif_drv_test_sync(ctrl);
+
+ // 1. Disalbe interrupt and clean the pending interrupt
+ CMIF_DisableInterrupt();
+ CMIF_ClearPendingInterrupt();
+
+ cmif_drv_test_sync(ctrl);
+
+ // 2. Wait for MD32
+
+ cmif_drv_test_sync(ctrl);
+
+ // 3. Enable the interrupt
+ CMIF_EnableInterrupt();
+ while(cmif_drvtest_irq_test_success != cmif_drvtest_case);
+ CMIF_DisableInterrupt();
+
+
+ cmif_drv_test_sync(ctrl);
+}
+
+
+void CMIF_DriverTestISR_U3G(CMIF_Mask_t* mask)
+{
+ cmif_uint32 cmif_drvtest_curr_irq;
+ if(cmif_drvtest_case == 1){
+ // auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ CMIF_DRV_TEST_ASSERT_EQ(cmif_drvtest_curr_irq - cmif_drvtest_prev_irq, 1);
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 4){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+ else if(cmif_drvtest_case == 2){
+ // non-auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ switch (cmif_drvtest_prev_irq) {
+ case 0:
+ CMIF_M2C_EOI_U3G(8);
+ break;
+ case 5:
+ if(cmif_drvtest_curr_irq == 5)
+ CMIF_M2C_EOI_U3G(5);
+ else if(cmif_drvtest_curr_irq == 6)
+ CMIF_M2C_EOI_U3G(6);
+ break;
+ case 6:
+ CMIF_M2C_EOI_U3G(7);
+ break;
+ default:
+ CMIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 7){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+}
+
+
+void CMIF_DriverTestISR_FPC_1X(CMIF_Mask_t* mask)
+{
+ cmif_uint32 cmif_drvtest_curr_irq;
+ if(cmif_drvtest_case == 1){
+ // auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ CMIF_DRV_TEST_ASSERT_EQ(cmif_drvtest_curr_irq - cmif_drvtest_prev_irq, 1);
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 4){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+ else if(cmif_drvtest_case == 2){
+ // non-auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ switch (cmif_drvtest_prev_irq) {
+ case 0:
+ CMIF_M2C_EOI_FPC_1X(8);
+ break;
+ case 5:
+ if(cmif_drvtest_curr_irq == 5)
+ CMIF_M2C_EOI_FPC_1X(5);
+ else if(cmif_drvtest_curr_irq == 6)
+ CMIF_M2C_EOI_FPC_1X(6);
+ break;
+ case 6:
+ CMIF_M2C_EOI_FPC_1X(7);
+ break;
+ default:
+ CMIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 7){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+}
+
+void CMIF_DriverTestISR_DO_PD(CMIF_Mask_t* mask)
+{
+ cmif_uint32 cmif_drvtest_curr_irq;
+ if(cmif_drvtest_case == 1){
+ // auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ CMIF_DRV_TEST_ASSERT_EQ(cmif_drvtest_curr_irq - cmif_drvtest_prev_irq, 1);
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 4){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+ else if(cmif_drvtest_case == 2){
+ // non-auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ switch (cmif_drvtest_prev_irq) {
+ case 0:
+ CMIF_M2C_EOI_DO_PD(8);
+ break;
+ case 5:
+ if(cmif_drvtest_curr_irq == 5)
+ CMIF_M2C_EOI_DO_PD(5);
+ else if(cmif_drvtest_curr_irq == 6)
+ CMIF_M2C_EOI_DO_PD(6);
+ break;
+ case 6:
+ CMIF_M2C_EOI_DO_PD(7);
+ break;
+ default:
+ CMIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 7){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+}
+
+void CMIF_DriverTestISR_FOE_1X(CMIF_Mask_t* mask)
+{
+ cmif_uint32 cmif_drvtest_curr_irq;
+ if(cmif_drvtest_case == 1){
+ // auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ CMIF_DRV_TEST_ASSERT_EQ(cmif_drvtest_curr_irq - cmif_drvtest_prev_irq, 1);
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 4){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+ else if(cmif_drvtest_case == 2){
+ // non-auto eoi mode
+ cmif_drvtest_curr_irq = CMIF_GET_LSB(mask->mask31_0);
+
+ switch (cmif_drvtest_prev_irq) {
+ case 0:
+ CMIF_M2C_EOI_FOE_1X(8);
+ break;
+ case 5:
+ if(cmif_drvtest_curr_irq == 5)
+ CMIF_M2C_EOI_FOE_1X(5);
+ else if(cmif_drvtest_curr_irq == 6)
+ CMIF_M2C_EOI_FOE_1X(6);
+ break;
+ case 6:
+ CMIF_M2C_EOI_FOE_1X(7);
+ break;
+ default:
+ CMIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cmif_drvtest_prev_irq = cmif_drvtest_curr_irq;
+ if(cmif_drvtest_prev_irq == 7){
+ cmif_drvtest_prev_irq = 0;
+ cmif_drvtest_irq_test_success = cmif_drvtest_case;
+ }
+ }
+}
+
+
+#endif /* __MD32S_CMIF_DRV_TEST__ */