diff --git a/mcu/driver/devdrv/common/src/GCC/mon_counter.S b/mcu/driver/devdrv/common/src/GCC/mon_counter.S
new file mode 100644
index 0000000..242de49
--- /dev/null
+++ b/mcu/driver/devdrv/common/src/GCC/mon_counter.S
@@ -0,0 +1,2 @@
+
+# Not used anymore
diff --git a/mcu/driver/devdrv/common/src/devdrv_common.c b/mcu/driver/devdrv/common/src/devdrv_common.c
new file mode 100644
index 0000000..f0922d1
--- /dev/null
+++ b/mcu/driver/devdrv/common/src/devdrv_common.c
@@ -0,0 +1,3413 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *    drvdrv_common.c
+ *
+ * Project:
+ * --------
+ *   Tataka_Software
+ *
+ * Description:
+ * ------------
+ *   This Module defines device driver common functions.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#include "drv_features.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#include "drv_comm.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#include "reg_base.h"
+#include "intrCtrl.h"
+
+#include "kal_trace.h"
+#include "system_trc.h"
+#include "init_trc_api.h"
+#include "init.h"
+#include "dcl.h"
+#include "drv_cmif.h"
+#include "cuif_l1core_public.h"
+#include "prbm.h"
+
+#if defined(MT6297)
+#include "d2d_public.h"
+#endif
+
+#if defined(__MD97__)
+#include "csif_l1core_public_api.h"
+#endif
+
+#ifdef __MTK_TARGET__
+   #include "ex_public.h"
+#ifdef __MULTI_BOOT__
+   #include "multiboot_config.h"
+#endif /* __MULTI_BOOT__ */
+#endif /* __MTK_TARGET__ */
+
+#if defined(__RESOURCE_MANAGER__)
+#include "rm.h"
+#endif //__RESOURCE_MANAGER__
+
+#include "us_timer.h"
+#include "drv_hisr.h"
+
+#ifdef DRV_HIF_SUPPORT
+#include "hif_hal.h"
+#endif
+
+#ifdef __HIF_CCCI_SUPPORT__
+#include "ccci_if.h"
+#endif
+
+#ifdef __HIF_PCCIF4_SUPPORT__
+#include "pccif4_if.h"
+#endif
+
+#ifdef __HIF_PCCIF5_SUPPORT__
+#include "pccif5_if.h"
+#endif
+
+#if defined(__SMART_PHONE_MODEM__)
+#include "ccci.h"
+
+#endif /* __SMART_PHONE_MODEM__ */
+
+#if defined(DRV_MISC_TDMA_L1_MACRO) || defined(DRV_MISC_TOPSM_32K_RTC)
+#include "RM_public.h"
+#endif
+
+#if defined(__SCC_SIB_SUPPORT__)
+#include "scc.h"
+#include "Drv_mtad.h"
+#endif
+
+#if defined(__HIF_PCIE_SUPPORT__)
+#include "hif_pcie.h"
+#endif
+
+#if defined(__HIF_MHCCIF_SUPPORT__)
+#include "mhccif_if.h"
+#endif
+#if defined(DRV_EMIMPU)
+extern void emimpu_init(void);
+#endif /* DRV_EMIMPU */
+
+//extern void DRVPDN_ini(void);
+//extern void DMA_Ini(void);
+extern void WDT_init(void);
+//extern void spi_init(void);
+extern void custom_drv_init(void);
+extern void GCU_Disable_ReverseBit(void);
+extern void UART_PDN_Enable(UART_PORT port);
+//extern void USB2UART_init(void);
+/* comment unused code after annouce at 2016/02/02  */
+//extern void Visual_Init(void);
+
+//extern void che_hw_init(void);
+//extern void lpwr_init(void);
+#if !defined(DCL_MSDC_INTERFACE)
+extern void MSDC_Initialize();
+#if defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__)
+extern void MSDC_Initialize2();
+#endif//defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__)
+#endif//!defined(DCL_MSDC_INTERFACE)
+
+/* comment unused code after annouce at 2016/02/02 */
+//#ifdef __WIFI_SUPPORT__
+//extern void wndrv_HWinit(void);
+//#endif
+ 
+extern void custom_drv_deinit(void);
+
+/* comment unused code after annouce at 2016/02/02 */ 
+//#if defined(ISP_SUPPORT)
+//extern void CalInit(void);
+//#endif
+
+#if defined(DRV_UART_SWITCHABLE_BETWEEN_PROCESSORS)
+extern kal_uint8 UartPortOwnedByMD[3];
+#endif // #if defined(DRV_UART_SWITCHABLE_BETWEEN_PROCESSORS)
+//extern kal_bool INT_QueryExceptionStatus(void);
+//Remove old extern function announcement & add new header file due to WCS/MDD/DE5 Kari Suvanto's request
+#include <ex_public.h>
+
+/*lint -e552*/
+boot_mode_type system_boot_mode = UNKNOWN_BOOT_MODE;
+/*lint +e552*/
+extern kal_uint16 INT_BootMode(void);
+
+#ifdef IC_MODULE_TEST
+   extern void IC_ModuleTest_Start(void);
+#endif   /*IC_MODULE_TEST*/
+
+#if defined(IC_BURNIN_TEST) || defined(DRV_MISC_GPT1_AS_OS_TICK)
+extern void INT_Timer_Interrupt(void);
+#endif //IC_BURNIN_TEST
+
+typedef void (* MEMCPY_FUNC)(const void *srcaddr, void *dstaddr, kal_uint32 len);
+#ifdef DRV_MISC_DMA_NO_MEMCPY
+   void (* DRV_MEMCPY)(const void *srcaddr, void *dstaddr, kal_uint32 len);
+#elif defined(DRV_MISC_DMA_MEMCPY)
+   extern kal_bool DMA_memcpy(const void *src, const void *dst, kal_uint32 length);
+   void (* DRV_MEMCPY_PTR)(const void *srcaddr, void *dstaddr, kal_uint32 len);
+   void DRV_MEMCPY(const void *srcaddr, void *dstaddr, kal_uint32 len);
+#endif   /**/
+
+//#if defined(__IRDA_SUPPORT__) && !defined(__MEUT__) && !defined(__MEIT__)
+/*TY adds this 2004/10/27*/
+//extern UartDriver_strcut ircomm_uart_api;
+//#endif
+
+#if defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__))
+extern Seriport_HANDLER_T  SPPA_Uart_Drv_Handler;
+extern void bchs_host_controller_power_off(void);
+#elif defined __CMUX_SUPPORT__
+extern Seriport_HANDLER_T  CmuxUart_Drv_Handler;
+#endif
+
+#ifdef __SWDBG_SUPPORT__
+extern kal_uint8 SWDBG_Profile;
+#endif  /* _SWDBG_SUPPORT__ */
+
+/* comment unused code after annouce at 2016/02/02 */
+//#ifdef  __BTMODULE_MT6601__
+//extern void BT_Radio_Shutdown(void);
+//#endif
+
+#if (defined( DRV_MULTIPLE_SIM) && (!defined(DRV_2_SIM_CONTROLLER)))
+extern void sim_MT6302_init(void);
+#endif
+
+extern void EINT_Setting_Init(void);
+
+extern void SOE_Drv_Init(void);
+
+extern void OSTD_register_ccci_callback(void);
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_MISC_REG_DBG__)
+#define DRV_MISC_WriteReg(addr,data)              DRV_DBG_WriteReg(addr,data)
+#define DRV_MISC_Reg(addr)                        DRV_DBG_Reg(addr)
+#define DRV_MISC_WriteReg32(addr,data)            DRV_DBG_WriteReg32(addr,data)
+#define DRV_MISC_Reg32(addr)                      DRV_DBG_Reg32(addr)
+#define DRV_MISC_WriteReg8(addr,data)             DRV_DBG_WriteReg8(addr,data)
+#define DRV_MISC_Reg8(addr)                       DRV_DBG_Reg8(addr)
+#define DRV_MISC_ClearBits(addr,data)             DRV_DBG_ClearBits(addr,data)
+#define DRV_MISC_SetBits(addr,data)               DRV_DBG_SetBits(addr,data)
+#define DRV_MISC_SetData(addr, bitmask, value)    DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_MISC_ClearBits32(addr,data)           DRV_DBG_ClearBits32(addr,data)
+#define DRV_MISC_SetBits32(addr,data)             DRV_DBG_SetBits32(addr,data)
+#define DRV_MISC_SetData32(addr, bitmask, value)  DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_MISC_ClearBits8(addr,data)            DRV_DBG_ClearBits8(addr,data)
+#define DRV_MISC_SetBits8(addr,data)              DRV_DBG_SetBits8(addr,data)
+#define DRV_MISC_SetData8(addr, bitmask, value)   DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_MISC_WriteReg(addr,data)              DRV_WriteReg(addr,data)
+#define DRV_MISC_Reg(addr)                        DRV_Reg(addr)
+#define DRV_MISC_WriteReg32(addr,data)            DRV_WriteReg32(addr,data)
+#define DRV_MISC_Reg32(addr)                      DRV_Reg32(addr)
+#define DRV_MISC_WriteReg8(addr,data)             DRV_WriteReg8(addr,data)
+#define DRV_MISC_Reg8(addr)                       DRV_Reg8(addr)
+#define DRV_MISC_ClearBits(addr,data)             DRV_ClearBits(addr,data)
+#define DRV_MISC_SetBits(addr,data)               DRV_SetBits(addr,data)
+#define DRV_MISC_SetData(addr, bitmask, value)    DRV_SetData(addr, bitmask, value)
+#define DRV_MISC_ClearBits32(addr,data)           DRV_ClearBits32(addr,data)
+#define DRV_MISC_SetBits32(addr,data)             DRV_SetBits32(addr,data)
+#define DRV_MISC_SetData32(addr, bitmask, value)  DRV_SetData32(addr, bitmask, value)
+#define DRV_MISC_ClearBits8(addr,data)            DRV_ClearBits8(addr,data)
+#define DRV_MISC_SetBits8(addr,data)              DRV_SetBits8(addr,data)
+#define DRV_MISC_SetData8(addr, bitmask, value)   DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_MISC_REG_DBG__)
+
+#ifdef __DRV_COMM_REG_DBG__
+DRV_REG_DBG_STRUCT    DRV_REG_DBG_INFO_DATA;
+
+static void drv_reg_dbg_trace(kal_uint8 write, kal_uint16 line, kal_uint32 addr, kal_uint32 value)
+{
+   DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].write_flag = write;
+   DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].line_number = line;
+   DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].reg_addr = addr;
+   DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].reg_value = value;
+   DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].time_log = drv_get_current_time();
+   DRV_REG_DBG_INFO_DATA.dbg_data_idx++;
+}
+
+void drv_reg_dbg_trace_write16(kal_uint16 line, kal_uint32 addr, kal_uint32 data)
+{
+   kal_uint32 savedMask;
+
+   savedMask = SaveAndSetIRQMask();
+   ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data));
+   drv_reg_dbg_trace(1, line, addr, data);
+   RestoreIRQMask(savedMask);
+   return;
+}
+
+void drv_reg_dbg_trace_write32(kal_uint16 line, kal_uint32 addr, kal_uint32 data)
+{
+   kal_uint32 savedMask;
+
+   savedMask = SaveAndSetIRQMask();
+   ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data));
+   drv_reg_dbg_trace(1, line, addr, data);
+   RestoreIRQMask(savedMask);
+   return;
+}
+
+void drv_reg_dbg_trace_write8(kal_uint16 line, kal_uint32 addr, kal_uint32 data)
+{
+   kal_uint32 savedMask;
+
+   savedMask = SaveAndSetIRQMask();
+   ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data));
+   drv_reg_dbg_trace(1, line, addr, data);
+   RestoreIRQMask(savedMask);
+   return;
+}
+
+kal_uint16 drv_reg_dbg_trace_read16(kal_uint16 line, kal_uint32 addr)
+{
+   kal_uint16 value;
+   kal_uint32 savedMask;
+
+   savedMask = SaveAndSetIRQMask();
+   value = DRV_Reg(addr);
+   drv_reg_dbg_trace(0, line, addr, value);
+   RestoreIRQMask(savedMask);
+   return value;
+}
+
+kal_uint32 drv_reg_dbg_trace_read32(kal_uint16 line, kal_uint32 addr)
+{
+   kal_uint32 value;
+   kal_uint32 savedMask;
+
+   savedMask = SaveAndSetIRQMask();
+   value = DRV_Reg32(addr);
+   drv_reg_dbg_trace(0, line, addr, value);
+   RestoreIRQMask(savedMask);
+   return value;
+}
+
+kal_uint32 drv_reg_dbg_trace_read8(kal_uint16 line, kal_uint32 addr)
+{
+   kal_uint8 value;
+   kal_uint32 savedMask;
+
+   savedMask = SaveAndSetIRQMask();
+   value = DRV_Reg8(addr);
+   drv_reg_dbg_trace(0, line, addr, value);
+   RestoreIRQMask(savedMask);
+   return value;
+}
+
+#endif //__DRV_COMM_REG_DBG__
+
+#if defined(__MTK_TARGET__)
+/* bb reg dump setting */
+EX_BBREG_DUMP devdrv_dump;
+const kal_uint32 devdrv_dump_regions[] = {
+  #if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765)
+  /*Base Address,                length,   type(0/1=byte access, 2=16-bit access, 4=32-bit access)  */
+    BASE_ADDR_MDGPTM,            0x0070, 4,     /*GPT */
+    BASE_MADDR_MDMCU_BUSMON,     0x0C18, 4,
+    BASE_MADDR_MDINFRABUSMON,    0x0C18, 4,
+    BASE_MADDR_MDINFRAMISC, 	 0x0210, 4,
+    BASE_MADDR_LOGTOP,		     0x0200, 4,
+	BASE_ADDR_MML2_QP_APB,		 0x0084, 4,
+	(BASE_ADDR_MML2_QP_APB+0x100),	 0x00BC, 4,
+	(BASE_ADDR_MML2_QP_APB+0x200),	 0x0024, 4,
+	BASE_ADDR_MML2_QP_MEM,		 0x0148, 4,
+	BASE_ADDR_MML2_META_APB,		 0x0170, 4,
+	(BASE_ADDR_MML2_META_APB+0x200),	 0x0058, 4,
+	BASE_ADDR_MML2_META_MEM,		 0x0198, 4,
+	BASE_ADDR_MML2_VRB_MANAGER,	 0x0114, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x200),0x0314, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x700),0x0114, 4,
+	BASE_ADDR_MML2_MMU,		 0x004C, 4,
+	(BASE_ADDR_MML2_MMU+0x80),	 0x0004, 4,
+	(BASE_ADDR_MML2_MMU+0x100),	 0x0014, 4,
+	(BASE_ADDR_MML2_MMU+0x200),	 0x00C4, 4,
+	(BASE_ADDR_MML2_MMU+0x300),	 0x0044, 4,
+	(BASE_ADDR_MML2_MMU+0x400),	 0x0084, 4,
+	BASE_ADDR_MML2_DMA_RD,		 0x00C8, 4,
+	BASE_ADDR_MML2_DMA_WR,		 0x0090, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x100),	 0x00C8, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x200),	 0x00C8, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x300),	 0x00C8, 4,
+	BASE_ADDR_MML2_LHIF,			 0x003C, 4,
+	BASE_ADDR_MML2_CIPHER,		 0x00EC, 4,
+	(BASE_ADDR_MML2_CIPHER+0x800),	 0x013C, 4,
+	BASE_ADDR_MML2_DL_LMAC,		 0x0058, 4,
+	BASE_ADDR_MML2_HARQ_CTRL, 	 0x0028, 4,
+	(BASE_ADDR_MML2_HARQ_CTRL+0x800),	0x0220, 4,
+	BASE_ADDR_MML2_SRAM_WRAP, 	 0x0020, 4,
+	BASE_ADDR_MML2_CFG_TOP,			 0x0060, 4,
+	(BASE_ADDR_MML2_CFG_TOP+0x800),	 0x0008, 4,
+	BASE_ADDR_MML2_BYC,			 0x0030, 4,
+	BASE_ADDR_MCUMMU_MMU, 		 0x004C, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x080), 	 0x0004, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x100), 	 0x0014, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x200), 	 0x00C4, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x300), 	 0x0044, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x400), 	 0x0084, 4,
+	BASE_ADDR_MCUMMU_VRB, 		 0x0024, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x100), 	 0x0014, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x200), 	 0x0014, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x300), 	 0x0014, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x400), 	 0x0014, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x500), 	 0x0014, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x700), 	 0x0014, 4,
+	BASE_ADDR_MCUMMU, 		 0x0178, 4,
+	(BASE_MADDR_MDMCU_PDAMON+0x800), 0x00A0, 4,
+	BASE_ADDR_MCUSYS_ELM_EMI, 		 0x0480, 4,
+	BASE_ADDR_MDINFRA_ELM, 		     0x0480, 4,
+	(0x1f010060), 		     0x0060, 4,
+	(BASE_ADDR_MDPERIMISC+0x70), 		     0x0010, 4, 
+    (BASE_MADDR_USIP_DSPLOG),            0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x100),      0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x200),      0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x300),      0x0100, 4,
+    BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB,     0x0100, 4,
+    BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB,     0x0100, 4,
+    BASE_MADDR_RAKESYS_DSP_SW_LOGGER,    0x0100, 4,
+    BASE_MADDR_MDTOP_PLLMIXED,           0x0700, 4,   /* PLLMIXED */
+    (BASE_MADDR_MDTOP_PLLMIXED+0xC00),   0x0320, 4,   /* PLLMIXED */    
+    BASE_MADDR_MDTOP_CLKSW,              0x0220, 4,   /* CLKSW */  
+    (BASE_MADDR_MDTOP_CLKSW+0xF00),        0x10, 4,   /* CLKSW */ 
+    L1_BASE_ADDR_IDC_CTRL,		 0x0308, 4,	/*IDC_CTRL*/
+    L1_BASE_ADDR_IDC_UART,		 0x00FC, 1,	/*IDC_UART*/
+  #elif defined(MT6295M) || defined(MT3967) || defined(MT6779)
+  /*Base Address,                length,   type(0/1=byte access, 2=16-bit access, 4=32-bit access)  */
+    BASE_ADDR_MDGPTM,            0x00D0, 4,     /*GPT */
+    BASE_MADDR_MDMCU_BUSMON,     0x0C18, 4,
+    BASE_MADDR_MDINFRABUSMON,    0x0C18, 4,
+    BASE_MADDR_MDINFRAMISC, 	 0x0210, 4,
+    BASE_MADDR_LOGTOP,		     0x0200, 4,
+	BASE_ADDR_MML2_QP_APB,		 0x0220, 4,
+	BASE_ADDR_MML2_DLCH_QP_APB,	 0x0220, 4,
+	BASE_ADDR_MML2_QP_MEM,		 0x0148, 4,
+	BASE_ADDR_MML2_META_APB,		 	0x0170, 4,
+	(BASE_ADDR_MML2_META_APB+0x200),	0x0058, 4,
+	BASE_ADDR_MML2_META_MEM,		 	0x01B0, 4,
+	BASE_ADDR_MML2_VRB_MANAGER,	 		0x008C, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x100),	0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x140),	0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x180),	0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x1C0),	0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x200),	0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x240),	0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x280), 0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x2C0), 0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x300), 0x0014, 4,
+	(BASE_ADDR_MML2_VRB_MANAGER+0x340), 0x0014, 4,
+	BASE_ADDR_MML2_MMU, 			0x004C, 4,
+	(BASE_ADDR_MML2_MMU+0x80), 		0x0004, 4,
+	(BASE_ADDR_MML2_MMU+0x100), 	0x0014, 4,
+	(BASE_ADDR_MML2_MMU+0x200),		0x0018, 4,
+	(BASE_ADDR_MML2_MMU+0x2C0),		0x0004, 4,
+	(BASE_ADDR_MML2_MMU+0x300),		0x0010, 4,
+	(BASE_ADDR_MML2_MMU+0x400),		0x0130, 4,
+	(BASE_ADDR_MML2_MMU+0x600),		0x0130, 4,
+	BASE_ADDR_MML2_DMA_RD, 			0x00C8, 4,
+	BASE_ADDR_MML2_DLCH_RDMA,		0x00c8,	4,
+	BASE_ADDR_MML2_DMA_WR, 			0x0030, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x80), 	0x0010, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x100), 	0x0030, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x1C0), 	0x0010, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x200), 	0x0020, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x2C0), 	0x0010, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x300), 	0x0024, 4,
+	(BASE_ADDR_MML2_DMA_WR+0x3C0), 	0x0010, 4,
+	BASE_ADDR_MML2_LHIF,			0x0068, 4,
+	BASE_ADDR_MML2_CIPHER,		 	0x00F4, 4,
+	(BASE_ADDR_MML2_CIPHER+0x800),	0x0150, 4,
+	BASE_ADDR_MML2_DLCH_CIPHER,		 	0x00F4, 4,
+	(BASE_ADDR_MML2_DLCH_CIPHER+0x800),	0x0150, 4,
+	BASE_ADDR_MML2_DL_LMAC,		 		0x0058, 4,
+	BASE_ADDR_MML2_HARQ_CTRL, 	 		0x0028, 4,
+	(BASE_ADDR_MML2_HARQ_CTRL+0x800),	0x0550, 4,
+	BASE_ADDR_MML2_SRAM_WRAP, 	 		0x0020, 4,
+	BASE_ADDR_MML2_CFG_TOP,			 	0x0060, 4,
+	(BASE_ADDR_MML2_CFG_TOP+0x80),	 	0x0008, 4,
+	BASE_ADDR_MML2_BYC, 				0x0030, 4,
+	BASE_ADDR_MCUMMU_MMU, 				0x004C, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x080), 		0x0004, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x100), 		0x0014, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x200), 		0x0018, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x2C0), 		0x0004, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x300), 		0x0010, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x400), 		0x0130, 4,
+	(BASE_ADDR_MCUMMU_MMU+0x600), 		0x0130, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x100), 		0x0010, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x200), 		0x0010, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x300), 		0x0010, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x400), 		0x0010, 4,
+	(BASE_ADDR_MCUMMU_VRB+0x500), 		0x0010, 4,
+	BASE_ADDR_MCUMMU, 		 			0x0094, 4,
+	BASE_MADDR_MML2_ROHC, 				0x004C, 4,
+	BASE_NADDR_MML2_IPF_UL, 			0x00B0, 4,
+	BASE_NADDR_MML2_IPF_DL, 			0x00D0, 4,
+	BASE_NADDR_MML2_IPF_PN, 			0x0030, 4,
+	BASE_NADDR_MML2_IPF_HPCNAT, 		0x00B0, 4,
+	BASE_NADDR_MML2_IPF_SRAM, 			0x0C00, 4,
+	(BASE_MADDR_MDMCU_PDAMON+0x1000), 	0x00A0, 4,
+	BASE_ADDR_MCUSYS_ELM_EMI, 		 	0x0480, 4,
+	BASE_ADDR_MDINFRA_ELM, 		     	0x0480, 4,
+	(0x1f010060), 		     			0x0060, 4,
+	(BASE_ADDR_MDPERIMISC+0x70), 		0x0010, 4, 
+    (BASE_MADDR_USIP_DSPLOG),           0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x100),     0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x200),     0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x300),     0x0100, 4,
+    BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB,    0x0100, 4,
+    BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB,    0x0100, 4,
+    BASE_MADDR_RAKESYS_DSP_SW_LOGGER,   0x0100, 4,
+    BASE_MADDR_MDTOP_PLLMIXED,          0x0700, 4,   /* PLLMIXED */
+    (BASE_MADDR_MDTOP_PLLMIXED+0xC00),  0x0320, 4,   /* PLLMIXED */    
+    BASE_MADDR_MDTOP_CLKSW,             0x0220, 4,   /* CLKSW */  
+    (BASE_MADDR_MDTOP_CLKSW+0xF00),     0x10, 	4,   /* CLKSW */ 
+    L1_BASE_ADDR_IDC_CTRL,		 0x0308, 4,	/*IDC_CTRL*/
+    L1_BASE_ADDR_IDC_UART,		 0x00FC, 1,	/*IDC_UART*/    
+  #elif defined(__MD97__) 
+  /*Base Address,                length,   type(0/1=byte access, 2=16-bit access, 4=32-bit access)  */
+    BASE_ADDR_MDGPTM,            0x00D0, 4,     /*GPT */
+    //BASE_MADDR_MDMCU_BUSMON,     0x0C18, 4,
+    //BASE_MADDR_MDINFRABUSMON,    0x0C18, 4,
+    BASE_MADDR_MDINFRAMISC, 	 0x0210, 4,
+    BASE_MADDR_LOGTOP,		     0x0600, 4,
+	//Start of NRL2
+	BASE_NADDR_NRL2_NRL2_TOP_CFG, 0x128, 4,
+	BASE_NADDR_NRL2_ROHC,		  0x10C, 4,
+	(BASE_NADDR_NRL2_NRL2_QP_UL_LHIF+0x800), 0x1B4, 4,
+	BASE_NADDR_NRL2_NRL2_QP_UL_NR,	0x688, 4,
+	BASE_NADDR_NRL2_NRL2_METADATA_MNG, 0x700, 4,
+	(BASE_NADDR_NRL2_NRL2_METADATA_MNG+0x800), 0x66C, 4,
+	(BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB+0x100), 0x188, 4,
+	BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB, 0x6F0, 4,
+	BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI, 0x118, 4,
+	BASE_NADDR_NRL2_LTEDL_LMAC,	  0x88, 4,
+	BASE_NADDR_NRL2_LTEDL_HARQ,	  0x2C, 4,
+	(BASE_NADDR_NRL2_LTEDL_HARQ+0x400), 0x640, 4,
+	(BASE_NADDR_NRL2_LTEDL_HARQ+0xA40), 0x64, 4,
+	BASE_NADDR_NRL2_NRL2_LHIF,	  0x70,	4,
+	BASE_NADDR_NRL2_NRL2_IPF_UL,  0xB0,	4,
+	BASE_NADDR_NRL2_NRL2_IPF_DL,  0x15C, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH, 0x90, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_HPCNAT,   0xB0, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_RULE,     0x800, 4,
+	(BASE_NADDR_NRL2_NRL2_IPF_RULE+0x800), 0x400, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_LOG,      0x400, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL,   0x300, 4,
+	BASE_NADDR_NRL2_GEN95_QP,          0x240, 4,
+	BASE_NADDR_NRL2_NRL2_DL_UPP,       0x728, 4,
+	(BASE_NADDR_NRL2_NRL2_DL_UPP+0x870),  0x54,  4,
+	(BASE_NADDR_NRL2_NRL2_DL_UPP+0xA00),  0x244, 4,
+	(BASE_NADDR_NRL2_NRL2_DL_UPP+0xEF8),  0x8,   4,
+	BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0, 0xFD8, 4,
+	BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1, 0x68, 4,
+	BASE_NADDR_NRL2_NRL2_CPHR_NR,	     0xED0, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC,   0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_GEN95,	 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF,   0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX,	 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0, 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1, 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR, 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP,	 0x148, 4,
+	BASE_NADDR_NRL2_VRB_MNG,			 0x3D4,	4,
+	BASE_NADDR_NRL2_NRL2_QP_UL_RETX,	 0x22C, 4,
+	BASE_NADDR_NRL2_NRL2_QP_UL_LHIF,	 0x22C, 4,
+	BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0, 0x8, 4,
+	BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1, 0x8, 4,
+	BASE_NADDR_NRL2_NRL2_SRAM_WRAP, 	 0x100, 4,
+	BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP, 	 0xC8,  4,
+	BASE_NADDR_NRL2_DLSYS_5GPL_RDMA,	 0xC8,  4,
+	BASE_NADDR_NRL2_DLSYS_4GPL_RDMA,	 0xC8,  4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0, 0xC8,  4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1, 0xC8,	4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX,   0xC8,  4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF,	 0xC8,	4,
+	BASE_NADDR_NRL2_GEN95_RDMA,			 0xC8,	4,
+	BASE_NADDR_NRL2_NRL2_PPHY,			 0x1C,	4,
+	BASE_NADDR_NRL2_NRL2_MMU,			 0x84,  4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x100),	 0x18,  4,
+    (BASE_NADDR_NRL2_NRL2_MMU+0x200),    0xd0,  4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x300),    0xC,   4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x400),    0x180, 4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x600),    0x170, 4,
+	BASE_NADDR_NRL2_GEN95_CPHR,		     0xF4,  4,
+	(BASE_NADDR_NRL2_GEN95_CPHR+0x800),  0x148,	4,
+	BASE_NADDR_NRL2_GEN95_BYC,			 0x30,	4,
+	BASE_NADDR_NRL2_DLSYS_COPRO_ARB,	 0x7C,	4,
+	(BASE_NADDR_NRL2_DLSYS_COPRO_ARB+0x120), 0xE8, 4,
+	BASE_NADDR_NRL2_DLSYS_5GPL_QP,		 0x44,  4,
+	(BASE_NADDR_NRL2_DLSYS_5GPL_QP+0x104), 0x128, 4,
+	BASE_NADDR_NRL2_DLSYS_4GPL_QP,		 0x44,	4,
+	(BASE_NADDR_NRL2_DLSYS_4GPL_QP+0x104), 0x128, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x100), 0x148, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x300), 0xCC, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x400), 0x48, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x500), 0x2C, 4,
+	//End of NRL2
+	(BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER+0x1C00), 0x00F0, 4,
+	BASE_ADDR_MCUSYS_ELM_EMI, 		 0x0720, 4,
+	BASE_ADDR_MDINFRA_ELM, 		     0x0720, 4,
+#if defined(MT6297)	
+	BASE_ADDR_MDINFRA_ELM_B,         0x0600, 4,
+#endif		
+	(0x1f010060), 		     0x0060, 4,
+	(BASE_ADDR_MDPERIMISC+0x70), 		     0x0010, 4, 
+    (BASE_MADDR_USIP_DSPLOG),            0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x100),      0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x200),      0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x300),      0x0100, 4,
+// 20180315 mark DSPLOG_1PB related regiester due to MT6297 FPGA load build fail
+/*
+    BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB,     0x0100, 4,
+    BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB,     0x0100, 4,
+*/
+    BASE_MADDR_RAKESYS_DSP_SW_LOGGER,    0x0100, 4,
+    BASE_MADDR_MDTOP_PLLMIXED,            0x550, 4,   /* PLLMIXED */
+    (BASE_MADDR_MDTOP_PLLMIXED+0x800),     0x50, 4,  /* PLLMIXED */     
+    (BASE_MADDR_MDTOP_PLLMIXED+0xC00),    0x50, 4,   /* PLLMIXED */  
+    (BASE_MADDR_MDTOP_PLLMIXED+0xD00),    0x10, 4,   /* PLLMIXED */ 
+    (BASE_MADDR_MDTOP_PLLMIXED+0xF00),    0x20, 4,   /* PLLMIXED */    
+    BASE_MADDR_MDTOP_CLKSW,               0x150, 4,   /* CLKSW */ 
+    (BASE_MADDR_MDTOP_CLKSW+0x200),        0x30, 4,   /* CLKSW */
+    (BASE_MADDR_MDTOP_CLKSW+0x300),        0x10, 4,   /* CLKSW */ 
+    (BASE_MADDR_MDTOP_CLKSW+0x400),        0x20, 4,   /* CLKSW */
+    (BASE_MADDR_MDTOP_CLKSW+0x500),        0x10, 4,   /* CLKSW */    
+    (BASE_MADDR_MDTOP_CLKSW+0xF00),        0x10, 4,   /* CLKSW */ 
+    L1_BASE_ADDR_IDC_CTRL,		 0x040C, 4,	/*IDC_CTRL*/  /* 20191104 Grass request to enlarge  */
+    L1_BASE_ADDR_IDC_UART,		 0x0218, 1,	/*IDC_UART*/  /* 20191104 Grass request to enlarge  */
+    BASE_MADDR_CLK_CTRL, 0x20, 4,
+    L1_BASE_MADDR_AO_CONFG, 0x60, 4,
+
+  #elif defined(__MD97P__)
+  /*Base Address,                length,   type(0/1=byte access, 2=16-bit access, 4=32-bit access)  */
+    BASE_ADDR_MDGPTM,            0x00D0, 4,     /*GPT */
+    BASE_MADDR_MDMCU_BUSMON,     0x0C18, 4,
+    BASE_MADDR_MDINFRABUSMON,    0x0C18, 4,
+  /*  BASE_MADDR_MDINFRAMISC, 	 0x0210, 4,  20190805 marked it for avoid build error */
+    BASE_MADDR_LOGTOP,		     0x0600, 4,
+
+// 20190717 for solve build error & FPGA usage , mark most register first
+/* 
+	//Start of NRL2
+	BASE_NADDR_NRL2_NRL2_TOP_CFG, 0x128, 4,
+	BASE_NADDR_NRL2_ROHC,		  0x10C, 4,
+	(BASE_NADDR_NRL2_NRL2_QP_UL_LHIF+0x800), 0x1B4, 4,
+	BASE_NADDR_NRL2_NRL2_QP_UL_NR,	0x688, 4,
+	BASE_NADDR_NRL2_NRL2_METADATA_MNG, 0x700, 4,
+	(BASE_NADDR_NRL2_NRL2_METADATA_MNG+0x800), 0x66C, 4,
+	(BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB+0x100), 0x188, 4,
+	BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB, 0x6F0, 4,
+	BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI, 0x118, 4,
+	BASE_NADDR_NRL2_LTEDL_LMAC,	  0x88, 4,
+	BASE_NADDR_NRL2_LTEDL_HARQ,	  0x2C, 4,
+	(BASE_NADDR_NRL2_LTEDL_HARQ+0x400), 0x640, 4,
+	(BASE_NADDR_NRL2_LTEDL_HARQ+0xA40), 0x64, 4,
+	BASE_NADDR_NRL2_NRL2_LHIF,	  0x70,	4,
+	BASE_NADDR_NRL2_NRL2_IPF_UL,  0xB0,	4,
+	BASE_NADDR_NRL2_NRL2_IPF_DL,  0x15C, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH, 0x90, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_HPCNAT,   0xB0, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_RULE,     0x800, 4,
+	(BASE_NADDR_NRL2_NRL2_IPF_RULE+0x800), 0x400, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_LOG,      0x400, 4,
+	BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL,   0x300, 4,
+	BASE_NADDR_NRL2_GEN95_QP,          0x240, 4,
+	BASE_NADDR_NRL2_NRL2_DL_UPP,       0x728, 4,
+	(BASE_NADDR_NRL2_NRL2_DL_UPP+0x870),  0x54,  4,
+	(BASE_NADDR_NRL2_NRL2_DL_UPP+0xA00),  0x244, 4,
+	(BASE_NADDR_NRL2_NRL2_DL_UPP+0xEF8),  0x8,   4,
+	BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0, 0xFD8, 4,
+	BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1, 0x68, 4,
+	BASE_NADDR_NRL2_NRL2_CPHR_NR,	     0xED0, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC,   0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_GEN95,	 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF,   0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX,	 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0, 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1, 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR, 0x148, 4,
+	BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP,	 0x148, 4,
+	BASE_NADDR_NRL2_VRB_MNG,			 0x3D4,	4,
+	BASE_NADDR_NRL2_NRL2_QP_UL_RETX,	 0x22C, 4,
+	BASE_NADDR_NRL2_NRL2_QP_UL_LHIF,	 0x22C, 4,
+	BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0, 0x8, 4,
+	BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1, 0x8, 4,
+	BASE_NADDR_NRL2_NRL2_SRAM_WRAP, 	 0x100, 4,
+	BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP, 	 0xC8,  4,
+	BASE_NADDR_NRL2_DLSYS_5GPL_RDMA,	 0xC8,  4,
+	BASE_NADDR_NRL2_DLSYS_4GPL_RDMA,	 0xC8,  4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0, 0xC8,  4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1, 0xC8,	4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX,   0xC8,  4,
+	BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF,	 0xC8,	4,
+	BASE_NADDR_NRL2_GEN95_RDMA,			 0xC8,	4,
+	BASE_NADDR_NRL2_NRL2_PPHY,			 0x1C,	4,
+	BASE_NADDR_NRL2_NRL2_MMU,			 0x84,  4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x100),	 0x18,  4,
+    (BASE_NADDR_NRL2_NRL2_MMU+0x200),    0xd0,  4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x300),    0xC,   4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x400),    0x180, 4,
+	(BASE_NADDR_NRL2_NRL2_MMU+0x600),    0x170, 4,
+	BASE_NADDR_NRL2_GEN95_CPHR,		     0xF4,  4,
+	(BASE_NADDR_NRL2_GEN95_CPHR+0x800),  0x148,	4,
+	BASE_NADDR_NRL2_GEN95_BYC,			 0x30,	4,
+	BASE_NADDR_NRL2_DLSYS_COPRO_ARB,	 0x7C,	4,
+	(BASE_NADDR_NRL2_DLSYS_COPRO_ARB+0x120), 0xE8, 4,
+	BASE_NADDR_NRL2_DLSYS_5GPL_QP,		 0x44,  4,
+	(BASE_NADDR_NRL2_DLSYS_5GPL_QP+0x104), 0x128, 4,
+	BASE_NADDR_NRL2_DLSYS_4GPL_QP,		 0x44,	4,
+	(BASE_NADDR_NRL2_DLSYS_4GPL_QP+0x104), 0x128, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x100), 0x148, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x300), 0xCC, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x400), 0x48, 4,
+	(BASE_NADDR_NRL2_NRL2_BUS_SMI+0x500), 0x2C, 4,
+	//End of NRL2
+	(BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER+0x1C00), 0x00F0, 4,
+	BASE_ADDR_MCUSYS_ELM_EMI, 		 0x0480, 4,
+	BASE_ADDR_MDINFRA_ELM, 		     0x0480, 4,
+      #if defined(MT6297)	
+	BASE_ADDR_MDINFRA_ELM_B,         0x0480, 4,
+      #endif		
+	(0x1f010060), 		     0x0060, 4,
+	(BASE_ADDR_MDPERIMISC+0x70), 		     0x0010, 4, 
+    (BASE_MADDR_USIP_DSPLOG),            0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x100),      0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x200),      0x0100, 4,
+    (BASE_MADDR_USIP_DSPLOG+0x300),      0x0100, 4,
+*/
+
+
+    BASE_MADDR_RAKESYS_DSP_SW_LOGGER,    0x0100, 4,
+    BASE_MADDR_MDTOP_PLLMIXED,            0x550, 4,   /* PLLMIXED */
+    (BASE_MADDR_MDTOP_PLLMIXED+0x800),     0x50, 4,  /* PLLMIXED */     
+    (BASE_MADDR_MDTOP_PLLMIXED+0xC00),    0x50, 4,   /* PLLMIXED */  
+    (BASE_MADDR_MDTOP_PLLMIXED+0xD00),    0x10, 4,   /* PLLMIXED */ 
+    (BASE_MADDR_MDTOP_PLLMIXED+0xF00),    0x20, 4,   /* PLLMIXED */    
+    BASE_MADDR_MDTOP_CLKSW,               0x150, 4,   /* CLKSW */ 
+    (BASE_MADDR_MDTOP_CLKSW+0x200),        0x30, 4,   /* CLKSW */
+    (BASE_MADDR_MDTOP_CLKSW+0x300),        0x10, 4,   /* CLKSW */ 
+    (BASE_MADDR_MDTOP_CLKSW+0x400),        0x20, 4,   /* CLKSW */
+    (BASE_MADDR_MDTOP_CLKSW+0x500),        0x10, 4,   /* CLKSW */    
+    (BASE_MADDR_MDTOP_CLKSW+0xF00),        0x10, 4,   /* CLKSW */ 
+    L1_BASE_ADDR_IDC_CTRL,		 0x050C, 4,	/*IDC_CTRL*/
+    L1_BASE_ADDR_IDC_UART,		 0x0218, 1,	/*IDC_UART*/
+    BASE_MADDR_CLK_CTRL, 0x20, 4,
+    L1_BASE_MADDR_AO_CONFG, 0x60, 4,
+  
+  /* end of MD97P */
+
+  #else /* MT6290 */
+    #error "Unsupported Chip"
+    //    0, 0, 0
+  #endif/* MT6290 */
+};
+#endif /* __MTK_TARGET__ */
+
+
+/*To get all customized data*/
+void Drv_Customize_Init(void)
+{
+    DCL_HANDLE chr_usb_det_handle;
+
+    chr_usb_det_handle = Dcl_Chr_Det_Open(DCL_CHR_USB_DET, FLAGS_NONE);
+    Dcl_Chr_Det_Control(chr_usb_det_handle, CHR_DET_CMD_REGISTER_CHR_USB_EINT, NULL);
+    Dcl_Chr_Det_Close(chr_usb_det_handle);
+}
+
+/*************************************************************************
+* FUNCTION
+*   Drv_query_boot_mode
+*
+* DESCRIPTION
+*   Return boot mode.
+*
+* PARAMETERS
+*
+* RETURNS
+*   FACTORY_BOOT, NORMAL_BOOT and USBMS_BOOT
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+boot_mode_type Drv_query_boot_mode(void)
+{
+
+#ifdef __MULTI_BOOT__
+
+
+   if( FACTORY_BOOT == kal_query_boot_mode() )
+      return FACTORY_BOOT;
+
+
+#endif /* __MULTI_BOOT__ */
+
+   return NORMAL_BOOT;
+}
+
+/*************************************************************************
+* FUNCTION
+*   Drv_query_boot_mode_at_init
+*
+* DESCRIPTION
+*   Return boot mode at init stage.
+*   Due to Seamless META feature, we will never into META mode at init stage.
+*
+* PARAMETERS
+*
+* RETURNS
+*   NORMAL_BOOT and USBMS_BOOT
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+boot_mode_type Drv_query_boot_mode_at_init(void)
+{
+
+#ifdef __MULTI_BOOT__
+
+
+
+#endif /* __MULTI_BOOT__ */
+
+   return NORMAL_BOOT;
+}
+
+/*************************************************************************
+* FUNCTION
+*   Drv_PW_Init
+*
+* DESCRIPTION
+*   PW initialization
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void Drv_PW_Init(void)
+{
+
+    //DclBMT_Initialize();
+
+#ifndef __L1_STANDALONE__
+   #ifdef PMIC_PRESENT
+      INT_Trace_Enter(INIT_DRV1_PW);
+            {
+                DCL_HANDLE handle;
+                Dcl_Chr_Det_Initialize();
+                handle=DclPW_Open(DCL_PW, FLAGS_NONE);
+                DclPW_Control(handle, PW_CMD_POWER_INIT, NULL);
+                DclPW_Close(handle);
+            }
+      INT_Trace_Exit(INIT_DRV1_PW);
+
+#if defined(DRV_BMT_HW_PRECC_WORKAROUND)
+    {
+        PW_CTRL_GET_POWERON_REASON CtrlVal;
+        DCL_HANDLE pmu_handle;
+        pmu_handle = DclPW_Open(DCL_PW, FLAGS_NONE);
+        DclPW_Control(pmu_handle, PW_CMD_GET_POWERON_REASON, (DCL_CTRL_DATA_T *)&CtrlVal);
+        if(CtrlVal.powerOnReason == CHRPWRON || CtrlVal.powerOnReason == USBPWRON_WDT ||
+            CtrlVal.powerOnReason == USBPWRON)
+        {
+               // For Pre-cc 3.2~3.3V VCore Drop Issue
+            DclPW_Control(pmu_handle, PW_CMD_POWERON, NULL);
+        }
+        DclPW_Close(pmu_handle);
+    }
+
+#endif
+
+    {
+       DCL_HANDLE handle;
+
+       handle=DclPW_Open(DCL_PW, FLAGS_NONE);
+       DclPW_Control(handle,PW_CMD_POWERON,NULL);
+       DclPW_Close(handle);
+    }
+
+/*
+    if(BMT.PWRon == PWRKEYPWRON)
+        GPTI_BusyWait(Custom_Keypress_Period);
+*/
+   #else    /*PMIC_PRESENT*/
+       DCL_HANDLE handle;
+
+       handle=DclPW_Open(DCL_PW, FLAGS_NONE);
+       DclPW_Control(handle,PW_CMD_POWERON,NULL);
+       DclPW_Close(handle);
+   #endif   /*PMIC_PRESENT*/
+#else /*__L1_STANDALONE__*/
+      {
+       DCL_HANDLE handle;
+
+       handle=DclPW_Open(DCL_PW, FLAGS_NONE);
+       DclPW_Control(handle,PW_CMD_POWERON,NULL);
+       DclPW_Close(handle);
+      }
+#endif   /*__L1_STANDALONE__*/
+}
+
+/*
+* FUNCTION
+*  Drv_Init_Phase1
+*
+* DESCRIPTION
+*     This function is the NFB phase1 (Primary ROM) initial function for
+*     all device drivers.
+*     This function is called once to initialize the device driver.
+*
+* CALLS
+*
+* PARAMETERS
+*  None
+*
+* RETURNS
+*  None
+*
+* GLOBALS AFFECTED
+*   external_global
+*
+* NOTE XXX
+*   All sub functions reference by this function should be placed on
+*   Primary ROM for NFB projects. Or it cannot boot up because Drv_Init()
+*   executed before Secondary ROM loaded.
+*   Please make sure all sub-functions under custom.lib that referenced by
+*   Drv_Init() list in NFB scatter file.
+*/
+
+void Drv_Init_Phase1(void)
+{
+#if defined(MT6297)
+    d2d_init();
+#endif
+
+#if defined(__MD97__) 
+#if defined(__MD97__)
+    csif_init();
+#endif
+#endif //defined(__MD97__)
+
+#if defined (__FPGA__)
+
+/**/
+/* =========== Below is Init Flow of FPGA =============== */
+/**/
+
+    DCL_HANDLE uart_handle;
+    DCL_CTRL_DATA_T data;
+    extern Seriport_HANDLER_T Uart_Drv_Handler;
+
+#if defined(__SCC_SIB_SUPPORT__)
+   // Init SIB Related IP Driver
+   scc_init();
+#endif
+
+    CMIF_Init();
+    CUIF_Init();
+    /* TTY initialization */
+    INT_Trace_Enter(INIT_DRV1_TTY);
+    DclSerialPort_Initialize();
+    INT_Trace_Exit(INIT_DRV1_TTY);
+
+    //int gpt module
+    INT_Trace_Enter(INIT_DRV1_GPTI);
+    DclSGPT_Initialize();
+    INT_Trace_Exit(INIT_DRV1_GPTI);
+
+    //init uart1
+    INT_Trace_Enter(INIT_DRV1_UART1);
+    uart_handle =  DclSerialPort_Open(uart_port1, 0);
+    DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler);
+    DclSerialPort_DrvAttach(uart_handle);
+    DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data);
+    INT_Trace_Exit(INIT_DRV1_UART1);
+
+    // VoLTE core will use UART2 (share UART0)
+    //init uart2
+    INT_Trace_Enter(INIT_DRV1_UART2);
+    uart_handle =  DclSerialPort_Open(uart_port2, 0);
+    DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler);
+    DclSerialPort_DrvAttach(uart_handle);
+    DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data);
+    INT_Trace_Exit(INIT_DRV1_UART2);
+
+#ifdef __HIF_CCCI_SUPPORT__
+   INT_Trace_Enter(INIT_DRV1_CCCI);
+   lte_ccci_hal_init();
+   INT_Trace_Exit(INIT_DRV1_CCCI);
+#endif
+
+#ifdef  __HIF_PCCIF4_SUPPORT__  
+   INT_Trace_Enter(INIT_DRV1_PCCIF4);
+   pccif4_isr_init();
+   INT_Trace_Exit(INIT_DRV1_PCCIF4);
+#endif
+   
+#ifdef  __HIF_PCCIF5_SUPPORT__  
+   INT_Trace_Enter(INIT_DRV1_PCCIF5);
+   pccif5_isr_init();
+   INT_Trace_Exit(INIT_DRV1_PCCIF5);
+#endif
+
+   /* update the system boot mode */
+/*lint -e552*/
+   system_boot_mode = Drv_query_boot_mode_at_init();
+/*lint +e552*/
+      print_boot_mode();
+
+   // 2016/07/26  request by Chi-Yen Yu
+#if !defined(__TCM_ONLY_LOAD__) && !defined(__FLAVOR_BASIC__)
+   prbm_init();
+#endif
+/**/
+/* =========== Above is Init Flow of FPGA =============== */
+/**/
+
+#else     /* Not __FPGA__, means ASIC */
+
+/**/
+/* =========== Below is Init Flow of ASIC  =============== */
+/**/
+
+
+#if defined(DRV_GPT_GPT3) && (!defined(__LTE_RAT__))
+   DCL_HANDLE gpt_handle;
+#endif //defined(DRV_GPT_GPT3)
+#ifndef DRV_RTC_NOT_EXIST
+   DCL_HANDLE rtc_handler;
+#endif //#ifndef DRV_RTC_NOT_EXIST
+
+   DCL_HANDLE uart_handle;
+   DCL_CTRL_DATA_T data;
+   extern Seriport_HANDLER_T Uart_Drv_Handler;
+
+#if defined(__MTK_TARGET__)
+   /* register bb reg dump */
+   devdrv_dump.regions = (kal_uint32*)devdrv_dump_regions;
+   devdrv_dump.num = sizeof(devdrv_dump_regions) / (sizeof(kal_uint32) * 3);
+   devdrv_dump.bbreg_dump_callback = NULL;
+   EX_REGISTER_BBREG_DUMP(&devdrv_dump);
+#endif /* __MTK_TARGET__ */
+
+#ifdef __BACKUP_DOWNLOAD_RESTORE_WITHOUT_BATTERY__
+    if (INT_GetSysStaByCmd(CHK_USB_META_WO_BAT, NULL)==KAL_TRUE)
+    {
+
+#if !defined(CHIP10992)
+        DCL_HANDLE handle;
+        DclPMU_Initialize();
+        handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+        DclPMU_Control(handle, CHR_SET_CHARGE_WITHOUT_BATTERY, NULL);
+        DclPMU_Close(handle);
+#endif
+
+    }
+#endif //#ifdef __BACKUP_DOWNLOAD_RESTORE_WITHOUT_BATTERY__
+
+#if defined(__SCC_SIB_SUPPORT__)
+   // Init SIB Related IP Driver
+   scc_init();
+#endif
+
+   CMIF_Init();
+   CUIF_Init();
+   /* TTY initialization */
+   INT_Trace_Enter(INIT_DRV1_TTY);
+   DclSerialPort_Initialize();
+   INT_Trace_Exit(INIT_DRV1_TTY);
+
+/* 20160921 : according to WCT1_CD2_DSD Chun-Hsien Lu's requirement, remove MTAD relate code */
+   /* attach MTAD driver to TTYcore, if SIB was enabled */
+//#if defined(__SCC_SIB_SUPPORT__)
+//   mtad_driver_attach_to_tty();
+//#endif
+
+#if defined(__DSP_FCORE4__)
+   INT_Trace_Enter(INIT_DRV1_MDCIHW);
+   mdci_hw_init(1,0x0);
+   INT_Trace_Exit(INIT_DRV1_MDCIHW);
+#endif
+
+#ifdef __HIF_CCCI_SUPPORT__
+   INT_Trace_Enter(INIT_DRV1_CCCI);
+   lte_ccci_hal_init();
+   INT_Trace_Exit(INIT_DRV1_CCCI);
+
+   INT_Trace_Enter(INIT_DRV1_OSTD_CCCI_CALLBACK);
+   OSTD_register_ccci_callback();
+   INT_Trace_Exit(ININIT_DRV1_OSTD_CCCI_CALLBACK);
+#endif
+
+#ifdef  __HIF_PCCIF4_SUPPORT__  
+   INT_Trace_Enter(INIT_DRV1_PCCIF4);
+   pccif4_isr_init();
+   INT_Trace_Exit(INIT_DRV1_PCCIF4);
+#endif
+
+#ifdef  __HIF_PCCIF5_SUPPORT__  
+   INT_Trace_Enter(INIT_DRV1_PCCIF5);
+   pccif5_isr_init();
+   INT_Trace_Exit(INIT_DRV1_PCCIF5);
+#endif
+
+#ifdef __HIF_MHCCIF_SUPPORT__
+    INT_Trace_Enter(INIT_DRV1_MHCCIF);
+    mhccif_init();
+    INT_Trace_Exit(INIT_DRV1_MHCCIF);
+#endif
+
+#ifdef __HIF_PCIE_SUPPORT__
+    INT_Trace_Enter(INIT_DRV1_PCIE);
+    hifpcie_init();
+    INT_Trace_Exit(INIT_DRV1_PCIE);
+#endif
+
+#if defined(DRV_EMIMPU)
+   INT_Trace_Enter(INIT_DRV1_EMIMPU);
+   emimpu_init();
+   INT_Trace_Exit(INIT_DRV1_EMIMPU);
+#endif /* DRV_EMIMPU */
+
+#ifndef DRV_PWM_NOT_EXIST
+   INT_Trace_Enter(INIT_DRV1_PWM);
+   DclPWM_Initialize();
+   INT_Trace_Exit(INIT_DRV1_PWM);
+#endif
+
+   /*To get all customized data*/
+   INT_Trace_Enter(INIT_DRV1_CUSTOM);
+
+   Drv_Customize_Init();
+   custom_drv_init();
+
+   INT_Trace_Exit(INIT_DRV1_CUSTOM);
+
+   #if defined(DRV_GPT_GPT3) && (!defined(__LTE_RAT__))
+    INT_Trace_Enter(INIT_DRV1_GPT3);
+    /*turn on gpt3 to count powen on period*/
+    DclFGPT_Initialize();
+    gpt_handle=DclFGPT_Open(DCL_GPT_FreeRUN3,0);
+    DclFGPT_Control(gpt_handle,FGPT_CMD_START,0);
+    DclFGPT_Close(gpt_handle);
+    INT_Trace_Exit(INIT_DRV1_GPT3);
+   #endif
+
+#if 0  /* comment unused code after annouce at 2016/02/02 */
+   #if defined(MULTI_MEDIA_EXIST)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+   #endif /* defined(MULTI_MEDIA_EXIST)*/
+#endif
+
+   #ifdef DRV_MISC_DMA_NO_MEMCPY
+      DRV_MEMCPY = (MEMCPY_FUNC)0x48000150;
+   #elif defined(DRV_MISC_DMA_MEMCPY)
+      DRV_MEMCPY_PTR = (MEMCPY_FUNC)0x48000134;
+   #endif
+
+   INT_Trace_Enter(INIT_DRV1_GPTI);
+   DclSGPT_Initialize();
+   INT_Trace_Exit(INIT_DRV1_GPTI);
+
+   INT_Trace_Enter(INIT_DRV1_WDT);
+   WDT_init();
+   INT_Trace_Exit(INIT_DRV1_WDT);
+
+
+   {
+       // F32K HW init
+       DCL_HANDLE F32K_handle;
+       F32K_handle = DclF32K_Open(DCL_F32K_CLK, FLAGS_NONE);
+       DclF32K_Control(F32K_handle, F32K_CLK_CMD_HW_INIT, (DCL_CTRL_DATA_T *)NULL);
+       DclF32K_Close(F32K_handle);
+   }
+
+#ifndef DRV_RTC_NOT_EXIST
+   // need to set XOSC earlier
+   INT_Trace_Enter(INIT_DRV1_XOSC);
+    rtc_handler = DclRTC_Open(DCL_RTC,FLAGS_NONE);
+   DclRTC_Control(rtc_handler, RTC_CMD_SETXOSC, (DCL_CTRL_DATA_T *)NULL);
+   INT_Trace_Exit(INIT_DRV1_XOSC);
+#endif /*DRV_RTC_NOT_EXIST*/
+
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+#ifdef  __DRV_EXT_ACCESSORY_DETECTION__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif // #ifdef  __DRV_EXT_ACCESSORY_DETECTION__
+#endif 
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */ 
+#if defined(__RESOURCE_MANAGER__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //__RESOURCE_MANAGER__
+#endif
+
+#ifndef DRV_RTC_NOT_EXIST
+#ifdef DRV_RTC_HW_CALI
+   print_bootup_trace_enter(SST_INIT_DRV1_RTCHW);
+   DclRTC_Control(rtc_handler, RTC_CMD_HW_INIT, (DCL_CTRL_DATA_T *)NULL);
+   print_bootup_trace_exit(SST_INIT_DRV1_RTCHW);
+#endif
+#endif /*DRV_RTC_NOT_EXIST*/
+    //DclPW_Initialize();
+
+    DclSPMI_Initialize();
+
+#if !defined(CHIP10992)
+    DclPMU_Initialize();
+#endif
+
+    Drv_PW_Init();
+
+   /* update the system boot mode */
+/*lint -e552*/
+   system_boot_mode = Drv_query_boot_mode_at_init();
+/*lint +e552*/
+      print_boot_mode();
+
+   INT_Trace_Enter(INIT_DRV1_UART1);
+   uart_handle =  DclSerialPort_Open(uart_port1, 0);
+   DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler);
+   DclSerialPort_DrvAttach(uart_handle);
+
+   // Initialization
+
+   DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data);
+   INT_Trace_Exit(INIT_DRV1_UART1);
+
+#if defined(__ANDROID_MODEM__) && !defined(__X_BOOTING__)
+    //in Router product. SUART0 is AP  own, so it should not be init here.
+	UART_PDN_Enable(uart_port2);
+#else
+   // Register the callback function
+   INT_Trace_Enter(INIT_DRV1_UART2);
+   uart_handle =  DclSerialPort_Open(uart_port2, 0);
+   DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler);
+   DclSerialPort_DrvAttach(uart_handle);
+
+   // Initialization
+   DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data);
+   INT_Trace_Exit(INIT_DRV1_UART2);
+#endif
+   #ifdef __UART3_SUPPORT__
+   INT_Trace_Enter(INIT_DRV1_UART3);
+   // Register the callback function
+   uart_handle =  DclSerialPort_Open(uart_port3, 0);
+   DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler);
+   DclSerialPort_DrvAttach(uart_handle);
+   DclSerialPort_Control(uart_handle,SIO_CMD_INIT,(DCL_CTRL_DATA_T *)&data_init);
+   INT_Trace_Exit(INIT_DRV1_UART3);
+   #endif
+
+   // 2016/07/26  request by Chi-Yen Yu
+#if (!defined(__TCM_ONLY_LOAD__) && !defined(__FLAVOR_BASIC__)) || defined(ATEST_DPCOPRO_EN)
+   prbm_init();
+#endif
+/**/
+/* =========== Above is Init Flow of ASIC  =============== */
+/**/
+
+#endif
+}
+
+/*
+* FUNCTION
+*  Drv_Init_Phase2
+*
+* DESCRIPTION
+*     This function is the NFB phase2 (Secondary ROM) initial function for
+*     all device drivers.
+*     This function is called once to initialize the device driver.
+*
+* CALLS
+*
+* PARAMETERS
+*  None
+*
+* RETURNS
+*  None
+*
+* GLOBALS AFFECTED
+*   external_global
+*
+* NOTE XXX
+*   All sub functions reference by this function should be placed on
+*   Secondary ROM for NFB projects.
+*/
+void Drv_Init_Phase2(void)
+{
+
+#if defined (__FPGA__)
+
+/**/
+/* =========== Below is Init Flow of FPGA =============== */
+/**/
+
+
+#if defined(__CMUX_SUPPORT__) || (defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__)))
+    DCL_HANDLE uart_handle;
+#endif /* __CMUX_SUPPORT__ || (__BTMTK__ && (__BT_SPP_PROFILE__ || __BT_HFG_PROFILE__))  */
+
+#if defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__))
+{
+   kal_uint16 i;
+   for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++)
+   {
+      uart_handle =  DclSerialPort_Open((DCL_DEV)i, 0);
+      DclSerialPort_RegisterCallback(uart_handle, &SPPA_Uart_Drv_Handler);
+   }
+}
+#elif defined __CMUX_SUPPORT__
+{
+   kal_uint16 i;
+   for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++)
+   {
+      uart_handle =  DclSerialPort_Open((DCL_DEV)i, 0);
+      DclSerialPort_DrvRegisterCb(uart_handle, &CmuxUart_Drv_Handler);
+      DclSerialPort_DrvAttach(uart_handle);
+   }
+}
+#endif
+
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+   INT_Trace_Enter(INIT_DRV2_SIM);
+   DclSIM_Initialize();
+   INT_Trace_Exit(INIT_DRV2_SIM);
+#endif
+
+
+/**/
+/* =========== Above is Init Flow of FPGA =============== */
+/**/
+
+#else     /* Not __FPGA__, means ASIC */
+
+/**/
+/* =========== Below is Init Flow of ASIC  =============== */
+/**/
+
+#if defined(__CMUX_SUPPORT__) || (defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__)))
+    DCL_HANDLE uart_handle;
+#endif /* __CMUX_SUPPORT__ || (__BTMTK__ && (__BT_SPP_PROFILE__ || __BT_HFG_PROFILE__))  */
+
+#ifndef DRV_RTC_NOT_EXIST
+   DCL_HANDLE rtc_handler;
+#endif /*DRV_RTC_NOT_EXIST*/
+
+#if defined(IC_BURNIN_TEST) || defined(DRV_MISC_GPT1_AS_OS_TICK)
+   /*AB: Enable GPT1 for OS tick in the burn-in test load*/
+   extern void GPT_init(kal_uint8 timerNum, void (*GPT_Callback)(void));
+   extern void GPT_ResetTimer(kal_uint8 timerNum,kal_uint16 countValue,kal_bool autoReload);
+   extern void GPT_Start(kal_uint8 timerNum);
+   GPT_init(1, INT_Timer_Interrupt);
+   GPT_ResetTimer(1, 4, KAL_TRUE);
+   GPT_Start(1);
+#endif //IC_BURNIN_TEST
+
+#if defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__))
+{
+   kal_uint16 i;
+   for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++)
+   {
+      uart_handle =  DclSerialPort_Open((DCL_DEV)i, 0);
+      DclSerialPort_RegisterCallback(uart_handle, &SPPA_Uart_Drv_Handler);
+   }
+}
+#elif defined __CMUX_SUPPORT__
+{
+   kal_uint16 i;
+   for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++)
+   {
+      uart_handle =  DclSerialPort_Open((DCL_DEV)i, 0);
+      DclSerialPort_DrvRegisterCb(uart_handle, &CmuxUart_Drv_Handler);
+      DclSerialPort_DrvAttach(uart_handle);
+   }
+}
+#endif
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+#ifndef DRV_KBD_NOT_EXIST
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /*DRV_KBD_NOT_EXIST*/
+#endif
+
+#ifndef DRV_RTC_NOT_EXIST
+   INT_Trace_Enter(INIT_DRV2_RTCSW);
+    rtc_handler = DclRTC_Open(DCL_RTC,FLAGS_NONE);
+    DclRTC_Control(rtc_handler, RTC_CMD_INIT_TC_AL_INTR, (DCL_CTRL_DATA_T *)NULL);
+   INT_Trace_Exit(INIT_DRV2_RTCSW);
+#endif /*DRV_RTC_NOT_EXIST*/
+
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+   INT_Trace_Enter(INIT_DRV2_SIM);
+   DclSIM_Initialize();
+   INT_Trace_Exit(INIT_DRV2_SIM);
+#endif
+
+#if (defined( DRV_MULTIPLE_SIM) && (!defined(DRV_2_SIM_CONTROLLER)))
+   INT_Trace_Enter(INIT_DRV2_SIMMT6302);
+   sim_MT6302_init();
+   INT_Trace_Exit(INIT_DRV2_SIMMT6302);
+ #endif
+
+#if defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_MSDC)
+
+#else   //defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_MSDC)
+
+#if defined(__MSDC_SD_MMC__)
+   INT_Trace_Enter(INIT_DRV2_MSDC);
+#if !defined(DCL_MSDC_INTERFACE)
+   MSDC_Initialize();
+#else
+   DclSD_Initialize();
+#endif//!defined(DCL_MSDC_INTERFACE)
+   INT_Trace_Exit(INIT_DRV2_MSDC);
+#endif  // defined(__MSDC_SD_MMC__)
+
+#if defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__)
+   INT_Trace_Enter(INIT_DRV2_MSDC2);
+#if !defined(DCL_MSDC_INTERFACE)
+   MSDC_Initialize2();
+#endif//!defined(DCL_MSDC_INTERFACE)
+   INT_Trace_Exit(INIT_DRV2_MSDC2);
+#endif//defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__)
+#endif  //defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_MSDC)
+
+#ifdef IC_MODULE_TEST
+   IC_ModuleTest_Start();
+#endif   /*IC_MODULE_TEST*/
+
+#ifdef MT6218B/*only 6218B has this */
+   GCU_Disable_ReverseBit();
+#endif
+#ifdef __SWDBG_SUPPORT__
+
+   /* initialize SWDBG */
+   INT_Trace_Enter(INIT_DRV2_SWDBG);
+   swdbg_init();
+   INT_Trace_Exit(INIT_DRV2_SWDBG);
+
+#endif   /* __SWDBG_SUPPORT__ */
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+/* under construction !*/
+#if defined(ISP_SUPPORT)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+#ifdef __WIFI_SUPPORT__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif 
+
+#if 0   //There is no I2C driver request for MT6290
+/* under construction !*/
+#if defined(DRV_I2C_25_SERIES)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+/* under construction !*/
+/* under construction !*/
+#if defined(__PXS_ENABLE__) && !defined(IC_MODULE_TEST) && !defined(IC_BURNIN_TEST)
+/* under construction !*/
+#endif // #if defined(__PXS_ENABLE__) && !defined(IC_MODULE_TEST) && !defined(IC_BURNIN_TEST)
+#endif
+
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+#ifdef CAS_SMD_SUPPORT
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+#if 0 // Init BTIF_HWInit_VFIFO(); in bluetooth module
+#if defined(__BTMODULE_MT6236__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(__BTMODULE_MT6256__) || defined(__BTMODULE_MT6276__)
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif // 0
+
+//#ifdef DRV_HIF_SUPPORT
+    //hif_init();
+//#endif
+//#ifdef DRV_SPI_SUPPORT
+    //spi_init();
+//#endif
+#if defined(__TOUCH_PANEL_CAPACITY__)
+   DclSTS_Initialize();
+#endif
+
+#if defined(MOTION_SENSOR_SUPPORT)
+   INT_Trace_Enter(INIT_DRV2_MSENS);
+   motion_sensor_init();
+   INT_Trace_Exit(INIT_DRV2_MSENS);
+#endif
+
+   INT_Trace_Enter(INIT_DRV2_ADC);
+   DclHADC_Initialize();
+   DclSADC_Initialize();
+   INT_Trace_Exit(INIT_DRV2_ADC);
+
+   INT_Trace_Enter(INIT_DRV2_SOE);
+   SOE_Drv_Init();
+   INT_Trace_Exit(INIT_DRV2_SOE);
+
+   EINT_Setting_Init();
+
+#ifdef __HIF_PCIE_SUPPORT__
+   /* Must init after EINT */
+   INT_Trace_Enter(INIT_DRV2_PCIE2);
+   hifpcie_init_2();
+   INT_Trace_Exit(INIT_DRV2_PCIE2);
+#endif
+
+/**/
+/* =========== Above is Init Flow of ASIC  =============== */
+/**/
+
+#endif
+}
+
+/*
+* FUNCTION
+*  Drv_Deinit
+*
+* DESCRIPTION
+*     This function is the deinitial function for all device drivers.
+*     This function is called once to deinitialize the device driver.
+*
+* CALLS
+*
+* PARAMETERS
+*  None
+*
+* RETURNS
+*  None
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+void Drv_Deinit(void)
+{
+   /* Don't do driver deinit when still in system initialization stage.
+      Otherwise it may cause problem in NFI booting. */
+   if (KAL_FALSE == kal_query_systemInit())
+   {
+      custom_drv_deinit();
+#if 0 /* comment unused code after annouce at 2016/02/02 */
+#ifdef  __BTMODULE_MT6601__
+/* under construction !*/
+#endif
+#endif
+   }
+
+   {
+    DCL_HANDLE usb_hcd;
+
+    usb_hcd = DclUSB_HCD_Open(DCL_USB, FLAGS_NONE);
+    DclUSB_HCD_Control(usb_hcd, USB_HCD_CMD_USB_HCD_VBUS_OFF, NULL); // turn off Vbus 5V
+    DclUSB_HCD_Close(usb_hcd);
+   }
+}
+
+#if defined(DRV_MISC_DMA_MEMCPY)
+void DRV_MEMCPY(const void *srcaddr, void *dstaddr, kal_uint32 len)
+{
+   if (!DMA_memcpy(srcaddr,dstaddr,len))
+      DRV_MEMCPY_PTR(srcaddr,dstaddr,len);
+}
+#endif   /*DRV_MISC_DMA_MEMCPY*/
+
+
+kal_bool Drv_WriteReg(kal_uint32 addr, kal_uint16 data)
+{
+#ifdef __LTE_RAT__
+   if (addr < 0xB0000000)
+      return KAL_FALSE;
+#else
+   if (addr < 0x70000000)
+      return KAL_FALSE;
+#endif
+
+   DRV_MISC_WriteReg(addr,data);
+   return KAL_TRUE;
+}
+
+kal_bool Drv_ReadReg(kal_uint32 addr, kal_uint16 *data)
+{
+#ifdef __LTE_RAT__
+   if (addr < 0xB0000000)
+      return KAL_FALSE;
+#else
+   if (addr < 0x70000000)
+      return KAL_FALSE;
+#endif
+
+   *data = DRV_MISC_Reg(addr);
+   return KAL_TRUE;
+}
+
+kal_uint32 drv_get_current_time(void)
+{
+
+#if defined(DRV_MISC_TDMA_NO_TIME)
+   ASSERT(0);
+#endif   /*DRV_MISC_TDMA_NO_TIME*/
+
+#if defined(DRV_MISC_TDMA_TIME_BASE)
+   return (DRV_MISC_Reg32(TDMA_base+0x0230));
+#elif defined(DRV_MISC_TDMA_TIME_BASE_8200)
+    return (DRV_MISC_Reg32(0x82000230));
+#elif defined(DRV_MISC_TDMA_TIME_BASE_8020)
+    return (DRV_MISC_Reg32(0x80200230));
+#elif defined(DRV_MISC_TDMA_TIME_BASE_8406)
+    return (DRV_MISC_Reg32(0x84060230));
+#elif defined(DRV_MISC_TDMA_L1_MACRO)
+    //return (HW_TDMA_GET_32KCNT());
+    // 2014/12/04 , replace 32KCNT function by request of TH Yeh & Hsiao-Hsien Chen
+    return RM_GetF32k();
+#elif defined(DRV_MISC_TOPSM_32K_RTC) /* Get 32K ticks */
+    // 2016/09/01, change to use 32K Tick API provide by low-power team (Owen Ho)
+    //return DRV_MISC_Reg32(BASE_ADDR_MDTOPSM+0x0104);
+    return MD_TOPSM_Get_F32K_Cnt();
+#else
+   return 0;
+#endif
+
+}
+
+kal_uint32 drv_get_duration_tick(kal_uint32 previous_time, kal_uint32 current_time)
+{
+    kal_uint32 result=0;
+#if defined(DRV_MISC_TDMA_NO_TIME)
+   ASSERT(0);
+#endif   /*DRV_MISC_TDMA_NO_TIME*/
+
+    if (previous_time > current_time)
+    {
+//#if defined(DRV_MISC_TDMA_TIME_MAX_80000)
+#if defined(DRV_MISC_TDMA_TIME_MAX_19BITS)
+        result = 0x80000 - previous_time + current_time;
+#elif defined(DRV_MISC_TDMA_TIME_MAX_24BITS)
+      result = 0x1000000 - previous_time + current_time;
+#elif defined(DRV_MISC_TDMA_TIME_MAX_32BITS) || defined(DRV_MISC_TOPSM_32K_RTC)
+      result = 0xFFFFFFFF - previous_time + current_time + 1;
+#else /* use us_counter=>Qbit as tick*/
+      result = 0;
+#endif
+    }
+    else
+    {
+        result = current_time - previous_time;
+    }
+    return result;
+}
+
+kal_uint32 drv_get_duration_ms(kal_uint32 previous_time)
+{
+    kal_uint32 result;
+    kal_uint32 current_time;
+   kal_uint64 temp_value;
+
+    current_time = drv_get_current_time();
+    result = drv_get_duration_tick(previous_time, current_time);
+   /* X ms = result x 1000/32K = (result x 125)>>12 */
+   temp_value = (kal_uint64)(((kal_uint64) result)*125);
+    result = (kal_uint32)(temp_value>>12);
+    return result;
+}
+
+#ifdef DRV_MEMORY_TRACE_DEBUG
+DRV_DBG_STRUCT DRV_DBG_INFO_DATA;
+/*drv_dbg_trace(NAND_READ_START,drv_get_current_time(),0,0);*/
+void drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2)
+{
+   kal_uint32        savedMask;
+   savedMask = SaveAndSetIRQMask();
+   {
+      DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].tag = index;
+      DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].time = time;
+      DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].data1 = data1;
+      DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].data2 = data2;
+      DRV_DBG_INFO_DATA.dbg_data_idx++;
+   }
+   RestoreIRQMask(savedMask);
+}
+#endif   /*DRV_MEMORY_TRACE_DEBUG*/
+
+/*************************************************************************
+   APIs for driver debugging
+*************************************************************************/
+#if 0 //#if defined(__TST_MODULE__)
+#if (!defined(MTK_KAL_MNT))&&(!defined(KAL_ON_OSCAR))&&(!defined(MCD_DLL_EXPORT))&&(!defined(L1_SIM))&&(!defined(__FUE__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* (!defined(MTK_KAL_MNT))&&(!defined(KAL_ON_OSCAR))&&(!defined(MCD_DLL_EXPORT))&&(!defined(L1_SIM))*/
+#endif // #if defined(__TST_MODULE__)
+
+kal_uint8 drv_dummy_return(void)
+{
+   return 0;
+}
+
diff --git a/mcu/driver/devdrv/common/src/devdrv_hisr.c b/mcu/driver/devdrv/common/src/devdrv_hisr.c
new file mode 100644
index 0000000..e941172
--- /dev/null
+++ b/mcu/driver/devdrv/common/src/devdrv_hisr.c
@@ -0,0 +1,427 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *	drv_hisr.c
+ *
+ * Project:
+ * --------
+ *		ALL
+ *
+ * Description:
+ * ------------
+ *   This file is intends for driver HISR management.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#include "kal_public_defs.h"
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "drv_comm.h"
+#include "hisr_config.h"
+#include "drv_hisr.h"
+#include "devdrv_ls.h"
+#include "us_timer.h"
+#include "intrCtrl.h"
+#if defined(__DHL_MODULE__)||defined(__TST_MODULE__)
+  #include "devdrv_trace.h"
+#endif /* __DHL_MODULE__ || __TST_MODULE__ */
+
+/* Debug/Log/Record Configuration */
+#define DEVDRV_HISR_TRACE_ENABLE 1
+#define DEVDRV_HISR_MEASURE_TIME 1
+//#define DEVDRV_DEBUG_TRACE 1
+
+#define MAX_DRV_HISR_DBG_INFO_SIZE 64  /*must be 2^n*/
+
+typedef struct{
+   kal_uint32      time_enter;
+   kal_uint32      time_leave;
+   kal_uint16      tag;
+}DRV_HISR_DBG_DATA;
+
+typedef struct{
+   DRV_HISR_DBG_DATA dbg_data[MAX_DRV_HISR_DBG_INFO_SIZE];
+   kal_uint16        dbg_data_idx;
+}DRV_HISR_DBG_STRUCT;
+
+#if defined(_MAUI_SOFTWARE_LA_)
+#define SWLA_ACTION_LABEL   (2)
+extern void SLA_CustomLogging(kal_char *customJob, kal_int32 saAction);
+#endif
+
+kal_uint32 drv_hisr_status[(MAX_DRV_HISR_DEVICE+31)/32];
+
+#if defined(DEVDRV_HISR_TRACE_ENABLE) && (defined(__DHL_MODULE__)||defined(__TST_MODULE__))
+    #define DEVDRV_TRC(x...)       \
+    do{                            \
+        dhl_trace(x);              \
+    }while(0)
+
+    //remove us/10ms GPT timer monitor
+    kal_uint32 devdrv_hisr_monitor_mask[] = {0xFFCFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
+#else /* DEVDRV_HISR_TRACE_ENABLE && (__DHL_MODULE__ || __TST_MODULE__) */
+    #define DEVDRV_TRC(...)
+#endif /* DEVDRV_HISR_TRACE_ENABLE && (__DHL_MODULE__ || __TST_MODULE__)*/
+#define DEVDRV_TRC_LEVEL TRACE_INFO
+
+/* to measure time */
+#if defined(DEVDRV_HISR_MEASURE_TIME)
+#if defined(__CR4__)
+#include "cp15_int.h"
+#elif defined(__MTK_MMU_V2__)
+#include "mpu_mtk_mmu_v2_int.h"
+#endif
+
+#define IFDEF_DEVDRV_HISR_MEASURE_TIME(x) x
+kal_uint32 drv_hisr_exec_enter_time[MAX_DRV_HISR_DEVICE];
+kal_uint32 drv_hisr_exec_leave_time[MAX_DRV_HISR_DEVICE];
+#else
+#define IFDEF_DEVDRV_HISR_MEASURE_TIME(x)
+#endif /* DEVDRV_HISR_MEASURE_TIME */
+
+void DRV_ERROR_HISR(void);
+
+DRV_HISR_STRUCT DRV_HISR_TABLE[MAX_DRV_HISR_DEVICE];
+DRV_HISR_ID     DRV_CURRENT_HISR;
+
+#if defined(DEVDRV_DEBUG_TRACE)
+DRV_HISR_DBG_STRUCT DRV_HISR_DBG_INFO_DATA;
+
+void drv_hisr_dbg_trace(DRV_HISR_ID index, kal_uint32 time)
+{
+    //kal_uint32 savedMask;
+
+    //savedMask = SaveAndSetIRQMask();
+    if (DRV_UNKNOWN_HISR_ID != index) /* Means it's enter. */
+    {
+       DRV_HISR_DBG_INFO_DATA.dbg_data[DRV_HISR_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_HISR_DBG_INFO_SIZE - 1)].tag = (kal_uint16)index;
+       DRV_HISR_DBG_INFO_DATA.dbg_data[DRV_HISR_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_HISR_DBG_INFO_SIZE - 1)].time_enter = time;
+       DRV_HISR_DBG_INFO_DATA.dbg_data[DRV_HISR_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_HISR_DBG_INFO_SIZE - 1)].time_leave = 0;
+    }
+    else /* Means it's leave. */
+    {
+       DRV_HISR_DBG_INFO_DATA.dbg_data[DRV_HISR_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_HISR_DBG_INFO_SIZE - 1)].time_leave = time;
+       DRV_HISR_DBG_INFO_DATA.dbg_data_idx++;
+    }
+
+    //RestoreIRQMask(savedMask);
+}
+#else  /* DEVDRV_DEBUG_TRACE */
+#define drv_hisr_dbg_trace(x...)
+#endif /* DEVDRV_DEBUG_TRACE */
+
+
+void DRV_ERROR_HISR(void)
+{
+   ASSERT(0);
+}
+
+void DRV_Register_HISR(DRV_HISR_ID hisr_id, VOID_FUNC hisr_func)
+{
+   ASSERT(hisr_id < MAX_DRV_HISR_DEVICE);
+   DRV_HISR_TABLE[hisr_id].hisr_func = hisr_func;
+}
+
+// For fix 35 MGM platform over 60 q-bit issue
+DEVDRV_LS_INTERNCODE void DRV_HISR(void)
+{
+   kal_uint16 index;
+   kal_uint32 savedMask;
+#if defined(_MAUI_SOFTWARE_LA_)
+   kal_char   swla_label[4] = "DH ";
+#endif
+
+   if (drv_hisr_status[0] != 0)
+      index = 0;
+   else if (drv_hisr_status[1] != 0)
+      index = 32;
+   else
+      return;
+
+   while(index<(kal_uint16)MAX_DRV_HISR_DEVICE)
+   {
+      kal_bool bit_mask;
+      kal_uint32 index_shift;
+      kal_uint32 status_index;
+      
+      bit_mask = KAL_FALSE;
+      index_shift = 1<<(index%32);
+      status_index = index>>5;
+      if(drv_hisr_status[status_index] & index_shift)
+      {
+         bit_mask = KAL_TRUE;
+      }
+      if (bit_mask == KAL_TRUE)
+      {
+         DRV_HISR_STRUCT *hisr_pointer;
+
+         hisr_pointer = DRV_HISR_TABLE+index;
+         ASSERT(hisr_pointer->hisr_count!=0);
+         DRV_CURRENT_HISR = (DRV_HISR_ID)index;
+#if defined(DEVDRV_HISR_TRACE_ENABLE)&&(__DHL_MODULE__ || __TST_MODULE__)
+         if(devdrv_hisr_monitor_mask[status_index] & index_shift)
+         {
+            DEVDRV_TRC(DEVDRV_TRC_LEVEL, 0, DEVDRV_CURRENT_HISR_ID, (kal_uint32)index);
+         }
+#endif /* DEVDRV_HISR_TRACE_ENABLE */
+         savedMask = SaveAndSetIRQMask();
+#if defined(_MAUI_SOFTWARE_LA_)
+         swla_label[2] += index;
+         SLA_CustomLogging(swla_label, SWLA_ACTION_LABEL);
+#endif
+         hisr_pointer->hisr_count--;
+         if (hisr_pointer->hisr_count == 0)
+         {
+            drv_hisr_status[status_index] &= ~(index_shift);
+            if (drv_hisr_status[status_index] == 0)
+            {
+                index |= 0x1F;
+            }
+         }
+         RestoreIRQMask(savedMask);
+         drv_hisr_dbg_trace(DRV_CURRENT_HISR, ust_get_current_time());
+#if defined(__CR4__)
+         IFDEF_DEVDRV_HISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(drv_hisr_exec_enter_time[DRV_CURRENT_HISR]));
+#elif defined(__MTK_MMU_V2__)
+         IFDEF_DEVDRV_HISR_MEASURE_TIME(drv_hisr_exec_enter_time[DRV_CURRENT_HISR]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
+#endif
+         hisr_pointer->hisr_func();
+#if defined(__CR4__)
+         IFDEF_DEVDRV_HISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(drv_hisr_exec_leave_time[DRV_CURRENT_HISR]));
+#elif defined(__MTK_MMU_V2__)                  
+         IFDEF_DEVDRV_HISR_MEASURE_TIME(drv_hisr_exec_leave_time[DRV_CURRENT_HISR]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
+#endif
+         drv_hisr_dbg_trace(DRV_UNKNOWN_HISR_ID, ust_get_current_time());
+         DRV_CURRENT_HISR = DRV_UNKNOWN_HISR_ID;
+      }//if (bit_mask == KAL_TRUE)
+      index++;
+   } //while(index<(kal_uint16)MAX_DRV_HISR_DEVICE)
+}
+
+void drv_hisr_init(void)
+{
+   kal_uint32 index;
+
+   ASSERT(MAX_DRV_HISR_DEVICE <= (DRV_HISR_ID)64);
+   for(index=0;index<(kal_uint32)MAX_DRV_HISR_DEVICE;index++)
+   {
+      DRV_HISR_TABLE[index].hisr_func = DRV_ERROR_HISR;
+      DRV_HISR_TABLE[index].hisr_count = 0;
+   }
+}
+
+#if !defined(__FUE__) && !defined(__UBL__)
+
+DEVDRV_LS_INTSRAM_ROCODE void drv_active_hisr(DRV_HISR_ID id)
+{
+    kal_uint32 savedMask;
+    
+    savedMask = SaveAndSetIRQMask();
+    drv_hisr_status[id>>5] |= 1UL<<(id&0x1FUL);
+
+    DRV_HISR_TABLE[id].hisr_count++;
+
+    RestoreIRQMask(savedMask);
+    kal_activate_hisr_index(DRVHISR);
+}
+#endif
+
+