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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/cuif/cuif_test/inc/cuif_test.h b/mcu/driver/devdrv/cuif/cuif_test/inc/cuif_test.h
new file mode 100644
index 0000000..dd11f23
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/inc/cuif_test.h
@@ -0,0 +1,233 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CUIF_TEST_H__
+#define __CUIF_TEST_H__
+
+#include "ssdvt_typedef.h"
+#include "drv_cuif.h"
+#include "dsp_header_define_cuif_inner_brp.h"
+#include "dsp_header_define_cuif_fec_wbrp.h"
+#include "cuif_l1core_public.h"
+
+/*******************************************************************************
+* Macros
+*******************************************************************************/
+#if defined(__CORE_USIP__)
+#define SSDVT_CUIF_CLZ(z) KAL_INTRINSIC_CLZ((z))
+#define SSDVT_CUIF_GET_LSB(b) (31 - CUIF_CLZ((b) & -(b)))
+#else
+#define SSDVT_CUIF_CLZ(z) __builtin_clz((z))
+#define SSDVT_CUIF_GET_LSB(b) (31 - SSDVT_CUIF_CLZ((b) & -(b)))
+#endif
+
+
+#define SSDVT_CUIF_EXCHANGE_CLIENT_NUMBER(c) c = (c)?0:1;
+
+/*******************************************************************************
+* CUIF Memory Definition
+*******************************************************************************/
+
+/* CR4 Side */
+
+#define SSDVT_CUIF_USIP0_MEM_SIZE 0x4000
+#if defined(__MD95__)
+#define SSDVT_CUIF_USIP1_MEM_SIZE 0x2400
+#else
+#define SSDVT_CUIF_USIP1_MEM_SIZE 0xc00
+#endif
+
+#define SSDVT_CUIF_INTERRUPT_SIZE 32
+#define SSDVT_CUIF_INTERRUPT_WAIT_LOOP_COUNT 1000
+
+// for the most handsome iger.
+#define SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN 0x39383938
+
+#if !defined(__MD32S_SSDVT_RTLCOSIM__)
+#define SSDVT_CUIF_SYNC_MEM_SIZE 8
+#else /* __MD32S_SSDVT_RTLCOSIM__ */
+#define SSDVT_CUIF_SYNC_MEM_SIZE (8 + SSDVT_RTLCOSIM_SIZE)
+#endif /* __MD32S_SSDVT_RTLCOSIM__ */
+
+/*******************************************************************************
+* CUIF Interrupt Register Information
+*******************************************************************************/
+#define SSDVT_CUIF_C2U_U0_CHECK_MEM_OFFSET (0x0)
+#define SSDVT_CUIF_C2U_U1_CHECK_MEM_OFFSET (0x4)
+#define SSDVT_CUIF_C2U_U2_CHECK_MEM_OFFSET (0x8)
+#define SSDVT_CUIF_C2U_U3_CHECK_MEM_OFFSET (0xc)
+
+#define SSDVT_CUIF_U2C_N0_CHECK_MEM_OFFSET (0x10)
+#define SSDVT_CUIF_U2C_N1_CHECK_MEM_OFFSET (0x14)
+#define SSDVT_CUIF_U2C_N2_CHECK_MEM_OFFSET (0x18)
+#define SSDVT_CUIF_U2C_N3_CHECK_MEM_OFFSET (0x1c)
+#define SSDVT_CUIF_U2C_N4_CHECK_MEM_OFFSET (0x20)
+
+#if defined(__MD95__)
+
+#define SSDVT_CUIF_U2C_N5_CHECK_MEM_OFFSET (0x24)
+#define SSDVT_CUIF_U2C_N6_CHECK_MEM_OFFSET (0x28)
+
+#define SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET (0x2C)
+#define SSDVT_CUIF_U2C_N5_WFI_CHECK_MEM_OFFSET (0x30)
+#define SSDVT_CUIF_U2C_N6_WFI_CHECK_MEM_OFFSET (0x34)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define SSDVT_CUIF_U2C_N5_CHECK_MEM_OFFSET (0x24)
+#define SSDVT_CUIF_U2C_N6_CHECK_MEM_OFFSET (0x28)
+#define SSDVT_CUIF_U2C_N7_CHECK_MEM_OFFSET (0x30)
+#define SSDVT_CUIF_U2C_N8_CHECK_MEM_OFFSET (0x34)
+#define SSDVT_CUIF_U2C_N9_CHECK_MEM_OFFSET (0x38)
+#define SSDVT_CUIF_U2C_N10_CHECK_MEM_OFFSET (0x3C)
+#define SSDVT_CUIF_U2C_N11_CHECK_MEM_OFFSET (0x40)
+#define SSDVT_CUIF_U2C_N12_CHECK_MEM_OFFSET (0x44)
+#define SSDVT_CUIF_U2C_N13_CHECK_MEM_OFFSET (0x48)
+
+#define SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET (0x50)
+#define SSDVT_CUIF_U2C_N1_WFI_CHECK_MEM_OFFSET (0x54)
+#define SSDVT_CUIF_U2C_N2_WFI_CHECK_MEM_OFFSET (0x58)
+#define SSDVT_CUIF_U2C_N3_WFI_CHECK_MEM_OFFSET (0x5C)
+#define SSDVT_CUIF_U2C_N4_WFI_CHECK_MEM_OFFSET (0x60)
+#define SSDVT_CUIF_U2C_N5_WFI_CHECK_MEM_OFFSET (0x64)
+#define SSDVT_CUIF_U2C_N6_WFI_CHECK_MEM_OFFSET (0x68)
+#define SSDVT_CUIF_U2C_N7_WFI_CHECK_MEM_OFFSET (0x6C)
+#define SSDVT_CUIF_U2C_N8_WFI_CHECK_MEM_OFFSET (0x70)
+#define SSDVT_CUIF_U2C_N9_WFI_CHECK_MEM_OFFSET (0x74)
+#define SSDVT_CUIF_U2C_N10_WFI_CHECK_MEM_OFFSET (0x78)
+#define SSDVT_CUIF_U2C_N11_WFI_CHECK_MEM_OFFSET (0x80)
+#define SSDVT_CUIF_U2C_N12_WFI_CHECK_MEM_OFFSET (0x84)
+#define SSDVT_CUIF_U2C_N13_WFI_CHECK_MEM_OFFSET (0x88)
+
+#else
+
+#define SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET (0x24)
+#define SSDVT_CUIF_U2C_N4_WFI_CHECK_MEM_OFFSET (0x28)
+
+#endif
+
+
+
+/*******************************************************************************
+* Function prototypes
+*******************************************************************************/
+/**
+ * @note CUIF(CR4-MD32) test, it would test CR4 to MD32, MD32 to CR4 and two cores writing concurrently.
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_CUIF_Test(void);
+
+#endif /* __CUIF_TEST_H__ */
diff --git a/mcu/driver/devdrv/cuif/cuif_test/inc/memory_test.h b/mcu/driver/devdrv/cuif/cuif_test/inc/memory_test.h
new file mode 100644
index 0000000..19bc101
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/inc/memory_test.h
@@ -0,0 +1,315 @@
+#ifndef __MEMORY_TEST_H__
+#define __MEMORY_TEST_H__
+
+#include "ssdvt_typedef.h"
+
+/*******************************************************************************
+* Macros
+*******************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#define SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(value, expect_value) \
+ do{ \
+ if((value) != (expect_value)){ \
+ ERROR_LOOP; \
+ } \
+ }while(0);
+
+/*******************************************************************************
+* Definitions
+*******************************************************************************/
+/* reduce test buffer size in simulation to save simulation time */
+#if defined(__SIMULATION__)
+#define SSDVT_MEM_TEST_BUFFER_SIZE 0x80
+#else
+#define SSDVT_MEM_TEST_BUFFER_SIZE 0x1000
+#endif
+
+/*******************************************************************************
+* Typedefes
+*******************************************************************************/
+typedef enum SSDVT_MEM_TestType_t{
+ SSDVT_MEM_NO_TEST_TYPE = 0x0,
+ SSDVT_MEM_MD32_TEST_TYPE = 0x1,
+ SSDVT_MEM_CMIF_TEST_TYPE = 0x2,
+ SSDVT_MEM_CUIF_TEST_TYPE = 0x3
+}SSDVT_MEM_TestType;
+
+typedef struct {
+ ssdvt_uint32_p base_addr; // the begin memory address of xxif
+ ssdvt_uint32 size; // the size of xxif by byte
+ ssdvt_uint32_p sync; // xxif status register
+}SSDVT_MEM_MemInfo;
+
+typedef SSDVT_MEM_MemInfo* SSDVT_MEM_MemInfo_ptr;
+
+typedef void (*SSDVT_MEM_BarrierSyncFun)(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+typedef ssdvt_uint32 (*SSDVT_MEM_TestCaseFun)(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+ssdvt_uint32 SSDVT_MEM_Test();
+
+
+/**
+ * basic test (SRAM base).
+ *
+ * the function would test 0x00000000 and 0xFFFFFFFF.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_basic_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * Full size test (SRAM base).
+ *
+ * the function would write the whole size and check the whole size.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_full_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_half_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * @note It would test write memory bidirection, client 0/1 would write XXIF concurrently.
+ * Then client 0 and client 1 check the memory together.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] check_all_client Unused parameter
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/* random test */
+/**
+ * random test.
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_random_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * random test.
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_random_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+/**
+ * random test.
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_random_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+
+/**
+ * Init test (fill with 0x0).
+ *
+ * the function would write data randomly and check the writing action.
+ *
+ * Each test case is in the form of the action of write to memory and check
+ * memory(read). After each read action and write action, it would call read
+ * sync function and write sync function.
+ *
+ * @param[in] client if `client` is 1, it would write the test case
+ * @param[in] check_all_client 1: the client 0 and client 1 would check the test case.
+ * 0: only clien 0 would check the test case
+ * @param[in] xxif XXIF base memory address, size and size
+ * @param[in] read_sync sync function for each read action
+ * @param[in] write_sync sync function for each write action
+ *
+ * @retval 0 test successly
+ * @retval otherwise no return
+ */
+ssdvt_uint32 SSDVT_MEM_init_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync);
+
+#endif /* __MEMORY_TEST_H__ */
diff --git a/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_header.h b/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_header.h
new file mode 100644
index 0000000..97f7106
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_header.h
@@ -0,0 +1,9 @@
+#ifndef __SSDVT_HEADER_H__
+#define __SSDVT_HEADER_H__
+
+#include <stdio.h>
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_util.h"
+
+#endif /* __SSDVT_HEADER_H__ */
diff --git a/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_typedef.h b/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_typedef.h
new file mode 100644
index 0000000..847fa22
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_typedef.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * Typedefs.h
+ *
+ * Project:
+ * --------
+ * Device Test
+ *
+ * Description:
+ * ------------
+ * Type definition.
+ *
+ * Author:
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+ /**
+ * @file typedefs.h
+ * @brief this file defines the basic types of SSDVT
+ *
+ */
+#ifndef __SSDVT_TYPEDEF_H__
+#define __SSDVT_TYPEDEF_H__
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef unsigned long int ssdvt_uint32;
+typedef long int ssdvt_int32;
+typedef unsigned short int ssdvt_uint16;
+typedef short int ssdvt_int16;
+typedef unsigned char ssdvt_uint8;
+typedef char ssdvt_int8;
+typedef char ssdvt_char;
+typedef ssdvt_uint32 ssdvt_size_t;
+
+typedef volatile ssdvt_uint8* ssdvt_uint8_p;
+typedef volatile ssdvt_int8* ssdvt_int8_p;
+typedef volatile ssdvt_uint16* ssdvt_uint16_p;
+typedef volatile ssdvt_int16* ssdvt_int16_p;
+typedef volatile ssdvt_uint32* ssdvt_uint32_p;
+typedef volatile ssdvt_int32* ssdvt_int32_p;
+
+#endif /* !__TYPEDEFS_H_ */
+
diff --git a/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_util.h b/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_util.h
new file mode 100644
index 0000000..54bc436
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/inc/ssdvt_util.h
@@ -0,0 +1,107 @@
+#ifndef __SSDVT_UTIL_H__
+#define __SSDVT_UTIL_H__
+
+/*******************************************************************************
+* Included header files
+*******************************************************************************/
+#include "ssdvt_typedef.h"
+
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#define SSDVT_MD32_CHECK (defined(__CORE_BRP__) || defined(__CORE_RAKE__) || defined(__CORE_DFE__))
+
+
+#define NO_DBG /* force to use printf */
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+#if defined(__CORE_BRP__)
+// set base addr
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0x1000 - 0x8)
+#elif defined(__CORE_RAKE__)
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0xC00 - 0x8)
+#elif defined(__CORE_DFE__)
+#define SSDVT_RTLCOSIM_ADDR_BASE (0xD0358000 + 0x800 - 0x8)
+#else /* __CORE_DFE__ __CORE_RAKE__ __CORE_BRP__ */
+ #error "not support for the md32 processor"
+#endif /* __CORE_DFE__ __CORE_RAKE__ __CORE_BRP__ */
+
+/**
+ * SSDVT_RTLCOSIM_NOTIFICATION_SIZE
+ * - unit: bytes
+ * SSDVT_RTLCOSIMA_STATUS: (*SSDVT_RTLCOSIM_NOTIFICATION_ADDR + 0) : 4 bytes
+ * - 0: Not finish
+ * - 1: Success
+ * - 2: Fail
+ * SSDVT_RTLCOSIM_ERROR_PC: (*SSDVT_RTLCOSIM_NOTIFICATION_ADDR + 4) : 4 bytes
+ * - If test status fails (== 2), the error pc responds the LR
+ */
+#define SSDVT_RTLCOSIM_SIZE 8
+#define SSDVT_RTLCOSIM_STATUS ((volatile ssdvt_uint32 *)(SSDVT_RTLCOSIM_ADDR_BASE+0x0000))
+#define SSDVT_RTLCOSIM_ERROR_PC ((volatile ssdvt_uint32 *)(SSDVT_RTLCOSIM_ADDR_BASE+0x0004))
+#endif /* __MD32S_SSDVT_RTLCOSIM__ */
+
+/*******************************************************************************
+ * Macro
+ *******************************************************************************/
+#define dbg_print(str, args...)
+
+#if !defined(__MD32S_SSDVT_RTLCOSIM__)
+#define ERROR_LOOP \
+ do { \
+ ssdvt_test_fail_notification(); \
+ } while(0);
+
+
+#else /* !__MD32S_SSDVT_RTLCOSIM__ */
+#define ERROR_LOOP \
+ do { \
+ ssdvt_test_fail_notification(); \
+ } while(0);
+#endif /* !__MD32S_SSDVT_RTLCOSIM__ */
+
+#define ERROR_LOOP_MSG(msg) \
+ do { \
+ dbg_print(msg); \
+ ERROR_LOOP \
+ } while(0)
+
+#define SSDVT_ERROR_HANDLER(msg) \
+ do { \
+ while(1); \
+ } while(0)
+
+#define SSDVT_DELAY_LOOP(count) \
+ do { \
+ volatile unsigned int delay; \
+ for (delay = (unsigned int)count; delay != 0; delay--) \
+ /* NOP */ \
+ ; \
+ }while (0)
+
+#define SSDVT_ASSERT_EQ(a, b) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d\n", __FILE__, __LINE__, (a), (b)); \
+ ERROR_LOOP \
+ } \
+ }while(0);
+
+#define SSDVT_ASSERT_EQ_MSG(a, b, msg) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d"msg"\n", __FILE__, __LINE__, (a), (b)); \
+ ERROR_LOOP \
+ } \
+ }while(0);
+
+#define SSDVT_SET_CURRENT_STATUS(status) \
+ do{ \
+ ssdvt_set_current_status((status)); \
+ }while(0)
+
+void ssdvt_set_current_status(ssdvt_uint32 status);
+extern void ssdvt_test_fail_notification();
+extern void ssdvt_test_pass_notification();
+
+#endif /* __SSDVT_UTIL_H__ */
diff --git a/mcu/driver/devdrv/cuif/cuif_test/src/cuif_test.c b/mcu/driver/devdrv/cuif/cuif_test/src/cuif_test.c
new file mode 100644
index 0000000..bd90c76
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/src/cuif_test.c
@@ -0,0 +1,282 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(__SSDVT_CUIF_TEST__)
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+#include "memory_test.h"
+#include "cuif_test.h"
+
+/*******************************************************************************
+* Global vairable
+*******************************************************************************/
+// list all test cases
+SSDVT_MEM_TestCaseFun cuif_test_case[] = {SSDVT_MEM_basic_test_XXIF,
+ SSDVT_MEM_full_size_test_XXIF,
+ SSDVT_MEM_half_size_test_XXIF,
+ SSDVT_MEM_interleave_test_base_8_XXIF,
+ SSDVT_MEM_interleave_test_base_16_XXIF,
+ SSDVT_MEM_interleave_test_base_32_XXIF,
+ SSDVT_MEM_init_test_XXIF,
+ };
+
+ssdvt_uint32 cuif_test_case_size = sizeof(cuif_test_case)/ sizeof(SSDVT_MEM_TestCaseFun);
+ssdvt_uint32 ssdvt_cuif_interrupt_enter = 0xFFFFFFFF;
+ssdvt_uint32 ssdvt_cuif_interrupt_test_case_num;
+
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+extern SSDVT_MEM_TestType ssdvt_mem_test_type;
+extern ssdvt_uint32 ssdvt_mem_test_current_status_base;
+extern ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+
+/*******************************************************************************
+* Function
+*******************************************************************************/
+extern void cuif_test_sync(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+extern void SSDVT_CUIF_InterruptTestInternal_L1core(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* en_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+extern void SSDVT_CUIF_InterruptTestInternal_USIP(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* en_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+
+ssdvt_uint32 cuif_test_internal(ssdvt_uint32 client,
+ const ssdvt_uint32 check_by_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info)
+{
+ // Assume USIP would initial client with 0.
+ ssdvt_uint32 i;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 1);
+
+ // Start to test
+ dbg_print("cuif test wait for staring...");
+ cuif_test_sync(client, mem_info->sync);
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 2);
+
+ dbg_print("cuif test starts ...");
+ for(i=0; i<cuif_test_case_size; ++i){
+ ssdvt_mem_test_mem_range_num = i + 1;
+ /* Master */
+ SSDVT_CUIF_EXCHANGE_CLIENT_NUMBER(client)
+ (*cuif_test_case[i])(client, check_by_all_client, mem_info, cuif_test_sync, cuif_test_sync);
+
+ /* Slave */
+ SSDVT_CUIF_EXCHANGE_CLIENT_NUMBER(client)
+ (*cuif_test_case[i])(client, check_by_all_client, mem_info, cuif_test_sync, cuif_test_sync);
+ }
+
+ ssdvt_mem_test_mem_range_num = 0x0;
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 3);
+
+ return 0;
+}
+
+void SSDVT_CUIF_RamTest() {
+#if defined(__CORE_USIP__)
+ /* USIP side */
+ extern void SSDVT_CUIF_RamTest_USIP();
+ SSDVT_CUIF_RamTest_USIP();
+#else
+ /* L1core side */
+ extern void SSDVT_CUIF_RamTest_USIP0();
+ SSDVT_CUIF_RamTest_USIP0();
+#endif
+}
+
+/*******************************************************************************
+* CUIF Interrupt Test
+*******************************************************************************/
+void SSDVT_CUIF_InterruptTestInternal(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* en_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync)
+{
+ // master == 1: send interrupt
+ // master == 0: receive interrupt
+#if defined(__CORE_USIP__)
+ SSDVT_CUIF_InterruptTestInternal_USIP(master, irq_set, en_set, irq_check, sync);
+#else
+ SSDVT_CUIF_InterruptTestInternal_L1core(master, irq_set, en_set, irq_check, sync);
+#endif
+}
+
+
+void SSDVT_CUIF_InterruptTest()
+{
+#if defined(__CORE_USIP__)
+ /* USIP side */
+ extern void SSDVT_CUIF_InterruptTest_USIP();
+ SSDVT_CUIF_InterruptTest_USIP();
+#else
+ /* L1core side */
+ extern void SSDVT_CUIF_InterruptTest_L1core();
+ SSDVT_CUIF_InterruptTest_L1core();
+#endif
+}
+
+void SSDVT_CUIF_TestPreprocess()
+{
+#if defined(__CORE_USIP__)
+ if (!KAL_CURRENT_THREAD_ID) // inner & fec
+ {
+ extern void SSDVT_CUIF_sync_addr_init();
+ SSDVT_CUIF_sync_addr_init();
+ }
+ extern void SSDVT_CUIF_disable_all_int_USP();
+ SSDVT_CUIF_disable_all_int_USP();
+#else
+ extern void SSDVT_CUIF_disable_all_int_L1core();
+ SSDVT_CUIF_disable_all_int_L1core();
+#endif
+}
+
+void SSDVT_CUIF_REG_TEST()
+{
+#if defined(__CORE_USIP__)
+ extern void SSDVT_CUIF_REG_TEST_USIP();
+ SSDVT_CUIF_REG_TEST_USIP();
+#else
+ extern void SSDVT_CUIF_REG_TEST_L1core();
+ SSDVT_CUIF_REG_TEST_L1core();
+#endif
+}
+ssdvt_uint32 SSDVT_CUIF_Test(void)
+{
+ SSDVT_CUIF_TestPreprocess();
+
+ SSDVT_CUIF_REG_TEST();
+
+ /* Ram test */
+ SSDVT_CUIF_RamTest();
+
+ /* interrupt test*/
+ SSDVT_CUIF_InterruptTest();
+
+ return 0;
+}
+
+#define SSDVT_CUIF_TEST_SUCCESS_PATTERN 0x39383938
+
+unsigned int ssdvt_cuif_test_success = 0;
+unsigned int ssdvt_cuif_test_enter = 0;
+unsigned int ssdvt_cuif_test_success_while_value = 1;
+
+void SS_MD32_CUIF_TestSuccess(){
+ ssdvt_cuif_test_success = SSDVT_CUIF_TEST_SUCCESS_PATTERN;
+
+ ssdvt_test_pass_notification();
+ while(ssdvt_cuif_test_success_while_value == 1);
+}
+
+void SS_MD32_CUIF_Test(){
+
+ ssdvt_cuif_test_enter = 0x1;
+
+ SSDVT_CUIF_Test();
+
+ SS_MD32_CUIF_TestSuccess();
+
+}
+#endif /* __SSDVT_CUIF_TEST__ */
+
diff --git a/mcu/driver/devdrv/cuif/cuif_test/src/cuif_test_l1core.c b/mcu/driver/devdrv/cuif/cuif_test/src/cuif_test_l1core.c
new file mode 100644
index 0000000..1921ccd
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/src/cuif_test_l1core.c
@@ -0,0 +1,1873 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *
+ *
+ * Project:
+ * --------
+ *
+ *
+ * Description:
+ * ------------
+ *
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if defined(__SSDVT_CUIF_TEST__)
+
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+#include "memory_test.h"
+#include "cuif_test.h"
+#include "intrCtrl.h"
+#include "sync_data.h"
+#include "drv_comm.h"
+
+/*******************************************************************************
+* Interrrupt Registers
+*******************************************************************************/
+/* USIP part */
+
+#define SSDVT_CUIF_USIP0_MEM_BASE_ADDR (CUIF_INNER_BRP_BASE)
+
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD98__)
+
+#define SSDVT_CUIF_USIP1_MEM_BASE_ADDR (CUIF_FEC_SS_BASE)
+
+#else
+
+#define SSDVT_CUIF_USIP1_MEM_BASE_ADDR (CUIF_FEC_WBRP_BASE)
+
+#endif
+
+#define SSDVT_CUIF_C2U_INNER_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_C2U_INNER_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_C2U_INNER_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_C2U_INNER_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_C2U_INNER_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_C2U_INNER_EN_SET ((volatile ssdvt_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_C2U_INNER_EN_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_C2U_OUTER_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_OUTER_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_C2U_OUTER_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_C2U_OUTER_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_C2U_OUTER_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_OUTER_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_C2U_OUTER_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_OUTER_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_C2U_OUTER_EN_SET ((volatile ssdvt_uint32*)(CUIF_C2U_OUTER_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_C2U_OUTER_EN_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_OUTER_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_C2U_FEC_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_FEC_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_C2U_FEC_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_C2U_FEC_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_C2U_FEC_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_FEC_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_C2U_FEC_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_FEC_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_C2U_FEC_EN_SET ((volatile ssdvt_uint32*)(CUIF_C2U_FEC_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_C2U_FEC_EN_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_FEC_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_C2U_SPEECH_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_SPEECH_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_C2U_SPEECH_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_C2U_SPEECH_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_C2U_SPEECH_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_SPEECH_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_C2U_SPEECH_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_C2U_SPEECH_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_C2U_SPEECH_EN_SET ((volatile ssdvt_uint32*)(CUIF_C2U_SPEECH_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_C2U_SPEECH_EN_CLR ((volatile ssdvt_uint32*)(CUIF_C2U_SPEECH_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N0_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N0_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N0_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N0_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N0_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N0_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N0_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET))
+
+
+#define SSDVT_CUIF_U2C_N1_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N1_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N1_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N1_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N1_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N1_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N1_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N1_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N1_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N1_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N1_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N1_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N2_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N2_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N2_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N2_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N2_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N2_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N2_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N2_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N2_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N2_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N2_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N2_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N3_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N3_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N3_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N3_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N3_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N3_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N3_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N3_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N3_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N3_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N3_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N3_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N4_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N4_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N4_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N4_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N4_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N4_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N4_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N4_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N4_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N4_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N4_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N4_INTERRUPT_EN_CLR_OFFSET))
+
+
+#if defined(__MD95__)
+
+#define SSDVT_CUIF_U2C_N5_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N5_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N5_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N5_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N5_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N5_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N6_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N6_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N6_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N6_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N6_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N6_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET))
+
+#endif
+
+
+#if defined(__MD97__) || defined(__MD97P__)
+
+#define SSDVT_CUIF_U2C_N5_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N5_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N5_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N5_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N5_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N5_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N6_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N6_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N6_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N6_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N6_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N6_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N7_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N7_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N7_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N7_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N7_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N7_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N7_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N7_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N7_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N7_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N7_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N7_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N8_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N8_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N8_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N8_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N8_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N8_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N8_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N8_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N8_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N8_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N8_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N8_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N9_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N9_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N9_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N9_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N9_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N9_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N9_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N9_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N9_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N9_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N9_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N9_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N10_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N10_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N10_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N10_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N10_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N10_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N10_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N10_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N10_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N10_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N10_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N10_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N11_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N11_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N11_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N11_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N11_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N11_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N11_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N11_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N11_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N11_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N11_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N11_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N12_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N12_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N12_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N12_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N12_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N12_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N12_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N12_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N12_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N12_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N12_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N12_INTERRUPT_EN_CLR_OFFSET))
+
+#define SSDVT_CUIF_U2C_N13_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N13_INTERRUPT_STATUS_OFFSET))
+#define SSDVT_CUIF_U2C_N13_STATUS_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N13_INTERRUPT_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N13_STATUS_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N13_INTERRUPT_CLEAR_OFFSET))
+#define SSDVT_CUIF_U2C_N13_EN_STATUS ((volatile ssdvt_uint32*)(CUIF_U2C_N13_INTERRUPT_EN_OFFSET))
+#define SSDVT_CUIF_U2C_N13_EN_SET ((volatile ssdvt_uint32*)(CUIF_U2C_N13_INTERRUPT_EN_SET_OFFSET))
+#define SSDVT_CUIF_U2C_N13_EN_CLR ((volatile ssdvt_uint32*)(CUIF_U2C_N13_INTERRUPT_EN_CLR_OFFSET))
+
+#endif
+
+
+#define SSDVT_CUIF_USIP0_C2U_U0_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U0_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_C2U_U1_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U1_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_C2U_U2_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U2_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_C2U_U3_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U3_CHECK_MEM_OFFSET))
+
+#define SSDVT_CUIF_USIP0_U2C_N0_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N1_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N1_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N2_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N2_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N3_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N3_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N4_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_CHECK_MEM_OFFSET))
+
+#if defined(__MD95__)
+
+#define SSDVT_CUIF_USIP0_U2C_N5_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N6_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_CHECK_MEM_OFFSET))
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define SSDVT_CUIF_USIP0_U2C_N5_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N6_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N7_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N7_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N8_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N8_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N9_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N9_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N10_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N10_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N11_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N11_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N12_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N12_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N13_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N13_CHECK_MEM_OFFSET))
+
+#endif
+
+#define SSDVT_CUIF_USIP0_U2C_N0_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET))
+
+#if defined(__MD95__)
+
+#define SSDVT_CUIF_USIP0_U2C_N5_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N6_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_WFI_CHECK_MEM_OFFSET))
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define SSDVT_CUIF_USIP0_U2C_N0_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N1_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N1_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N2_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N2_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N3_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N3_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N4_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N5_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N6_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N7_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N7_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N8_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N8_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N9_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N9_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N10_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N10_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N11_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N11_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N12_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N12_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP0_U2C_N13_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N13_WFI_CHECK_MEM_OFFSET))
+
+#else
+
+#define SSDVT_CUIF_USIP0_U2C_N4_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_WFI_CHECK_MEM_OFFSET))
+
+#endif
+
+#define SSDVT_CUIF_USIP0_SYNC_ADDR ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP0_MEM_BASE_ADDR + SSDVT_CUIF_USIP0_MEM_SIZE - SSDVT_CUIF_SYNC_MEM_SIZE))
+
+#define SSDVT_CUIF_USIP1_C2U_U0_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U0_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_C2U_U1_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U1_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_C2U_U2_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U2_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_C2U_U3_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_C2U_U3_CHECK_MEM_OFFSET))
+
+#define SSDVT_CUIF_USIP1_U2C_N0_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N1_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N1_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N2_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N2_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N3_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N3_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N4_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_CHECK_MEM_OFFSET))
+
+#if defined(__MD95__)
+
+#define SSDVT_CUIF_USIP1_U2C_N5_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N6_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_CHECK_MEM_OFFSET))
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define SSDVT_CUIF_USIP1_U2C_N0_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N1_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N1_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N2_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N2_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N3_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N3_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N4_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N5_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N6_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N7_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N7_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N8_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N8_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N9_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N9_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N10_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N10_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N11_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N11_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N12_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N12_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N13_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N13_CHECK_MEM_OFFSET))
+
+#endif
+
+
+#define SSDVT_CUIF_USIP1_U2C_N0_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET))
+
+#if defined(__MD95__)
+
+#define SSDVT_CUIF_USIP1_U2C_N5_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N6_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_WFI_CHECK_MEM_OFFSET))
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define SSDVT_CUIF_USIP1_U2C_N0_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N0_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N1_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N1_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N2_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N2_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N3_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N3_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N4_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N5_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N5_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N6_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N6_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N7_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N7_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N8_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N8_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N9_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N9_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N10_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N10_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N11_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N11_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N12_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N12_WFI_CHECK_MEM_OFFSET))
+#define SSDVT_CUIF_USIP1_U2C_N13_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N13_WFI_CHECK_MEM_OFFSET))
+
+#else
+
+#define SSDVT_CUIF_USIP1_U2C_N4_WFI_CHECK ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_U2C_N4_WFI_CHECK_MEM_OFFSET))
+
+#endif
+
+#define SSDVT_CUIF_USIP1_SYNC_ADDR ((volatile ssdvt_uint32*)(SSDVT_CUIF_USIP1_MEM_BASE_ADDR + SSDVT_CUIF_USIP1_MEM_SIZE - SSDVT_CUIF_SYNC_MEM_SIZE))
+
+/*******************************************************************************
+* Global variables
+*******************************************************************************/
+/**
+ * define CUIF base address(.base_addr), size(.size) and status register (.sync)
+ */
+SSDVT_MEM_MemInfo cuif_usip0 = {.base_addr= (ssdvt_uint32_p)SSDVT_CUIF_USIP0_MEM_BASE_ADDR,
+ .size= (ssdvt_uint32)(SSDVT_CUIF_USIP0_MEM_SIZE - SSDVT_CUIF_SYNC_MEM_SIZE),
+ .sync= (ssdvt_uint32_p)SSDVT_CUIF_USIP0_SYNC_ADDR
+ };
+
+SSDVT_MEM_MemInfo cuif_usip1 = {.base_addr= (ssdvt_uint32_p)SSDVT_CUIF_USIP1_MEM_BASE_ADDR,
+ .size= (ssdvt_uint32)(SSDVT_CUIF_USIP1_MEM_SIZE - SSDVT_CUIF_SYNC_MEM_SIZE),
+ .sync= (ssdvt_uint32_p)SSDVT_CUIF_USIP1_SYNC_ADDR
+ };
+
+
+ssdvt_uint32 ssdvt_cuif_usip_core_testing = 0;
+ssdvt_uint32 ssdvt_cuif_usip_module_testing = 0;
+ssdvt_uint32 ssdvt_cuif_wfi_testing = 0;
+
+
+ssdvt_uint32 cuif_c2u_int_source_num[CUIF_ENUM_ALL_USIP_INT_NUM] =
+{
+ CUIF_NUM_INTERRUPT_INNER_SOURCES,
+ CUIF_NUM_INTERRUPT_OUTER_SOURCES,
+ CUIF_NUM_INTERRUPT_FEC_SOURCES,
+ CUIF_NUM_INTERRUPT_SPEECH_SOURCES
+};
+
+ssdvt_uint32 cuif_u2c_int_source_num[CUIF_ENUM_ALL_MCU_INT_NUM - 1] =
+{
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES,
+#if defined(__MD95__)
+ CUIF_MCU_INT_N5_SOURCES,
+ CUIF_MCU_INT_N6_SOURCES,
+#endif
+#if defined(__MD97__) || defined(__MD97P__)
+ CUIF_MCU_INT_N5_SOURCES,
+ CUIF_MCU_INT_N6_SOURCES,
+ CUIF_MCU_INT_N7_SOURCES,
+ CUIF_MCU_INT_N8_SOURCES,
+ CUIF_MCU_INT_N9_SOURCES,
+ CUIF_MCU_INT_N10_SOURCES,
+ CUIF_MCU_INT_N11_SOURCES,
+ CUIF_MCU_INT_N12_SOURCES,
+ CUIF_MCU_INT_N13_SOURCES,
+#endif
+};
+
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+extern SSDVT_MEM_TestType ssdvt_mem_test_type;
+extern ssdvt_uint32 ssdvt_mem_test_current_status_base;
+extern ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+extern ssdvt_uint32 ssdvt_cuif_interrupt_test_case_num;
+
+
+/*******************************************************************************
+* Function prototypes
+*******************************************************************************/
+void cuif_test_sync(const ssdvt_uint32 client,
+ const ssdvt_uint32_p sync);
+
+extern ssdvt_uint32 cuif_test_internal(ssdvt_uint32 client,
+ const ssdvt_uint32 check_by_all_client,
+ const SSDVT_MEM_MemInfo_ptr mem_info);
+
+extern void SSDVT_CUIF_InterruptTestInternal(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* en_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync);
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+void cuif_test_sync(const ssdvt_uint32 client, const ssdvt_uint32_p sync)
+{
+ // MCU Part
+ while(sync[0] == 1);
+ sync[0] = 1;
+
+ while(sync[1] == 0);
+ sync[1] = 0;
+}
+#if defined(__MD95__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0 //6 bits WFI
+#else
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFF0
+#endif
+#define EN_ALL_MASK 0xFFFFFFFF
+
+void SSDVT_CUIF_disable_all_int_L1core()
+{
+#if defined(__MD93__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+#elif defined(__MD95__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+#elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+#endif
+}
+
+
+void CUIF_U2C_ENABLE_REG_TEST()
+{
+ ssdvt_uint32 write_mask = 0;
+ ssdvt_uint32 total_mask = 0;
+ ssdvt_uint32 get_mask = 0;
+ cuif_uint8 nID = 0;
+ cuif_uint8 irq_num = 0;
+
+ for (nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ for(irq_num = 0; irq_num < cuif_u2c_int_source_num[nID]; irq_num++)
+ {
+ write_mask = 1 << irq_num;
+ total_mask |= write_mask;
+ // set enable reg by bit
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(nID), write_mask);
+ get_mask = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET(nID));
+ SSDVT_ASSERT_EQ(get_mask, total_mask);
+ }
+
+ for(irq_num = 0; irq_num < cuif_u2c_int_source_num[nID]; irq_num++)
+ {
+ write_mask = 1 << irq_num;
+ total_mask &= ~(write_mask);
+ // clear enable reg by bit
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(nID), write_mask);
+ get_mask = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET(nID));
+ SSDVT_ASSERT_EQ(get_mask, total_mask);
+ }
+ SSDVT_ASSERT_EQ(get_mask, 0x0);
+ dbg_print("n %d enable reg test - Pass\n", nID);
+ }
+
+}
+
+
+void CUIF_U2C_STATUS_REG_TEST()
+{
+ ssdvt_uint32 write_mask = 0;
+ ssdvt_uint32 total_mask = 0;
+ ssdvt_uint32 get_mask = 0;
+ cuif_uint8 nID = 0;
+ cuif_uint8 irq_num = 0;
+
+ for (nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+#if defined(__MD95__)
+ irq_num = (0 == nID || 5 == nID || 6 == nID) ? 6 : 0;
+#elif defined(__MD97__) || defined(__MD97P__)
+ irq_num = 6;
+#else
+ irq_num = (0 == nID || 4 == nID) ? 4 : 0;
+#endif
+ for(; irq_num < cuif_u2c_int_source_num[nID]; irq_num++)
+ {
+ write_mask = 1 << irq_num;
+ total_mask |= write_mask;
+ // set status by bit
+ CUIF_REG_WRITE(CUIF_U2C_SET_BASE + REG_OFFSET(nID), write_mask);
+ get_mask = CUIF_REG_READ(CUIF_U2C_STATUS_BASE + REG_OFFSET(nID));
+ SSDVT_ASSERT_EQ(get_mask, total_mask);
+ }
+#if defined(__MD95__)
+ irq_num = (0 == nID || 5 == nID || 6 == nID) ? 6 : 0;
+#elif defined(__MD97__) || defined(__MD97P__)
+ irq_num = 6;
+#else
+ irq_num = (0 == nID || 4 == nID) ? 4 : 0;
+#endif
+
+ for(; irq_num < cuif_u2c_int_source_num[nID]; irq_num++)
+ {
+ write_mask = 1 << irq_num;
+ total_mask &= ~(write_mask);
+ // clear status by bit
+ CUIF_REG_WRITE(CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), write_mask);
+ get_mask = CUIF_REG_READ(CUIF_U2C_STATUS_BASE + REG_OFFSET(nID));
+ SSDVT_ASSERT_EQ(get_mask, total_mask);
+ }
+
+ SSDVT_ASSERT_EQ(get_mask, 0x0);
+ dbg_print("n %d status reg test - Pass\n", nID);
+ }
+
+}
+
+void SSDVT_CUIF_REG_TEST_L1core()
+{
+ CUIF_U2C_ENABLE_REG_TEST();
+ CUIF_U2C_STATUS_REG_TEST();
+}
+
+
+void SSDVT_CUIF_RamTest_USIP0()
+{
+ cuif_test_internal(0, 1, &cuif_usip0);
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 0xFF);
+}
+
+void SSDVT_CUIF_RamTest_USIP1()
+{
+ ssdvt_mem_test_current_status_base = 0x2000;
+ ssdvt_mem_test_type = SSDVT_MEM_CUIF_TEST_TYPE;
+ ssdvt_mem_test_mem_range_num = 0x0;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base);
+
+ cuif_test_internal(0, 1, &cuif_usip1);
+
+ /* reset test type */
+ ssdvt_mem_test_type = SSDVT_MEM_NO_TEST_TYPE;
+ ssdvt_mem_test_current_status_base = 0x0;
+ ssdvt_mem_test_mem_range_num = 0x0;
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 0xFF);
+}
+
+
+/*******************************************************************************
+* CUIF Interrupt Test
+*******************************************************************************/
+
+void SSDVT_CUIF_L1_WAKEUP_USIP()
+{
+
+ switch (ssdvt_cuif_usip_module_testing)
+ {
+ case CUIF_ENUM_INNER:
+ // send c2u interrupt to to wake up usip
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_INNER_EN_SET, 0x1);
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_INNER_STATUS_SET, 0x1);
+ break;
+ case CUIF_ENUM_OUTER:
+ // send c2u interrupt to to wake up usip
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_OUTER_EN_SET, 0x1);
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_OUTER_STATUS_SET, 0x1);
+ break;
+#define CUIF_ENUM_USIP_USER2 CUIF_ENUM_SPEECH
+ case CUIF_ENUM_USIP_USER2:
+#undef CUIF_ENUM_USIP_USER2
+ // send c2u interrupt to to wake up usip
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_FEC_EN_SET, 0x1);
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_FEC_STATUS_SET, 0x1);
+ break;
+#define CUIF_ENUM_USIP_USER3 CUIF_ENUM_FEC
+ case CUIF_ENUM_USIP_USER3:
+#undef CUIF_ENUM_USIP_USER3
+ // send c2u interrupt to to wake up usip
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_SPEECH_EN_SET, 0x1);
+ CUIF_REG_WRITE(SSDVT_CUIF_C2U_SPEECH_STATUS_SET, 0x1);
+ break;
+ default:
+ dbg_print("strange module when wfi testing, check it\n");
+ ERROR_LOOP;
+ break;
+
+ }
+
+
+}
+
+#if defined(__MD95__) || defined(__MD93__)
+void SSDVT_CUIF_InterruptTestISR_N0()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N0_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N0_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N0_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N0_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N0_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N0_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N0_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N1()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N1_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N1_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N1_EN_CLR, status);
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N1_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N1_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N2()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N2_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N2_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N2_EN_CLR, status);
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N2_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N2_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N3()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N3_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N3_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N3_EN_CLR, status);
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N3_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N3_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+}
+#if defined(__MD95__)
+void SSDVT_CUIF_InterruptTestISR_N4()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N4_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N4_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N4_EN_CLR, status);
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N4_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N4_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N5()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N5_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N5_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N5_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N5_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N5_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N5_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N5_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N6()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N6_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N6_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N6_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N6_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N6_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N6_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N6_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+
+#else
+void SSDVT_CUIF_InterruptTestISR_N4()
+{
+ ssdvt_uint32 status;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N4_STATUS);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N4_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N4_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N4_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N4_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N4_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N4_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+#endif
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+ssdvt_uint32 ISR_enter=0x6297;
+ssdvt_uint32 ISR_pattern=0x62970;
+ssdvt_uint32 ISR_sta=0xF00;
+
+void SSDVT_CUIF_InterruptTestISR_N0()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 0;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N0_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N0_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N0_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N0_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N0_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N0_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N0_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62970;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N0_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62971;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N1()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 1;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N1_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N1_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N1_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N1_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N1_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N1_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N1_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62972;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N1_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62973;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N2()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 2;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N2_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N2_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N2_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N2_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N2_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N2_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N2_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62974;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N2_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62975;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N3()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 3;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N3_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N3_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N3_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N3_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N3_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N3_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N3_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62976;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N3_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62977;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N4()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 4;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N4_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N4_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N4_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N4_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N4_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N4_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N4_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62978;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N4_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62979;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N5()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 5;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N5_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N5_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N5_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N5_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N5_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N5_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N5_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6297a;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N5_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6297b;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N6()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 6;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N6_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N6_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N6_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N6_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N6_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N6_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N6_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6297c;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N6_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6297d;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N7()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 7;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N7_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N7_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N7_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N7_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N7_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N7_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N7_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6297e;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N7_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6297f;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N8()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 8;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N8_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N8_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N8_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N8_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N8_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N8_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N8_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62980;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N8_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62981;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N9()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 9;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N9_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N9_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N9_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N9_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N9_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N9_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N9_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62982;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N9_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62983;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N10()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 10;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N10_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N10_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N10_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N10_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N10_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N10_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N10_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62984;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N10_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62985;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N11()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 11;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N11_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N11_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N11_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N11_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N11_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N11_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N11_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62986;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N11_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62987;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N12()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 12;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N12_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N12_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N12_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N12_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N12_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N12_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N12_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62988;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N12_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x62989;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+
+void SSDVT_CUIF_InterruptTestISR_N13()
+{
+ ssdvt_uint32 status;
+ ISR_enter = 13;
+ status = CUIF_REG_READ(SSDVT_CUIF_U2C_N13_STATUS);
+ ISR_sta = CUIF_REG_READ(SSDVT_CUIF_U2C_N13_STATUS + 0xc);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N13_STATUS_CLR, status);
+ CUIF_REG_WRITE(SSDVT_CUIF_U2C_N13_EN_CLR, status);
+
+ if (ssdvt_cuif_wfi_testing == 0) {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N13_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N13_CHECK, SSDVT_CUIF_GET_LSB(status)+1);
+ }
+ }
+ else {
+ if (ssdvt_cuif_usip_core_testing == 0) {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP0_U2C_N13_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6298a;
+ }
+ else {
+ CUIF_REG_WRITE(SSDVT_CUIF_USIP1_U2C_N13_WFI_CHECK, SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN);
+ ISR_pattern=0x6298b;
+ }
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+ }
+}
+#endif
+
+ssdvt_uint32 SSDVT_get_irq_num_L1core(volatile ssdvt_uint32* irq_check)
+{
+ ssdvt_uint32 irq_num = 0;
+ if (SSDVT_CUIF_USIP0_C2U_U0_CHECK == irq_check) {
+ irq_num = CUIF_NUM_INTERRUPT_INNER_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_C2U_U1_CHECK == irq_check) {
+ irq_num = CUIF_NUM_INTERRUPT_OUTER_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP1_C2U_U2_CHECK == irq_check) {
+ irq_num = CUIF_NUM_INTERRUPT_FEC_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP1_C2U_U3_CHECK == irq_check) {
+ irq_num = CUIF_NUM_INTERRUPT_SPEECH_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N0_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N0_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N0_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N1_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N1_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N1_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N2_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N2_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N2_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N3_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N3_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N3_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N4_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N4_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N4_SOURCES;
+ }
+#if defined(__MD95__)
+ else if (SSDVT_CUIF_USIP0_U2C_N5_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N5_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N5_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N6_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N6_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N6_SOURCES;
+ }
+#elif defined(__MD97__) || defined(__MD97P__)
+ else if (SSDVT_CUIF_USIP0_U2C_N5_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N5_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N5_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N6_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N6_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N6_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N7_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N7_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N7_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N8_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N8_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N8_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N9_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N9_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N9_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N10_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N10_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N10_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N11_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N11_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N11_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N12_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N12_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N12_SOURCES;
+ }
+ else if (SSDVT_CUIF_USIP0_U2C_N13_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N13_CHECK == irq_check) {
+ irq_num = CUIF_MCU_INT_N13_SOURCES;
+ }
+#endif
+ else
+ {
+ dbg_print("strange irq check, check it\n");
+ ERROR_LOOP;
+ }
+
+ return irq_num;
+}
+
+
+void SSDVT_CUIF_InterruptTestInternal_L1core(ssdvt_uint32 master,
+ volatile ssdvt_uint32* irq_set,
+ volatile ssdvt_uint32* en_set,
+ volatile ssdvt_uint32* irq_check,
+ volatile ssdvt_uint32* sync)
+{
+ // master == 1: send interrupt
+ // master == 0: receive interrupt
+
+ volatile ssdvt_uint32 i;
+ volatile ssdvt_uint32 wait;
+ volatile ssdvt_uint32 irq_bits_num = SSDVT_get_irq_num_L1core(irq_check);
+
+ if(master == 1){
+ *(irq_check) = 0xFFFFFFFF;
+
+ // send interrupt
+ for(i = 0; i < irq_bits_num; ++i){
+ SSDVT_SET_CURRENT_STATUS(0xB000 + ssdvt_cuif_interrupt_test_case_num + i);
+ dbg_print(".... send interrupt %d ... ", i);
+
+ // start sync
+ cuif_test_sync(0, sync);
+
+ *(irq_set) = (1 << i);
+
+ // make sure before enable, the interrupt won't be triggerred
+ SSDVT_DELAY_LOOP(SSDVT_CUIF_INTERRUPT_WAIT_LOOP_COUNT);
+
+ if(*(irq_check) != i+1){
+ dbg_print("enable test ok\n");
+ }
+ else{
+ dbg_print("enable test fail\n");
+ ERROR_LOOP;
+ }
+
+ *(en_set) = (1 << i);
+
+
+ wait = SSDVT_CUIF_INTERRUPT_WAIT_LOOP_COUNT;
+ do{
+ wait--;
+ }while(wait != 0 && *(irq_check) != i+1);
+
+ if(*(irq_check) == i+1){
+ dbg_print("success\n");
+ }
+ else{
+ dbg_print("error\n");
+ ERROR_LOOP;
+ }
+
+ // end sync
+ cuif_test_sync(0, sync);
+ }
+ }
+ else{
+#if defined(__MD97__) || defined(__MD97P__)
+ // All vpe skip wfi 6 bits
+ i = 6;
+#else
+#if defined(__MD95__)
+ // N0/N5/N6 skip wfi 6 bits
+ if (SSDVT_CUIF_USIP0_U2C_N0_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N0_CHECK == irq_check
+ || SSDVT_CUIF_USIP0_U2C_N5_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N5_CHECK == irq_check
+ || SSDVT_CUIF_USIP0_U2C_N6_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N6_CHECK == irq_check) {
+ i = 6;
+ }
+#else
+ // N0, N4, skip wfi 4 bits
+ if (SSDVT_CUIF_USIP0_U2C_N0_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N0_CHECK == irq_check
+ || SSDVT_CUIF_USIP0_U2C_N4_CHECK == irq_check || SSDVT_CUIF_USIP1_U2C_N4_CHECK == irq_check) {
+ i = 4;
+ }
+#endif
+ else {
+ i = 0;
+ }
+#endif
+ // receive interrupt
+ for(; i < irq_bits_num; ++i){
+ SSDVT_SET_CURRENT_STATUS(0xB000 + ssdvt_cuif_interrupt_test_case_num + i);
+ dbg_print(".... recive interrupt %d ... ", i);
+
+ // start sync
+ cuif_test_sync(0, sync);
+
+ while(*(irq_check) != i+1);
+
+ // check interrupt enter in order
+ SSDVT_ASSERT_EQ(*(irq_check), i+1);
+ dbg_print("success\n");
+
+ // end sync
+ cuif_test_sync(0, sync);
+ }
+ *(irq_check) = 0;
+ }
+}
+
+void SSDVT_CUIF_InterruptTestRegisterISR_L1CORE()
+{
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N0 , SSDVT_CUIF_InterruptTestISR_N0, "SSDVT_CUIF_U2C_N0");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N0 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N0);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N1 , SSDVT_CUIF_InterruptTestISR_N1, "SSDVT_CUIF_U2C_N1");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N1 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N1);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N2 , SSDVT_CUIF_InterruptTestISR_N2, "SSDVT_CUIF_U2C_N2");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N2 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N2);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N3 , SSDVT_CUIF_InterruptTestISR_N3, "SSDVT_CUIF_U2C_N3");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N3 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N3);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N4 , SSDVT_CUIF_InterruptTestISR_N4, "SSDVT_CUIF_U2C_N4");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N4 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N4);
+
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N5 , SSDVT_CUIF_InterruptTestISR_N5, "SSDVT_CUIF_U2C_N5");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N5 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N5);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N6 , SSDVT_CUIF_InterruptTestISR_N6, "SSDVT_CUIF_U2C_N6");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N6 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N6);
+
+#if defined(__MD97__) || defined(__MD97P__)
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N7 , SSDVT_CUIF_InterruptTestISR_N7, "SSDVT_CUIF_U2C_N7");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N7 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N7);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N8 , SSDVT_CUIF_InterruptTestISR_N8, "SSDVT_CUIF_U2C_N8");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N8 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N8);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N9 , SSDVT_CUIF_InterruptTestISR_N9, "SSDVT_CUIF_U2C_N9");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N9 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N9);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N10 , SSDVT_CUIF_InterruptTestISR_N10, "SSDVT_CUIF_U2C_N10");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N10 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N10);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N11 , SSDVT_CUIF_InterruptTestISR_N11, "SSDVT_CUIF_U2C_N11");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N11 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N11);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N12 , SSDVT_CUIF_InterruptTestISR_N12, "SSDVT_CUIF_U2C_N12");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N12 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N12);
+
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N13 , SSDVT_CUIF_InterruptTestISR_N13, "SSDVT_CUIF_U2C_N13");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N13 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N13);
+#endif
+#endif
+}
+
+
+
+void SSDVT_CUIF_U2C_InterruptTest()
+{
+ volatile ssdvt_uint32_p n0_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N0_CHECK : SSDVT_CUIF_USIP1_U2C_N0_CHECK;
+ volatile ssdvt_uint32_p n1_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N1_CHECK : SSDVT_CUIF_USIP1_U2C_N1_CHECK;
+ volatile ssdvt_uint32_p n2_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N2_CHECK : SSDVT_CUIF_USIP1_U2C_N2_CHECK;
+ volatile ssdvt_uint32_p n3_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N3_CHECK : SSDVT_CUIF_USIP1_U2C_N3_CHECK;
+ volatile ssdvt_uint32_p n4_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N4_CHECK : SSDVT_CUIF_USIP1_U2C_N4_CHECK;
+#if defined(__MD95__)
+ volatile ssdvt_uint32_p n5_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N5_CHECK : SSDVT_CUIF_USIP1_U2C_N5_CHECK;
+ volatile ssdvt_uint32_p n6_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N6_CHECK : SSDVT_CUIF_USIP1_U2C_N6_CHECK;
+#elif defined(__MD97__) || defined(__MD97P__)
+ volatile ssdvt_uint32_p n5_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N5_CHECK : SSDVT_CUIF_USIP1_U2C_N5_CHECK;
+ volatile ssdvt_uint32_p n6_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N6_CHECK : SSDVT_CUIF_USIP1_U2C_N6_CHECK;
+ volatile ssdvt_uint32_p n7_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N7_CHECK : SSDVT_CUIF_USIP1_U2C_N7_CHECK;
+ volatile ssdvt_uint32_p n8_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N8_CHECK : SSDVT_CUIF_USIP1_U2C_N8_CHECK;
+ volatile ssdvt_uint32_p n9_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N9_CHECK : SSDVT_CUIF_USIP1_U2C_N9_CHECK;
+ volatile ssdvt_uint32_p n10_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N10_CHECK : SSDVT_CUIF_USIP1_U2C_N10_CHECK;
+ volatile ssdvt_uint32_p n11_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N11_CHECK : SSDVT_CUIF_USIP1_U2C_N11_CHECK;
+ volatile ssdvt_uint32_p n12_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N12_CHECK : SSDVT_CUIF_USIP1_U2C_N12_CHECK;
+ volatile ssdvt_uint32_p n13_check = (ssdvt_cuif_usip_core_testing == 0) ? SSDVT_CUIF_USIP0_U2C_N13_CHECK : SSDVT_CUIF_USIP1_U2C_N13_CHECK;
+#endif
+ volatile ssdvt_uint32_p sync_addr = (ssdvt_cuif_usip_core_testing == 0) ? cuif_usip0.sync : cuif_usip1.sync;
+
+ dbg_print("interrupt test - to L1 N0 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x100;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n0_check, sync_addr);
+ dbg_print("interrupt test - to L1 N0 pass!\n");
+
+ dbg_print("interrupt test - to L1 N1 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x200;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n1_check, sync_addr);
+ dbg_print("interrupt test - to L1 N1 pass!\n");
+
+ dbg_print("interrupt test - inner to L1 N2 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x300;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n2_check, sync_addr);
+ dbg_print("interrupt test - to L1 N2 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N3 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x400;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n3_check, sync_addr);
+ dbg_print("interrupt test - to L1 N3 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N4 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x500;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n4_check, sync_addr);
+ dbg_print("interrupt test - to L1 N4 pass!\n");
+
+#if defined(__MD95__)
+ dbg_print("interrupt test - to L1 N5 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x600;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n5_check, sync_addr);
+ dbg_print("interrupt test - to L1 N5 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N6 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x700;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n6_check, sync_addr);
+ dbg_print("interrupt test - to L1 N6 pass!\n");
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ dbg_print("interrupt test - to L1 N5 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x600;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n5_check, sync_addr);
+ dbg_print("interrupt test - to L1 N5 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N6 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x700;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n6_check, sync_addr);
+ dbg_print("interrupt test - to L1 N6 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N7 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x701;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n7_check, sync_addr);
+ dbg_print("interrupt test - to L1 N7 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N8 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x702;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n8_check, sync_addr);
+ dbg_print("interrupt test - to L1 N8 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N9 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x703;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n9_check, sync_addr);
+ dbg_print("interrupt test - to L1 N9 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N10 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x704;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n10_check, sync_addr);
+ dbg_print("interrupt test - to L1 N10 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N11 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x705;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n11_check, sync_addr);
+ dbg_print("interrupt test - to L1 N11 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N12 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x706;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n12_check, sync_addr);
+ dbg_print("interrupt test - to L1 N12 pass!\n");
+
+
+ dbg_print("interrupt test - to L1 N13 start!\n");
+ // receive u2c interrupt from USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x707;
+ SSDVT_CUIF_InterruptTestInternal(0, NULL, NULL, n13_check, sync_addr);
+ dbg_print("interrupt test - to L1 N13 pass!\n");
+#endif
+}
+
+// if no enable set, the wfi interrupt should be triggerred
+void SSDVT_CUIF_CHECK_NO_WFI_INTERRUPT(volatile ssdvt_uint32 *wfi_check)
+{
+ volatile ssdvt_uint32 wfi_bit = 0x1 << ssdvt_cuif_usip_module_testing;
+#if defined(__MD95__)
+ // the 0~5 bit of N0/N5/N6 should be set when USIP WFI
+ while (!((*(SSDVT_CUIF_U2C_N0_STATUS) & wfi_bit) && ((*SSDVT_CUIF_U2C_N5_STATUS) & wfi_bit) && ((*SSDVT_CUIF_U2C_N6_STATUS) & wfi_bit)));
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ // the 0~5 bit of N0~13 should be set when USIP WFI
+ while ( !((*(SSDVT_CUIF_U2C_N0_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N1_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N2_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N3_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N4_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N5_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N6_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N7_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N8_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N9_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N10_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N11_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N12_STATUS) & wfi_bit)
+ && ((*SSDVT_CUIF_U2C_N13_STATUS) & wfi_bit)));
+
+#else
+ // the 0~3 bit of N0 and N4 should be set when USIP WFI
+ while (!((*(SSDVT_CUIF_U2C_N0_STATUS) & wfi_bit) && ((*SSDVT_CUIF_U2C_N4_STATUS) & wfi_bit)));
+#endif
+
+ SSDVT_DELAY_LOOP(2000);
+
+ // make sure the interrupt handler not be triggerred
+ if (*(wfi_check) == SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN) {
+ dbg_print("no enable but trigger wfi interrupt");
+ ERROR_LOOP;
+ }
+
+ SSDVT_CUIF_L1_WAKEUP_USIP();
+}
+
+#if defined(__MD95__)
+#define SSDVT_CUIF_WFT_NUM 3
+#elif defined(__MD97__) || defined(__MD97P__)
+#define SSDVT_CUIF_WFT_NUM 14
+#else
+#define SSDVT_CUIF_WFT_NUM 2
+#endif
+
+ssdvt_uint32 ssdvt_cuif_wfi_test_setting[SSDVT_CUIF_WFT_NUM][2] = {
+ {SSDVT_CUIF_USIP0_U2C_N0_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N0_WFI_CHECK},
+#if defined(__MD95__)
+ {SSDVT_CUIF_USIP0_U2C_N5_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N5_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N6_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N6_WFI_CHECK},
+#elif defined(__MD97__) || defined(__MD97P__)
+ {SSDVT_CUIF_USIP0_U2C_N1_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N1_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N2_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N2_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N3_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N3_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N4_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N4_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N5_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N5_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N6_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N6_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N7_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N7_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N8_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N8_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N9_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N9_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N10_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N10_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N11_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N11_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N12_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N12_WFI_CHECK},
+ {SSDVT_CUIF_USIP0_U2C_N13_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N13_WFI_CHECK},
+#else
+ {SSDVT_CUIF_USIP0_U2C_N4_WFI_CHECK, SSDVT_CUIF_USIP1_U2C_N4_WFI_CHECK},
+#endif
+};
+
+
+/*
+WFI test flow overview:
+uSIP: WFI (no enable)
+MCU: check status bit is set and no interrupt was triggerred
+ wake up uSIP
+uSIP: enable bit set (N0 or N4); WFI
+MCU: trap in while loop until interrupt was teiggerred
+ interrupt handler write special pattern
+uSIP: wakeup; check pattern
+*/
+void SSDVT_CUIF_U2C_WFI_Test_L1core(){
+ volatile ssdvt_uint32 mcu_vpe;
+ volatile ssdvt_uint32 *wfi_check;
+ volatile ssdvt_uint32_p sync_addr = (ssdvt_cuif_usip_core_testing == 0) ? cuif_usip0.sync : cuif_usip1.sync;
+
+ ssdvt_cuif_wfi_testing = 1;
+ //only N0 & N4 can get WFI interrupt
+ for (mcu_vpe = 0; mcu_vpe < SSDVT_CUIF_WFT_NUM; mcu_vpe++)
+ {
+ wfi_check = ssdvt_cuif_wfi_test_setting[mcu_vpe][ssdvt_cuif_usip_core_testing];
+
+ // sync first
+ cuif_test_sync(0, sync_addr);
+
+ SSDVT_CUIF_CHECK_NO_WFI_INTERRUPT(wfi_check);
+
+ while(*(wfi_check) != SSDVT_CUIF_U2C_WFI_ISR_CHECK_PATTERN) ;
+
+ }
+ ssdvt_cuif_wfi_testing = 0;
+}
+
+void SSDVT_CUIF_InterruptTest_L1core()
+{
+ SSDVT_CUIF_InterruptTestRegisterISR_L1CORE();
+
+ /*
+ test with usip core 0
+ */
+ //inner
+ dbg_print("inner interrupt test stating!\n");
+ SSDVT_CUIF_U2C_InterruptTest();
+
+ dbg_print("interrupt test - from L1 start!\n");
+ // send c2u interrupt to USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x900;
+ SSDVT_CUIF_InterruptTestInternal(1, SSDVT_CUIF_C2U_INNER_STATUS_SET, SSDVT_CUIF_C2U_INNER_EN_SET, SSDVT_CUIF_USIP0_C2U_U0_CHECK, cuif_usip0.sync);
+ dbg_print("interrupt test - from L1 inner pass!\n");
+
+ ssdvt_cuif_usip_module_testing = CUIF_ENUM_INNER;
+ SSDVT_CUIF_U2C_WFI_Test_L1core();
+
+ //brp
+ dbg_print("brp interrupt test stating!\n");
+
+ SSDVT_CUIF_U2C_InterruptTest();
+
+ dbg_print("interrupt test - from L1 start!\n");
+ // send c2u interrupt to USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x900;
+ SSDVT_CUIF_InterruptTestInternal(1, SSDVT_CUIF_C2U_OUTER_STATUS_SET, SSDVT_CUIF_C2U_OUTER_EN_SET, SSDVT_CUIF_USIP0_C2U_U1_CHECK, cuif_usip0.sync);
+ dbg_print("interrupt test - from L1 inner pass!\n");
+
+ ssdvt_cuif_usip_module_testing = CUIF_ENUM_OUTER;
+ SSDVT_CUIF_U2C_WFI_Test_L1core();
+
+
+ /*
+ test with usip core 1
+ */
+ ssdvt_cuif_usip_core_testing = 1;
+ cuif_test_sync(0, cuif_usip1.sync);
+
+ dbg_print("usip1 mem test stating!\n");
+ //SSDVT_CUIF_RamTest_USIP1();
+
+
+ //fec
+ dbg_print("fec interrupt test stating!\n");
+
+ SSDVT_CUIF_U2C_InterruptTest();
+
+ dbg_print("interrupt test - from L1 start!\n");
+ // send c2u interrupt to USIP
+ ssdvt_cuif_interrupt_test_case_num = 0x900;
+ SSDVT_CUIF_InterruptTestInternal(1, SSDVT_CUIF_C2U_FEC_STATUS_SET, SSDVT_CUIF_C2U_FEC_EN_SET, SSDVT_CUIF_USIP1_C2U_U2_CHECK, cuif_usip1.sync);
+ dbg_print("interrupt test - from L1 inner pass!\n");
+
+ #define CUIF_ENUM_USIP_USER2 CUIF_ENUM_SPEECH
+ ssdvt_cuif_usip_module_testing = CUIF_ENUM_USIP_USER2;
+ SSDVT_CUIF_U2C_WFI_Test_L1core();
+ #undef CUIF_ENUM_USIP_USER2
+ //speech
+ dbg_print("speech interrupt test stating!\n");
+
+ SSDVT_CUIF_U2C_InterruptTest();
+
+ dbg_print("interrupt test - from L1 start!\n");
+ // send c2u interrupt to USIP
+ ssdvt_cuif_interrupt_test_case_num = 0xA00;
+ SSDVT_CUIF_InterruptTestInternal(1, SSDVT_CUIF_C2U_SPEECH_STATUS_SET, SSDVT_CUIF_C2U_SPEECH_EN_SET, SSDVT_CUIF_USIP1_C2U_U3_CHECK, cuif_usip1.sync);
+ dbg_print("interrupt test - from L1 inner pass!\n");
+
+ #define CUIF_ENUM_USIP_USER3 CUIF_ENUM_FEC
+ ssdvt_cuif_usip_module_testing = CUIF_ENUM_USIP_USER3;
+ SSDVT_CUIF_U2C_WFI_Test_L1core();
+ #undef CUIF_ENUM_USIP_USER3
+
+ dbg_print("all interrupt test pass!\n");
+}
+
+#endif /* #if defined(__SSDVT_CUIF_TEST__) */
+
diff --git a/mcu/driver/devdrv/cuif/cuif_test/src/memory_test.c b/mcu/driver/devdrv/cuif/cuif_test/src/memory_test.c
new file mode 100644
index 0000000..6e28413
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/src/memory_test.c
@@ -0,0 +1,1658 @@
+#include "ssdvt_header.h"
+#include "ssdvt_typedef.h"
+
+#include "memory_test.h"
+
+#include <stdlib.h>
+
+/*******************************************************************************
+* Macros
+*******************************************************************************/
+#define SSDVT_MEM_RANDOM_TEST_SIZE 128
+#define SSDVT_MEM_RANDOM_TEST_TIMES 1
+
+#define SSDVT_MEM_TEST_BANK2_ALIGIN_ADDR 0x8000
+
+#define SSDVT_MEM_DELAY_LOOP_COUNT 1000
+
+/*******************************************************************************
+* Global variable
+*******************************************************************************/
+SSDVT_MEM_TestType ssdvt_mem_test_type;
+ssdvt_uint32 ssdvt_mem_test_current_status_base;
+ssdvt_uint32 ssdvt_mem_test_mem_range_num;
+
+
+#if !defined(__SIMULATION__)
+/* random test */
+ssdvt_uint32 ssdvt_mem_check_index[SSDVT_MEM_RANDOM_TEST_SIZE]; // check random index
+ssdvt_uint32 ssdvt_mem_check_value[SSDVT_MEM_RANDOM_TEST_SIZE]; // check random value
+ssdvt_uint32 ssdvt_mem_check_test_size;
+#endif /* __SIMULATION__ */
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+
+void write_word_value(const ssdvt_uint32 write_value,
+ const ssdvt_uint32_p x,
+ const ssdvt_uint32 x_size)
+{
+ ssdvt_uint32 i;
+ for(i = 0; i < x_size ; ++i){
+ x[i] = write_value;
+ }
+}
+
+ssdvt_uint32 check_word_value(const ssdvt_uint32 ssdvt_mem_check_value,
+ const ssdvt_uint32_p x,
+ const ssdvt_uint32 x_size)
+{
+ ssdvt_uint32 i;
+ for(i = 0; i < x_size ; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(x[i], ssdvt_mem_check_value);
+ }
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_basic_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync_fun,
+ const SSDVT_MEM_BarrierSyncFun write_sync_fun)
+{
+ /*volatile ssdvt_uint32 i;*/
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 11);
+ /* Write */
+ if(client){
+ write_word_value(0x0, base_32, size_base_32);
+ dbg_print(".... test for 0x0 write \r\n");
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync_fun)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 12);
+ if(check_all_client || !client){
+ dbg_print(".... test for 0x0 read \r\n");
+ check_word_value(0x0, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync_fun)(client, sync);
+ dbg_print("... test for 0x0 success.\r\n");
+
+
+ /** 0xFFFFFFFF*/
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 13);
+ if(client){
+ write_word_value(0xFFFFFFFF, base_32, size_base_32);
+ dbg_print(".... test for 0xFFFFFFFF write \r\n");
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync_fun)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 14);
+ if(check_all_client || !client){
+ dbg_print(".... xxif test for 0xFFFFFFFF read \r\n");
+ check_word_value(0xFFFFFFFF, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync_fun)(client, sync);
+ dbg_print("... mem test for 0xFFFFFFFF success.\r\n");
+
+ dbg_print("... mem basic test: Pass.\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_full_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+
+ volatile ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint16_p base_16 = (ssdvt_uint16_p)xxif->base_addr;
+ const ssdvt_uint8_p base_8 = (ssdvt_uint8_p)xxif->base_addr;
+
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ const ssdvt_uint32 size_base_16 = xxif->size/ sizeof(ssdvt_uint16);
+ const ssdvt_uint32 size_base_8 = xxif->size/ sizeof(ssdvt_uint8);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 pattern_32 = 0;
+ ssdvt_uint16 pattern_16 = 0;
+ ssdvt_uint8 pattern_8 = 0;
+
+
+ /** 0, 1, 2, ... for each byte(1 byte) */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 15);
+ /* Write */
+ if(client){
+ for(i = 0, pattern_8 = 0; i<size_base_8; i++, pattern_8++){
+ base_8[i] = pattern_8;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 16);
+ if(check_all_client || !client){
+ for(i = 0, pattern_8 = 0; i<size_base_8; i++, pattern_8++){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], pattern_8);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0, 1, 2, ... for each byte(1 byte) test success\n");
+
+ /** 0, 1, 2, ... for each half word(2 bytes)*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 17);
+ /* Write */
+ if(client){
+ for(i = 0, pattern_16 = 0; i<size_base_16; i++, pattern_16++){
+ base_16[i] = pattern_16;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 18);
+ if(check_all_client || !client){
+ for(i = 0, pattern_16 = 0; i<size_base_16; i++, pattern_16++){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], pattern_16);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0, 1, 2, ... for each half word(2 bytes) test success\n");
+
+ /** 0, 1, 2, ... for each word(4 bytes)*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 19);
+ /* Write */
+ if(client){
+ for(i = 0, pattern_32 = 0; i<size_base_32; i++, pattern_32++){
+ base_32[i] = pattern_32;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 20);
+ if(check_all_client || !client){
+ for(i = 0, pattern_32 = 0; i<size_base_32; i++, pattern_32++){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], pattern_32);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0, 1, 2, ... for word(4 bytes) test success\n");
+
+ /** 0x5a5a5a5a*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 21);
+ /* Write */
+ if(client){
+ write_word_value(0x5a5a5a5a, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 22);
+ if(check_all_client || !client){
+ check_word_value(0x5a5a5a5a, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x5a5a5a5a test success\n");
+
+ /** 0xa5a5a5a5 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 23);
+ /* Write */
+ if(client){
+ write_word_value(0xa5a5a5a5, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 24);
+ if(check_all_client || !client){
+ check_word_value(0xa5a5a5a5, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa5a5a5a5 test success\n");
+
+ /** 0xa5a5a500 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 25);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 26);
+ if(check_all_client || !client){
+ check_word_value(0xa5a5a500, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa5a5a500 test success\n");
+
+ /** 0xa500a500 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 27);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4+2] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 28);
+ if(check_all_client || !client){
+ check_word_value(0xa500a500, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa500a500 test success\n");
+
+ /** 0xa5000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 29);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4+1] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 30);
+ if(check_all_client || !client){
+ check_word_value(0xa5000000, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xa5000000 test success\n");
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 31);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_8[i*4+3] = 0x00;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 32);
+ if(check_all_client || !client){
+ check_word_value(0x00000000, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x00000000 test success\n");
+
+ /** 0xFFFF0000*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 33);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_16[i*2+1] = 0xFFFF;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+ dbg_print("... 0xFFFF0000 test success\n");
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 34);
+ if(check_all_client || !client){
+ check_word_value(0xFFFF0000, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xFFFF0000 test success\n");
+
+ /** 0xFFFFFFFF*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 35);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; ++i){
+ base_16[i*2] = 0xFFFF;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 36);
+ if(check_all_client || !client){
+ check_word_value(0xFFFFFFFF, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0xFFFFFFFF test success\n");
+
+ /** 0x5A for each byte by fibonacci sequence (index: 8, 13, 21, 34 ...) */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 37);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_8; i++){
+ base_8[i] = 0x5A;
+ }
+ for(i=8, j=5; i<size_base_8; k=i, i+=j, j=k){
+ base_8[i] = (ssdvt_uint8)j;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 38);
+ if(check_all_client || !client){
+ for(i=0; i<(ssdvt_uint32)((size_base_8<8)?size_base_8:8); ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x5A);
+ }
+ for(i=8, j=5; i<size_base_8; k=i, i+=j, j=k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], (ssdvt_uint8)j);
+
+ for(k=i+1; k < (i+j) && k < size_base_8; ++k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[k], 0x5A);
+ }
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x5A by fibonacci sequence (index: 8, 13, 21, 34 ...) test success\n");
+
+ /** 0x55AA for each half word by fibonacci sequence (index: 8, 13, 21, 34 ...) */
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 39);
+ if(client){
+ for(i=0; i<size_base_16; i++){
+ base_16[i] = 0x55AA;
+ }
+ for(i=8, j=5; i<size_base_16; k=i, i+=j, j=k){
+ base_16[i] = (ssdvt_uint16)j;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 40);
+ if(check_all_client || !client){
+ for(i=0; i<(ssdvt_uint32)((size_base_16<8)?size_base_16:8); ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x55AA);
+ }
+ for(i=8, j=5; i<size_base_16; k=i, i+=j, j=k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], (ssdvt_uint16)j);
+
+ for(k=i+1; k < (i+j) && k < size_base_16; ++k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[k], 0x55AA);
+ }
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x55AA by fibonacci sequence (index: 8, 13, 21, 34 ...) test success\n");
+
+ /** 0x12345678 for each word by fibonacci sequence (index: 8, 13, 21, 34 ...) */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 41);
+ /* Write */
+ if(client){
+ for(i=0; i<size_base_32; i++){
+ base_32[i] = 0x12345678;
+ }
+ for(i=8, j=5; i<size_base_32; k=i, i+=j, j=k){
+ base_32[i] = (ssdvt_uint32)j;
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 42);
+ if(check_all_client || !client){
+ for(i=0; i<(ssdvt_uint32)((size_base_32<8)?size_base_32:8); ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x12345678);
+ }
+ for(i=8, j=5; i<size_base_32; k=i, i+=j, j=k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], (ssdvt_uint32)j);
+
+ for(k=i+1; k < (i+j) && k < size_base_32; ++k){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[k], 0x12345678);
+ }
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... 0x12345678 by fibonacci sequence (index: 8, 13, 21, 34 ...) test success\n");
+
+ dbg_print("... full size test: Pass.\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_half_size_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ /*ssdvt_uint32 i;*/
+
+ const ssdvt_uint32_p base_32 = xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p c1_base_addr = base_32;
+ const ssdvt_uint32 c1_size = size_base_32 / 2;
+ const ssdvt_uint32_p c2_base_addr = base_32 + c1_size;
+ const ssdvt_uint32 c2_size = size_base_32 - c1_size;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 43);
+ /* Write */
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ write_word_value(0x0, c1_base_addr, c1_size);
+ }
+ else{
+ write_word_value(0x0, c2_base_addr, c2_size);
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ write_word_value(0x0, c1_base_addr, c1_size);
+ write_word_value(0x0, c2_base_addr, c2_size);
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 44);
+ check_word_value(0x0, base_32, size_base_32);
+ (*read_sync)(client, sync);
+ dbg_print("... half size: 0x0 + 0x0 test success\n");
+
+ /** 0xFFFFFFFF */
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 45);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ write_word_value(0xFFFFFFFF, c1_base_addr, c1_size);
+ }
+ else{
+ write_word_value(0xFFFFFFFF, c2_base_addr, c2_size);
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ write_word_value(0xFFFFFFFF, c1_base_addr, c1_size);
+ write_word_value(0xFFFFFFFF, c2_base_addr, c2_size);
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 46);
+ check_word_value(0xFFFFFFFF, base_32, size_base_32);
+ (*read_sync)(client, sync);
+ dbg_print("... half size: 0xFFFFFFFF + 0xFFFFFFFF test success\n");
+
+ /** 0xa5a5a5a5 + 0x5a5a5a5a */
+ /* Write */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 47);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ write_word_value(0x5a5a5a5a, c1_base_addr, c1_size);
+ }
+ else{
+ write_word_value(0xa5a5a5a5, c2_base_addr, c2_size);
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ write_word_value(0x5a5a5a5a, c1_base_addr, c1_size);
+ write_word_value(0xa5a5a5a5, c2_base_addr, c2_size);
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 48);
+ check_word_value(0x5a5a5a5a, c1_base_addr, c1_size);
+ check_word_value(0xa5a5a5a5, c2_base_addr, c2_size);
+ (*read_sync)(client, sync);
+ dbg_print("... half size: 0x5a5a5a5a + 0xa5a5a5a5 test success\n");
+
+ dbg_print("... half size test: Pass.\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint8_p base_8 = (ssdvt_uint8_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_8 = xxif->size/ sizeof(ssdvt_uint8);
+ ssdvt_uint8 pattern_8 = 0;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** Test for bytes */
+ /** Interleave test for each byte fill with 0x0 */
+ /* Write */
+ /* i: 0 write 0x0 in index 0, 2, 4, ... */
+ /* i: 1 write 0x0 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 49);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+ for(i= 1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 50);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0, ...success\n");
+
+ /** Interlave test for each byte fill with 0xFF */
+ /* Write */
+ /* i: 0 write 0xFF in index 0, 2, 4, ... */
+ /* i: 1 write 0xFF in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 51);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i< size_base_8; i+= 2){
+ base_8[i] = 0xFF;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i< size_base_8; i+= 2){
+ base_8[i] = 0xFF;
+ }
+ for(i= 1; i< size_base_8; i+= 2){
+ base_8[i] = 0xFF;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 52);
+ for(i= 0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0xFF);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0xFF, 0xFF success\n");
+
+ /** Interlave test for each byte fill with 0x5A and 0xA5 */
+ /* Write */
+ /* i: 0 write 0x5A in index 0, 2, 4, ... */
+ /* i: 1 write 0xA5 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 53);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1, pattern_8= (client)?0x5A:0xA5; i< size_base_8; i+=2){
+ base_8[i] = pattern_8;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0, pattern_8= 0x5A; i< size_base_8; i+=2){
+ base_8[i] = pattern_8;
+ }
+ for(i= 1, pattern_8= 0xA5; i< size_base_8; i+=2){
+ base_8[i] = pattern_8;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 54);
+ for(i=0; i< size_base_8; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x5A);
+ }
+ for(i=1; i< size_base_8; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0xA5);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0x5a, 0xa5 success\n");
+
+ /** Interlave test for each byte */
+ /* Write */
+ /* i: 0 write 0, 2, 4, ... in index 0, 2, 4, ... */
+ /* i: 1 write 1, 3, 5, ... in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 55);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_8; i+=2){
+ base_8[i] = (ssdvt_uint8)i;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_8; i+=2){
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for(i= 1; i<size_base_8; i+=2){
+ base_8[i] = (ssdvt_uint8)i;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 56);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], (ssdvt_uint8)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: 0, 1, 2 ... success\n");
+
+ /* Write in fib seuqences */
+ /* Before fib test, we reset the test memory to zero */
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+ for(i= 1; i<size_base_8; i+=2){
+ base_8[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 50);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("reset the test memory to zero Done\n");
+ /* reset the test memory to zero Done */
+
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 57);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ for (i= 0; i< (size_base_8<8?size_base_8:8); i++) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ }
+ else{
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_8; ++k){
+ base_8[k] = (ssdvt_uint8)k;
+ }
+ }
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for (i= 0; i< (size_base_8<8?size_base_8:8); i++) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ base_8[i] = (ssdvt_uint8)i;
+ }
+ for (i= 8, j= 5; i< size_base_8; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_8; ++k){
+ base_8[k] = (ssdvt_uint8)k;
+ }
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 58);
+ for(i=0; i<size_base_8; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[i], (ssdvt_uint8)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 8: fibonacci sequence success\n");
+
+ dbg_print("... interleave test base 8 bits: Pass.\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint16_p base_16 = (ssdvt_uint16_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_16 = xxif->size/ sizeof(ssdvt_uint16);
+ ssdvt_uint16 pattern_16 = 0;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** Test for bytes */
+ /** Interlave test for each byte fill with 0x0 */
+ /* Write */
+ /* i: 0 write 0x0 in index 0, 2, 4, ... */
+ /* i: 1 write 0x0 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 59);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 60);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0, ...success\n");
+
+ /** Interlave test for each byte fill with 0xFFFF */
+ /* Write */
+ /* i: 0 write 0xFFFF in index 0, 2, 4, ... */
+ /* i: 1 write 0xFFFF in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 61);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = 0xFFFF;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = 0xFFFF;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = 0xFFFF;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 62);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0xFFFF);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0xFFFF, 0xFFFF success\n");
+
+ /** Interlave test for each byte fill with 0x5A and 0xA5 */
+ /* Write */
+ /* i: 0 write 0x5A in index 0, 2, 4, ... */
+ /* i: 1 write 0xA5 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 63);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1, pattern_16= (client)?0x5A5A:0xA5A5; i< size_base_16; i+=2){
+ base_16[i] = pattern_16;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0, pattern_16= 0x5A5A; i< size_base_16; i+=2){
+ base_16[i] = pattern_16;
+ }
+ for(i= 1, pattern_16= 0xA5A5; i< size_base_16; i+=2){
+ base_16[i] = pattern_16;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 64);
+ for(i=0; i< size_base_16; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x5A5A);
+ }
+ for(i=1; i< size_base_16; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0xA5A5);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0x5a5a, 0xa5a5 success\n");
+
+ /** Interlave test for each half word */
+ /* Write */
+ /* i: 0 write 0, 2, 4, ... in index 0, 2, 4, ... */
+ /* i: 1 write 1, 3, 5, ... in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 65);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = (ssdvt_uint16)i;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = (ssdvt_uint16)i;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 66);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], (ssdvt_uint16)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0, 1, 2 ... success\n");
+
+ /* Write in fib seuqences */
+ /* Before test fib sequence, reset the test memory */
+ #if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+ for(i= 1; i<size_base_16; i+=2){
+ base_16[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 60);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("Reset test memory done\n");
+ /* Reset test memory done */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 67);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ for (i= 0; i< (size_base_16<8?size_base_16:8); i++) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ }
+ else{
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_16; ++k){
+ base_16[k] = (ssdvt_uint16)k;
+ }
+ }
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for (i= 0; i< (size_base_16<8?size_base_16:8); i++) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ base_16[i] = (ssdvt_uint16)i;
+ }
+ for (i= 8, j= 5; i< size_base_16; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_16; ++k){
+ base_16[k] = (ssdvt_uint16)k;
+ }
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 68);
+ for(i=0; i<size_base_16; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[i], (ssdvt_uint16)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: fibonacci sequence success\n");
+
+ dbg_print("... interleave test base 16 bits: Pass.\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_interleave_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ ssdvt_uint32 i, j, k;
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ ssdvt_uint32 pattern_32 = 0;
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** Test for bytes */
+ /** Interleave test for each byte fill with 0x0 */
+ /* Write */
+ /* i: 0 write 0x0 in index 0, 2, 4, ... */
+ /* i: 1 write 0x0 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 69);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 70);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: 0, ...success\n");
+
+ /** Interleave test for each byte fill with 0xFFFFFFFF */
+ /* Write */
+ /* i: 0 write 0xFFFFFFFF in index 0, 2, 4, ... */
+ /* i: 1 write 0xFFFFFFFF in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 71);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = 0xFFFFFFFF;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = 0xFFFFFFFF;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = 0xFFFFFFFF;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 72);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0xFFFFFFFF);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: 0xFFFFFFFF, 0xFFFFFFFF success\n");
+
+ /** Interlave test for each byte fill with 0x5A and 0xA5 */
+ /* Write */
+ /* i: 0 write 0x5A5A5A5A in index 0, 2, 4, ... */
+ /* i: 1 write 0xA5A5A5A5 in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 73);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1, pattern_32= (client)?0x5A5A5A5A:0xA5A5A5A5; i< size_base_32; i+=2){
+ base_32[i] = pattern_32;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0, pattern_32= 0x5A5A5A5A; i< size_base_32; i+=2){
+ base_32[i] = pattern_32;
+ }
+ for(i= 1, pattern_32= 0xA5A5A5A5; i< size_base_32; i+=2){
+ base_32[i] = pattern_32;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 74);
+ for(i=0; i< size_base_32; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x5A5A5A5A);
+ }
+ for(i=1; i< size_base_32; i+=2){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0xA5A5A5A5);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 16: 0x5a5a5a5a, 0xa5a5a5a5 success\n");
+
+ /** Interlave test for each half word */
+ /* Write */
+ /* i: 0 write 0, 2, 4, ... in index 0, 2, 4, ... */
+ /* i: 1 write 1, 3, 5, ... in index 1, 3, 5, ... */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 75);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = (ssdvt_uint32)i;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = (ssdvt_uint32)i;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 76);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], (ssdvt_uint32)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: 0, 1, 2 ... success\n");
+
+ /* Write in fib sequences */
+ /* Before test, reset test memory */
+ #if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ for(i= (client)?0:1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for(i= 0; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+ for(i= 1; i<size_base_32; i+=2){
+ base_32[i] = 0x0;
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 70);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], 0x0);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("Reset test memory done\n");
+ /* Reset test memory done */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 77);
+#if !defined(__CMIF_SIGNLE_CORE_TEST__)
+ if(client){
+ for (i= 0; i< (size_base_32<8?size_base_32:8); i++) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ }
+ else{
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_32; ++k){
+ base_32[k] = (ssdvt_uint32)k;
+ }
+ }
+ }
+#else /* !__CMIF_SIGNLE_CORE_TEST__ */
+ for (i= 0; i< (size_base_32<8?size_base_32:8); i++) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ base_32[i] = (ssdvt_uint32)i;
+ }
+ for (i= 8, j= 5; i< size_base_32; k=i, i+=j, j=k) {
+ for(k=i+1; k < (i+j) && k < size_base_32; ++k){
+ base_32[k] = (ssdvt_uint32)k;
+ }
+ }
+#endif /* !__CMIF_SIGNLE_CORE_TEST__ */
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 78);
+ for(i=0; i<size_base_32; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[i], (ssdvt_uint32)i);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... interleave base 32: fibonacci sequence success\n");
+
+ dbg_print("... interleave test base 32 bits: Pass.\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_random_test_base_8_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ volatile ssdvt_uint32 i, j;
+ ssdvt_uint32 times;
+
+ const ssdvt_uint8_p base_8 = (ssdvt_uint8_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_8 = xxif->size/ sizeof(ssdvt_uint8);
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 ridx[SSDVT_MEM_RANDOM_TEST_SIZE]; // random index
+ ssdvt_uint8 rvalue[SSDVT_MEM_RANDOM_TEST_SIZE]; // random value
+ ssdvt_uint32 random_test_size = (SSDVT_MEM_RANDOM_TEST_SIZE > size_base_32)? size_base_32: SSDVT_MEM_RANDOM_TEST_SIZE;
+
+ ssdvt_uint32 sidx;
+
+ for(times = 0; times < SSDVT_MEM_RANDOM_TEST_TIMES; ++times){
+ dbg_print("... 8 byte random test %u/%u:\n", times+1, SSDVT_MEM_RANDOM_TEST_TIMES);
+
+ /* Generator index */
+ for(i=0; i< random_test_size; i++){
+ ridx[i] = (rand()+1) % size_base_8;
+ }
+
+ /* Generate value */
+ for(i=0; i< random_test_size; i++){
+ rvalue[i] = (ssdvt_uint8)(rand()+1);
+ }
+
+
+ /* Random Test */
+ /**
+ * Step 1: Send index
+ * Step 2: Send value
+ * Step 3: Check the index and the value
+ **/
+ /* Send index*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 79);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = ridx[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive index */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 80);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ ridx[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Send value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 81);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_8[i] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 82);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ rvalue[i] = base_8[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Random write with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 83);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_8[ridx[i]] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 84);
+ if(check_all_client || !client){
+ /* Generate golden pattern */
+ for(i=0, ssdvt_mem_check_test_size = 0; i<random_test_size; ++i){
+ sidx = i;
+ for(j=0; j<ssdvt_mem_check_test_size; j++){
+ if(ssdvt_mem_check_index[j] == ridx[i]){
+ sidx = j;
+ break;
+ }
+ }
+ if(j == ssdvt_mem_check_test_size){
+ sidx = ssdvt_mem_check_test_size;
+ ssdvt_mem_check_test_size++;
+
+ ssdvt_mem_check_index[sidx] = ridx[i];
+ }
+ ssdvt_mem_check_value[sidx] = rvalue[i];
+ }
+
+ /* check */
+ for(i=0; i<ssdvt_mem_check_test_size; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_8[ssdvt_mem_check_index[i]], ssdvt_mem_check_value[i]);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ }
+ dbg_print("... memory random test (1 byte) success\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_random_test_base_16_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ volatile ssdvt_uint32 i, j;
+ ssdvt_uint32 times;
+
+ const ssdvt_uint16_p base_16 = (ssdvt_uint16_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_16 = xxif->size/ sizeof(ssdvt_uint16);
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 ridx[SSDVT_MEM_RANDOM_TEST_SIZE]; // random index
+ ssdvt_uint16 rvalue[SSDVT_MEM_RANDOM_TEST_SIZE]; // random value
+ ssdvt_uint32 random_test_size = (SSDVT_MEM_RANDOM_TEST_SIZE > size_base_32)? size_base_32: SSDVT_MEM_RANDOM_TEST_SIZE;
+
+ ssdvt_uint32 sidx;
+
+ srand(91);
+ for(times = 0; times < SSDVT_MEM_RANDOM_TEST_TIMES; ++times){
+ dbg_print("... 16 byte random test %u/%u:\n", times+1, SSDVT_MEM_RANDOM_TEST_TIMES);
+
+ /* Generatr index */
+ for(i=0; i< random_test_size; i++){
+ ridx[i] = (rand() + 1)%size_base_16;
+ }
+
+ /* Generate value */
+ for(i=0; i< random_test_size; i++){
+ rvalue[i] = (ssdvt_uint16)(rand()+1);
+ }
+
+ /* Random Test */
+ /**
+ * Step 1: Send index
+ * Step 2: Send value
+ * Step 3: Check the index and the value
+ **/
+ /* Send index*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 85);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = ridx[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive index */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 86);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ ridx[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Send value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 87);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_16[i] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 88);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ rvalue[i] = base_16[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Random write with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 89);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_16[ridx[i]] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 90);
+ if(check_all_client || !client){
+ /* Generate golden pattern */
+ for(i=0, ssdvt_mem_check_test_size = 0; i<random_test_size; ++i){
+ sidx = i;
+ for(j=0; j<ssdvt_mem_check_test_size; j++){
+ if(ssdvt_mem_check_index[j] == ridx[i]){
+ sidx = j;
+ break;
+ }
+ }
+ if(j == ssdvt_mem_check_test_size){
+ sidx = ssdvt_mem_check_test_size;
+ ssdvt_mem_check_test_size++;
+
+ ssdvt_mem_check_index[sidx] = ridx[i];
+ }
+ ssdvt_mem_check_value[sidx] = rvalue[i];
+ }
+
+ /* check */
+ for(i=0; i<ssdvt_mem_check_test_size; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_16[ssdvt_mem_check_index[i]], ssdvt_mem_check_value[i]);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ }
+ dbg_print("... memory random test (2 bytes) success\n");
+
+ return 0;
+}
+
+ssdvt_uint32 SSDVT_MEM_random_test_base_32_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ volatile ssdvt_uint32 i, j;
+ ssdvt_uint32 times;
+
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ ssdvt_uint32 ridx[SSDVT_MEM_RANDOM_TEST_SIZE]; // random index
+ ssdvt_uint32 rvalue[SSDVT_MEM_RANDOM_TEST_SIZE]; // random value
+ ssdvt_uint32 random_test_size = (SSDVT_MEM_RANDOM_TEST_SIZE > size_base_32)? size_base_32: SSDVT_MEM_RANDOM_TEST_SIZE;
+
+ ssdvt_uint32 sidx;
+
+ for(times = 0; times < SSDVT_MEM_RANDOM_TEST_TIMES; ++times){
+ dbg_print("... 32 byte random test %u/%u:\n", times+1, SSDVT_MEM_RANDOM_TEST_TIMES);
+
+ /* Generatr index */
+ for(i=0; i< random_test_size; i++){
+ ridx[i] = (rand() + 1) % size_base_32;
+ }
+
+ /* Generate value */
+ for(i=0; i< random_test_size; i++){
+ rvalue[i] = (ssdvt_uint32)(rand()+1);
+ }
+
+
+ /* Random Test */
+ /**
+ * Step 1: Send index
+ * Step 2: Send value
+ * Step 3: Check the index and the value
+ **/
+ /* Send index*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 91);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = ridx[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive index */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 92);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ ridx[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Send value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 93);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[i] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Receive value */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 94);
+ if(check_all_client || !client){
+ for(i=0; i<random_test_size; ++i){
+ rvalue[i] = base_32[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+
+ /* Random write with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 95);
+ if(client){
+ for(i=0; i<random_test_size; ++i){
+ base_32[ridx[i]] = rvalue[i];
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check with index and value*/
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 96);
+ if(check_all_client || !client){
+ /* Generate golden pattern */
+ for(i=0, ssdvt_mem_check_test_size = 0; i<random_test_size; ++i){
+ sidx = i;
+ for(j=0; j<ssdvt_mem_check_test_size; j++){
+ if(ssdvt_mem_check_index[j] == ridx[i]){
+ sidx = j;
+ break;
+ }
+ }
+ if(j == ssdvt_mem_check_test_size){
+ sidx = ssdvt_mem_check_test_size;
+ ssdvt_mem_check_test_size++;
+
+ ssdvt_mem_check_index[sidx] = ridx[i];
+ }
+ ssdvt_mem_check_value[sidx] = rvalue[i];
+ }
+
+ /* check */
+ for(i=0; i<ssdvt_mem_check_test_size; ++i){
+ SSDVT_MEM_ASSERT_EQ_PRINT_ERROR(base_32[ssdvt_mem_check_index[i]], ssdvt_mem_check_value[i]);
+ }
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ }
+ dbg_print("... memory random test (4 bytes) success\n");
+
+ return 0;
+}
+
+
+ssdvt_uint32 SSDVT_MEM_init_test_XXIF(const ssdvt_uint32 client,
+ const ssdvt_uint32 check_all_client,
+ const SSDVT_MEM_MemInfo_ptr xxif,
+ const SSDVT_MEM_BarrierSyncFun read_sync,
+ const SSDVT_MEM_BarrierSyncFun write_sync)
+{
+ /*volatile ssdvt_uint32 i;*/
+ const ssdvt_uint32_p base_32 = (ssdvt_uint32_p)xxif->base_addr;
+ const ssdvt_uint32 size_base_32 = xxif->size/ sizeof(ssdvt_uint32);
+ const ssdvt_uint32_p sync = xxif->sync;
+
+ /** 0x00000000 */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 97);
+ /* Write */
+ if(client){
+ write_word_value(0x0, base_32, size_base_32);
+ dbg_print("... test init for 0x0 write\r\n");
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*write_sync)(client, sync);
+
+ /* Check */
+ SSDVT_SET_CURRENT_STATUS(ssdvt_mem_test_current_status_base + (ssdvt_mem_test_mem_range_num << 8) + 98);
+ if(check_all_client || !client){
+ dbg_print("... test init for 0x0 read \r\n");
+ check_word_value(0x0, base_32, size_base_32);
+ }
+ else{
+ SSDVT_DELAY_LOOP(SSDVT_MEM_DELAY_LOOP_COUNT);
+ }
+ (*read_sync)(client, sync);
+ dbg_print("... test init for 0x0 success \r\n");
+
+ return 0;
+}
+
diff --git a/mcu/driver/devdrv/cuif/cuif_test/src/ssdvt_util.c b/mcu/driver/devdrv/cuif/cuif_test/src/ssdvt_util.c
new file mode 100644
index 0000000..b070bd2
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/cuif_test/src/ssdvt_util.c
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+/*******************************************************************************
+ * Definition
+ *******************************************************************************/
+#if defined(__SIMULATION__)
+#define SYSREG_PASS ((volatile ssdvt_uint32 *)(0xe0000004))
+#define SYSREG_FAIL ((volatile ssdvt_uint32 *)(0xe0000008))
+#endif
+
+#define SSDVT_GET_VIC_VEC() SCU_IO_READ(VIC_VEC)
+
+/*******************************************************************************
+ * Global Variable
+ *******************************************************************************/
+ssdvt_uint32 ssdvt_stored_stack_pointer;
+ssdvt_uint32 ssdvt_stored_return_address;
+ssdvt_uint32 ssdvt_current_status;
+
+/*******************************************************************************
+ * Functions
+ *******************************************************************************/
+void ssdvt_test_fail_notification()
+{
+#if defined(__SIMULATION__)
+ *SYSREG_FAIL = 0xDEAD;
+#endif
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+ *SSDVT_RTLCOSIM_ERROR_PC = ssdvt_stored_return_address;
+ *SSDVT_RTLCOSIM_STATUS = 2;
+#endif
+
+ while(1);
+}
+
+void ssdvt_test_pass_notification()
+{
+#if defined(__SIMULATION__)
+ *SYSREG_PASS = 0xABBA;
+#endif
+
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+ *SSDVT_RTLCOSIM_STATUS = 1;
+#endif
+
+ while(1);
+}
+
+void ssdvt_set_current_status(ssdvt_uint32 status)
+{
+ ssdvt_current_status = status;
+#if defined(__MD32S_SSDVT_RTLCOSIM__)
+ *SSDVT_RTLCOSIM_ERROR_PC = status;
+#endif
+}
+
diff --git a/mcu/driver/devdrv/cuif/dsp_sram_ctrl_dvt/src/dsp_sram_ctrl_dvt.c b/mcu/driver/devdrv/cuif/dsp_sram_ctrl_dvt/src/dsp_sram_ctrl_dvt.c
new file mode 100644
index 0000000..5d1daac
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/dsp_sram_ctrl_dvt/src/dsp_sram_ctrl_dvt.c
@@ -0,0 +1,543 @@
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+#include "reg_base.h"
+#include "mem_access_path_test.h"
+
+#include "RM_public.h"
+#include "drv_comm.h"
+#include "sync_data.h"
+
+/*******************************************************************************
+* Macro
+*******************************************************************************/
+//#define __BIG_RAM_TEST__
+
+/*
+ * for some component cannot be access from mcu, ex: usip cache/tbuf/btb
+ * rake tbuf, so we need to connect to dsp coretracer to check the value
+ *
+ * there are some problem with csys mask restore, so we can only test power down and sleep mode one by one
+ * i.e. don't open __MANUALLY_TEST_POWER_DOWN__ and __MANUALLY_TEST_SLEEP__ at the same time
+ */
+#if 0
+/* under construction !*/
+#else
+//#define __MANUALLY_TEST_SLEEP__
+#endif
+
+#define SRAM_CTRL_WRITE(addr, data) {DRV_WriteReg32(addr, data); MO_Sync();}
+
+typedef enum DSP_SRAM_CTRL {
+ DSP_SRAM_CTRL_POWER_DOWN_TYPE,
+ DSP_SRAM_CTRL_SLEEP_TYPE
+} DSP_SRAM_CTRL_TYPE;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+// #define BASE_MADDR_MDPERI_MD_TOPSM (0xA00D0000)
+// #define L1_BASE_MADDR_MODEM_TOPSM (0xA6000000)
+#define TOPSM_DSP_PWR_CTRL (BASE_MADDR_MDPERI_MD_TOPSM + 0x300)
+#define TOPSM_USIP_PWR_CTRL (BASE_MADDR_MDPERI_MD_TOPSM + 0x340)
+#define TOPSM_RAKE_PWR_CTRL (L1_BASE_MADDR_MODEM_TOPSM + 0x344)
+#define TOPSM_SCQ16_PWR_CTRL (L1_BASE_MADDR_MODEM_TOPSM + 0x144)
+#define L1_USIP_TIMER_CTRL (L1_BASE_MADDR_MODEM_TOPSM + 0x160)
+#define RAKE_SCQ_FORCE_ON_ADDR (L1_BASE_MADDR_MODEM_TOPSM + 0x14)
+
+#define SRAM_CTRL_USIP_ADDR (0xA01D0000)
+#define SRAM_CTRL_SCQ16_ADDR (0xA6120004)
+#define SRAM_CTRL_BIGRAM_ADDR (0xA612000C)
+#define SRAM_CTRL_RAKE_ADDR (0xA6120010)
+
+/* power down type: default value, the data on sram will lost if power-off */
+#define SRAM_CTRL_USIP_POWER_DOWN (0x3)
+#define SRAM_CTRL_SCQ16_POWER_DOWN (0x7FF)
+#define SRAM_CTRL_BIGRAM_POWER_DOWN (0x7)
+#define SRAM_CTRL_RAKE_POWER_DOWN (0xFF)
+
+/* sleep type, the data on sram will keep if power-off */
+#define SRAM_CTRL_USIP_SLEEP (0x0)
+#define SRAM_CTRL_SCQ16_SLEEP (0x0)
+#define SRAM_CTRL_BIGRAM_SLEEP (0x0)
+#define SRAM_CTRL_RAKE_SLEEP (0x0)
+
+#define USIP01_PWR_STA (BASE_MADDR_MDPERI_MD_TOPSM + 0xD4)
+#define RAKE_SCQ_PWR_STA (L1_BASE_MADDR_MODEM_TOPSM + 0xD4)
+
+//bit 2/3 = usip0/1
+#define USIP01_PWR_MASK (0x0000000C)
+//bit 5/6 = rake/bram
+#define RAKE_PWR_MASK (0x00000020)
+#define SCQ16_PWR_MASK (0x00000040)
+
+#define big_ram_base (0xa9000000)
+#define big_rame_size (0x100000)
+#define SRAM_CTRL_WRITE_PATTERN (0x55668877)
+
+#define USIP_UNGATE_ADDR_U0 (0xA1630400)
+#define USIP_UNGATE_ADDR_U1 (0xA1630404)
+#define USIP_UNGATE_ADDR_U2 (0xA1630408)
+#define USIP_UNGATE_ADDR_U3 (0xA163040c)
+
+#define USIP_EVENT_ADDR_U0 (0xA1630600)
+#define USIP_EVENT_ADDR_U1 (0xA1630604)
+#define USIP_EVENT_ADDR_U2 (0xA1630608)
+#define USIP_EVENT_ADDR_U3 (0xA163060c)
+
+#define USIP_USTIMER_CLR_U0 (0xA1630204)
+#define USIP_USTIMER_CLR_U1 (0xA1630284)
+#define USIP_USTIMER_CLR_U2 (0xA1630304)
+#define USIP_USTIMER_CLR_U3 (0xA1630384)
+
+
+/*******************************************************************************
+* Global variables
+*******************************************************************************/
+volatile ssdvt_uint32 ssdvt_usip_power_status = 0;
+volatile ssdvt_uint32 ssdvt_rake_power_status = 0;
+volatile ssdvt_uint32 ssdvt_scq16_power_status = 0;
+
+volatile ssdvt_uint32 ssdvt_usip_mask_backup = 0;
+volatile ssdvt_uint32 ssdvt_rake_mask_backup = 0;
+volatile ssdvt_uint32 ssdvt_scq16_mask_backup = 0;
+
+ssdvt_uint32 dsp_sram_base_addr[] = {usip0_itcm_base,
+ usip1_itcm_base,
+ usip0_dtcm_base,
+ usip1_dtcm_base,
+ rake_pm_base,
+ rake_dm_base,
+ SHARE_PM_base,
+ SHARE_DM_base,
+ PRIVATE_DM0_base,
+ PRIVATE_DM1_base,
+#if defined(__BIG_RAM_TEST__)
+ big_ram_base,
+#endif
+ };
+#if 1
+ssdvt_uint32 dsp_sram_base_size[] = {usip0_itcm_size,
+ usip1_itcm_size,
+ usip0_dtcm_size,
+ usip1_dtcm_size,
+ rake_pm_size,
+ rake_dm_size,
+ share_pm_size,
+ share_dm_size,
+ local_dm_size,
+ local_dm_size,
+#if defined(__BIG_RAM_TEST__)
+ big_rame_size,
+#endif
+ };
+#else
+/* under construction !*/
+/* under construction !*/
+#endif
+ssdvt_uint32 dsp_sram_number = sizeof(dsp_sram_base_addr) / sizeof(ssdvt_uint32);
+
+#if (defined(__MANUALLY_TEST_POWER_DOWN__) || defined(__MANUALLY_TEST_SLEEP__))
+volatile ssdvt_uint32 dsp_sram_test_stop = 1;
+#endif
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+
+void SSDVT_USIP_TCM_DATA_BACKUP()
+{
+ kal_mem_cpy(0xfcc0000, usip0_itcm_base, usip0_itcm_size);
+ kal_mem_cpy(0xfcd0000, usip0_dtcm_base, usip0_dtcm_size);
+ kal_mem_cpy(0xfce0000, usip1_itcm_base, usip1_itcm_size);
+ kal_mem_cpy(0xfcf0000, usip1_dtcm_base, usip1_dtcm_size);
+ Data_Sync_Barrier();
+}
+
+void SSDVT_USIP_TCM_DATA_RESTORE()
+{
+ kal_mem_cpy(usip0_itcm_base, 0xfcc0000, usip0_itcm_size);
+ kal_mem_cpy(usip0_dtcm_base, 0xfcd0000, usip0_dtcm_size);
+ kal_mem_cpy(usip1_itcm_base, 0xfce0000, usip1_itcm_size);
+ kal_mem_cpy(usip1_dtcm_base, 0xfcf0000, usip1_dtcm_size);
+ Data_Sync_Barrier();
+}
+
+void SSDVT_DSP_SRAM_CTRL_TEST_INIT()
+{
+ L1_RM_Module i;
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+ SSDVT_USIP_TCM_DATA_BACKUP();
+
+ // rake mask
+ ssdvt_rake_mask_backup = DRV_Reg32(TOPSM_RAKE_PWR_CTRL);
+ SRAM_CTRL_WRITE(TOPSM_RAKE_PWR_CTRL, 0x03030302);
+
+ // scq16 mask
+ ssdvt_scq16_mask_backup = DRV_Reg32(TOPSM_SCQ16_PWR_CTRL);
+ SRAM_CTRL_WRITE(TOPSM_SCQ16_PWR_CTRL, 0x3F3F3F21);
+
+ // clean all sw power-on source
+ for (i = 0; i < L1_NUMBER_OF_RESOURCE; i++)
+ {
+ L1_RM_Resource_Control(i, KAL_FALSE);
+ }
+
+ // set non force on
+ MODEM_TOPSM_NonForceOnMTCMOS(0xff);
+
+ SRAM_CTRL_WRITE(RAKE_SCQ_FORCE_ON_ADDR, 0xB2000D01);
+
+ // mask csys and cti, let dsp can power down when use debugger connect to iA
+ // set 1: mask it
+ ssdvt_usip_mask_backup = DRV_Reg32(TOPSM_DSP_PWR_CTRL);
+ // dsp cores mask - bit 0: csys, bit 1: cti
+ SRAM_CTRL_WRITE(TOPSM_DSP_PWR_CTRL, 0x3);
+
+ // mask 2/3/4G timer of usip
+ SRAM_CTRL_WRITE(L1_USIP_TIMER_CTRL, 0xFFFFFFFF);
+
+}
+
+void SSDVT_DSP_SRAM_CTRL_TEST_RESUME_MASK()
+{
+ SRAM_CTRL_WRITE(TOPSM_RAKE_PWR_CTRL, ssdvt_rake_mask_backup);
+
+ SRAM_CTRL_WRITE(TOPSM_SCQ16_PWR_CTRL, ssdvt_scq16_mask_backup);
+
+ SRAM_CTRL_WRITE(TOPSM_DSP_PWR_CTRL, ssdvt_usip_mask_backup);
+}
+
+
+void SSDVT_UNGATE_USIP()
+{
+
+ SRAM_CTRL_WRITE(USIP_USTIMER_CLR_U0, 0xFFFFFFFF);
+ SRAM_CTRL_WRITE(USIP_USTIMER_CLR_U1, 0xFFFFFFFF);
+ SRAM_CTRL_WRITE(USIP_USTIMER_CLR_U2, 0xFFFFFFFF);
+ SRAM_CTRL_WRITE(USIP_USTIMER_CLR_U3, 0xFFFFFFFF);
+
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U0, 0);
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U1, 0);
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U2, 0);
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U3, 0);
+
+ SRAM_CTRL_WRITE(USIP_EVENT_ADDR_U0, 1);
+ SRAM_CTRL_WRITE(USIP_EVENT_ADDR_U1, 1);
+ SRAM_CTRL_WRITE(USIP_EVENT_ADDR_U2, 1);
+ SRAM_CTRL_WRITE(USIP_EVENT_ADDR_U3, 1);
+}
+
+void SSDVT_GATE_USIP()
+{
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U0, 1);
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U1, 1);
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U2, 1);
+ SRAM_CTRL_WRITE(USIP_UNGATE_ADDR_U3, 1);
+}
+
+
+void SSDVT_CHECK_USIP_POWER_ON()
+{
+ do {
+ ssdvt_usip_power_status = DRV_Reg32(USIP01_PWR_STA) & USIP01_PWR_MASK;
+ } while (ssdvt_usip_power_status == 0);
+}
+
+void SSDVT_CHECK_USIP_POWER_OFF()
+{
+ do {
+ ssdvt_usip_power_status = DRV_Reg32(USIP01_PWR_STA) & USIP01_PWR_MASK;
+ } while (ssdvt_usip_power_status != 0);
+}
+
+
+void SSDVT_CHECK_RAKE_POWER_ON()
+{
+ do {
+ ssdvt_rake_power_status = DRV_Reg32(RAKE_SCQ_PWR_STA) & RAKE_PWR_MASK;
+ } while (ssdvt_rake_power_status == 0);
+}
+
+void SSDVT_CHECK_RAKE_POWER_OFF()
+{
+ do {
+ ssdvt_rake_power_status = DRV_Reg32(RAKE_SCQ_PWR_STA) & RAKE_PWR_MASK;
+ } while (ssdvt_rake_power_status != 0);
+}
+
+void SSDVT_CHECK_SCQ16_POWER_ON()
+{
+ do {
+ ssdvt_scq16_power_status = DRV_Reg32(RAKE_SCQ_PWR_STA) & SCQ16_PWR_MASK;
+ } while (ssdvt_scq16_power_status == 0);
+
+#if defined(__BIG_RAM_TEST__)
+ /* turn on bigram clock for bigram access later */
+ SRAM_CTRL_WRITE(0xAB810008, 0x7ff);
+ SRAM_CTRL_WRITE(0xAB830000, 0x1);
+ SRAM_CTRL_WRITE(0xAB860000, 0x10);
+ SSDVT_ASSERT_EQ(DRV_Reg32(0xAB810000), 0xFFFFF800);
+ SSDVT_ASSERT_EQ(DRV_Reg32(0xAB830000), 0x1);
+ SRAM_CTRL_WRITE(0xAB810008, 0x7ff);
+ SRAM_CTRL_WRITE(0xAB830000, 0x1);
+#endif
+}
+
+void SSDVT_CHECK_SCQ16_POWER_OFF()
+{
+ do {
+ ssdvt_scq16_power_status = DRV_Reg32(RAKE_SCQ_PWR_STA) & SCQ16_PWR_MASK;
+ } while (ssdvt_scq16_power_status != 0);
+}
+
+
+void SSDVT_FORCE_USIP_ON(void)
+{
+ MD_TOPSM_PWR_SW_Control(USIP0_PWR, KAL_TRUE);
+
+ SSDVT_CHECK_USIP_POWER_ON();
+}
+
+void SSDVT_FORCE_USIP_OFF(void)
+{
+ MD_TOPSM_PWR_SW_Control(USIP0_PWR, KAL_FALSE);
+
+ SSDVT_CHECK_USIP_POWER_OFF();
+}
+
+void SSDVT_FORCE_RAKE_ON(void)
+{
+ L1_RM_Resource_Control(L1_RAKE_REQ_FDD, KAL_TRUE);
+ while(L1_RM_Resource_CheckReady(L1_RAKE_REQ_FDD) == KAL_FALSE);
+
+ SSDVT_CHECK_RAKE_POWER_ON();
+}
+
+void SSDVT_FORCE_RAKE_OFF(void)
+{
+ L1_RM_Resource_Control(L1_RAKE_REQ_FDD, KAL_FALSE);
+ while(L1_RM_Resource_CheckReady(L1_RAKE_REQ_FDD) == KAL_TRUE);
+
+ SSDVT_CHECK_RAKE_POWER_OFF();
+}
+
+void SSDVT_FORCE_SCQ16_ON(void)
+{
+ L1_RM_Resource_Control(L1_BRAM_ALL_REQ_FDD, KAL_TRUE);
+ while(L1_RM_Resource_CheckReady(L1_BRAM_ALL_REQ_FDD) == KAL_FALSE);
+
+ SSDVT_CHECK_SCQ16_POWER_ON();
+}
+
+void SSDVT_FORCE_SCQ16_OFF(void)
+{
+ L1_RM_Resource_Control(L1_BRAM_ALL_REQ_FDD, KAL_FALSE);
+ while(L1_RM_Resource_CheckReady(L1_BRAM_ALL_REQ_FDD) == KAL_TRUE);
+
+ SSDVT_CHECK_SCQ16_POWER_OFF();
+}
+
+void SSDVT_DSP_POWER_ON()
+{
+ SSDVT_FORCE_SCQ16_ON();
+
+ SSDVT_FORCE_RAKE_ON();
+
+ SSDVT_FORCE_USIP_ON();
+}
+
+void SSDVT_DSP_POWER_OFF()
+{
+ SSDVT_FORCE_SCQ16_OFF();
+
+ SSDVT_FORCE_RAKE_OFF();
+
+ SSDVT_FORCE_USIP_OFF();
+}
+
+void SSDVT_CHECK_SRAM_CTRL_DEFAULT_VALUE()
+{
+ SSDVT_ASSERT_EQ(DRV_Reg32(SRAM_CTRL_USIP_ADDR), SRAM_CTRL_USIP_POWER_DOWN);
+
+ SSDVT_ASSERT_EQ(DRV_Reg32(SRAM_CTRL_SCQ16_ADDR), SRAM_CTRL_SCQ16_POWER_DOWN);
+
+ SSDVT_ASSERT_EQ(DRV_Reg32(SRAM_CTRL_RAKE_ADDR), SRAM_CTRL_RAKE_POWER_DOWN);
+}
+
+void SSDVT_SET_SRAM_TYPE_SLEEP()
+{
+ SRAM_CTRL_WRITE(SRAM_CTRL_USIP_ADDR, SRAM_CTRL_USIP_SLEEP);
+
+ SRAM_CTRL_WRITE(SRAM_CTRL_SCQ16_ADDR, SRAM_CTRL_SCQ16_SLEEP);
+
+ SRAM_CTRL_WRITE(SRAM_CTRL_BIGRAM_ADDR, SRAM_CTRL_BIGRAM_SLEEP);
+
+ SRAM_CTRL_WRITE(SRAM_CTRL_RAKE_ADDR, SRAM_CTRL_RAKE_SLEEP);
+}
+
+void SSDVT_SET_SRAM_TYPE_POWER_DOWN()
+{
+ SRAM_CTRL_WRITE(SRAM_CTRL_USIP_ADDR, SRAM_CTRL_USIP_POWER_DOWN);
+
+ SRAM_CTRL_WRITE(SRAM_CTRL_SCQ16_ADDR, SRAM_CTRL_SCQ16_POWER_DOWN);
+
+ SRAM_CTRL_WRITE(SRAM_CTRL_BIGRAM_ADDR, SRAM_CTRL_BIGRAM_POWER_DOWN);
+
+ SRAM_CTRL_WRITE(SRAM_CTRL_RAKE_ADDR, SRAM_CTRL_RAKE_POWER_DOWN);
+}
+
+
+void SSDVT_WRITE_DATA_TO_DSP_SRAM()
+{
+ ssdvt_uint32 i;
+ ssdvt_uint32 j = 0;
+ for (i = 0; i < dsp_sram_number; i++)
+ {
+ for (j = 0; j < dsp_sram_base_size[i]; j += 4)
+ {
+ SRAM_CTRL_WRITE(dsp_sram_base_addr[i] + j, (dsp_sram_base_addr[i] + j));
+ }
+ }
+}
+
+
+void SSDVT_READ_DATA_FROM_DSP_SRAM(const DSP_SRAM_CTRL_TYPE sram_ctrl_type, const ssdvt_uint32 expect_value)
+{
+ ssdvt_uint32 i;
+ ssdvt_uint32 j = 0;
+ for (i = 0; i < dsp_sram_number; i++)
+ {
+ for (j = 0; j < dsp_sram_base_size[i]; j += 4)
+ {
+ if (DSP_SRAM_CTRL_POWER_DOWN_TYPE == sram_ctrl_type)
+ {
+ if (DRV_Reg32(dsp_sram_base_addr[i] + j) == (dsp_sram_base_addr[i] + j))
+ {
+ ERROR_LOOP
+ }
+ }
+ else if (DSP_SRAM_CTRL_SLEEP_TYPE == sram_ctrl_type)
+ {
+ SSDVT_ASSERT_EQ(DRV_Reg32(dsp_sram_base_addr[i] + j), (dsp_sram_base_addr[i] + j));
+ }
+ else
+ {
+ SSDVT_ASSERT_EQ(1, 2);
+ }
+ }
+ }
+}
+
+void SSDVT_SRAM_CTRL_TYPE_TEST(const DSP_SRAM_CTRL_TYPE sram_ctrl_type)
+{
+ if (DSP_SRAM_CTRL_POWER_DOWN_TYPE == sram_ctrl_type)
+ {
+ SSDVT_SET_SRAM_TYPE_POWER_DOWN();
+ }
+ else if (DSP_SRAM_CTRL_SLEEP_TYPE == sram_ctrl_type)
+ {
+ SSDVT_SET_SRAM_TYPE_SLEEP();
+ }
+ else
+ {
+ SSDVT_ASSERT_EQ(1, 2);
+ }
+
+ SSDVT_DSP_POWER_ON();
+
+#if !(defined(__MANUALLY_TEST_POWER_DOWN__) || defined(__MANUALLY_TEST_SLEEP__))
+ SSDVT_WRITE_DATA_TO_DSP_SRAM();
+#else
+ SSDVT_DELAY_LOOP(0x1000000);
+ SSDVT_DELAY_LOOP(0x1000000);
+ SSDVT_DELAY_LOOP(0x1000000);
+ SSDVT_GATE_USIP();
+#endif
+
+ SSDVT_DSP_POWER_OFF();
+
+ SSDVT_DSP_POWER_ON();
+
+#if !(defined(__MANUALLY_TEST_POWER_DOWN__) || defined(__MANUALLY_TEST_SLEEP__))
+ SSDVT_READ_DATA_FROM_DSP_SRAM(sram_ctrl_type, SRAM_CTRL_WRITE_PATTERN);
+
+ //SSDVT_CHECK_DATA(sram_ctrl_type, SRAM_CTRL_WRITE_PATTERN);
+#else
+ if (DSP_SRAM_CTRL_POWER_DOWN_TYPE == sram_ctrl_type)
+ {
+ SSDVT_USIP_TCM_DATA_RESTORE();
+ }
+ SSDVT_UNGATE_USIP();
+#endif
+}
+
+void SSDVT_SRAM_CTRL_TEST()
+{
+ /* let dsp cores can power-ff */
+ SSDVT_DSP_SRAM_CTRL_TEST_INIT();
+
+ /* init value test */
+ SSDVT_CHECK_SRAM_CTRL_DEFAULT_VALUE();
+
+#if !defined(__MANUALLY_TEST_SLEEP__)
+ /* SRAM control type : power down */
+ SSDVT_SRAM_CTRL_TYPE_TEST(DSP_SRAM_CTRL_POWER_DOWN_TYPE);
+
+#if defined(__MANUALLY_TEST_POWER_DOWN__)
+ SSDVT_DSP_SRAM_CTRL_TEST_RESUME_MASK();
+
+ // stop here to attach dsp debugger to check the data
+ while(1 == dsp_sram_test_stop);
+ dsp_sram_test_stop = 1;
+
+ //SSDVT_DSP_SRAM_CTRL_TEST_INIT();
+#endif // defined(__MANUALLY_TEST_SLEEP__)
+
+#endif // !defined(__MANUALLY_TEST_SLEEP__)
+ /* SRAM control type : sleep */
+ SSDVT_SRAM_CTRL_TYPE_TEST(DSP_SRAM_CTRL_SLEEP_TYPE);
+
+#if defined(__MANUALLY_TEST_SLEEP__)
+ SSDVT_DSP_SRAM_CTRL_TEST_RESUME_MASK();
+
+ // stop here to attach dsp debugger to check the data
+ while(1 == dsp_sram_test_stop);
+ dsp_sram_test_stop = 1;
+#endif
+
+ ssdvt_test_pass_notification();
+
+ return;
+}
+
+
+
diff --git a/mcu/driver/devdrv/cuif/inc/drv_cuif.h b/mcu/driver/devdrv/cuif/inc/drv_cuif.h
new file mode 100644
index 0000000..088e165
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/inc/drv_cuif.h
@@ -0,0 +1,523 @@
+#ifndef __DRV_CUIF_H__
+#define __DRV_CUIF_H__
+
+
+#include "cuif_l1core_public.h"
+
+#include "intrCtrl.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+#include "sync_data.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+
+#define __CUIF_DEBUG__
+
+/*******************************************************************************
+ * CUIF Memory Definition
+ *******************************************************************************/
+
+/* Control Register Offset */
+#define CUIF_INTERRUPT_STATUS_OFFSET (0x00)
+#define CUIF_INTERRUPT_SET_OFFSET (0x04)
+#define CUIF_INTERRUPT_CLEAR_OFFSET (0x08)
+#define CUIF_INTERRUPT_EN_OFFSET (0x0C)
+#define CUIF_INTERRUPT_EN_SET_OFFSET (0x10)
+#define CUIF_INTERRUPT_EN_CLR_OFFSET (0x14)
+
+#define CUIF_INTERRUPT_STA_EN_OFFSET (CUIF_INTERRUPT_EN_OFFSET - CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_INTERRUPT_NEXT_INT_OFFSET (0x18)
+
+
+/* C2U Core Offset*/
+#define CUIF_C2U_INNER (0x00 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_C2U_OUTER (0x18 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#if defined(__MD97__) || defined(__MD98__)
+
+#if defined(__SSDVT_CUIF_TEST__)
+
+#define CUIF_C2U_FEC (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_C2U_SPEECH (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#else
+
+#define CUIF_C2U_SPEECH (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_C2U_FEC (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#endif
+
+#else
+
+#define CUIF_C2U_FEC (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_C2U_SPEECH (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#endif
+
+/* C2U INNER */
+#define CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_C2U_INNER_INTERRUPT_SET_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_C2U_INNER_INTERRUPT_EN_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+
+/* C2U OUTER */
+#define CUIF_C2U_OUTER_INTERRUPT_STATUS_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_C2U_OUTER_INTERRUPT_SET_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_C2U_OUTER_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_C2U_OUTER_INTERRUPT_EN_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_C2U_OUTER_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_C2U_OUTER_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* C2U FEC */
+#define CUIF_C2U_FEC_INTERRUPT_STATUS_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_C2U_FEC_INTERRUPT_SET_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_C2U_FEC_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_C2U_FEC_INTERRUPT_EN_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_C2U_FEC_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_C2U_FEC_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* C2U SPEECH */
+#define CUIF_C2U_SPEECH_INTERRUPT_STATUS_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_C2U_SPEECH_INTERRUPT_SET_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_C2U_SPEECH_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_C2U_SPEECH_INTERRUPT_EN_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_C2U_SPEECH_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_C2U_SPEECH_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C Core Offset*/
+
+#if defined(__MD93__)
+
+/* U2C Core Offset*/
+/* to iA core0 VPE0 */
+#define CUIF_U2C_N0 (0x60 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+/* to iA core0 VPE1 */
+#define CUIF_U2C_N1 (0x78 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N2 (0x90 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N3 (0xa8 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+/* to iA core1 VPE1 */
+#define CUIF_U2C_N4 (0xc0 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#define CUIF_U2C_WAKEUP (0xd8 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#elif defined(__MD95__)
+
+/* to iA core0 VPE0 */
+#define CUIF_U2C_N0 (0x90 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+/* to iA core0 VPE1 */
+#define CUIF_U2C_N1 (0xa8 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N2 (0xc0 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N3 (0xd8 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+/* to iA core1 VPE0/1 */
+#define CUIF_U2C_N4 (0xf0 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N5 (0x108 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N6 (0x120 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#define CUIF_U2C_WAKEUP (0x138 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define CUIF_U2C_N0 (0xA00 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N1 (0xA18 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N2 (0xA30 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N3 (0xA48 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N4 (0xA60 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N5 (0xA78 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N6 (0xA90 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N7 (0xAA8 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N8 (0xAC0 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N9 (0xAD8 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N10 (0xAF0 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N11 (0xB08 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N12 (0xB20 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+#define CUIF_U2C_N13 (0xB38 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#define CUIF_U2C_WAKEUP (0x120 + BASE_MADDR_USIP_CROSS_CORE_CTRL)
+
+#else
+#error "not support this arch!!!!"
+#endif
+
+/* U2C N0 */
+#define CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N0_INTERRUPT_SET_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N0_INTERRUPT_EN_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N1 */
+#define CUIF_U2C_N1_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N1_INTERRUPT_SET_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N1_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N1_INTERRUPT_EN_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N1_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N1_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N2 */
+#define CUIF_U2C_N2_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N2_INTERRUPT_SET_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N2_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N2_INTERRUPT_EN_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N2_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N2_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N3 */
+#define CUIF_U2C_N3_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N3_INTERRUPT_SET_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N3_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N3_INTERRUPT_EN_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N3_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N3_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N4 */
+#define CUIF_U2C_N4_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N4_INTERRUPT_SET_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N4_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N4_INTERRUPT_EN_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N4_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N4_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+#if defined(__MD95__)
+
+/* U2C N5 */
+#define CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_EN_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N6 */
+#define CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_EN_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+/* U2C N5 */
+#define CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_EN_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N6 */
+#define CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_EN_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N7 */
+#define CUIF_U2C_N7_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N7_INTERRUPT_SET_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N7_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N7_INTERRUPT_EN_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N7_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N7_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N8 */
+#define CUIF_U2C_N8_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N8_INTERRUPT_SET_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N8_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N8_INTERRUPT_EN_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N8_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N8_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N9 */
+#define CUIF_U2C_N9_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N9_INTERRUPT_SET_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N9_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N9_INTERRUPT_EN_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N9_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N9_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N10 */
+#define CUIF_U2C_N10_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N10_INTERRUPT_SET_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N10_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N10_INTERRUPT_EN_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N10_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N10_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N11 */
+#define CUIF_U2C_N11_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N11_INTERRUPT_SET_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N11_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N11_INTERRUPT_EN_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N11_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N11_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N12 */
+#define CUIF_U2C_N12_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N12_INTERRUPT_SET_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N12_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N12_INTERRUPT_EN_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N12_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N12_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C N13 */
+#define CUIF_U2C_N13_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_N13_INTERRUPT_SET_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_N13_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_N13_INTERRUPT_EN_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_N13_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_N13_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+/* U2C WAKEUP */
+#define CUIF_U2C_WAKEUP_INTERRUPT_STATUS_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_STATUS_OFFSET)
+#define CUIF_U2C_WAKEUP_INTERRUPT_SET_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_SET_OFFSET)
+#define CUIF_U2C_WAKEUP_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_CLEAR_OFFSET)
+#define CUIF_U2C_WAKEUP_INTERRUPT_EN_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_OFFSET)
+#define CUIF_U2C_WAKEUP_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_SET_OFFSET)
+#define CUIF_U2C_WAKEUP_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_CLR_OFFSET)
+
+#endif
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+
+ /* C2U */
+#define CUIF_C2U_STATUS_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET))
+#define CUIF_C2U_SET_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_SET_OFFSET))
+#define CUIF_C2U_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET))
+#define CUIF_C2U_EN_STATUS_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_OFFSET))
+#define CUIF_C2U_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET))
+#define CUIF_C2U_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET))
+
+
+/* U2C */
+#define CUIF_U2C_STATUS_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET))
+#define CUIF_U2C_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_SET_OFFSET))
+#define CUIF_U2C_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET))
+#define CUIF_U2C_EN_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_OFFSET))
+#define CUIF_U2C_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET))
+#define CUIF_U2C_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET))
+
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* U2C WAKEUP*/
+#define CUIF_U2C_WAKEUP_STATUS_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_STATUS_OFFSET))
+#define CUIF_U2C_WAKEUP_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_SET_OFFSET))
+#define CUIF_U2C_WAKEUP_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_CLEAR_OFFSET))
+#define CUIF_U2C_WAKEUP_EN_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_OFFSET))
+#define CUIF_U2C_WAKEUP_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_SET_OFFSET))
+#define CUIF_U2C_WAKEUP_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_CLR_OFFSET))
+#endif
+
+#define CUIF_TRUE KAL_TRUE
+#define CUIF_FALSE KAL_FALSE
+
+
+/* Read/Write macros */
+#define CUIF_REG_READ(addr) *(volatile cuif_uint32*)(addr)
+#define CUIF_REG_WRITE(addr, value) do{DRV_WriteReg32(addr, value); MO_Sync();}while(0);
+
+
+#define CUIF_NULL NULL
+#define CUIF_ASSERT(expr, c1, c2, c3) EXT_ASSERT(expr, c1, c2, c3)
+#define CUIF_GET_RETURN_ADDRESS(a) GET_RETURN_ADDRESS(a)
+
+#define CUIF_CLZ(z) __builtin_clz((z))
+#define CUIF_GET_LSB(b) (31 - CUIF_CLZ((b) & -(b)))
+
+#if defined(__MD93__) || defined(__MD95__)
+
+#define IRQID_CUIF_U2C_IRQ_N0 IRQ_USIP0_0_CODE
+#define IRQID_CUIF_U2C_IRQ_N1 IRQ_USIP1_0_CODE
+#define IRQID_CUIF_U2C_IRQ_N2 IRQ_USIP2_0_CODE
+#define IRQID_CUIF_U2C_IRQ_N3 IRQ_USIP3_0_CODE
+#define IRQID_CUIF_U2C_IRQ_N4 IRQ_USIP0_1_CODE
+
+#if defined(__MD95__)
+#define IRQID_CUIF_U2C_IRQ_N5 IRQ_USIP1_1_CODE
+#define IRQID_CUIF_U2C_IRQ_N6 IRQ_USIP2_1_CODE
+#endif
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define IRQID_CUIF_U2C_IRQ_N0 IRQ_USIP0_CODE
+#define IRQID_CUIF_U2C_IRQ_N1 IRQ_USIP1_CODE
+#define IRQID_CUIF_U2C_IRQ_N2 IRQ_USIP2_CODE
+#define IRQID_CUIF_U2C_IRQ_N3 IRQ_USIP3_CODE
+#define IRQID_CUIF_U2C_IRQ_N4 IRQ_USIP4_CODE
+#define IRQID_CUIF_U2C_IRQ_N5 IRQ_USIP5_CODE
+#define IRQID_CUIF_U2C_IRQ_N6 IRQ_USIP6_CODE
+#define IRQID_CUIF_U2C_IRQ_N7 IRQ_USIP7_CODE
+#define IRQID_CUIF_U2C_IRQ_N8 IRQ_USIP8_CODE
+#define IRQID_CUIF_U2C_IRQ_N9 IRQ_USIP9_CODE
+#define IRQID_CUIF_U2C_IRQ_N10 IRQ_USIP10_CODE
+#define IRQID_CUIF_U2C_IRQ_N11 IRQ_USIP11_CODE
+#define IRQID_CUIF_U2C_IRQ_N12 IRQ_USIP12_CODE
+#define IRQID_CUIF_U2C_IRQ_N13 IRQ_USIP13_CODE
+
+#endif
+
+
+#if defined(__MD93__)
+#define CUIF_VPE_NUM (4)
+#elif defined(__MD95__)
+#define CUIF_VPE_NUM (6)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CUIF_VPE_NUM (12)
+#endif
+/* because reg is type of int, reg + 1 = addr + 4 */
+#define REG_OFFSET(mID) (mID * 6)
+
+#define ARRAY_OFFSET(mID) (mID)
+
+
+/* cuif handler*/
+#if !defined(__CUIF_DEBUG__)
+#define CUIF_HANDLER(nID) \
+cuif_InterruptHandlerInternal( \
+ CUIF_U2C_STATUS_BASE + REG_OFFSET(nID), \
+ CUIF_U2C_EN_BASE + REG_OFFSET(nID), \
+ CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), \
+ cuif_isr_handler[ARRAY_OFFSET(nID)], \
+ cuif_isr_eoi[ARRAY_OFFSET(nID)])
+#else /* __CUIF_DEBUG__ */
+#define CUIF_HANDLER(nID) \
+cuif_InterruptHandlerInternal( \
+ CUIF_U2C_STATUS_BASE + REG_OFFSET(nID), \
+ CUIF_U2C_EN_BASE + REG_OFFSET(nID), \
+ CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), \
+ cuif_isr_handler[ARRAY_OFFSET(nID)], \
+ cuif_isr_eoi[ARRAY_OFFSET(nID)], \
+ nID)
+#endif /* __CUIF_DEBUG__ */
+
+
+
+/* cuif overflow debug info */
+typedef struct{
+ cuif_uint32 receiver; /**< The mcu receiver: 0~4 means n0~n4 */
+ cuif_uint32 interrupt_bit; /**< The overflow bit */
+ cuif_uint32 status_addr; /**< The addr of the status register */
+ cuif_uint32 current_status;/**< The current value of the status register */
+ cuif_uint32 caller; /**< The caller address */
+ cuif_uint32 time;
+}CUIF_OverFlowRecord;
+
+/**
+ * CUIF Init function
+ */
+extern void CUIF_Init();
+
+
+/*******************************************************************************
+ * Debug feature
+ *******************************************************************************/
+#if defined(__CUIF_DEBUG__)
+
+#if __CUIF_MD32S_CORE__
+/* MD32 side */
+#define CUIF_DEBUG_API_RECORD_SIZE 8
+#define CUIF_DEBUG_ISR_HANDLE_CODE_SIZE 8
+
+#else /* __CUIF_MD32S_CORE__ */
+
+#define CUIF_DEBUG_API_RECORD_SIZE 16
+#define CUIF_DEBUG_ISR_HANDLE_CODE_SIZE 16
+
+#endif /* __CUIF_MD32S_CORE__ */
+
+typedef struct{
+ cuif_uint32 time;
+ cuif_uint32 code;
+}CUIF_DebugISRRecord;
+
+/** The Ring Buffer */
+typedef struct{
+ CUIF_DebugISRRecord records[CUIF_DEBUG_ISR_HANDLE_CODE_SIZE];
+ cuif_uint32 top_index;
+}CUIF_DebugISRCodeList;
+
+typedef struct{
+ cuif_uint32 time;
+ cuif_uint32 status;
+ cuif_uint32 set_addr; /**< The control register address */
+ cuif_uint32 set_value; /**< The writing value for the control regsiters */
+ cuif_uint32 caller; /**< The caller address */
+}CUIF_DebugRecord;
+
+/** The Ring Buffer */
+typedef struct{
+ CUIF_DebugRecord records[CUIF_DEBUG_API_RECORD_SIZE];
+ kal_atomic_uint32 top_index;
+}CUIF_DebugRecordList;
+
+void cuif_DebugAddRecord(cuif_uint32 status,
+ volatile cuif_uint32* set_addr,
+ cuif_uint32 set_value,
+ cuif_uint32 caller);
+
+void cuif_DebugAddISRHandleCode(cuif_uint32 code, CUIF_MCU_INT nID);
+
+#endif /* __CUIF_DEBUG__ */
+
+
+
+#if defined(__CUIF_DRV_TEST__)
+
+
+//#include "dsp_header_define_cuif_inner_brp.h"
+#define CUIF_INNER_BRP_BASE ((kal_uint32)(0xA0840000)) // Bank A: L1 normal access.
+#define CUIF_SYNC_ADDR_USIP0 ((CUIF_INNER_BRP_BASE) + 0x2000)
+
+#if defined(__MD97__) || defined(__MD97P__)
+//#include "dsp_header_define_cuif_speech.h"
+#define CUIF_SPEECH_BASE ((kal_uint32)(0xA0944700))
+#define CUIF_SYNC_ADDR_USIP1 ((CUIF_SPEECH_BASE) + 0x2000)
+#else
+#include "dsp_header_define_cuif_fec_wbrp.h"
+#define CUIF_SYNC_ADDR_USIP1 ((CUIF_FEC_WBRP_BASE) + 0x2000)
+#endif
+
+#define INT INVALID_INT
+#define UINT INVALID_UINT
+#define INT32 INVALID_INT32
+#define UINT32 INVALID_UINT32
+
+#define CUIF_DRV_TEST_ASSERT_EQ(a, b) \
+ do{ \
+ if((a) != (b)){ \
+ dbg_print("Error: %s: %d - %d != %d\n", __FILE__, __LINE__, (a), (b)); \
+ while(1); \
+ } \
+ }while(0)
+
+extern cuif_uint32 cuif_c2u_int_source_num[CUIF_ENUM_ALL_USIP_INT_NUM];
+extern cuif_uint32 cuif_u2c_int_source_num[CUIF_ENUM_ALL_MCU_INT_NUM - 1];
+
+extern void CUIF_DriverTestISR_N0(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N1(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N2(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N3(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N4(CUIF_Mask_t* mask);
+#if defined(__MD97__) || defined(__MD97P__)
+extern void CUIF_DriverTestISR_N5(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N6(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N7(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N8(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N9(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N10(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N11(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N12(CUIF_Mask_t* mask);
+extern void CUIF_DriverTestISR_N13(CUIF_Mask_t* mask);
+#endif
+
+#endif /* __CUIF_DRV_TEST__ */
+
+
+#endif /* __DRV_CUIF_H__ */
diff --git a/mcu/driver/devdrv/cuif/pmu_cc_test/inc/pmu_cc_test.h b/mcu/driver/devdrv/cuif/pmu_cc_test/inc/pmu_cc_test.h
new file mode 100644
index 0000000..dbcc9ba
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/pmu_cc_test/inc/pmu_cc_test.h
@@ -0,0 +1,4 @@
+#ifndef __PMU_CC_TEST_H__
+#define __PMU_CC_TEST_H__
+extern void SSDVT_PMU_Cross_Core();
+#endif
diff --git a/mcu/driver/devdrv/cuif/pmu_cc_test/src/pmu_cc_test.c b/mcu/driver/devdrv/cuif/pmu_cc_test/src/pmu_cc_test.c
new file mode 100644
index 0000000..762c789
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/pmu_cc_test/src/pmu_cc_test.c
@@ -0,0 +1,74 @@
+#include"pmu_cc_test.h"
+#include "drv_cuif.h"
+#include "dsp_header_define_cuif_inner_brp.h"
+#define CUIF_ADDR_USIP0 ((CUIF_INNER_BRP_BASE)+0x2000)
+#include "dsp_header_define_cuif_fec_wbrp.h"
+#if defined(__MD93__)
+#define CUIF_ADDR_USIP1 ((CUIF_FEC_WBRP_BASE)+0x2000)
+#define USIP0_DTCM_BASE 0xA1040000
+#define USIP1_DTCM_BASE 0xA1140000
+#elif defined(__MD95__)
+#define CUIF_ADDR_USIP1 ((CUIF_FEC_SS_BASE)+0x2000)
+#define USIP0_DTCM_BASE 0xA1040000
+#define USIP1_DTCM_BASE 0xA1140000
+#elif defined(__MD97__)
+#define CUIF_ADDR_USIP1 ((CUIF_FEC_SS_BASE)+0x200)
+#define USIP0_DTCM_BASE 0xA0840000
+#define USIP1_DTCM_BASE 0xA0940000
+#else
+ #error "Unsupporting project!!"
+#endif
+
+
+void cuif_test_sync(kal_uint32 usip0or1)
+{
+ volatile cuif_uint32* sync;
+ if (usip0or1==0)
+ {
+ sync = (volatile cuif_uint32*)CUIF_ADDR_USIP0;
+ }
+ else
+ {
+ sync = (volatile cuif_uint32*)CUIF_ADDR_USIP1;
+ }
+ // MCU Part
+ while(sync[1] == 2) ;
+ sync[1] = 2;
+
+ while(sync[0] == 1) ;
+ sync[0] = 1;
+}
+
+
+
+void MCU_Transaction_to_uSIP(kal_uint32 usip0_or_1)
+{
+ volatile kal_uint32 temp;
+ volatile kal_uint32 address;
+ if (usip0_or_1==0)
+ {
+ address=USIP0_DTCM_BASE;
+ }
+ else
+ {
+ address=USIP1_DTCM_BASE;
+ }
+ *(kal_uint32*)(address)=0x12345678;
+ temp=*(kal_uint32*)(address);
+ while(temp==0x12345678)
+ {
+ cuif_test_sync(usip0_or_1);
+ temp=*(volatile kal_uint32*)(address);
+ temp=*(volatile kal_uint32*)(address);
+ temp=*(volatile kal_uint32*)(address);
+ temp=*(volatile kal_uint32*)(address);
+ }
+}
+
+void SSDVT_PMU_Cross_Core()
+{
+ MCU_Transaction_to_uSIP(0);
+ MCU_Transaction_to_uSIP(1);
+
+
+}
diff --git a/mcu/driver/devdrv/cuif/src/drv_cuif.c b/mcu/driver/devdrv/cuif/src/drv_cuif.c
new file mode 100644
index 0000000..fc02320
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/src/drv_cuif.c
@@ -0,0 +1,439 @@
+#include "drv_cuif.h"
+#include "kal_hrt_api.h"
+#if defined(__CUIF_DEBUG__)
+#include "us_timer.h"
+#endif
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+#if defined(__CUIF_DEBUG__)
+extern CUIF_DebugRecordList cuif_debug_records[CUIF_VPE_NUM];
+#endif
+
+
+#if !defined(__CUIF_DEBUG__)
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi);
+#else /* __CUIF_DEBUG__ */
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi,
+ CUIF_MCU_INT nID);
+#endif /* __CUIF_DEBUG__ */
+
+/*******************************************************************************
+ * Functions - Common Part
+ *******************************************************************************/
+void CUIF_DefaultISR(CUIF_Mask_t* mask)
+{
+ // code 1: status register value, code 2: enable register vale, code 3: n0~n4 (0~4)
+ CUIF_ASSERT(0, CUIF_REG_READ(mask->status_reg_addr),
+ CUIF_REG_READ((cuif_uint32)mask->status_reg_addr + CUIF_INTERRUPT_STA_EN_OFFSET),
+ ((cuif_uint32)mask->status_reg_addr - (cuif_uint32)CUIF_U2C_STATUS_BASE) / CUIF_INTERRUPT_NEXT_INT_OFFSET);
+}
+
+#if defined(__CUIF_DEBUG__)
+void cuif_DebugAddRecord(cuif_uint32 status,
+ volatile cuif_uint32* set_addr,
+ cuif_uint32 set_value,
+ cuif_uint32 caller)
+{
+ cuif_uint32 save_index = 0;
+ cuif_uint32 vpe_id = kal_get_current_vpe_id();
+ CUIF_ASSERT(vpe_id < CUIF_VPE_NUM, vpe_id, CUIF_VPE_NUM, 0);
+
+ CUIF_DebugRecordList *cuif_debug_records_ptr = &cuif_debug_records[vpe_id];
+
+ //cuif_uint32 mask;
+ //mask = kal_hrt_SaveAndSetIRQMask();
+
+ // fetch and add top_index atomically.
+ //save_index = cuif_debug_records_ptr->top_index;
+ save_index = kal_atomic_inc_circular_index(&(cuif_debug_records_ptr -> top_index), CUIF_DEBUG_ISR_HANDLE_CODE_SIZE);
+ //++(cuif_debug_records_ptr->top_index);
+ //if(cuif_debug_records_ptr->top_index == CUIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ // cuif_debug_records_ptr->top_index = 0;
+ //}
+
+ //kal_hrt_RestoreIRQMask(mask);
+
+ cuif_debug_records_ptr->records[save_index].time = ust_get_current_time();
+ cuif_debug_records_ptr->records[save_index].status = status;
+ cuif_debug_records_ptr->records[save_index].set_addr = (cuif_uint32)set_addr;
+ cuif_debug_records_ptr->records[save_index].set_value = set_value;
+ cuif_debug_records_ptr->records[save_index].caller = caller;
+}
+#endif /* __CUIF_DEBUG__ */
+
+
+/**
+ * General interrupt handler function
+ *
+ * @param[in] sreg CUIF interrupt status register
+ * @param[in] creg CUIF interrupt clean register
+ * @param[in] handler CUIF user entry function lists
+ * @param[in] core CUIF interrupt core type - BRP, DFE and RAKE (Debug only)
+ * @param[in] interrupt_type CUIF interrupt type - U3G or U4G (Debug only)
+ **/
+#if !defined(__CUIF_DEBUG__)
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi
+ )
+#else /* __CUIF_DEBUG__ */
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi,
+ CUIF_MCU_INT nID)
+#endif /* __CUIF_DEBUG__ */
+{
+ cuif_uint32 eidx; // entry function index
+ CUIF_Mask_t cuif_mask;
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ // for debug when no register callback
+ cuif_mask.status_reg_addr = (cuif_uint32*)sreg;
+
+ // read the sreg to the mask
+ cuif_mask.mask31_0 = CUIF_REG_READ(sreg) & CUIF_REG_READ(ereg);
+
+ while(cuif_mask.mask31_0){
+ // find the lsb
+ eidx = CUIF_GET_LSB(cuif_mask.mask31_0);
+
+ // invoke the user register interupt handler function
+ (*handler[eidx])((CUIF_Mask_t *)&cuif_mask);
+
+ // if the `irq_auto_eoi` is CUIF_TRUE, clean the interupt bit
+ if(auto_eoi[eidx] == CUIF_TRUE){
+
+ CUIF_REG_WRITE(creg, 1 << eidx);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(cuif_mask.mask31_0, creg, (1 << eidx), caller);
+#endif /* __CUIF_DEBUG__ */
+ }
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddISRHandleCode(eidx, nID);
+#endif /* __CUIF_DEBUG__ */
+
+ // read the sreg to the mask
+ cuif_mask.mask31_0 = CUIF_REG_READ(sreg) & CUIF_REG_READ(ereg);
+ }
+}
+
+
+/*******************************************************************************
+ * Functions - Driver test
+ *******************************************************************************/
+
+#if defined(__CUIF_DRV_TEST__)
+
+
+extern cuif_uint32 cuif_drvtest_case;
+extern cuif_uint32 cuif_drvtest_prev_irq;
+extern cuif_uint32 cuif_drvtest_irq_test_success;
+
+extern void CUIF_DriverAPIU2CTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID);
+extern void CUIF_DriverAPIC2UTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID);
+
+extern void CUIF_DriverISRTestC2U(CUIF_MODULE_INDEX moduleID, cuif_uint32 case_num);
+extern void CUIF_DriverISRTestU2C(CUIF_MCU_INT nID, cuif_uint32 case_num, CUIF_MODULE_INDEX moduleID);
+
+void cuif_drv_test_sync(CUIF_MODULE_INDEX moduleID)
+{
+ volatile cuif_uint32* sync;
+ if (CUIF_ENUM_INNER == moduleID || CUIF_ENUM_OUTER == moduleID)
+ {
+ sync = (volatile cuif_uint32*)CUIF_SYNC_ADDR_USIP0;
+ }
+ else
+ {
+ sync = (volatile cuif_uint32*)CUIF_SYNC_ADDR_USIP1;
+ }
+ // MCU Part
+ while(sync[1] == 1) ;
+ sync[1] = 1;
+
+ while(sync[0] == 0) ;
+ sync[0] = 0;
+}
+
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0
+#define EN_ALL_MASK 0xFFFFFFFF
+
+void CUIF_DisableInterrupt()
+{
+ #if defined(__MD93__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD95__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+ #endif
+}
+
+void CUIF_EnableInterrupt()
+{
+ #if defined(__MD93__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD95__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+ #endif
+}
+
+void CUIF_ENABLE_ALL_CHECK()
+{
+ cuif_uint8 nID;
+ cuif_uint32 set_mask;
+ cuif_uint32 get_mask;
+ cuif_uint8 irq_num;
+
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ #if defined(__MD93__)
+ if (nID == 0 || nID == 4)
+ { // skip WFI bits
+ irq_num = 4;
+ }
+ else
+ {
+ irq_num = 0;
+ }
+ #elif defined(__MD95__)
+ if (nID == 0 || nID == 5 || nID == 6)
+ { // skip WFI bits
+ irq_num = 6;
+ }
+ else
+ {
+ irq_num = 0;
+ }
+ #elif defined(__MD97__) || defined(__MD97P__)
+ irq_num = 6;
+ #endif
+
+ set_mask = 0;
+ for(; irq_num < cuif_u2c_int_source_num[nID]; irq_num++)
+ {
+ set_mask |= 1 << irq_num;
+ }
+ get_mask = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET(nID));
+ CUIF_DRV_TEST_ASSERT_EQ(get_mask, set_mask);
+ dbg_print("Enable n%d - Pass\n", nID);
+ }
+}
+
+void CUIF_DISABLE_ALL_CHECK()
+{
+ CUIF_Mask_t mask;
+
+ CUIF_N0_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N1_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N2_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N3_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N4_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ #if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ CUIF_N5_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N6_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+ #endif
+
+ #if defined(__MD97__) || defined(__MD97P__)
+ CUIF_N7_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N8_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N9_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N10_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N11_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N12_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N13_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+ #endif
+}
+
+void CUIF_EN_STA_API_TEST()
+{
+ CUIF_EnableInterrupt();
+ CUIF_ENABLE_ALL_CHECK();
+ CUIF_DisableInterrupt();
+ CUIF_DISABLE_ALL_CHECK();
+}
+
+void CUIF_DriverAPITest()
+{
+ cuif_uint8 mID;
+ cuif_uint8 nID;
+
+ CUIF_EN_STA_API_TEST();
+
+#if 0
+/* under construction !*/
+#else
+ for(mID = 0; mID < 1; mID++)
+#endif
+ {
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ CUIF_DriverAPIU2CTest(mID, nID);
+ CUIF_DriverAPIC2UTest(mID, nID);
+ }
+ }
+}
+
+void CUIF_ClearPendingInterrupt()
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+void CUIF_InterruptTest()
+{
+ cuif_uint8 mID;
+ cuif_uint8 nID;
+
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ CUIF_DriverISRTestU2C(nID, 1, CUIF_ENUM_INNER);
+ }
+
+#if 0
+/* under construction !*/
+#else
+ for(mID = 0; mID < 1; mID++)
+#endif
+
+ {
+ CUIF_DriverISRTestC2U(mID, 1);
+ }
+
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ CUIF_DriverISRTestU2C(nID, 2, CUIF_ENUM_INNER);
+ }
+
+#if 0
+/* under construction !*/
+#else
+ for(mID = 0; mID < 1; mID++)
+#endif
+
+ {
+ CUIF_DriverISRTestC2U(mID, 2);
+ }
+}
+
+/* how to run cuif driver test ? */
+/* MD32 Side: insert CUIF_DriverTest to basic load function */
+/* CR4 Side: insert CUIF_DriverTest to idle task function */
+
+void CUIF_DriverTest()
+{
+#if __CUIF_MD32S_CORE__
+ extern void CUIF_DriverInitTest();
+ CUIF_DriverInitTest();
+#endif
+
+ CUIF_DisableInterrupt();
+ dbg_print("-- CUIF API Test Start.\n");
+ CUIF_DisableInterrupt();
+ CUIF_DriverAPITest();
+ dbg_print("-- CUIF API Test End.\n");
+
+ dbg_print("-- CUIF Interrupt Start.\n");
+ CUIF_EnableInterrupt();
+ CUIF_InterruptTest();
+ dbg_print("-- CUIF Interrupt End.\n");
+
+ while(1);
+
+}
+
+#endif /* __CUIF_DRV_TEST__ */
+
diff --git a/mcu/driver/devdrv/cuif/src/drv_cuif_l1core.c b/mcu/driver/devdrv/cuif/src/drv_cuif_l1core.c
new file mode 100644
index 0000000..554e499
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/src/drv_cuif_l1core.c
@@ -0,0 +1,1575 @@
+#include "drv_cuif.h"
+#include "kal_internal_api.h"
+
+//#if defined(__CUIF_DEBUG__)
+#include "us_timer.h"
+//#endif
+
+#if defined(__MTK_TARGET__)
+#include "kal_trace.h" // for logging
+static char cuif_fatal_error_trace_buf[128];
+#endif /* __MTK_TARGET__ */
+
+
+/*******************************************************************************
+ * Data Structure
+ *******************************************************************************/
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name) extern void fun_name(CUIF_Mask_t*);
+#define irq_auto_eoi(eoi)
+
+#include "cuif_u2c_isr_config_n0_pre.h"
+#include "cuif_u2c_isr_config_n1_pre.h"
+#include "cuif_u2c_isr_config_n2_pre.h"
+#include "cuif_u2c_isr_config_n3_pre.h"
+#include "cuif_u2c_isr_config_n4_pre.h"
+#if defined(__MD95__)
+#include "cuif_u2c_isr_config_n5_pre.h"
+#include "cuif_u2c_isr_config_n6_pre.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cuif_u2c_isr_config_n5_pre.h"
+#include "cuif_u2c_isr_config_n6_pre.h"
+#include "cuif_u2c_isr_config_n7_pre.h"
+#include "cuif_u2c_isr_config_n8_pre.h"
+#include "cuif_u2c_isr_config_n9_pre.h"
+#include "cuif_u2c_isr_config_n10_pre.h"
+#include "cuif_u2c_isr_config_n11_pre.h"
+#include "cuif_u2c_isr_config_n12_pre.h"
+#include "cuif_u2c_isr_config_n13_pre.h"
+#endif
+
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name) fun_name,
+#define irq_auto_eoi(eoi)
+
+CUIF_InterruptEntryFun cuif_isr_handler_n0[] = {
+ #include "cuif_u2c_isr_config_n0_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n1[] = {
+ #include "cuif_u2c_isr_config_n1_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n2[] = {
+ #include "cuif_u2c_isr_config_n2_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n3[] = {
+ #include "cuif_u2c_isr_config_n3_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n4[] = {
+ #include "cuif_u2c_isr_config_n4_pre.h"
+};
+
+#if defined(__MD95__)
+CUIF_InterruptEntryFun cuif_isr_handler_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+
+CUIF_InterruptEntryFun cuif_isr_handler_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+
+#elif defined(__MD97__) || defined(__MD97P__)
+CUIF_InterruptEntryFun cuif_isr_handler_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n7[] = {
+ #include "cuif_u2c_isr_config_n7_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n8[] = {
+ #include "cuif_u2c_isr_config_n8_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n9[] = {
+ #include "cuif_u2c_isr_config_n9_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n10[] = {
+ #include "cuif_u2c_isr_config_n10_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n11[] = {
+ #include "cuif_u2c_isr_config_n11_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n12[] = {
+ #include "cuif_u2c_isr_config_n12_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n13[] = {
+ #include "cuif_u2c_isr_config_n13_pre.h"
+};
+#endif
+
+CUIF_InterruptEntryFun* cuif_isr_handler[CUIF_ENUM_ALL_MCU_INT_NUM - 1] = {
+ cuif_isr_handler_n0,
+ cuif_isr_handler_n1,
+ cuif_isr_handler_n2,
+ cuif_isr_handler_n3,
+ cuif_isr_handler_n4,
+#if defined(__MD95__)
+ cuif_isr_handler_n5,
+ cuif_isr_handler_n6
+#elif defined(__MD97__) || defined(__MD97P__)
+ cuif_isr_handler_n5,
+ cuif_isr_handler_n6,
+ cuif_isr_handler_n7,
+ cuif_isr_handler_n8,
+ cuif_isr_handler_n9,
+ cuif_isr_handler_n10,
+ cuif_isr_handler_n11,
+ cuif_isr_handler_n12,
+ cuif_isr_handler_n13
+#endif
+};
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name)
+#define irq_auto_eoi(eoi) eoi,
+
+cuif_bool cuif_isr_eoi_n0[] = {
+ #include "cuif_u2c_isr_config_n0_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n1[] = {
+ #include "cuif_u2c_isr_config_n1_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n2[] = {
+ #include "cuif_u2c_isr_config_n2_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n3[] = {
+ #include "cuif_u2c_isr_config_n3_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n4[] = {
+ #include "cuif_u2c_isr_config_n4_pre.h"
+};
+
+#if defined(__MD95__)
+cuif_bool cuif_isr_eoi_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+#elif defined(__MD97__) || defined(__MD97P__)
+cuif_bool cuif_isr_eoi_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n7[] = {
+ #include "cuif_u2c_isr_config_n7_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n8[] = {
+ #include "cuif_u2c_isr_config_n8_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n9[] = {
+ #include "cuif_u2c_isr_config_n9_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n10[] = {
+ #include "cuif_u2c_isr_config_n10_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n11[] = {
+ #include "cuif_u2c_isr_config_n11_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n12[] = {
+ #include "cuif_u2c_isr_config_n12_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n13[] = {
+ #include "cuif_u2c_isr_config_n13_pre.h"
+};
+#endif
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+cuif_bool* cuif_isr_eoi[CUIF_ENUM_ALL_MCU_INT_NUM - 1] = {
+ cuif_isr_eoi_n0,
+ cuif_isr_eoi_n1,
+ cuif_isr_eoi_n2,
+ cuif_isr_eoi_n3,
+#if defined(__MD93__)
+ cuif_isr_eoi_n4
+#elif defined(__MD95__)
+ cuif_isr_eoi_n4,
+ cuif_isr_eoi_n5,
+ cuif_isr_eoi_n6
+#elif defined(__MD97__) || defined(__MD97P__)
+ cuif_isr_eoi_n4,
+ cuif_isr_eoi_n5,
+ cuif_isr_eoi_n6,
+ cuif_isr_eoi_n7,
+ cuif_isr_eoi_n8,
+ cuif_isr_eoi_n9,
+ cuif_isr_eoi_n10,
+ cuif_isr_eoi_n11,
+ cuif_isr_eoi_n12,
+ cuif_isr_eoi_n13
+#endif
+};
+
+/* backup U2C enable registers because sleep flow may power-down the mdcore (CCC) module */
+kal_uint32 CUIF_U2C_bk_en_reg[CUIF_ENUM_ALL_MCU_INT_NUM];
+
+
+/*******************************************************************************
+ * Debug
+ *******************************************************************************/
+#if defined(__CUIF_DEBUG__)
+
+CUIF_DebugISRCodeList cuif_debug_isr_handle[CUIF_ENUM_ALL_MCU_INT_NUM - 1];
+
+// for 4 VPE
+CUIF_DebugRecordList cuif_debug_records[CUIF_VPE_NUM];
+#endif
+
+CUIF_OverFlowRecord cuif_overflow_record[CUIF_VPE_NUM];
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+#if !defined(__CUIF_DEBUG__)
+extern void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi);
+#else /* __CUIF_DEBUG__ */
+extern void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi,
+ CUIF_MCU_INT nID);
+#endif /* __CUIF_DEBUG__ */
+
+void CUIF_InterruptHandler_N0();
+void CUIF_InterruptHandler_N1();
+void CUIF_InterruptHandler_N2();
+void CUIF_InterruptHandler_N3();
+void CUIF_InterruptHandler_N4();
+#if defined(__MD95__)
+void CUIF_InterruptHandler_N5();
+void CUIF_InterruptHandler_N6();
+#elif defined(__MD97__) || defined(__MD97P__)
+void CUIF_InterruptHandler_N5();
+void CUIF_InterruptHandler_N6();
+void CUIF_InterruptHandler_N7();
+void CUIF_InterruptHandler_N8();
+void CUIF_InterruptHandler_N9();
+void CUIF_InterruptHandler_N10();
+void CUIF_InterruptHandler_N11();
+void CUIF_InterruptHandler_N12();
+void CUIF_InterruptHandler_N13();
+#endif
+
+
+/*******************************************************************************
+ * Functions - CR4 Part
+ *******************************************************************************/
+
+
+/* U2C read status */
+void CUIF_U2C_STATUS(CUIF_MCU_INT nID, CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_U2C_STATUS_BASE + REG_OFFSET(nID));
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* U2C read WAKEUP status */
+void CUIF_U2C_WAKEUP_STATUS(CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_U2C_WAKEUP_STATUS_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP));
+}
+#endif
+
+/* U2C eoi */
+void CUIF_U2C_EOI(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ /* EOI2 */
+ CUIF_REG_WRITE(CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* U2C WAKEUP eoi */
+void CUIF_U2C_WAKEUP_EOI(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ /* EOI2 */
+ CUIF_REG_WRITE(CUIF_U2C_WAKEUP_CLEAR_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_WAKEUP_CLEAR_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+#endif
+
+/* C2U read status */
+void CUIF_U2C_ENABLE_STATUS(CUIF_MCU_INT nID, CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET(nID));
+}
+
+
+/* U2C enable*/
+void CUIF_U2C_ENABLE(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_EN_SET_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+
+}
+
+/* U2C disable*/
+void CUIF_U2C_DISABLE(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_EN_CLR_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+
+}
+
+
+/* C2U set*/
+void CUIF_C2U_SWI_SW(CUIF_MODULE_INDEX moduleID, cuif_uint32 code, cuif_uint32 limit)
+{
+ cuif_uint32 caller;
+ CUIF_Mask_t before;
+
+ CUIF_GET_RETURN_ADDRESS(caller);
+ before.mask31_0 = CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID));
+
+ // check the code in the range
+ CUIF_ASSERT(code < limit, moduleID, code, limit);
+
+ // avoid set the same interrupt again
+ if ((before.mask31_0 >> code) & 0x1)
+ {
+ cuif_uint32 vpe_id = kal_get_current_vpe_id();
+ CUIF_ASSERT(vpe_id < CUIF_VPE_NUM, vpe_id, CUIF_VPE_NUM, 0);
+
+ cuif_overflow_record[vpe_id].time = ust_get_current_time();
+ cuif_overflow_record[vpe_id].receiver = (cuif_uint32)moduleID;
+ cuif_overflow_record[vpe_id].interrupt_bit = code;
+ cuif_overflow_record[vpe_id].status_addr = (cuif_uint32)(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID));
+ cuif_overflow_record[vpe_id].current_status = before.mask31_0;
+ cuif_overflow_record[vpe_id].caller = caller;
+
+#if defined(__MTK_TARGET__) // print log
+ sprintf(cuif_fatal_error_trace_buf, "CUIF C2U %d interrupt bit overflow: overflow bit: %d, current status: 0x%x, caller 0x%x",
+ moduleID, code, CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID)), caller);
+ kal_sys_trace(cuif_fatal_error_trace_buf);
+#endif
+ kal_fatal_error_handler(KAL_ERROR_DSP_CUIF_INTERRUPT_TRIGGER_INVALID, caller);
+ //CUIF_ASSERT(((CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID)) >> code) & 0x1) == 0, moduleID, code, CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID)));
+ }
+
+ //dbg_print("SWI_SET on addr %x\n", CUIF_U2C_SET_BASE + REG_OFFSET(nID));
+ /* set interrupt */
+ CUIF_REG_WRITE(CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(before.mask31_0, CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+
+void CUIF_C2U_SWI_NO_CHECK(CUIF_MODULE_INDEX moduleID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, moduleID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ //dbg_print("SWI_SET on addr %x\n", CUIF_U2C_SET_BASE + REG_OFFSET(nID));
+ /* set interrupt */
+ CUIF_REG_WRITE(CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(moduleID, CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+
+void CUIF_C2U_STATUS(CUIF_MODULE_INDEX moduleID, CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID));
+}
+
+#if defined(__MD93__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFF0
+#define EN_ALL_WAKEUP_MASK 0xF
+#define EN_N1_ALL_MASK 0x11FFF // bit 13~16 reserved for ddr_en, 13: inner, 14: brp, 15:fec, 16:spch
+#elif defined(__MD95__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0
+#define EN_ALL_WAKEUP_MASK 0x3F
+#elif defined(__MD97__) || defined(__MD97P__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0
+#define EN_ALL_WAKEUP_MASK 0x3F
+#endif
+#define EN_ALL_MASK 0xFFFFFFFF
+
+
+/* default enable all interrupt */
+void CUIF_MCU_EN_ALL_INT()
+{
+#if defined(__MD93__) || defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+#if defined(__MD93__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_N1_ALL_MASK);
+#elif defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+#endif
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+#if defined(__MD93__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+#elif defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+#endif
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+#endif
+
+#if defined(__MD97__) || defined(__MD97P__)
+ DRV_WriteReg32(CUIF_U2C_WAKEUP_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), EN_ALL_WAKEUP_MASK);
+#else
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), EN_ALL_WAKEUP_MASK);
+#endif
+ MO_Sync();
+}
+
+void CUIF_register_backup()
+{
+ kal_uint32 idx;
+
+ #if defined(__MD97__) || defined(__MD97P__)
+ for (idx = 0; idx < CUIF_ENUM_ALL_MCU_INT_NUM-1; idx++)
+ {
+ CUIF_U2C_bk_en_reg[idx] = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET((idx)));
+ }
+ CUIF_U2C_bk_en_reg[CUIF_ENUM_WAKEUP_LEGACY_DUMMY] = CUIF_REG_READ(CUIF_U2C_WAKEUP_EN_BASE + REG_OFFSET((CUIF_ENUM_WAKEUP)));
+ #else
+ for (idx = 0; idx < CUIF_ENUM_ALL_MCU_INT_NUM; idx++)
+ {
+ CUIF_U2C_bk_en_reg[idx] = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET((idx)));
+ }
+ #endif
+
+ MO_Sync();
+}
+
+void CUIF_register_restore()
+{
+#if defined(__MD93__) || defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N0] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N1] & EN_ALL_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N2] & EN_ALL_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N3] & EN_ALL_MASK));
+
+#if defined(__MD93__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N4] & EN_ALL_EXCEPT_WFI_MASK));
+#elif defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N4] & EN_ALL_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N5] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N6] & EN_ALL_EXCEPT_WFI_MASK));
+#endif
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N0] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N1] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N2] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N3] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N4] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N5] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N6] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N7), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N7] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N8), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N8] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N9), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N9] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N10), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N10] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N11), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N11] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N12), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N12] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N13), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N13] & EN_ALL_EXCEPT_WFI_MASK));
+
+#endif
+
+ #if defined(__MD97__) || defined(__MD97P__)
+ DRV_WriteReg32(CUIF_U2C_WAKEUP_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), (CUIF_U2C_bk_en_reg[CUIF_ENUM_WAKEUP_LEGACY_DUMMY] & EN_ALL_WAKEUP_MASK));
+ #else
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), (CUIF_U2C_bk_en_reg[CUIF_ENUM_WAKEUP] & EN_ALL_WAKEUP_MASK));
+ #endif
+ MO_Sync();
+}
+
+void CUIF_Init()
+{
+ // register u2c n0 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N0, (void*)CUIF_InterruptHandler_N0, "CUIF_U2C_N0");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N0, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N0);
+
+ // register u2c n1 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N1, (void*)CUIF_InterruptHandler_N1, "CUIF_U2C_N1");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N1, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N1);
+
+ // register u2c n2 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N2, CUIF_InterruptHandler_N2, "CUIF_U2C_N2");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N2, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N2);
+
+ // register u2c n3 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N3 , CUIF_InterruptHandler_N3, "CUIF_U2C_N3");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N3 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N3 );
+
+
+ // register u2c n4 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N4, CUIF_InterruptHandler_N4, "CUIF_U2C_N4");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N4, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N4);
+
+#if defined(__MD95__)
+ // register u2c n5 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N5, CUIF_InterruptHandler_N5, "CUIF_U2C_N5");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N5, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N5);
+
+ // register u2c n6 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N6, CUIF_InterruptHandler_N6, "CUIF_U2C_N6");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N6, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N6);
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ // register u2c n5 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N5, CUIF_InterruptHandler_N5, "CUIF_U2C_N5");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N5, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N5);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N6, CUIF_InterruptHandler_N6, "CUIF_U2C_N6");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N6, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N6);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N7, CUIF_InterruptHandler_N7, "CUIF_U2C_N7");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N7, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N7);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N8, CUIF_InterruptHandler_N8, "CUIF_U2C_N8");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N8, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N8);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N9, CUIF_InterruptHandler_N9, "CUIF_U2C_N9");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N9, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N9);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N10, CUIF_InterruptHandler_N10, "CUIF_U2C_N10");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N10, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N10);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N11, CUIF_InterruptHandler_N11, "CUIF_U2C_N11");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N11, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N11);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N12, CUIF_InterruptHandler_N12, "CUIF_U2C_N12");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N12, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N12);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N13, CUIF_InterruptHandler_N13, "CUIF_U2C_N13");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N13, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N13);
+#endif
+ CUIF_MCU_EN_ALL_INT();
+
+}
+
+
+/**
+ * CUIF Interrupt handler: uSIP trigger MCU
+ *
+ **/
+void CUIF_InterruptHandler_N0()
+{
+ CUIF_HANDLER(CUIF_ENUM_N0);
+}
+
+void CUIF_InterruptHandler_N1()
+{
+ CUIF_HANDLER(CUIF_ENUM_N1);
+}
+
+void CUIF_InterruptHandler_N2()
+{
+ CUIF_HANDLER(CUIF_ENUM_N2);
+}
+
+void CUIF_InterruptHandler_N3()
+{
+ CUIF_HANDLER(CUIF_ENUM_N3);
+}
+
+void CUIF_InterruptHandler_N4()
+{
+ CUIF_HANDLER(CUIF_ENUM_N4);
+}
+
+#if defined(__MD95__)
+void CUIF_InterruptHandler_N5()
+{
+ CUIF_HANDLER(CUIF_ENUM_N5);
+}
+
+void CUIF_InterruptHandler_N6()
+{
+ CUIF_HANDLER(CUIF_ENUM_N6);
+}
+
+#elif defined(__MD97__) || defined(__MD97P__)
+void CUIF_InterruptHandler_N5()
+{
+ CUIF_HANDLER(CUIF_ENUM_N5);
+}
+
+void CUIF_InterruptHandler_N6()
+{
+ CUIF_HANDLER(CUIF_ENUM_N6);
+}
+
+void CUIF_InterruptHandler_N7()
+{
+ CUIF_HANDLER(CUIF_ENUM_N7);
+}
+
+void CUIF_InterruptHandler_N8()
+{
+ CUIF_HANDLER(CUIF_ENUM_N8);
+}
+
+void CUIF_InterruptHandler_N9()
+{
+ CUIF_HANDLER(CUIF_ENUM_N9);
+}
+
+void CUIF_InterruptHandler_N10()
+{
+ CUIF_HANDLER(CUIF_ENUM_N10);
+}
+
+void CUIF_InterruptHandler_N11()
+{
+ CUIF_HANDLER(CUIF_ENUM_N11);
+}
+
+void CUIF_InterruptHandler_N12()
+{
+ CUIF_HANDLER(CUIF_ENUM_N12);
+}
+
+void CUIF_InterruptHandler_N13()
+{
+ CUIF_HANDLER(CUIF_ENUM_N13);
+}
+#endif
+
+
+
+#if defined(__CUIF_DEBUG__)
+void cuif_DebugAddISRHandleCode(cuif_uint32 code, CUIF_MCU_INT nID)
+{
+ CUIF_DebugISRCodeList* code_list = CUIF_NULL;
+ cuif_uint32 save_index;
+
+ code_list = &cuif_debug_isr_handle[nID];
+
+ if(code_list != CUIF_NULL){
+ save_index = code_list -> top_index;
+
+ ++code_list -> top_index;
+ if(code_list -> top_index == CUIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ code_list -> top_index = 0;
+ }
+ code_list->records[save_index].time = ust_get_current_time();
+ code_list->records[save_index].code = code;
+ }
+}
+#endif
+
+
+/*******************************************************************************
+ * Functions - Driver test
+ *******************************************************************************/
+#if defined(__CUIF_DRV_TEST__)
+
+extern void cuif_drv_test_sync(CUIF_MODULE_INDEX moduleID);
+extern void CUIF_DisableInterrupt();
+extern void CUIF_EnableInterrupt();
+extern void CUIF_ClearPendingInterrupt();
+
+volatile cuif_uint32 cuif_drvtest_case = 0;
+volatile cuif_uint32 cuif_drvtest_prev_irq = 0;
+volatile cuif_uint32 cuif_drvtest_irq_test_success = 0;
+
+cuif_uint32 cuif_c2u_int_source_num[CUIF_ENUM_ALL_USIP_INT_NUM] =
+{
+ CUIF_NUM_INTERRUPT_INNER_SOURCES,
+ CUIF_NUM_INTERRUPT_OUTER_SOURCES,
+#if defined(__DSP_CODEBASE_MT6297__)
+ CUIF_NUM_INTERRUPT_SPEECH_SOURCES,
+ CUIF_NUM_INTERRUPT_FEC_SOURCES
+#else
+ CUIF_NUM_INTERRUPT_FEC_SOURCES,
+ CUIF_NUM_INTERRUPT_SPEECH_SOURCES
+#endif
+};
+
+cuif_uint32 cuif_u2c_int_source_num[CUIF_ENUM_ALL_MCU_INT_NUM - 1] =
+{
+ #if defined(__MD93__)
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES
+ #elif defined(__MD95__)
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES,
+ CUIF_MCU_INT_N5_SOURCES,
+ CUIF_MCU_INT_N6_SOURCES
+ #elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES,
+ CUIF_MCU_INT_N5_SOURCES,
+ CUIF_MCU_INT_N6_SOURCES,
+ CUIF_MCU_INT_N7_SOURCES,
+ CUIF_MCU_INT_N8_SOURCES,
+ CUIF_MCU_INT_N9_SOURCES,
+ CUIF_MCU_INT_N10_SOURCES,
+ CUIF_MCU_INT_N11_SOURCES,
+ CUIF_MCU_INT_N12_SOURCES,
+ CUIF_MCU_INT_N13_SOURCES
+ #endif
+};
+
+/* from usIP: moduleID(inner, outer, fec, speech) to MCU nID (N0~N4) */
+void CUIF_DriverAPIU2CTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID)
+{
+ CUIF_Mask_t mask;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Check the status and clear the status registers
+
+ CUIF_U2C_STATUS(nID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x7C0);
+
+ CUIF_U2C_EOI(nID, 6, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 7, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 8, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 9, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 10, cuif_u2c_int_source_num[nID]);
+// CUIF_U2C_EOI(nID, 11, cuif_u2c_int_source_num[nID]);
+
+ CUIF_U2C_STATUS(nID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ cuif_drv_test_sync(moduleID);
+
+ // 3. Wait for uSIP
+
+
+ cuif_drv_test_sync(moduleID);
+}
+
+void CUIF_DriverAPIC2UTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID)
+{
+ CUIF_Mask_t mask;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. set the interrupt bit and check status registers
+ CUIF_C2U_SWI_SW(moduleID, 6, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 7, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 8, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 9, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 10, cuif_c2u_int_source_num[moduleID]);
+// CUIF_C2U_SWI_SW(moduleID, 11, cuif_c2u_int_source_num[moduleID]);
+
+ CUIF_C2U_STATUS(moduleID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x7C0);
+
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ // 3. Check the status regsiters
+ CUIF_C2U_STATUS(moduleID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ cuif_drv_test_sync(moduleID);
+
+}
+
+void CUIF_DriverISRTestC2U(CUIF_MODULE_INDEX moduleID, cuif_uint32 case_num)
+{
+
+ cuif_drvtest_case = case_num;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Send interrupt to uSIP
+ if(cuif_drvtest_case == 1){
+ CUIF_C2U_SWI_SW(moduleID, 1, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 2, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 3, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 4, cuif_c2u_int_source_num[moduleID]);
+ }
+ else if(cuif_drvtest_case == 2){
+ CUIF_C2U_SWI_SW(moduleID, 5, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 6, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 7, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 8, cuif_c2u_int_source_num[moduleID]);
+ }
+
+ cuif_drv_test_sync(moduleID);
+
+ // 3. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+}
+
+void CUIF_DriverISRTestU2C(CUIF_MCU_INT nID, cuif_uint32 case_num, CUIF_MODULE_INDEX moduleID)
+{
+ cuif_drvtest_case = case_num;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. Disalbe interrupt and clean the pending interrupt
+ CUIF_DisableInterrupt();
+ CUIF_ClearPendingInterrupt();
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ if (1 == case_num)
+ {
+ cuif_drvtest_prev_irq = 5;
+ }
+
+ // 3. Enable the interrupt
+ CUIF_EnableInterrupt();
+ while(cuif_drvtest_irq_test_success != (cuif_drvtest_case << 4) + nID);
+ CUIF_DisableInterrupt();
+
+
+ cuif_drv_test_sync(moduleID);
+}
+
+
+void CUIF_DriverTestISR_N0(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N0;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N0_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N0_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N0_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N0;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N1(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N1;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N1_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N1_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N1_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N1;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N2(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N2;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N2_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N2_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N2_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N2;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N3(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N3;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N3_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N3_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N3_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N3;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N4(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N4;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N4_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N4_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N4_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N4;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N5(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N5;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N5_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N5_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N5_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N5;
+ }
+ }
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+void CUIF_DriverTestISR_N6(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N6;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N6_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N6_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N6_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N6;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N7(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N7;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N7_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N7_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N7_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N7;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N8(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N8;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N8_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N8_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N8_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N8;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N9(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N9;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N9_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N9_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N9_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N9;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N10(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N10;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N10_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N10_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N10_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N10;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N11(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N11;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N11_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N11_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N11_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N11;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N12(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N12;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N12_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N12_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N12_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N12;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N13(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N13;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N13_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N13_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N13_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N13;
+ }
+ }
+}
+
+
+#endif /* __MD97__ ||MD97P */
+
+#endif /* __CUIF_DRV_TEST__ */
diff --git a/mcu/driver/devdrv/cuif/usip_power_test/inc/usip_power_test.h b/mcu/driver/devdrv/cuif/usip_power_test/inc/usip_power_test.h
new file mode 100644
index 0000000..69efd88
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/usip_power_test/inc/usip_power_test.h
@@ -0,0 +1,30 @@
+#ifndef __USIP_POWER_TEST_H__
+#define __USIP_POWER_TEST_H__
+
+#include "dsp_header_define_cuif_inner_brp.h"
+#include "dsp_header_define_cuif_fec_wbrp.h"
+#include "dsp_header_define_cuif_speech.h"
+
+#define POWER_TEST_NUM (0xFFFF)
+#if defined(MT6763)
+// usip
+
+#define USIP_PWR_STA_ADDR (0xA00D00D4)
+#define USIP_PWR_STA_BIT (2)
+#define USIP_PWR_STA_MASK (0x00000004)
+#define USIP_POWER_STATUS ((((*(volatile ssdvt_uint32 *)USIP_PWR_STA_ADDR) & USIP_PWR_STA_MASK) >> USIP_PWR_STA_BIT))
+
+#define USIP_UNGATE_ADDR_U0 (0xA1630400)
+#define USIP_UNGATE_ADDR_U1 (0xA1630404)
+#define USIP_UNGATE_ADDR_U2 (0xA1630408)
+#define USIP_UNGATE_ADDR_U3 (0xA163040c)
+
+#define USIP_BOOT_DOWN_PAT (uSIPBOOTPATTERN2)
+
+#else
+#error "no configuration for this project!\n"
+#endif
+
+extern void SSDVT_USIP_POWER_TEST();
+
+#endif //__USIP_POWER_TEST_H__
diff --git a/mcu/driver/devdrv/cuif/usip_power_test/src/usip_power_test.c b/mcu/driver/devdrv/cuif/usip_power_test/src/usip_power_test.c
new file mode 100644
index 0000000..0c7b2e7
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/usip_power_test/src/usip_power_test.c
@@ -0,0 +1,153 @@
+#include "ssdvt_typedef.h"
+#include "ssdvt_header.h"
+#include "ssdvt_util.h"
+
+#include "usip_power_test.h"
+#include "RM_public.h"
+#include "drv_comm.h"
+/*******************************************************************************
+* Global variables
+*******************************************************************************/
+volatile ssdvt_uint32 usip_power_status;
+volatile ssdvt_uint32 usip0_th0_boot_pattern;
+volatile ssdvt_uint32 usip0_th1_boot_pattern;
+volatile ssdvt_uint32 usip1_th0_boot_pattern;
+volatile ssdvt_uint32 usip1_th1_boot_pattern;
+/*******************************************************************************
+* External Global variable
+*******************************************************************************/
+
+/*******************************************************************************
+* Function prototypes
+*******************************************************************************/
+void SSDVT_USIP_POWER_TEST_INIT(void);
+
+void SSDVT_CHECK_USIP_POWER_OFF(void);
+void SSDVT_CHECK_USIP_POWER_ON(void);
+
+void SSDVT_FORCE_USIP_POWER_OFF(void);
+void SSDVT_FORCE_USIP_POWER_ON(void);
+
+void SSDVT_UNGATE_USIP(void);
+
+void SSDVT_CHECK_USIP_BOOT_DONE(ssdvt_uint32 number);
+
+/*******************************************************************************
+* Functions
+*******************************************************************************/
+/*
+1. check usip power status is off in the beginning
+2. force on usip power domain, and un-gate the usip
+3. check usip power status is on
+4. delay, check usip boot down
+5. Turn off force-on usip power domain
+6. check usip power status is off
+7. force on usip power domain, and un-gate the usip
+8. check usip power status is on
+9. delay, check usip boot down (2)
+*/
+
+volatile ssdvt_uint32 ssdvt_usip_pwr_test_counter;
+
+void SSDVT_USIP_POWER_TEST()
+{
+
+
+ SSDVT_USIP_POWER_TEST_INIT();
+
+ for (ssdvt_usip_pwr_test_counter = 0; ssdvt_usip_pwr_test_counter < POWER_TEST_NUM; ssdvt_usip_pwr_test_counter++)
+ {
+ if (0 == ssdvt_usip_pwr_test_counter)
+ {
+ SSDVT_CHECK_USIP_POWER_OFF();
+ }
+ else
+ {
+ SSDVT_FORCE_USIP_POWER_OFF();
+ }
+
+ SSDVT_FORCE_USIP_POWER_ON();
+
+ if (0 == ssdvt_usip_pwr_test_counter)
+ {
+ SSDVT_UNGATE_USIP();
+ }
+
+ SSDVT_DELAY_LOOP(2000);
+
+ SSDVT_CHECK_USIP_BOOT_DONE(USIP_BOOT_DOWN_PAT | ssdvt_usip_pwr_test_counter);
+ }
+
+ ssdvt_test_pass_notification();
+
+ return;
+}
+
+void SSDVT_USIP_POWER_TEST_INIT()
+{
+ // let usip can power down
+ //DRV_WriteReg32(0xA0081108, DRV_Reg32(0xA0081108)|(0x2));
+ DRV_WriteReg32(0xA00D0300, 0x3);
+
+ // mask 2/3/4G timer of usip
+ DRV_WriteReg32(0xA6000160, 0xFFFFFFFF);
+}
+
+void SSDVT_CHECK_USIP_POWER_OFF()
+{
+ do {
+ usip_power_status = (volatile ssdvt_uint32)USIP_POWER_STATUS;
+ } while (1 == usip_power_status);
+
+ SSDVT_ASSERT_EQ(usip_power_status, 0);
+}
+
+void SSDVT_CHECK_USIP_POWER_ON()
+{
+ do {
+ usip_power_status = (volatile ssdvt_uint32)USIP_POWER_STATUS;
+ } while (0 == usip_power_status);
+
+ SSDVT_ASSERT_EQ(usip_power_status, 1);
+}
+
+void SSDVT_FORCE_USIP_POWER_OFF()
+{
+ MD_TOPSM_PWR_SW_Control(USIP0_PWR, KAL_FALSE);
+ SSDVT_DELAY_LOOP(2000);
+ SSDVT_CHECK_USIP_POWER_OFF();
+}
+
+void SSDVT_FORCE_USIP_POWER_ON()
+{
+ MD_TOPSM_PWR_SW_Control(USIP0_PWR, KAL_TRUE);
+ SSDVT_DELAY_LOOP(2000);
+ SSDVT_CHECK_USIP_POWER_ON();
+}
+
+void SSDVT_UNGATE_USIP()
+{
+ *(volatile ssdvt_uint32 *)USIP_UNGATE_ADDR_U0 = 0;
+ *(volatile ssdvt_uint32 *)USIP_UNGATE_ADDR_U1 = 0;
+ *(volatile ssdvt_uint32 *)USIP_UNGATE_ADDR_U2 = 0;
+ *(volatile ssdvt_uint32 *)USIP_UNGATE_ADDR_U3 = 0;
+}
+
+void SSDVT_CHECK_USIP_BOOT_DONE(ssdvt_uint32 check_pattern)
+{
+ do {
+ usip0_th0_boot_pattern = (volatile ssdvt_uint32)INNER_SS_BOOTINFO->BootUpReady;
+ usip0_th1_boot_pattern = (volatile ssdvt_uint32)BRP_SS_BOOTINFO->BootUpReady;
+ usip1_th0_boot_pattern = (volatile ssdvt_uint32)FEC_WBRP_SS_BOOTINFO->BootUpReady;
+ usip1_th1_boot_pattern = (volatile ssdvt_uint32)SPEECH_SS_BOOTINFO->BootUpReady;
+ } while(usip0_th0_boot_pattern != check_pattern || usip0_th1_boot_pattern != check_pattern
+ || usip1_th0_boot_pattern != check_pattern || usip1_th1_boot_pattern != check_pattern);
+
+ SSDVT_ASSERT_EQ(usip0_th0_boot_pattern, check_pattern);
+ SSDVT_ASSERT_EQ(usip0_th1_boot_pattern, check_pattern);
+ SSDVT_ASSERT_EQ(usip1_th0_boot_pattern, check_pattern);
+ SSDVT_ASSERT_EQ(usip1_th1_boot_pattern, check_pattern);
+}
+
+
+