[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/cuif/src/drv_cuif.c b/mcu/driver/devdrv/cuif/src/drv_cuif.c
new file mode 100644
index 0000000..fc02320
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/src/drv_cuif.c
@@ -0,0 +1,439 @@
+#include "drv_cuif.h"
+#include "kal_hrt_api.h"
+#if defined(__CUIF_DEBUG__)
+#include "us_timer.h"
+#endif
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+#if defined(__CUIF_DEBUG__)
+extern CUIF_DebugRecordList cuif_debug_records[CUIF_VPE_NUM];
+#endif
+
+
+#if !defined(__CUIF_DEBUG__)
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi);
+#else /* __CUIF_DEBUG__ */
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi,
+ CUIF_MCU_INT nID);
+#endif /* __CUIF_DEBUG__ */
+
+/*******************************************************************************
+ * Functions - Common Part
+ *******************************************************************************/
+void CUIF_DefaultISR(CUIF_Mask_t* mask)
+{
+ // code 1: status register value, code 2: enable register vale, code 3: n0~n4 (0~4)
+ CUIF_ASSERT(0, CUIF_REG_READ(mask->status_reg_addr),
+ CUIF_REG_READ((cuif_uint32)mask->status_reg_addr + CUIF_INTERRUPT_STA_EN_OFFSET),
+ ((cuif_uint32)mask->status_reg_addr - (cuif_uint32)CUIF_U2C_STATUS_BASE) / CUIF_INTERRUPT_NEXT_INT_OFFSET);
+}
+
+#if defined(__CUIF_DEBUG__)
+void cuif_DebugAddRecord(cuif_uint32 status,
+ volatile cuif_uint32* set_addr,
+ cuif_uint32 set_value,
+ cuif_uint32 caller)
+{
+ cuif_uint32 save_index = 0;
+ cuif_uint32 vpe_id = kal_get_current_vpe_id();
+ CUIF_ASSERT(vpe_id < CUIF_VPE_NUM, vpe_id, CUIF_VPE_NUM, 0);
+
+ CUIF_DebugRecordList *cuif_debug_records_ptr = &cuif_debug_records[vpe_id];
+
+ //cuif_uint32 mask;
+ //mask = kal_hrt_SaveAndSetIRQMask();
+
+ // fetch and add top_index atomically.
+ //save_index = cuif_debug_records_ptr->top_index;
+ save_index = kal_atomic_inc_circular_index(&(cuif_debug_records_ptr -> top_index), CUIF_DEBUG_ISR_HANDLE_CODE_SIZE);
+ //++(cuif_debug_records_ptr->top_index);
+ //if(cuif_debug_records_ptr->top_index == CUIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ // cuif_debug_records_ptr->top_index = 0;
+ //}
+
+ //kal_hrt_RestoreIRQMask(mask);
+
+ cuif_debug_records_ptr->records[save_index].time = ust_get_current_time();
+ cuif_debug_records_ptr->records[save_index].status = status;
+ cuif_debug_records_ptr->records[save_index].set_addr = (cuif_uint32)set_addr;
+ cuif_debug_records_ptr->records[save_index].set_value = set_value;
+ cuif_debug_records_ptr->records[save_index].caller = caller;
+}
+#endif /* __CUIF_DEBUG__ */
+
+
+/**
+ * General interrupt handler function
+ *
+ * @param[in] sreg CUIF interrupt status register
+ * @param[in] creg CUIF interrupt clean register
+ * @param[in] handler CUIF user entry function lists
+ * @param[in] core CUIF interrupt core type - BRP, DFE and RAKE (Debug only)
+ * @param[in] interrupt_type CUIF interrupt type - U3G or U4G (Debug only)
+ **/
+#if !defined(__CUIF_DEBUG__)
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi
+ )
+#else /* __CUIF_DEBUG__ */
+void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi,
+ CUIF_MCU_INT nID)
+#endif /* __CUIF_DEBUG__ */
+{
+ cuif_uint32 eidx; // entry function index
+ CUIF_Mask_t cuif_mask;
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ // for debug when no register callback
+ cuif_mask.status_reg_addr = (cuif_uint32*)sreg;
+
+ // read the sreg to the mask
+ cuif_mask.mask31_0 = CUIF_REG_READ(sreg) & CUIF_REG_READ(ereg);
+
+ while(cuif_mask.mask31_0){
+ // find the lsb
+ eidx = CUIF_GET_LSB(cuif_mask.mask31_0);
+
+ // invoke the user register interupt handler function
+ (*handler[eidx])((CUIF_Mask_t *)&cuif_mask);
+
+ // if the `irq_auto_eoi` is CUIF_TRUE, clean the interupt bit
+ if(auto_eoi[eidx] == CUIF_TRUE){
+
+ CUIF_REG_WRITE(creg, 1 << eidx);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(cuif_mask.mask31_0, creg, (1 << eidx), caller);
+#endif /* __CUIF_DEBUG__ */
+ }
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddISRHandleCode(eidx, nID);
+#endif /* __CUIF_DEBUG__ */
+
+ // read the sreg to the mask
+ cuif_mask.mask31_0 = CUIF_REG_READ(sreg) & CUIF_REG_READ(ereg);
+ }
+}
+
+
+/*******************************************************************************
+ * Functions - Driver test
+ *******************************************************************************/
+
+#if defined(__CUIF_DRV_TEST__)
+
+
+extern cuif_uint32 cuif_drvtest_case;
+extern cuif_uint32 cuif_drvtest_prev_irq;
+extern cuif_uint32 cuif_drvtest_irq_test_success;
+
+extern void CUIF_DriverAPIU2CTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID);
+extern void CUIF_DriverAPIC2UTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID);
+
+extern void CUIF_DriverISRTestC2U(CUIF_MODULE_INDEX moduleID, cuif_uint32 case_num);
+extern void CUIF_DriverISRTestU2C(CUIF_MCU_INT nID, cuif_uint32 case_num, CUIF_MODULE_INDEX moduleID);
+
+void cuif_drv_test_sync(CUIF_MODULE_INDEX moduleID)
+{
+ volatile cuif_uint32* sync;
+ if (CUIF_ENUM_INNER == moduleID || CUIF_ENUM_OUTER == moduleID)
+ {
+ sync = (volatile cuif_uint32*)CUIF_SYNC_ADDR_USIP0;
+ }
+ else
+ {
+ sync = (volatile cuif_uint32*)CUIF_SYNC_ADDR_USIP1;
+ }
+ // MCU Part
+ while(sync[1] == 1) ;
+ sync[1] = 1;
+
+ while(sync[0] == 0) ;
+ sync[0] = 0;
+}
+
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0
+#define EN_ALL_MASK 0xFFFFFFFF
+
+void CUIF_DisableInterrupt()
+{
+ #if defined(__MD93__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD95__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+ #endif
+}
+
+void CUIF_EnableInterrupt()
+{
+ #if defined(__MD93__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD95__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ #elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+ #endif
+}
+
+void CUIF_ENABLE_ALL_CHECK()
+{
+ cuif_uint8 nID;
+ cuif_uint32 set_mask;
+ cuif_uint32 get_mask;
+ cuif_uint8 irq_num;
+
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ #if defined(__MD93__)
+ if (nID == 0 || nID == 4)
+ { // skip WFI bits
+ irq_num = 4;
+ }
+ else
+ {
+ irq_num = 0;
+ }
+ #elif defined(__MD95__)
+ if (nID == 0 || nID == 5 || nID == 6)
+ { // skip WFI bits
+ irq_num = 6;
+ }
+ else
+ {
+ irq_num = 0;
+ }
+ #elif defined(__MD97__) || defined(__MD97P__)
+ irq_num = 6;
+ #endif
+
+ set_mask = 0;
+ for(; irq_num < cuif_u2c_int_source_num[nID]; irq_num++)
+ {
+ set_mask |= 1 << irq_num;
+ }
+ get_mask = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET(nID));
+ CUIF_DRV_TEST_ASSERT_EQ(get_mask, set_mask);
+ dbg_print("Enable n%d - Pass\n", nID);
+ }
+}
+
+void CUIF_DISABLE_ALL_CHECK()
+{
+ CUIF_Mask_t mask;
+
+ CUIF_N0_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N1_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N2_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N3_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N4_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ #if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ CUIF_N5_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N6_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+ #endif
+
+ #if defined(__MD97__) || defined(__MD97P__)
+ CUIF_N7_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N8_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N9_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N10_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N11_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N12_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ CUIF_N13_EN_STATUS(&mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+ #endif
+}
+
+void CUIF_EN_STA_API_TEST()
+{
+ CUIF_EnableInterrupt();
+ CUIF_ENABLE_ALL_CHECK();
+ CUIF_DisableInterrupt();
+ CUIF_DISABLE_ALL_CHECK();
+}
+
+void CUIF_DriverAPITest()
+{
+ cuif_uint8 mID;
+ cuif_uint8 nID;
+
+ CUIF_EN_STA_API_TEST();
+
+#if 0
+/* under construction !*/
+#else
+ for(mID = 0; mID < 1; mID++)
+#endif
+ {
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ CUIF_DriverAPIU2CTest(mID, nID);
+ CUIF_DriverAPIC2UTest(mID, nID);
+ }
+ }
+}
+
+void CUIF_ClearPendingInterrupt()
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+void CUIF_InterruptTest()
+{
+ cuif_uint8 mID;
+ cuif_uint8 nID;
+
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ CUIF_DriverISRTestU2C(nID, 1, CUIF_ENUM_INNER);
+ }
+
+#if 0
+/* under construction !*/
+#else
+ for(mID = 0; mID < 1; mID++)
+#endif
+
+ {
+ CUIF_DriverISRTestC2U(mID, 1);
+ }
+
+ for(nID = 0; nID < CUIF_ENUM_ALL_MCU_INT_NUM - 1; nID++)
+ {
+ CUIF_DriverISRTestU2C(nID, 2, CUIF_ENUM_INNER);
+ }
+
+#if 0
+/* under construction !*/
+#else
+ for(mID = 0; mID < 1; mID++)
+#endif
+
+ {
+ CUIF_DriverISRTestC2U(mID, 2);
+ }
+}
+
+/* how to run cuif driver test ? */
+/* MD32 Side: insert CUIF_DriverTest to basic load function */
+/* CR4 Side: insert CUIF_DriverTest to idle task function */
+
+void CUIF_DriverTest()
+{
+#if __CUIF_MD32S_CORE__
+ extern void CUIF_DriverInitTest();
+ CUIF_DriverInitTest();
+#endif
+
+ CUIF_DisableInterrupt();
+ dbg_print("-- CUIF API Test Start.\n");
+ CUIF_DisableInterrupt();
+ CUIF_DriverAPITest();
+ dbg_print("-- CUIF API Test End.\n");
+
+ dbg_print("-- CUIF Interrupt Start.\n");
+ CUIF_EnableInterrupt();
+ CUIF_InterruptTest();
+ dbg_print("-- CUIF Interrupt End.\n");
+
+ while(1);
+
+}
+
+#endif /* __CUIF_DRV_TEST__ */
+
diff --git a/mcu/driver/devdrv/cuif/src/drv_cuif_l1core.c b/mcu/driver/devdrv/cuif/src/drv_cuif_l1core.c
new file mode 100644
index 0000000..554e499
--- /dev/null
+++ b/mcu/driver/devdrv/cuif/src/drv_cuif_l1core.c
@@ -0,0 +1,1575 @@
+#include "drv_cuif.h"
+#include "kal_internal_api.h"
+
+//#if defined(__CUIF_DEBUG__)
+#include "us_timer.h"
+//#endif
+
+#if defined(__MTK_TARGET__)
+#include "kal_trace.h" // for logging
+static char cuif_fatal_error_trace_buf[128];
+#endif /* __MTK_TARGET__ */
+
+
+/*******************************************************************************
+ * Data Structure
+ *******************************************************************************/
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name) extern void fun_name(CUIF_Mask_t*);
+#define irq_auto_eoi(eoi)
+
+#include "cuif_u2c_isr_config_n0_pre.h"
+#include "cuif_u2c_isr_config_n1_pre.h"
+#include "cuif_u2c_isr_config_n2_pre.h"
+#include "cuif_u2c_isr_config_n3_pre.h"
+#include "cuif_u2c_isr_config_n4_pre.h"
+#if defined(__MD95__)
+#include "cuif_u2c_isr_config_n5_pre.h"
+#include "cuif_u2c_isr_config_n6_pre.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cuif_u2c_isr_config_n5_pre.h"
+#include "cuif_u2c_isr_config_n6_pre.h"
+#include "cuif_u2c_isr_config_n7_pre.h"
+#include "cuif_u2c_isr_config_n8_pre.h"
+#include "cuif_u2c_isr_config_n9_pre.h"
+#include "cuif_u2c_isr_config_n10_pre.h"
+#include "cuif_u2c_isr_config_n11_pre.h"
+#include "cuif_u2c_isr_config_n12_pre.h"
+#include "cuif_u2c_isr_config_n13_pre.h"
+#endif
+
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name) fun_name,
+#define irq_auto_eoi(eoi)
+
+CUIF_InterruptEntryFun cuif_isr_handler_n0[] = {
+ #include "cuif_u2c_isr_config_n0_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n1[] = {
+ #include "cuif_u2c_isr_config_n1_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n2[] = {
+ #include "cuif_u2c_isr_config_n2_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n3[] = {
+ #include "cuif_u2c_isr_config_n3_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n4[] = {
+ #include "cuif_u2c_isr_config_n4_pre.h"
+};
+
+#if defined(__MD95__)
+CUIF_InterruptEntryFun cuif_isr_handler_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+
+CUIF_InterruptEntryFun cuif_isr_handler_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+
+#elif defined(__MD97__) || defined(__MD97P__)
+CUIF_InterruptEntryFun cuif_isr_handler_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n7[] = {
+ #include "cuif_u2c_isr_config_n7_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n8[] = {
+ #include "cuif_u2c_isr_config_n8_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n9[] = {
+ #include "cuif_u2c_isr_config_n9_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n10[] = {
+ #include "cuif_u2c_isr_config_n10_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n11[] = {
+ #include "cuif_u2c_isr_config_n11_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n12[] = {
+ #include "cuif_u2c_isr_config_n12_pre.h"
+};
+
+CUIF_InterruptEntryFun cuif_isr_handler_n13[] = {
+ #include "cuif_u2c_isr_config_n13_pre.h"
+};
+#endif
+
+CUIF_InterruptEntryFun* cuif_isr_handler[CUIF_ENUM_ALL_MCU_INT_NUM - 1] = {
+ cuif_isr_handler_n0,
+ cuif_isr_handler_n1,
+ cuif_isr_handler_n2,
+ cuif_isr_handler_n3,
+ cuif_isr_handler_n4,
+#if defined(__MD95__)
+ cuif_isr_handler_n5,
+ cuif_isr_handler_n6
+#elif defined(__MD97__) || defined(__MD97P__)
+ cuif_isr_handler_n5,
+ cuif_isr_handler_n6,
+ cuif_isr_handler_n7,
+ cuif_isr_handler_n8,
+ cuif_isr_handler_n9,
+ cuif_isr_handler_n10,
+ cuif_isr_handler_n11,
+ cuif_isr_handler_n12,
+ cuif_isr_handler_n13
+#endif
+};
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+#define irq_index(code)
+#define irq_name(name)
+#define irq_entry_function(fun_name)
+#define irq_auto_eoi(eoi) eoi,
+
+cuif_bool cuif_isr_eoi_n0[] = {
+ #include "cuif_u2c_isr_config_n0_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n1[] = {
+ #include "cuif_u2c_isr_config_n1_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n2[] = {
+ #include "cuif_u2c_isr_config_n2_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n3[] = {
+ #include "cuif_u2c_isr_config_n3_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n4[] = {
+ #include "cuif_u2c_isr_config_n4_pre.h"
+};
+
+#if defined(__MD95__)
+cuif_bool cuif_isr_eoi_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+#elif defined(__MD97__) || defined(__MD97P__)
+cuif_bool cuif_isr_eoi_n5[] = {
+ #include "cuif_u2c_isr_config_n5_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n6[] = {
+ #include "cuif_u2c_isr_config_n6_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n7[] = {
+ #include "cuif_u2c_isr_config_n7_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n8[] = {
+ #include "cuif_u2c_isr_config_n8_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n9[] = {
+ #include "cuif_u2c_isr_config_n9_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n10[] = {
+ #include "cuif_u2c_isr_config_n10_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n11[] = {
+ #include "cuif_u2c_isr_config_n11_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n12[] = {
+ #include "cuif_u2c_isr_config_n12_pre.h"
+};
+
+cuif_bool cuif_isr_eoi_n13[] = {
+ #include "cuif_u2c_isr_config_n13_pre.h"
+};
+#endif
+
+#undef irq_index
+#undef irq_name
+#undef irq_entry_function
+#undef irq_auto_eoi
+
+cuif_bool* cuif_isr_eoi[CUIF_ENUM_ALL_MCU_INT_NUM - 1] = {
+ cuif_isr_eoi_n0,
+ cuif_isr_eoi_n1,
+ cuif_isr_eoi_n2,
+ cuif_isr_eoi_n3,
+#if defined(__MD93__)
+ cuif_isr_eoi_n4
+#elif defined(__MD95__)
+ cuif_isr_eoi_n4,
+ cuif_isr_eoi_n5,
+ cuif_isr_eoi_n6
+#elif defined(__MD97__) || defined(__MD97P__)
+ cuif_isr_eoi_n4,
+ cuif_isr_eoi_n5,
+ cuif_isr_eoi_n6,
+ cuif_isr_eoi_n7,
+ cuif_isr_eoi_n8,
+ cuif_isr_eoi_n9,
+ cuif_isr_eoi_n10,
+ cuif_isr_eoi_n11,
+ cuif_isr_eoi_n12,
+ cuif_isr_eoi_n13
+#endif
+};
+
+/* backup U2C enable registers because sleep flow may power-down the mdcore (CCC) module */
+kal_uint32 CUIF_U2C_bk_en_reg[CUIF_ENUM_ALL_MCU_INT_NUM];
+
+
+/*******************************************************************************
+ * Debug
+ *******************************************************************************/
+#if defined(__CUIF_DEBUG__)
+
+CUIF_DebugISRCodeList cuif_debug_isr_handle[CUIF_ENUM_ALL_MCU_INT_NUM - 1];
+
+// for 4 VPE
+CUIF_DebugRecordList cuif_debug_records[CUIF_VPE_NUM];
+#endif
+
+CUIF_OverFlowRecord cuif_overflow_record[CUIF_VPE_NUM];
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+#if !defined(__CUIF_DEBUG__)
+extern void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi);
+#else /* __CUIF_DEBUG__ */
+extern void cuif_InterruptHandlerInternal(volatile cuif_uint32* sreg,
+ volatile cuif_uint32* ereg,
+ volatile cuif_uint32* creg,
+ CUIF_InterruptEntryFun* handler,
+ cuif_bool* auto_eoi,
+ CUIF_MCU_INT nID);
+#endif /* __CUIF_DEBUG__ */
+
+void CUIF_InterruptHandler_N0();
+void CUIF_InterruptHandler_N1();
+void CUIF_InterruptHandler_N2();
+void CUIF_InterruptHandler_N3();
+void CUIF_InterruptHandler_N4();
+#if defined(__MD95__)
+void CUIF_InterruptHandler_N5();
+void CUIF_InterruptHandler_N6();
+#elif defined(__MD97__) || defined(__MD97P__)
+void CUIF_InterruptHandler_N5();
+void CUIF_InterruptHandler_N6();
+void CUIF_InterruptHandler_N7();
+void CUIF_InterruptHandler_N8();
+void CUIF_InterruptHandler_N9();
+void CUIF_InterruptHandler_N10();
+void CUIF_InterruptHandler_N11();
+void CUIF_InterruptHandler_N12();
+void CUIF_InterruptHandler_N13();
+#endif
+
+
+/*******************************************************************************
+ * Functions - CR4 Part
+ *******************************************************************************/
+
+
+/* U2C read status */
+void CUIF_U2C_STATUS(CUIF_MCU_INT nID, CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_U2C_STATUS_BASE + REG_OFFSET(nID));
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* U2C read WAKEUP status */
+void CUIF_U2C_WAKEUP_STATUS(CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_U2C_WAKEUP_STATUS_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP));
+}
+#endif
+
+/* U2C eoi */
+void CUIF_U2C_EOI(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ /* EOI2 */
+ CUIF_REG_WRITE(CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+/* U2C WAKEUP eoi */
+void CUIF_U2C_WAKEUP_EOI(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ /* EOI2 */
+ CUIF_REG_WRITE(CUIF_U2C_WAKEUP_CLEAR_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_WAKEUP_CLEAR_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+#endif
+
+/* C2U read status */
+void CUIF_U2C_ENABLE_STATUS(CUIF_MCU_INT nID, CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET(nID));
+}
+
+
+/* U2C enable*/
+void CUIF_U2C_ENABLE(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ CUIF_REG_WRITE(CUIF_U2C_EN_SET_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_EN_SET_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+
+}
+
+/* U2C disable*/
+void CUIF_U2C_DISABLE(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, nID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ CUIF_REG_WRITE(CUIF_U2C_EN_CLR_BASE + REG_OFFSET(nID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(nID, CUIF_U2C_EN_CLR_BASE + REG_OFFSET(nID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+
+}
+
+
+/* C2U set*/
+void CUIF_C2U_SWI_SW(CUIF_MODULE_INDEX moduleID, cuif_uint32 code, cuif_uint32 limit)
+{
+ cuif_uint32 caller;
+ CUIF_Mask_t before;
+
+ CUIF_GET_RETURN_ADDRESS(caller);
+ before.mask31_0 = CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID));
+
+ // check the code in the range
+ CUIF_ASSERT(code < limit, moduleID, code, limit);
+
+ // avoid set the same interrupt again
+ if ((before.mask31_0 >> code) & 0x1)
+ {
+ cuif_uint32 vpe_id = kal_get_current_vpe_id();
+ CUIF_ASSERT(vpe_id < CUIF_VPE_NUM, vpe_id, CUIF_VPE_NUM, 0);
+
+ cuif_overflow_record[vpe_id].time = ust_get_current_time();
+ cuif_overflow_record[vpe_id].receiver = (cuif_uint32)moduleID;
+ cuif_overflow_record[vpe_id].interrupt_bit = code;
+ cuif_overflow_record[vpe_id].status_addr = (cuif_uint32)(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID));
+ cuif_overflow_record[vpe_id].current_status = before.mask31_0;
+ cuif_overflow_record[vpe_id].caller = caller;
+
+#if defined(__MTK_TARGET__) // print log
+ sprintf(cuif_fatal_error_trace_buf, "CUIF C2U %d interrupt bit overflow: overflow bit: %d, current status: 0x%x, caller 0x%x",
+ moduleID, code, CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID)), caller);
+ kal_sys_trace(cuif_fatal_error_trace_buf);
+#endif
+ kal_fatal_error_handler(KAL_ERROR_DSP_CUIF_INTERRUPT_TRIGGER_INVALID, caller);
+ //CUIF_ASSERT(((CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID)) >> code) & 0x1) == 0, moduleID, code, CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID)));
+ }
+
+ //dbg_print("SWI_SET on addr %x\n", CUIF_U2C_SET_BASE + REG_OFFSET(nID));
+ /* set interrupt */
+ CUIF_REG_WRITE(CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(before.mask31_0, CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+
+void CUIF_C2U_SWI_NO_CHECK(CUIF_MODULE_INDEX moduleID, cuif_uint32 code, cuif_uint32 limit)
+{
+ // check the code in the range
+ CUIF_ASSERT(code < limit, moduleID, code, limit);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_uint32 caller;
+ CUIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CUIF_DEBUG__ */
+
+ //dbg_print("SWI_SET on addr %x\n", CUIF_U2C_SET_BASE + REG_OFFSET(nID));
+ /* set interrupt */
+ CUIF_REG_WRITE(CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), 1 << code);
+
+#if defined(__CUIF_DEBUG__)
+ cuif_DebugAddRecord(moduleID, CUIF_C2U_SET_BASE + REG_OFFSET(moduleID), (1 << code), caller);
+#endif /* __CUIF_DEBUG__ */
+}
+
+void CUIF_C2U_STATUS(CUIF_MODULE_INDEX moduleID, CUIF_Mask_t* m)
+{
+ m -> mask31_0 = CUIF_REG_READ(CUIF_C2U_STATUS_BASE + REG_OFFSET(moduleID));
+}
+
+#if defined(__MD93__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFF0
+#define EN_ALL_WAKEUP_MASK 0xF
+#define EN_N1_ALL_MASK 0x11FFF // bit 13~16 reserved for ddr_en, 13: inner, 14: brp, 15:fec, 16:spch
+#elif defined(__MD95__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0
+#define EN_ALL_WAKEUP_MASK 0x3F
+#elif defined(__MD97__) || defined(__MD97P__)
+#define EN_ALL_EXCEPT_WFI_MASK 0xFFFFFFC0
+#define EN_ALL_WAKEUP_MASK 0x3F
+#endif
+#define EN_ALL_MASK 0xFFFFFFFF
+
+
+/* default enable all interrupt */
+void CUIF_MCU_EN_ALL_INT()
+{
+#if defined(__MD93__) || defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+#if defined(__MD93__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_N1_ALL_MASK);
+#elif defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_MASK);
+#endif
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_MASK);
+#if defined(__MD93__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+#elif defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+#endif
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N7), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N8), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N9), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N10), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N11), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N12), EN_ALL_EXCEPT_WFI_MASK);
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N13), EN_ALL_EXCEPT_WFI_MASK);
+#endif
+
+#if defined(__MD97__) || defined(__MD97P__)
+ DRV_WriteReg32(CUIF_U2C_WAKEUP_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), EN_ALL_WAKEUP_MASK);
+#else
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), EN_ALL_WAKEUP_MASK);
+#endif
+ MO_Sync();
+}
+
+void CUIF_register_backup()
+{
+ kal_uint32 idx;
+
+ #if defined(__MD97__) || defined(__MD97P__)
+ for (idx = 0; idx < CUIF_ENUM_ALL_MCU_INT_NUM-1; idx++)
+ {
+ CUIF_U2C_bk_en_reg[idx] = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET((idx)));
+ }
+ CUIF_U2C_bk_en_reg[CUIF_ENUM_WAKEUP_LEGACY_DUMMY] = CUIF_REG_READ(CUIF_U2C_WAKEUP_EN_BASE + REG_OFFSET((CUIF_ENUM_WAKEUP)));
+ #else
+ for (idx = 0; idx < CUIF_ENUM_ALL_MCU_INT_NUM; idx++)
+ {
+ CUIF_U2C_bk_en_reg[idx] = CUIF_REG_READ(CUIF_U2C_EN_BASE + REG_OFFSET((idx)));
+ }
+ #endif
+
+ MO_Sync();
+}
+
+void CUIF_register_restore()
+{
+#if defined(__MD93__) || defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N0] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N1] & EN_ALL_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N2] & EN_ALL_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N3] & EN_ALL_MASK));
+
+#if defined(__MD93__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N4] & EN_ALL_EXCEPT_WFI_MASK));
+#elif defined(__MD95__)
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N4] & EN_ALL_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N5] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N6] & EN_ALL_EXCEPT_WFI_MASK));
+#endif
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N0), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N0] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N1), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N1] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N2), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N2] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N3), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N3] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N4), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N4] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N5), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N5] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N6), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N6] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N7), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N7] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N8), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N8] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N9), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N9] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N10), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N10] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N11), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N11] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N12), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N12] & EN_ALL_EXCEPT_WFI_MASK));
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_N13), (CUIF_U2C_bk_en_reg[CUIF_ENUM_N13] & EN_ALL_EXCEPT_WFI_MASK));
+
+#endif
+
+ #if defined(__MD97__) || defined(__MD97P__)
+ DRV_WriteReg32(CUIF_U2C_WAKEUP_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), (CUIF_U2C_bk_en_reg[CUIF_ENUM_WAKEUP_LEGACY_DUMMY] & EN_ALL_WAKEUP_MASK));
+ #else
+ DRV_WriteReg32(CUIF_U2C_EN_SET_BASE + REG_OFFSET(CUIF_ENUM_WAKEUP), (CUIF_U2C_bk_en_reg[CUIF_ENUM_WAKEUP] & EN_ALL_WAKEUP_MASK));
+ #endif
+ MO_Sync();
+}
+
+void CUIF_Init()
+{
+ // register u2c n0 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N0, (void*)CUIF_InterruptHandler_N0, "CUIF_U2C_N0");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N0, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N0);
+
+ // register u2c n1 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N1, (void*)CUIF_InterruptHandler_N1, "CUIF_U2C_N1");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N1, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N1);
+
+ // register u2c n2 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N2, CUIF_InterruptHandler_N2, "CUIF_U2C_N2");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N2, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N2);
+
+ // register u2c n3 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N3 , CUIF_InterruptHandler_N3, "CUIF_U2C_N3");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N3 , LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N3 );
+
+
+ // register u2c n4 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N4, CUIF_InterruptHandler_N4, "CUIF_U2C_N4");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N4, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N4);
+
+#if defined(__MD95__)
+ // register u2c n5 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N5, CUIF_InterruptHandler_N5, "CUIF_U2C_N5");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N5, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N5);
+
+ // register u2c n6 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N6, CUIF_InterruptHandler_N6, "CUIF_U2C_N6");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N6, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N6);
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ // register u2c n5 interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N5, CUIF_InterruptHandler_N5, "CUIF_U2C_N5");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N5, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N5);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N6, CUIF_InterruptHandler_N6, "CUIF_U2C_N6");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N6, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N6);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N7, CUIF_InterruptHandler_N7, "CUIF_U2C_N7");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N7, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N7);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N8, CUIF_InterruptHandler_N8, "CUIF_U2C_N8");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N8, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N8);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N9, CUIF_InterruptHandler_N9, "CUIF_U2C_N9");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N9, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N9);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N10, CUIF_InterruptHandler_N10, "CUIF_U2C_N10");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N10, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N10);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N11, CUIF_InterruptHandler_N11, "CUIF_U2C_N11");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N11, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N11);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N12, CUIF_InterruptHandler_N12, "CUIF_U2C_N12");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N12, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N12);
+
+ // register u2c n interrupt handler
+ //IRQ_Register_LISR(IRQID_CUIF_U2C_IRQ_N13, CUIF_InterruptHandler_N13, "CUIF_U2C_N13");
+ //IRQSensitivity(IRQID_CUIF_U2C_IRQ_N13, LEVEL_SENSITIVE);
+ IRQUnmask(IRQID_CUIF_U2C_IRQ_N13);
+#endif
+ CUIF_MCU_EN_ALL_INT();
+
+}
+
+
+/**
+ * CUIF Interrupt handler: uSIP trigger MCU
+ *
+ **/
+void CUIF_InterruptHandler_N0()
+{
+ CUIF_HANDLER(CUIF_ENUM_N0);
+}
+
+void CUIF_InterruptHandler_N1()
+{
+ CUIF_HANDLER(CUIF_ENUM_N1);
+}
+
+void CUIF_InterruptHandler_N2()
+{
+ CUIF_HANDLER(CUIF_ENUM_N2);
+}
+
+void CUIF_InterruptHandler_N3()
+{
+ CUIF_HANDLER(CUIF_ENUM_N3);
+}
+
+void CUIF_InterruptHandler_N4()
+{
+ CUIF_HANDLER(CUIF_ENUM_N4);
+}
+
+#if defined(__MD95__)
+void CUIF_InterruptHandler_N5()
+{
+ CUIF_HANDLER(CUIF_ENUM_N5);
+}
+
+void CUIF_InterruptHandler_N6()
+{
+ CUIF_HANDLER(CUIF_ENUM_N6);
+}
+
+#elif defined(__MD97__) || defined(__MD97P__)
+void CUIF_InterruptHandler_N5()
+{
+ CUIF_HANDLER(CUIF_ENUM_N5);
+}
+
+void CUIF_InterruptHandler_N6()
+{
+ CUIF_HANDLER(CUIF_ENUM_N6);
+}
+
+void CUIF_InterruptHandler_N7()
+{
+ CUIF_HANDLER(CUIF_ENUM_N7);
+}
+
+void CUIF_InterruptHandler_N8()
+{
+ CUIF_HANDLER(CUIF_ENUM_N8);
+}
+
+void CUIF_InterruptHandler_N9()
+{
+ CUIF_HANDLER(CUIF_ENUM_N9);
+}
+
+void CUIF_InterruptHandler_N10()
+{
+ CUIF_HANDLER(CUIF_ENUM_N10);
+}
+
+void CUIF_InterruptHandler_N11()
+{
+ CUIF_HANDLER(CUIF_ENUM_N11);
+}
+
+void CUIF_InterruptHandler_N12()
+{
+ CUIF_HANDLER(CUIF_ENUM_N12);
+}
+
+void CUIF_InterruptHandler_N13()
+{
+ CUIF_HANDLER(CUIF_ENUM_N13);
+}
+#endif
+
+
+
+#if defined(__CUIF_DEBUG__)
+void cuif_DebugAddISRHandleCode(cuif_uint32 code, CUIF_MCU_INT nID)
+{
+ CUIF_DebugISRCodeList* code_list = CUIF_NULL;
+ cuif_uint32 save_index;
+
+ code_list = &cuif_debug_isr_handle[nID];
+
+ if(code_list != CUIF_NULL){
+ save_index = code_list -> top_index;
+
+ ++code_list -> top_index;
+ if(code_list -> top_index == CUIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ code_list -> top_index = 0;
+ }
+ code_list->records[save_index].time = ust_get_current_time();
+ code_list->records[save_index].code = code;
+ }
+}
+#endif
+
+
+/*******************************************************************************
+ * Functions - Driver test
+ *******************************************************************************/
+#if defined(__CUIF_DRV_TEST__)
+
+extern void cuif_drv_test_sync(CUIF_MODULE_INDEX moduleID);
+extern void CUIF_DisableInterrupt();
+extern void CUIF_EnableInterrupt();
+extern void CUIF_ClearPendingInterrupt();
+
+volatile cuif_uint32 cuif_drvtest_case = 0;
+volatile cuif_uint32 cuif_drvtest_prev_irq = 0;
+volatile cuif_uint32 cuif_drvtest_irq_test_success = 0;
+
+cuif_uint32 cuif_c2u_int_source_num[CUIF_ENUM_ALL_USIP_INT_NUM] =
+{
+ CUIF_NUM_INTERRUPT_INNER_SOURCES,
+ CUIF_NUM_INTERRUPT_OUTER_SOURCES,
+#if defined(__DSP_CODEBASE_MT6297__)
+ CUIF_NUM_INTERRUPT_SPEECH_SOURCES,
+ CUIF_NUM_INTERRUPT_FEC_SOURCES
+#else
+ CUIF_NUM_INTERRUPT_FEC_SOURCES,
+ CUIF_NUM_INTERRUPT_SPEECH_SOURCES
+#endif
+};
+
+cuif_uint32 cuif_u2c_int_source_num[CUIF_ENUM_ALL_MCU_INT_NUM - 1] =
+{
+ #if defined(__MD93__)
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES
+ #elif defined(__MD95__)
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES,
+ CUIF_MCU_INT_N5_SOURCES,
+ CUIF_MCU_INT_N6_SOURCES
+ #elif defined(__MD97__) || defined(__MD97P__)
+ CUIF_MCU_INT_N0_SOURCES,
+ CUIF_MCU_INT_N1_SOURCES,
+ CUIF_MCU_INT_N2_SOURCES,
+ CUIF_MCU_INT_N3_SOURCES,
+ CUIF_MCU_INT_N4_SOURCES,
+ CUIF_MCU_INT_N5_SOURCES,
+ CUIF_MCU_INT_N6_SOURCES,
+ CUIF_MCU_INT_N7_SOURCES,
+ CUIF_MCU_INT_N8_SOURCES,
+ CUIF_MCU_INT_N9_SOURCES,
+ CUIF_MCU_INT_N10_SOURCES,
+ CUIF_MCU_INT_N11_SOURCES,
+ CUIF_MCU_INT_N12_SOURCES,
+ CUIF_MCU_INT_N13_SOURCES
+ #endif
+};
+
+/* from usIP: moduleID(inner, outer, fec, speech) to MCU nID (N0~N4) */
+void CUIF_DriverAPIU2CTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID)
+{
+ CUIF_Mask_t mask;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Check the status and clear the status registers
+
+ CUIF_U2C_STATUS(nID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x7C0);
+
+ CUIF_U2C_EOI(nID, 6, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 7, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 8, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 9, cuif_u2c_int_source_num[nID]);
+ CUIF_U2C_EOI(nID, 10, cuif_u2c_int_source_num[nID]);
+// CUIF_U2C_EOI(nID, 11, cuif_u2c_int_source_num[nID]);
+
+ CUIF_U2C_STATUS(nID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ cuif_drv_test_sync(moduleID);
+
+ // 3. Wait for uSIP
+
+
+ cuif_drv_test_sync(moduleID);
+}
+
+void CUIF_DriverAPIC2UTest(CUIF_MODULE_INDEX moduleID, CUIF_MCU_INT nID)
+{
+ CUIF_Mask_t mask;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. set the interrupt bit and check status registers
+ CUIF_C2U_SWI_SW(moduleID, 6, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 7, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 8, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 9, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 10, cuif_c2u_int_source_num[moduleID]);
+// CUIF_C2U_SWI_SW(moduleID, 11, cuif_c2u_int_source_num[moduleID]);
+
+ CUIF_C2U_STATUS(moduleID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x7C0);
+
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ // 3. Check the status regsiters
+ CUIF_C2U_STATUS(moduleID, &mask);
+ CUIF_DRV_TEST_ASSERT_EQ(mask.mask31_0, 0x0);
+
+ cuif_drv_test_sync(moduleID);
+
+}
+
+void CUIF_DriverISRTestC2U(CUIF_MODULE_INDEX moduleID, cuif_uint32 case_num)
+{
+
+ cuif_drvtest_case = case_num;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Send interrupt to uSIP
+ if(cuif_drvtest_case == 1){
+ CUIF_C2U_SWI_SW(moduleID, 1, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 2, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 3, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 4, cuif_c2u_int_source_num[moduleID]);
+ }
+ else if(cuif_drvtest_case == 2){
+ CUIF_C2U_SWI_SW(moduleID, 5, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 6, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 7, cuif_c2u_int_source_num[moduleID]);
+ CUIF_C2U_SWI_SW(moduleID, 8, cuif_c2u_int_source_num[moduleID]);
+ }
+
+ cuif_drv_test_sync(moduleID);
+
+ // 3. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+}
+
+void CUIF_DriverISRTestU2C(CUIF_MCU_INT nID, cuif_uint32 case_num, CUIF_MODULE_INDEX moduleID)
+{
+ cuif_drvtest_case = case_num;
+
+ cuif_drv_test_sync(moduleID);
+
+ // 1. Disalbe interrupt and clean the pending interrupt
+ CUIF_DisableInterrupt();
+ CUIF_ClearPendingInterrupt();
+
+ cuif_drv_test_sync(moduleID);
+
+ // 2. Wait for uSIP
+
+ cuif_drv_test_sync(moduleID);
+
+ if (1 == case_num)
+ {
+ cuif_drvtest_prev_irq = 5;
+ }
+
+ // 3. Enable the interrupt
+ CUIF_EnableInterrupt();
+ while(cuif_drvtest_irq_test_success != (cuif_drvtest_case << 4) + nID);
+ CUIF_DisableInterrupt();
+
+
+ cuif_drv_test_sync(moduleID);
+}
+
+
+void CUIF_DriverTestISR_N0(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N0;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N0_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N0_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N0_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N0;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N1(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N1;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N1_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N1_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N1_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N1;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N2(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N2;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N2_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N2_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N2_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N2;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N3(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N3;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N3_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N3_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N3_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N3;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N4(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N4;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N4_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N4_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N4_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N4;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N5(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N5;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N5_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N5_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N5_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N5;
+ }
+ }
+}
+
+#if defined(__MD97__) || defined(__MD97P__)
+void CUIF_DriverTestISR_N6(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N6;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N6_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N6_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N6_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N6;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N7(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N7;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N7_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N7_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N7_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N7;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N8(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N8;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N8_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N8_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N8_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N8;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N9(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N9;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N9_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N9_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N9_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N9;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N10(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N10;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N10_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N10_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N10_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N10;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N11(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N11;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N11_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N11_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N11_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N11;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N12(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N12;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N12_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N12_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N12_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N12;
+ }
+ }
+}
+
+void CUIF_DriverTestISR_N13(CUIF_Mask_t* mask)
+{
+ cuif_uint32 cuif_drvtest_curr_irq;
+ if(cuif_drvtest_case == 1){
+ // auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ CUIF_DRV_TEST_ASSERT_EQ(cuif_drvtest_curr_irq - cuif_drvtest_prev_irq, 1);
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 7){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N13;
+ }
+ }
+ else if(cuif_drvtest_case == 2){
+ // non-auto eoi mode
+ cuif_drvtest_curr_irq = CUIF_GET_LSB(mask->mask31_0);
+
+ switch (cuif_drvtest_prev_irq) {
+ case 0:
+ CUIF_N13_EOI(10);
+ break;
+ case 8:
+ if(cuif_drvtest_curr_irq == 8)
+ CUIF_N13_EOI(8);
+ else if(cuif_drvtest_curr_irq == 9)
+ CUIF_N13_EOI(9);
+ break;
+ default:
+ CUIF_DRV_TEST_ASSERT_EQ(1,2);
+ }
+
+ cuif_drvtest_prev_irq = cuif_drvtest_curr_irq;
+ if(cuif_drvtest_prev_irq == 9){
+ cuif_drvtest_prev_irq = 0;
+ cuif_drvtest_irq_test_success = (cuif_drvtest_case << 4) + CUIF_ENUM_N13;
+ }
+ }
+}
+
+
+#endif /* __MD97__ ||MD97P */
+
+#endif /* __CUIF_DRV_TEST__ */