[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/d2d/inc/d2d_dvt.h b/mcu/driver/devdrv/d2d/inc/d2d_dvt.h
new file mode 100644
index 0000000..c272303
--- /dev/null
+++ b/mcu/driver/devdrv/d2d/inc/d2d_dvt.h
@@ -0,0 +1,12 @@
+#define D2D_DSP_SEMAPHORESYS_BANK_A_BASE (BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE)
+#define D2D_DSP_SEMAPHORESYS_BANK_B_BASE (BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE)
+
+#define D2D_DSP_SEMAPHORESYS_IDLE_SET_CR_BANK_A_BASE (D2D_DSP_SEMAPHORESYS_BANK_A_BASE + 0x4)
+#define D2D_DSP_SEMAPHORESYS_IDLE_SET_CR_BANK_B_BASE (D2D_DSP_SEMAPHORESYS_BANK_A_BASE + 0x4)
+
+#define D2D_DSP_SEMAPHORESYS_IDLE_STS_CR_BANK_A_BASE (D2D_DSP_SEMAPHORESYS_BANK_B_BASE + 0xC)
+#define D2D_DSP_SEMAPHORESYS_IDLE_STS_CR_BANK_B_BASE (D2D_DSP_SEMAPHORESYS_BANK_B_BASE + 0xC)
+
+volatile kal_uint32 FAIL_MSG[3];
+#define SSDVT_FAIL_MSG(a, b, c) FAIL_MSG[0]=a;FAIL_MSG[1]=b;FAIL_MSG[2]=c;while(1)
+#define SSDVT_PASS() FAIL_MSG[0]=6297;FAIL_MSG[1]=6295;FAIL_MSG[2]=6293;while(1)
diff --git a/mcu/driver/devdrv/d2d/inc/drv_d2d.h b/mcu/driver/devdrv/d2d/inc/drv_d2d.h
new file mode 100644
index 0000000..db58fa3
--- /dev/null
+++ b/mcu/driver/devdrv/d2d/inc/drv_d2d.h
@@ -0,0 +1,80 @@
+#ifndef __DRV_D2D_H__
+#define __DRV_D2D_H__
+
+#include "sync_data.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+#include "d2d_public.h"
+
+/*******************************************************************************
+ * CSIF CR Definition
+ *******************************************************************************/
+
+#define D2D_MC1_BANK_A_BASE (BASE_MADDR_MCORE1_D2D)
+#define D2D_MC1_BANK_B_BASE (BASE_NADDR_MCORE1_D2D)
+
+#define D2D_DSR_BASE (CSIF_BANK_A_BASE)
+
+#define D2D_RWDATA_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x0)
+#define D2D_RWDATA_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x0)
+
+#define D2D_TADDR_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x10)
+#define D2D_TADDR_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x10)
+
+#define D2D_LENGTH_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x14)
+#define D2D_LENGTH_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x14)
+
+#define D2D_TUSER_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x18)
+#define D2D_TUSER_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x18)
+#define D2D_TUSER_TUSER_OFFSET (0x0)
+#define D2D_TUSER_TMODE_OFFSET (0x8)
+#define D2D_TUSER_TAUX_OFFSET (0x10)
+
+#define D2D_SIGCTRL_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x1C)
+#define D2D_SIGCTRL_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x1C)
+#define D2D_SIGCTRL_TADDRMOD_OFFSET (0x0)
+#define D2D_SIGCTRL_TRW_OFFSET (0x2)
+#define D2D_SIGCTRL_ALIGN_OFFSET (0x3)
+#define D2D_SIGCTRL_TSIZE_OFFSET (0x4)
+#define D2D_SIGCTRL_TRIGMOD_OFFSET (0x8)
+
+#define D2D_TRIGCTRL_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x20)
+#define D2D_TRIGCTRL_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x20)
+
+#define D2D_DBGCTRL_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x24)
+#define D2D_DBGCTRL_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x24)
+#define D2D_DBGCTRL_IDLE_OFFSET (0x0)
+#define D2D_DBGCTRL_ERR_TX_EN_OFFSET (0x1)
+#define D2D_DBGCTRL_ABORT_OFFSET (0x2)
+#define D2D_DBGCTRL_FORCE_ABORT_OFFSET (0x3)
+#define D2D_DBGCTRL_USE_DBG_TID_OFFSET (0x4)
+#define D2D_DBGCTRL_REPLACE_MOD_OFFSET (0x6)
+#define D2D_DBGCTRL_DBG_PATH_EN_OFFSET (0x7)
+
+
+
+// TADDRMOD =0, Fixed-address
+// TRW =1, write
+// ALIGN =1
+// TSIZE =2, 4 byte
+// TRIGRMODE =1, triggered based
+#define D2D_SIGCTRL_WRITE32_CMD (0x12C)
+// TADDRMOD =0, Fixed-address
+// TRW =0, read
+// ALIGN =1
+// TSIZE =2, 4 byte
+// TRIGRMODE =1, triggered based
+#define D2D_SIGCTRL_READ32_CMD (0x128)
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+
+/* Read/Write macros */
+#define D2D_REG(addr) DRV_Reg32(addr)
+#define D2D_REG_WRITE(addr, data) DRV_WriteReg32(addr, data);
+
+/* Sync macros */
+#define D2D_MO_SYNC() MO_Sync();
+
+#endif /* __DRV_D2D_H__ */
diff --git a/mcu/driver/devdrv/d2d/src/d2d_dvt_main.c b/mcu/driver/devdrv/d2d/src/d2d_dvt_main.c
new file mode 100644
index 0000000..da614df
--- /dev/null
+++ b/mcu/driver/devdrv/d2d/src/d2d_dvt_main.c
@@ -0,0 +1,22 @@
+#include "drv_d2d.h"
+#include "d2d_dvt.h"
+
+void d2d_rw_test(void)
+{
+ kal_uint32 idle_set=0;
+ kal_uint32 idle_sts=1;
+
+ for(kal_uint32 i=0; i < 32; i++)
+ {
+ idle_set |= 1 << i;
+ d2d_wreg32(D2D_DSP_SEMAPHORESYS_IDLE_SET_CR_BANK_A_BASE, idle_set);
+ d2d_rwconfigure(D2D_READ_INIT_CMD);
+ idle_sts = d2d_rreg32(D2D_DSP_SEMAPHORESYS_IDLE_STS_CR_BANK_A_BASE);
+ if(idle_sts != idle_set)
+ {
+ SSDVT_FAIL_MSG(i, idle_set, idle_sts);
+ }
+ d2d_rwconfigure(D2D_WRITE_INIT_CMD);
+ }
+ SSDVT_PASS();
+}
diff --git a/mcu/driver/devdrv/d2d/src/drv_d2d_init.c b/mcu/driver/devdrv/d2d/src/drv_d2d_init.c
new file mode 100644
index 0000000..0b4a0fb
--- /dev/null
+++ b/mcu/driver/devdrv/d2d/src/drv_d2d_init.c
@@ -0,0 +1,40 @@
+#include "drv_d2d.h"
+
+/*
+****************************************************************************************************************************
+* D2D_Init.
+*
+* This function is for initiate the D2D HW to write mode
+*
+* Input: None
+*
+* Output: None
+*
+****************************************************************************************************************************
+*/
+
+void d2d_init(void)
+{
+ // mcu d2d for csif only, only write cmd
+ D2D_REG_WRITE(D2D_SIGCTRL_CR_BANK_B_BASE, D2D_SIGCTRL_WRITE32_CMD);
+}
+
+/*
+****************************************************************************************************************************
+* D2D_RWConfigure.
+*
+* This function is for Configure the D2D HW to read/write mode
+*
+* Input: D2D_READ_INIT_CMD for read mode
+* D2D_WRITE_INIT_CMD for write mode
+*
+* Output: None
+*
+****************************************************************************************************************************
+*/
+
+void d2d_rwconfigure(D2D_RW_INIT_ENUM_T rw_config)
+{
+ // mcu d2d for csif only, only write cmd
+ D2D_REG_WRITE(D2D_SIGCTRL_CR_BANK_B_BASE, rw_config);
+}
diff --git a/mcu/driver/devdrv/d2d/src/drv_d2d_main.c b/mcu/driver/devdrv/d2d/src/drv_d2d_main.c
new file mode 100644
index 0000000..e80b3bc
--- /dev/null
+++ b/mcu/driver/devdrv/d2d/src/drv_d2d_main.c
@@ -0,0 +1,57 @@
+#include "drv_d2d.h"
+#include "us_timer.h"
+#include "SST_intrCtrl.h"
+#include "kal_public_api.h"
+/*
+****************************************************************************************************************************
+* d2d_wreg32
+*
+* This function is for writing data through MCORE1 TH0 taux
+*
+* Input: kal_uint32 addr, address to write
+* kal_uint32 data, data to write
+*
+* Output: None
+*
+****************************************************************************************************************************
+*/
+INLINE INLINE_ALWAYS void d2d_wreg32(kal_uint32 addr, kal_uint32 data)
+{
+ kal_uint32 time1, time2;
+ time1 = ust_get_current_time();
+ // other paras are ready, only need config addr/data then trigger
+ // bankB for performance
+ D2D_REG_WRITE(D2D_TADDR_CR_BANK_B_BASE, addr);
+ D2D_REG_WRITE(D2D_RWDATA_CR_BANK_B_BASE, data);
+ D2D_REG_WRITE(D2D_TRIGCTRL_CR_BANK_A_BASE, 0x1);
+ // check idle address is different from above, need sync to keep ordering
+ D2D_MO_SYNC();
+ while(!(D2D_REG(D2D_DBGCTRL_CR_BANK_A_BASE) & 0x1)) {
+ time2 = ust_get_current_time();
+ ASSERT(ust_us_duration(time1,time2) < IRQ_DISABLE_MAX_DURATION_HRT);
+ }
+}
+
+/*
+****************************************************************************************************************************
+* d2d_rreg32
+*
+* This function is for reading data through MCORE1 TH0 taux
+*
+* Input: kal_uint32 addr, address to read
+*
+* Output: kal_uint32 data, data read from given address
+*
+****************************************************************************************************************************
+*/
+INLINE INLINE_ALWAYS kal_uint32 d2d_rreg32(kal_uint32 addr)
+{
+ // other paras are ready, only need config addr then trigger
+ // bankB for performance
+ D2D_REG_WRITE(D2D_TADDR_CR_BANK_B_BASE, addr);
+ D2D_REG_WRITE(D2D_TRIGCTRL_CR_BANK_A_BASE, 0x1);
+ // check idle address is different from above, need sync to keep ordering
+ D2D_MO_SYNC();
+ while(!(D2D_REG(D2D_DBGCTRL_CR_BANK_A_BASE) & 0x1));
+ return D2D_REG(D2D_RWDATA_CR_BANK_B_BASE);
+}