[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/elm/inc/elm.h b/mcu/driver/devdrv/elm/inc/elm.h
new file mode 100644
index 0000000..ea935c2
--- /dev/null
+++ b/mcu/driver/devdrv/elm/inc/elm.h
@@ -0,0 +1,526 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * elm.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Header file for ELM.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if !defined(__ELM_H__)
+#define __ELM_H__
+/* ==================== */
+/* CONFIGURATIONS */
+/* ==================== */
+/* ==================== */
+/* INCLUDES */
+/* ==================== */
+#include "reg_base.h"
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "sync_data.h"
+#include "boot.h"
+
+#include "drv_comm.h"
+/*******************************************************************************
+ * Feature Option
+ *******************************************************************************/
+#define ELM_AMIF_ENABLE
+#define ELM_GCR
+#define __ELM_RUNTIME_PROFILE__
+
+
+/* ==================== */
+/* DEFINITIONS */
+/* ==================== */
+#if defined(__MD95__)
+ #define __ELM_MD95__
+ #define ELM_IF_DEF_MD95(def_statement, undef_statement) def_statement
+#elif defined(__MD97__)
+ #define __ELM_MD97__
+#elif defined(__MD97P__)
+ #define __ELM_MD97P__
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_MD95(def_statement, undef_statement) undef_statement
+#endif
+
+#if defined(__ELM_MD95__) || defined(__ELM_MD97__) || defined(__ELM_MD97P__)
+
+#ifdef ELM_GCR
+#define REG_ELM_STAT (GCR_CUSTOM_ADDR + 0x00A0) //0xA0~0xAC, MDMCU, CNT0~CNT3
+#define REG_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x00B0) //0xB0~0xB4, MDMCU, CNT4~CNT5, only valid in mode0, representing word count
+
+#if defined(MT6297)
+#define REG_INFRA_B_ELM_STAT (GCR_CUSTOM_ADDR + 0x0490) //APOLLO MDINFRA_ELM_B
+#define REG_INFRA_B_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x04a0) //APOLLO MDINFRA_ELM_B
+
+#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x060) //APOLLO MDINFRA_ELM_A
+#define REG_INFRA_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x0B8) //APOLLO MDINFRA_ELM_A
+#else
+#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x0060) //0x60~0x6C, MDINFRA, CNT0~CNT3
+#define REG_INFRA_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x00B8) //0xB8~0xBC, MDINFRA, CNT4~CNT5, only valid in mode0, representing word count
+#endif
+
+#else
+#define REG_ELM_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+#define REG_ELM_WC_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x00E0)
+#define REG_INFRA_ELM_STAT (BASE_ADDR_MDINFRA_ELM + 0x0050)
+#define REG_INFRA_ELM_WC_STAT (BASE_ADDR_MDINFRA_ELM + 0x00E0)
+#endif //ifdef ELM_GCR
+#define REG_ELM_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+#define REG_ELM_WC_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x00E0)
+
+#define ELM_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_ELM_WC_STAT + (rw << 2));\
+ } while(0)
+
+#define ELM_INFRA_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_ELM_WC_STAT + (rw << 2));\
+ } while(0)
+
+#if defined(MT6297)
+#define ELM_INFRA_B_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_B_ELM_WC_STAT + (rw << 2));\
+ } while(0)
+#endif
+
+#else //!__ELM_MD95__
+
+#ifdef ELM_GCR
+#define REG_ELM_STAT (GCR_CUSTOM_ADDR + 0x00B0)
+#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x0060)
+#else
+#define REG_ELM_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+#define REG_INFRA_ELM_STAT (BASE_ADDR_MDINFRA_ELM + 0x0050)
+#endif //ifdef ELM_GCR
+#define REG_ELM_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+
+#define ELM_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ } while(0)
+
+#define ELM_INFRA_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ } while(0)
+
+#endif //ifdef __ELM_MD95__
+
+/* ==================== */
+/* ELM CONTROL API */
+/* ==================== */
+
+// ELM init
+extern void ELM_INIT(void);
+extern void ELM_Config_DormantEnter(void);
+extern void ELM_Config_DormantLeave(void);
+extern kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type);
+extern kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+// ELM clear
+#define ELM_CLR() \
+ do {\
+ } while(0)
+
+// ELM Start
+#define ELM_START() \
+ do {\
+ } while(0)
+
+// ELM Pause
+#define ELM_PAUSE() \
+ do {\
+ } while(0)
+
+// ELM Counter Selection
+enum {
+ ELM_RD = 0,
+ ELM_WR = 1
+};
+
+enum {
+ ELM_TYPE_TRANS = 0,
+ ELM_TYPE_LATENCY = 1
+};
+
+
+#define ELM_GET_CNT(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+
+
+#define ELM_INFRA_GET_CNT(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+
+#if defined(MT6297)
+#define ELM_INFRA_B_GET_CNT(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_B_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+#endif
+
+
+#define ELM_GET_CNT_APB(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_ELM_STAT_APB+ (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+
+
+typedef struct _ELM_LOG_T
+{
+ kal_uint32 w_trans;
+ kal_uint32 w_latency;
+ kal_uint32 r_trans;
+ kal_uint32 r_latency;
+} ELM_LOG_T;
+
+typedef struct _ELM_FULL_LOG_T
+{
+ kal_uint32 fma_stamp;
+ kal_uint32 w_trans;
+ kal_uint32 w_latency;
+ kal_uint32 w_wordcount;
+ kal_uint32 r_trans;
+ kal_uint32 r_latency;
+ kal_uint32 r_wordcount;
+ kal_uint32 r_lat_thr;// read latency criteria
+ kal_uint32 w_lat_thr;// write latency criteria
+} ELM_FULL_LOG_T;
+
+typedef struct _ELM_M4PORT_FULL_LOG_T
+{
+ kal_uint32 infra_w_trans;
+ kal_uint32 infra_w_latency;
+ kal_uint32 infra_w_wordcount;
+ kal_uint32 infra_r_trans;
+ kal_uint32 infra_r_latency;
+ kal_uint32 infra_r_wordcount;
+} ELM_M4PORT_FULL_LOG_T;
+
+
+// for spv compatibility
+#define ELM_GET_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).w_trans));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).w_latency));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).r_trans));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).r_latency));\
+ } while (0)
+
+#define ELM_GET_ALL_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).w_trans));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).w_latency));\
+ ELM_GET_WC_CNT(ELM_WR, (c), &((l).w_wordcount));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).r_trans));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).r_latency));\
+ ELM_GET_WC_CNT(ELM_RD, (c), &((l).r_wordcount));\
+ } while (0)
+
+#define ELM_GET_M4PORT_ALL_LOG(c, l) do { \
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).infra_w_trans));\
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).infra_w_latency));\
+ ELM_INFRA_GET_WC_CNT(ELM_WR, (c), &((l).infra_w_wordcount));\
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).infra_r_trans));\
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).infra_r_latency));\
+ ELM_INFRA_GET_WC_CNT(ELM_RD, (c), &((l).infra_r_wordcount));\
+ } while (0)
+
+#if defined(MT6297)
+#define ELM_GET_MDINFRA_B_ALL_LOG(c, l) do { \
+ ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).infra_w_trans));\
+ ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).infra_w_latency));\
+ ELM_INFRA_B_GET_WC_CNT(ELM_WR, (c), &((l).infra_w_wordcount));\
+ ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).infra_r_trans));\
+ ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).infra_r_latency));\
+ ELM_INFRA_B_GET_WC_CNT(ELM_RD, (c), &((l).infra_r_wordcount));\
+ } while (0)
+#endif
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data);
+
+// for profiling ELM log
+typedef enum
+{
+ //When ELM irq happend
+ ELM_NONE = 0, //show trace only
+ ELM_ASSERT, //trigger assert
+ ELM_ASSERT_AT_2nd, //show trace first, twice in 500us then assert
+} elm_exception_type;
+
+typedef struct _ELM_RUNTIME_PROFILE_LAT_T
+{
+ kal_uint32 cur_frc;
+ kal_uint32 int_status;
+ kal_uint32 r_trans;
+ kal_uint32 w_trans;
+ kal_uint32 r_alat;
+ kal_uint32 r_alat_maxost;
+ kal_uint32 w_alat;
+ kal_uint32 w_alat_maxost;
+ kal_uint32 r_l2_tot_lat;
+ kal_uint32 w_l2_tot_lat;
+ kal_uint32 ap_dvfs_tick;
+ kal_uint32 txzq_dvfs_tick;
+ kal_uint32 md_tick;
+#if defined(__MD97__) || defined(__MD97P__)
+ kal_uint32 enter_lisr_frc;
+ kal_uint32 ap_ddren_tick ;
+ kal_uint32 id0_subwindow_status;
+ kal_uint32 id1_subwindow_status;
+ kal_uint32 emi_blocking;
+#endif
+} ELM_RUNTIME_PROFILE_LAT_T;
+
+typedef struct _ELM_RUNTIME_PROFILE_WC_T
+{
+ kal_uint32 cur_frc;
+ kal_uint32 int_status;
+ kal_uint32 r_wc;
+ kal_uint32 w_wc;
+} ELM_RUNTIME_PROFILE_WC_T;
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us);
+void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us);
+
+#if defined(__MD97__) || defined(__MD97P__)
+typedef struct _ELM_MAX_LOG_T
+{
+ kal_uint32 m3_max_r_word_cnt ;
+ kal_uint32 m3_max_w_word_cnt ;
+ kal_uint32 m4_max_r_word_cnt ;
+ kal_uint32 m4_max_w_word_cnt ;
+#if defined(MT6297)
+ kal_uint32 m4b_max_r_word_cnt ;
+ kal_uint32 m4b_max_w_word_cnt ;
+#endif
+} ELM_MAX_LOG_T;
+
+void EMI_ELM_GET_MAX_LOG(ELM_MAX_LOG_T * tt);
+void EMI_ELM_AMIF_SCENARIO_CHANGE_LOGGING(ELM_MAX_LOG_T t);
+
+#endif
+
+#endif /* !__ELM_H__ */
diff --git a/mcu/driver/devdrv/elm/src/md93/elm.c b/mcu/driver/devdrv/elm/src/md93/elm.c
new file mode 100644
index 0000000..0427c40
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md93/elm.c
@@ -0,0 +1,1388 @@
+#include "elm.h"
+#include "drv_comm.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "drv_mdap_interface.h" //for show MD_DVFS_CON in trace
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+// for profiling ELM log
+#include "kal_trace.h" //for kal_sys_trace
+#include "TrcMod.h" //for L1 Trace API
+#endif
+
+
+#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
+#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
+#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
+#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
+#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
+#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
+#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
+#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
+#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
+#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
+#define REG_MDMCU_ELM_AO_STATUS0_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
+#define REG_MDMCU_ELM_AO_STATUS0_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
+
+
+#define REG_MDINFRA_EMI_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
+#define REG_MDINFRA_EMI_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_EMI_ELM_ID0_WORST_AVG_LAT (BASE_ADDR_MDINFRA_ELM+0x70)
+#define REG_MDINFRA_EMI_ELM_ID0_WORST_TOT_LAT (BASE_ADDR_MDINFRA_ELM+0x74)
+#define REG_MDINFRA_EMI_ELM_ID1_WORST_AVG_LAT (BASE_ADDR_MDINFRA_ELM+0x78)
+#define REG_MDINFRA_EMI_ELM_ID1_WORST_TOT_LAT (BASE_ADDR_MDINFRA_ELM+0x7C)
+#define REG_MDINFRA_EMI_ELM_ID0_TRANS_IN_WORST_AVG (BASE_ADDR_MDINFRA_ELM+0x80)
+#define REG_MDINFRA_EMI_ELM_ID1_TRANS_IN_WORST_AVG (BASE_ADDR_MDINFRA_ELM+0x84)
+
+#define REG_MDINFRA_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
+#define REG_MDINFRA_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
+#define REG_MDINFRA_EMI_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_AO_STATUS0_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
+#define REG_MDINFRA_ELM_AO_STATUS0_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
+#if defined(MT6771)
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xDC) // current dvfsrc level
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x308) // last dvfsrc level
+#define AP_VCORE_DVFS_HISTORY_BASE (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x400) // dvfsrc history start address, end address should be 0x15C
+#define AP_VCORE_DVFS_HISTORY_SIZE 24
+#else
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x50) // current dvfsrc level
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x88) // last dvfsrc level
+#define AP_VCORE_DVFS_HISTORY_BASE (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x100) // dvfsrc history start address, end address should be 0x13C
+#define AP_VCORE_DVFS_HISTORY_SIZE 16
+#endif
+#define AP_TXZQ_OCCUR_TICK (volatile kal_uint32 *)(BASE_ADDR_AP_SPM+0x65C) // AP TX/ZQ occur time
+#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(BASE_ADDR_AP_SPM+0x658) // AP DVFS occur time
+
+
+#include "sleepdrv_interface.h"
+
+
+
+// ELM Set Mode (HW/SW Mode)
+enum {
+ ELM_MODE_0_LATENCY = 0, //write transaction, write latency, read transaction, read latency
+ ELM_MODE_1_WORD_COUNT = 1, //
+ ELM_MODE_2_SPECIAL = 2,
+
+};
+
+enum {
+ ELM_MASTER_ALL = 0,
+ ELM_MASTER_USIP = 1,
+ ELM_MASTER_MDMCU = 2,
+
+};
+
+#define DECODE_ID0(x) ((x)<<0)
+#define LAT_TH_ID0(x) ((x)<<5)
+#define LAT_TH_ID1(x) ((x)<<15)
+#define ELM_ACCURACY(x) ((x)<<25)
+ #define ELM_unit_1us 0
+ #define ELM_unit_10us 1
+ #define ELM_unit_100us 2
+ #define ELM_unit_1000us 3
+#define ELM_ENABLE (1<<27)
+#define ELM_DISABLE (0<<27)
+
+
+#define ELM_INT_MASK(x) ((x)<<0)
+ #define ID1 (3<<2)
+ #define ID0 (3<<0)
+#define EMI_BLOCK(x) ((x)<<4)
+ #define E_NOT_MASK 0
+ #define E_MASK 1
+#define ELM_DURATION(x) ((x)<<5)
+ #define ELM_200US 1 // need to pair EMI_unit_xxxus 0:means 1, 1:means 2
+ #define ELM_400US 3
+ #define ELM_1000US 0
+#define DECODE_ID1(x) ((x)<<12)
+ #define ELM_READ (0<<4)
+ #define ELM_WRITE (1<<4)
+ #define ELM_ALL_MASTER (0<<2)
+ #define ELM_MDMCU_ONLY (1<<2)
+ #define ELM_USIP_ONLY (2<<2)
+ #define ELM_ALL_PRIO (0<<0)
+ #define ELM_PRE_ULTRA (1<<0)
+ #define ELM_ULTRA (2<<0)
+#define ELM_EMI_TOP_BLOCK(x) ((x)<<24)
+
+#define ELM_AO_DECODE(x) ((x)<<13)
+ #define ELM_DECODE_FROM_AO 1
+ #define ELM_DECODE_FROM_APB 0
+#define ELM_AO_CONTROL_DEFAULT 0x73F73FFF
+
+#define ELM_VPE_SEL(x) ((x)<<28)
+ #define ELM_SEL_VPE0 0x0
+ #define ELM_SEL_VPE1 0x4
+ #define ELM_SEL_VPE2 0x1
+ #define ELM_SEL_VPE3 0x5
+#define ELM_MASTER_SEL(x) ((x)<<0)
+ #define ELM_MASTER_IA_MASK 0x3
+
+#define ELM_USIP_CORE_SEL(x) (((x)<<4)|0x2)
+#define ELM_USIP_PORT_SEL(x) ((x)<<2)
+ #define ELM_USIP_PORT_ENABLE_MASK 0x3
+ #define ELM_USIP_PORT_DISABLE_MASK 0x0
+ #define ELM_SEL_USIP_ALL 0x0
+ #define ELM_SEL_USIP_ICACHE 0x0
+ #define ELM_SEL_USIP_DCACHE 0x1
+ #define ELM_SEL_USIP_DNOCACHE 0x2
+
+
+//MCUSYS fixed clock 208Mhz, 1T = 4.8ns
+#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
+#define ELM_NS2TRAN(X) ((((X)*208)/1000))
+
+//MDINFRA fixed clock 100Mhz, 1T = 10ns
+#define ELM_MDIFRA_TRANS2NS(X) (((X)*10))
+#define ELM_MDIFRA_NS2TRAN(X) (((X)/10))
+
+#define ELM_HISTORY_SIZE 64
+
+//for assert information
+#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
+//#define KAL_ERROR_IOCU_ELM_EXCEP 0x4101
+#define KAL_ERROR_DMA_ELM_EXCEP 0x4102
+//#define KAL_ERROR_L1_ELM_EXCEP 0x4103
+
+#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ #define __ELM_TRACE__
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
+#endif
+
+
+/*
+#define REG_MDINFRA_ELM_CFG0 0xA0060078
+#define REG_MDINFRA_ELM_CFG0 0xA006007C
+*/
+#ifdef __MTK_TARGET__
+
+#ifdef ELM_AMIF_ENABLE
+kal_uint32 elm_read_lat_threshold = 2000;
+kal_uint32 elm_write_lat_threshold = 2000;
+#else
+kal_uint32 elm_read_lat_threshold = 400;
+kal_uint32 elm_write_lat_threshold = 300;
+#endif
+kal_uint32 elm_infra_read_lat_threshold = 2000;
+kal_uint32 elm_infra_write_lat_threshold = 2000;
+
+
+kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
+kal_uint32 elm_lat_duration = 200;
+kal_uint32 elm_trans_threshold = 100;
+kal_uint32 elm_mode = ELM_MODE_0_LATENCY;
+kal_uint32 elm_id0_master = ELM_ALL_MASTER;
+kal_uint32 elm_id0_rw = ELM_READ;
+kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
+
+kal_uint32 elm_id1_master = ELM_ALL_MASTER;
+kal_uint32 elm_id1_rw = ELM_WRITE;
+kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
+
+kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_ao_id0_value = 0;
+kal_uint32 elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_ao_id1_value = 0;
+kal_uint32 elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+
+
+
+
+#if defined(__PRODUCTION_RELEASE__)
+elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
+elm_exception_type L1_DMA_irq_exception_type = ELM_NONE; //L1 and DMA default use trace
+#else
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*--- ELM history variable ---*/
+//EMI ELM
+#define ELM_RUNTIME_HISTORY_SIZE 8
+kal_uint32 emi_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+
+//DMA ELM
+kal_uint32 dma_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T dma_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+
+
+
+
+
+void elmtop_emi_isr_handler();
+void elm_dma_isr_handler();
+
+
+
+kal_uint32 elm_profile_history_idx_0 = 0;
+ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
+
+
+void ELM_INIT(void)
+{
+ /*MDMCU EMI ELM*/
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, 0x0F); //clear ELM interrup
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (0x3<<4)); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ((elm_mode&0x3)<<4));//select ELM mode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(ELM_200US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ MDCIRQ_IRQ_Register_LISR(IRQ_ELMTOP_EMI_IRQ_CODE, (void *)elmtop_emi_isr_handler, "ELMTOP_EMI_LISR");
+ MDCIRQ_IRQSensitivity(IRQ_ELMTOP_EMI_IRQ_CODE, KAL_FALSE); // level trigger
+ MDCIRQ_IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+
+
+ /*MDINFRA EMI ELM*/
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_INT_STATUS, 0x0F); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| \
+ ELM_DURATION(ELM_1000US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_1000us)| \
+ LAT_TH_ID1(ELM_MDIFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0(ELM_MDIFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ MDCIRQ_IRQ_Register_LISR(IRQ_ELM_DMA_IRQ_CODE, (void *)elm_dma_isr_handler, "ELM_DMA_LISR");
+ MDCIRQ_IRQSensitivity(IRQ_ELM_DMA_IRQ_CODE, KAL_FALSE); // level trigger
+ MDCIRQ_IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+}
+
+
+void ELM_Config_DormantLeave(void)
+{
+ kal_uint32 vpe_idx;
+ vpe_idx = kal_get_current_vpe_id();
+ if(0 == vpe_idx)
+ {
+ ELM_INIT();
+ emi_elm_runtime_lat_history_idx =0;
+ memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
+ }
+}
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
+{
+ if(NULL==data)
+ {
+ return;
+ }
+
+#ifdef __ELM_RUNTIME_PROFILE__
+ elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
+ ELM_GET_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
+ elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
+ elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
+ memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
+ elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
+#else
+ data->fma_stamp = ust_get_current_time();
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
+#endif
+
+}
+
+kal_uint32 debug_emi_elm_runtime_counter = 0;
+kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
+kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
+
+
+#define ID0_AVG_LAT_INT (1<<0)
+#define ID0_TOT_LAT_INT (1<<1)
+#define ID1_AVG_LAT_INT (1<<2)
+#define ID1_TOT_LAT_INT (1<<3)
+
+#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
+
+//#define MD2SPM_DVFS_CON (volatile kal_uint32 *)(0xF013000 + 0xC00)
+
+kal_uint32 elm_md_dvfs_con = 0;
+kal_uint32 elm_ap_vcore_dvfs_current = 0;
+kal_uint32 elm_ap_vcore_dvfs_last = 0;
+kal_uint32 elm_ap_vcore_dvfs_history[AP_VCORE_DVFS_HISTORY_SIZE] = {0};
+
+void elmtop_emi_isr_handler()
+{
+ // TODO: ELM mutex need here
+
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 int_Result = 0; //Indicate this irq is caused by whether read(KAL_TRUE) or write(KAL_FALSE)
+ kal_uint32 read_worst_latency_count = 0;
+ kal_uint32 write_worst_latency_count = 0;
+ kal_uint32 read_trans_count = 0;
+ kal_uint32 write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0;
+ kal_uint32 write_worst_latency_ns = 0;
+ kal_uint32 read_total_count = 0;
+ kal_uint32 write_total_count = 0;
+ kal_uint32 ia_13m_tick = 0, txzq_13m_tick = 0, dvfs_13m_tick = 0;
+ debug_emi_elm_runtime_counter++;
+
+
+
+
+ //Mask cirq ELM interrupt
+ MDCIRQ_IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //DRV_WriteReg32_NPW(REG_MCUSYS_EMI_ELM_ELM_EN_REG, 0); //stop ELM
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+
+ curr_frc = ust_get_current_time();
+ ia_13m_tick = SleepDrv_GetWallClk();
+ txzq_13m_tick = DRV_Reg32(AP_TXZQ_OCCUR_TICK);
+ dvfs_13m_tick = DRV_Reg32(AP_DVFS_OCCUR_TICK);
+
+ //SET_ELM_RW_LAT_FLAG(REG_MCUSYS_EMI_ELM_ELM_INT_STATUS, &lat_flag, &r_flag);
+ int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS); //clear ELM interrupt
+
+ read_worst_latency_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT);
+ write_worst_latency_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT);
+ read_worst_latency_ns = ELM_TRANS2NS(read_worst_latency_count);
+ write_worst_latency_ns = ELM_TRANS2NS(write_worst_latency_count);
+
+ read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG);
+ write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG);
+ read_total_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT);
+ write_total_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT);
+
+
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;//write_worst_latency_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].txzq_dvfs_tick = txzq_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+ emi_elm_runtime_lat_history_idx++;
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ int_Result= ID0_AVG_LAT_INT; //read latency over criteria
+ }
+ else
+ {
+ int_Result= ID1_AVG_LAT_INT; //write latency over criteria
+ }
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, 0x0F); //clear ELM interrupt
+ elm_md_dvfs_con = *MD2SPM_DVFS_CON;
+ elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
+ elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
+
+
+ // 1000us(Ibit off maximum) + 200us (IRQ priority prempt) + 200us(detect window) = 1400us
+ if(ust_us_duration(txzq_13m_tick, ia_13m_tick) < 18200) //1400us * 13 = 18200 system tick
+ {
+ //debug_MDMCU_elm_last_INT_FRC = 0;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_TXZQ_WARN(curr_frc, ia_13m_tick, txzq_13m_tick),);
+ }
+ else if(ust_us_duration(dvfs_13m_tick, ia_13m_tick) < 18200) //1400us * 13 = 18200 system tick
+ {
+ //debug_MDMCU_elm_last_INT_FRC = 0;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_AP_DVFS_WARN(curr_frc, ia_13m_tick, dvfs_13m_tick),);
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_TXZQ_WARN(curr_frc, ia_13m_tick, txzq_13m_tick),);
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_AP_DVFS_WARN(curr_frc, ia_13m_tick, dvfs_13m_tick),);
+ }
+
+
+ switch(EMI_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+
+#ifdef __ELM_TRACE__
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS %xl"
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_count, read_trans_count, elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last);
+ }
+ else
+ {
+ //warn EMI_ELM_R_LAT_WARN ELM_Basic_Info_H "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS %xl"
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_count, write_trans_count, elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last);
+ }
+#endif
+ break;
+ }
+
+ case ELM_ASSERT:
+ {
+ if(int_Result == ID0_AVG_LAT_INT) //read latency over criteria
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_count)), \
+ (E_MAX16(*MD2SPM_DVFS_CON)<<16)|(E_MAX16(int_status)));
+ }
+ else //write latency over criteria
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_count)), \
+ (E_MAX16(*MD2SPM_DVFS_CON)<<16)|(E_MAX16(int_status)));
+ }
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ // just show trace on first time over criteria in 300us
+ if(debug_MDMCU_elm_last_INT_FRC == 0)
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ #ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS %xl"
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_count, read_trans_count, elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last);
+ }
+ else
+ {
+ //warn EMI_ELM_R_LAT_WARN ELM_Basic_Info_H "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS %xl"
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_count, write_trans_count, elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last);
+ }
+ #endif
+ }
+ else
+ {
+ if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < 300)
+ {
+ kal_uint32 i;
+ for(i=0;i<AP_VCORE_DVFS_HISTORY_SIZE;i++)
+ {
+ elm_ap_vcore_dvfs_history[i] = *(AP_VCORE_DVFS_HISTORY_BASE + i);
+ }
+
+ if(int_Result == ID0_AVG_LAT_INT) //read latency over criteria
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_count)), \
+ (E_MAX16(*MD2SPM_DVFS_CON)<<16)|(E_MAX16(int_status)));
+ }
+ else //write latency over criteria
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_count)), \
+ (E_MAX16(*MD2SPM_DVFS_CON)<<16)|(E_MAX16(int_status)));
+ }
+ }
+ else
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ #ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS %xl"
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_count, read_trans_count, elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last);
+ }
+ else
+ {
+ //warn EMI_ELM_R_LAT_WARN ELM_Basic_Info_H "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS %xl"
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_count, write_trans_count, elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last);
+ }
+ #endif
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ MDCIRQ_IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+}
+
+void elm_dma_isr_handler()
+{
+
+ // TODO: ELM mutex need here
+
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_worst_latency_count = 0;
+ kal_uint32 write_worst_latency_count = 0;
+ kal_uint32 read_trans_count = 0;
+ kal_uint32 write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0;
+ kal_uint32 write_worst_latency_ns = 0;
+ kal_uint32 read_total_count = 0;
+ kal_uint32 write_total_count = 0;
+
+
+
+
+
+ //Mask cirq ELM interrupt
+ MDCIRQ_IRQMask(IRQ_ELM_DMA_IRQ_CODE);
+
+ //DRV_WriteReg32_NPW(REG_MCUSYS_EMI_ELM_ELM_EN_REG, 0); //stop ELM
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+
+ curr_frc = ust_get_current_time();
+
+ //SET_ELM_RW_LAT_FLAG(REG_MCUSYS_EMI_ELM_ELM_INT_STATUS, &lat_flag, &r_flag);
+ int_status = DRV_Reg32(REG_MDINFRA_EMI_ELM_INT_STATUS); //clear ELM interrupt
+
+ read_worst_latency_count = DRV_Reg32(REG_MDINFRA_EMI_ELM_ID0_WORST_AVG_LAT);
+ write_worst_latency_count = DRV_Reg32(REG_MDINFRA_EMI_ELM_ID1_WORST_AVG_LAT);
+ read_worst_latency_ns = ELM_MDIFRA_TRANS2NS(read_worst_latency_count);
+ write_worst_latency_ns = ELM_MDIFRA_TRANS2NS(write_worst_latency_count);
+
+ read_trans_count = DRV_Reg32(REG_MDINFRA_EMI_ELM_ID0_TRANS_IN_WORST_AVG);
+ write_trans_count = DRV_Reg32(REG_MDINFRA_EMI_ELM_ID1_TRANS_IN_WORST_AVG);
+ read_total_count = DRV_Reg32(REG_MDINFRA_EMI_ELM_ID0_WORST_TOT_LAT);
+ write_total_count = DRV_Reg32(REG_MDINFRA_EMI_ELM_ID1_WORST_TOT_LAT);
+
+
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;//write_worst_latency_count;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_count;
+ dma_elm_runtime_lat_history[dma_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_count;
+ dma_elm_runtime_lat_history_idx++;
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_INT_STATUS, 0x0F); //clear ELM interrupt
+
+ switch(L1_DMA_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+#ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l"
+ MD_TRC_DMA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_count, read_trans_count);
+ }
+ else
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l"
+ MD_TRC_DMA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_count, write_trans_count);
+ }
+#endif
+ break;
+ }
+
+ default:
+ break;
+ }
+
+
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_1000us)| \
+ LAT_TH_ID1(ELM_MDIFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0(ELM_MDIFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ MDCIRQ_IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+}
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
+ {
+ kal_uint32 lr = 0;
+ kal_uint32 sub_error_code = 0;
+ GET_RETURN_ADDRESS(lr);
+ if(read_avg_lat_ns<200)
+ {
+ sub_error_code = 1;
+ }
+ else if(write_avg_lat_ns<200)
+ {
+ sub_error_code = 2;
+ }
+ else
+ {
+ sub_error_code = 3;
+ }
+ EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
+ }
+
+
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ MDCIRQ_IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_duration = dur_us;
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, 0x0F); //clear ELM interrupt
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+#ifdef __ELM_TRACE__
+ {
+ // L1 trace
+ kal_uint32 curr_frc = 0;
+ curr_frc = ust_get_current_time();
+ MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
+ MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
+ }
+#endif
+
+ if(!mask_state)
+ {
+ MDCIRQ_IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+void _ELM_exception_saved(void)
+{
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+kal_uint32 g_elm_read_worst_latency_count;
+kal_uint32 g_elm_write_worst_latency_count;
+kal_uint32 g_elm_read_worst_latency_ns;
+kal_uint32 g_elm_write_worst_latency_ns;
+
+kal_uint8 _ELM_latency_status(void)
+{
+#if 1//def __ELM_RUNTIME_PROFILE__
+
+ //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
+ if(emi_elm_runtime_lat_history_idx != 0)
+ {
+ kal_uint32 int_status = 0;
+ int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ return 0xAE; //EMI read latency may be too long
+ }
+ else
+ {
+ return 0xBE; //EMI write latency may be too long
+ }
+ }
+ return 0xDE; // EMI read/write latency are OK.
+#else
+/* under construction !*/
+#endif
+}
+
+/******************************************************************************
+* Function : void Set_EMI_ELM_ExceptionType(kal_bool lat_flag, kal_uint8 exception_type)
+* Description : this function is called when set EMI ELM Read/Write Latency/WordCount Exception Type
+* Parameter : kal_uint8 exception_type: 0,1,2
+* Return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
+{
+ switch (exception_type)
+ {
+ case ELM_NONE:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_NONE;
+ break;
+ }
+
+ case ELM_ASSERT:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
+ break;
+ }
+ default:
+ return KAL_FALSE;
+ break;
+ }
+ return KAL_TRUE;
+}
+
+kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
+{
+ ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
+ ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+ if((info&0xF0))
+ { // infra
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_infra_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_DMA_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_infra_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_DMA_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_1000us)| \
+ LAT_TH_ID1(ELM_MDIFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0(ELM_MDIFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+ }
+ else
+ { //mdmcu
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ }
+
+
+ return KAL_TRUE;
+}
+
+kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if( id == 1 ) // id 1 (default write)
+ {
+ if(m_sel==0)
+ {
+ elm_id1_master = ELM_ALL_MASTER;
+ }
+ else if(m_sel==1)
+ {
+ elm_id1_master = ELM_MDMCU_ONLY;
+ }
+ else if(m_sel==2)
+ {
+ elm_id1_master = ELM_USIP_ONLY;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id1_rw = ELM_READ;
+ }
+ else if(rw == 1)
+ {
+ elm_id1_rw = ELM_WRITE;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if(id == 0)// id 0
+ {
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id0_rw = ELM_READ;
+ }
+ else if(rw == 1)
+ {
+ elm_id0_rw = ELM_WRITE;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ }
+ else if(id == 2)// ID 0/1 are the same
+ {
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+ elm_id1_master = ELM_ALL_MASTER;
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+ elm_id1_master = ELM_MDMCU_ONLY;
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+ elm_id1_master = ELM_USIP_ONLY;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(ELM_200US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+
+}
+
+kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if( mode == 0)
+ {
+ elm_mode = ELM_MODE_0_LATENCY;
+ }
+ else if( mode == 1)
+ {
+ elm_mode = ELM_MODE_1_WORD_COUNT;
+ }
+ else if( mode == 2)
+ {
+ elm_mode = ELM_MODE_2_SPECIAL;
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ DRV_ClrReg32(REG_MDINFRA_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MDINFRA_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (0x3<<4)); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ((elm_mode&0x3)<<4));//select ELM mode
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(ELM_200US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+
+ DRV_ClrReg32(REG_MDINFRA_EMI_ELM_CTRL_REG, (0x3<<4)); // clear ELM mode
+ DRV_SetReg32(REG_MDINFRA_EMI_ELM_CTRL_REG, ((elm_mode&0x3)<<4));//select ELM mode
+
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| \
+ ELM_DURATION(ELM_1000US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_1000us)| \
+ LAT_TH_ID1(ELM_MDIFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0(ELM_MDIFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+
+
+kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 vpe_sel, kal_uint8 port_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ elm_ao_id0_value = 0;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_ao_id1_value = 0;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+
+ if( id == 1 ) // id 1 (default write)
+ {
+ if (port_sel==0)
+ {
+ elm_ao_id1_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_DISABLE_MASK));
+ }
+ else
+ {
+ elm_ao_id1_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_ENABLE_MASK));
+ }
+
+ if(vpe_sel==0)
+ {
+ if (port_sel == 0)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ }
+ else if (port_sel == 1)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ }
+ else if (port_sel == 2)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ }
+ else if (port_sel == 3)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(vpe_sel==1)
+ {
+ if (port_sel == 0)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ }
+ else if (port_sel == 1)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ }
+ else if (port_sel == 2)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ }
+ else if (port_sel == 3)
+ {
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(id == 0)// id 0
+ {
+ if (port_sel==0)
+ {
+ elm_ao_id0_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_DISABLE_MASK));
+ }
+ else
+ {
+ elm_ao_id0_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_ENABLE_MASK));
+ }
+
+ if(vpe_sel==0)
+ {
+ if (port_sel == 0)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ }
+ else if (port_sel == 1)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ }
+ else if (port_sel == 2)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ }
+ else if (port_sel == 3)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(vpe_sel==1)
+ {
+ if (port_sel == 0)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ }
+ else if (port_sel == 1)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ }
+ else if (port_sel == 2)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ }
+ else if (port_sel == 3)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(id == 2)// ID 0/1 are the same
+ {
+ if (port_sel==0)
+ {
+ elm_ao_id0_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_DISABLE_MASK));
+ elm_ao_id1_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_DISABLE_MASK));
+ }
+ else
+ {
+ elm_ao_id0_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_ENABLE_MASK));
+ elm_ao_id1_mask &=~ (ELM_USIP_CORE_SEL(1)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK)|ELM_USIP_PORT_SEL(ELM_USIP_PORT_ENABLE_MASK));
+ }
+
+ if(vpe_sel==0)
+ {
+ if (port_sel == 0)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ }
+ else if (port_sel == 1)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ }
+ else if (port_sel == 2)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ }
+ else if (port_sel == 3)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(0)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(vpe_sel==1)
+ {
+ if (port_sel == 0)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ALL);
+ }
+ else if (port_sel == 1)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_ICACHE);
+ }
+ else if (port_sel == 2)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DCACHE);
+ }
+ else if (port_sel == 3)
+ {
+ elm_ao_id0_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ elm_ao_id1_value = ELM_USIP_CORE_SEL(1)|ELM_USIP_PORT_SEL(ELM_SEL_USIP_DNOCACHE);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rtn == KAL_FALSE)
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+ }
+ else
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_ao_id0_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_ao_id0_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_ao_id1_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_ao_id1_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(ELM_200US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+
+}
+
+kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ elm_ao_id0_value = 0;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_ao_id1_value = 0;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+
+ if( id == 1 ) // id 1 (default write)
+ {
+ elm_ao_id1_mask &=~ (ELM_VPE_SEL(0X7)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK));
+ if(vpe_sel==0)
+ {
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE3);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(id == 0)// id 0
+ {
+ elm_ao_id0_mask &=~ (ELM_VPE_SEL(0X7)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK));
+ if(vpe_sel==0)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE3);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 2)// ID 0/1 are the same
+ {
+ elm_ao_id0_mask &=~ (ELM_VPE_SEL(0x7)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK));
+ elm_ao_id1_mask &=~ (ELM_VPE_SEL(0x7)|ELM_MASTER_SEL(ELM_MASTER_IA_MASK));
+ if(vpe_sel==0)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE0);
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE1);
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE2);
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_ao_id0_value = ELM_VPE_SEL(ELM_SEL_VPE3);
+ elm_ao_id1_value = ELM_VPE_SEL(ELM_SEL_VPE3);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_ao_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_ao_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rtn == KAL_FALSE)
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+ }
+ else
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_ao_id0_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_ao_id0_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_ao_id1_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_ao_id1_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS0_CFG1, ELM_EMI_TOP_BLOCK(0xff)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(ELM_200US)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(0));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS0_CFG0, ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+
+}
+
+
+
+#endif
+
+
diff --git a/mcu/driver/devdrv/elm/src/md93/elm_trace_utmd.json b/mcu/driver/devdrv/elm/src/md93/elm_trace_utmd.json
new file mode 100644
index 0000000..ffd0d76
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md93/elm_trace_utmd.json
@@ -0,0 +1,95 @@
+{
+ "endGen": "Legacy",
+ "legacyParameters": {
+ "modemType": "elm"
+ },
+ "module": "ELM",
+ "startGen": "Legacy",
+ "stringTranslationDefs": [],
+ "traceClassDefs": [
+ {
+ "ELM_Basic_Info_H": {
+ "_comment": "filterDefaulValue is used in xl1sim, will be phased out later",
+ "debugLevel": "High",
+ "filterDefaultValue": "ON",
+ "tag": [
+ "Basic_Info"
+ ],
+ "traceType": "CoreDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "EMI_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Read Latency Threshold] US_CNT %l us, R_Threshold %l ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Write Latency Threshold] US_CNT %l us, W_Threshold %l ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "DMA_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Read Latency Threshold] US_CNT %l us, R_Threshold %l ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "DMA_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Write Latency Threshold] US_CNT %l us, W_Threshold %l ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT %l us, L1 R_ave_lat %l ns, R_Threhsold %l ns, L2 R_Latency %l T, R_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Latency Violation] US_CNT %l us, L1 W_ave_lat %l ns, W_Threhsold %l ns, L2 W_Latency %l T, w_tran %l, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "DMA_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Read Latency Violation] US_CNT %l us, L1 R_ave_lat %l ns, R_Threhsold %l ns, L2 R_Latency %l T, R_tran %l",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "DMA_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Write Latency Violation] US_CNT %l us, L1 W_ave_lat %l ns, W_Threhsold %l ns, L2 W_Latency %l T, R_tran %l",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_TXZQ_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][TXZQ] US_CNT %l us, MD systick %l T, TXZQ %l T",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_AP_DVFS_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Vcore DVFS] US_CNT %l us, MD systick %l T, Vcore DVFS %l T",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ }
+ ],
+ "traceFamily": "L1"
+}
\ No newline at end of file
diff --git a/mcu/driver/devdrv/elm/src/md95/elm.c b/mcu/driver/devdrv/elm/src/md95/elm.c
new file mode 100644
index 0000000..fe9b2e6
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md95/elm.c
@@ -0,0 +1,2074 @@
+#include "elm.h"
+#include "drv_comm.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "drv_mdap_interface.h" //for show AMIF scenario register in trace
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+// for profiling ELM log
+#include "TrcMod.h" //for L1 Trace API
+#endif
+
+/** ----- Register definition ------ **/
+
+// MDMCU ELM
+#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
+#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
+#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
+ #define ELM_MODE(x) ((x)<<4)
+ #define ELM_MODE_MASK 0x3
+ #define ELM_AO_DECODE(x) ((x)<<13)
+ #define ELM_DECODE_FROM_AO 1
+ #define ELM_DECODE_FROM_APB 0
+ #define ELM_MODE_ID_SEL(x) (x<<8)
+ #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only
+ #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3
+#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
+ //Note: For "MDMCU" ELM support all in Mode 0 & Mode 2. For "MDINFRA" ELM only support AXI ID in mode 0, support all in mode 2.
+ #define AUSER(x) ((x)<<24) //7'h7F
+ #define AUSER_MASK 0x7F
+ #define USER_SOURCE(x) (x<<0)
+ #define US_MASK 0x3
+ #define US_USIP 0x0
+ #define US_IA 0x1
+ #define US_SFU 0x2
+ #define US_SPU 0x3
+ #define USER_ID(x) (x<<2)
+ #define UI_MASK 0x3
+ #define UI_VPE0 0x0
+ #define UI_VPE1 0x1
+ #define UI_THREAD0 0x0
+ #define UI_THREAD1 0x1
+ #define USER_CORE(x) (x<<4)
+ #define UC_MASK 0x7
+ #define UC_CORE0 0x0
+ #define UC_CORE1 0x1
+ #define UC_CORE2 0x2
+ #define UC_CORE3 0x3
+ #define UC_IOCU 0x4
+ #define UC_USIP0 0x5
+ #define UC_USIP1 0x6
+ #define ELM_SEL_VPE0 USER_SOURCE(US_IA)|USER_CORE(UC_CORE0)|USER_ID(UI_VPE0)
+ #define ELM_SEL_VPE1 USER_SOURCE(US_IA)|USER_CORE(UC_CORE0)|USER_ID(UI_VPE1)
+ #define ELM_SEL_VPE2 USER_SOURCE(US_IA)|USER_CORE(UC_CORE1)|USER_ID(UI_VPE0)
+ #define ELM_SEL_VPE3 USER_SOURCE(US_IA)|USER_CORE(UC_CORE1)|USER_ID(UI_VPE1)
+ #define ELM_SEL_VPE4 USER_SOURCE(US_IA)|USER_CORE(UC_CORE2)|USER_ID(UI_VPE0)
+ #define ELM_SEL_VPE5 USER_SOURCE(US_IA)|USER_CORE(UC_CORE2)|USER_ID(UI_VPE1)
+ #define ELM_SEL_USIP0_TH0 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP0)|USER_ID(UI_THREAD0)
+ #define ELM_SEL_USIP0_TH1 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP0)|USER_ID(UI_THREAD1)
+ #define ELM_SEL_USIP1_TH0 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP1)|USER_ID(UI_THREAD0)
+ #define ELM_SEL_USIP1_TH1 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP1)|USER_ID(UI_THREAD1)
+ #define ALEN(x) ((x)<<20) //4'hf
+ #define ASIZE(x) ((x)<<16) //3'h7
+ #define AULTRA(x) ((x)<<14) //2'h3
+ #define ABUST(x) ((x)<<12) //2'h3
+ #define AID(x) ((x)<<0) //12'hFFF
+ #define MASTER_DEFAULT_MASK 0xFFF //defualt value
+ #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2
+ #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU)
+ #define MASTER_MDMCU_MASK 0xFFD
+ #define MASTER_USIP 0x2 //USIP -> 0x2
+ #define MASTER_USIP_MASK 0xFFC
+ #define MASTER_USIP_PORT(x) (x<<2)
+ #define MUP_ALL_MASK 0x3FF
+ #define MUP_PM_MASK 0x3FA
+ #define MUP_PM 0x0
+ #define MUP_DC_MASK 0x3FA
+ #define MUP_DC 0x4
+ #define MUP_DP_ALL_MASK 0x3FE
+ #define MUP_DP_ALL 0x1
+ #define MUP_DP_MASK 0x3EE
+ #define MUP_DP_CACHE 0x11
+ #define MUP_DP_NONCACHE 0x1
+/*
+#define ELM_USIP_CORE_SEL(x) (((x)<<4)|0x2)
+#define ELM_USIP_PORT_SEL(x) ((x)<<2)
+ #define ELM_USIP_PORT_ENABLE_MASK 0x3
+ #define ELM_USIP_PORT_DISABLE_MASK 0x0
+ #define ELM_SEL_USIP_ALL 0x0
+ #define ELM_SEL_USIP_ICACHE 0x0
+ #define ELM_SEL_USIP_DCACHE 0x1
+ #define ELM_SEL_USIP_DNOCACHE 0x2
+*/
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
+ #define ELM_AO_CONTROL_DEFAULT 0x7FF7FFFF
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
+#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
+#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
+#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
+#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
+#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
+#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
+ #define INT_MASK_ALL 0x3F
+ #define INT_MASK_LAT 0xF
+ #define INT_MASK_WC 0x30
+ #define ID0_AVG_LAT_INT (1<<0)
+ #define ID0_TOT_LAT_INT (1<<1)
+ #define ID1_AVG_LAT_INT (1<<2)
+ #define ID1_TOT_LAT_INT (1<<3)
+ #define ID2_TOT_WC_INT (1<<4)
+ #define ID3_TOT_WC_INT (1<<5)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
+ #define DECODE_ID0(x) ((x)<<0)
+ #define ELM_READ (0<<4)
+ #define ELM_WRITE (1<<4)
+ #define ELM_ALL_MASTER (0<<2)
+ #define ELM_MDMCU_ONLY (1<<2)
+ #define ELM_USIP_ONLY (2<<2)
+ #define ELM_ALL_PRIO (0<<0)
+ #define ELM_PRE_ULTRA (1<<0)
+ #define ELM_ULTRA (2<<0)
+ #define LAT_TH_ID0_NORMAL(x) ((x)<<5)
+ #define LAT_TH_ID1_NORMAL(x) ((x)<<15)
+ #define ELM_ACCURACY(x) ((x)<<25)
+ #define ELM_unit_100us 2
+ #define ELM_ENABLE (1<<27)
+ #define ELM_DISABLE (0<<27)
+ #define ELM_IDLE_ENABLE (1<<28)
+ #define ELM_IDLE_DISABLE (0<<28)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
+ #define ELM_INT_MASK(x) ((x)<<0)
+ #define LAT_INT_MASK_ALL 0xF
+ #define LAT_INT_UNMASK_ALL 0x0
+ #define EMI_BLOCK(x) ((x)<<4)
+ #define E_NOT_MASK 0
+ #define E_MASK 1
+ #define ELM_DURATION(x) ((x-1)<<5) // (x-1+1)*(ELM_ACCURACY), ELM_ACCURACY = 100us
+ #define DECODE_ID1(x) ((x)<<12)
+ /* #define usage same as DECODE_ID0 */
+ #define ELM_EMI_TOP_BLOCK(x) ((x)<<31)
+ #define E_TOP_MASK 1
+ #define E_TOP_NOT_MASK 0
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC)
+#define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0)
+#define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC)
+#define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0)
+#define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0)
+ #define ELM_WC_INT_MASK(x) ((x)<<0)
+ #define WC_INT_MASK_ALL 0x3
+ #define WC_INT_UNMASK_ALL 0x0
+ #define LAT_TH_ID0_BLOCK(x) ((x)<<4)
+ #define LAT_TH_ID1_BLOCK(x) ((x)<<16)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510)
+#define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514)
+#define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528)
+ #define ELM_WC_DURATION(x) (x-1) // (x-1+1) us
+
+
+// MDINFRA ELM
+#define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
+#define REG_MDINFRA_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x20)
+#define REG_MDINFRA_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x24)
+#define REG_MDINFRA_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x28)
+#define REG_MDINFRA_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x2C)
+#define REG_MDINFRA_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x30)
+#define REG_MDINFRA_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x34)
+#define REG_MDINFRA_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x38)
+#define REG_MDINFRA_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x3C)
+#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70)
+#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74)
+#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78)
+#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C)
+#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80)
+#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84)
+#define REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x88)
+#define REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x8C)
+#define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0)
+#define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4)
+#define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
+#define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
+#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510)
+#define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514)
+#define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528)
+ #define ELM_WC_DURATION(x) (x-1) // (x-1+1) us
+
+//AO Register in MDPERIMISC
+#define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
+#define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
+#define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090
+#define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
+#define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
+#define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094
+
+/** ----- AP debugging register definition ------ **/
+#if 1 //defined(MT3967)
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xFC) // current dvfsrc level
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x308) // last dvfsrc level
+#define AP_VCORE_DVFS_HISTORY_BASE (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x400) // dvfsrc history start address, end address should be 0x45C
+#define AP_VCORE_DVFS_HISTORY_SIZE 24
+#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(BASE_ADDR_AP_SPM+0x624)
+#endif
+
+#include "sleepdrv_interface.h"
+
+// ELM Set Mode (HW/SW Mode)
+enum {
+ ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt
+ ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA
+};
+
+//MCUSYS fixed clock 208Mhz, 1T = 4.8ns
+#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
+#define ELM_NS2TRAN(X) ((((X)*208)/1000))
+
+//MDINFRA fixed clock 100Mhz, 1T = 10ns
+#define ELM_MDINFRA_TRANS2NS(X) (((X)*10))
+#define ELM_MDINFRA_NS2TRAN(X) (((X)/10))
+
+
+//for assert information
+#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
+#define KAL_ERROR_INFRA_ELM_EXCEP 0x4102
+
+#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ #define __ELM_TRACE__
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
+#endif
+
+
+#ifdef __MTK_TARGET__
+
+kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
+
+/*--- MDMCU global variable ---*/
+kal_uint32 elm_mode = ELM_MODE_0;
+// latency criteria
+kal_uint32 elm_trans_threshold = 100;
+kal_uint32 elm_lat_dur_100us = 2; //2*100us = 200us
+#ifdef ELM_AMIF_ENABLE
+kal_uint32 elm_read_lat_threshold = 2000;
+kal_uint32 elm_write_lat_threshold = 2000;
+#else
+kal_uint32 elm_read_lat_threshold = 450;
+kal_uint32 elm_write_lat_threshold = 300;
+#endif
+// word count criteria
+kal_uint32 elm_wc_dur_in_us = 200; // 2*100us = 200us
+kal_uint32 elm_read_wc_threshold = 2*1024*1024*256; // 2*1024*1024*1024/4 * 4 = 2GB
+kal_uint32 elm_write_wc_threshold = 2*1024*1024*256; // 2*1024*1024*1024/4 * 4 = 2GB
+// AO decode setting
+kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_id0_master = ELM_ALL_MASTER;
+kal_uint32 elm_id0_rw = ELM_READ;
+kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
+kal_uint32 elm_id1_master = ELM_ALL_MASTER;
+kal_uint32 elm_id1_rw = ELM_WRITE;
+kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
+// IDx cnt default value target all transaction
+kal_uint32 elm_id0_value = 0;
+kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id1_value = 0;
+kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id2_value = 0;
+kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id3_value = 0;
+kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id2_rw = ELM_RD;
+kal_uint32 elm_id3_rw = ELM_WR;
+
+/*--- MDINFRA global variable ---*/
+// latency criteria
+kal_uint32 elm_infra_lat_dur_100us = 10; //10*100us = 1000us = 1ms
+kal_uint32 elm_infra_read_lat_threshold = 2000;
+kal_uint32 elm_infra_write_lat_threshold = 2000;
+// word count criteria
+kal_uint32 elm_infra_wc_dur_in_us = 10000; // 10*1000us = 10ms
+kal_uint32 elm_infra_read_wc_threshold = 2*1024*1024*256;
+kal_uint32 elm_infra_write_wc_threshold = 2*1024*1024*256;
+// ID2/3 cnt default value target all transaction
+kal_uint32 elm_infra_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_infra_id0_value = 0;
+kal_uint32 elm_infra_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id1_value = 0;
+kal_uint32 elm_infra_id1_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id2_value = 0;
+kal_uint32 elm_infra_id2_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id3_value = 0;
+kal_uint32 elm_infra_id3_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id2_rw = ELM_RD;
+kal_uint32 elm_infra_id3_rw = ELM_WR;
+
+
+#if defined(__PRODUCTION_RELEASE__)
+elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
+elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace
+elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace
+elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*--- ELM history variable ---*/
+#define ELM_RUNTIME_HISTORY_SIZE 8
+
+//EMI ELM
+kal_uint32 emi_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 emi_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+//INFRA ELM
+kal_uint32 infra_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 infra_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+
+
+
+
+void elmtop_emi_isr_handler();
+void elm_infra_isr_handler();
+
+
+
+#define ELM_HISTORY_SIZE 64
+kal_uint32 elm_profile_history_idx_0 = 0;
+ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
+
+
+void ELM_INIT(void)
+{
+ /*MDMCU EMI ELM*/
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config id2/3 setting
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, elm_read_wc_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, elm_write_wc_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_DURATION(elm_wc_dur_in_us));
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2, LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))| \
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+#if 0 //IRQ register is done by IRQ centralization
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ /*MDINFRA EMI ELM*/
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_infra_id2_rw, 2)|ELM_ID_RW(elm_infra_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config word_cnt window setting
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID2_CTRL_REG, elm_infra_id2_value);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID2_CTRL_MASK, elm_infra_id2_mask);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID3_CTRL_REG, elm_infra_id3_value);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID3_CTRL_MASK, elm_infra_id3_mask);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, elm_infra_read_wc_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, elm_infra_write_wc_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_DURATION(elm_infra_wc_dur_in_us));
+
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| \
+ ELM_DURATION(elm_infra_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2, LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))| \
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+#if 0 //IRQ register is done by IRQ centralization
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+void ELM_Config_DormantLeave(void)
+{
+ kal_uint32 vpe_idx;
+ vpe_idx = kal_get_current_vpe_id();
+ if(0 == vpe_idx)
+ {
+ ELM_INIT();
+ emi_elm_runtime_lat_history_idx =0;
+ memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
+ }
+}
+
+void ELM_Config_DormantEnter(void)
+{
+
+}
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
+{
+ if(NULL==data)
+ {
+ return;
+ }
+
+#ifdef __ELM_RUNTIME_PROFILE__
+ elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
+ ELM_GET_ALL_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
+ elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
+ elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
+ memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
+ elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
+#else
+ data->fma_stamp = ust_get_current_time();
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
+ ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
+ ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount));
+#endif
+
+}
+
+kal_uint32 debug_emi_elm_runtime_counter = 0;
+kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
+kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
+
+
+
+#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
+
+kal_uint32 elm_md_dvfs_con = 0;
+kal_uint32 elm_ap_vcore_dvfs_current = 0;
+kal_uint32 elm_ap_vcore_dvfs_last = 0;
+kal_uint32 elm_ap_vcore_dvfs_history[AP_VCORE_DVFS_HISTORY_SIZE] = {0};
+
+void elmtop_emi_isr_handler()
+{
+ // TODO: ELM mutex need here
+
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0;
+ debug_emi_elm_runtime_counter++;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //DRV_WriteReg32_NPW(REG_MCUSYS_EMI_ELM_ELM_EN_REG, 0); //stop ELM
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+
+ curr_frc = ust_get_current_time();
+#if 1
+ ia_13m_tick = SleepDrv_GetWallClk();
+ dvfs_13m_tick = DRV_Reg32(AP_DVFS_OCCUR_TICK);
+#endif
+ int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS); //Read ELM interrupt status
+
+ // Check latency or word count interrupt first
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) );
+ write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+ write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) );
+ read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+ emi_elm_runtime_lat_history_idx++;
+
+ elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg();
+ // Read AP side debugging register
+ elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
+ elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
+#if defined(MT3967)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ // only dvfs tick information, no need to use if/else.
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_AP_DVFS_WARN(curr_frc, ia_13m_tick, dvfs_13m_tick),);
+#endif
+ switch(EMI_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ //read latency over criteria
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ //write latency over criteria
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ // just show trace on first time over criteria in 300us
+ if(debug_MDMCU_elm_last_INT_FRC == 0)
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ }
+ else
+ {
+ if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < 300)
+ {
+ kal_uint32 i;
+ for(i=0;i<AP_VCORE_DVFS_HISTORY_SIZE;i++)
+ {
+ elm_ap_vcore_dvfs_history[i] = *(AP_VCORE_DVFS_HISTORY_BASE + i);
+ }
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ }
+ else
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ }
+ /* Handling word count interrupt */
+ else
+ {
+ read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
+
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ emi_elm_runtime_wc_history_idx++;
+
+ switch(EMI_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, read_worst_wc, elm_read_wc_threshold), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, write_worst_wc, elm_write_wc_threshold), \
+ );
+ }
+ break;
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ default:
+ break;
+ }
+ }
+
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+}
+
+void elm_infra_isr_handler()
+{
+
+ // TODO: ELM mutex need here
+
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+ kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELM_DMA_IRQ_CODE);
+
+ //DRV_WriteReg32_NPW(REG_MCUSYS_EMI_ELM_ELM_EN_REG, 0); //stop ELM
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+#if 1
+ ia_13m_tick = SleepDrv_GetWallClk();
+ dvfs_13m_tick = DRV_Reg32(AP_DVFS_OCCUR_TICK);
+#endif
+ curr_frc = ust_get_current_time();
+
+ //SET_ELM_RW_LAT_FLAG(REG_MCUSYS_EMI_ELM_ELM_INT_STATUS, &lat_flag, &r_flag);
+ int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS); //Read ELM interrupt status
+
+
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL));
+ read_total_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL));
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL));
+ write_total_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL));
+ read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_alat_maxost = DRV_Reg32(REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_alat_maxost = DRV_Reg32(REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+
+ infra_elm_runtime_lat_history_idx++;
+
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_AP_DVFS_WARN(curr_frc, ia_13m_tick, dvfs_13m_tick),);
+
+ switch(INFRA_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+#ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l"
+ MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count, int_status);
+ }
+ else
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l"
+ MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count, int_status);
+ }
+#endif
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ /* Handling word count interrupt */
+ else
+ {
+ /* do nothing */
+ read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
+
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ infra_elm_runtime_wc_history_idx++;
+
+ switch(INFRA_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, read_worst_wc, elm_infra_read_wc_threshold), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, write_worst_wc, elm_infra_write_wc_threshold), \
+ );
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+}
+
+/* Lightweight version for AMIF using in dormant backup/restore */
+void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_dur_100us = (kal_uint32)(dur_us/100);
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_DISABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ /* Set AO_ELM_EN bit should be last step. */
+ DRV_SetReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
+ {
+ kal_uint32 lr = 0;
+ kal_uint32 sub_error_code = 0;
+ GET_RETURN_ADDRESS(lr);
+ if(read_avg_lat_ns<200)
+ {
+ sub_error_code = 1;
+ }
+ else if(write_avg_lat_ns<200)
+ {
+ sub_error_code = 2;
+ }
+ else
+ {
+ sub_error_code = 3;
+ }
+ EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
+ }
+
+
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_dur_100us = (kal_uint32)(dur_us/100);
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+#ifdef __ELM_TRACE__
+ {
+ // L1 trace
+ kal_uint32 curr_frc = 0;
+ curr_frc = ust_get_current_time();
+ MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
+ MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
+ }
+#endif
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+void _ELM_exception_saved(void)
+{
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+
+kal_uint8 _ELM_latency_status(void)
+{
+#if 1//def __ELM_RUNTIME_PROFILE__
+
+ //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
+ if(emi_elm_runtime_lat_history_idx != 0)
+ {
+ kal_uint32 int_status = 0;
+ int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ return 0xAE; //EMI read latency may be too long
+ }
+ else
+ {
+ return 0xBE; //EMI write latency may be too long
+ }
+ }
+ return 0xDE; // EMI read/write latency are OK.
+#else
+/* under construction !*/
+#endif
+}
+
+/******************************************************************************
+* function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type)
+* description : this function is called when set emi elm read/write latency/wordcount exception type
+* parameter : kal_uint8 exception_type: 0,1,2
+* return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
+{
+ switch (exception_type)
+ {
+ case ELM_NONE:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_NONE;
+ break;
+ }
+
+ case ELM_ASSERT:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
+ break;
+ }
+ default:
+ return KAL_FALSE;
+ break;
+ }
+ return KAL_TRUE;
+}
+
+kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
+{
+ ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
+ ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+ if((info&0xF0))
+ { // infra
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_infra_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_infra_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+ }
+ else
+ { //mdmcu
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ }
+
+
+ return KAL_TRUE;
+}
+
+/******************************************************************************
+* function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+* description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's
+* counter to monitro read or write transaction and master.
+* parameter :
+* kal_uint8 id: 0, 1, 0xFF;
+* -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters.
+* -> 0xFF is used for let all ID monitor same masters.
+* return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if(id == 0) // id 0 (default read), assume id2 use same master as id 0
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = AID(MASTER_MDMCU);
+ elm_id2_mask |= AID(MASTER_MDMCU_MASK);
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+
+ elm_id2_value = AID(MASTER_USIP);
+ elm_id2_mask |= AID(MASTER_USIP_MASK);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id0_rw = ELM_READ;
+ elm_id2_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id0_rw = ELM_WRITE;
+ elm_id2_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1
+ {
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+ if(m_sel==0)
+ {
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id3_value = 0;
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(m_sel==1)
+ {
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id3_value = AID(MASTER_MDMCU);
+ elm_id3_mask |= AID(MASTER_MDMCU_MASK);
+ }
+ else if(m_sel==2)
+ {
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id3_value = AID(MASTER_USIP);
+ elm_id3_mask |= AID(MASTER_USIP_MASK);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id1_rw = ELM_READ;
+ elm_id3_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id1_rw = ELM_WRITE;
+ elm_id3_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+
+ elm_id0_rw = ELM_READ;
+ elm_id1_rw = ELM_WRITE;
+ elm_id2_rw = ELM_RD;
+ elm_id3_rw = ELM_WR;
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id3_value = 0;
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = AID(MASTER_MDMCU);
+ elm_id2_mask |= AID(MASTER_MDMCU_MASK);
+ elm_id3_value = AID(MASTER_MDMCU);
+ elm_id3_mask |= AID(MASTER_MDMCU_MASK);
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id2_value = AID(MASTER_USIP);
+ elm_id2_mask |= AID(MASTER_USIP_MASK);
+ elm_id3_value = AID(MASTER_USIP);
+ elm_id3_mask |= AID(MASTER_USIP_MASK);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if( mode == 0)
+ {
+ elm_mode = ELM_MODE_0;
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ else if( mode == 2)
+ {
+ elm_mode = ELM_MODE_2;
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| \
+ ELM_DURATION(elm_infra_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+
+
+kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 core_th_sel, kal_uint8 port_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ if(id == 0)// id 0
+ {
+ elm_id0_value = 0;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id2_value = 0;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+
+ if(core_th_sel==0x00)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH0);
+ }
+ else if(core_th_sel==0x01)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH1);
+ }
+ else if(core_th_sel==0x10)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH0);
+ }
+ else if(core_th_sel==0x11)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH1);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ // Port select
+ if(port_sel==0x0) // All master
+ {
+ elm_id0_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(port_sel==0x1) // PM port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ }
+ else if(port_sel==0x2) // DC port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ }
+ else if(port_sel==0x3) // DP port all
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ }
+ else if(port_sel==0x4) // DP port cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ }
+ else if(port_sel==0x5) // DP port non-cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 1)// id 1
+ {
+ elm_id1_value = 0;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id3_value = 0;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+
+ if(core_th_sel==0x00)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH0);
+ }
+ else if(core_th_sel==0x01)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH1);
+ }
+ else if(core_th_sel==0x10)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH0);
+ }
+ else if(core_th_sel==0x11)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH1);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ // Port select
+ if(port_sel==0x0) // All master
+ {
+ elm_id1_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(port_sel==0x1) // PM port
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ }
+ else if(port_sel==0x2) // DC port
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ }
+ else if(port_sel==0x3) // DP port all
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ }
+ else if(port_sel==0x4) // DP port cachable
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ }
+ else if(port_sel==0x5) // DP port non-cachable
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 0xFF) // ID 0/1 are the same
+ {
+ elm_id0_value = 0;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id1_value = 0;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id2_value = 0;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id3_value = 0;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+
+ if(core_th_sel==0x00)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH0);
+ }
+ else if(core_th_sel==0x01)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH1);
+ }
+ else if(core_th_sel==0x10)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH0);
+ }
+ else if(core_th_sel==0x11)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH1);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ // Port select
+ if(port_sel==0x0) // All master
+ {
+ elm_id0_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id1_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(port_sel==0x1) // PM port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ }
+ else if(port_sel==0x2) // DC port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ }
+ else if(port_sel==0x3) // DP port all
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ }
+ else if(port_sel==0x4) // DP port cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ }
+ else if(port_sel==0x5) // DP port non-cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rtn == KAL_FALSE)
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+ }
+ else
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_id0_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_id0_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_id1_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_id1_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ if(id == 0)// id 0
+ {
+ elm_id0_mask &= ~(AUSER(AUSER_MASK));
+ elm_id2_mask &= ~(AUSER(AUSER_MASK));
+ if(vpe_sel==0)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE0);
+ elm_id2_value = AUSER(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE1);
+ elm_id2_value = AUSER(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE2);
+ elm_id2_value = AUSER(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE3);
+ elm_id2_value = AUSER(ELM_SEL_VPE3);
+ }
+ else if(vpe_sel==4)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE4);
+ elm_id2_value = AUSER(ELM_SEL_VPE4);
+ }
+ else if(vpe_sel==5)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE5);
+ elm_id2_value = AUSER(ELM_SEL_VPE5);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 1) // id 1 (default write)
+ {
+ elm_id1_mask &= ~(AUSER(AUSER_MASK));
+ elm_id3_mask &= ~(AUSER(AUSER_MASK));
+ if(vpe_sel==0)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE0);
+ elm_id3_value = AUSER(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE1);
+ elm_id3_value = AUSER(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE2);
+ elm_id3_value = AUSER(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE3);
+ elm_id3_value = AUSER(ELM_SEL_VPE3);
+ }
+ else if(vpe_sel==4)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE4);
+ elm_id3_value = AUSER(ELM_SEL_VPE4);
+ }
+ else if(vpe_sel==5)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE5);
+ elm_id3_value = AUSER(ELM_SEL_VPE5);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(id == 0xFF)// ID 0/1 are the same
+ {
+ elm_id0_mask &= ~(AUSER(AUSER_MASK));
+ elm_id1_mask &= ~(AUSER(AUSER_MASK));
+ elm_id2_mask &= ~(AUSER(AUSER_MASK));
+ elm_id3_mask &= ~(AUSER(AUSER_MASK));
+ if(vpe_sel==0)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE0);
+ elm_id1_value = AUSER(ELM_SEL_VPE0);
+ elm_id2_value = AUSER(ELM_SEL_VPE0);
+ elm_id3_value = AUSER(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE1);
+ elm_id1_value = AUSER(ELM_SEL_VPE1);
+ elm_id2_value = AUSER(ELM_SEL_VPE1);
+ elm_id3_value = AUSER(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE2);
+ elm_id1_value = AUSER(ELM_SEL_VPE2);
+ elm_id2_value = AUSER(ELM_SEL_VPE2);
+ elm_id3_value = AUSER(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE3);
+ elm_id1_value = AUSER(ELM_SEL_VPE3);
+ elm_id2_value = AUSER(ELM_SEL_VPE3);
+ elm_id3_value = AUSER(ELM_SEL_VPE3);
+ }
+ else if(vpe_sel==4)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE4);
+ elm_id1_value = AUSER(ELM_SEL_VPE4);
+ elm_id2_value = AUSER(ELM_SEL_VPE4);
+ elm_id3_value = AUSER(ELM_SEL_VPE4);
+ }
+ else if(vpe_sel==5)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE5);
+ elm_id1_value = AUSER(ELM_SEL_VPE5);
+ elm_id2_value = AUSER(ELM_SEL_VPE5);
+ elm_id3_value = AUSER(ELM_SEL_VPE5);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rtn == KAL_FALSE)
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+ }
+ else
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_id0_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_id0_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_id1_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_id1_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+kal_bool ELM_INFRA_set_master(kal_uint8 id, kal_uint8 m_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ return rtn;
+}
+#endif
diff --git a/mcu/driver/devdrv/elm/src/md95/elm_trace_utmd.json b/mcu/driver/devdrv/elm/src/md95/elm_trace_utmd.json
new file mode 100644
index 0000000..24726c7
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md95/elm_trace_utmd.json
@@ -0,0 +1,116 @@
+{
+ "endGen": "Legacy",
+ "legacyParameters": {
+ "modemType": "elm"
+ },
+ "module": "ELM",
+ "startGen": "Legacy",
+ "stringTranslationDefs": [],
+ "traceClassDefs": [
+ {
+ "ELM_Basic_Info_H": {
+ "_comment": "filterDefaulValue is used in xl1sim, will be phased out later",
+ "debugLevel": "High",
+ "filterDefaultValue": "ON",
+ "tag": [
+ "Basic_Info"
+ ],
+ "traceType": "CoreDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "EMI_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Read Latency Threshold] US_CNT %ul us, R_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Write Latency Threshold] US_CNT %ul us, W_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Read Latency Threshold] US_CNT %ul us, R_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Write Latency Threshold] US_CNT %ul us, W_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT %ul us, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Latency Violation] US_CNT %ul us, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, w_tran %ul, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Read Latency Violation] US_CNT %ul us, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul, int_status %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Write Latency Violation] US_CNT %ul us, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, W_tran %ul, int_status %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_R_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Bandwidth Violation] US_CNT %ul us, R_BW %ul, R_BW_Threhsold %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Bandwidth Violation] US_CNT %ul us, W_BW %ul, W_BW_Threhsold %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_R_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Read Bandwidth Violation] US_CNT %ul us, R_BW %ul, R_BW_Threhsold %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_W_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Write Bandwidth Violation] US_CNT %ul us, W_BW %ul, W_BW_Threhsold %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_AP_DVFS_WARN": {
+ "format": "[WARN][ELM][EMI][Vcore DVFS] US_CNT %ul us, MD systick %ul T, Vcore DVFS %ul T",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ }
+ ],
+ "traceFamily": "L1"
+}
\ No newline at end of file
diff --git a/mcu/driver/devdrv/elm/src/md97/elm.c b/mcu/driver/devdrv/elm/src/md97/elm.c
new file mode 100644
index 0000000..a9a08d5
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md97/elm.c
@@ -0,0 +1,2205 @@
+#include "elm.h"
+#include "drv_comm.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "drv_mdap_interface.h" //for show MD_DVFS_CON in trace
+#include "spv_service.h" // for __SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION__
+#include <math.h>
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+// for profiling ELM log
+#include "TrcMod.h" //for L1 Trace API
+#endif
+
+#if defined(__ELM_MD97__) && !defined(MT6297)
+#define ID2_SET_TO_RW
+kal_bool id2_rw_enable = KAL_TRUE;
+#else
+kal_bool id2_rw_enable = KAL_FALSE;
+#endif
+
+static kal_bool emi_elm_urgent_enable = KAL_TRUE ;
+
+/** ----- Register definition ------ **/
+
+
+// MDMCU ELM
+#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
+#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
+#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
+ #define ELM_MODE(x) ((x)<<4)
+ #define ELM_MODE_MASK 0x3
+ #define ELM_AO_DECODE(x) ((x)<<13)
+ #define ELM_DECODE_FROM_AO 1
+ #define ELM_DECODE_FROM_APB 0
+ #define ELM_MODE_ID_SEL(x) (x<<8)
+ #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only
+ #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3
+ #define ELM_TOTAL_LAT_WEIGHT_BLOCK(x) (x<<20) //[22:20]
+#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
+
+ #define ALEN(x) ((x)<<28) //4'hf
+ #define ASIZE(x) ((x)<<24) //3'h7
+ #define AULTRA(x) ((x)<<20) //2'h3
+ #define ABUST(x) ((x)<<16) //2'h3
+ #define AID(x) ((x)<<0) //12'h1FFF
+ #define MASTER_DEFAULT_MASK 0x1FFF //defualt value
+ #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2
+ #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU)
+ #define MASTER_MDMCU_MASK 0x1FFD
+ #define MASTER_USIP 0x2 //USIP -> 0x2
+ #define MASTER_USIP_MASK 0x1FFC
+ #define MASTER_MCORE 0x3
+ #define MASTER_MCORE_MASK 0x1FFC
+
+
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
+#define ELM_AO_CONTROL_DEFAULT 0xF7331FFF
+
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
+#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
+#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
+#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
+#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
+#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
+#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
+
+#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700)
+#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704)
+#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70C)
+#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710)
+#define REG_MCUSYS_EMI_ELM_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718)
+
+
+
+
+
+ #define INT_MASK_ALL 0x3F
+ #define INT_MASK_LAT 0xF
+ #define INT_MASK_LAT_TOT 0xA
+ #define INT_MASK_LAT_AVG 0x5
+ #define INT_MASK_WC 0x30
+ #define ID0_AVG_LAT_INT (1<<0)
+ #define ID0_TOT_LAT_INT (1<<1)
+ #define ID1_AVG_LAT_INT (1<<2)
+ #define ID1_TOT_LAT_INT (1<<3)
+ #define ID2_TOT_WC_INT (1<<4)
+ #define ID3_TOT_WC_INT (1<<5)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
+ #define DECODE_ID0(x) ((x)<<0)
+ #define ELM_READ (0<<4)
+ #define ELM_WRITE (1<<4)
+ #define ELM_ALL_MASTER (0<<2)
+ #define ELM_MDMCU_ONLY (1<<2)
+ #define ELM_USIP_ONLY (2<<2)
+ #define ELM_ALL_PRIO (0<<0)
+ #define ELM_PRE_ULTRA (1<<0)
+ #define ELM_ULTRA (2<<0)
+ #define LAT_TH_ID0_NORMAL(x) ((x)<<5)
+ #define LAT_TH_ID1_NORMAL(x) ((x)<<15)
+ #define ELM_ACCURACY(x) ((x)<<29)
+ #define ELM_unit_25us 2
+ #define ELM_unit_100us 4
+ #define ELM_ENABLE (1<<27)
+ #define ELM_DISABLE (0<<27)
+ #define ELM_IDLE_ENABLE (1<<28)
+ #define ELM_IDLE_DISABLE (0<<28)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
+ #define ELM_INT_MASK(x) ((x)<<0)
+ #define LAT_INT_MASK_ALL 0xF
+ #define LAT_INT_UNMASK_ALL 0x0
+ #define EMI_BLOCK(x) ((x)<<4)
+ #define E_NOT_MASK 0
+ #define E_MASK 1
+ #define ELM_DURATION(x) ((x-1)<<5)
+ #define DECODE_ID1(x) ((x)<<12)
+ /* #define usage same as DECODE_ID0 */
+ #define ELM_EMI_TOP_BLOCK(x) ((x)<<31)
+ #define E_TOP_MASK 1
+ #define E_TOP_NOT_MASK 0
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC)
+#define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0)
+#define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC)
+#define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0)
+#define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0)
+ #define ELM_WC_INT_MASK(x) ((x)<<0)
+ #define WC_INT_MASK_ALL 0x3
+ #define WC_INT_UNMASK_ALL 0x0
+ #define LAT_TH_ID0_BLOCK(x) ((x)<<4)
+ #define LAT_TH_ID1_BLOCK(x) ((x)<<16)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510)
+#define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514)
+#define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528)
+ #define ELM_WC_ACCURACY(x) ((x)<<4) //[31:4]
+ #define ELM_WC_DURATION(x) ((x)<<0) // [3:0]
+ //wc duration length = (WORDCNT_DURATION+1)*(WORDCNT_ACCURACY+1) us
+
+#define REG_MCUSYS_EMI_ELM_INT_FRCVAL (BASE_ADDR_MCUSYS_ELM_EMI+0x530)
+#define REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x534)
+
+#define REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x538)
+#define REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x53C)
+#define REG_MCUSYS_EMI_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x540)
+#define REG_MCUSYS_EMI_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x544)
+
+#define REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x600)
+#define REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x604)
+#define REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x608)
+#define REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x60C)
+#define REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x610)
+#define REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x614)
+#define REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x618)
+#define REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x61C)
+ #define REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL 0x3fff
+
+#define REG_MCUSYS_EMI_ID0_URG_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700)
+#define REG_MCUSYS_EMI_ID0_URG_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704)
+#define REG_MCUSYS_EMI_ID0_URG_CTRL2 (BASE_ADDR_MCUSYS_ELM_EMI+0x708)
+#define REG_MCUSYS_EMI_ID1_URG_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70c)
+#define REG_MCUSYS_EMI_ID1_URG_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710)
+#define REG_MCUSYS_EMI_ID1_URG_CTRL2 (BASE_ADDR_MCUSYS_ELM_EMI+0x714)
+#define REG_MCUSYS_EMI_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718)
+
+
+// MDINFRA ELM_A
+#define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
+#define REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x30)
+#define REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x34)
+#define REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x38)
+#define REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x3C)
+#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70)
+#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74)
+#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78)
+#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C)
+#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80)
+#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84)
+#define REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x88)
+#define REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x8C)
+
+#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x90)
+#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x94)
+#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x98)
+#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x9C)
+#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xA0)
+#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xA4)
+#define REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xA8)
+#define REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xAC)
+
+#define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0)
+#define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4)
+#define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
+#define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
+#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510)
+#define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514)
+#define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528)
+#define REG_MDINFRA_ELM_INT_FRCVAL (BASE_ADDR_MDINFRA_ELM+0x530)
+
+#define REG_MDINFRA_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x538)
+#define REG_MDINFRA_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x53C)
+#define REG_MDINFRA_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x540)
+#define REG_MDINFRA_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x544)
+
+
+//AO Register in MDPERIMISC
+#define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
+#define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
+#define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090
+#define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
+#define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
+#define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094
+
+/** ----- AP debugging register definition ------ **/
+#if defined(__MD97__) && !defined(MT6297)
+
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level
+#define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48)
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xAE4) // last dvfsrc level
+// SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project
+#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x780)
+#define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x784)
+//#define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4)
+
+#else // Apollo
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level
+#define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48)
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xB08) // last dvfsrc level
+
+// SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project
+#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x630)
+#define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x634)
+//#define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4)
+#endif
+
+#define AP_VCORE_MD_SCEN (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x700)
+#define AP_VCORE_MD_HRT_REQ (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x70C)
+#define AP_VCORE_TOT_HRT_REQ (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x710)
+
+
+#include "sleepdrv_interface.h"
+
+// ELM Set Mode (HW/SW Mode)
+enum {
+ ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt
+ ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA
+};
+
+// (MT6297) MCUSYS/MDINFRA fixed clock 208Mhz, 1T ~ 4.8ns ; (97 others) MCUSYS fixed clock 650/3 Mhz, 1T ~ 4.6ns
+#if defined(MT6297)
+#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
+#define ELM_NS2TRAN(X) ((((X)*208)/1000))
+#define ELM_MDINFRA_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
+#define ELM_MDINFRA_NS2TRAN(X) ((((X)*208)/1000))
+
+#else
+#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4))
+#define ELM_NS2TRAN(X) ((((X)*(650/3))/1000))
+#define ELM_MDINFRA_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4))
+#define ELM_MDINFRA_NS2TRAN(X) ((((X)*(650/3))/1000))
+
+#endif
+
+
+
+typedef enum {
+ E_ELM_WC_B = 0,
+ E_ELM_WC_KB = 1,
+ E_ELM_WC_MB = 2,
+ E_ELM_WC_GB = 3,
+} ELM_WC_UNIT;
+//XB, X can be K(KB), M(MB), G(GB), using ELM_WC_UNIT to represent it.
+#define ELM_XB2WC(X, unit) (X<<(10*unit))>>2
+#define ELM_WC2XB(X, unit) ((X<<2)>>(10*unit))
+
+//for assert information
+#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
+#define KAL_ERROR_INFRA_ELM_EXCEP 0x4102
+
+#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ #define __ELM_TRACE__
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
+#endif
+
+#define ELM_2ND_ASSERT_CHECK_DURATION 300
+
+#ifdef __MTK_TARGET__
+
+const kal_uint16 ELM_ACCURACY_TBL[] = {8,12,25,62,100,125,625,1000};
+
+#define ELM_WINDOW_COUNT 3
+const kal_uint32 ELM_WORD_CNT_WINDOW_TABLE[ELM_WINDOW_COUNT] = {200, 1000, 10000};
+// trace of BW warning threshold depends on ESL result: r+w 200us 1.6GB/s (5x)
+// 1ms: 3x, 10ms: 2x
+const kal_uint32 MDMCU_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[ELM_WINDOW_COUNT] = {320, 960, 6400};
+const kal_uint32 MDINFRA_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[ELM_WINDOW_COUNT] = {320, 960, 6400};
+kal_uint32 elm_mdmcu_window_select_idx = 0;
+kal_uint32 elm_mdinfra_window_select_idx = 0;
+
+static kal_uint32 current_elm_mdinfra_axid_sel_idx=0;
+kal_uint32 elm_mdinfra_axid_sel_idx = 0;
+#define M4_ELM_AXID_GRP_IDX 9
+kal_uint32 const m4_elm_axid_grp[M4_ELM_AXID_GRP_IDX*2] = { 0,0xf73307ff,//All
+ 0,0xf733003f,//NRL2
+ 0x100,0xf7330007,//RXDBRP_NR
+ 0x200,0xF733007F,//MCORE
+ 0x300,0xF733007F,//DFESYS
+ 0x200,0xf7330007,//bigram
+ 0x500,0xF733001F,//BRP0
+ 0x600,0xF733003b,//log_top
+ 0x604,0xF73300fb //trace_top,pppha,ipsec,gdma,dbgsys
+ };
+
+
+
+#ifdef ELM_AMIF_ENABLE
+kal_uint32 elm_read_lat_threshold = 2000;
+kal_uint32 elm_write_lat_threshold = 2000;
+#else
+kal_uint32 elm_read_lat_threshold = 450;
+kal_uint32 elm_write_lat_threshold = 300;
+#endif
+
+kal_uint8 emi_blocking_weight = 7;
+kal_uint32 elm_write_lat_2nd_threshold = 550;
+
+ELM_WC_UNIT elm_read_wc_unit = E_ELM_WC_KB;
+ELM_WC_UNIT elm_write_wc_unit = E_ELM_WC_KB;
+kal_uint32 elm_read_wc_threshold = 320;
+kal_uint32 elm_write_wc_threshold = 320;
+kal_uint32 elm_wc_dur_in_us = 200; // 200us
+
+kal_uint32 elm_infra_read_lat_threshold = 2000;
+kal_uint32 elm_infra_write_lat_threshold = 2000;
+ELM_WC_UNIT elm_infra_read_wc_unit = E_ELM_WC_KB;
+ELM_WC_UNIT elm_infra_write_wc_unit = E_ELM_WC_KB;
+kal_uint32 elm_infra_read_wc_threshold = 320;
+kal_uint32 elm_infra_write_wc_threshold = 320;
+kal_uint32 elm_infra_wc_dur_in_us = 200;
+
+kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
+kal_uint32 elm_lat_accuracy = ELM_unit_25us ;
+kal_uint32 elm_lat_duration = 200;
+kal_uint32 elm_infra_lat_accuracy = ELM_unit_100us ;
+kal_uint32 elm_infra_lat_duration = 1000;
+kal_uint32 elm_trans_threshold = 100;
+kal_uint32 elm_mode = ELM_MODE_0;
+kal_uint32 elm_id2_rw = ELM_RD;
+kal_uint32 elm_id3_rw = ELM_WR;
+kal_uint32 elm_id0_master = ELM_ALL_MASTER;
+kal_uint32 elm_id0_rw = ELM_READ;
+kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
+
+kal_uint32 elm_id1_master = ELM_ALL_MASTER;
+kal_uint32 elm_id1_rw = ELM_WRITE;
+kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
+
+kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_id0_value = 5;
+kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id1_value = 5;
+kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+
+// ID2/3 cnt default value target all transaction
+kal_uint32 elm_id2_value = 0;
+kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id3_value = 0;
+kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+
+
+#if defined(__PRODUCTION_RELEASE__)
+elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
+elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace
+elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace
+elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*--- ELM history variable ---*/
+#define ELM_RUNTIME_HISTORY_SIZE 8
+
+//EMI ELM
+kal_uint32 emi_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 emi_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+//INFRA_A ELM
+kal_uint32 infra_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 infra_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+#if defined(MT6297)
+//INFRA_B ELM
+kal_uint32 infra_b_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T infra_b_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 infra_b_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T infra_b_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+#endif
+
+
+void elmtop_emi_isr_handler();
+void elm_infra_isr_handler();
+
+void Drv_ELM_Reset_Mdinfra_AXID_MASK()
+{
+ elm_dynamic_lat_threshold_disable = 1;
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG, m4_elm_axid_grp[0]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG, m4_elm_axid_grp[0]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK, m4_elm_axid_grp[1]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK, m4_elm_axid_grp[1]);
+
+ return ;
+}
+
+void Drv_ELM_Toggle(kal_uint8 info)
+{
+ elm_dynamic_lat_threshold_disable = 1;
+ if(info==0){
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }else{
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }
+ return ;
+}
+
+void Drv_ELM_Change_WC_Threshold(kal_uint8 info, kal_uint32 wc)
+{
+ kal_uint32 flag = ((info&0xF0)==0x0) ? 0 : 1;
+ kal_uint32 id23 = ((info&0xF)==0x0) ? 0 : 1;
+
+ elm_dynamic_lat_threshold_disable = 1;
+ if(flag==0)// mdmcu elm
+ {
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ if(id23==0)// id2
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, wc);
+ }
+ else // id3
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, wc);
+ }
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }
+ else// mdinfra elm
+ {
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ if(id23==0)// id2
+ {
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, wc);
+ }
+ else // id3
+ {
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, wc);
+ }
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }
+
+ return;
+}
+
+#define ELM_HISTORY_SIZE 64
+kal_uint32 elm_profile_history_idx_0 = 0;
+ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
+
+void Drv_ELM_Set_ID2_RW(kal_bool flag, kal_bool elm_toggle)
+{
+ if(flag)
+ {
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, 1<<23);
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, 1<<23);
+ }
+ else
+ {
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, 1<<23);
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, 1<<23);
+
+ //disable bigdata trace due to the trace type is determined by option
+ elm_dynamic_lat_threshold_disable = 1 ;
+ }
+
+ if(elm_toggle)
+ {
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }
+}
+
+#define ELM_URGENT_READ_NS 300
+#define ELM_URGENT_WRITE_NS 200
+//the setting is based on sub-window = 25us
+#define ELM_URGENT_TRANS 10
+#define ELM_URGENT_SUBWIN 1
+
+void ELM_urgent_config()
+{
+ //set ID0 CTRL1 RG
+ DRV_WriteReg32(REG_MCUSYS_EMI_ID0_URG_CTRL1,
+ (ELM_NS2TRAN(ELM_URGENT_READ_NS)<<20)|
+ (ELM_URGENT_TRANS<<8)|(0x0<<4)|
+ (ELM_URGENT_SUBWIN<<2)|(1<<0));
+ //set ID1 CTRL1 RG
+ DRV_WriteReg32(REG_MCUSYS_EMI_ID1_URG_CTRL1,
+ (ELM_NS2TRAN(ELM_URGENT_WRITE_NS)<<20)|
+ (ELM_URGENT_TRANS<<8)|(0x0<<4)|
+ (ELM_URGENT_SUBWIN<<2)|(1<<0));
+ //keep urgent function enable when elm irq assert
+ DRV_WriteReg32(REG_MCUSYS_EMI_URG_IDLE_CLR_CTRL, 0x00030001);
+ return ;
+}
+
+void ELM_INIT(void)
+{
+/*MDMCU EMI ELM*/
+ //disable elm
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //clear ELM interrupt
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt
+ //set to mode 0
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode
+ //ID select for ID2/3 (ID0/1 by ao_reg later)
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3)));
+ //set total latency weight for 2nd level detection (set to max-> DISABLE)
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(emi_blocking_weight));
+ //ID0/1 trans count threshold
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config ID2/3 setting (config ID0/1 by ao_reg later)
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+ //set word count threshold to 1.5GB/sec (both read and write)
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit));
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit));
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+ //set ao_reg cfg1 (ID1 config)
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|
+ DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|
+ ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ //set ao_reg cfg2 (threshold when emi blocking, wc int)
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ //subwindow enable; grand total mode
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL, 1);
+
+ //set emi elm urgent
+ if(emi_elm_urgent_enable)
+ {
+ ELM_urgent_config();
+ }
+
+ //set ao_reg cfg0 (ELM enable, ID0 config, threshold when emi normal)
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+#if 0 //IRQ register is done by IRQ centralization
+/* under construction !*/
+/* under construction !*/
+#endif
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+/* MDINFRA_A EMI ELM*/
+ //disable elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //clear ELM interrupt
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL);
+ //set ID mode
+ //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(emi_blocking_weight));
+ //set trans threshold
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config word_cnt window setting
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
+ DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+ // set ao_reg cfg1 (ID1 csetting, duration, irq unmask)
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)|
+ ELM_DURATION(elm_infra_lat_duration/ELM_ACCURACY_TBL[elm_infra_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|
+ ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ // set ao_reg cfg2 (threshold when emi blocking)
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+
+ kal_uint32 tmp_idx = (current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)*2;
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
+
+ // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting)
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_infra_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+#if defined(MT6297)
+/* MDINFRA_B EMI ELM */
+ //disable elm
+ DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);// ao_cfg0
+ //clear ELM interrupt
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x64, INT_MASK_ALL);
+ //set ID mode
+ //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ //set trans threshold
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x40, elm_trans_threshold);
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x44, elm_trans_threshold);
+ // config word_cnt window setting
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x510, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x514, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x528, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+ // set ao_reg cfg1 (ID1 csetting, duration, irq unmask)
+ DRV_WriteReg32(BASE_ADDR_MDPERIMISC+0x584, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|
+ DECODE_ID1(elm_id1_rw|elm_id1_prio)|
+ ELM_DURATION(elm_infra_lat_duration/ELM_ACCURACY_TBL[elm_infra_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ // set ao_reg cfg2 (threshold when emi blocking)
+ DRV_WriteReg32(BASE_ADDR_MDPERIMISC+0x588,
+ LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting)
+ DRV_WriteReg32_NPW(BASE_ADDR_MDPERIMISC+0x580,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_infra_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+#endif
+
+#if 0 //IRQ register is done by ISR centralization
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#ifdef ID2_SET_TO_RW
+ Drv_ELM_Set_ID2_RW(id2_rw_enable, KAL_TRUE);
+#endif
+
+ IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+ return ;
+}
+
+void ELM_Config_DormantLeave(void)
+{
+ kal_uint32 vpe_idx;
+ vpe_idx = kal_get_current_vpe_id();
+ if(0 == vpe_idx)
+ {
+ ELM_INIT();
+ emi_elm_runtime_lat_history_idx =0;
+ memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
+ }
+}
+
+void ELM_Config_DormantEnter(void)
+{
+
+}
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
+{
+ if(NULL==data)
+ {
+ return;
+ }
+
+#ifdef __ELM_RUNTIME_PROFILE__
+ elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
+ ELM_GET_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
+ elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
+ elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
+ memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
+ elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
+#else
+ data->fma_stamp = ust_get_current_time();
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
+ ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
+ ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount));
+#endif
+
+}
+
+kal_uint32 debug_emi_elm_runtime_counter = 0;
+kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
+kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
+
+
+
+#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
+
+kal_uint32 elm_md_dvfs_con = 0;
+kal_uint32 elm_ap_vcore_dvfs_current = 0;
+kal_uint32 elm_ap_vcore_dvfs_target = 0;
+kal_uint32 elm_ap_vcore_dvfs_last = 0;
+kal_uint32 elm_ap_vcore_md_scen = 0;
+kal_uint32 elm_ap_vcore_md_hrt_req = 0;
+kal_uint32 elm_ap_vcore_tot_hrt_req = 0;
+
+void elmtop_emi_isr_handler()
+{
+ kal_uint32 curr_frc = 0, enter_lisr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_worst_ostd_cnt = 0, write_worst_ostd_cnt = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0, ddren_13m_tick = 0;
+ enter_lisr_frc = ust_get_current_time();
+ debug_emi_elm_runtime_counter++;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ //stop ELM
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ curr_frc = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_FRCVAL);
+ int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS);
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+ read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) );
+ write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) );
+ read_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+ kal_uint32 emi_blocking = 0 ;
+ if((int_status & INT_MASK_LAT_AVG) &&
+ read_worst_latency_ns<elm_read_lat_threshold && write_worst_latency_ns<elm_write_lat_threshold)
+ {
+ read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK) );
+ write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK) );
+ read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK);
+ write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK);
+ read_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK);
+ write_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK);
+ emi_blocking = 1;
+ }
+ else if(int_status & INT_MASK_LAT_TOT)
+ {
+ read_trans_count = 0; write_trans_count = 0;
+ read_worst_ostd_cnt = 0; write_worst_ostd_cnt=0;
+ if(read_total_latency_ns<elm_read_lat_threshold*pow(2,emi_blocking_weight) &&
+ write_total_latency_ns<elm_write_lat_threshold*pow(2,emi_blocking_weight))
+ {
+ read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK) );
+ write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK) );
+ emi_blocking = 1;
+ }
+ }
+
+// Read AP side related debugging register
+#if defined(__ELM_MD97__)
+ ia_13m_tick = SleepDrv_GetWallClk(); //AP systimer
+ dvfs_13m_tick = *AP_DVFS_OCCUR_TICK;// last dvfs occur tick
+ ddren_13m_tick = *AP_DDREN_OCCUR_TICK;// last ddren occur tick
+ elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
+ elm_ap_vcore_dvfs_target = *AP_VCORE_DVFS_TARGET;
+ elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
+ elm_ap_vcore_md_scen = *AP_VCORE_MD_SCEN;
+ elm_ap_vcore_md_hrt_req = *AP_VCORE_MD_HRT_REQ;
+ elm_ap_vcore_tot_hrt_req = *AP_VCORE_TOT_HRT_REQ;
+#endif
+
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].enter_lisr_frc= enter_lisr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_ostd_cnt;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_ostd_cnt;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_ddren_tick = ddren_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS);
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS);
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].emi_blocking = emi_blocking;
+ emi_elm_runtime_lat_history_idx++;
+
+ elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg();
+
+ //for meta mode, there is no any l1 hrt check. change to trace mode anyway
+ //for spv usage, check elm_dynamic_lat_threshold_disable==1 to indicate local spv testing
+ if(kal_query_boot_mode()==FACTORY_BOOT && elm_dynamic_lat_threshold_disable==0)
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_NONE;
+ }
+
+ switch(EMI_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ //read latency over criteria
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ //write latency over criteria
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ // just show trace on first time over criteria in 300us
+ if(debug_MDMCU_elm_last_INT_FRC == 0)
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ }
+ else
+ {
+ if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < ELM_2ND_ASSERT_CHECK_DURATION)
+ {
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ //bypass 2nd assertion for write latency violation on swift tool env
+ //the violation latency is about 300~400ns but no any performance issue occurred
+ //bypass the assertion to let SQC stable and analyze offline
+ if(write_worst_latency_ns>=elm_write_lat_2nd_threshold){
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }else{
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ }
+ }
+ else
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
+ dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
+ );
+ }
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ }
+ /* Handling word count interrupt */
+ else
+ {
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ kal_uint32 infra_elm_irq_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS);
+ kal_uint32 infra_elm_id2_worst_wc=0, infra_elm_id3_worst_wc=0;
+
+ //stop infra elm for bigdata
+ if(!(infra_elm_irq_status & INT_MASK_WC))
+ {
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ infra_elm_id2_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
+ infra_elm_id3_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }
+#endif
+ read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
+
+ kal_uint32 R_BW_in_MB = read_worst_wc*4/elm_wc_dur_in_us;
+ kal_uint32 W_BW_in_MB = write_worst_wc*4/elm_wc_dur_in_us;
+
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ emi_elm_runtime_wc_history_idx++;
+
+ //check config mode: assertion or trace
+ switch(EMI_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ if(id2_rw_enable)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_RW_BW_WARN(curr_frc, R_BW_in_MB, elm_read_wc_threshold*1000/elm_wc_dur_in_us, elm_wc_dur_in_us,\
+ infra_elm_id2_worst_wc, infra_elm_id3_worst_wc, W_BW_in_MB), \
+ );
+#if defined(__SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION__)
+ spv_mpb_m3_bw_warn_cb(curr_frc, elm_wc_dur_in_us, R_BW_in_MB);
+#endif
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, R_BW_in_MB, elm_read_wc_threshold*1000/elm_wc_dur_in_us, elm_wc_dur_in_us,\
+ infra_elm_id2_worst_wc, infra_elm_id3_worst_wc), \
+ );
+ }
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, W_BW_in_MB, elm_write_wc_threshold*1000/elm_wc_dur_in_us, elm_wc_dur_in_us,\
+ infra_elm_id2_worst_wc, infra_elm_id3_worst_wc), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ EXT_ASSERT(0, curr_frc, R_BW_in_MB, elm_read_wc_threshold*1000/elm_wc_dur_in_us);
+ }
+ else
+ {
+ EXT_ASSERT(0, curr_frc, W_BW_in_MB, elm_write_wc_threshold*1000/elm_wc_dur_in_us);
+
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL);
+
+ //enable ELM
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ return ;
+
+}
+
+void elm_infra_isr_handler()
+{
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+#if defined(MT6297)
+ kal_uint32 int_status_b = 0;
+#endif
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 read_worst_ostd_cnt = 0, write_worst_ostd_cnt = 0;
+
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELM_DMA_IRQ_CODE);
+
+ //stop elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+#if defined(MT6297)
+ DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
+#endif
+ //curr_frc = ust_get_current_time();
+
+ //read INT status
+ int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS);
+#if defined(MT6297)
+ int_status_b = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x64);
+#endif
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
+ read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+ read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL) );
+ write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL) );
+ read_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+ kal_uint32 emi_blocking = 0;
+ if(int_status&INT_MASK_LAT_AVG &&
+ read_worst_latency_ns<elm_infra_read_lat_threshold && write_worst_latency_ns<elm_infra_write_lat_threshold)
+ {
+ read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK);
+ write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK);
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_BLOCK) );
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_BLOCK) );
+ read_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK);
+ write_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK);
+ emi_blocking = 1;
+ }
+ else if(int_status&INT_MASK_LAT_TOT)
+ {
+ read_trans_count = 0; write_trans_count = 0;
+ read_worst_ostd_cnt = 0; write_worst_ostd_cnt = 0;
+ if(read_total_latency_ns<elm_infra_read_lat_threshold*pow(2,emi_blocking_weight) &&
+ write_total_latency_ns<elm_infra_write_lat_threshold*pow(2,emi_blocking_weight))
+ {
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_BLOCK) );
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_BLOCK) );
+ emi_blocking = 1;
+ }
+ }
+
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_ostd_cnt;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_ostd_cnt;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MDINFRA_ELM_ID0_SUBWINDOW_STS);
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MDINFRA_ELM_ID1_SUBWINDOW_STS);
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].emi_blocking = emi_blocking;
+ infra_elm_runtime_lat_history_idx++;
+
+ switch(INFRA_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+#ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count,
+ read_worst_ostd_cnt, emi_blocking);
+ }
+ else
+ {
+ MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count,
+ write_worst_ostd_cnt, emi_blocking);
+ }
+#endif
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ /* Handling word count interrupt */
+ else if(int_status & INT_MASK_WC)
+ {
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ kal_uint32 mcu_elm_irq_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS);
+ kal_uint32 mcu_elm_id2_worst_wc=0, mcu_elm_id3_worst_wc=0;
+ //stop mcu elm for bigdata
+ if(!(mcu_elm_irq_status & INT_MASK_WC))
+ {
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ mcu_elm_id2_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
+ mcu_elm_id3_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ }
+#endif
+ curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
+ read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
+
+ kal_uint32 R_BW_in_MB = read_worst_wc*4/elm_infra_wc_dur_in_us;
+ kal_uint32 W_BW_in_MB = write_worst_wc*4/elm_infra_wc_dur_in_us;
+
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ infra_elm_runtime_wc_history_idx++;
+
+ switch(INFRA_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ if(id2_rw_enable)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_RW_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us,\
+ mcu_elm_id2_worst_wc, mcu_elm_id3_worst_wc, MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX), W_BW_in_MB),\
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us,\
+ mcu_elm_id2_worst_wc, mcu_elm_id3_worst_wc, MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)), \
+ );
+ }
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, W_BW_in_MB, elm_infra_write_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us,\
+ mcu_elm_id2_worst_wc, mcu_elm_id3_worst_wc, MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ EXT_ASSERT(0, curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us);
+ }
+ else
+ {
+ EXT_ASSERT(0, curr_frc, W_BW_in_MB, elm_infra_write_wc_threshold*1000/elm_infra_wc_dur_in_us);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+#if defined(MT6297)
+ if(int_status_b & INT_MASK_LAT)
+ {
+ curr_frc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x530);
+ read_trans_count = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x80);
+ write_trans_count = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x84);
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x70) );
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x78) );
+ read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x74) );
+ write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x7c) );
+
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status_b;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ infra_b_elm_runtime_lat_history_idx++;
+ switch(INFRA_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+#ifdef __ELM_TRACE__
+ if(int_status_b & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ MD_TRC_INFRA_ELM_B_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count);
+ }
+ else
+ {
+ MD_TRC_INFRA_ELM_B_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count);
+ }
+#endif
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ else if(int_status_b & INT_MASK_WC)
+ {
+ curr_frc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x530);
+ read_worst_wc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0xb0);
+ write_worst_wc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0xb4);
+
+ kal_uint32 R_BW_in_MB = read_worst_wc*4/elm_infra_wc_dur_in_us;
+ kal_uint32 W_BW_in_MB = write_worst_wc*4/elm_infra_wc_dur_in_us;
+
+ infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status_b;
+ infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ infra_b_elm_runtime_wc_history_idx++;
+
+ switch(INFRA_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status_b & ID2_TOT_WC_INT)
+ {
+ if(id2_rw_enable)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_B_RW_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_B_R_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us), \
+ );
+ }
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_B_W_BW_WARN(curr_frc, W_BW_in_MB, elm_infra_write_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ // Read wordcount violation
+ if(int_status_b & ID2_TOT_WC_INT)
+ {
+ EXT_ASSERT(0, curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us);
+ }
+ else
+ {
+ EXT_ASSERT(0, curr_frc, W_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+#endif
+
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear M4_A ELM interrupt
+#if defined(MT6297)
+ DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x64, INT_MASK_ALL); //clear M4_B ELM interrupt
+#endif
+
+ //Enable ELM
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+#if defined(MT6297)
+ DRV_SetReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
+#endif
+
+ IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+}
+
+void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); //disable ELM
+
+ // kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_duration= dur_us;
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ // kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+}
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
+ {
+ kal_uint32 lr = 0;
+ kal_uint32 sub_error_code = 0;
+ GET_RETURN_ADDRESS(lr);
+ if(read_avg_lat_ns<200)
+ {
+ sub_error_code = 1;
+ }
+ else if(write_avg_lat_ns<200)
+ {
+ sub_error_code = 2;
+ }
+ else
+ {
+ sub_error_code = 3;
+ }
+ EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
+ }
+
+
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_duration= dur_us;
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+#ifdef __ELM_TRACE__
+ {
+ // L1 trace
+ kal_uint32 curr_frc = 0;
+ curr_frc = ust_get_current_time();
+ MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
+ MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
+ }
+#endif
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+kal_uint8 _ELM_latency_status(void)
+{
+#ifdef __ELM_RUNTIME_PROFILE__
+
+ //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
+ if(emi_elm_runtime_lat_history_idx != 0)
+ {
+ kal_uint32 int_status = 0;
+ int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ return 0xAE; //EMI read latency may be too long
+ }
+ else
+ {
+ return 0xBE; //EMI write latency may be too long
+ }
+ }
+ return 0xDE; // EMI read/write latency are OK.
+#else
+ return 0xFF; //no ELM info
+#endif
+}
+
+/******************************************************************************
+* function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type)
+* description : this function is called when set emi elm read/write latency/wordcount exception type
+* parameter : kal_uint8 exception_type: 0,1,2
+* return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
+{
+ switch (exception_type)
+ {
+ case ELM_NONE:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_NONE;
+ break;
+ }
+
+ case ELM_ASSERT:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
+ break;
+ }
+ default:
+ return KAL_FALSE;
+ break;
+ }
+ return KAL_TRUE;
+}
+
+kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
+{
+ ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
+ ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+ if((info&0xF0))
+ { // infra
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+#if defined(MT6297)
+ DRV_WriteReg32_NPW(BASE_ADDR_MDINFRA_ELM_B+0x580, ELM_DISABLE);
+#endif
+ if( info & 0x01 )
+ {
+ elm_infra_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_infra_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ //M4_A ELM
+
+ //set block latency threshold
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ //set normal latency threshold to target and enable elm
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+
+#if defined(MT6297)
+ //set block latency threshold
+ DRV_WriteReg32_NPW(BASE_ADDR_MDPERIMISC+0x558,
+ LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ //M4_B ELM
+ DRV_WriteReg32_NPW(BASE_ADDR_MDPERIMISC+0x580,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+#endif
+ }
+ else
+ { //mdmcu
+
+ //Disable before re-configure
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ if( info & 0x01 )
+ {
+ elm_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ //set block latency threshold
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN(elm_read_lat_threshold))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ //set normal latency threshold to target and enable elm
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ }
+
+
+ return KAL_TRUE;
+}
+
+/******************************************************************************
+* function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+* description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's
+* counter to monitro read or write transaction and master.
+* parameter :
+* kal_uint8 id: 0, 1, 0xFF;
+* -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters.
+* -> 0xFF is used for let all ID monitor same masters.
+* return : void
+******************************************************************************/
+
+//!!!! AXID RELATED API !!!!
+kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if(id == 0) // id 0 (default read), assume id2 use same master as id 0
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= MASTER_DEFAULT_MASK;
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = MASTER_MDMCU;
+ elm_id2_mask |= MASTER_MDMCU_MASK;
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+
+ elm_id2_value = MASTER_USIP;
+ elm_id2_mask |= MASTER_USIP_MASK;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id0_rw = ELM_READ;
+ elm_id2_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id0_rw = ELM_WRITE;
+ elm_id2_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1
+ {
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+ if(m_sel==0)
+ {
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id3_value = 0;
+ elm_id3_mask |= MASTER_DEFAULT_MASK;
+ }
+ else if(m_sel==1)
+ {
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id3_value = MASTER_MDMCU;
+ elm_id3_mask |= MASTER_MDMCU_MASK;
+ }
+ else if(m_sel==2)
+ {
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id3_value = MASTER_USIP;
+ elm_id3_mask |= MASTER_USIP_MASK;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id1_rw = ELM_READ;
+ elm_id3_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id1_rw = ELM_WRITE;
+ elm_id3_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+
+ elm_id0_rw = ELM_READ;
+ elm_id1_rw = ELM_WRITE;
+ elm_id2_rw = ELM_RD;
+ elm_id3_rw = ELM_WR;
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+ elm_id1_master = ELM_ALL_MASTER;
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
+
+ elm_id2_value = 0;
+ elm_id2_mask |= MASTER_DEFAULT_MASK;
+ elm_id3_value = 0;
+ elm_id3_mask |= MASTER_DEFAULT_MASK;
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+ elm_id1_master = ELM_MDMCU_ONLY;
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
+
+ elm_id2_value = MASTER_MDMCU;
+ elm_id2_mask |= MASTER_MDMCU_MASK;
+ elm_id3_value = MASTER_MDMCU;
+ elm_id3_mask |= MASTER_MDMCU_MASK;
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+ elm_id1_master = ELM_USIP_ONLY;
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
+
+ elm_id2_value = MASTER_USIP;
+ elm_id2_mask |= MASTER_USIP_MASK;
+ elm_id3_value = MASTER_USIP;
+ elm_id3_mask |= MASTER_USIP_MASK;
+ }
+ else if(m_sel==3)
+ {
+ elm_id2_value = MASTER_MCORE;
+ elm_id2_mask |= MASTER_MCORE_MASK;
+ elm_id3_value = MASTER_MCORE;
+ elm_id3_mask |= MASTER_MCORE_MASK;
+
+ //id0/1 filter do not have mcore option. Use APB mode
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_id3_mask);
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ return rtn;
+}
+
+
+kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable elm
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+#if defined(MT6297)
+ DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
+#endif
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if( mode == 0)
+ {
+ elm_mode = ELM_MODE_0;
+ }
+ else if( mode == 2)
+ {
+ elm_mode = ELM_MODE_2;
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ //mdmcu elm
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ //mdinfra_a elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+#if defined(MT6297)
+ //mdinfra_b elm
+ DRV_ClrReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+#endif
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ //Set mode & enable elm
+ //mdmcu elm
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //mdinfra_a elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //mdinfra_b elm
+#if defined(MT6297)
+ DRV_ClrReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+ DRV_SetReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
+#endif
+ return rtn;
+}
+
+//!!!! AXID RELATED API !!!!
+kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 thread_val, kal_uint8 port_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ kal_uint32 assembled_axid=0, assembled_axid_mask=0; // [13]
+ kal_uint16 usip_core=0, usip_thread=0 ;
+
+ //Disable ELM
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //disable dynamic latency threshold
+ elm_dynamic_lat_threshold_disable = 1;
+ //elm id setting from apb
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
+
+ usip_core = thread_val/2 ;
+ usip_thread = thread_val%2 ;
+
+ if(usip_core==1){
+ assembled_axid |= (1<<1) ;
+ }
+ assembled_axid |= (usip_thread<<4);
+
+ switch(port_sel)
+ {
+ case 0:
+ assembled_axid_mask |= (1<<6) ;
+ break;
+ case 1:
+ assembled_axid |= (1<<3);
+ assembled_axid_mask |= (1<<6) ;
+ break;
+ case 2:
+ assembled_axid |= (1<<0);
+ assembled_axid_mask |= (0x7<<6);
+ break;
+ case 3:
+ assembled_axid |= (1<<0);
+ assembled_axid_mask |= (0x3<<6);
+ break;
+ default: //monitor all ports
+ assembled_axid_mask |= 0x1CD ;
+ break;
+ }
+
+ assembled_axid = (assembled_axid<<2) | 0x2 ;
+ assembled_axid_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_DEFAULT_MASK)) | (assembled_axid_mask<<2) ;
+ //config AXID value/mask
+ if(id==0)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, assembled_axid_mask);
+ }
+ else if(id==1)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, assembled_axid_mask);
+ }
+ else if(id==2)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, assembled_axid_mask);
+ }
+ else
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, assembled_axid_mask);
+ }
+
+ //Enable ELM
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ return rtn;
+}
+
+//!!!! SIDEBAND RELATED API !!!!
+kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ kal_uint32 sideband_val = 0 ;
+ //Disable ELM
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //disable dynamic latency threshold
+ elm_dynamic_lat_threshold_disable = 1;
+ //elm id setting from apb
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
+
+ //calculate vpe sideband value
+ if(vpe_sel >= SYS_MCU_NUM_VPE)
+ {
+ return KAL_FALSE ;
+ }
+ else
+ {
+ kal_uint8 core_id= vpe_sel/(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
+ kal_uint8 vpe_id = vpe_sel%(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
+ sideband_val = (core_id<<6) | ((vpe_id+1)<<4) ;
+ }
+
+ //config ID sideband value/mask
+ if(id==0)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, 0);
+ }
+ else if(id==1)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, 0);
+ }
+ else if(id==2)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, 0);
+ }
+ else if(id==3)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, 0);
+ }
+ else
+ { //reset to default
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ }
+
+ //Enable ELM
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ return rtn;
+}
+
+kal_bool Set_EMI_ELM_ID_SIDEBAND(kal_uint16 sideband_val, kal_uint16 sideband_mask)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //disable dynamic latency threshold
+ elm_dynamic_lat_threshold_disable = 1;
+ //elm id setting from apb
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);//REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, sideband_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, sideband_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, sideband_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, sideband_mask);
+
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ return rtn;
+}
+
+void EMI_ELM_GET_MAX_LOG(ELM_MAX_LOG_T *st)
+{
+#if !defined(__MPB_DISABLE__)
+ if(elm_dynamic_lat_threshold_disable==1){
+ return ;
+ }
+
+ st->m3_max_r_word_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
+ st->m3_max_w_word_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
+ st->m4_max_r_word_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
+ st->m4_max_w_word_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
+#if defined(MT6297)
+ st->m4b_max_r_word_cnt = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x80);
+ st->m4b_max_w_word_cnt = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x84);
+#endif
+#endif
+ return;
+}
+#if !defined(__MPB_DISABLE__)
+static kal_uint32 current_elm_mdmcu_window_select_idx=0;
+static kal_uint32 current_elm_mdinfra_window_select_idx=0;
+#endif
+void EMI_ELM_AMIF_SCENARIO_CHANGE_LOGGING(ELM_MAX_LOG_T t)
+{
+#if !defined(__MPB_DISABLE__)
+
+ kal_uint32 int_status;
+ if(elm_dynamic_lat_threshold_disable==1){
+ return ;
+ }
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ kal_uint32 mdmcu_elm_wrost_rlat = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );;
+ kal_uint32 mdmcu_elm_wrost_wlat = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );;
+ kal_uint32 mdinfra_elm_wrost_rlat = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ kal_uint32 mdinfra_elm_wrost_wlat = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+#endif
+
+ //print trace
+#ifdef ID2_SET_TO_RW
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_RW_AMIF_SCEN_CHANGE_LOG(t.m3_max_r_word_cnt, t.m3_max_w_word_cnt, elm_wc_dur_in_us, mdmcu_elm_wrost_rlat,mdmcu_elm_wrost_wlat, elm_lat_duration), \
+ );
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_RW_AMIF_SCEN_CHANGE_LOG(t.m4_max_r_word_cnt, t.m4_max_w_word_cnt, elm_infra_wc_dur_in_us, mdinfra_elm_wrost_rlat, mdinfra_elm_wrost_wlat,MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX), elm_infra_lat_duration), \
+ );
+#endif
+
+#if defined(MT6297)
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_B_ELM_AMIF_SCEN_CHANGE_LOG(t.m4b_max_r_word_cnt, t.m4b_max_w_word_cnt, elm_infra_wc_dur_in_us), \
+ );
+#endif
+
+ //check elm int status to ensure no reset when latency problem happen
+ //toggle elm to reset max value
+ int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS) ;
+ if(int_status == 0)
+ {
+ //disable mdmcu elm
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //change word count window:
+ if(current_elm_mdmcu_window_select_idx != elm_mdmcu_window_select_idx){
+ kal_uint32 tmp_idx = current_elm_mdmcu_window_select_idx%ELM_WINDOW_COUNT;
+ // change elm global variable
+ elm_wc_dur_in_us = ELM_WORD_CNT_WINDOW_TABLE[tmp_idx];
+ elm_read_wc_threshold = MDMCU_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
+ elm_write_wc_threshold = MDMCU_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
+ // change elm register
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit));
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit));
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+
+ current_elm_mdmcu_window_select_idx = elm_mdmcu_window_select_idx ;
+ }
+
+ //enable mdmcu elm
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ //disable infra elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //change word count window
+ if(current_elm_mdinfra_window_select_idx != elm_mdinfra_window_select_idx){
+ kal_uint32 tmp_idx = current_elm_mdinfra_window_select_idx%ELM_WINDOW_COUNT;
+ // change elm global variable
+ elm_infra_wc_dur_in_us = ELM_WORD_CNT_WINDOW_TABLE[tmp_idx];
+ elm_infra_read_wc_threshold = MDINFRA_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
+ elm_infra_write_wc_threshold = MDINFRA_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
+ // change elm register
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
+ DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+
+ current_elm_mdinfra_window_select_idx = elm_mdinfra_window_select_idx ;
+ }
+
+ if(current_elm_mdinfra_axid_sel_idx != elm_mdinfra_axid_sel_idx)
+ {
+ current_elm_mdinfra_axid_sel_idx = elm_mdinfra_axid_sel_idx ;
+ kal_uint32 tmp_idx = (current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)*2;
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
+ DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
+ }
+
+ // enable infra elm
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+#if defined(MT6297)
+ DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
+ DRV_SetReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
+#endif
+ }
+
+#endif
+ return ;
+}
+#endif
diff --git a/mcu/driver/devdrv/elm/src/md97/elm_trace_utmd.json b/mcu/driver/devdrv/elm/src/md97/elm_trace_utmd.json
new file mode 100644
index 0000000..63c71c6
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md97/elm_trace_utmd.json
@@ -0,0 +1,201 @@
+{
+ "endGen": "-",
+ "legacyParameters": {
+ "modemType": "elm"
+ },
+ "module": "ELM",
+ "startGen": "97",
+ "stringTranslationDefs": [
+ {
+ "MDINFRA_ELM_AXID_GRP": [
+ "ALL",
+ "NRL2",
+ "RXDBRP_NR",
+ "MCORE",
+ "DFESYS",
+ "BIGRAM",
+ "BRP0",
+ "log_top",
+ "trace_top,pppha,ipsec,gdma,dbgsys"
+ ]
+ }
+ ],
+ "traceClassDefs": [
+ {
+ "ELM_Basic_Info_H": {
+ "_comment": "filterDefaulValue is used in xl1sim, will be phased out later",
+ "debugLevel": "High",
+ "filterDefaultValue": "ON",
+ "tag": [
+ "Basic_Info"
+ ],
+ "traceType": "CoreDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "EMI_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Read Latency Threshold] US_CNT=%ul, R_Threshold=%ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Write Latency Threshold] US_CNT=%ul, W_Threshold=%ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Read Latency Threshold] US_CNT=%ul, R_Threshold=%ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Write Latency Threshold] US_CNT=%ul, W_Threshold=%ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT=%ul, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl, AP_LAST_DVFS_DDREN_1 %xl, AP_LAST_DVFS_DDREN_2 %xl, AP_SYSTICK %xl, emi_blocking %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Latency Violation] US_CNT=%ul, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, w_tran %ul, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl, AP_LAST_DVFS_DDREN_1 %xl, AP_LAST_DVFS_DDREN_2 %xl, AP_SYSTICK %xl, emi_blocking %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_A][Read Latency Violation] US_CNT=%ul, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul, ostd_cnt %ul, emi_blocking %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_A][Write Latency Violation] US_CNT=%ul, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, R_tran %ul, ostd_cnt %ul, emi_blocking %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Read Latency Violation] US_CNT=%ul, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Write Latency Violation] US_CNT=%ul, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, R_tran %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_AP_DVFS_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Vcore DVFS] US_CNT=%ul, MD systick %ul T, Vcore DVFS %ul T",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_RW_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][R+W Bandwidth Violation] US_CNT=%ul, RW_BW=%ul MB/s, BW_Threhsold=%ul MB/s, window=%ul us, infra_id2_worst_wc=%ul, infra_id3_worst_wc=%ul, W_BW=%ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_R_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Bandwidth Violation] US_CNT=%ul, R_BW=%ul MB/s, BW_Threhsold=%ul MB/s, window=%ul us, infra_id2_worst_wc=%ul, infra_id3_worst_wc=%ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Bandwidth Violation] US_CNT=%ul, W_BW=%ul MB/s, BW_Threhsold=%ul MB/s, window=%ul us, infra_id2_worst_wc=%ul, infra_id3_worst_wc=%ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_R_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Read Bandwidth Violation] US_CNT=%ul, R_BW=%ul MB/s, BW_Threhsold=%ul MB/s, window=%ul us, mcu_id2_worst_wc=%ul, mcu_id3_worst_wc=%ul, axid_grp=%s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_RW_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][R+W Bandwidth Violation] US_CNT=%ul, RW_BW=%ul MB/s, BW_Threhsold=%ul MB/s, window=%ul us, mcu_id2_worst_wc=%ul, mcu_id3_worst_wc=%ul, axid_grp=%s, W_BW=%ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_W_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4][Write Bandwidth Violation] US_CNT=%ul, W_BW=%ul MB/s, BW_Threhsold %ul MB/s, window=%ul us, mcu_id2_worst_wc=%ul, mcu_id3_worst_wc=%ul, axid_grp=%s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_RW_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][R+W Bandwidth Violation] US_CNT=%ul, W_BW=%ul MB/s, BW_Threhsold %ul MB/s, window=%ul us",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_R_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Read Bandwidth Violation] US_CNT=%ul, BW=%ul MB/s, BW_Threhsold %ul MB/s, window=%ul us",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_W_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Write Bandwidth Violation] US_CNT=%ul , BW=%ul MB/s, BW_Threhsold %ul MB/s, window=%ul us",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_RW_AMIF_SCEN_CHANGE_LOG": {
+ "format": "[MPB][ELM][AMIF][MDMCU] max r+w word cnt = %ul, max w word cnt = %ul, window = %ul us, id0_worst_avg_lat = %ul, id1_worst_avg_lat = %ul, lat_window = %ul us",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_RW_AMIF_SCEN_CHANGE_LOG": {
+ "format": "[MPB][ELM][AMIF][MDINFRA] max r+w word cnt = %ul, max w word cnt = %ul, window = %ul us, id0_worst_avg_lat = %ul, id1_worst_avg_lat = %ul, axid_grp=%s, lat_window = %ul us",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_B_ELM_AMIF_SCEN_CHANGE_LOG": {
+ "format": "[MPB][ELM][AMIF][MDINFRA_B] max r word cnt = %ul, max w word cnt = %ul, window = %ul us",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ }
+ ],
+ "traceFamily": "L1",
+ "userModule": "elm"
+}
diff --git a/mcu/driver/devdrv/elm/src/md97p/elm.c b/mcu/driver/devdrv/elm/src/md97p/elm.c
new file mode 100644
index 0000000..3a648e3
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md97p/elm.c
@@ -0,0 +1,1486 @@
+#include "elm.h"
+#include "drv_comm.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "drv_mdap_interface.h" //for show MD_DVFS_CON in trace
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+// for profiling ELM log
+#include "TrcMod.h" //for L1 Trace API
+#endif
+
+/** ----- Register definition ------ **/
+
+
+// MDMCU ELM
+#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
+#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
+#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
+ #define ELM_MODE(x) ((x)<<4)
+ #define ELM_MODE_MASK 0x3
+ #define ELM_AO_DECODE(x) ((x)<<13)
+ #define ELM_DECODE_FROM_AO 1
+ #define ELM_DECODE_FROM_APB 0
+ #define ELM_MODE_ID_SEL(x) (x<<8)
+ #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only
+ #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3
+ #define ELM_TOTAL_LAT_WEIGHT_BLOCK(x) (x<<20) //[22:20]
+#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
+
+ #define ALEN(x) ((x)<<28) //4'hf
+ #define ASIZE(x) ((x)<<24) //3'h7
+ #define AULTRA(x) ((x)<<20) //2'h3
+ #define ABUST(x) ((x)<<16) //2'h3
+ #define AID(x) ((x)<<0) //12'h1FFF
+ #define MASTER_DEFAULT_MASK 0x1FFF //defualt value
+ #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2
+ #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU)
+ #define MASTER_MDMCU_MASK 0x1FFD
+ #define MASTER_USIP 0x2 //USIP -> 0x2
+ #define MASTER_USIP_MASK 0x1FFC
+
+
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
+#define ELM_AO_CONTROL_DEFAULT 0xF7331FFF
+
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
+#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
+#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
+#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
+#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
+#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
+#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
+
+#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700)
+#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704)
+#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70C)
+#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710)
+#define REG_MCUSYS_EMI_ELM_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718)
+
+
+
+
+
+ #define INT_MASK_ALL 0x3F
+ #define INT_MASK_LAT 0xF
+ #define INT_MASK_WC 0x30
+ #define ID0_AVG_LAT_INT (1<<0)
+ #define ID0_TOT_LAT_INT (1<<1)
+ #define ID1_AVG_LAT_INT (1<<2)
+ #define ID1_TOT_LAT_INT (1<<3)
+ #define ID2_TOT_WC_INT (1<<4)
+ #define ID3_TOT_WC_INT (1<<5)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
+ #define DECODE_ID0(x) ((x)<<0)
+ #define ELM_READ (0<<4)
+ #define ELM_WRITE (1<<4)
+ #define ELM_ALL_MASTER (0<<2)
+ #define ELM_MDMCU_ONLY (1<<2)
+ #define ELM_USIP_ONLY (2<<2)
+ #define ELM_ALL_PRIO (0<<0)
+ #define ELM_PRE_ULTRA (1<<0)
+ #define ELM_ULTRA (2<<0)
+ #define LAT_TH_ID0_NORMAL(x) ((x)<<5)
+ #define LAT_TH_ID1_NORMAL(x) ((x)<<15)
+ #define ELM_ACCURACY(x) ((x)<<29)
+ #define ELM_unit_25us 2
+ #define ELM_unit_100us 4
+ #define ELM_ENABLE (1<<27)
+ #define ELM_DISABLE (0<<27)
+ #define ELM_IDLE_ENABLE (1<<28)
+ #define ELM_IDLE_DISABLE (0<<28)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
+ #define ELM_INT_MASK(x) ((x)<<0)
+ #define LAT_INT_MASK_ALL 0xF
+ #define LAT_INT_UNMASK_ALL 0x0
+ #define EMI_BLOCK(x) ((x)<<4)
+ #define E_NOT_MASK 0
+ #define E_MASK 1
+ #define ELM_DURATION(x) ((x-1)<<5)
+ #define DECODE_ID1(x) ((x)<<12)
+ /* #define usage same as DECODE_ID0 */
+ #define ELM_EMI_TOP_BLOCK(x) ((x)<<31)
+ #define E_TOP_MASK 1
+ #define E_TOP_NOT_MASK 0
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC)
+#define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0)
+#define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC)
+#define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0)
+#define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0)
+ #define ELM_WC_INT_MASK(x) ((x)<<0)
+ #define WC_INT_MASK_ALL 0x3
+ #define WC_INT_UNMASK_ALL 0x0
+ #define LAT_TH_ID0_BLOCK(x) ((x)<<4)
+ #define LAT_TH_ID1_BLOCK(x) ((x)<<16)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510)
+#define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514)
+#define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528)
+ #define ELM_WC_ACCURACY(x) ((x)<<4) //[31:4]
+ #define ELM_WC_DURATION(x) ((x)<<0) // [3:0]
+ //wc duration length = (WORDCNT_DURATION+1)*(WORDCNT_ACCURACY+1) us
+
+#define REG_MCUSYS_EMI_ELM_INT_FRCVAL (BASE_ADDR_MCUSYS_ELM_EMI+0x530)
+#define REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x534)
+
+#define REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x538)
+#define REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x53C)
+#define REG_MCUSYS_EMI_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x540)
+#define REG_MCUSYS_EMI_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x544)
+
+#define REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x600)
+#define REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x604)
+#define REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x608)
+#define REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x60C)
+#define REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x610)
+#define REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x614)
+#define REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x618)
+#define REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x61C)
+ #define REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL 0x3fff
+// MDINFRA ELM_A
+#define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
+#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70)
+#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74)
+#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78)
+#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C)
+#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80)
+#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84)
+#define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0)
+#define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4)
+#define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
+#define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
+#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510)
+#define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514)
+#define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528)
+#define REG_MDINFRA_ELM_INT_FRCVAL (BASE_ADDR_MDINFRA_ELM+0x530)
+
+//AO Register in MDPERIMISC
+#define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
+#define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
+#define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090
+#define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
+#define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
+#define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094
+
+/** ----- AP debugging register definition ------ **/
+#if 1 //defined(MT3967)
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level
+#define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48)
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xB08) // last dvfsrc level
+
+// SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project
+#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x630)
+#define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x634)
+#define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4)
+#endif
+
+#include "sleepdrv_interface.h"
+
+// ELM Set Mode (HW/SW Mode)
+enum {
+ ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt
+ ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA
+};
+
+//MCUSYS fixed clock 650/3 Mhz, 1T ~ 4.6ns
+#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4))
+#define ELM_NS2TRAN(X) ((((X)*(650/3))/1000))
+
+
+//MDINFRA fixed clock 100Mhz, 1T = 10ns
+#define ELM_MDINFRA_TRANS2NS(X) (((X)*10))
+#define ELM_MDINFRA_NS2TRAN(X) (((X)/10))
+
+typedef enum {
+ E_ELM_WC_B = 0,
+ E_ELM_WC_KB = 1,
+ E_ELM_WC_MB = 2,
+ E_ELM_WC_GB = 3,
+} ELM_WC_UNIT;
+//XB, X can be K(KB), M(MB), G(GB), using ELM_WC_UNIT to represent it.
+#define ELM_XB2WC(X, unit) (X<<(10*unit))>>2
+#define ELM_WC2XB(X, unit) ((X<<2)>>(10*unit))
+
+//for assert information
+#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
+#define KAL_ERROR_INFRA_ELM_EXCEP 0x4102
+
+#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ #define __ELM_TRACE__
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
+#endif
+
+#define ELM_2ND_ASSERT_CHECK_DURATION 300
+
+#ifdef __MTK_TARGET__
+
+const kal_uint16 ELM_ACCURACY_TBL[] = {8,12,25,62,100,125,625,1000};
+
+#ifdef ELM_AMIF_ENABLE
+kal_uint32 elm_read_lat_threshold = 2000;
+kal_uint32 elm_write_lat_threshold = 2000;
+#else
+kal_uint32 elm_read_lat_threshold = 450;
+kal_uint32 elm_write_lat_threshold = 300;
+#endif
+ELM_WC_UNIT elm_read_wc_unit = E_ELM_WC_KB;
+ELM_WC_UNIT elm_write_wc_unit = E_ELM_WC_KB;
+kal_uint32 elm_read_wc_threshold = 300;
+kal_uint32 elm_write_wc_threshold = 300;
+kal_uint32 elm_wc_dur_in_us = 200;
+
+kal_uint32 elm_infra_read_lat_threshold = 2000;
+kal_uint32 elm_infra_write_lat_threshold = 2000;
+ELM_WC_UNIT elm_infra_read_wc_unit = E_ELM_WC_MB;
+ELM_WC_UNIT elm_infra_write_wc_unit = E_ELM_WC_MB;
+kal_uint32 elm_infra_read_wc_threshold = 15;
+kal_uint32 elm_infra_write_wc_threshold = 15;
+kal_uint32 elm_infra_wc_dur_in_us = 10*1000; // 10ms
+
+kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
+kal_uint32 elm_lat_accuracy = ELM_unit_25us ;
+kal_uint32 elm_lat_duration = 200;
+kal_uint32 elm_trans_threshold = 100;
+kal_uint32 elm_mode = ELM_MODE_0;
+kal_uint32 elm_id2_rw = ELM_RD;
+kal_uint32 elm_id3_rw = ELM_WR;
+kal_uint32 elm_id0_master = ELM_ALL_MASTER;
+kal_uint32 elm_id0_rw = ELM_READ;
+kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
+
+kal_uint32 elm_id1_master = ELM_ALL_MASTER;
+kal_uint32 elm_id1_rw = ELM_WRITE;
+kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
+
+kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_id0_value = 5;
+kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id1_value = 5;
+kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+
+// ID2/3 cnt default value target all transaction
+kal_uint32 elm_id2_value = 0;
+kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id3_value = 0;
+kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+
+
+#if defined(__PRODUCTION_RELEASE__)
+elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
+elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace
+elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace
+elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*--- ELM history variable ---*/
+#define ELM_RUNTIME_HISTORY_SIZE 8
+
+//EMI ELM
+kal_uint32 emi_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 emi_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+//INFRA_A ELM
+kal_uint32 infra_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 infra_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+
+
+
+void elmtop_emi_isr_handler();
+void elm_infra_isr_handler();
+
+
+
+#define ELM_HISTORY_SIZE 64
+kal_uint32 elm_profile_history_idx_0 = 0;
+ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
+
+
+void ELM_INIT(void)
+{
+/*MDMCU EMI ELM*/
+ //disable elm
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ //clear ELM interrupt
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt
+ //set to mode 0
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode
+ //ID select for ID2/3 (ID0/1 by ao_reg later)
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3)));
+ //set total latency weight for 2nd level detection (set to max-> DISABLE)
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(7));
+ //ID0/1 trans count threshold
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config ID2/3 setting (config ID0/1 by ao_reg later)
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+ //set word count threshold to 1.5GB/sec (both read and write)
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit));
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit));
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+ //set ao_reg cfg1 (ID1 config)
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|
+ DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|
+ ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ //set ao_reg cfg2 (threshold when emi blocking, wc int)
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ //subwindow enable; grand total mode
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL, 1);
+ //set ao_reg cfg0 (ELM enable, ID0 config, threshold when emi normal)
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+/* MDINFRA_A EMI ELM*/
+ //disable elm
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ //clear ELM interrupt
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL);
+ //set ID mode
+ //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ //set trans threshold
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config word_cnt window setting
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
+ DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
+ // set ao_reg cfg1 (ID1 csetting, duration, irq unmask)
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|
+ ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ // set ao_reg cfg2 (threshold when emi blocking)
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2,
+ LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))|
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|
+ ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting)
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+
+
+ IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+ return ;
+}
+
+void ELM_Config_DormantLeave(void)
+{
+ kal_uint32 vpe_idx;
+ vpe_idx = kal_get_current_vpe_id();
+ if(0 == vpe_idx)
+ {
+ ELM_INIT();
+ emi_elm_runtime_lat_history_idx =0;
+ memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
+ }
+}
+
+void ELM_Config_DormantEnter(void)
+{
+
+}
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
+{
+ if(NULL==data)
+ {
+ return;
+ }
+
+#ifdef __ELM_RUNTIME_PROFILE__
+ elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
+ ELM_GET_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
+ elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
+ elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
+ memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
+ elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
+#else
+ data->fma_stamp = ust_get_current_time();
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
+ ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
+ ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount));
+#endif
+
+}
+
+kal_uint32 debug_emi_elm_runtime_counter = 0;
+kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
+kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
+
+
+
+#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
+
+kal_uint32 elm_md_dvfs_con = 0;
+kal_uint32 elm_ap_vcore_dvfs_current = 0;
+kal_uint32 elm_ap_vcore_dvfs_target = 0;
+kal_uint32 elm_ap_vcore_dvfs_last = 0;
+
+void elmtop_emi_isr_handler()
+{
+ kal_uint32 curr_frc = 0, enter_lisr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0, ddren_13m_tick = 0;
+ enter_lisr_frc = ust_get_current_time();
+ debug_emi_elm_runtime_counter++;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ //stop ELM
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ curr_frc = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_FRCVAL);
+ int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS);
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+ read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) );
+ write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) );
+ read_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+// Read AP side related debugging register
+#if 1
+ ia_13m_tick = *AP_SYSTIMER_TICK; //AP systimer
+ dvfs_13m_tick = *AP_DVFS_OCCUR_TICK;// last dvfs occur tick
+ ddren_13m_tick = *AP_DDREN_OCCUR_TICK;// last ddren occur tick
+ elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
+ elm_ap_vcore_dvfs_target = *AP_VCORE_DVFS_TARGET;
+ elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
+#endif
+
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].enter_lisr_frc= enter_lisr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_ddren_tick = ddren_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS);
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS);
+ emi_elm_runtime_lat_history_idx++;
+
+ elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg();
+
+ switch(EMI_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ //read latency over criteria
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ //write latency over criteria
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ // just show trace on first time over criteria in 300us
+ if(debug_MDMCU_elm_last_INT_FRC == 0)
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ }
+ else
+ {
+ if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < ELM_2ND_ASSERT_CHECK_DURATION)
+ {
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
+ }
+ }
+ else
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ }
+ /* Handling word count interrupt */
+ else
+ {
+ read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
+
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ emi_elm_runtime_wc_history_idx++;
+
+ //check config mode: assertion or trace
+ switch(EMI_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, ELM_WC2XB(read_worst_wc, elm_read_wc_unit), ELM_WC2XB(elm_read_wc_threshold, elm_read_wc_unit), ELM_WC_UNIT_STRING(elm_read_wc_unit)), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, ELM_WC2XB(write_worst_wc, elm_write_wc_unit), ELM_WC2XB(elm_write_wc_threshold, elm_write_wc_unit), ELM_WC_UNIT_STRING(elm_write_wc_unit)), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ EXT_ASSERT(0, ELM_WC2XB(read_worst_wc, elm_read_wc_unit), elm_read_wc_unit, 0);
+ }
+ else
+ {
+ EXT_ASSERT(0, ELM_WC2XB(write_worst_wc, elm_write_wc_unit), elm_write_wc_unit, 0);
+
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL);
+
+ //enable ELM
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ return ;
+
+}
+
+void elm_infra_isr_handler()
+{
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELM_DMA_IRQ_CODE);
+
+ //stop elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ //curr_frc = ust_get_current_time();
+
+ //read INT status
+ int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS);
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
+ read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+ read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL) );
+ write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL) );
+
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ infra_elm_runtime_lat_history_idx++;
+
+ switch(INFRA_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+#ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count);
+ }
+ else
+ {
+ MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count);
+ }
+#endif
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ /* Handling word count interrupt */
+ else if(int_status & INT_MASK_WC)
+ {
+ curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
+ read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
+
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ infra_elm_runtime_wc_history_idx++;
+
+ switch(INFRA_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, ELM_WC2XB(read_worst_wc, elm_infra_read_wc_unit), ELM_WC2XB(elm_infra_read_wc_threshold, elm_infra_read_wc_unit), ELM_WC_UNIT_STRING(elm_infra_read_wc_unit)), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, ELM_WC2XB(write_worst_wc, elm_infra_write_wc_unit), ELM_WC2XB(elm_infra_write_wc_threshold, elm_infra_write_wc_unit), ELM_WC_UNIT_STRING(elm_infra_write_wc_unit)), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ EXT_ASSERT(0, ELM_WC2XB(read_worst_wc, elm_infra_read_wc_unit), elm_infra_read_wc_unit, 0);
+ }
+ else
+ {
+ EXT_ASSERT(0, ELM_WC2XB(write_worst_wc, elm_infra_write_wc_unit), elm_infra_write_wc_unit, 0);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear M4_A ELM interrupt
+
+ //Enable ELM
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+}
+
+void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
+
+ // kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_duration= dur_us;
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ // kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+}
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
+ {
+ kal_uint32 lr = 0;
+ kal_uint32 sub_error_code = 0;
+ GET_RETURN_ADDRESS(lr);
+ if(read_avg_lat_ns<200)
+ {
+ sub_error_code = 1;
+ }
+ else if(write_avg_lat_ns<200)
+ {
+ sub_error_code = 2;
+ }
+ else
+ {
+ sub_error_code = 3;
+ }
+ EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
+ }
+
+
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_duration= dur_us;
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+#ifdef __ELM_TRACE__
+ {
+ // L1 trace
+ kal_uint32 curr_frc = 0;
+ curr_frc = ust_get_current_time();
+ MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
+ MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
+ }
+#endif
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+kal_uint8 _ELM_latency_status(void)
+{
+#ifdef __ELM_RUNTIME_PROFILE__
+
+ //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
+ if(emi_elm_runtime_lat_history_idx != 0)
+ {
+ kal_uint32 int_status = 0;
+ int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ return 0xAE; //EMI read latency may be too long
+ }
+ else
+ {
+ return 0xBE; //EMI write latency may be too long
+ }
+ }
+ return 0xDE; // EMI read/write latency are OK.
+#else
+ return 0xFF; //no ELM info
+#endif
+}
+
+/******************************************************************************
+* function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type)
+* description : this function is called when set emi elm read/write latency/wordcount exception type
+* parameter : kal_uint8 exception_type: 0,1,2
+* return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
+{
+ switch (exception_type)
+ {
+ case ELM_NONE:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_NONE;
+ break;
+ }
+
+ case ELM_ASSERT:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
+ break;
+ }
+ default:
+ return KAL_FALSE;
+ break;
+ }
+ return KAL_TRUE;
+}
+
+kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
+{
+ ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
+ ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+ if((info&0xF0))
+ { // infra
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+
+ if( info & 0x01 )
+ {
+ elm_infra_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_infra_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ //M4_A ELM
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+ }
+ else
+ { //mdmcu
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ }
+
+
+ return KAL_TRUE;
+}
+
+/******************************************************************************
+* function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+* description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's
+* counter to monitro read or write transaction and master.
+* parameter :
+* kal_uint8 id: 0, 1, 0xFF;
+* -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters.
+* -> 0xFF is used for let all ID monitor same masters.
+* return : void
+******************************************************************************/
+
+//!!!! AXID RELATED API !!!!
+kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if(id == 0) // id 0 (default read), assume id2 use same master as id 0
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= MASTER_DEFAULT_MASK;
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = MASTER_MDMCU;
+ elm_id2_mask |= MASTER_MDMCU_MASK;
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+
+ elm_id2_value = MASTER_USIP;
+ elm_id2_mask |= MASTER_USIP_MASK;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id0_rw = ELM_READ;
+ elm_id2_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id0_rw = ELM_WRITE;
+ elm_id2_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1
+ {
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+ if(m_sel==0)
+ {
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id3_value = 0;
+ elm_id3_mask |= MASTER_DEFAULT_MASK;
+ }
+ else if(m_sel==1)
+ {
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id3_value = MASTER_MDMCU;
+ elm_id3_mask |= MASTER_MDMCU_MASK;
+ }
+ else if(m_sel==2)
+ {
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id3_value = MASTER_USIP;
+ elm_id3_mask |= MASTER_USIP_MASK;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id1_rw = ELM_READ;
+ elm_id3_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id1_rw = ELM_WRITE;
+ elm_id3_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
+
+ elm_id0_rw = ELM_READ;
+ elm_id1_rw = ELM_WRITE;
+ elm_id2_rw = ELM_RD;
+ elm_id3_rw = ELM_WR;
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= MASTER_DEFAULT_MASK;
+ elm_id3_value = 0;
+ elm_id3_mask |= MASTER_DEFAULT_MASK;
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = MASTER_MDMCU;
+ elm_id2_mask |= MASTER_MDMCU_MASK;
+ elm_id3_value = MASTER_MDMCU;
+ elm_id3_mask |= MASTER_MDMCU_MASK;
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id2_value = MASTER_USIP;
+ elm_id2_mask |= MASTER_USIP_MASK;
+ elm_id3_value = MASTER_USIP;
+ elm_id3_mask |= MASTER_USIP_MASK;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
+ ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
+ ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
+ EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
+ ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
+ LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ return rtn;
+}
+
+
+kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable elm
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if( mode == 0)
+ {
+ elm_mode = ELM_MODE_0;
+ }
+ else if( mode == 2)
+ {
+ elm_mode = ELM_MODE_2;
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ //mdmcu elm
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ //mdinfra_a elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ //Set mode & enable elm
+ //mdmcu elm
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //mdinfra_a elm
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+ DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ return rtn;
+}
+
+//!!!! AXID RELATED API !!!!
+kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 thread_val, kal_uint8 port_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ kal_uint32 assembled_axid=0, assembled_axid_mask=0; // [13]
+ kal_uint16 usip_core=0, usip_thread=0 ;
+
+ //Disable ELM
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //disable dynamic latency threshold
+ elm_dynamic_lat_threshold_disable = 1;
+ //elm id setting from apb
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
+
+ usip_core = thread_val/2 ;
+ usip_thread = thread_val%2 ;
+
+ if(usip_core==1){
+ assembled_axid |= (1<<1) ;
+ }
+ assembled_axid |= (usip_thread<<4);
+
+ switch(port_sel)
+ {
+ case 0:
+ assembled_axid_mask |= (1<<6) ;
+ break;
+ case 1:
+ assembled_axid |= (1<<3);
+ assembled_axid_mask |= (1<<6) ;
+ break;
+ case 2:
+ assembled_axid |= (1<<0);
+ assembled_axid_mask |= (0x7<<6);
+ break;
+ case 3:
+ assembled_axid |= (1<<0);
+ assembled_axid_mask |= (0x3<<6);
+ break;
+ default: //monitor all ports
+ assembled_axid_mask |= 0x1CD ;
+ break;
+ }
+
+ assembled_axid = (assembled_axid<<2) | 0x2 ;
+ assembled_axid_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_DEFAULT_MASK)) | (assembled_axid_mask<<2) ;
+ //config AXID value/mask
+ if(id==0)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, assembled_axid_mask);
+ }
+ else if(id==1)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, assembled_axid_mask);
+ }
+ else if(id==2)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, assembled_axid_mask);
+ }
+ else
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, assembled_axid);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, assembled_axid_mask);
+ }
+
+ //Enable ELM
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ return rtn;
+}
+
+//!!!! SIDEBAND RELATED API !!!!
+kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ kal_uint32 sideband_val = 0 ;
+ //Disable ELM
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //disable dynamic latency threshold
+ elm_dynamic_lat_threshold_disable = 1;
+ //elm id setting from apb
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
+
+ //calculate vpe sideband value
+ if(vpe_sel >= SYS_MCU_NUM_VPE)
+ {
+ return KAL_FALSE ;
+ }
+ else
+ {
+ kal_uint8 core_id= vpe_sel/(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
+ kal_uint8 vpe_id = vpe_sel%(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
+ sideband_val = (core_id<<6) | ((vpe_id+1)<<4) ;
+ }
+
+ //config ID sideband value/mask
+ if(id==0)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, 0);
+ }
+ else if(id==1)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, 0);
+ }
+ else if(id==2)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, 0);
+ }
+ else if(id==3)
+ {
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, 0);
+ }
+ else
+ { //reset to default
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, 0);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
+ }
+
+ //Enable ELM
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ return rtn;
+}
+
+kal_bool Set_EMI_ELM_ID_SIDEBAND(kal_uint16 sideband_val, kal_uint16 sideband_mask)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ //disable dynamic latency threshold
+ elm_dynamic_lat_threshold_disable = 1;
+ //elm id setting from apb
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);//REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, sideband_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, sideband_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, sideband_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
+ DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, sideband_mask);
+
+ DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+ return rtn;
+}
+
+#endif
diff --git a/mcu/driver/devdrv/elm/src/md97p/elm_trace_utmd.json b/mcu/driver/devdrv/elm/src/md97p/elm_trace_utmd.json
new file mode 100644
index 0000000..6583c27
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md97p/elm_trace_utmd.json
@@ -0,0 +1,154 @@
+{
+ "endGen": "-",
+ "legacyParameters": {
+ "modemType": "elm"
+ },
+ "module": "ELM",
+ "startGen": "97",
+ "stringTranslationDefs": [
+ {
+ "ELM_WC_UNIT_STRING": [
+ "Bytes",
+ "KB",
+ "MB",
+ "GB"
+ ]
+ }
+ ],
+ "traceClassDefs": [
+ {
+ "ELM_Basic_Info_H": {
+ "_comment": "filterDefaulValue is used in xl1sim, will be phased out later",
+ "debugLevel": "High",
+ "filterDefaultValue": "ON",
+ "tag": [
+ "Basic_Info"
+ ],
+ "traceType": "CoreDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "EMI_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Read Latency Threshold] US_CNT %ul us, R_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDMCU][EMI][Write Latency Threshold] US_CNT %ul us, W_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_SET_R_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Read Latency Threshold] US_CNT %ul us, R_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "INFRA_ELM_SET_W_TH": {
+ "format": "[INFO][ELM][MDIFRA][EMI][Write Latency Threshold] US_CNT %ul us, W_Threshold %ul ns",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "INFO"
+ }
+ },
+ {
+ "EMI_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Latency Violation] US_CNT %ul us, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Latency Violation] US_CNT %ul us, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, w_tran %ul, MD_DVFS_CON %xl, AP_VCORE_DVFS_CURR %xl, AP_VCORE_DVFS_LAST %xl",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_A][Read Latency Violation] US_CNT %ul us, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_A][Write Latency Violation] US_CNT %ul us, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, R_tran %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_R_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Read Latency Violation] US_CNT %ul us, L1 R_ave_lat %ul ns, R_Threhsold %ul ns, L2 R_Latency %ul ns, R_tran %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_W_LAT_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Write Latency Violation] US_CNT %ul us, L1 W_ave_lat %ul ns, W_Threhsold %ul ns, L2 W_Latency %ul ns, R_tran %ul",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_AP_DVFS_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Vcore DVFS] US_CNT %ul us, MD systick %ul T, Vcore DVFS %ul T",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_R_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Read Bandwidth Violation] US_CNT %ul us, R_BW %ul, R_BW_Threhsold %ul %s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "EMI_ELM_W_BW_WARN": {
+ "format": "[WARN][ELM][MDMCU][EMI][M3][Write Bandwidth Violation] US_CNT %ul us, W_BW %ul, W_BW_Threhsold %ul %s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_R_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_A][Read Bandwidth Violation] US_CNT %ul us, R_BW %ul, R_BW_Threhsold %ul %s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_W_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_A][Write Bandwidth Violation] US_CNT %ul us, W_BW %ul, W_BW_Threhsold %ul %s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_R_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Read Bandwidth Violation] US_CNT %ul us, R_BW %ul, R_BW_Threhsold %ul %s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ },
+ {
+ "INFRA_ELM_B_W_BW_WARN": {
+ "format": "[WARN][ELM][MDIFRA][EMI][M4_B][Write Bandwidth Violation] US_CNT %ul us, W_BW %ul, W_BW_Threhsold %ul %s",
+ "traceClass": "ELM_Basic_Info_H",
+ "traceHighlightOption": "warn"
+ }
+ }
+ ],
+ "traceFamily": "L1",
+ "userModule": "elm"
+}
\ No newline at end of file