[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/elm/inc/elm.h b/mcu/driver/devdrv/elm/inc/elm.h
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+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * elm.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Header file for ELM.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if !defined(__ELM_H__)
+#define __ELM_H__
+/* ==================== */
+/* CONFIGURATIONS */
+/* ==================== */
+/* ==================== */
+/* INCLUDES */
+/* ==================== */
+#include "reg_base.h"
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "sync_data.h"
+#include "boot.h"
+
+#include "drv_comm.h"
+/*******************************************************************************
+ * Feature Option
+ *******************************************************************************/
+#define ELM_AMIF_ENABLE
+#define ELM_GCR
+#define __ELM_RUNTIME_PROFILE__
+
+
+/* ==================== */
+/* DEFINITIONS */
+/* ==================== */
+#if defined(__MD95__)
+ #define __ELM_MD95__
+ #define ELM_IF_DEF_MD95(def_statement, undef_statement) def_statement
+#elif defined(__MD97__)
+ #define __ELM_MD97__
+#elif defined(__MD97P__)
+ #define __ELM_MD97P__
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_MD95(def_statement, undef_statement) undef_statement
+#endif
+
+#if defined(__ELM_MD95__) || defined(__ELM_MD97__) || defined(__ELM_MD97P__)
+
+#ifdef ELM_GCR
+#define REG_ELM_STAT (GCR_CUSTOM_ADDR + 0x00A0) //0xA0~0xAC, MDMCU, CNT0~CNT3
+#define REG_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x00B0) //0xB0~0xB4, MDMCU, CNT4~CNT5, only valid in mode0, representing word count
+
+#if defined(MT6297)
+#define REG_INFRA_B_ELM_STAT (GCR_CUSTOM_ADDR + 0x0490) //APOLLO MDINFRA_ELM_B
+#define REG_INFRA_B_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x04a0) //APOLLO MDINFRA_ELM_B
+
+#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x060) //APOLLO MDINFRA_ELM_A
+#define REG_INFRA_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x0B8) //APOLLO MDINFRA_ELM_A
+#else
+#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x0060) //0x60~0x6C, MDINFRA, CNT0~CNT3
+#define REG_INFRA_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x00B8) //0xB8~0xBC, MDINFRA, CNT4~CNT5, only valid in mode0, representing word count
+#endif
+
+#else
+#define REG_ELM_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+#define REG_ELM_WC_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x00E0)
+#define REG_INFRA_ELM_STAT (BASE_ADDR_MDINFRA_ELM + 0x0050)
+#define REG_INFRA_ELM_WC_STAT (BASE_ADDR_MDINFRA_ELM + 0x00E0)
+#endif //ifdef ELM_GCR
+#define REG_ELM_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+#define REG_ELM_WC_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x00E0)
+
+#define ELM_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_ELM_WC_STAT + (rw << 2));\
+ } while(0)
+
+#define ELM_INFRA_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_ELM_WC_STAT + (rw << 2));\
+ } while(0)
+
+#if defined(MT6297)
+#define ELM_INFRA_B_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_B_ELM_WC_STAT + (rw << 2));\
+ } while(0)
+#endif
+
+#else //!__ELM_MD95__
+
+#ifdef ELM_GCR
+#define REG_ELM_STAT (GCR_CUSTOM_ADDR + 0x00B0)
+#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x0060)
+#else
+#define REG_ELM_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+#define REG_INFRA_ELM_STAT (BASE_ADDR_MDINFRA_ELM + 0x0050)
+#endif //ifdef ELM_GCR
+#define REG_ELM_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
+
+#define ELM_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ } while(0)
+
+#define ELM_INFRA_GET_WC_CNT(rw, idx, p_cnt) \
+ do {\
+ } while(0)
+
+#endif //ifdef __ELM_MD95__
+
+/* ==================== */
+/* ELM CONTROL API */
+/* ==================== */
+
+// ELM init
+extern void ELM_INIT(void);
+extern void ELM_Config_DormantEnter(void);
+extern void ELM_Config_DormantLeave(void);
+extern kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type);
+extern kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+// ELM clear
+#define ELM_CLR() \
+ do {\
+ } while(0)
+
+// ELM Start
+#define ELM_START() \
+ do {\
+ } while(0)
+
+// ELM Pause
+#define ELM_PAUSE() \
+ do {\
+ } while(0)
+
+// ELM Counter Selection
+enum {
+ ELM_RD = 0,
+ ELM_WR = 1
+};
+
+enum {
+ ELM_TYPE_TRANS = 0,
+ ELM_TYPE_LATENCY = 1
+};
+
+
+#define ELM_GET_CNT(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+
+
+#define ELM_INFRA_GET_CNT(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+
+#if defined(MT6297)
+#define ELM_INFRA_B_GET_CNT(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_INFRA_B_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+#endif
+
+
+#define ELM_GET_CNT_APB(rw, type, idx, p_cnt) \
+ do {\
+ *p_cnt = DRV_Reg32(REG_ELM_STAT_APB+ (((rw ) + (type<< 1)) << 2));\
+ } while(0)
+
+
+typedef struct _ELM_LOG_T
+{
+ kal_uint32 w_trans;
+ kal_uint32 w_latency;
+ kal_uint32 r_trans;
+ kal_uint32 r_latency;
+} ELM_LOG_T;
+
+typedef struct _ELM_FULL_LOG_T
+{
+ kal_uint32 fma_stamp;
+ kal_uint32 w_trans;
+ kal_uint32 w_latency;
+ kal_uint32 w_wordcount;
+ kal_uint32 r_trans;
+ kal_uint32 r_latency;
+ kal_uint32 r_wordcount;
+ kal_uint32 r_lat_thr;// read latency criteria
+ kal_uint32 w_lat_thr;// write latency criteria
+} ELM_FULL_LOG_T;
+
+typedef struct _ELM_M4PORT_FULL_LOG_T
+{
+ kal_uint32 infra_w_trans;
+ kal_uint32 infra_w_latency;
+ kal_uint32 infra_w_wordcount;
+ kal_uint32 infra_r_trans;
+ kal_uint32 infra_r_latency;
+ kal_uint32 infra_r_wordcount;
+} ELM_M4PORT_FULL_LOG_T;
+
+
+// for spv compatibility
+#define ELM_GET_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).w_trans));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).w_latency));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).r_trans));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).r_latency));\
+ } while (0)
+
+#define ELM_GET_ALL_LOG(c, l) do { \
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).w_trans));\
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).w_latency));\
+ ELM_GET_WC_CNT(ELM_WR, (c), &((l).w_wordcount));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).r_trans));\
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).r_latency));\
+ ELM_GET_WC_CNT(ELM_RD, (c), &((l).r_wordcount));\
+ } while (0)
+
+#define ELM_GET_M4PORT_ALL_LOG(c, l) do { \
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).infra_w_trans));\
+ ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).infra_w_latency));\
+ ELM_INFRA_GET_WC_CNT(ELM_WR, (c), &((l).infra_w_wordcount));\
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).infra_r_trans));\
+ ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).infra_r_latency));\
+ ELM_INFRA_GET_WC_CNT(ELM_RD, (c), &((l).infra_r_wordcount));\
+ } while (0)
+
+#if defined(MT6297)
+#define ELM_GET_MDINFRA_B_ALL_LOG(c, l) do { \
+ ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).infra_w_trans));\
+ ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).infra_w_latency));\
+ ELM_INFRA_B_GET_WC_CNT(ELM_WR, (c), &((l).infra_w_wordcount));\
+ ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).infra_r_trans));\
+ ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).infra_r_latency));\
+ ELM_INFRA_B_GET_WC_CNT(ELM_RD, (c), &((l).infra_r_wordcount));\
+ } while (0)
+#endif
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data);
+
+// for profiling ELM log
+typedef enum
+{
+ //When ELM irq happend
+ ELM_NONE = 0, //show trace only
+ ELM_ASSERT, //trigger assert
+ ELM_ASSERT_AT_2nd, //show trace first, twice in 500us then assert
+} elm_exception_type;
+
+typedef struct _ELM_RUNTIME_PROFILE_LAT_T
+{
+ kal_uint32 cur_frc;
+ kal_uint32 int_status;
+ kal_uint32 r_trans;
+ kal_uint32 w_trans;
+ kal_uint32 r_alat;
+ kal_uint32 r_alat_maxost;
+ kal_uint32 w_alat;
+ kal_uint32 w_alat_maxost;
+ kal_uint32 r_l2_tot_lat;
+ kal_uint32 w_l2_tot_lat;
+ kal_uint32 ap_dvfs_tick;
+ kal_uint32 txzq_dvfs_tick;
+ kal_uint32 md_tick;
+#if defined(__MD97__) || defined(__MD97P__)
+ kal_uint32 enter_lisr_frc;
+ kal_uint32 ap_ddren_tick ;
+ kal_uint32 id0_subwindow_status;
+ kal_uint32 id1_subwindow_status;
+ kal_uint32 emi_blocking;
+#endif
+} ELM_RUNTIME_PROFILE_LAT_T;
+
+typedef struct _ELM_RUNTIME_PROFILE_WC_T
+{
+ kal_uint32 cur_frc;
+ kal_uint32 int_status;
+ kal_uint32 r_wc;
+ kal_uint32 w_wc;
+} ELM_RUNTIME_PROFILE_WC_T;
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us);
+void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us);
+
+#if defined(__MD97__) || defined(__MD97P__)
+typedef struct _ELM_MAX_LOG_T
+{
+ kal_uint32 m3_max_r_word_cnt ;
+ kal_uint32 m3_max_w_word_cnt ;
+ kal_uint32 m4_max_r_word_cnt ;
+ kal_uint32 m4_max_w_word_cnt ;
+#if defined(MT6297)
+ kal_uint32 m4b_max_r_word_cnt ;
+ kal_uint32 m4b_max_w_word_cnt ;
+#endif
+} ELM_MAX_LOG_T;
+
+void EMI_ELM_GET_MAX_LOG(ELM_MAX_LOG_T * tt);
+void EMI_ELM_AMIF_SCENARIO_CHANGE_LOGGING(ELM_MAX_LOG_T t);
+
+#endif
+
+#endif /* !__ELM_H__ */