[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/elm/src/md95/elm.c b/mcu/driver/devdrv/elm/src/md95/elm.c
new file mode 100644
index 0000000..fe9b2e6
--- /dev/null
+++ b/mcu/driver/devdrv/elm/src/md95/elm.c
@@ -0,0 +1,2074 @@
+#include "elm.h"
+#include "drv_comm.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "drv_mdap_interface.h" //for show AMIF scenario register in trace
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+// for profiling ELM log
+#include "TrcMod.h" //for L1 Trace API
+#endif
+
+/** ----- Register definition ------ **/
+
+// MDMCU ELM
+#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
+#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
+#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
+ #define ELM_MODE(x) ((x)<<4)
+ #define ELM_MODE_MASK 0x3
+ #define ELM_AO_DECODE(x) ((x)<<13)
+ #define ELM_DECODE_FROM_AO 1
+ #define ELM_DECODE_FROM_APB 0
+ #define ELM_MODE_ID_SEL(x) (x<<8)
+ #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only
+ #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3
+#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
+ //Note: For "MDMCU" ELM support all in Mode 0 & Mode 2. For "MDINFRA" ELM only support AXI ID in mode 0, support all in mode 2.
+ #define AUSER(x) ((x)<<24) //7'h7F
+ #define AUSER_MASK 0x7F
+ #define USER_SOURCE(x) (x<<0)
+ #define US_MASK 0x3
+ #define US_USIP 0x0
+ #define US_IA 0x1
+ #define US_SFU 0x2
+ #define US_SPU 0x3
+ #define USER_ID(x) (x<<2)
+ #define UI_MASK 0x3
+ #define UI_VPE0 0x0
+ #define UI_VPE1 0x1
+ #define UI_THREAD0 0x0
+ #define UI_THREAD1 0x1
+ #define USER_CORE(x) (x<<4)
+ #define UC_MASK 0x7
+ #define UC_CORE0 0x0
+ #define UC_CORE1 0x1
+ #define UC_CORE2 0x2
+ #define UC_CORE3 0x3
+ #define UC_IOCU 0x4
+ #define UC_USIP0 0x5
+ #define UC_USIP1 0x6
+ #define ELM_SEL_VPE0 USER_SOURCE(US_IA)|USER_CORE(UC_CORE0)|USER_ID(UI_VPE0)
+ #define ELM_SEL_VPE1 USER_SOURCE(US_IA)|USER_CORE(UC_CORE0)|USER_ID(UI_VPE1)
+ #define ELM_SEL_VPE2 USER_SOURCE(US_IA)|USER_CORE(UC_CORE1)|USER_ID(UI_VPE0)
+ #define ELM_SEL_VPE3 USER_SOURCE(US_IA)|USER_CORE(UC_CORE1)|USER_ID(UI_VPE1)
+ #define ELM_SEL_VPE4 USER_SOURCE(US_IA)|USER_CORE(UC_CORE2)|USER_ID(UI_VPE0)
+ #define ELM_SEL_VPE5 USER_SOURCE(US_IA)|USER_CORE(UC_CORE2)|USER_ID(UI_VPE1)
+ #define ELM_SEL_USIP0_TH0 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP0)|USER_ID(UI_THREAD0)
+ #define ELM_SEL_USIP0_TH1 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP0)|USER_ID(UI_THREAD1)
+ #define ELM_SEL_USIP1_TH0 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP1)|USER_ID(UI_THREAD0)
+ #define ELM_SEL_USIP1_TH1 USER_SOURCE(US_USIP)|USER_CORE(UC_USIP1)|USER_ID(UI_THREAD1)
+ #define ALEN(x) ((x)<<20) //4'hf
+ #define ASIZE(x) ((x)<<16) //3'h7
+ #define AULTRA(x) ((x)<<14) //2'h3
+ #define ABUST(x) ((x)<<12) //2'h3
+ #define AID(x) ((x)<<0) //12'hFFF
+ #define MASTER_DEFAULT_MASK 0xFFF //defualt value
+ #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2
+ #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU)
+ #define MASTER_MDMCU_MASK 0xFFD
+ #define MASTER_USIP 0x2 //USIP -> 0x2
+ #define MASTER_USIP_MASK 0xFFC
+ #define MASTER_USIP_PORT(x) (x<<2)
+ #define MUP_ALL_MASK 0x3FF
+ #define MUP_PM_MASK 0x3FA
+ #define MUP_PM 0x0
+ #define MUP_DC_MASK 0x3FA
+ #define MUP_DC 0x4
+ #define MUP_DP_ALL_MASK 0x3FE
+ #define MUP_DP_ALL 0x1
+ #define MUP_DP_MASK 0x3EE
+ #define MUP_DP_CACHE 0x11
+ #define MUP_DP_NONCACHE 0x1
+/*
+#define ELM_USIP_CORE_SEL(x) (((x)<<4)|0x2)
+#define ELM_USIP_PORT_SEL(x) ((x)<<2)
+ #define ELM_USIP_PORT_ENABLE_MASK 0x3
+ #define ELM_USIP_PORT_DISABLE_MASK 0x0
+ #define ELM_SEL_USIP_ALL 0x0
+ #define ELM_SEL_USIP_ICACHE 0x0
+ #define ELM_SEL_USIP_DCACHE 0x1
+ #define ELM_SEL_USIP_DNOCACHE 0x2
+*/
+#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
+ #define ELM_AO_CONTROL_DEFAULT 0x7FF7FFFF
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
+#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
+#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
+#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
+#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
+#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
+#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
+#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
+#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
+#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
+ #define INT_MASK_ALL 0x3F
+ #define INT_MASK_LAT 0xF
+ #define INT_MASK_WC 0x30
+ #define ID0_AVG_LAT_INT (1<<0)
+ #define ID0_TOT_LAT_INT (1<<1)
+ #define ID1_AVG_LAT_INT (1<<2)
+ #define ID1_TOT_LAT_INT (1<<3)
+ #define ID2_TOT_WC_INT (1<<4)
+ #define ID3_TOT_WC_INT (1<<5)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
+ #define DECODE_ID0(x) ((x)<<0)
+ #define ELM_READ (0<<4)
+ #define ELM_WRITE (1<<4)
+ #define ELM_ALL_MASTER (0<<2)
+ #define ELM_MDMCU_ONLY (1<<2)
+ #define ELM_USIP_ONLY (2<<2)
+ #define ELM_ALL_PRIO (0<<0)
+ #define ELM_PRE_ULTRA (1<<0)
+ #define ELM_ULTRA (2<<0)
+ #define LAT_TH_ID0_NORMAL(x) ((x)<<5)
+ #define LAT_TH_ID1_NORMAL(x) ((x)<<15)
+ #define ELM_ACCURACY(x) ((x)<<25)
+ #define ELM_unit_100us 2
+ #define ELM_ENABLE (1<<27)
+ #define ELM_DISABLE (0<<27)
+ #define ELM_IDLE_ENABLE (1<<28)
+ #define ELM_IDLE_DISABLE (0<<28)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
+ #define ELM_INT_MASK(x) ((x)<<0)
+ #define LAT_INT_MASK_ALL 0xF
+ #define LAT_INT_UNMASK_ALL 0x0
+ #define EMI_BLOCK(x) ((x)<<4)
+ #define E_NOT_MASK 0
+ #define E_MASK 1
+ #define ELM_DURATION(x) ((x-1)<<5) // (x-1+1)*(ELM_ACCURACY), ELM_ACCURACY = 100us
+ #define DECODE_ID1(x) ((x)<<12)
+ /* #define usage same as DECODE_ID0 */
+ #define ELM_EMI_TOP_BLOCK(x) ((x)<<31)
+ #define E_TOP_MASK 1
+ #define E_TOP_NOT_MASK 0
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90)
+#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98)
+#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C)
+#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0)
+#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4)
+#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8)
+#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC)
+#define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0)
+#define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8)
+#define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8)
+#define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC)
+#define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0)
+#define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4)
+#define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0)
+ #define ELM_WC_INT_MASK(x) ((x)<<0)
+ #define WC_INT_MASK_ALL 0x3
+ #define WC_INT_UNMASK_ALL 0x0
+ #define LAT_TH_ID0_BLOCK(x) ((x)<<4)
+ #define LAT_TH_ID1_BLOCK(x) ((x)<<16)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510)
+#define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514)
+#define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528)
+ #define ELM_WC_DURATION(x) (x-1) // (x-1+1) us
+
+
+// MDINFRA ELM
+#define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
+#define REG_MDINFRA_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x20)
+#define REG_MDINFRA_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x24)
+#define REG_MDINFRA_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x28)
+#define REG_MDINFRA_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x2C)
+#define REG_MDINFRA_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x30)
+#define REG_MDINFRA_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x34)
+#define REG_MDINFRA_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x38)
+#define REG_MDINFRA_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x3C)
+#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70)
+#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74)
+#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78)
+#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C)
+#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80)
+#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84)
+#define REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x88)
+#define REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x8C)
+#define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0)
+#define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4)
+#define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
+#define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
+#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
+#define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510)
+#define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514)
+#define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528)
+ #define ELM_WC_DURATION(x) (x-1) // (x-1+1) us
+
+//AO Register in MDPERIMISC
+#define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
+#define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
+#define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090
+#define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
+#define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
+#define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094
+
+/** ----- AP debugging register definition ------ **/
+#if 1 //defined(MT3967)
+#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xFC) // current dvfsrc level
+#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x308) // last dvfsrc level
+#define AP_VCORE_DVFS_HISTORY_BASE (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x400) // dvfsrc history start address, end address should be 0x45C
+#define AP_VCORE_DVFS_HISTORY_SIZE 24
+#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(BASE_ADDR_AP_SPM+0x624)
+#endif
+
+#include "sleepdrv_interface.h"
+
+// ELM Set Mode (HW/SW Mode)
+enum {
+ ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt
+ ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA
+};
+
+//MCUSYS fixed clock 208Mhz, 1T = 4.8ns
+#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
+#define ELM_NS2TRAN(X) ((((X)*208)/1000))
+
+//MDINFRA fixed clock 100Mhz, 1T = 10ns
+#define ELM_MDINFRA_TRANS2NS(X) (((X)*10))
+#define ELM_MDINFRA_NS2TRAN(X) (((X)/10))
+
+
+//for assert information
+#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
+#define KAL_ERROR_INFRA_ELM_EXCEP 0x4102
+
+#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
+
+#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
+ #define __ELM_TRACE__
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
+#else /* __MCU_DORMANT_MODE__ */
+ #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
+#endif
+
+
+#ifdef __MTK_TARGET__
+
+kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
+
+/*--- MDMCU global variable ---*/
+kal_uint32 elm_mode = ELM_MODE_0;
+// latency criteria
+kal_uint32 elm_trans_threshold = 100;
+kal_uint32 elm_lat_dur_100us = 2; //2*100us = 200us
+#ifdef ELM_AMIF_ENABLE
+kal_uint32 elm_read_lat_threshold = 2000;
+kal_uint32 elm_write_lat_threshold = 2000;
+#else
+kal_uint32 elm_read_lat_threshold = 450;
+kal_uint32 elm_write_lat_threshold = 300;
+#endif
+// word count criteria
+kal_uint32 elm_wc_dur_in_us = 200; // 2*100us = 200us
+kal_uint32 elm_read_wc_threshold = 2*1024*1024*256; // 2*1024*1024*1024/4 * 4 = 2GB
+kal_uint32 elm_write_wc_threshold = 2*1024*1024*256; // 2*1024*1024*1024/4 * 4 = 2GB
+// AO decode setting
+kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_id0_master = ELM_ALL_MASTER;
+kal_uint32 elm_id0_rw = ELM_READ;
+kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
+kal_uint32 elm_id1_master = ELM_ALL_MASTER;
+kal_uint32 elm_id1_rw = ELM_WRITE;
+kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
+// IDx cnt default value target all transaction
+kal_uint32 elm_id0_value = 0;
+kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id1_value = 0;
+kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id2_value = 0;
+kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id3_value = 0;
+kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_id2_rw = ELM_RD;
+kal_uint32 elm_id3_rw = ELM_WR;
+
+/*--- MDINFRA global variable ---*/
+// latency criteria
+kal_uint32 elm_infra_lat_dur_100us = 10; //10*100us = 1000us = 1ms
+kal_uint32 elm_infra_read_lat_threshold = 2000;
+kal_uint32 elm_infra_write_lat_threshold = 2000;
+// word count criteria
+kal_uint32 elm_infra_wc_dur_in_us = 10000; // 10*1000us = 10ms
+kal_uint32 elm_infra_read_wc_threshold = 2*1024*1024*256;
+kal_uint32 elm_infra_write_wc_threshold = 2*1024*1024*256;
+// ID2/3 cnt default value target all transaction
+kal_uint32 elm_infra_ao_decode_cfg = ELM_DECODE_FROM_AO;
+kal_uint32 elm_infra_id0_value = 0;
+kal_uint32 elm_infra_id0_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id1_value = 0;
+kal_uint32 elm_infra_id1_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id2_value = 0;
+kal_uint32 elm_infra_id2_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id3_value = 0;
+kal_uint32 elm_infra_id3_mask = ELM_AO_CONTROL_DEFAULT;
+kal_uint32 elm_infra_id2_rw = ELM_RD;
+kal_uint32 elm_infra_id3_rw = ELM_WR;
+
+
+#if defined(__PRODUCTION_RELEASE__)
+elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
+elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace
+elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace
+elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*--- ELM history variable ---*/
+#define ELM_RUNTIME_HISTORY_SIZE 8
+
+//EMI ELM
+kal_uint32 emi_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 emi_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+//INFRA ELM
+kal_uint32 infra_elm_runtime_lat_history_idx = 0;
+ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
+kal_uint32 infra_elm_runtime_wc_history_idx = 0;
+ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
+
+
+
+
+void elmtop_emi_isr_handler();
+void elm_infra_isr_handler();
+
+
+
+#define ELM_HISTORY_SIZE 64
+kal_uint32 elm_profile_history_idx_0 = 0;
+ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
+
+
+void ELM_INIT(void)
+{
+ /*MDMCU EMI ELM*/
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config id2/3 setting
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, elm_read_wc_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, elm_write_wc_threshold);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_DURATION(elm_wc_dur_in_us));
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2, LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))| \
+ LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+#if 0 //IRQ register is done by IRQ centralization
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ /*MDINFRA EMI ELM*/
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_infra_id2_rw, 2)|ELM_ID_RW(elm_infra_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold);
+ // config word_cnt window setting
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID2_CTRL_REG, elm_infra_id2_value);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID2_CTRL_MASK, elm_infra_id2_mask);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID3_CTRL_REG, elm_infra_id3_value);
+ DRV_WriteReg32(REG_MDINFRA_ELM_AXI_ID3_CTRL_MASK, elm_infra_id3_mask);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, elm_infra_read_wc_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, elm_infra_write_wc_threshold);
+ DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_DURATION(elm_infra_wc_dur_in_us));
+
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| \
+ ELM_DURATION(elm_infra_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2, LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))| \
+ LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+#if 0 //IRQ register is done by IRQ centralization
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+void ELM_Config_DormantLeave(void)
+{
+ kal_uint32 vpe_idx;
+ vpe_idx = kal_get_current_vpe_id();
+ if(0 == vpe_idx)
+ {
+ ELM_INIT();
+ emi_elm_runtime_lat_history_idx =0;
+ memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
+ }
+}
+
+void ELM_Config_DormantEnter(void)
+{
+
+}
+
+void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
+{
+ if(NULL==data)
+ {
+ return;
+ }
+
+#ifdef __ELM_RUNTIME_PROFILE__
+ elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
+ ELM_GET_ALL_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
+ elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
+ elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
+ memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
+ elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
+#else
+ data->fma_stamp = ust_get_current_time();
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
+ ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
+ ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
+ ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
+ ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount));
+#endif
+
+}
+
+kal_uint32 debug_emi_elm_runtime_counter = 0;
+kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
+kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
+
+
+
+#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
+
+kal_uint32 elm_md_dvfs_con = 0;
+kal_uint32 elm_ap_vcore_dvfs_current = 0;
+kal_uint32 elm_ap_vcore_dvfs_last = 0;
+kal_uint32 elm_ap_vcore_dvfs_history[AP_VCORE_DVFS_HISTORY_SIZE] = {0};
+
+void elmtop_emi_isr_handler()
+{
+ // TODO: ELM mutex need here
+
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0;
+ debug_emi_elm_runtime_counter++;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //DRV_WriteReg32_NPW(REG_MCUSYS_EMI_ELM_ELM_EN_REG, 0); //stop ELM
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+
+ curr_frc = ust_get_current_time();
+#if 1
+ ia_13m_tick = SleepDrv_GetWallClk();
+ dvfs_13m_tick = DRV_Reg32(AP_DVFS_OCCUR_TICK);
+#endif
+ int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS); //Read ELM interrupt status
+
+ // Check latency or word count interrupt first
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );
+ read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) );
+ write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );
+ write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) );
+ read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+ emi_elm_runtime_lat_history_idx++;
+
+ elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg();
+ // Read AP side debugging register
+ elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
+ elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
+#if defined(MT3967)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ // only dvfs tick information, no need to use if/else.
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_AP_DVFS_WARN(curr_frc, ia_13m_tick, dvfs_13m_tick),);
+#endif
+ switch(EMI_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ //read latency over criteria
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ //write latency over criteria
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ break;
+ }
+ case ELM_ASSERT:
+ {
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ // just show trace on first time over criteria in 300us
+ if(debug_MDMCU_elm_last_INT_FRC == 0)
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ }
+ else
+ {
+ if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < 300)
+ {
+ kal_uint32 i;
+ for(i=0;i<AP_VCORE_DVFS_HISTORY_SIZE;i++)
+ {
+ elm_ap_vcore_dvfs_history[i] = *(AP_VCORE_DVFS_HISTORY_BASE + i);
+ }
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
+ (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ else
+ {
+ EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
+ (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
+ (E_MAX16(0)<<16)|(E_MAX16(int_status)));
+ }
+ }
+ else
+ {
+ debug_MDMCU_elm_last_INT_FRC = curr_frc;
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
+ elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
+ );
+ }
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ }
+ /* Handling word count interrupt */
+ else
+ {
+ read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
+
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ emi_elm_runtime_wc_history_idx++;
+
+ switch(EMI_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, read_worst_wc, elm_read_wc_threshold), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, write_worst_wc, elm_write_wc_threshold), \
+ );
+ }
+ break;
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ default:
+ break;
+ }
+ }
+
+
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+}
+
+void elm_infra_isr_handler()
+{
+
+ // TODO: ELM mutex need here
+
+ kal_uint32 curr_frc = 0;
+ kal_uint32 int_status = 0;
+ kal_uint32 read_trans_count = 0, write_trans_count = 0;
+ kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
+ kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
+ kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0;
+ kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
+ kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0;
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELM_DMA_IRQ_CODE);
+
+ //DRV_WriteReg32_NPW(REG_MCUSYS_EMI_ELM_ELM_EN_REG, 0); //stop ELM
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+#if 1
+ ia_13m_tick = SleepDrv_GetWallClk();
+ dvfs_13m_tick = DRV_Reg32(AP_DVFS_OCCUR_TICK);
+#endif
+ curr_frc = ust_get_current_time();
+
+ //SET_ELM_RW_LAT_FLAG(REG_MCUSYS_EMI_ELM_ELM_INT_STATUS, &lat_flag, &r_flag);
+ int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS); //Read ELM interrupt status
+
+
+
+ /* Handling latency interrupt */
+ if(int_status & INT_MASK_LAT)
+ {
+ read_worst_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL));
+ read_total_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL));
+ write_worst_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL));
+ write_total_latency_ns = ELM_MDINFRA_TRANS2NS(DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL));
+ read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
+ write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
+ read_worst_alat_maxost = DRV_Reg32(REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
+ write_worst_alat_maxost = DRV_Reg32(REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
+
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
+ infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
+
+ infra_elm_runtime_lat_history_idx++;
+
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_AP_DVFS_WARN(curr_frc, ia_13m_tick, dvfs_13m_tick),);
+
+ switch(INFRA_ELM_lat_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+#ifdef __ELM_TRACE__
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l"
+ MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count, int_status);
+ }
+ else
+ {
+ //US_CNT %l us, R_ave_lat %l ns, R_Threhsold %l ns, R_Latency %l T, R_tran %l"
+ MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count, int_status);
+ }
+#endif
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ /* Handling word count interrupt */
+ else
+ {
+ /* do nothing */
+ read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
+ write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
+
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
+ infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
+ infra_elm_runtime_wc_history_idx++;
+
+ switch(INFRA_ELM_wc_irq_exception_type)
+ {
+ case ELM_NONE:
+ {
+ // Read wordcount violation
+ if(int_status & ID2_TOT_WC_INT)
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, read_worst_wc, elm_infra_read_wc_threshold), \
+ );
+ }
+ else
+ {
+ ELM_IF_DEF_TRACE( \
+ MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, write_worst_wc, elm_infra_write_wc_threshold), \
+ );
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ //Clear ELM interrupt after read irq type
+ DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
+
+}
+
+/* Lightweight version for AMIF using in dormant backup/restore */
+void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_dur_100us = (kal_uint32)(dur_us/100);
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_DISABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+
+ /* Set AO_ELM_EN bit should be last step. */
+ DRV_SetReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
+{
+ kal_uint32 mask_state=0;
+
+ if(elm_dynamic_lat_threshold_disable)
+ {
+ return;
+ }
+
+ if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
+ {
+ kal_uint32 lr = 0;
+ kal_uint32 sub_error_code = 0;
+ GET_RETURN_ADDRESS(lr);
+ if(read_avg_lat_ns<200)
+ {
+ sub_error_code = 1;
+ }
+ else if(write_avg_lat_ns<200)
+ {
+ sub_error_code = 2;
+ }
+ else
+ {
+ sub_error_code = 3;
+ }
+ EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
+ }
+
+
+
+ mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ //Mask cirq ELM interrupt
+ IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
+
+ kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
+
+
+ elm_read_lat_threshold = read_avg_lat_ns;
+ elm_write_lat_threshold = write_avg_lat_ns;
+ elm_lat_dur_100us = (kal_uint32)(dur_us/100);
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
+
+#ifdef __ELM_TRACE__
+ {
+ // L1 trace
+ kal_uint32 curr_frc = 0;
+ curr_frc = ust_get_current_time();
+ MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
+ MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
+ }
+#endif
+
+ if(!mask_state)
+ {
+ IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
+ }
+
+}
+
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+void _ELM_exception_saved(void)
+{
+#if 0//def __ELM_RUNTIME_PROFILE__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+}
+
+
+kal_uint8 _ELM_latency_status(void)
+{
+#if 1//def __ELM_RUNTIME_PROFILE__
+
+ //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
+ if(emi_elm_runtime_lat_history_idx != 0)
+ {
+ kal_uint32 int_status = 0;
+ int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
+
+ if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
+ {
+ return 0xAE; //EMI read latency may be too long
+ }
+ else
+ {
+ return 0xBE; //EMI write latency may be too long
+ }
+ }
+ return 0xDE; // EMI read/write latency are OK.
+#else
+/* under construction !*/
+#endif
+}
+
+/******************************************************************************
+* function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type)
+* description : this function is called when set emi elm read/write latency/wordcount exception type
+* parameter : kal_uint8 exception_type: 0,1,2
+* return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
+{
+ switch (exception_type)
+ {
+ case ELM_NONE:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_NONE;
+ break;
+ }
+
+ case ELM_ASSERT:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
+ break;
+ }
+ case ELM_ASSERT_AT_2nd:
+ {
+ EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
+ break;
+ }
+ default:
+ return KAL_FALSE;
+ break;
+ }
+ return KAL_TRUE;
+}
+
+kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
+{
+ ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
+ ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+ if((info&0xF0))
+ { // infra
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_infra_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_infra_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio));
+ }
+ else
+ { //mdmcu
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ if( info & 0x01 )
+ {
+ elm_read_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
+ }
+ else
+ {
+ elm_write_lat_threshold = threshold;
+ ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
+ }
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
+ }
+
+
+ return KAL_TRUE;
+}
+
+/******************************************************************************
+* function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+* description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's
+* counter to monitro read or write transaction and master.
+* parameter :
+* kal_uint8 id: 0, 1, 0xFF;
+* -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters.
+* -> 0xFF is used for let all ID monitor same masters.
+* return : void
+******************************************************************************/
+kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
+{
+ kal_bool rtn = KAL_TRUE;
+
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if(id == 0) // id 0 (default read), assume id2 use same master as id 0
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = AID(MASTER_MDMCU);
+ elm_id2_mask |= AID(MASTER_MDMCU_MASK);
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+
+ elm_id2_value = AID(MASTER_USIP);
+ elm_id2_mask |= AID(MASTER_USIP_MASK);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id0_rw = ELM_READ;
+ elm_id2_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id0_rw = ELM_WRITE;
+ elm_id2_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1
+ {
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+ if(m_sel==0)
+ {
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id3_value = 0;
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(m_sel==1)
+ {
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id3_value = AID(MASTER_MDMCU);
+ elm_id3_mask |= AID(MASTER_MDMCU_MASK);
+ }
+ else if(m_sel==2)
+ {
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id3_value = AID(MASTER_USIP);
+ elm_id3_mask |= AID(MASTER_USIP_MASK);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rw == 0)
+ {
+ elm_id1_rw = ELM_READ;
+ elm_id3_rw = ELM_RD;
+ }
+ else if(rw == 1)
+ {
+ elm_id1_rw = ELM_WRITE;
+ elm_id3_rw = ELM_WR;
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write
+ {
+ elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+ elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~AID((MASTER_ALL_MASK)));
+
+ elm_id0_rw = ELM_READ;
+ elm_id1_rw = ELM_WRITE;
+ elm_id2_rw = ELM_RD;
+ elm_id3_rw = ELM_WR;
+ if(m_sel==0)
+ {
+ elm_id0_master = ELM_ALL_MASTER;
+ elm_id1_master = ELM_ALL_MASTER;
+
+ elm_id2_value = 0;
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id3_value = 0;
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(m_sel==1)
+ {
+ elm_id0_master = ELM_MDMCU_ONLY;
+ elm_id1_master = ELM_MDMCU_ONLY;
+
+ elm_id2_value = AID(MASTER_MDMCU);
+ elm_id2_mask |= AID(MASTER_MDMCU_MASK);
+ elm_id3_value = AID(MASTER_MDMCU);
+ elm_id3_mask |= AID(MASTER_MDMCU_MASK);
+ }
+ else if(m_sel==2)
+ {
+ elm_id0_master = ELM_USIP_ONLY;
+ elm_id1_master = ELM_USIP_ONLY;
+
+ elm_id2_value = AID(MASTER_USIP);
+ elm_id2_mask |= AID(MASTER_USIP_MASK);
+ elm_id3_value = AID(MASTER_USIP);
+ elm_id3_mask |= AID(MASTER_USIP_MASK);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+ if( mode == 0)
+ {
+ elm_mode = ELM_MODE_0;
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ else if( mode == 2)
+ {
+ elm_mode = ELM_MODE_2;
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+
+ DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
+ DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
+
+ DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| \
+ ELM_DURATION(elm_infra_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+
+
+kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 core_th_sel, kal_uint8 port_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ if(id == 0)// id 0
+ {
+ elm_id0_value = 0;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id2_value = 0;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+
+ if(core_th_sel==0x00)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH0);
+ }
+ else if(core_th_sel==0x01)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH1);
+ }
+ else if(core_th_sel==0x10)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH0);
+ }
+ else if(core_th_sel==0x11)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH1);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ // Port select
+ if(port_sel==0x0) // All master
+ {
+ elm_id0_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(port_sel==0x1) // PM port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ }
+ else if(port_sel==0x2) // DC port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ }
+ else if(port_sel==0x3) // DP port all
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ }
+ else if(port_sel==0x4) // DP port cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ }
+ else if(port_sel==0x5) // DP port non-cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 1)// id 1
+ {
+ elm_id1_value = 0;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id3_value = 0;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+
+ if(core_th_sel==0x00)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH0);
+ }
+ else if(core_th_sel==0x01)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH1);
+ }
+ else if(core_th_sel==0x10)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH0);
+ }
+ else if(core_th_sel==0x11)
+ {
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH1);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ // Port select
+ if(port_sel==0x0) // All master
+ {
+ elm_id1_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(port_sel==0x1) // PM port
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ }
+ else if(port_sel==0x2) // DC port
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ }
+ else if(port_sel==0x3) // DP port all
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ }
+ else if(port_sel==0x4) // DP port cachable
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ }
+ else if(port_sel==0x5) // DP port non-cachable
+ {
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 0xFF) // ID 0/1 are the same
+ {
+ elm_id0_value = 0;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id1_value = 0;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id2_value = 0;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+ elm_id3_value = 0;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT & (~(AUSER(AUSER_MASK)) & ~(AID(MASTER_USIP_PORT(MUP_ALL_MASK))));
+
+ if(core_th_sel==0x00)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH0);
+ }
+ else if(core_th_sel==0x01)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id1_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP0_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP0_TH1);
+ }
+ else if(core_th_sel==0x10)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH0);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH0);
+ }
+ else if(core_th_sel==0x11)
+ {
+ elm_id0_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id1_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id2_value = AUSER(ELM_SEL_USIP1_TH1);
+ elm_id3_value = AUSER(ELM_SEL_USIP1_TH1);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ // Port select
+ if(port_sel==0x0) // All master
+ {
+ elm_id0_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id1_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id2_mask |= AID(MASTER_DEFAULT_MASK);
+ elm_id3_mask |= AID(MASTER_DEFAULT_MASK);
+ }
+ else if(port_sel==0x1) // PM port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_PM_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_PM));
+ }
+ else if(port_sel==0x2) // DC port
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DC_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DC));
+ }
+ else if(port_sel==0x3) // DP port all
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_ALL_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_ALL));
+ }
+ else if(port_sel==0x4) // DP port cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_CACHE));
+ }
+ else if(port_sel==0x5) // DP port non-cachable
+ {
+ elm_id0_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id1_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id2_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id3_mask |= AID(MASTER_USIP_PORT(MUP_DP_MASK));
+ elm_id0_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id1_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id2_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ elm_id3_value |= AID(MASTER_USIP_PORT(MUP_DP_NONCACHE));
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rtn == KAL_FALSE)
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+ }
+ else
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_id0_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_id0_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_id1_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_id1_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+ //Disable before re-configure
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
+ elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ if(id == 0)// id 0
+ {
+ elm_id0_mask &= ~(AUSER(AUSER_MASK));
+ elm_id2_mask &= ~(AUSER(AUSER_MASK));
+ if(vpe_sel==0)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE0);
+ elm_id2_value = AUSER(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE1);
+ elm_id2_value = AUSER(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE2);
+ elm_id2_value = AUSER(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE3);
+ elm_id2_value = AUSER(ELM_SEL_VPE3);
+ }
+ else if(vpe_sel==4)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE4);
+ elm_id2_value = AUSER(ELM_SEL_VPE4);
+ }
+ else if(vpe_sel==5)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE5);
+ elm_id2_value = AUSER(ELM_SEL_VPE5);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+
+ }
+ else if(id == 1) // id 1 (default write)
+ {
+ elm_id1_mask &= ~(AUSER(AUSER_MASK));
+ elm_id3_mask &= ~(AUSER(AUSER_MASK));
+ if(vpe_sel==0)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE0);
+ elm_id3_value = AUSER(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE1);
+ elm_id3_value = AUSER(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE2);
+ elm_id3_value = AUSER(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE3);
+ elm_id3_value = AUSER(ELM_SEL_VPE3);
+ }
+ else if(vpe_sel==4)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE4);
+ elm_id3_value = AUSER(ELM_SEL_VPE4);
+ }
+ else if(vpe_sel==5)
+ {
+ elm_id1_value = AUSER(ELM_SEL_VPE5);
+ elm_id3_value = AUSER(ELM_SEL_VPE5);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else if(id == 0xFF)// ID 0/1 are the same
+ {
+ elm_id0_mask &= ~(AUSER(AUSER_MASK));
+ elm_id1_mask &= ~(AUSER(AUSER_MASK));
+ elm_id2_mask &= ~(AUSER(AUSER_MASK));
+ elm_id3_mask &= ~(AUSER(AUSER_MASK));
+ if(vpe_sel==0)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE0);
+ elm_id1_value = AUSER(ELM_SEL_VPE0);
+ elm_id2_value = AUSER(ELM_SEL_VPE0);
+ elm_id3_value = AUSER(ELM_SEL_VPE0);
+ }
+ else if(vpe_sel==1)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE1);
+ elm_id1_value = AUSER(ELM_SEL_VPE1);
+ elm_id2_value = AUSER(ELM_SEL_VPE1);
+ elm_id3_value = AUSER(ELM_SEL_VPE1);
+ }
+ else if(vpe_sel==2)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE2);
+ elm_id1_value = AUSER(ELM_SEL_VPE2);
+ elm_id2_value = AUSER(ELM_SEL_VPE2);
+ elm_id3_value = AUSER(ELM_SEL_VPE2);
+ }
+ else if(vpe_sel==3)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE3);
+ elm_id1_value = AUSER(ELM_SEL_VPE3);
+ elm_id2_value = AUSER(ELM_SEL_VPE3);
+ elm_id3_value = AUSER(ELM_SEL_VPE3);
+ }
+ else if(vpe_sel==4)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE4);
+ elm_id1_value = AUSER(ELM_SEL_VPE4);
+ elm_id2_value = AUSER(ELM_SEL_VPE4);
+ elm_id3_value = AUSER(ELM_SEL_VPE4);
+ }
+ else if(vpe_sel==5)
+ {
+ elm_id0_value = AUSER(ELM_SEL_VPE5);
+ elm_id1_value = AUSER(ELM_SEL_VPE5);
+ elm_id2_value = AUSER(ELM_SEL_VPE5);
+ elm_id3_value = AUSER(ELM_SEL_VPE5);
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
+ elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
+ }
+ }
+ else
+ {
+ rtn = KAL_FALSE;
+ }
+
+ if(rtn == KAL_FALSE)
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
+ }
+ else
+ {
+ elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
+ }
+
+ DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
+ DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
+
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_id0_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_id0_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_id1_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_id1_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
+ DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
+
+ DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| \
+ ELM_DURATION(elm_lat_dur_100us)|EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
+
+ DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(ELM_unit_100us)| \
+ LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
+ DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); //ELM enable for MDMCU Reset
+ return rtn;
+}
+
+kal_bool ELM_INFRA_set_master(kal_uint8 id, kal_uint8 m_sel)
+{
+ kal_bool rtn = KAL_TRUE;
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ return rtn;
+}
+#endif