diff --git a/mcu/driver/devdrv/gpio/src/dcl_gpio.c b/mcu/driver/devdrv/gpio/src/dcl_gpio.c
new file mode 100644
index 0000000..1bbc682
--- /dev/null
+++ b/mcu/driver/devdrv/gpio/src/dcl_gpio.c
@@ -0,0 +1,624 @@
+
+
+#if !defined(DRV_GPIO_NOT_EXIST) && !defined(DRV_GPIO_OFF)
+
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "dcl.h"
+#include "drv_gpio.h"
+
+#include "drvpdn.h"
+
+#define DCL_GPIO_MAGIC_NUM			0x80000000
+#define DCL_GPO_MAGIC_NUM			0x40000000
+#define DCL_GPIO_CLK_MAGIC_NUM	0x20000000
+
+#define DCL_GPIO_IS_HANDLE_MAGIC(handle_)       ((handle_)& DCL_GPIO_MAGIC_NUM)
+#define DCL_GPIO_GET_DEV(handle_) 	   	      ((handle_)& (~DCL_GPIO_MAGIC_NUM))
+
+#define DCL_GPO_IS_HANDLE_MAGIC(handle_)        ((handle_) & DCL_GPO_MAGIC_NUM)
+#define DCL_GPO_GET_DEV(handle_)                ((handle_) & (~DCL_GPO_MAGIC_NUM))
+
+#define DCL_GPIO_CLK_IS_HANDLE_MAGIC(handle_)   ((handle_) & DCL_GPIO_CLK_MAGIC_NUM)
+#define DCL_GPIO_CLK_GET_DEV(handle_)           ((handle_) & (~DCL_GPIO_MAGIC_NUM))
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_Initialize
+*
+* DESCRIPTION
+*  This function is to initialize GPIO module. Note that all the GPIO pin
+* will be set to a predefined state.
+*
+* PARAMETERS
+*	DCL_STATUS_OK
+*
+* RETURNS
+*  none
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_Initialize(void)
+{
+   extern void GPIO_init(void);
+   
+   GPIO_init();
+   return STATUS_OK;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_Open
+* DESCRIPTION
+*  This function is to open the GPIO module and get a handle. Note that multiple opens are allowed.
+*
+* PARAMETERS
+*	eDev: - only valid for DCL_GPIO,DCL_GPO,DCL_GPIO_CLK.
+*	flags: - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURN VALUES
+*	DCL_HANDLE_INVALID: - Open failed.
+* other value: - a valid handle
+*
+*-----------------------------------------------------------------------*/
+
+DCL_HANDLE DclGPIO_Open(DCL_DEV eDev, DCL_FLAGS flags)
+{
+//   PDN_CLR(PDN_GPIO);
+   if(flags>GPIO_PIN_MAX)
+   {
+      ASSERT(0);
+      return DCL_HANDLE_INVALID;
+   }
+   if(eDev==DCL_GPIO)
+   {
+      return (DCL_GPIO_MAGIC_NUM | flags);
+   }
+   else if(eDev==DCL_GPO)
+   {
+      return (DCL_GPO_MAGIC_NUM | flags);
+   }
+   else if(eDev==DCL_GPIO_CLK)
+   {
+	   return (DCL_GPIO_CLK_MAGIC_NUM | flags);
+   }
+   else
+   {
+      EXT_ASSERT(0,eDev,flags,0);
+      return DCL_HANDLE_INVALID;
+   }	
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_ReadData
+*
+* DESCRIPTION
+*  This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURN VALUES
+*	STATUS_UNSUPPORTED: 
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_WriteData
+*
+* DESCRIPTION
+*  This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_Configure
+*
+* DESCRIPTION
+*  This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_RegisterCallback
+*
+* DESCRIPTION
+*  This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_Control
+*
+* DESCRIPTION
+*  This function is to send command to control the GPIO module.
+*
+* PARAMETERS
+*	handle - a valid handle return by DclGPIO_Open()
+*  cmd   - a control command for GPIO module
+*          1. GPIO_CMD_READ: to read the input value from the GPIO port contain in handle.
+*          2. GPIO_CMD_WRITE_LOW: to write low to the output of GPIO port contain in handle.
+*          3. GPIO_CMD_WRITE_HIGH: to write high to the output of  GPIO port contain in handle.
+*          4. GPIO_CMD_SET_MODE_0: to set the mode of the GPIO port contain in handle as mode 0.
+*          5. GPIO_CMD_SET_MODE_1: to set the mode of the GPIO port contain in handle as mode 1.
+*          6. GPIO_CMD_SET_MODE_2: to set the mode of the GPIO port contain in handle as mode 2.
+*          7. GPIO_CMD_SET_MODE_3: to set the mode of the GPIO port contain in handle as mode 3.
+*          8. GPIO_CMD_SET_DIR_OUT: to set the direction of the GPIO port as output.
+*          9. GPIO_CMD_SET_DIR_IN: to set the direction of the GPIO port as input.
+*         10. GPIO_CMD_RETURN_MODE: to get the mode of the GPIO port
+*         11. GPIO_CMD_RETURN_DIR: to get the direction of the GPIO port
+*         12. GPIO_CMD_RETURN_OUT: to return the output value of the GPIO port
+*         13. GPIO_CMD_ENABLE_PULL: to enable the pull resister for a GPIO port
+*         14. GPIO_CMD_DISABLE_PULL: to disenable the pull resister for a GPIO port
+*         15. GPIO_CMD_SET_PULL_HIGH: to select the pull up for a GPIO port
+*         16. GPIO_CMD_SET_PULL_LOW: to select the pull down for a GPIO port
+*         17. GPIO_CMD_SET_DINV: to set the inversion of a GPIO port
+*         18. GPIO_CMD_SET_DEBUG: to enable or disable debug mode
+*         19. GPIO_CMD_SET_CLK_OUT: to set the clock frequency for a clock output
+*
+*         20. GPO_CMD_RETURN_MODE: to get the mode of the GPO port
+*         21. GPO_CMD_RETURN_OUT: to return the output value of the GPO port
+*         22. GPO_CMD_WRITE_HIGH: to write high to the output of  GPO port contain in handle.
+*         23. GPO_CMD_WRITE_LOW: to write low to the output of GPO port contain in handle.
+*         24. GPO_CMD_MODE_SET_0: to set the mode of the GPIO port contain in handle as mode 0.
+*         25. GPO_CMD_MODE_SET_1: to set the mode of the GPI1 port contain in handle as mode 1.
+*         26. GPO_CMD_MODE_SET_2: to set the mode of the GPI2 port contain in handle as mode 2.
+*         27. GPO_CMD_MODE_SET_3: to set the mode of the GPI3 port contain in handle as mode 3.
+
+*         28. GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK_T: to set the direction of the GPIO port as output without IRQ protect.
+*         29. GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK_T:  to set the direction of the GPIO port as input without IRQ protect
+*         30. GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK_T:  to write high to the output of  GPIO port contain in handle without IRQ protect.
+*         31. GPIO_CMD_WRITE_LOW_NO_IRQ_MASK_T:	  to write low to the output of GPIO port contain in handle without IRQ protect.
+*         32. GPIO_CMD_READ_NO_IRQ_MASK_T:		  to read the input value from the GPIO port contain in handle without IRQ protect..
+
+*         33. GPIO_CMD_WRITE_FOR_SPI_T: 
+*  data - for 1. GPIO_CMD_READ: 
+*          1. GPIO_CMD_READ: pointer to a GPIO_CTRLS structure
+*          2. GPIO_CMD_WRITE_LOW:		NULL.
+*          3. GPIO_CMD_WRITE_HIGH:		NULL.
+*          4. GPIO_CMD_SET_MODE_0:		NULL.
+*          5. GPIO_CMD_SET_MODE_1:		NULL.
+*          6. GPIO_CMD_SET_MODE_2:		NULL.
+*          7. GPIO_CMD_SET_MODE_3:		NULL.
+*          8. GPIO_CMD_SET_DIR_OUT:		NULL.
+*          9. GPIO_CMD_SET_DIR_IN:		NULL.
+*         10. GPIO_CMD_RETURN_MODE: pointer to a GPIO_CTRL_RETURN_MODE_T structure
+*         11. GPIO_CMD_RETURN_DIR:  pointer to a GPIO_CTRL_SET_DIR_T structure
+*         12. GPIO_CMD_RETURN_OUT:  pointer to a GPIO_CTRL_RETURN_OUT_T structure
+*         13. GPIO_CMD_ENABLE_PULL:		NULL.
+*         14. GPIO_CMD_DISABLE_PULL:	NULL.
+*         15. GPIO_CMD_SET_PULL_HIGH:	NULL.	
+*         16. GPIO_CMD_SET_PULL_LOW:	NULL.
+*         17. GPIO_CMD_SET_DINV:  pointer to a GPIO_CTRL_SET_DINV_T structure
+*         18. GPIO_CMD_SET_DEBUG: pointer to a GPIO_CTRL_SET_DEBUG_T structure
+*         19. GPIO_CMD_SET_CLK_OUT: pointer to a GPIO_CTRL_SET_CLK_OUT_T structure
+*
+*         20. GPO_CMD_RETURN_MODE: pointer to a GPO_CTRL_RETURN_MODE_T structure
+*         21. GPO_CMD_RETURN_OUT:  pointer to a GPO_CTRL_RETURN_OUT_T structure
+*         22. GPO_CMD_WRITE_HIGH: NULL.
+*         23. GPO_CMD_WRITE_LOW:  NULL.
+*         24. GPO_CMD_MODE_SET_0: NULL..
+*         25. GPO_CMD_MODE_SET_1: NULL..
+*         26. GPO_CMD_MODE_SET_2: NULL.
+*         27. GPO_CMD_MODE_SET_3: NULL.
+
+*         28. GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK_T: NULL.
+*         29. GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK_T:  NULL.
+*         30. GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK_T:  NULL.
+*         31. GPIO_CMD_WRITE_LOW_NO_IRQ_MASK_T:	  NULL.
+*         32. GPIO_CMD_READ_NO_IRQ_MASK_T:		  pointer to a GPIO_CTRLS structure
+
+*         33. GPIO_CMD_WRITE_FOR_SPI_T: pointer to
+* RETURNS
+*	STATUS_OK - command is executed successfully.
+*	STATUS_FAIL - command is failed.
+*  STATUS_INVALID_CMD - The command is invalid.
+*  STATUS_INVALID_HANDLE - The handle is invalid.
+*  STATUS_INVALID_CTRL_DATA - The ctrl data is not valid.
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+   kal_int16  port; 
+   port= 0x0000FFFF & handle;
+
+   if(DCL_HANDLE_INVALID==handle)
+   {
+   	return STATUS_FAIL;
+   }
+
+   if(DCL_GPIO_IS_HANDLE_MAGIC(handle))
+   {
+	   switch(cmd)
+	   {
+         case GPIO_CMD_READ:
+         {
+            GPIO_CTRL_READ_T   *prRead;
+            prRead = &(data->rRead);
+            prRead->u1IOData = GPIO_ReadIO(port);
+            break;
+         }
+         case GPIO_CMD_WRITE_LOW:
+         {
+            GPIO_WriteIO(GPIO_IO_LOW, port);
+            break;
+         }
+         case GPIO_CMD_WRITE_HIGH:
+         {
+            GPIO_WriteIO(GPIO_IO_HIGH, port);
+            break;
+         } 
+         case GPIO_CMD_SET_MODE_0:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_0);
+            break;
+         }
+         case GPIO_CMD_SET_MODE_1:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_1);
+            break;
+         }
+         case GPIO_CMD_SET_MODE_2:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_2);
+            break;		   	  	
+         }
+         case GPIO_CMD_SET_MODE_3:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_3);
+            break;			   	  	
+         }
+         case GPIO_CMD_SET_MODE_4: //mode4-7 only for chip support more than 3bit mode control.
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_4);
+            break;
+         }
+         case GPIO_CMD_SET_MODE_5:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_5);
+            break;
+         }
+         case GPIO_CMD_SET_MODE_6:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_6);
+            break;	
+         }
+         case GPIO_CMD_SET_MODE_7:
+         {
+            GPIO_ModeSetup(port, GPIO_MODE_7);
+            break;	
+         } 	  
+         case GPIO_CMD_SET_DIR_OUT:
+         {
+            GPIO_InitIO(GPIO_DIR_OUT,port);
+            break;
+         }
+         case GPIO_CMD_SET_DIR_IN:
+         {
+            GPIO_InitIO(GPIO_DIR_IN,port);
+            break;		   			
+         }
+         case GPIO_CMD_RETURN_MODE:
+         {
+            GPIO_CTRL_RETURN_MODE_T   *prReturnMode;
+            prReturnMode = &(data->rReturnMode);
+            prReturnMode->u1RetMode = GPIO_ReturnMode(port);
+            break;
+         }
+         case GPIO_CMD_RETURN_DIR:
+         {
+            GPIO_CTRL_RETURN_DIR_T   *prReturnDir;
+            prReturnDir = &(data->rReturnDir);
+            prReturnDir->u1RetDirData =GPIO_ReturnDir(port);
+            break;
+         }
+         case GPIO_CMD_RETURN_OUT:
+         {
+            GPIO_CTRL_RETURN_OUT_T   *prReturnOut;
+            prReturnOut = &(data->rReturnOut);
+            prReturnOut->u1RetOutData = GPIO_ReturnDout(port);
+            break;
+         }
+         case GPIO_CMD_ENABLE_PULL:
+         {
+            GPIO_PullenSetup(port, (kal_bool)GPIO_PULL_ENABLE);
+            break;
+         }
+         case GPIO_CMD_DISABLE_PULL:
+         {
+            GPIO_PullenSetup(port, (kal_bool)GPIO_PULL_DISABLE);
+            break;
+         }
+         case GPIO_CMD_SET_PULL_HIGH:
+         {
+            GPIO_PullSelSetup(port,(kal_bool) GPIO_PULL_HIGH);
+            break;
+         }
+         case GPIO_CMD_SET_PULL_LOW:
+         {
+            GPIO_PullSelSetup(port, (kal_bool)GPIO_PULL_LOW);
+            break;
+         }   
+         case GPIO_CMD_SET_DINV:
+         {
+            GPIO_CTRL_SET_DINV_T   *prSetDinv;
+            prSetDinv = &(data->rSetDinv);
+            GPIO_DinvSetup(port,(kal_bool)( prSetDinv->fgSetDinv));
+            break;
+         }
+         case GPIO_CMD_SET_DEBUG:
+         {
+//            GPIO_CTRL_SET_DEBUG_T   *prSetDebug;
+//            prSetDebug = &(data->rSetDebug);
+//            GPIO_SetDebugMode((kal_bool)(prSetDebug->fgSetDebug));
+            break;
+         }
+         #ifdef __CUST_NEW__
+         case GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK: 
+         {
+            GPIO_InitIO_FAST(GPIO_DIR_OUT,port);
+            break;
+         }
+         case GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK:
+         {
+            GPIO_InitIO_FAST(GPIO_DIR_IN,port);
+            break;
+         }
+         case GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK:
+         {
+            GPIO_WriteIO_FAST(GPIO_IO_HIGH,port);
+            break;
+         }
+         case GPIO_CMD_WRITE_LOW_NO_IRQ_MASK:
+         {
+            GPIO_WriteIO_FAST(GPIO_IO_LOW,port);
+            break;
+         }
+		  case GPIO_CMD_READ_NO_IRQ_MASK:
+         {
+            GPIO_CTRL_READ_T   *prRead;
+            prRead = &(data->rRead);
+            prRead->u1IOData = GPIO_ReadIO_FAST(port);
+            break;
+         }
+         #endif
+         case GPIO_CMD_WRITE_FOR_SPI:
+         {
+            GPIO_CTRL_WRITE_FOR_SPI_T *prWrite;
+            prWrite = &(data->rWriteSpi);
+            GPIO_WriteIO_FAST2(prWrite->data,prWrite->no,prWrite->remainder_shift);
+            break;
+         }		
+         case GPIO_CMD_SET_OWNERSHIP_TO_MD:
+         {
+         	gpio_set_ownership(port,GPIO_MD_OWNERSHIP);
+         	break;
+         }
+         case GPIO_CMD_SET_OWNERSHIP_TO_AP:
+         {
+         	gpio_set_ownership(port,GPIO_AP_OWNERSHIP);
+         	break;
+         }
+         case GPIO_CMD_SET_DRIVE:
+         {
+         	GPIO_CTRL_SET_DRIVE_T *prDrive;
+         	prDrive = &(data->rSetDrive);
+         	if(gpio_set_drive(port,prDrive->u1DriveMode)!=0)
+         	{
+         	 	return STATUS_FAIL;	
+         	}
+         	break;
+         }
+         case GPIO_CMD_RETURN_DRIVE:
+         {
+//         	GPIO_CTRL_SET_DRIVE_T *prDrive;
+//         	prDrive = &(data->rReturnDrive);
+//         	prDrive->u1DriveMode = gpio_get_drive_value(port);
+         	break;
+         }
+         case GPIO_CMD_RETURN_OWNERSHIP:
+         {
+         	GPIO_CTRL_RETURN_OWNERSHIP_T *prOwnership;
+         	prOwnership = &(data->rReturnOwnership);
+         	prOwnership->u1OwnerShip = gpio_get_ownership(port);
+         	break;
+         }
+         default:
+            EXT_ASSERT(0,handle,cmd,0);
+            return STATUS_INVALID_CMD;
+      }
+   }
+   else if(DCL_GPO_IS_HANDLE_MAGIC(handle))
+   {
+      switch(cmd)
+      {
+         case GPO_CMD_MODE_SET_0:
+         {
+//            GPO_ModeSetup(port,GPO_MODE_0);
+            break;
+         }
+         case GPO_CMD_MODE_SET_1:
+         {
+//            GPO_ModeSetup(port,GPO_MODE_1);
+            break;
+         }
+         case GPO_CMD_MODE_SET_2:
+         {
+//            GPO_ModeSetup(port,GPO_MODE_2);
+            break;
+         }
+         case GPO_CMD_MODE_SET_3:
+         {
+//            GPO_ModeSetup(port,GPO_MODE_3);
+            break;
+         }
+         case GPO_CMD_WRITE_LOW :
+         {
+//            GPO_WriteIO(port,GPO_IO_LOW);
+            break;
+         }
+         case GPO_CMD_WRITE_HIGH:
+         {
+//            GPO_WriteIO(port,GPO_IO_HIGH);
+            break;
+         }
+         case GPO_CMD_RETURN_OUT:
+         {
+//            GPO_CTRL_RETURN_OUT_T   *prReturnOut;
+//            prReturnOut = &(data->oReturnOut);
+//            prReturnOut->u1RetOutData = GPO_ReturnDout(port);
+            break;
+         }
+         case GPO_CMD_RETURN_MODE:
+         {
+//            GPO_CTRL_RETURN_MODE_T   *prReturnMode;
+//            prReturnMode = &(data->oReturnMode);
+//            prReturnMode->u1RetMode = GPO_ReturnMode(port);
+            break;
+         }
+         default:
+            EXT_ASSERT(0,handle,cmd,0);
+            return STATUS_INVALID_CMD;
+      }
+   }
+   else if (DCL_GPIO_CLK_IS_HANDLE_MAGIC(handle))
+   {
+      switch(cmd)
+      {
+         case GPIO_CMD_SET_CLK_OUT:
+         {
+         	/* //not support in MT6290
+            kal_uint8 mode=0;
+            kal_uint8 clknum=0;
+            GPIO_CTRL_SET_CLK_OUT_T   *prSetClkOut;
+            prSetClkOut = &(data->rSetClkOut);
+            mode = get_mode(prSetClkOut->u2Mode);
+            clknum=get_clknum(prSetClkOut->u2ClkNum);
+            GPIO_SetClkOut(clknum,(gpio_clk_mode)mode);
+            */
+            break;
+         }
+         case GPIO_CMD_SET_CLK_DIV:
+         {
+         	/* //not support in MT6290
+            kal_uint8 clknum=0;
+            GPIO_CTRL_SET_CLK_DIV_T *prSetClkDiv;
+            prSetClkDiv= &(data->rSetClkDiv);
+            clknum=get_clknum(prSetClkDiv->u2ClkNum);
+            GPIO_SetClkDiv(clknum,prSetClkDiv->u2Div);
+            */
+            break;
+         }
+         default:
+            EXT_ASSERT(0,handle,cmd,0);
+            return STATUS_INVALID_CMD;
+      }
+   }
+   else
+   {
+      EXT_ASSERT(0,handle,cmd,0);
+      return STATUS_INVALID_DCL_HANDLE;
+   }  
+   return STATUS_OK;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+*  DclGPIO_Close
+*
+* DESCRIPTION
+*  This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclGPIO_Close(DCL_HANDLE handle)
+{
+   return STATUS_OK;
+}
+
+
+#else /*!defined(DRV_GPIO_NOT_EXIST) && !defined(DRV_GPIO_OFF)*/
+
+DCL_STATUS DclGPIO_Initialize(void)
+{
+   return STATUS_FAIL;
+}
+
+DCL_HANDLE DclGPIO_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+   return DCL_HANDLE_INVALID;
+}
+
+DCL_STATUS DclGPIO_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclGPIO_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclGPIO_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+   return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclGPIO_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+   return STATUS_FAIL;
+}
+
+DCL_STATUS DclGPIO_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+   return STATUS_FAIL;
+}
+
+DCL_STATUS DclGPIO_Close(DCL_HANDLE handle)
+{
+   return STATUS_FAIL;
+}
+#endif /*!defined(DRV_GPIO_NOT_EXIST) && !defined(DRV_GPIO_OFF)*/
+
diff --git a/mcu/driver/devdrv/gpio/src/drv_gpio.c b/mcu/driver/devdrv/gpio/src/drv_gpio.c
new file mode 100644
index 0000000..9971f3f
--- /dev/null
+++ b/mcu/driver/devdrv/gpio/src/drv_gpio.c
@@ -0,0 +1,1447 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drv_gpio.c
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Low level GPIO driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 05 06 2022 yao.xue
+ * [MOLY00851720] [FM350][MIPI][IO_Driving][clock speed][zontn.wang]The MIPI IO Driving strength and clock speed setting
+ * modify GPIO IOCFG regbase.
+ *
+ * 11 16 2020 zhiqiang.yu
+ * [MOLY00595491] [Colgin]MD GPIO DRV Patchback From T700 Branch
+ * 	
+ * 	.
+ *
+ * 11 11 2020 zhiqiang.yu
+ * [MOLY00593568] [MT6877]Call For Check In MD GPIO Drv
+ * 	
+ * 	.
+ *
+ * 07 16 2020 zhiqiang.yu
+ * [MOLY00546611] [MT6833]Call For Check In MD GPIO Driver
+ * 	
+ * 	.
+ *
+ * 01 21 2020 zhiqiang.yu
+ * [MOLY00476172] [MT6853]Call For Check In GPIO Drv
+ * 	
+ * 	.
+ *
+ * 12 04 2019 zhiqiang.yu
+ * [MOLY00463572] [MMRF] Ddie driving customization development
+ * 	
+ * 	.GPIO DRIVER
+ *
+ * 09 24 2019 zhiqiang.yu
+ * [MOLY00443103] [MT6873]Check in md gpio driver
+ * 	
+ * 	.
+ *
+ * 06 18 2019 zhiqiang.yu
+ * [MOLY00413533] [MT6297]Fix GPIO Drv build Warning about LTO
+ * 	
+ * 	.
+ *
+ * 12 07 2018 zhiqiang.yu
+ * [MOLY00371362] [Pertus]check in gpio drv
+ * 	
+ * 	.fix build error
+ *
+ * 08 21 2018 zhiqiang.yu
+ * [MOLY00347417] [MT6297][VMOLY]check in md gpio&eint drv
+ * 	
+ * 	.fix build error
+ *
+ * 08 02 2018 zhiqiang.yu
+ * [MOLY00343825] [MT6779]Call For Check In,gpio driver
+ * 	
+ * 	.
+ *
+ * 04 03 2018 zhiqiang.yu
+ * remove ownership@6290.
+ *
+ * 12 18 2017 zhiqiang.yu
+ * [MOLY00296840] [EIGER]call for mt3967 gpio driver
+ * 	
+ * 	.
+ *
+ * 11 01 2017 zhiqiang.yu
+ * [MOLY00244517] [MT6295M]fix build error,for gpio driver.patch back from LR12A.MP2.MT6295M.DEV.
+ *
+ * 10 30 2017 zhiqiang.yu
+ * [MOLY00286048] [MT6765]check in gpio drv for MT6765.
+ *
+ * 08 24 2017 zhiqiang.yu
+ * [MOLY00273500] [MT6771]check in md gpio driver
+ * 	
+ * 	.
+ *
+ * 06 12 2017 zhiqiang.yu
+ * [MOLY00244007] [MT6739]check in gpio driver for zion
+ * 	
+ * 	.
+ *
+ * 11 16 2016 zhiqiang.yu
+ * [MOLY00213576] [MT6763]eint&gpio driver check in.
+ *
+ * 02 22 2016 zhiqiang.yu
+ * [MOLY00165689] Code Inspection and MSBB Scan
+ * Fix high impact defect.
+ *
+ * 08 04 2015 zhiqiang.yu
+ * [MOLY00135213] check in gpiodriver code for mt6797 project
+ * .
+ *
+ * 07 22 2015 zhiqiang.yu
+ * [MOLY00131033] enable sp set gpio mode funtion
+ * 	<saved by Perforce>
+ *
+ * 06 17 2015 zhiqiang.yu
+ * [MOLY00121904] checkin md eint code for mt6755
+ * .
+ *
+ * 06 16 2015 zhiqiang.yu
+ * [MOLY00121625] checkin md gpio code for mt6755
+ * 	.
+ *
+ * 06 30 2014 chuanbo.liao
+ * [MOLY00070787] [tk6291]fix 6291 build error
+ * [6291]modify the EINT/GPIO base address
+ *
+ * 05 10 2013 da.wang
+ * [MOLY00022149] [MT6290E1][TRUNK] Add GPIO driver API for Meta mode solution
+ * Upload GPIO driver API for meta mode.
+ *
+ * 02 04 2013 da.wang
+ * [MOLY00009904] [GPIO/EINT] Rename MT7280 to MT6290 on MOLY trunk
+ * .rename GPIO/EINT related keywords MT7208 to MT6290 in MOLY
+ ****************************************************************************/
+#include "drv_comm.h"
+#include "drv_gpio.h"
+#include "kal_general_types.h"
+#include "devdrv_ls.h"
+
+
+//========================================================================
+//  Global variable
+//========================================================================   
+
+#ifdef __CUST_NEW__
+   #if defined(DRV_GPIO_8_MODES) || defined(DRV_GPIO_MODE_4BITS)
+   extern const kal_uint32  gpio_mode_allowed[][8];
+   #else //defined(DRV_GPIO_8_MODES) || defined(DRV_GPIO_MODE_4BITS)
+extern const kal_uint32  gpio_mode_allowed[][4];
+   #endif //defined(DRV_GPIO_8_MODES) || defined(DRV_GPIO_MODE_4BITS)
+extern const kal_uint32  gpio_dir_out_allowed[];
+extern const kal_uint32  gpio_dir_in_allowed[];
+extern const kal_uint16  gpo_mode_allowed[];
+extern kal_uint32  gpio_check_for_write[];
+extern kal_uint32  gpio_check_for_read[];
+extern kal_uint16  gpo_check_for_write[];
+extern kal_bool   gpio_debug_enable;
+#endif /* __CUST_NEW__ */
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+//========================================================================
+/**
+ *  @brief     get direction register value of pin
+ *  @param  gpio_pin :  The GPIO pin to be read.
+ *  @return   return the direction register value of gpio_pin
+ *		      0:                 the direction of gpio is input
+ *            1:                 the direction of gpio is output
+ *            GPIO_FAIL:   gpio_pin is out of range
+ */
+kal_int32 gpio_get_dir_value (gpio_pin_e gpio_pin)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+	unsigned long pos;
+	unsigned long bit;
+	unsigned long data;
+
+	if (gpio_pin>GPIO_PIN_MAX)
+	{
+		GPIO_ERR("The gpio pin is out of range of MAX num (%d) !!!!", GPIO_PIN_MAX);
+		return GPIO_FAIL;
+	}	
+
+	pos = gpio_pin/32;
+	bit = gpio_pin%32;
+
+	data = DRV_Reg32((GPIO_DIR1 + pos*0x10));
+
+	return ((data&(1<<bit))?1:0);	
+
+#endif
+}
+
+// ----------------------------------------------------------
+/**
+ *  @brief	Set GPIO_DIR input or output
+ *  @param  gpio_pin :  The GPIO pin to be set.
+ *  @param  direction : The direction to be set in gpio_pin.
+ *  					1: set as output pin
+ *					0: set as input pin
+ *  @return  GPIO_OK : set successful,  GPIO_FAIL : set failed
+ */
+static kal_int32 _GPIO_Set_Direction(gpio_pin_e gpio_pin, kal_uint32 direction)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+	unsigned long pos;
+	unsigned long bit;
+	//unsigned long data;
+
+	if (gpio_pin>GPIO_PIN_MAX)
+	{
+		GPIO_ERR("The gpio pin is out of range of MAX num (%d) !!!!", GPIO_PIN_MAX);
+		return GPIO_FAIL;
+	}	
+
+	pos = gpio_pin/32;
+	bit = gpio_pin%32;
+	if (direction == GPIO_AS_OUTPUT)
+		DRV_WriteReg32(GPIO_DIR_SET(pos),1<<bit);
+	else
+		DRV_WriteReg32(GPIO_DIR_CLR(pos),1<<bit);
+
+	return GPIO_OK; 
+
+#endif
+}
+
+
+
+//========================================================================
+/*-----------------------------------------------------------------------*
+*  @brief  Read the input value of the gpio pin.
+*  @param  gpio_pin :   The pin which to read value.
+*  @param  *value	   :	The variable to save value read from the pin, will be 0 or 1.
+*  @return GPIO_OK :   get successful,  GPIO_FAIL : get failed
+*-----------------------------------------------------------------------*/
+kal_int32 GPIO_READ_INPUT_VALUE (gpio_pin_e gpio_pin, kal_uint32 *value)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+	unsigned long pos;
+	unsigned long bit;
+	unsigned long data;
+
+	if (gpio_pin>GPIO_PIN_MAX)
+	{
+		GPIO_ERR("The gpio pin is out of range of MAX num (%d) !!!!", GPIO_PIN_MAX);
+		return GPIO_FAIL;
+	}	
+
+	pos = gpio_pin/32;
+	bit = gpio_pin%32;
+	data = DRV_Reg32((GPIO_DIN1 + pos*0x10));
+	*value=((data&(1<<bit))?1:0);
+
+	return GPIO_OK; 
+
+#endif
+}
+
+
+
+
+// ----------------------------------------------------------
+/**
+ *  @brief	Enable or Disable GPIO_PULLEN specific pin
+ *  @param  gpio_pin :  The GPIO pin to be set.
+ *  @param  pullen : set 1 to enable pull up/down in gpio_pin.
+ *  @return  GPIO_OK : set successful,  GPIO_FAIL : set failed
+ */
+kal_int32 _GPIO_Set_Pullen(gpio_pin_e gpio_pin, kal_uint32 pullen)  
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+	return GPIO_FAIL;	
+#else
+	return GPIO_FAIL;
+#endif
+}
+
+// ----------------------------------------------------------
+/**
+ *  @brief	Set GPIO_PULLSEL to pull-up or pull-down
+ *  @param  gpio_pin :  The GPIO pin to be set.
+ *  @param  updown : set GPIO_PULL_UP to set gpio_pin in pull-up. set GPIO_PULL_DOWN to set gpio_pin pull_down.
+ *  @return  GPIO_OK : set successful,  GPIO_FAIL : set failed
+ */
+kal_int32 _GPIO_Set_Pullsel(gpio_pin_e gpio_pin, kal_uint32 updown)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+	return GPIO_FAIL;	
+#else
+	return GPIO_FAIL;
+#endif
+}
+
+
+/**
+*  @brief  Set pin direction as an output pin.
+*  @param  gpio_pin : The pin which to be set direction to output pin.
+*  @return GPIO_OK : set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 GPIO_SET_DIRECT_OUTPUT (gpio_pin_e gpio_pin)
+{
+	if (gpio_pin>GPIO_PIN_MAX)
+	{
+		GPIO_ERR("The gpio pin is out of range of MAX num (%d) !!!!", GPIO_PIN_MAX);
+		return GPIO_FAIL;
+	}
+	
+	if (GPIO_FAIL == _GPIO_Set_Pullen(gpio_pin, GPIO_DISABLE) )
+	{	return GPIO_FAIL; }
+		
+	if (GPIO_FAIL == _GPIO_Set_Direction(gpio_pin, GPIO_AS_OUTPUT) )
+	{	return GPIO_FAIL; }
+
+	return GPIO_OK;
+}
+
+//========================================================================
+/**
+*  @brief  Set pin direction as an input pin.
+*  @param  gpio_pin	   :	The pin which want to be set.
+*  @param  pull_en	   :   GPIO_ENABLE or GPIO_DISABLE, Set if pull-up/down function is enable. 
+*  @param  pull_updown  :   GPIO_PULL_UP / GPIO_PULL_DOWN, it works only when pull_en is enable.
+*  @return GPIO_OK : set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 GPIO_SET_DIRECT_INPUT (gpio_pin_e gpio_pin, kal_uint32 pull_en, kal_uint32 pull_updown)
+{
+	if (gpio_pin>GPIO_PIN_MAX)
+	{
+		GPIO_ERR("The gpio pin is out of range of MAX num (%d) !!!!", GPIO_PIN_MAX);
+		return GPIO_FAIL;
+	}	
+				/* Step-1 Check GPIO_Mode to make sure the pin can be uesed as GPIO*/
+				//_GPIO_ShareMode_Chk(gpio_pin);
+
+				/* Step-2 set the pull-up/down */
+				// When input, the pullen could be set as required
+				// If the pullen is set, the pullsel should be set.
+	if (GPIO_FAIL == _GPIO_Set_Pullen(gpio_pin, pull_en) )
+	{	return GPIO_FAIL; }
+
+				/* Step-3 set the pull-up/down when gpio is input*/
+	if (GPIO_FAIL == _GPIO_Set_Pullsel(gpio_pin, pull_updown) )
+	{	return GPIO_FAIL; }
+
+				/* Step-4 set the direction to input*/
+	if (GPIO_FAIL == _GPIO_Set_Direction(gpio_pin, GPIO_AS_INPUT) )
+	{	return GPIO_FAIL; }		
+	
+	
+		return GPIO_OK;
+}
+	
+
+//========================================================================
+/**
+*  @brief  set the data inversion parameter of the gpio pin.
+*  @param  gpio_pin :	The pin which is to be set data inversion.
+*  @param  inversion:	The value to be set, will be 0 or 1.
+*					0: disable data inversion
+					1: enable data inversion
+*  @return GPIO_OK :   set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 gpio_set_data_inversion(gpio_pin_e gpio_pin, kal_uint32 inversion)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	return GPIO_FAIL;	
+#else
+	return GPIO_FAIL;
+#endif
+}
+
+
+
+//========================================================================
+/**
+*  @brief  Write the output value of the gpio pin. It only work when the pin is an output pin.
+*  @param  gpio_pin :	The pin which to be set output value.
+*  @param  value	   :	The value which want to be set, can be 0 or 1.
+*  @return GPIO_OK :   set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 GPIO_WRITE_OUTPUT_VALUE (gpio_pin_e gpio_pin, kal_uint32 value)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	unsigned long pos;
+	unsigned long bit;
+	//unsigned long data;
+
+	if (gpio_pin>GPIO_PIN_MAX)
+	{
+		GPIO_ERR("The gpio pin is out of range of MAX num (%d) !!!!", GPIO_PIN_MAX);
+		return GPIO_FAIL;
+	}	
+
+	pos = gpio_pin/32;
+	bit = gpio_pin%32;
+	if (value == GPIO_OUTPUT_HIGH)
+		DRV_WriteReg32(GPIO_DOUT_SET(pos),1<<bit);
+	else
+		DRV_WriteReg32(GPIO_DOUT_CLR(pos),1<<bit);
+
+	return GPIO_OK;	
+#endif
+}
+
+
+/*-----------------------------------------------------------------------*
+* FUNCTION                                                            
+*	GPIO_ReadIO
+*
+* DESCRIPTION                                                           
+*   	This function is to read data from one GPIO pin
+*
+* CALLS  
+*	Read data from one GPIO pin
+*
+* PARAMETERS
+*	port: pin number
+*	
+* RETURNS
+*	1 or 0
+*
+* GLOBALS AFFECTED
+*   external_global
+*-----------------------------------------------------------------------*/
+char GPIO_ReadIO(kal_int16 port)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+	kal_uint32 input_val = 0;
+	if(GPIO_READ_INPUT_VALUE((gpio_pin_e)port, &input_val) != GPIO_OK)
+	{
+		GPIO_ERR("\tGPIO_ReadIO: read the value of port[%d] failed!! ",port);
+	}
+	return (char)input_val;
+#endif
+}
+
+
+/*
+* FUNCTION                                                            
+*	GPIO_WriteIO
+*
+* DESCRIPTION                                                           
+*   	This function is to write data to one GPIO port
+*
+* CALLS  
+*	Write data to one GPIO port
+*
+* PARAMETERS
+*	data: KAL_TRUE(1) or KAL_FALSE(0)
+*	port: gpio pin number
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global        
+*/
+void GPIO_WriteIO(char data, kal_int16 port)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	GPIO_WRITE_OUTPUT_VALUE((gpio_pin_e)port,data);
+#endif
+}
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+#define MAX_GPIO_MODE_PER_REG 8
+#define GPIO_MODE_BITS  4
+#endif
+void GPIO_ModeSetup(kal_uint16 pin, kal_uint16 conf_data)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+#if defined(__FPGA__) && defined(MT6295M)
+
+#else
+	unsigned long pos;
+	unsigned long bit;
+	unsigned long data;
+	unsigned long mask = (1L << GPIO_MODE_BITS)-1;
+	unsigned long offset;
+
+	pos = pin/MAX_GPIO_MODE_PER_REG;
+	bit = pin%MAX_GPIO_MODE_PER_REG;
+
+	offset = GPIO_MODE_BITS*bit;
+	
+	data = DRV_Reg32(GPIO_MODE(pos));
+	data &= ~(mask << offset);
+	data |= (conf_data << offset);
+	//to avoid possible race condition with AP,use SET/CLR reg to setup MODE register
+	DRV_WriteReg32(GPIO_MODE_CLR(pos),(mask << (GPIO_MODE_BITS*bit)));
+	DRV_WriteReg32(GPIO_MODE_SET(pos),data);
+#endif	
+#endif	
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_InitIO
+*
+* DESCRIPTION                                                           
+*   	This function is to initialize one GPIO pin as INPUT or OUTPUT
+*
+* CALLS  
+*	Initialize one GPIO pin as INPUT or OUTPUT
+*
+* PARAMETERS
+*	direction: INPUT or OUTPUT
+*	port: pin number
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+void GPIO_InitIO(char direction, kal_int16 port)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	if(GPIO_OUTPUT == direction)
+	{
+		_GPIO_Set_Direction((gpio_pin_e)port,GPIO_OUTPUT);
+	}
+	else
+	{
+		_GPIO_Set_Direction((gpio_pin_e)port,GPIO_INPUT);
+	}
+
+#endif
+}
+
+char GPIO_ReturnMode(kal_int16 port)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+#if defined(__FPGA__) && defined(MT6295M)
+	return GPIO_FAIL;
+#else
+	unsigned long pos;
+	unsigned long bit;
+	unsigned long data;
+	unsigned long mask = (1L << GPIO_MODE_BITS)-1;
+	unsigned long offset;
+
+	pos = port/MAX_GPIO_MODE_PER_REG;
+	bit = port%MAX_GPIO_MODE_PER_REG;
+
+	offset = GPIO_MODE_BITS*bit;
+	
+	data = DRV_Reg32(GPIO_MODE(pos));
+	data = (data >> offset)&mask;
+	return (char)data;
+#endif	
+#else
+	return GPIO_FAIL;
+#endif	
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_ReturnDir
+*
+* DESCRIPTION                                                           
+*   	This function is to report GPIO direction value
+*
+* CALLS  
+*	Report GPIO direction value accoding to input pin
+*
+* PARAMETERS
+*	GPIO pin 
+*	
+* RETURNS
+*	GPIO direction value
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+char GPIO_ReturnDir(kal_int16 port)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	return gpio_get_dir_value(port);
+#endif
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_ReturnDout
+*
+* DESCRIPTION                                                           
+*   	This function is to report GPIO output value
+*
+* CALLS  
+*	Report GPIO output value accoding to input pin
+*
+* PARAMETERS
+*	GPIO pin 
+*	
+* RETURNS
+*	GPIO output value
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+char GPIO_ReturnDout(kal_int16 port)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	return GPIO_FAIL;
+#endif
+}
+
+
+/*
+* FUNCTION                                                            
+*	GPIO_PullenSetup
+*
+* DESCRIPTION                                                           
+*   	This function is to enable or disable the pull up/down of the related GPIO pin.
+*		You can not decide to pull up or down, it is set inside the chip.
+*		And, the setting is different from pin by pin.
+*
+* PARAMETERS
+*	pin : gpio pin number range from 0~63
+*	enable: enable the pull up/down
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*
+*/
+void GPIO_PullenSetup(kal_uint16 pin, kal_bool enable)
+{
+	#ifdef __CUST_NEW__  
+	pin &= (~GPIO_MAGIC_NUM);
+	#endif
+	_GPIO_Set_Pullen(pin,enable);
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_PullSelSetup
+*
+* DESCRIPTION                                                           
+*   	This function is to select pull up/down of the related GPIO pin.
+*
+* PARAMETERS
+*	pin : gpio pin number range from 0~63
+*	enable: enable the pull up/down
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*
+*/
+void GPIO_PullSelSetup(kal_uint16 pin, kal_bool pull_up)
+{
+	#ifdef __CUST_NEW__  
+	pin &= (~GPIO_MAGIC_NUM);
+	#endif
+	_GPIO_Set_Pullsel(pin,pull_up);
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_DinvSetup
+*
+* DESCRIPTION                                                           
+*   	This function is to enable data invert of the related GPIO pin
+*
+* PARAMETERS
+*	pin : gpio pin number range from 0~63
+*	enable: enable the data inversion
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*
+*/
+void GPIO_DinvSetup(kal_uint16 pin, kal_bool enable)
+{
+	#ifdef __CUST_NEW__  
+	pin &= (~GPIO_MAGIC_NUM);
+	#endif
+	gpio_set_data_inversion(pin,enable);
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_SetDebugMode
+*
+* DESCRIPTION                                                           
+*  This function is to set GPIO HW debug mode
+*  currently MT6290 not support this function
+*
+* CALLS  
+*	set GPIO HW debug mode
+*
+* PARAMETERS
+*	enable   - KAL_TRUE: turn on the debug mode
+*             KAL_FALSE: turn off the debug mode
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+void GPIO_SetDebugMode(kal_bool enable)
+{
+	//not support in MT6290
+}
+
+#ifdef __CUST_NEW__
+
+/*
+* FUNCTION                                                            
+*	GPIO_InitIO_FAST
+*
+* DESCRIPTION                                                           
+*   	This function is to initialize one GPIO pin as INPUT or OUTPUT. 
+*  Note that it's for fast access without debug checking and only exists
+*  when __CUST_NEW__ is defined.
+*
+* CALLS  
+*	Initialize one GPIO pin as INPUT or OUTPUT
+*
+* PARAMETERS
+*	direction: INPUT or OUTPUT
+*	port: pin number
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+void GPIO_InitIO_FAST(char direction, kal_int16 port)
+{
+	 #ifdef __GPIO_FAST_DEBUB__
+   if (gpio_debug_enable == KAL_TRUE)
+   {
+      if (direction == 0)
+      {
+      #ifdef __GPIO_CHECK_WARNING__
+         if (!kal_if_lisr()) {
+            if (!((gpio_dir_in_allowed[(kal_uint8)port>>5]) & (1 << (port & 0x1f))))
+            {
+               kal_int32 ret;
+             system_print("GPIO WARNING!! GPIO_InitIO_FAST: Direction Input is not allowed!");
+             ret = sprintf(buff, "pin=%d", port);
+             system_print(buff);
+            }
+         }
+      #elif defined(__GPIO_CHECK_ASSERT__)
+         ASSERT((gpio_dir_in_allowed[(kal_uint8)port>>5]) & (1 << (port & 0x1f)));
+		#endif  /* __GPIO_CHECK_WARNING__ */
+      }
+      else
+      {
+      #ifdef __GPIO_CHECK_WARNING__
+         if (!kal_if_lisr()) {
+            if (!((gpio_dir_out_allowed[(kal_uint8)port>>5]) & (1 << (port & 0x1f))))
+            {
+               kal_int32 ret;
+             system_print("GPIO WARNING!! GPIO_InitIO_FAST: Direction Output is not allowed!");
+             ret = sprintf(buff, "pin=%d", port);
+             system_print(buff);
+            }
+         }
+      #elif defined(__GPIO_CHECK_ASSERT__)
+         ASSERT((gpio_dir_out_allowed[(kal_uint8)port>>5]) & (1 << (port & 0x1f)));
+		#endif  /* __GPIO_CHECK_WARNING__ */
+      }
+	  gpio_check_for_write[(kal_uint8)port>>5] |= (1 << (port & 0x1f));
+	  gpio_check_for_read[(kal_uint8)port>>5] |= (1 << (port & 0x1f));
+   }
+   #endif /* __GPIO_FAST_DEBUB__ */
+
+   #ifdef __CUST_NEW__   	
+   port &= (~GPIO_MAGIC_NUM);
+   #endif /* __CUST_NEW__ */
+	if(GPIO_OUTPUT == direction)
+	{
+		GPIO_SET_DIRECT_OUTPUT((gpio_pin_e)port);
+	}
+	else
+	{
+		_GPIO_Set_Direction((gpio_pin_e)port,GPIO_INPUT);
+	}
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_WriteIO_FAST
+*
+* DESCRIPTION                                                           
+*   	This function is to write data to one GPIO port
+*  Note that it's for fast access without debug checking and only exists
+*  when __CUST_NEW__ is defined.
+*
+* CALLS  
+*	Write data to one GPIO port
+*
+* PARAMETERS
+*	data: KAL_TRUE(1) or KAL_FALSE(0)
+*	port: gpio pin number
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global        
+*/
+void GPIO_WriteIO_FAST(char data, kal_int16 port)
+{
+   #ifdef __GPIO_FAST_DEBUB__
+   if ((gpio_debug_enable == KAL_TRUE) && 
+	   (gpio_check_for_write[(kal_uint8)port>>5] & (1 << (port & 0x1f))))
+   {
+
+      #ifdef __GPIO_CHECK_WARNING__
+      if (!kal_if_lisr()) {
+         kal_uint16 mode;
+         mode = GPIO_ReturnMode(port);
+         if (mode != 0)
+         {
+            kal_int32 ret;
+          system_print("GPIO WARNING!! GPIO_WriteIO_FAST: mode is not correct.");
+          ret = sprintf(buff, "pin=%d, mode=%d", port, mode);
+          system_print(buff);
+         }
+      #elif defined(__GPIO_CHECK_ASSERT__)
+         ASSERT(GPIO_ReturnMode(port) == 0);
+		#endif  /* __GPIO_CHECK_WARNING__ */
+      }
+      #ifdef __GPIO_CHECK_WARNING__
+      if (!kal_if_lisr()) {
+         char dir;
+         dir = GPIO_ReturnDir(port);
+         if (dir != 1)
+         {
+            kal_int32 ret;
+          system_print("GPIO WARNING!! GPIO_WriteIO_FAST: direction is not correct.");
+          ret = sprintf(buff, "pin=%d, direction=%d", port, dir);
+          system_print(buff);
+         }
+      }
+      #elif defined(__GPIO_CHECK_ASSERT__)
+      ASSERT(GPIO_ReturnDir(port) == 1);
+		#endif  /* __GPIO_CHECK_WARNING__ */
+	  gpio_check_for_write[(kal_uint8)port>>5] &= (~(1 << (port & 0x1f)));
+   }
+   #endif /* __GPIO_FAST_DEBUB__ */
+
+   	#ifdef __CUST_NEW__  
+	port &= (~GPIO_MAGIC_NUM);
+	#endif
+	GPIO_WRITE_OUTPUT_VALUE((gpio_pin_e)port,data);
+
+}
+
+/*
+* FUNCTION                                                            
+*	GPIO_ReadIO_FAST
+*
+* DESCRIPTION                                                           
+*   	This function is to read data from one GPIO pin.
+*  Note that it's for fast access without debug checking and only exists
+*  when __CUST_NEW__ is defined.
+*
+* CALLS  
+*	Read data from one GPIO pin
+*
+* PARAMETERS
+*	port: pin number
+*	
+* RETURNS
+*	1 or 0
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+char GPIO_ReadIO_FAST(kal_int16 port)
+{
+	kal_uint32 input_val;
+
+   #ifdef __GPIO_FAST_DEBUB__
+   if ((gpio_debug_enable == KAL_TRUE) && 
+	   (gpio_check_for_read[(kal_uint8)port>>5] & (1 << (port & 0x1f))))
+   {
+      #ifdef __GPIO_CHECK_WARNING__
+      if (!kal_if_lisr()) {
+         kal_uint16 mode;
+         char dir;
+         mode = GPIO_ReturnMode(port);
+         dir = GPIO_ReturnDir(port);
+         if ((mode != 0) || (dir != 0))
+         {
+            kal_int32 ret;
+          system_print("GPIO WARNING!! GPIO_ReadIO_FAST: mode or direction is not correct.");
+          ret = sprintf(buff, "pin=%d, mode=%d, direction=%d", port, mode, dir);
+          system_print(buff);
+         }
+      }
+      #elif defined(__GPIO_CHECK_ASSERT__)
+      ASSERT(GPIO_ReturnMode(port) == 0);
+      ASSERT(GPIO_ReturnDir(port) == 0);
+		#endif  /* __GPIO_CHECK_WARNING__ */
+	  gpio_check_for_read[(kal_uint8)port>>5] &= (~(1 << (port & 0x1f)));
+   }
+   #endif /* __GPIO_FAST_DEBUB__ */
+
+   #ifdef __CUST_NEW__   	
+   port &= (~GPIO_MAGIC_NUM);
+   #endif /* __CUST_NEW__ */
+   
+	if(GPIO_READ_INPUT_VALUE((gpio_pin_e)port, &input_val) != GPIO_OK)
+	{
+		GPIO_ERR("\tGPIO_ReadIO: read the value of port[%d] failed!! ",port);
+	}
+	return (char)input_val;
+}
+
+
+#endif
+
+//#pragma arm section code = "INTERNCODE"
+/*
+* FUNCTION                                                            
+*	GPIO_WriteIO_FAST2
+*
+* DESCRIPTION                                                           
+*   	This function is to write data to one GPIO port
+*  Note that it's for faster access without debug checking.
+*
+* CALLS  
+*	Write data to one GPIO port
+*
+* PARAMETERS
+*	data: KAL_TRUE(1) or KAL_FALSE(0)
+*	no: no = port/16; port: GPIO port number
+*	remainder_shift: remainder_shift = 1<<(port%16);
+*
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global        
+*/
+void DEVDRV_LS_INTERNCODE GPIO_WriteIO_FAST2(char data, kal_uint16 no, kal_uint16 remainder_shift)
+{
+	kal_uint32 gpio_pin,shift_bit;
+
+   #if defined(__CUST_NEW__)&&defined(__GPIO_FAST_DEBUB__)
+   if ((gpio_debug_enable == KAL_TRUE) && 
+	   (gpio_check_for_write[(kal_uint8)port>>5] & (1 << (port & 0x1f))))
+   {
+      kal_int16 port;
+      kal_uint16 index;
+
+      for (index = 0; index < 16; index++)
+      {
+         if (remainder_shift & (1 << index))
+            break;
+      }
+      port = (kal_int16)((no<<4)+(index&0x000f));
+
+      #ifdef __GPIO_CHECK_WARNING__
+      if (!kal_if_lisr()) {
+         kal_uint16 mode;
+         mode = GPIO_ReturnMode(port);
+         if (mode != 0)
+         {
+            kal_int32 ret;
+          system_print("GPIO WARNING!! GPIO_WriteIO_FAST: mode is not correct.");
+          ret = sprintf(buff, "pin=%d, mode=%d", port, mode);
+          system_print(buff);
+         }
+
+      #elif defined(__GPIO_CHECK_ASSERT__)
+         ASSERT(GPIO_ReturnMode(port) == 0);
+		#endif  /* __GPIO_CHECK_WARNING__ */
+      }
+      #ifdef __GPIO_CHECK_WARNING__
+      if (!kal_if_lisr()) {
+         char dir;
+         dir = GPIO_ReturnDir(port);
+         if (dir != 1)
+         {
+            kal_int32 ret;
+          system_print("GPIO WARNING!! GPIO_WriteIO_FAST: direction is not correct.");
+          ret = sprintf(buff, "pin=%d, direction=%d", port, dir);
+          system_print(buff);
+         }
+      }
+      #elif defined(__GPIO_CHECK_ASSERT__)
+      ASSERT(GPIO_ReturnDir(port) == 1);
+		#endif  /* __GPIO_CHECK_WARNING__ */
+	  gpio_check_for_write[(kal_uint8)port>>5] &= (~(1 << (port & 0x1f)));
+   }
+   #endif /* __GPIO_FAST_DEBUB__ */
+   
+  for (shift_bit = 0; shift_bit < 16; shift_bit++)
+  {
+     if (remainder_shift & (1 << shift_bit))
+        break;
+  }
+  gpio_pin = (kal_int16)((no<<4)+(shift_bit&0x000f));
+  
+  GPIO_WRITE_OUTPUT_VALUE((gpio_pin_e)gpio_pin,data);
+
+}
+
+//#pragma arm section code
+
+
+/*conf_data = 0~3*/
+void GPO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
+{
+	//not support in MT6290
+}
+
+
+/*
+* FUNCTION                                                            
+*	GPI_O_WriteIO
+*
+* DESCRIPTION                                                           
+*   	This function is to write data to one GPO pin
+*
+* CALLS  
+*	Write data to one GPO pin
+*
+* PARAMETERS
+*	data: KAL_TRUE(1) or KAL_FALSE(0)
+*	port: gpo pin number
+*	
+* RETURNS
+*	None
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+
+void GPO_WriteIO(char data,kal_int16 port)
+{
+	//not support in MT6290
+}
+
+/*
+* FUNCTION                                                            
+*	GPO_ReturnDout
+*
+* DESCRIPTION                                                           
+*   	This function is to report GPO output value
+*
+* CALLS  
+*	Report GPO output value accoding to input pin
+*
+* PARAMETERS
+*	GPO pin 
+*	
+* RETURNS
+*	GPO output value
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+char GPO_ReturnDout(kal_int16 port)
+{
+	return 0;
+}
+
+
+/*
+* FUNCTION                                                            
+*	GPO_ReturnMode
+*
+* DESCRIPTION                                                           
+*   	This function is to report GPO mode value
+*
+* CALLS  
+*	Report GPO mode value accoding to input pin
+*
+* PARAMETERS
+*	GPO pin 
+*	
+* RETURNS
+*	GPO mode value
+*
+* GLOBALS AFFECTED
+*   external_global
+*/
+char GPO_ReturnMode(kal_int16 port)
+{
+	return 0;
+}
+
+
+/**
+*  @brief  set gpio ownership register
+*  @param  pin_num  : the gpio pin to set ownerhsip
+*  @param  ownership : the ownership register bit value to set ,it should be 0~1
+*                                    0: set ownership to MD
+*                                    1: set ownership to AP
+*  @return GPIO_OK :	set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 gpio_set_ownership(kal_uint32 pin_num,kal_uint32 ownership)
+{
+    return GPIO_FAIL;
+}
+#if defined(MT6885)
+#define DRIVING_SETTING_GPIO_NUM  8
+#define DRIVING_GEAR_NUM 2
+const gpio_driving_gear_t gpio_driving_gear[DRIVING_GEAR_NUM]=
+{
+	{
+	    0x07,
+	    0x08,
+	    {
+		    {0x00,2},	
+		    {0x01,4},	
+		    {0x02,6},	
+		    {0x03,8},	
+		    {0x04,10},	
+		    {0x05,12},	
+		    {0x06,14},	
+		    {0x07,16}	
+	    }
+    },
+};
+
+const drv_gpio_driving_priv_t drv_gpio_driving_priv[DRIVING_SETTING_GPIO_NUM]=
+{
+  {1,57,0, 6, 0xC1E20000},
+  {1,58,0, 9, 0xC1E20000},
+  {1,59,0,12, 0xC1E20000},
+  {1,60,0,15, 0xC1E20000},
+  {1,85,0,12, 0xC1E70000},
+  {1,86,0,15, 0xC1E70000},
+  {1,87,0, 6, 0xC1E70000},
+  {1,88,0, 9, 0xC1E70000}
+};
+#endif
+#if defined(MT6873)
+#define DRIVING_SETTING_GPIO_NUM  8
+#define DRIVING_GEAR_NUM 1
+const gpio_driving_gear_t gpio_driving_gear[DRIVING_GEAR_NUM]=
+{
+	{
+	    0x07,
+	    0x08,
+	    {
+		    {0x00,2},	
+		    {0x01,4},	
+		    {0x02,6},	
+		    {0x03,8},	
+		    {0x04,10},	
+		    {0x05,12},	
+		    {0x06,14},	
+		    {0x07,16}
+	    }
+    },
+};
+const drv_gpio_driving_priv_t drv_gpio_driving_priv[DRIVING_SETTING_GPIO_NUM]=
+{
+  {1,57,0,24, 0xC1D30010},
+  {1,58,0,24, 0xC1D30010},
+  {1,59,0,27, 0xC1D30010},
+  {1,60,0,27, 0xC1D30010},
+  {1,85,0,21, 0xC1D30010},
+  {1,86,0,21, 0xC1D30010},
+  {1,87,0,18, 0xC1D30010},
+  {1,88,0,18, 0xC1D30010}
+};
+#endif
+#if defined(MT6853)
+#define DRIVING_SETTING_GPIO_NUM  8
+#define DRIVING_GEAR_NUM 1
+const gpio_driving_gear_t gpio_driving_gear[DRIVING_GEAR_NUM]=
+{
+	{
+	    0x07,
+	    0x08,
+	    {
+		    {0x00,2},	
+		    {0x01,4},	
+		    {0x02,6},	
+		    {0x03,8},	
+		    {0x04,10},	
+		    {0x05,12},	
+		    {0x06,14},	
+		    {0x07,16}
+	    }
+    },
+};
+const drv_gpio_driving_priv_t drv_gpio_driving_priv[DRIVING_SETTING_GPIO_NUM]=
+{
+  {1,162,0,24, 0xC1D30000},
+  {1,163,0,24, 0xC1D30000},
+  {1,164,0,27, 0xC1D30000},
+  {1,165,0,27, 0xC1D30000},
+  {1,188,0,21, 0xC1D30000},
+  {1,189,0,21, 0xC1D30000},
+  {1,190,0,18, 0xC1D30000},
+  {1,191,0,18, 0xC1D30000}
+};
+#endif
+#if defined(MT6833)
+#define DRIVING_SETTING_GPIO_NUM  8
+#define DRIVING_GEAR_NUM 1
+const gpio_driving_gear_t gpio_driving_gear[DRIVING_GEAR_NUM]=
+{
+	{
+	    0x07,
+	    0x08,
+	    {
+		    {0x00,2},	
+		    {0x01,4},	
+		    {0x02,6},	
+		    {0x03,8},	
+		    {0x04,10},	
+		    {0x05,12},	
+		    {0x06,14},	
+		    {0x07,16}
+	    }
+    },
+};
+const drv_gpio_driving_priv_t drv_gpio_driving_priv[DRIVING_SETTING_GPIO_NUM]=
+{
+  {1,162,0,3,  0xC1D10030},
+  {1,163,0,3,  0xC1D10030},
+  {1,164,0,6,  0xC1D10030},
+  {1,165,0,6,  0xC1D10030},
+  {1,188,0,0,  0xC1D10030},
+  {1,189,0,0,  0xC1D10030},
+  {1,190,0,27, 0xC1D10020},
+  {1,191,0,27, 0xC1D10020}
+};
+#endif
+#if defined(MT6877)
+#define DRIVING_SETTING_GPIO_NUM  8
+#define DRIVING_GEAR_NUM 1
+const gpio_driving_gear_t gpio_driving_gear[DRIVING_GEAR_NUM]=
+{
+	{
+	    0x07,
+	    0x08,
+	    {
+		    {0x00,2},	
+		    {0x01,4},	
+		    {0x02,6},	
+		    {0x03,8},	
+		    {0x04,10},	
+		    {0x05,12},	
+		    {0x06,14},	
+		    {0x07,16}
+	    }
+    },
+};
+const drv_gpio_driving_priv_t drv_gpio_driving_priv[DRIVING_SETTING_GPIO_NUM]=
+{
+  {1,66,0, 3, 0xC1D30010},
+  {1,67,0, 3, 0xC1D30010},
+  {1,68,0, 0, 0xC1D30010},
+  {1,69,0, 0, 0xC1D30010},
+  {1,82,0,27, 0xC1D30000},
+  {1,83,0,27, 0xC1D30000},
+  {1,84,0,24, 0xC1D30000},
+  {1,85,0,24, 0xC1D30000}
+};
+#endif
+#if defined(CHIP10992)
+#define DRIVING_SETTING_GPIO_NUM  8
+#define DRIVING_GEAR_NUM 1
+const gpio_driving_gear_t gpio_driving_gear[DRIVING_GEAR_NUM]=
+{
+	{
+	    0x07,
+	    0x08,
+	    {
+		    {0x00,2},	
+		    {0x01,4},	
+		    {0x02,6},	
+		    {0x03,8},	
+		    {0x04,10},	
+		    {0x05,12},	
+		    {0x06,14},	
+		    {0x07,16}
+	    }
+    },
+};
+const drv_gpio_driving_priv_t drv_gpio_driving_priv[DRIVING_SETTING_GPIO_NUM]=
+{
+  {1,138,0,3, 0xC1D20000},
+  {1,139,0,3, 0xC1D20000},
+  {1,140,0,0, 0xC1D20000},
+  {1,141,0,0, 0xC1D20000},
+  {1,164,0,18, 0xC1C10010},
+  {1,165,0,18, 0xC1C10010},
+  {1,166,0,21, 0xC1C10010},
+  {1,167,0,21, 0xC1C10010}
+};
+#endif
+/**
+*  @brief  set the drive parameter of the gpio pin.
+*  @param  gpio_pin :	The pin which is to set drive.
+*  @param  drive:         the value of drive parameter to set, it should be 0~3
+*  @return GPIO_OK :   set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 gpio_set_drive(gpio_pin_e gpio_pin,kal_uint32 drive)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MERCURY)	
+	return GPIO_FAIL;
+#elif defined(MT6885)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)
+   kal_uint8 temp0,temp1;
+   kal_uint8 result = 0;
+   const drv_gpio_driving_priv_t *pGpio_driving_priv;
+   for(temp0=0;temp0<DRIVING_SETTING_GPIO_NUM;temp0++)
+   {
+   	  if(drv_gpio_driving_priv[temp0].valid)
+   	  {
+   	     pGpio_driving_priv = (drv_gpio_driving_priv + temp0);
+   	  	 if(drv_gpio_driving_priv[temp0].gpio_num==gpio_pin)
+   	  	 {
+   	  	 	  for(temp1=0;temp1<gpio_driving_gear[pGpio_driving_priv->driving_gear].gear_cnt;temp1++)
+   	  	 	  {
+	   	  	   	  if((gpio_driving_gear[pGpio_driving_priv->driving_gear].gear_mapping[temp1][1])==drive)
+	   	  	   	  {
+	   	  	   	    DRV_WriteReg32((pGpio_driving_priv->addr+8),
+	   	  	   	                  ((gpio_driving_gear[pGpio_driving_priv->driving_gear].mask) << (pGpio_driving_priv->offset)));
+	   	  	   	    DRV_WriteReg32((pGpio_driving_priv->addr+4),
+	   	  	   	                  ((gpio_driving_gear[pGpio_driving_priv->driving_gear].gear_mapping[temp1][0]) << (pGpio_driving_priv->offset)));
+	   	  	   	    result = 1;
+	   	  	   	    break;
+	              }   	  	    
+   	  	    }
+   	  	 }
+   	  }
+   	}
+    if(result==1)
+    	  return GPIO_OK;
+    else
+    	  return GPIO_FAIL;
+#else
+  return GPIO_FAIL;
+#endif
+}
+
+
+//========================================================================
+/**
+ *  @brief     get drive register value of pin
+ *  @param  gpio_pin :  The GPIO pin to be read.
+ *  @return   return the drive register value of pin, it should be 0x0~0x3.
+ *		      if gpio_pin is out of range, the return value will be GPIO_FAIL
+ */
+kal_int32 gpio_get_drive_value(gpio_pin_e gpio_pin)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	return GPIO_FAIL;
+#endif
+}
+
+
+
+/**
+*  @brief  set gpio ownership register
+*  @param  pin_num  : the gpio pin to set ownerhsip
+*  @param  ownership : the ownership register bit value to set ,it should be 0~1
+*                                    0: set ownership to MD
+*                                    1: set ownership to AP
+*  @return GPIO_OK :	set successful,  GPIO_FAIL : set failed
+*/
+kal_int32 gpio_get_ownership(kal_uint32 pin_num)
+{
+	return GPIO_FAIL;
+}
+
+void GPIO_MetaModeInit(void)
+{
+}
+
+kal_int32 GPIO_GetMetaMode(void)
+{
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)|| defined(MT6765)|| defined(MT6295M)|| defined(MT3967)|| defined(MT6779)||defined(MT6297)||defined(MT6885)||defined(MERCURY)||defined(MT6873)||defined(MT6853)||defined(MT6833)||defined(MT6877)||defined(CHIP10992)	
+	return GPIO_FAIL;
+#endif
+}
+
diff --git a/mcu/driver/devdrv/gpio/src/gpio_setting.c b/mcu/driver/devdrv/gpio/src/gpio_setting.c
new file mode 100644
index 0000000..3bf8973
--- /dev/null
+++ b/mcu/driver/devdrv/gpio/src/gpio_setting.c
@@ -0,0 +1,1662 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *    gpio_setting.c
+ *
+ * Project:
+ * --------
+ *   Dragonfly
+ *
+ * Description:
+ * ------------
+ *   This Module defines the GPIO and GPO settings.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef __CUST_NEW__
+#include "gpio_def.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+//#include "gpio_hw.h"
+//#include "gpio_sw.h"
+#include "gpio_drv.h"
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+
+#include "kal_general_types.h"
+#include "drv_gpio.h"
+#include "drvpdn.h"
+
+
+#define GPIO_PORTNULL_MODE  0
+#define GPO_PORTNULL_MODE  0
+#define GPIO_PORTNULL_DIR   0
+#define GPIO_PORTNULL_PULL  0
+#define GPIO_PORTNULL_INV   0
+#define GPIO_PORTNULL_OUTPUT_LEVEL  0
+#define GPO_PORTNULL_OUTPUT_LEVEL  0
+#define GPIO_PORTNULL_PULL_SEL  0
+
+#define MODE0_GPIONULL     0
+#define MODE1_GPIONULL     0
+#define MODE2_GPIONULL     0
+#define MODE3_GPIONULL     0
+#define MODE4_GPIONULL     0
+#define MODE5_GPIONULL     0
+#define MODE6_GPIONULL     0
+#define MODE7_GPIONULL     0
+
+#define DIR_OUT_GPIONULL   0
+#define DIR_IN_GPIONULL   0
+
+/************************************************************************************/
+/************************************************************************************/
+/************************************************************************************/
+/******** If DRV_GPIO is not off, we will open to use  GPIO_DRV_TOOL ****************/
+
+#if !defined(DRV_GPIO_OFF)    
+    #if defined(DRV_GPIO_REG_AS_6205B) || defined(DRV_GPIO_REG_AS_6218B) || defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_TK6516) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6270A) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6251) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1)|| defined(DRV_GPIO_REG_AS_6256)||defined(DRV_GPIO_REG_AS_6290)
+       #define __CHIP_SUPP_GPIO_DRV_TOOL__
+    #else
+       #error "No support driver customization tool for this chip."
+    #endif
+#endif //#if !defined(DRV_GPIO_OFF)
+
+
+
+/************************************************************************************/
+/************************************************************************************/
+/************************************************************************************/
+/***************General macro to calculate GPIO MODE register************************/
+
+
+#if defined(DRV_GPIO_MODE_4BITS)
+   #if defined(GPIO_MODE_32BIT_LENGTH)
+      #define GPIO_MODE_4BITS_REG_VAL(port0, port1, port2, port3, port4, port5, port6, port7) \
+          ((GPIO_PORT##port0##_MODE) | (GPIO_PORT##port1##_MODE<<4) | (GPIO_PORT##port2##_MODE<<8) |    \
+          (GPIO_PORT##port3##_MODE<<12) | (GPIO_PORT##port4##_MODE<<16) | (GPIO_PORT##port5##_MODE<<20) | \
+          (GPIO_PORT##port6##_MODE<<24) | (GPIO_PORT##port7##_MODE<<28))
+   #else //defined(GPIO_MODE_32BIT_LENGTH)
+     /* General macro to calculate GPIO MODE (with 4 bits per mode) register. */
+       #define GPIO_MODE_4BITS_REG_VAL(port0, port1, port2, port3)                 \
+          ((GPIO_PORT##port0##_MODE) | (GPIO_PORT##port1##_MODE<<4) | (GPIO_PORT##port2##_MODE<<8) |    \
+          (GPIO_PORT##port3##_MODE<<12))
+   #endif // define(GPIO_MODE_32BIT_LENGTH)
+#elif defined(DRV_GPIO_MODE_3BITS)
+	#define GPIO_MODE_3BITS_REG_VAL(port0,port1,port2,port3,port4)	\
+		((GPIO_PORT##port0##_MODE) | (GPIO_PORT##port1##_MODE<<3) | (GPIO_PORT##port2##_MODE<<6) |	  \
+		(GPIO_PORT##port3##_MODE<<9) | (GPIO_PORT##port4##_MODE<<12))
+#else //defined(DRV_GPIO_MODE_4BITS)
+
+    #define GPIO_MODE_REG_VAL(port0, port1, port2, port3, port4, port5, port6, port7)                 \
+      ((GPIO_PORT##port0##_MODE) | (GPIO_PORT##port1##_MODE<<2) | (GPIO_PORT##port2##_MODE<<4) |    \
+      (GPIO_PORT##port3##_MODE<<6) | (GPIO_PORT##port4##_MODE<<8) | (GPIO_PORT##port5##_MODE<<10) | \
+      (GPIO_PORT##port6##_MODE<<12) | (GPIO_PORT##port7##_MODE<<14))
+#endif //defined(DRV_GPIO_MODE_4BITS)
+
+
+/************************************************************************************/
+/************************************************************************************/
+/************************************************************************************/
+/****************** General macro to calculate GPO MODE register********************/
+
+
+#define GPO_MODE_REG_VAL(port0, port1, port2, port3, port4, port5, port6, port7)                 \
+    ((GPO_PORT##port0##_MODE) | (GPO_PORT##port1##_MODE<<2) | (GPO_PORT##port2##_MODE<<4) |    \
+    (GPO_PORT##port3##_MODE<<6) | (GPO_PORT##port4##_MODE<<8) | (GPO_PORT##port5##_MODE<<10) | \
+    (GPO_PORT##port6##_MODE<<12) | (GPO_PORT##port7##_MODE<<14))
+
+
+
+/************************************************************************************/
+/************************************************************************************/
+/************************************************************************************/
+/************* General macro to calculate GPIO register with 1 bit unit**************/
+
+#if !defined(DRV_GPIO_REG_AS_6290)
+#define GPIO_HWORD_REG_FOR_1BIT(name, port0, port1, port2, port3, port4, port5, port6, port7, port8, port9, \
+                                port10, port11, port12, port13, port14, port15)	\
+    ((GPIO_PORT##port0##_##name) | (GPIO_PORT##port1##_##name<<1) | (GPIO_PORT##port2##_##name<<2) |         \
+    (GPIO_PORT##port3##_##name<<3) | (GPIO_PORT##port4##_##name<<4) | (GPIO_PORT##port5##_##name<<5) |       \
+    (GPIO_PORT##port6##_##name<<6) | (GPIO_PORT##port7##_##name<<7) | (GPIO_PORT##port8##_##name<<8) |       \
+    (GPIO_PORT##port9##_##name<<9) | (GPIO_PORT##port10##_##name<<10) | (GPIO_PORT##port11##_##name<<11) |   \
+    (GPIO_PORT##port12##_##name<<12) | (GPIO_PORT##port13##_##name<<13) | (GPIO_PORT##port14##_##name<<14) | \
+    (GPIO_PORT##port15##_##name<<15))
+#else
+#define GPIO_HWORD_REG_FOR_1BIT(name, port0, port1, port2, port3, port4, port5, port6, port7, port8, port9, \
+                                port10, port11, port12, port13, port14, port15, port16, port17, port18, port19,\
+                                port20,port21, port22, port23, port24, port25, port26, port27, port28, port29, \
+                                port30, port31)	\
+    ((GPIO_PORT##port0##_##name) | (GPIO_PORT##port1##_##name<<1) | (GPIO_PORT##port2##_##name<<2) |         \
+    (GPIO_PORT##port3##_##name<<3) | (GPIO_PORT##port4##_##name<<4) | (GPIO_PORT##port5##_##name<<5) |       \
+    (GPIO_PORT##port6##_##name<<6) | (GPIO_PORT##port7##_##name<<7) | (GPIO_PORT##port8##_##name<<8) |       \
+    (GPIO_PORT##port9##_##name<<9) | (GPIO_PORT##port10##_##name<<10) | (GPIO_PORT##port11##_##name<<11) |   \
+    (GPIO_PORT##port12##_##name<<12) | (GPIO_PORT##port13##_##name<<13) | (GPIO_PORT##port14##_##name<<14) | \
+    (GPIO_PORT##port15##_##name<<15) | (GPIO_PORT##port16##_##name<<16) | (GPIO_PORT##port17##_##name<<17) | \
+    (GPIO_PORT##port18##_##name<<18) | (GPIO_PORT##port19##_##name<<19) | (GPIO_PORT##port20##_##name<<20) | \
+    (GPIO_PORT##port21##_##name<<21) | (GPIO_PORT##port22##_##name<<22) | (GPIO_PORT##port23##_##name<<23) | \
+    (GPIO_PORT##port24##_##name<<24) | (GPIO_PORT##port25##_##name<<25) | (GPIO_PORT##port26##_##name<<26) | \
+    (GPIO_PORT##port27##_##name<<27) | (GPIO_PORT##port28##_##name<<28) | (GPIO_PORT##port29##_##name<<29) | \
+    (GPIO_PORT##port30##_##name<<30) | (GPIO_PORT##port31##_##name<<31)) 
+#endif
+
+/************************************************************************************/
+/************************************************************************************/
+/************************************************************************************/
+/***************** General macro to calculate GPO register with 1 bit unit.**********/
+
+#define GPO_HWORD_REG_FOR_1BIT(name, port0, port1, port2, port3, port4, port5, port6, port7, port8, port9, \
+                                port10, port11, port12, port13, port14, port15)	\
+    ((GPO_PORT##port0##_##name) | (GPO_PORT##port1##_##name<<1) | (GPO_PORT##port2##_##name<<2) |         \
+    (GPO_PORT##port3##_##name<<3) | (GPO_PORT##port4##_##name<<4) | (GPO_PORT##port5##_##name<<5) |       \
+    (GPO_PORT##port6##_##name<<6) | (GPO_PORT##port7##_##name<<7) | (GPO_PORT##port8##_##name<<8) |       \
+    (GPO_PORT##port9##_##name<<9) | (GPO_PORT##port10##_##name<<10) | (GPO_PORT##port11##_##name<<11) |   \
+    (GPO_PORT##port12##_##name<<12) | (GPO_PORT##port13##_##name<<13) | (GPO_PORT##port14##_##name<<14) | \
+    (GPO_PORT##port15##_##name<<15))
+
+
+/************************************************************************************/
+/************************************************************************************/
+/************************************************************************************/
+/*****General macro to calculate GPIO word-length variable value with 1 bit unit.****/
+
+
+#define GPIO_WORD_VAR_FOR_1BIT(name, port0, port1, port2, port3, port4, port5, port6, port7, port8, port9, port10, \
+	                            port11, port12, port13, port14, port15, port16, port17, port18, port19, port20, port21, \
+                               port22, port23, port24, port25, port26, port27, port28, port29, port30, port31) \
+    ((name##_GPIO##port0) | (name##_GPIO##port1<<1) | (name##_GPIO##port2<<2) | (name##_GPIO##port3<<3) | (name##_GPIO##port4<<4) | \
+    (name##_GPIO##port5<<5) | (name##_GPIO##port6<<6) | (name##_GPIO##port7<<7) | (name##_GPIO##port8<<8) | (name##_GPIO##port9<<9) | \
+    (name##_GPIO##port10<<10) | (name##_GPIO##port11<<11) | (name##_GPIO##port12<<12) | (name##_GPIO##port13<<13) | (name##_GPIO##port14<<14) | \
+    (name##_GPIO##port15<<15) | (name##_GPIO##port16<<16) | (name##_GPIO##port17<<17) | (name##_GPIO##port18<<18) | (name##_GPIO##port19<<19) | \
+    (name##_GPIO##port20<<20) | (name##_GPIO##port21<<21) | (name##_GPIO##port22<<22) | (name##_GPIO##port23<<23) | (name##_GPIO##port24<<24) | \
+    (name##_GPIO##port25<<25) | (name##_GPIO##port26<<26) | (name##_GPIO##port27<<27) | (name##_GPIO##port28<<28) | (name##_GPIO##port29<<29) | \
+    (name##_GPIO##port30<<30) | (name##_GPIO##port31<<31))
+
+
+
+/****************************************************************************************/
+/****************************************************************************************/
+/****************************************************************************************/
+/*********************************__CHIP_SUPP_GPIO_DRV_TOOL__****************************/
+
+#if defined(__CHIP_SUPP_GPIO_DRV_TOOL__)
+
+/***************************GPIO MODE IS NEITHER 4 BIT NOR 3 BIT**********START*********/
+
+#if !defined(DRV_GPIO_MODE_4BITS) && !defined(DRV_GPIO_MODE_3BITS)
+   /* GPIO mode register values for different platforms. */
+
+  #if defined(DRV_GPIO_REG_AS_TK6516)
+      #define GPIO_MODE_REG1  GPIO_MODE_REG_VAL(0, 1, 2, 3, NULL, NULL, NULL, NULL)
+  #else /* DRV_GPIO_REG_AS_TK6516 */
+     #define GPIO_MODE_REG1  GPIO_MODE_REG_VAL(0, 1, 2, 3, 4, 5, 6, 7)
+     #define GPIO_MODE_REG2  GPIO_MODE_REG_VAL(8, 9, 10, 11, 12, 13, 14, 15)
+     #if defined(DRV_GPIO_REG_AS_6205B)
+         #define GPIO_MODE_REG3  GPIO_MODE_REG_VAL(16, 17, 18, 19, 20, 21, NULL, NULL)
+         #define GPO_MODE_REG    GPO_MODE_REG_VAL(0, 1, 2, 3, NULL, NULL, NULL, NULL)
+     #elif defined(DRV_GPIO_REG_AS_6270A)
+          #define GPIO_MODE_REG3  GPIO_MODE_REG_VAL(16, 17, 18, 19, 20, 21, 22, 23)
+          #define GPIO_MODE_REG4  GPIO_MODE_REG_VAL(24, 25, 26, 27, NULL, NULL, NULL, NULL)
+     #else /* DRV_GPIO_REG_AS_6270A */
+          #define GPIO_MODE_REG3  GPIO_MODE_REG_VAL(16, 17, 18, 19, 20, 21, 22, 23)
+          #define GPIO_MODE_REG4  GPIO_MODE_REG_VAL(24, 25, 26, 27, 28, 29, 30, 31)
+          #define GPIO_MODE_REG5  GPIO_MODE_REG_VAL(32, 33, 34, 35, 36, 37, 38, 39)
+          #define GPIO_MODE_REG6  GPIO_MODE_REG_VAL(40, 41, 42, 43, 44, 45, 46, 47)
+         #if defined(DRV_GPIO_REG_AS_6218B)
+              #define GPO_MODE_REG  GPO_MODE_REG_VAL(0, 1, 2, NULL, NULL, NULL, NULL, NULL)
+         #elif defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6225)
+             #define GPIO_MODE_REG7  GPIO_MODE_REG_VAL(48, 49, 50, 51, 52, 53, 54, NULL)
+             #if defined(DRV_GPIO_REG_AS_6219)
+                 #define GPO_MODE_REG  GPO_MODE_REG_VAL(0, 1, 2, 3, 4, NULL, NULL, NULL)
+             #elif defined(DRV_GPIO_REG_AS_6225)
+                 #define GPO_MODE_REG  GPO_MODE_REG_VAL(0, 1, 2, 3, NULL, NULL, NULL, NULL)
+             #endif
+         #elif defined(DRV_GPIO_REG_AS_6227)
+             #define GPIO_MODE_REG7  GPIO_MODE_REG_VAL(48, 49, 50, 51, 52, 53, 54, 55)
+             #define GPIO_MODE_REG8  GPIO_MODE_REG_VAL(56, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+             #define GPO_MODE_REG  GPO_MODE_REG_VAL(0, 1, 2, 3, 4, NULL, NULL, NULL)
+        #elif defined(DRV_GPIO_REG_AS_6228)
+            #define GPIO_MODE_REG7  GPIO_MODE_REG_VAL(48, 49, 50, 51, 52, 53, 54, 55)
+            #define GPIO_MODE_REG8  GPIO_MODE_REG_VAL(56, 57, 58, 59, 60, 61, 62, 63)
+            #define GPIO_MODE_REG9  GPIO_MODE_REG_VAL(64, 65, 66, 67, 68, 69, 70, 71)
+            #define GPIO_MODE_REG10  GPIO_MODE_REG_VAL(72, 73, 74, NULL, NULL, NULL, NULL, NULL)
+            #define GPO_MODE_REG  GPO_MODE_REG_VAL(0, 1, 2, NULL, NULL, NULL, NULL, NULL)
+        #elif defined(DRV_GPIO_REG_AS_6223)
+            #define GPIO_MODE_REG7  GPIO_MODE_REG_VAL(48, 49, 50, 51, 52, NULL, NULL, NULL)
+        #elif defined(DRV_GPIO_REG_AS_6238)  || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E)
+            #define GPIO_MODE_REG7  GPIO_MODE_REG_VAL(48, 49, 50, 51, 52, 53, 54, 55)
+            #define GPIO_MODE_REG8  GPIO_MODE_REG_VAL(56, 57, 58, 59, 60, 61, 62, 63)
+         #if defined(DRV_GPIO_REG_AS_6236) 
+            #define GPIO_MODE_REG9  GPIO_MODE_REG_VAL(64, 65, 66, 67, NULL, NULL, NULL, NULL)
+         #else // defined(DRV_GPIO_REG_AS_6236) 
+            #define GPIO_MODE_REG9  GPIO_MODE_REG_VAL(64, 65, 66, 67, 68, 69, 70, 71)
+            #if defined(DRV_GPIO_REG_AS_6238)
+               #define GPIO_MODE_REGA  GPIO_MODE_REG_VAL(72, 73, 74, 75, 76, 77, 78, 79)
+               #define GPIO_MODE_REGB  GPIO_MODE_REG_VAL(80, 81, 82, 83, 84, NULL, NULL, NULL)
+            #elif defined(DRV_GPIO_REG_AS_6235)
+               #define GPIO_MODE_REGA  GPIO_MODE_REG_VAL(72, 73, 74, 75, 76, 77, 78, NULL)
+            #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+               #define GPIO_MODE_REGA  GPIO_MODE_REG_VAL(72, 73, 74, 75, 76, 77, 78, 79)
+               #define GPIO_MODE_REGB  GPIO_MODE_REG_VAL(80, 81, 82, 83, 84, 85, 86, 87)
+               #define GPIO_MODE_REGC  GPIO_MODE_REG_VAL(88, 89, 90, 91, 92, 93, 94, 95)
+               #if defined(DRV_GPIO_REG_AS_6268A)
+               #define GPIO_MODE_REGD  GPIO_MODE_REG_VAL(96, 97, 98, 99, 100, NULL, NULL, NULL)
+               #elif defined(DRV_GPIO_REG_AS_6268)
+               #define GPIO_MODE_REGD  GPIO_MODE_REG_VAL(96, 97, 98, 99, NULL, NULL, NULL, NULL)
+               #elif defined(DRV_GPIO_REG_AS_6276)
+               #define GPIO_MODE_REGD  GPIO_MODE_REG_VAL(96, 97, 98, 99, 100, 101, 102, 103)
+               #define GPIO_MODE_REGE  GPIO_MODE_REG_VAL(104, 105, 106, 107, 108, NULL, NULL, NULL)
+               #endif
+            #elif defined(DRV_GPIO_REG_AS_6253T)
+               #define GPIO_MODE_REGA  GPIO_MODE_REG_VAL(72, 73, 74, 75, 76, 77, 78, 79)
+               #if defined(DRV_GPIO_6253_MODE11_DEFAULT)
+                  #define GPIO_PORT82FOR6253_MODE MODE_1 //GPIO82 for MT6253 should be fixed to mode1
+                  #define GPIO_MODE_REGB  GPIO_MODE_REG_VAL(80, 81, 82FOR6253, NULL, NULL, NULL, NULL, NULL)
+               #else //defined(DRV_GPIO_6253_MODE11_DEFAULT)
+               #define GPIO_MODE_REGB  GPIO_MODE_REG_VAL(80, 81, NULL, NULL, NULL, NULL, NULL, NULL)
+               #endif //defined(DRV_GPIO_6253_MODE11_DEFAULT)
+            #endif
+         #endif // defined(DRV_GPIO_REG_AS_6236) 
+      #endif
+   #endif /* DRV_GPIO_REG_AS_6205B */
+#endif /* DRV_GPIO_REG_AS_TK6516 */
+
+
+/***************************GPIO MODE IS NEITHER 4 BIT NOR 3 BIT**********END*********/
+
+
+/***************************GPIO MODE IS 4 BIT ***********************START***********/
+
+#elif defined(DRV_GPIO_MODE_4BITS) // DRV_GPIO_MODE_4BITS is defined
+#if defined(DRV_GPIO_REG_AS_6253E_1)
+   #define GPIO_MODE_REG1  GPIO_MODE_4BITS_REG_VAL(0, 1, 2, 3, 4, 5, 6, 7)
+   #define GPIO_MODE_REG2  GPIO_MODE_4BITS_REG_VAL(8, 9, 10, 11, 12, 13, 14, 15)
+   #define GPIO_MODE_REG3  GPIO_MODE_4BITS_REG_VAL(16, 17, 18, 19, 20, 21, 22, 23)
+   #define GPIO_MODE_REG4  GPIO_MODE_4BITS_REG_VAL(24, 25, 26, 27, 28, 29, 30, 31)
+   #define GPIO_MODE_REG5  GPIO_MODE_4BITS_REG_VAL(32, 33, 34, 35, 36, 37, 38, 39)
+   #define GPIO_MODE_REG6  GPIO_MODE_4BITS_REG_VAL(40, 41, 42, 43, 44, 45, 46, 47)
+   #define GPIO_MODE_REG7  GPIO_MODE_4BITS_REG_VAL(48, 49, 50, 51, 52, 53, 54, 55)
+   #define GPIO_MODE_REG8  GPIO_MODE_4BITS_REG_VAL(56, 57, 58, 59, 60, 61, 62, 63)
+   #define GPIO_MODE_REG9  GPIO_MODE_4BITS_REG_VAL(64, 65, 66, 67, 68, 69, 70, NULL)
+#endif //defined(DRV_GPIO_REG_AS_6253E_1)
+#if defined(DRV_GPIO_REG_AS_6255) 
+   #define GPIO_MODE_REG1  GPIO_MODE_4BITS_REG_VAL(0, 1, 2, 3)
+   #define GPIO_MODE_REG2  GPIO_MODE_4BITS_REG_VAL(4, 5, 6, 7)
+   #define GPIO_MODE_REG3  GPIO_MODE_4BITS_REG_VAL(8, 9, 10, 11)
+   #define GPIO_MODE_REG4  GPIO_MODE_4BITS_REG_VAL(12, 13, 14, 15)
+   #define GPIO_MODE_REG5  GPIO_MODE_4BITS_REG_VAL(16, 17, 18, 19)
+   #define GPIO_MODE_REG6  GPIO_MODE_4BITS_REG_VAL(20, 21, 22, 23)
+   #define GPIO_MODE_REG7  GPIO_MODE_4BITS_REG_VAL(24, 25, 26, 27)
+   #define GPIO_MODE_REG8  GPIO_MODE_4BITS_REG_VAL(28, 29, 30, 31)
+   #define GPIO_MODE_REG9  GPIO_MODE_4BITS_REG_VAL(32, 33, 34, 35)
+   #define GPIO_MODE_REG10  GPIO_MODE_4BITS_REG_VAL(36, 37, 38, 39)
+   #define GPIO_MODE_REG11  GPIO_MODE_4BITS_REG_VAL(40, 41, 42, 43)
+   #define GPIO_MODE_REG12  GPIO_MODE_4BITS_REG_VAL(44, 45, 46, 47)
+   #define GPIO_MODE_REG13  GPIO_MODE_4BITS_REG_VAL(48, 49, 50, 51)
+   #define GPIO_MODE_REG14  GPIO_MODE_4BITS_REG_VAL(52, 53, 54, 55)
+   #define GPIO_MODE_REG15  GPIO_MODE_4BITS_REG_VAL(56, 57, 58, 59)
+   #define GPIO_MODE_REG16  GPIO_MODE_4BITS_REG_VAL(60, 61, 62, 63)
+   #define GPIO_MODE_REG17  GPIO_MODE_4BITS_REG_VAL(64, 65, 66, 67)
+   #define GPIO_MODE_REG18  GPIO_MODE_4BITS_REG_VAL(68, 69, 70, 71)
+   #define GPIO_MODE_REG19  GPIO_MODE_4BITS_REG_VAL(72, 73, 74, 75)
+   #define GPIO_MODE_REG20  GPIO_MODE_4BITS_REG_VAL(76, 77, 78, 79)
+   #define GPIO_MODE_REG21  GPIO_MODE_4BITS_REG_VAL(80, 81, 82, 83)
+   #define GPIO_MODE_REG22  GPIO_MODE_4BITS_REG_VAL(84, 85, 86, 87)
+#define GPIO_MODE_REG23  GPIO_MODE_4BITS_REG_VAL(88, 89, 90, 91)
+#define GPIO_MODE_REG24  GPIO_MODE_4BITS_REG_VAL(92, 93, 94, 95)
+#define GPIO_MODE_REG25  GPIO_MODE_4BITS_REG_VAL(96, 97, 98, 99)
+#define GPIO_MODE_REG26  GPIO_MODE_4BITS_REG_VAL(100, 101, 102,103)
+#define GPIO_MODE_REG27  GPIO_MODE_4BITS_REG_VAL(104, NULL, NULL,NULL)
+
+ #endif 
+#if defined(DRV_GPIO_REG_AS_6256)
+   #define GPIO_MODE_REG1  GPIO_MODE_4BITS_REG_VAL(0, 1, 2, 3)
+   #define GPIO_MODE_REG2  GPIO_MODE_4BITS_REG_VAL(4, 5, 6, 7)
+   #define GPIO_MODE_REG3  GPIO_MODE_4BITS_REG_VAL(8, 9, 10, 11)
+   #define GPIO_MODE_REG4  GPIO_MODE_4BITS_REG_VAL(12, 13, 14, 15)
+   #define GPIO_MODE_REG5  GPIO_MODE_4BITS_REG_VAL(16, 17, 18, 19)
+   #define GPIO_MODE_REG6  GPIO_MODE_4BITS_REG_VAL(20, 21, 22, 23)
+   #define GPIO_MODE_REG7  GPIO_MODE_4BITS_REG_VAL(24, 25, 26, 27)
+   #define GPIO_MODE_REG8  GPIO_MODE_4BITS_REG_VAL(28, 29, 30, 31)
+   #define GPIO_MODE_REG9  GPIO_MODE_4BITS_REG_VAL(32, 33, 34, 35)
+   #define GPIO_MODE_REG10  GPIO_MODE_4BITS_REG_VAL(36, 37, 38, 39)
+   #define GPIO_MODE_REG11  GPIO_MODE_4BITS_REG_VAL(40, 41, 42, 43)
+   #define GPIO_MODE_REG12  GPIO_MODE_4BITS_REG_VAL(44, 45, 46, 47)
+   #define GPIO_MODE_REG13  GPIO_MODE_4BITS_REG_VAL(48, 49, 50, 51)
+   #define GPIO_MODE_REG14  GPIO_MODE_4BITS_REG_VAL(52, 53, 54, 55)
+   #define GPIO_MODE_REG15  GPIO_MODE_4BITS_REG_VAL(56, 57, 58, 59)
+   #define GPIO_MODE_REG16  GPIO_MODE_4BITS_REG_VAL(60, 61, 62, 63)
+   #define GPIO_MODE_REG17  GPIO_MODE_4BITS_REG_VAL(64, 65, 66, 67)
+   #define GPIO_MODE_REG18  GPIO_MODE_4BITS_REG_VAL(68, 69, 70, 71)
+   #define GPIO_MODE_REG19  GPIO_MODE_4BITS_REG_VAL(72, 73, 74, 75)
+   #define GPIO_MODE_REG20  GPIO_MODE_4BITS_REG_VAL(76, 77, 78, 79)
+   #define GPIO_MODE_REG21  GPIO_MODE_4BITS_REG_VAL(80, 81, 82, 83)
+   #define GPIO_MODE_REG22  GPIO_MODE_4BITS_REG_VAL(84, 85, 86, 87)
+   #define GPIO_MODE_REG23  GPIO_MODE_4BITS_REG_VAL(88, 89, 90, 91)
+   #define GPIO_MODE_REG24  GPIO_MODE_4BITS_REG_VAL(92, 93, 94, 95)
+   #define GPIO_MODE_REG25  GPIO_MODE_4BITS_REG_VAL(96, 97, 98, 99)
+   #define GPIO_MODE_REG26  GPIO_MODE_4BITS_REG_VAL(100, 101, 102, 103)
+   #define GPIO_MODE_REG27  GPIO_MODE_4BITS_REG_VAL(104, NULL, NULL, NULL)
+#endif      
+#if defined(DRV_GPIO_REG_AS_6251)
+   #define GPIO_MODE_REG1  GPIO_MODE_4BITS_REG_VAL(0, 1, 2, 3)
+   #define GPIO_MODE_REG2  GPIO_MODE_4BITS_REG_VAL(4, 5, 6, 7)
+   #define GPIO_MODE_REG3  GPIO_MODE_4BITS_REG_VAL(8, 9, 10, 11)
+   #define GPIO_MODE_REG4  GPIO_MODE_4BITS_REG_VAL(12, 13, 14, 15)
+   #define GPIO_MODE_REG5  GPIO_MODE_4BITS_REG_VAL(16, 17, 18, 19)
+   #define GPIO_MODE_REG6  GPIO_MODE_4BITS_REG_VAL(20, 21, 22, 23)
+   #define GPIO_MODE_REG7  GPIO_MODE_4BITS_REG_VAL(24, 25, 26, 27)
+   #define GPIO_MODE_REG8  GPIO_MODE_4BITS_REG_VAL(28, 29, 30, 31)
+#endif // defined(DRV_GPIO_REG_AS_6255)
+
+/***************************GPIO MODE IS NEITHER 4 BIT *********END**********/
+
+/***************************GPIO MODE IS 3 BIT******************START********/
+#elif defined(DRV_GPIO_MODE_3BITS)
+#if defined(DRV_GPIO_REG_AS_6276)
+    #define GPIO_MODE_REG0	GPIO_MODE_3BITS_REG_VAL(0, 1, 2, 3, 4)
+    #define GPIO_MODE_REG1	GPIO_MODE_3BITS_REG_VAL(5, 6, 7, 8, 9)
+    #define GPIO_MODE_REG2	GPIO_MODE_3BITS_REG_VAL(10, 11, 12, 13, 14)
+    #define GPIO_MODE_REG3	GPIO_MODE_3BITS_REG_VAL(15, 16, 17, 18, 19)
+    #define GPIO_MODE_REG4	GPIO_MODE_3BITS_REG_VAL(20, 21, 22, 23, 24)
+    #define GPIO_MODE_REG5	GPIO_MODE_3BITS_REG_VAL(25, 26, 27, 28, 29)	
+    #define GPIO_MODE_REG6	GPIO_MODE_3BITS_REG_VAL(30, 31, 32, 33, 34)
+    #define GPIO_MODE_REG7	GPIO_MODE_3BITS_REG_VAL(35, 36, 37, 38, 39)
+    #define GPIO_MODE_REG8	GPIO_MODE_3BITS_REG_VAL(40, 41, 42, 43, 44)	
+    #define GPIO_MODE_REG9	GPIO_MODE_3BITS_REG_VAL(45, 46, 47, 48, 49)
+    #define GPIO_MODE_REGA	GPIO_MODE_3BITS_REG_VAL(50, 51, 52, 53, 54)
+    #define GPIO_MODE_REGB	GPIO_MODE_3BITS_REG_VAL(55, 56, 57, 58, 59)
+    #define GPIO_MODE_REGC	GPIO_MODE_3BITS_REG_VAL(60, 61, 62, 63, 64)
+    #define GPIO_MODE_REGD	GPIO_MODE_3BITS_REG_VAL(65, 66, 67, 68, 69)
+    #define GPIO_MODE_REGE	GPIO_MODE_3BITS_REG_VAL(70, 71, 72, 73, 74)
+    #define GPIO_MODE_REGF	GPIO_MODE_3BITS_REG_VAL(75, 76, 77, 78, 79)
+    #define GPIO_MODE_REG10	GPIO_MODE_3BITS_REG_VAL(80, 81, 82, 83, 84)
+    #define GPIO_MODE_REG11	GPIO_MODE_3BITS_REG_VAL(85, 86, 87, 88, 89)
+    #define GPIO_MODE_REG12	GPIO_MODE_3BITS_REG_VAL(90, 91, 92, 93, 94)	
+    #define GPIO_MODE_REG13	GPIO_MODE_3BITS_REG_VAL(95, 96, 97, 98, 99)
+    #define GPIO_MODE_REG14	GPIO_MODE_3BITS_REG_VAL(100, 101, 102, 103, 104)
+    #define GPIO_MODE_REG15	GPIO_MODE_3BITS_REG_VAL(105, 106, 107, 108, 109)
+#endif //defined(DRV_GPIO_REG_AS_6276)
+
+#endif //!defined(DRV_GPIO_MODE_4BITS) && !defined(DRV_GPIO_MODE_3BITS)
+
+/****************************************************************************************/
+/*********************************__CHIP_SUPP_GPIO_DRV_TOOL__****************************/
+/*********************************************END****************************************/
+/****************************************************************************************/
+
+
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/
+ /* Macros to calulate GPIO related register value of different platforms with 1 bit unit 
+   for different settings, like dirction control pull-up/pull-down enable, inversion control. */
+/*****************************************START***********************************************/
+/*********************************************************************************************/
+
+
+#if defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_HWORD_REG1(name)  GPIO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+#else /* DRV_GPIO_REG_AS_TK6516 */
+   #if !defined(DRV_GPIO_REG_AS_6290)
+   #define GPIO_HWORD_REG1(name)  GPIO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
+   #else
+   #define GPIO_HWORD_REG1(name)  GPIO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ,25 ,26 ,27,28, 29 ,30, 31)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6205B)
+      #define GPO_HWORD_REG1(name)  GPO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #define GPIO_HWORD_REG2(name)  GPIO_HWORD_REG_FOR_1BIT(name, 16, 17, 18, 19, 20, 21, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6270A)
+      #define GPIO_HWORD_REG2(name)  GPIO_HWORD_REG_FOR_1BIT(name, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6251)
+      #define GPIO_HWORD_REG2(name)  GPIO_HWORD_REG_FOR_1BIT(name, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
+      #define GPIO_HWORD_REG3(name)  GPIO_HWORD_REG_FOR_1BIT(name, 32, 33, 34, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #define GPIO_HWORD_REG3_TO_38(name)  GPIO_HWORD_REG_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+   #else /* DRV_GPIO_REG_AS_6270A) */
+   	  #if !defined(DRV_GPIO_REG_AS_6290)
+      #define GPIO_HWORD_REG2(name)  GPIO_HWORD_REG_FOR_1BIT(name, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
+      #else
+	  #define GPIO_HWORD_REG2(name)  GPIO_HWORD_REG_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 ,57 ,58 ,59,60, 61 ,62, 63)
+	  #endif
+      #define GPIO_HWORD_REG3(name)  GPIO_HWORD_REG_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
+      #if defined(DRV_GPIO_REG_AS_6218B)
+         #define GPO_HWORD_REG1(name)  GPO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6225)  
+         #if defined(DRV_GPIO_REG_AS_6219)
+            #define GPO_HWORD_REG1(name)  GPO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, 4, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #elif defined(DRV_GPIO_REG_AS_6225)
+            #define GPO_HWORD_REG1(name)  GPO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #endif
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6227)
+         #define GPO_HWORD_REG1(name)  GPO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, 3, 4, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6228)
+         #define GPO_HWORD_REG1(name)  GPO_HWORD_REG_FOR_1BIT(name, 0, 1, 2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6223)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6238)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
+         #define GPIO_HWORD_REG6(name)  GPIO_HWORD_REG_FOR_1BIT(name, 80, 81, 82, 83, 84, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6235)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6236)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
+         #define GPIO_HWORD_REG6(name)  GPIO_HWORD_REG_FOR_1BIT(name, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95)
+         #if defined(DRV_GPIO_REG_AS_6268A)
+         #define GPIO_HWORD_REG7(name)  GPIO_HWORD_REG_FOR_1BIT(name, 96, 97, 98, 99, 100, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #elif defined(DRV_GPIO_REG_AS_6268)
+         #define GPIO_HWORD_REG7(name)  GPIO_HWORD_REG_FOR_1BIT(name, 96, 97, 98, 99, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #elif defined(DRV_GPIO_REG_AS_6276)
+         #define GPIO_HWORD_REG7(name)  GPIO_HWORD_REG_FOR_1BIT(name, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, NULL, NULL, NULL)
+         #endif
+      #elif defined(DRV_GPIO_REG_AS_6253T)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
+         #define GPIO_HWORD_REG6(name)  GPIO_HWORD_REG_FOR_1BIT(name, 80, 81, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6255)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
+         #define GPIO_HWORD_REG6(name)  GPIO_HWORD_REG_FOR_1BIT(name, 80, 81, 82, 83, 84, 85, 86, 87, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+         #define GPIO_HWORD_REG7(name)  GPIO_HWORD_REG_FOR_1BIT(name, 96, 97, 98, 99, 100, 101, 102, 103, 104, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+#elif defined(DRV_GPIO_REG_AS_6253E)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+     #elif defined(DRV_GPIO_REG_AS_6253E_1) 
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)     
+     #elif defined(DRV_GPIO_REG_AS_6256)
+         #define GPIO_HWORD_REG4(name)  GPIO_HWORD_REG_FOR_1BIT(name, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+         #define GPIO_HWORD_REG5(name)  GPIO_HWORD_REG_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
+         #define GPIO_HWORD_REG6(name)  GPIO_HWORD_REG_FOR_1BIT(name, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95)
+         #define GPIO_HWORD_REG7(name)  GPIO_HWORD_REG_FOR_1BIT(name, 96, 97, 98, 99, 100, 101, 102, 103, 104, NULL, NULL, NULL, NULL, NULL, NULL, NULL)    
+ #endif      
+   #endif /* DRV_GPIO_REG_AS_6205B */
+#endif /* DRV_GPIO_REG_AS_TK6516 */
+
+/*********************************************************************************************/
+/*********************************************************************************************/
+ /* Macros to calulate GPIO related register value of different platforms with 1 bit unit 
+   for different settings, like dirction control pull-up/pull-down enable, inversion control. */
+/*****************************************END***********************************************/
+/*********************************************************************************************/
+
+#if defined(DRV_GPIO_REG_AS_6290)
+
+   #define GPIO_OWNERSHIP_REG1 GPIO_HWORD_REG1(OWNERSHIP)
+   #define GPIO_OWNERSHIP_REG2 GPIO_HWORD_REG2(OWNERSHIP)   
+
+#endif
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/****************** GPIO direction control register value*************************************/
+/*************************************START************************************************/ 
+/*********************************************************************************************/ 
+
+   #define GPIO_DIR_REG1   GPIO_HWORD_REG1(DIR)
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_DIR_REG2   GPIO_HWORD_REG2(DIR)
+#if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_6270A)
+   #define GPIO_DIR_REG3   GPIO_HWORD_REG3(DIR)
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6253E)
+      #define GPIO_DIR_REG4   GPIO_HWORD_REG4(DIR)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6228)
+      #define GPIO_DIR_REG5   GPIO_HWORD_REG5(DIR)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1)
+      #define GPIO_DIR_REG4   GPIO_HWORD_REG4(DIR)
+      #define GPIO_DIR_REG5   GPIO_HWORD_REG5(DIR)
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) 
+         #define GPIO_DIR_REG6   GPIO_HWORD_REG6(DIR)
+      #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+         #define GPIO_DIR_REG6   GPIO_HWORD_REG6(DIR)
+         #define GPIO_DIR_REG7   GPIO_HWORD_REG7(DIR)
+      #endif
+  #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255) 
+      #define GPIO_DIR_REG4   GPIO_HWORD_REG4(DIR)
+      #define GPIO_DIR_REG5   GPIO_HWORD_REG5(DIR)
+      #define GPIO_DIR_REG6   GPIO_HWORD_REG6(DIR)
+      #define GPIO_DIR_REG7   GPIO_HWORD_REG7(DIR)
+   #endif
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_6270A) */
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/****************** GPIO direction control register value*************************************/
+/*************************************END*****************************************************/ 
+/*********************************************************************************************/ 
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/****************** GPIO Pull-up/Pull-down enable register value******************************/
+/*************************************START***************************************************/ 
+/*********************************************************************************************/ 
+
+   #define GPIO_PULL_REG1   GPIO_HWORD_REG1(PULL)
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_PULL_REG2   GPIO_HWORD_REG2(PULL)
+#if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_6270A)
+   #if defined(DRV_GPIO_REG_AS_6251)
+      #define GPIO_PULL_REG3   GPIO_HWORD_REG3_TO_38(PULL)
+   #else
+      #define GPIO_PULL_REG3   GPIO_HWORD_REG3(PULL)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223)|| defined(DRV_GPIO_REG_AS_6253E)
+      #define GPIO_PULL_REG4   GPIO_HWORD_REG4(PULL)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6228)
+      #define GPIO_PULL_REG5   GPIO_HWORD_REG5(PULL)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1)
+      #define GPIO_PULL_REG4   GPIO_HWORD_REG4(PULL)
+      #define GPIO_PULL_REG5   GPIO_HWORD_REG5(PULL)
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) 
+         #define GPIO_PULL_REG6   GPIO_HWORD_REG6(PULL)
+      #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+         #define GPIO_PULL_REG6   GPIO_HWORD_REG6(PULL)
+         #define GPIO_PULL_REG7   GPIO_HWORD_REG7(PULL)
+      #endif
+  #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255) 
+      #define GPIO_PULL_REG4   GPIO_HWORD_REG4(PULL)
+      #define GPIO_PULL_REG5   GPIO_HWORD_REG5(PULL)   
+      #define GPIO_PULL_REG6   GPIO_HWORD_REG6(PULL)
+      #define GPIO_PULL_REG7   GPIO_HWORD_REG7(PULL)
+   #endif
+#endif /* #if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_6270A) */
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/****************** GPIO Pull-up/Pull-down enable register value******************************/
+/*************************************END*****************************************************/ 
+/*********************************************************************************************/ 
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/******************GPIO inversion control register value**************************************/
+/************************************START*****************************************************/ 
+/*********************************************************************************************/ 
+
+#if !defined(DRV_GPIO_REG_AS_6205B)
+   #define GPIO_INV_REG1   GPIO_HWORD_REG1(INV)
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_INV_REG2   GPIO_HWORD_REG2(INV)
+#if !defined(DRV_GPIO_REG_AS_6270A) && !defined(DRV_GPIO_REG_AS_6251)
+   #define GPIO_INV_REG3   GPIO_HWORD_REG3(INV)
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6253E)
+      #define GPIO_INV_REG4   GPIO_HWORD_REG4(INV)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6228)
+      #define GPIO_INV_REG5   GPIO_HWORD_REG5(INV)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T)  || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1)
+      #define GPIO_INV_REG4   GPIO_HWORD_REG4(INV)
+      #define GPIO_INV_REG5   GPIO_HWORD_REG5(INV)
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T)
+         #define GPIO_INV_REG6   GPIO_HWORD_REG6(INV)
+      #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+         #define GPIO_INV_REG6   GPIO_HWORD_REG6(INV)
+         #define GPIO_INV_REG7   GPIO_HWORD_REG7(INV)
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255)  
+      #define GPIO_INV_REG4   GPIO_HWORD_REG4(INV)
+      #define GPIO_INV_REG5   GPIO_HWORD_REG5(INV)
+      #define GPIO_INV_REG6   GPIO_HWORD_REG6(INV)
+      #define GPIO_INV_REG7   GPIO_HWORD_REG7(INV)
+   #endif
+#endif /* !defined(DRV_GPIO_REG_AS_6270A) */
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/******************GPIO inversion control register value**************************************/
+/************************************END******************************************************/ 
+/*********************************************************************************************/ 
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*****************************GPIO Output register value**************************************/
+/************************************START*****************************************************/ 
+/*********************************************************************************************/ 
+
+   #define GPIO_OUTPUT_REG1   GPIO_HWORD_REG1(OUTPUT_LEVEL)
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_OUTPUT_REG2   GPIO_HWORD_REG2(OUTPUT_LEVEL)
+#if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_6270A)
+   #define GPIO_OUTPUT_REG3   GPIO_HWORD_REG3(OUTPUT_LEVEL)
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6253E)
+      #define GPIO_OUTPUT_REG4   GPIO_HWORD_REG4(OUTPUT_LEVEL)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6228)
+      #define GPIO_OUTPUT_REG5   GPIO_HWORD_REG5(OUTPUT_LEVEL)
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T)  || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1)
+      #define GPIO_OUTPUT_REG4   GPIO_HWORD_REG4(OUTPUT_LEVEL)
+      #define GPIO_OUTPUT_REG5   GPIO_HWORD_REG5(OUTPUT_LEVEL)
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255)
+         #define GPIO_OUTPUT_REG6   GPIO_HWORD_REG6(OUTPUT_LEVEL)
+      #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+         #define GPIO_OUTPUT_REG6   GPIO_HWORD_REG6(OUTPUT_LEVEL)
+         #define GPIO_OUTPUT_REG7   GPIO_HWORD_REG7(OUTPUT_LEVEL)
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255)
+      #define GPIO_OUTPUT_REG4   GPIO_HWORD_REG4(OUTPUT_LEVEL)
+      #define GPIO_OUTPUT_REG5   GPIO_HWORD_REG5(OUTPUT_LEVEL)
+      #define GPIO_OUTPUT_REG6   GPIO_HWORD_REG6(OUTPUT_LEVEL)
+      #define GPIO_OUTPUT_REG7   GPIO_HWORD_REG7(OUTPUT_LEVEL)
+   #endif
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_6270A) */
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*****************************GPIO Output register value**************************************/
+/************************************END*****************************************************/ 
+/*********************************************************************************************/ 
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*****************************GPO Output register value**************************************/
+/************************************START*****************************************************/ 
+/*********************************************************************************************/ 
+
+#if (!defined(DRV_GPIO_WO_GPO))
+   #define GPO_OUTPUT_REG1   GPO_HWORD_REG1(OUTPUT_LEVEL)
+#endif
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*****************************GPO Output register value**************************************/
+/************************************END*****************************************************/ 
+/*********************************************************************************************/ 
+  
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/****************************GPIO PULL up/down selection register value***********************/
+/************************************START*****************************************************/ 
+/*********************************************************************************************/ 
+
+#if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_TK6516) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6270A) || defined(DRV_GPIO_REG_AS_6253E)  || defined(DRV_GPIO_REG_AS_6276)|| defined(DRV_GPIO_REG_AS_6251) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6290)
+   #define GPIO_PULLSEL_REG1   GPIO_HWORD_REG1(PULL_SEL)
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_PULLSEL_REG2   GPIO_HWORD_REG2(PULL_SEL)
+#if defined(DRV_GPIO_REG_AS_6251)
+   #define GPIO_PULLSEL_REG3   GPIO_HWORD_REG3_TO_38(PULL_SEL)
+#elif !defined(DRV_GPIO_REG_AS_6270A) && !defined(DRV_GPIO_REG_AS_6290)
+   #define GPIO_PULLSEL_REG3   GPIO_HWORD_REG3(PULL_SEL)
+   #define GPIO_PULLSEL_REG4   GPIO_HWORD_REG4(PULL_SEL)
+#if !defined(DRV_GPIO_REG_AS_6253E)
+   #define GPIO_PULLSEL_REG5   GPIO_HWORD_REG5(PULL_SEL)
+   #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255)
+      #define GPIO_PULLSEL_REG6   GPIO_HWORD_REG6(PULL_SEL)
+   #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+      #define GPIO_PULLSEL_REG6   GPIO_HWORD_REG6(PULL_SEL)
+      #define GPIO_PULLSEL_REG7   GPIO_HWORD_REG7(PULL_SEL)
+   #endif
+#endif /* !defined(DRV_GPIO_REG_AS_6253E) */
+#endif /* !defined(DRV_GPIO_REG_AS_6270A) */
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+#elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255) 
+	#define GPIO_PULLSEL_REG1   GPIO_HWORD_REG1(PULL_SEL)
+	#define GPIO_PULLSEL_REG2   GPIO_HWORD_REG2(PULL_SEL)
+	#define GPIO_PULLSEL_REG3   GPIO_HWORD_REG3(PULL_SEL)
+	#define GPIO_PULLSEL_REG4   GPIO_HWORD_REG4(PULL_SEL)
+	#define GPIO_PULLSEL_REG5   GPIO_HWORD_REG5(PULL_SEL)
+	#define GPIO_PULLSEL_REG6   GPIO_HWORD_REG6(PULL_SEL)
+	#define GPIO_PULLSEL_REG7   GPIO_HWORD_REG7(PULL_SEL)
+#endif /* defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) */
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/****************************GPIO PULL up/down selection register value***********************/
+/************************************END*****************************************************/ 
+/*********************************************************************************************/ 
+
+#if defined(DRV_GPIO_REG_AS_6253E)
+   #define GPIO_SPMODE_REG ((SP_MODE_BIT0) | (SP_MODE_BIT2<<2) | (SP_MODE_BIT4<<4) | (SP_MODE_BIT6<<6) | (SP_MODE_BIT8<<8))
+   #define GPIO_BANK_REG ((BANK0) | (BANK1<<1) | (BANK2<<2) | (BANK3<<3) | (BANK4<<4) | (BANK5<<5) | (BANK6<<6) | (BANK7<<7))
+#endif //defined(DRV_GPIO_REG_AS_6253E)
+
+//this need to confirm after WS.chen work done!!!!
+#if defined(DRV_GPIO_REG_AS_6253E_1)
+   #define GPIO_SPMODE0_REG ((SP_MODE0_BIT0) | (SP_MODE0_BIT2<<2) | (SP_MODE0_BIT4<<4) | (SP_MODE0_BIT6<<6) | (SP_MODE0_BIT8<<8) |\
+   	   (SP_MODE0_BIT10<<10) | (SP_MODE0_BIT12<<12) | (SP_MODE0_BIT14<<14) | (SP_MODE0_BIT16<<16) | (SP_MODE0_BIT18<<18) |\
+   	   (SP_MODE0_BIT20<<20) | (SP_MODE0_BIT22<<22) | (SP_MODE0_BIT24<<24) | (SP_MODE0_BIT26<<26) | (SP_MODE0_BIT28<<28) |\
+   	   (SP_MODE0_BIT30<<30))
+
+   #define GPIO_SPMODE1_REG ((SP_MODE1_BIT0) | (SP_MODE1_BIT2<<2) | (SP_MODE1_BIT4<<4) | (SP_MODE1_BIT8<<8) | (SP_MODE1_BIT12<<12) |\
+   	   (SP_MODE1_BIT14<<14))
+  // #define GPIO_BANK_REG ((BANK0) | (BANK1<<1) | (BANK2<<2) | (BANK3<<3) | (BANK4<<4) | (BANK5<<5) | (BANK6<<6) | (BANK7<<7))
+#endif //defined(DRV_GPIO_REG_AS_6253E_1)
+
+
+
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/**************************** General macros to calulate GPIO word-length variable************/
+/**************************value with 1 bit unit for different platform***********************/
+/************************************START*****************************************************/ 
+/*********************************************************************************************/ 
+
+#if defined(DRV_GPIO_REG_AS_TK6516)
+   #define GPIO_WORD_VAR0(name)  GPIO_WORD_VAR_FOR_1BIT(name, 0, 1, 2, 3, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                    NULL, NULL, NULL, NULL)		
+#elif defined(DRV_GPIO_REG_AS_6205B)
+   #define GPIO_WORD_VAR0(name)  GPIO_WORD_VAR_FOR_1BIT(name, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+                                                    20, 21, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)		
+#elif defined(DRV_GPIO_REG_AS_6270A)
+   #define GPIO_WORD_VAR0(name)  GPIO_WORD_VAR_FOR_1BIT(name, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+                                                    20, 21, 22, 23, 24, 25, 26, 27, NULL, NULL, NULL, NULL)		
+#elif defined(DRV_GPIO_REG_AS_6251)
+   #define GPIO_WORD_VAR0(name)  GPIO_WORD_VAR_FOR_1BIT(name, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+                                                    20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)		
+   #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                       NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+#else /* defined(DRV_GPIO_REG_AS_6270A) */
+   #define GPIO_WORD_VAR0(name)  GPIO_WORD_VAR_FOR_1BIT(name, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+                                                    20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)		
+   #if defined(DRV_GPIO_REG_AS_6218B)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, NULL, \
+                                                       NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6225)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                       49, 50, 51, 52, 53, 54, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6227)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                       49, 50, 51, 52, 53, 54, 55, 56, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6228)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6223)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                       49, 50, 51, 52, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6238)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, \
+                                                  79, 80, 81, 82, 83, 84, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6235)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6236)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, \
+                                                  79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95)
+      #if defined(DRV_GPIO_REG_AS_6268A)
+      #define GPIO_WORD_VAR3(name)  GPIO_WORD_VAR_FOR_1BIT(name, 96, 97, 98, 99, 100, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6268)
+      #define GPIO_WORD_VAR3(name)  GPIO_WORD_VAR_FOR_1BIT(name, 96, 97, 98, 99, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL)
+      #elif defined(DRV_GPIO_REG_AS_6276)
+      #define GPIO_WORD_VAR3(name)  GPIO_WORD_VAR_FOR_1BIT(name, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL)
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6253T)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, \
+                                                  79, 80, 81, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6255)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, \
+                                                  79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95)
+      #define GPIO_WORD_VAR3(name)  GPIO_WORD_VAR_FOR_1BIT(name, 96, 97, 98, 99, 100, 101, 102, 103, 104, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6253E)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63) 
+   #elif defined(DRV_GPIO_REG_AS_6253E_1)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL)                                            
+#elif defined(DRV_GPIO_REG_AS_6256) 
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+      #define GPIO_WORD_VAR2(name)  GPIO_WORD_VAR_FOR_1BIT(name, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, \
+                                                  79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95)
+      #define GPIO_WORD_VAR3(name)  GPIO_WORD_VAR_FOR_1BIT(name, 96, 97, 98, 99, 100, 101, 102, 103, 104, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, \
+                                                  NULL, NULL, NULL, NULL, NULL)
+   #elif defined(DRV_GPIO_REG_AS_6290)
+      #define GPIO_WORD_VAR1(name)  GPIO_WORD_VAR_FOR_1BIT(name, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                                                  49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
+
+#endif
+
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/**************************** General macros to calulate GPIO word-length variable************/
+/**************************value with 1 bit unit for different platform***********************/
+/************************************END*****************************************************/ 
+/*********************************************************************************************/ 
+
+
+  
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/**************************** For each GPIO mode, specify if each GPIO pin is allowed to ******/
+/****************set to this mode with '1' allowed, '0' on the corresponding bit position******/
+/**********  Bit 0 means GPIO0, Bit 1 means GPIO1... etc ****************************************/ 
+/**************************************START****************************************************/ 
+/************************************************************************************************/ 
+
+   #define GPIO_MODE0_VAR0  GPIO_WORD_VAR0(MODE0)
+   #define GPIO_MODE1_VAR0  GPIO_WORD_VAR0(MODE1)
+   #define GPIO_MODE2_VAR0  GPIO_WORD_VAR0(MODE2)
+   #define GPIO_MODE3_VAR0  GPIO_WORD_VAR0(MODE3)
+   #if defined(DRV_GPIO_MODE_3BITS)
+   #define GPIO_MODE4_VAR0  GPIO_WORD_VAR0(MODE4)
+   #elif defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_MODE4_VAR0  GPIO_WORD_VAR0(MODE4)
+   #define GPIO_MODE5_VAR0  GPIO_WORD_VAR0(MODE5)
+   #define GPIO_MODE6_VAR0  GPIO_WORD_VAR0(MODE6)
+   #define GPIO_MODE7_VAR0  GPIO_WORD_VAR0(MODE7)
+   #endif //defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_DIROUT_VAR0  GPIO_WORD_VAR0(DIR_OUT)
+   #define GPIO_DIRIN_VAR0  GPIO_WORD_VAR0(DIR_IN)
+   
+   #if defined(DRV_GPIO_REG_AS_6251)
+   #define GPIO_DIROUT_VAR1  GPIO_WORD_VAR1(DIR_OUT)
+   #define GPIO_DIRIN_VAR1  GPIO_WORD_VAR1(DIR_IN)
+   #elif !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A)
+   #define GPIO_MODE0_VAR1  GPIO_WORD_VAR1(MODE0)
+   #define GPIO_MODE1_VAR1  GPIO_WORD_VAR1(MODE1)
+   #define GPIO_MODE2_VAR1  GPIO_WORD_VAR1(MODE2)
+   #define GPIO_MODE3_VAR1  GPIO_WORD_VAR1(MODE3)
+   #if defined(DRV_GPIO_MODE_3BITS)
+   #define GPIO_MODE4_VAR1  GPIO_WORD_VAR1(MODE4)
+   #elif defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_MODE4_VAR1  GPIO_WORD_VAR1(MODE4)
+   #define GPIO_MODE5_VAR1  GPIO_WORD_VAR1(MODE5)
+   #define GPIO_MODE6_VAR1  GPIO_WORD_VAR1(MODE6)
+   #define GPIO_MODE7_VAR1  GPIO_WORD_VAR1(MODE7)
+   #endif //defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_DIROUT_VAR1  GPIO_WORD_VAR1(DIR_OUT)
+   #define GPIO_DIRIN_VAR1  GPIO_WORD_VAR1(DIR_IN)
+   
+   #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6256)
+   #define GPIO_MODE0_VAR2     GPIO_WORD_VAR2(MODE0)
+   #define GPIO_MODE1_VAR2     GPIO_WORD_VAR2(MODE1)
+   #define GPIO_MODE2_VAR2     GPIO_WORD_VAR2(MODE2)
+   #define GPIO_MODE3_VAR2     GPIO_WORD_VAR2(MODE3)
+   #if defined(DRV_GPIO_MODE_3BITS)
+   #define GPIO_MODE4_VAR2  GPIO_WORD_VAR2(MODE4)
+   #elif defined(DRV_GPIO_MODE_4BITS) 
+   #define GPIO_MODE4_VAR2  GPIO_WORD_VAR2(MODE4)
+   #define GPIO_MODE5_VAR2  GPIO_WORD_VAR2(MODE5)
+   #define GPIO_MODE6_VAR2  GPIO_WORD_VAR2(MODE6)
+   #define GPIO_MODE7_VAR2  GPIO_WORD_VAR2(MODE7)
+   #endif //defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_DIROUT_VAR2    GPIO_WORD_VAR2(DIR_OUT)
+   #define GPIO_DIRIN_VAR2     GPIO_WORD_VAR2(DIR_IN)
+   #endif /* DRV_GPIO_REG_AS_6228 */
+   
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6256)|| defined(DRV_GPIO_REG_AS_6255)
+   #define GPIO_MODE0_VAR3     GPIO_WORD_VAR3(MODE0)
+   #define GPIO_MODE1_VAR3     GPIO_WORD_VAR3(MODE1)
+   #define GPIO_MODE2_VAR3     GPIO_WORD_VAR3(MODE2)
+   #define GPIO_MODE3_VAR3     GPIO_WORD_VAR3(MODE3)
+   #if defined(DRV_GPIO_MODE_3BITS)
+   #define GPIO_MODE4_VAR3  GPIO_WORD_VAR3(MODE4)   
+   #elif defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_MODE4_VAR3  GPIO_WORD_VAR3(MODE4)
+   #define GPIO_MODE5_VAR3  GPIO_WORD_VAR3(MODE5)
+   #define GPIO_MODE6_VAR3  GPIO_WORD_VAR3(MODE6)
+   #define GPIO_MODE7_VAR3  GPIO_WORD_VAR3(MODE7)
+   #endif //defined(DRV_GPIO_MODE_4BITS)
+   #define GPIO_DIROUT_VAR3    GPIO_WORD_VAR3(DIR_OUT)
+   #define GPIO_DIRIN_VAR3     GPIO_WORD_VAR3(DIR_IN)
+   #endif /* DRV_GPIO_REG_AS_6228 */
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A) */
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/**************************** For each GPIO mode, specify if each GPIO pin is allowed to ******/
+/****************set to this mode with '1' allowed, '0' on the corresponding bit position******/
+/**********  Bit 0 means GPIO0, Bit 1 means GPIO1... etc ****************************************/ 
+/**************************************END****************************************************/ 
+/************************************************************************************************/ 
+
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/**************************** For each GPO mode, specify if each GPO pin is allowed to ******/
+/****************set to this mode with '1' allowed, '0' on the corresponding bit position******/
+/**********  Bit 0 means GPO0, Bit 1 means GPO1... etc ****************************************/ 
+/**************************************START****************************************************/ 
+/************************************************************************************************/ 
+
+#if defined(DRV_GPIO_REG_AS_6205B) || defined(DRV_GPIO_REG_AS_6225)
+   #define GPO_MODE0_VAR0  (MODE0_GPO0 | (MODE0_GPO1 << 1) | (MODE0_GPO2 << 2) | (MODE0_GPO3 << 3))
+   #define GPO_MODE1_VAR0  (MODE1_GPO0 | (MODE1_GPO1 << 1) | (MODE1_GPO2 << 2) | (MODE1_GPO3 << 3))
+   #define GPO_MODE2_VAR0  (MODE2_GPO0 | (MODE2_GPO1 << 1) | (MODE2_GPO2 << 2) | (MODE2_GPO3 << 3))
+   #define GPO_MODE3_VAR0  (MODE3_GPO0 | (MODE3_GPO1 << 1) | (MODE3_GPO2 << 2) | (MODE3_GPO3 << 3))
+#elif defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227)
+   #define GPO_MODE0_VAR0  (MODE0_GPO0 | (MODE0_GPO1 << 1) | (MODE0_GPO2 << 2) | (MODE0_GPO3 << 3) | (MODE0_GPO4 << 4))
+   #define GPO_MODE1_VAR0  (MODE1_GPO0 | (MODE1_GPO1 << 1) | (MODE1_GPO2 << 2) | (MODE1_GPO3 << 3) | (MODE1_GPO4 << 4))
+   #define GPO_MODE2_VAR0  (MODE2_GPO0 | (MODE2_GPO1 << 1) | (MODE2_GPO2 << 2) | (MODE2_GPO3 << 3) | (MODE2_GPO4 << 4))
+   #define GPO_MODE3_VAR0  (MODE3_GPO0 | (MODE3_GPO1 << 1) | (MODE3_GPO2 << 2) | (MODE3_GPO3 << 3) | (MODE3_GPO4 << 4))
+#elif defined(DRV_GPIO_REG_AS_6218B) || defined(DRV_GPIO_REG_AS_6228)
+   #define GPO_MODE0_VAR0  (MODE0_GPO0 | (MODE0_GPO1 << 1) | (MODE0_GPO2 << 2))
+   #define GPO_MODE1_VAR0  (MODE1_GPO0 | (MODE1_GPO1 << 1) | (MODE1_GPO2 << 2))
+   #define GPO_MODE2_VAR0  (MODE2_GPO0 | (MODE2_GPO1 << 1) | (MODE2_GPO2 << 2))
+   #define GPO_MODE3_VAR0  (MODE3_GPO0 | (MODE3_GPO1 << 1) | (MODE3_GPO2 << 2))
+#endif
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/**************************** For each GPO mode, specify if each GPO pin is allowed to ******/
+/****************set to this mode with '1' allowed, '0' on the corresponding bit position******/
+/**********  Bit 0 means GPO0, Bit 1 means GPO1... etc ****************************************/ 
+/**************************************END****************************************************/ 
+/************************************************************************************************/ 
+
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*** The '1' of the bit in the variables denotes that the mode is allowed to be set for the **/
+/*** corresponding pin.******************gpio_mode_allowed[][4]*******************************/
+/**************************************START***************************************************/
+/**********************************************************************************************/ 
+#if !defined(DRV_GPIO_MODE_4BITS) && !defined(DRV_GPIO_MODE_3BITS) && !defined(DRV_GPIO_REG_AS_6290)
+const kal_uint32  gpio_mode_allowed[][4] = {
+   {GPIO_MODE0_VAR0, GPIO_MODE1_VAR0, GPIO_MODE2_VAR0, GPIO_MODE3_VAR0}
+   #if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A)
+   ,{GPIO_MODE0_VAR1, GPIO_MODE1_VAR1, GPIO_MODE2_VAR1, GPIO_MODE3_VAR1}
+   #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276)
+   ,{GPIO_MODE0_VAR2, GPIO_MODE1_VAR2, GPIO_MODE2_VAR2, GPIO_MODE3_VAR2}
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+   ,{GPIO_MODE0_VAR3, GPIO_MODE1_VAR3, GPIO_MODE2_VAR3, GPIO_MODE3_VAR3}
+   #endif
+   #endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+};
+#elif defined(DRV_GPIO_MODE_4BITS)//#if defined(DRV_GPIO_MODE_4BITS)
+const kal_uint32  gpio_mode_allowed[][8] = {
+#if defined(DRV_GPIO_REG_AS_6255)
+   {GPIO_MODE0_VAR0, GPIO_MODE1_VAR0, GPIO_MODE2_VAR0, GPIO_MODE3_VAR0, GPIO_MODE4_VAR0, GPIO_MODE5_VAR0, GPIO_MODE6_VAR0, GPIO_MODE7_VAR0}
+   ,{GPIO_MODE0_VAR1, GPIO_MODE1_VAR1, GPIO_MODE2_VAR1, GPIO_MODE3_VAR1, GPIO_MODE4_VAR1, GPIO_MODE5_VAR1, GPIO_MODE6_VAR1, GPIO_MODE7_VAR1}
+   ,{GPIO_MODE0_VAR2, GPIO_MODE1_VAR2, GPIO_MODE2_VAR2, GPIO_MODE3_VAR2, GPIO_MODE4_VAR2, GPIO_MODE5_VAR2, GPIO_MODE6_VAR2, GPIO_MODE7_VAR2}
+   ,{GPIO_MODE0_VAR3, GPIO_MODE1_VAR3, GPIO_MODE2_VAR3, GPIO_MODE3_VAR3, GPIO_MODE4_VAR3, GPIO_MODE5_VAR3, GPIO_MODE6_VAR3, GPIO_MODE7_VAR3}
+#elif defined(DRV_GPIO_REG_AS_6256)
+    {GPIO_MODE0_VAR0, GPIO_MODE1_VAR0, GPIO_MODE2_VAR0, GPIO_MODE3_VAR0, GPIO_MODE4_VAR0, GPIO_MODE5_VAR0, GPIO_MODE6_VAR0, GPIO_MODE7_VAR0}
+   ,{GPIO_MODE0_VAR1, GPIO_MODE1_VAR1, GPIO_MODE2_VAR1, GPIO_MODE3_VAR1, GPIO_MODE4_VAR1, GPIO_MODE5_VAR1, GPIO_MODE6_VAR1, GPIO_MODE7_VAR1}
+   ,{GPIO_MODE0_VAR2, GPIO_MODE1_VAR2, GPIO_MODE2_VAR2, GPIO_MODE3_VAR2, GPIO_MODE4_VAR2, GPIO_MODE5_VAR2, GPIO_MODE6_VAR2, GPIO_MODE7_VAR2}
+   ,{GPIO_MODE0_VAR3, GPIO_MODE1_VAR3, GPIO_MODE2_VAR3, GPIO_MODE3_VAR3, GPIO_MODE4_VAR3, GPIO_MODE5_VAR3, GPIO_MODE6_VAR3, GPIO_MODE7_VAR3}
+#elif defined(DRV_GPIO_REG_AS_6253E_1)
+   {GPIO_MODE0_VAR0, GPIO_MODE1_VAR0, GPIO_MODE2_VAR0, GPIO_MODE3_VAR0, GPIO_MODE4_VAR0, GPIO_MODE5_VAR0, GPIO_MODE6_VAR0, GPIO_MODE7_VAR0}
+   ,{GPIO_MODE0_VAR1, GPIO_MODE1_VAR1, GPIO_MODE2_VAR1, GPIO_MODE3_VAR1, GPIO_MODE4_VAR1, GPIO_MODE5_VAR1, GPIO_MODE6_VAR1, GPIO_MODE7_VAR1}
+#elif defined(DRV_GPIO_REG_AS_6251)
+   {GPIO_MODE0_VAR0, GPIO_MODE1_VAR0, GPIO_MODE2_VAR0, GPIO_MODE3_VAR0, GPIO_MODE4_VAR0, GPIO_MODE5_VAR0, GPIO_MODE6_VAR0, GPIO_MODE7_VAR0}
+#endif //defined(DRV_GPIO_REG_AS_6255)
+};
+#elif defined(DRV_GPIO_MODE_3BITS)
+const kal_uint32  gpio_mode_allowed[][5] = {
+#if defined(DRV_GPIO_REG_AS_6276)
+    {GPIO_MODE0_VAR0, GPIO_MODE1_VAR0, GPIO_MODE2_VAR0, GPIO_MODE3_VAR0,GPIO_MODE4_VAR0}
+   ,{GPIO_MODE0_VAR1, GPIO_MODE1_VAR1, GPIO_MODE2_VAR1, GPIO_MODE3_VAR1,GPIO_MODE4_VAR1}
+   ,{GPIO_MODE0_VAR2, GPIO_MODE1_VAR2, GPIO_MODE2_VAR2, GPIO_MODE3_VAR2,GPIO_MODE4_VAR2}
+   ,{GPIO_MODE0_VAR3, GPIO_MODE1_VAR3, GPIO_MODE2_VAR3, GPIO_MODE3_VAR3,GPIO_MODE4_VAR3}
+#endif  
+};
+
+#endif //#if !defined(DRV_GPIO_MODE_4BITS) && !defined(DRV_GPIO_MODE_3BITS)
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*** The '1' of the bit in the variables denotes that the mode is allowed to be set for the **/
+/*** corresponding pin.***********************************************************************/
+/*************************************START***************************************************/
+/**********************************************************************************************/ 
+
+kal_uint32  gpio_check_for_write[] = {
+   0xffffffff
+   #if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A)
+   #if defined(DRV_GPIO_REG_AS_6251)
+   ,0x0
+   #else //defined(DRV_GPIO_REG_AS_6251)
+   ,0xffffffff
+   #endif //defined(DRV_GPIO_REG_AS_6251)
+   #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6256)
+   ,0xffffffff
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6256)
+   ,0xffffffff
+   #endif /* DRV_GPIO_REG_AS_6268A */
+   #endif
+   #endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+};
+
+kal_uint32  gpio_check_for_read[] = {
+   0xffffffff
+   #if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A)
+   #if defined(DRV_GPIO_REG_AS_6251)
+   ,0x0
+   #else //defined(DRV_GPIO_REG_AS_6251)
+   ,0xffffffff
+   #endif //defined(DRV_GPIO_REG_AS_6251)
+   #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6256)
+   ,0xffffffff
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6256)
+   ,0xffffffff
+   #endif /* DRV_GPIO_REG_AS_6268A */
+   #endif
+   #endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+};
+
+/* The '1' of the bit in the variables denotes that the direction output is allowed to be 
+   set for the corresponding pin. */
+const kal_uint32  gpio_dir_out_allowed[] = {
+   GPIO_DIROUT_VAR0
+   #if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A)
+   ,GPIO_DIROUT_VAR1
+   #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6256)
+   ,GPIO_DIROUT_VAR2
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6256)
+   ,GPIO_DIROUT_VAR3
+   #endif
+   #endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+};
+
+/* The '1' of the bit in the variables denotes that the direction input is allowed to be 
+   set for the corresponding pin. */
+const kal_uint32  gpio_dir_in_allowed[] = {
+	GPIO_DIRIN_VAR0
+   #if !defined(DRV_GPIO_REG_AS_6205B) && !defined(DRV_GPIO_REG_AS_TK6516) && !defined(DRV_GPIO_REG_AS_6270A)
+   ,GPIO_DIRIN_VAR1
+   #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6256)
+   ,GPIO_DIRIN_VAR2
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6256)
+   ,GPIO_DIRIN_VAR3
+   #endif
+   #endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+};
+
+#if (!defined(DRV_GPIO_WO_GPO))
+const kal_uint16  gpo_mode_allowed[] = {
+	GPO_MODE0_VAR0, GPO_MODE1_VAR0, GPO_MODE2_VAR0, GPO_MODE3_VAR0
+};
+kal_uint16  gpo_check_for_write[] = {
+	0xffff
+};
+#endif /*!defined(DRV_GPIO_REG_AS_6223)*/
+
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/*** The '1' of the bit in the variables denotes that the mode is allowed to be set for the **/
+/*** corresponding pin.***********************************************************************/
+/*************************************END*****************************************************/
+/**********************************************************************************************/ 
+
+#if defined(MT6276_S01)
+#define CLK_MUX_SEL0_VALUE (CLKSEL1 | (CLKSEL2<<4) | (CLKSEL3<<8)| (CLKSEL4<<12) \
+														|(CLKSEL5<<16)|(CLKSEL6<<20)|(CLKSEL7<<24)|(CLKSEL8<<28))
+														
+#define CLK_MUX_SEL1_VALUE (CLKSEL9 | (CLKSEL10<<4) | (CLKSEL11<<8)| (CLKSEL12<<12) \
+														|(CLKSEL13<<16))
+const kal_uint32 GPIO_CLK_SEL[13]={CLKSEL1,CLKSEL2,CLKSEL3,CLKSEL4,CLKSEL5,CLKSEL6,CLKSEL7, \
+                                    CLKSEL8,CLKSEL9,CLKSEL10,CLKSEL11,CLKSEL12,CLKSEL13};
+#endif
+
+#endif /* __CHIP_SUPP_GPIO_DRV_TOOL__ */
+
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/************************************** GPIO_Setting_init*************************************/
+/************************************START***************************************************/
+/**********************************************************************************************/ 
+
+void GPIO_setting_init(void)
+{
+#if !defined(DRV_GPIO_OFF)
+#if defined(__CHIP_SUPP_GPIO_DRV_TOOL__)
+#if defined(DRV_GPIO_6290_SERIES)
+//	PDN_CLR(PDN_GPIO);
+#if 0 // !defined(TK6291)
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+#if !defined(DRV_GPIO_MODE_4BITS) && !defined(DRV_GPIO_MODE_3BITS) && !defined(DRV_GPIO_6290_SERIES)
+   DRV_GPIO_WriteReg(GPIO_MODE1, GPIO_MODE_REG1);
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   DRV_GPIO_WriteReg(GPIO_MODE2, GPIO_MODE_REG2);
+   DRV_GPIO_WriteReg(GPIO_MODE3, GPIO_MODE_REG3);
+#if defined(DRV_GPIO_REG_AS_6205B)
+   /* Note that for MT6205B, GPO mode register is on GPIO_MODE3, not GPO_MODE. */
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPO_MODE_REG);
+#elif defined(DRV_GPIO_REG_AS_6270A)
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPIO_MODE_REG4);
+#else /* defined(DRV_GPIO_REG_AS_6270A) */
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPIO_MODE_REG4);
+   DRV_GPIO_WriteReg(GPIO_MODE5, GPIO_MODE_REG5);
+   DRV_GPIO_WriteReg(GPIO_MODE6, GPIO_MODE_REG6);
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E)
+   DRV_GPIO_WriteReg(GPIO_MODE7, GPIO_MODE_REG7);
+      #if defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6276)
+      DRV_GPIO_WriteReg(GPIO_MODE8, GPIO_MODE_REG8);
+         #if defined(DRV_GPIO_REG_AS_6228)
+         DRV_GPIO_WriteReg(GPIO_MODE9, GPIO_MODE_REG9);
+         DRV_GPIO_WriteReg(GPIO_MODE10, GPIO_MODE_REG10);
+         #endif
+         #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276)
+         DRV_GPIO_WriteReg(GPIO_MODE9, GPIO_MODE_REG9);
+            #if !defined(DRV_GPIO_REG_AS_6236) 
+            DRV_GPIO_WriteReg(GPIO_MODEA, GPIO_MODE_REGA);
+               #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T)
+               DRV_GPIO_WriteReg(GPIO_MODEB, GPIO_MODE_REGB);
+               #endif
+               #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+               DRV_GPIO_WriteReg(GPIO_MODEB, GPIO_MODE_REGB);
+               DRV_GPIO_WriteReg(GPIO_MODEC, GPIO_MODE_REGC);
+               DRV_GPIO_WriteReg(GPIO_MODED, GPIO_MODE_REGD);
+                  #if  defined(DRV_GPIO_REG_AS_6276)
+                  DRV_GPIO_WriteReg(GPIO_MODEE, GPIO_MODE_REGE);
+                  #endif // defined(DRV_GPIO_REG_AS_6276)
+               #endif
+            #endif //!defined(DRV_GPIO_REG_AS_6236) 
+         #endif
+      #endif
+   #endif
+   #if (!defined(DRV_GPIO_WO_GPO))
+   DRV_GPIO_WriteReg(GPO_MODE, GPO_MODE_REG);
+   #endif
+#endif /* defined(DRV_GPIO_REG_AS_6205B) */
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+#elif defined(DRV_GPIO_MODE_3BITS)
+#if defined(DRV_GPIO_REG_AS_6276)
+   DRV_GPIO_WriteReg(GPIO_MODE0, GPIO_MODE_REG0);
+   DRV_GPIO_WriteReg(GPIO_MODE1, GPIO_MODE_REG1);
+   DRV_GPIO_WriteReg(GPIO_MODE2, GPIO_MODE_REG2);
+   DRV_GPIO_WriteReg(GPIO_MODE3, GPIO_MODE_REG3);
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPIO_MODE_REG4);
+   DRV_GPIO_WriteReg(GPIO_MODE5, GPIO_MODE_REG5);
+   DRV_GPIO_WriteReg(GPIO_MODE6, GPIO_MODE_REG6);
+   DRV_GPIO_WriteReg(GPIO_MODE7, GPIO_MODE_REG7);
+   DRV_GPIO_WriteReg(GPIO_MODE8, GPIO_MODE_REG8);
+   DRV_GPIO_WriteReg(GPIO_MODE9, GPIO_MODE_REG9);
+   DRV_GPIO_WriteReg(GPIO_MODEA, GPIO_MODE_REGA);
+   DRV_GPIO_WriteReg(GPIO_MODEB, GPIO_MODE_REGB);
+   DRV_GPIO_WriteReg(GPIO_MODEC, GPIO_MODE_REGC);
+   DRV_GPIO_WriteReg(GPIO_MODED, GPIO_MODE_REGD);
+   DRV_GPIO_WriteReg(GPIO_MODEE, GPIO_MODE_REGE);
+   DRV_GPIO_WriteReg(GPIO_MODEF, GPIO_MODE_REGF);
+   DRV_GPIO_WriteReg(GPIO_MODE10, GPIO_MODE_REG10);
+   DRV_GPIO_WriteReg(GPIO_MODE11, GPIO_MODE_REG11);
+   DRV_GPIO_WriteReg(GPIO_MODE12, GPIO_MODE_REG12);
+   DRV_GPIO_WriteReg(GPIO_MODE13, GPIO_MODE_REG13);
+   DRV_GPIO_WriteReg(GPIO_MODE14, GPIO_MODE_REG14);
+   DRV_GPIO_WriteReg(GPIO_MODE15, GPIO_MODE_REG15);	
+	//wait after drv_tool check in, there should modify.
+  // DRV_GPIO_WriteReg(GPIO_MODE16, GPIO_MODE_REG16);	
+#endif   
+#else // DRV_GPIO_MODE_4BITS is not defined
+#if defined(DRV_GPIO_REG_AS_6253E_1)
+   DRV_GPIO_WriteReg32(GPIO_MODE1, GPIO_MODE_REG1);
+   DRV_GPIO_WriteReg32(GPIO_MODE2, GPIO_MODE_REG2);
+   DRV_GPIO_WriteReg32(GPIO_MODE3, GPIO_MODE_REG3);
+   DRV_GPIO_WriteReg32(GPIO_MODE4, GPIO_MODE_REG4);
+   DRV_GPIO_WriteReg32(GPIO_MODE5, GPIO_MODE_REG5);
+   DRV_GPIO_WriteReg32(GPIO_MODE6, GPIO_MODE_REG6);
+   DRV_GPIO_WriteReg32(GPIO_MODE7, GPIO_MODE_REG7);
+   DRV_GPIO_WriteReg32(GPIO_MODE8, GPIO_MODE_REG8);
+   DRV_GPIO_WriteReg32(GPIO_MODE9, GPIO_MODE_REG9);
+#endif
+
+#if defined(DRV_GPIO_REG_AS_6255)
+   DRV_GPIO_WriteReg(GPIO_MODE1, GPIO_MODE_REG1);
+   DRV_GPIO_WriteReg(GPIO_MODE2, GPIO_MODE_REG2);
+   DRV_GPIO_WriteReg(GPIO_MODE3, GPIO_MODE_REG3);
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPIO_MODE_REG4);
+   DRV_GPIO_WriteReg(GPIO_MODE5, GPIO_MODE_REG5);
+   DRV_GPIO_WriteReg(GPIO_MODE6, GPIO_MODE_REG6);
+   DRV_GPIO_WriteReg(GPIO_MODE7, GPIO_MODE_REG7);
+   DRV_GPIO_WriteReg(GPIO_MODE8, GPIO_MODE_REG8);
+   DRV_GPIO_WriteReg(GPIO_MODE9, GPIO_MODE_REG9);
+   DRV_GPIO_WriteReg(GPIO_MODE10, GPIO_MODE_REG10);
+   DRV_GPIO_WriteReg(GPIO_MODE11, GPIO_MODE_REG11);
+   DRV_GPIO_WriteReg(GPIO_MODE12, GPIO_MODE_REG12);
+   DRV_GPIO_WriteReg(GPIO_MODE13, GPIO_MODE_REG13);
+   DRV_GPIO_WriteReg(GPIO_MODE14, GPIO_MODE_REG14);
+   DRV_GPIO_WriteReg(GPIO_MODE15, GPIO_MODE_REG15);
+   DRV_GPIO_WriteReg(GPIO_MODE16, GPIO_MODE_REG16);
+   DRV_GPIO_WriteReg(GPIO_MODE17, GPIO_MODE_REG17);
+   DRV_GPIO_WriteReg(GPIO_MODE18, GPIO_MODE_REG18);
+   DRV_GPIO_WriteReg(GPIO_MODE19, GPIO_MODE_REG19);
+   DRV_GPIO_WriteReg(GPIO_MODE20, GPIO_MODE_REG20);
+   DRV_GPIO_WriteReg(GPIO_MODE21, GPIO_MODE_REG21);
+   DRV_GPIO_WriteReg(GPIO_MODE22, GPIO_MODE_REG22);
+   DRV_GPIO_WriteReg(GPIO_MODE23, GPIO_MODE_REG23);
+   DRV_GPIO_WriteReg(GPIO_MODE24, GPIO_MODE_REG24);
+   DRV_GPIO_WriteReg(GPIO_MODE25, GPIO_MODE_REG25);
+   DRV_GPIO_WriteReg(GPIO_MODE26, GPIO_MODE_REG26);
+   DRV_GPIO_WriteReg(GPIO_MODE27, GPIO_MODE_REG27);
+#elif defined(DRV_GPIO_REG_AS_6251)
+   DRV_GPIO_WriteReg(GPIO_MODE1, GPIO_MODE_REG1);
+   DRV_GPIO_WriteReg(GPIO_MODE2, GPIO_MODE_REG2);
+   DRV_GPIO_WriteReg(GPIO_MODE3, GPIO_MODE_REG3);
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPIO_MODE_REG4);
+   DRV_GPIO_WriteReg(GPIO_MODE5, GPIO_MODE_REG5);
+   DRV_GPIO_WriteReg(GPIO_MODE6, GPIO_MODE_REG6);
+   DRV_GPIO_WriteReg(GPIO_MODE7, GPIO_MODE_REG7);
+   DRV_GPIO_WriteReg(GPIO_MODE8, GPIO_MODE_REG8);
+#endif //defined(DRV_GPIO_REG_AS_6255)
+#if defined(DRV_GPIO_REG_AS_6256)
+   DRV_GPIO_WriteReg(GPIO_MODE1, GPIO_MODE_REG1);
+   DRV_GPIO_WriteReg(GPIO_MODE2, GPIO_MODE_REG2);
+   DRV_GPIO_WriteReg(GPIO_MODE3, GPIO_MODE_REG3);
+   DRV_GPIO_WriteReg(GPIO_MODE4, GPIO_MODE_REG4);
+   DRV_GPIO_WriteReg(GPIO_MODE5, GPIO_MODE_REG5);
+   DRV_GPIO_WriteReg(GPIO_MODE6, GPIO_MODE_REG6);
+   DRV_GPIO_WriteReg(GPIO_MODE7, GPIO_MODE_REG7);
+   DRV_GPIO_WriteReg(GPIO_MODE8, GPIO_MODE_REG8);
+   DRV_GPIO_WriteReg(GPIO_MODE9, GPIO_MODE_REG9);
+   DRV_GPIO_WriteReg(GPIO_MODE10, GPIO_MODE_REG10);
+   DRV_GPIO_WriteReg(GPIO_MODE11, GPIO_MODE_REG11);
+   DRV_GPIO_WriteReg(GPIO_MODE12, GPIO_MODE_REG12);
+   DRV_GPIO_WriteReg(GPIO_MODE13, GPIO_MODE_REG13);
+   DRV_GPIO_WriteReg(GPIO_MODE14, GPIO_MODE_REG14);
+   DRV_GPIO_WriteReg(GPIO_MODE15, GPIO_MODE_REG15);
+   DRV_GPIO_WriteReg(GPIO_MODE16, GPIO_MODE_REG16);
+   DRV_GPIO_WriteReg(GPIO_MODE17, GPIO_MODE_REG17);
+   DRV_GPIO_WriteReg(GPIO_MODE18, GPIO_MODE_REG18);
+   DRV_GPIO_WriteReg(GPIO_MODE19, GPIO_MODE_REG19);
+   DRV_GPIO_WriteReg(GPIO_MODE20, GPIO_MODE_REG20);
+   DRV_GPIO_WriteReg(GPIO_MODE21, GPIO_MODE_REG21);
+   DRV_GPIO_WriteReg(GPIO_MODE22, GPIO_MODE_REG22);
+   DRV_GPIO_WriteReg(GPIO_MODE23, GPIO_MODE_REG23);
+   DRV_GPIO_WriteReg(GPIO_MODE24, GPIO_MODE_REG24);
+   DRV_GPIO_WriteReg(GPIO_MODE25, GPIO_MODE_REG25);
+   DRV_GPIO_WriteReg(GPIO_MODE26, GPIO_MODE_REG26);
+   DRV_GPIO_WriteReg(GPIO_MODE27, GPIO_MODE_REG27);
+#endif //defined(DRV_GPIO_REG_AS_6256)
+#endif //defined(DRV_GPIO_MODE_4BITS)
+
+#if defined(DRV_GPIO_REG_AS_6205B)
+   DRV_GPIO_WriteReg(GPIO_DIR, GPIO_DIR_REG1);
+   DRV_GPIO_WriteReg(GPIO_DIR2, GPIO_DIR_REG2);
+#elif defined(DRV_GPIO_REG_AS_TK6516)
+   DRV_GPIO_WriteReg(GPIO_DIR1, GPIO_DIR_REG1);
+#elif defined(DRV_GPIO_REG_AS_6270A)
+   DRV_GPIO_WriteReg(GPIO_DIR1, GPIO_DIR_REG1);
+   DRV_GPIO_WriteReg(GPIO_DIR2, GPIO_DIR_REG2);
+#else  /* defined(DRV_GPIO_REG_AS_6270A) */
+   
+   DRV_GPIO_WriteReg(GPIO_DIR1, GPIO_DIR_REG1);
+   DRV_GPIO_WriteReg(GPIO_DIR2, GPIO_DIR_REG2);
+   #if !defined(DRV_GPIO_REG_AS_6290)
+   DRV_GPIO_WriteReg(GPIO_DIR3, GPIO_DIR_REG3);
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E)|| defined(DRV_GPIO_REG_AS_6253E_1)
+   DRV_GPIO_WriteReg(GPIO_DIR4, GPIO_DIR_REG4);
+      #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6253E_1)
+      DRV_GPIO_WriteReg(GPIO_DIR5, GPIO_DIR_REG5);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T)
+      DRV_GPIO_WriteReg(GPIO_DIR5, GPIO_DIR_REG5);
+      DRV_GPIO_WriteReg(GPIO_DIR6, GPIO_DIR_REG6);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+      DRV_GPIO_WriteReg(GPIO_DIR5, GPIO_DIR_REG5);
+      DRV_GPIO_WriteReg(GPIO_DIR6, GPIO_DIR_REG6);
+      DRV_GPIO_WriteReg(GPIO_DIR7, GPIO_DIR_REG7);
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6256)  || defined(DRV_GPIO_REG_AS_6255)
+    DRV_GPIO_WriteReg(GPIO_DIR4, GPIO_DIR_REG4);
+    DRV_GPIO_WriteReg(GPIO_DIR5, GPIO_DIR_REG5);
+    DRV_GPIO_WriteReg(GPIO_DIR6, GPIO_DIR_REG6);
+    DRV_GPIO_WriteReg(GPIO_DIR7, GPIO_DIR_REG7); 
+   #endif
+#endif
+
+#if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_TK6516) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6270A) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6251) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1) || defined(DRV_GPIO_REG_AS_6256)  || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6290)
+   DRV_GPIO_WriteReg(GPIO_PULLSEL1, GPIO_PULLSEL_REG1);
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   DRV_GPIO_WriteReg(GPIO_PULLSEL2, GPIO_PULLSEL_REG2);
+   #if !defined(DRV_GPIO_REG_AS_6270A) && !defined(DRV_GPIO_REG_AS_6290)
+   DRV_GPIO_WriteReg(GPIO_PULLSEL3, GPIO_PULLSEL_REG3);
+   #if !defined(DRV_GPIO_REG_AS_6251)
+   DRV_GPIO_WriteReg(GPIO_PULLSEL4, GPIO_PULLSEL_REG4);
+   #if !defined(DRV_GPIO_REG_AS_6253E)
+   DRV_GPIO_WriteReg(GPIO_PULLSEL5, GPIO_PULLSEL_REG5);
+   #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) 
+   DRV_GPIO_WriteReg(GPIO_PULLSEL6, GPIO_PULLSEL_REG6);
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255)
+   DRV_GPIO_WriteReg(GPIO_PULLSEL6, GPIO_PULLSEL_REG6);
+   DRV_GPIO_WriteReg(GPIO_PULLSEL7, GPIO_PULLSEL_REG7);
+   #endif
+   #endif //!defined(DRV_GPIO_REG_AS_6253E)
+   #endif //!defined(DRV_GPIO_REG_AS_6251)
+   #endif //!defined(DRV_GPIO_REG_AS_6270A)
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+#endif
+
+#if defined(DRV_GPIO_REG_AS_6205B)
+   DRV_GPIO_WriteReg(GPIO_PULLEN, GPIO_PULL_REG1);
+   DRV_GPIO_WriteReg(GPIO_PULLEN2, GPIO_PULL_REG2);
+#elif defined(DRV_GPIO_REG_AS_TK6516)
+   DRV_GPIO_WriteReg(GPIO_PULLEN1, GPIO_PULL_REG1);
+#elif defined(DRV_GPIO_REG_AS_6270A)
+   DRV_GPIO_WriteReg(GPIO_PULLEN1, GPIO_PULL_REG1);
+   DRV_GPIO_WriteReg(GPIO_PULLEN2, GPIO_PULL_REG2);
+#else  /* defined(DRV_GPIO_REG_AS_6270A) */
+   DRV_GPIO_WriteReg(GPIO_PULLEN1, GPIO_PULL_REG1);
+   DRV_GPIO_WriteReg(GPIO_PULLEN2, GPIO_PULL_REG2);
+   #if !defined(DRV_GPIO_REG_AS_6290)
+   DRV_GPIO_WriteReg(GPIO_PULLEN3, GPIO_PULL_REG3);
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1)
+   DRV_GPIO_WriteReg(GPIO_PULLEN4, GPIO_PULL_REG4);
+      #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6253E_1)
+      DRV_GPIO_WriteReg(GPIO_PULLEN5, GPIO_PULL_REG5);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) 
+      DRV_GPIO_WriteReg(GPIO_PULLEN5, GPIO_PULL_REG5);
+      DRV_GPIO_WriteReg(GPIO_PULLEN6, GPIO_PULL_REG6);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+      DRV_GPIO_WriteReg(GPIO_PULLEN5, GPIO_PULL_REG5);
+      DRV_GPIO_WriteReg(GPIO_PULLEN6, GPIO_PULL_REG6);
+      DRV_GPIO_WriteReg(GPIO_PULLEN7, GPIO_PULL_REG7);
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255)
+      DRV_GPIO_WriteReg(GPIO_PULLEN4, GPIO_PULL_REG4);
+      DRV_GPIO_WriteReg(GPIO_PULLEN5, GPIO_PULL_REG5);
+      DRV_GPIO_WriteReg(GPIO_PULLEN6, GPIO_PULL_REG6);
+      DRV_GPIO_WriteReg(GPIO_PULLEN7, GPIO_PULL_REG7);
+   #endif
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+
+#if !defined(DRV_GPIO_REG_AS_6205B)
+   DRV_GPIO_WriteReg(GPIO_DINV1, GPIO_INV_REG1);
+#if !defined(DRV_GPIO_REG_AS_TK6516)
+   DRV_GPIO_WriteReg(GPIO_DINV2, GPIO_INV_REG2);
+   #if !defined(DRV_GPIO_REG_AS_6270A) && !defined(DRV_GPIO_REG_AS_6251) && !defined(DRV_GPIO_REG_AS_6290)
+   DRV_GPIO_WriteReg(GPIO_DINV3, GPIO_INV_REG3);
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228)  || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1)
+   DRV_GPIO_WriteReg(GPIO_DINV4, GPIO_INV_REG4);
+      #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6253E_1)
+      DRV_GPIO_WriteReg(GPIO_DINV5, GPIO_INV_REG5);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) 
+      DRV_GPIO_WriteReg(GPIO_DINV5, GPIO_INV_REG5);
+      DRV_GPIO_WriteReg(GPIO_DINV6, GPIO_INV_REG6);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+      DRV_GPIO_WriteReg(GPIO_DINV5, GPIO_INV_REG5);
+      DRV_GPIO_WriteReg(GPIO_DINV6, GPIO_INV_REG6);
+      DRV_GPIO_WriteReg(GPIO_DINV7, GPIO_INV_REG7);
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255)
+      DRV_GPIO_WriteReg(GPIO_DINV4, GPIO_INV_REG4); 
+      DRV_GPIO_WriteReg(GPIO_DINV5, GPIO_INV_REG5);
+      DRV_GPIO_WriteReg(GPIO_DINV6, GPIO_INV_REG6);
+      DRV_GPIO_WriteReg(GPIO_DINV7, GPIO_INV_REG7);  
+   #endif
+   #endif //!defined(DRV_GPIO_REG_AS_6270A)
+#endif /* !defined(DRV_GPIO_REG_AS_TK6516) */
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+
+#if defined(DRV_GPIO_REG_AS_6205B)
+   DRV_GPIO_WriteReg(GPIO_DOUT, GPIO_OUTPUT_REG1);
+   DRV_GPIO_WriteReg(GPIO_DOUT2, GPIO_OUTPUT_REG2);
+#elif defined(DRV_GPIO_REG_AS_TK6516)
+   DRV_GPIO_WriteReg(GPIO_DOUT1, GPIO_OUTPUT_REG1);
+#elif defined(DRV_GPIO_REG_AS_6270A)
+   DRV_GPIO_WriteReg(GPIO_DOUT1, GPIO_OUTPUT_REG1);
+   DRV_GPIO_WriteReg(GPIO_DOUT2, GPIO_OUTPUT_REG2);
+#else  /* defined(DRV_GPIO_REG_AS_6270A) */
+   DRV_GPIO_WriteReg(GPIO_DOUT1, GPIO_OUTPUT_REG1);
+   DRV_GPIO_WriteReg(GPIO_DOUT2, GPIO_OUTPUT_REG2);
+   #if !defined(DRV_GPIO_REG_AS_6290)
+   DRV_GPIO_WriteReg(GPIO_DOUT3, GPIO_OUTPUT_REG3);
+   #endif
+   #if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6227) || defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255) || defined(DRV_GPIO_REG_AS_6276) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1)
+   DRV_GPIO_WriteReg(GPIO_DOUT4, GPIO_OUTPUT_REG4);
+      #if defined(DRV_GPIO_REG_AS_6228) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6236) || defined(DRV_GPIO_REG_AS_6253E_1)
+      DRV_GPIO_WriteReg(GPIO_DOUT5, GPIO_OUTPUT_REG5);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6255)
+      DRV_GPIO_WriteReg(GPIO_DOUT5, GPIO_OUTPUT_REG5);
+      DRV_GPIO_WriteReg(GPIO_DOUT6, GPIO_OUTPUT_REG6);
+      #endif
+      #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+      DRV_GPIO_WriteReg(GPIO_DOUT5, GPIO_OUTPUT_REG5);
+      DRV_GPIO_WriteReg(GPIO_DOUT6, GPIO_OUTPUT_REG6);
+      DRV_GPIO_WriteReg(GPIO_DOUT7, GPIO_OUTPUT_REG7);
+      #endif
+   #elif defined(DRV_GPIO_REG_AS_6256) || defined(DRV_GPIO_REG_AS_6255)
+      DRV_GPIO_WriteReg(GPIO_DOUT4, GPIO_OUTPUT_REG4);
+      DRV_GPIO_WriteReg(GPIO_DOUT5, GPIO_OUTPUT_REG5);
+      DRV_GPIO_WriteReg(GPIO_DOUT6, GPIO_OUTPUT_REG6);
+      DRV_GPIO_WriteReg(GPIO_DOUT7, GPIO_OUTPUT_REG7); 
+   #endif
+#endif /* !defined(DRV_GPIO_REG_AS_6205B) */
+#if (!defined(DRV_GPIO_WO_GPO))
+   DRV_GPIO_WriteReg(GPO_DOUT, GPO_OUTPUT_REG1);
+#endif
+
+#if defined(DRV_GPIO_REG_AS_6253E)
+   DRV_GPIO_WriteReg(GPIO_SPMODE, GPIO_SPMODE_REG);
+   DRV_GPIO_WriteReg(GPIO_BANK, GPIO_BANK_REG);
+#elif defined(DRV_GPIO_REG_AS_6253E_1)
+   DRV_GPIO_WriteReg32(GPIO_SPMODE0, GPIO_SPMODE0_REG);
+   DRV_GPIO_WriteReg32(GPIO_SPMODE1, GPIO_SPMODE1_REG);
+#endif //defined(DRV_GPIO_REG_AS_6253E)
+
+#if defined(MT6276_S01)
+   DRV_GPIO_WriteReg32(CLK_MUX_SEL0, CLK_MUX_SEL0_VALUE);
+   DRV_GPIO_WriteReg32(CLK_MUX_SEL1, CLK_MUX_SEL1_VALUE);
+#endif
+
+#endif /* __CHIP_SUPP_GPIO_DRV_TOOL__*/
+#endif /*!defined(DRV_GPIO_OFF)*/
+}
+
+#endif /* __CUST_NEW__ */
+
+/*********************************************************************************************/
+/*********************************************************************************************/ 
+/************************************** GPIO_Setting_init*************************************/
+/************************************END******************************************************/