diff --git a/mcu/driver/devdrv/i2c/inc/drv_i2c.h b/mcu/driver/devdrv/i2c/inc/drv_i2c.h
new file mode 100644
index 0000000..8a9fd00
--- /dev/null
+++ b/mcu/driver/devdrv/i2c/inc/drv_i2c.h
@@ -0,0 +1,455 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *  i2c.h
+ *
+ *
+ * Description:
+ * ------------
+ *   I2C Driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "drv_features_i2c.h"
+#include "dcl_i2c_owner.h"
+
+#include "drv_comm.h"
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+#ifdef ATEST_DRV_ENABLE
+#define dhl_trace(...) 
+#define DRVI2C_PRINTF(x...) \
+do{                         \
+	dbg_print(x);           \
+	dbg_flush();            \
+}while(0)
+#else /*ATEST_DRV_ENABLE*/
+#include "drv_i2c_trace.h"
+#endif
+
+#ifndef __DRV_DEBUG_I2C_REG_READ_WRITE__
+#define DRV_I2C_ClearBits16(addr, data)             DRV_ClearBits(addr,data)
+#define DRV_I2C_SetBits16(addr, data)               DRV_SetBits(addr,data)
+#define DRV_I2C_WriteReg16(addr, data)              DRV_WriteReg(addr, data)
+#define DRV_I2C_ReadReg16(addr)                     DRV_Reg(addr)
+#define DRV_I2C_SetData16(addr, bitmask, value)     DRV_SetData(addr, bitmask, value)
+#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+#define DRV_I2C_ClearBits16(addr,data)              DRV_DBG_ClearBits(addr,data)
+#define DRV_I2C_SetBits16(addr)                     DRV_DBG_SetBits(addr)
+#define DRV_I2C_WriteReg16(addr, data)              DRV_DBG_WriteReg(addr, data)
+#define DRV_I2C_ReadReg16(addr)                     DRV_DBG_Reg(addr)
+#define DRV_I2C_SetData16(addr, bitmask, value)     DRV_DBG_SetData(addr, bitmask, value)
+#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+
+#define SCCB_MAXIMUM_TRANSACTION_LENGTH 8  // SCCB backward compatible
+
+#if defined(MT6885)||defined(MT6873)||defined(MT6853)
+#define I2C_CLOCK_RATE	65000 //65MHz
+#else
+#define I2C_CLOCK_RATE	12000 //12MHz
+#endif
+#define DRV_I2C_FIFO_DEPTH        8
+
+typedef enum
+{
+	I2C_TRANSACTION_COMPLETE,
+	I2C_TRANSACTION_FAIL,
+	I2C_TRANSACTION_IS_BUSY,
+	I2C_TRANSACTION_ACKERR,
+	I2C_TRANSACTION_HS_NACKERR,
+	I2C_TRANSACTION_SUCCESS,
+	I2C_TRANSACTION_TIMEOUT
+}I2C_TRANSACTION_RESULT;
+
+
+typedef enum
+{
+    I2C_IDLE_STATE = 0,
+	I2C_READY_STATE,
+	I2C_BUSY_STATE
+}I2C_STATE;
+
+/* Transaction mode for new SCCB APIs */
+typedef enum
+{
+	I2C_TRANSACTION_FAST_MODE,
+	I2C_TRANSACTION_HIGH_SPEED_MODE
+}I2C_TRANSACTION_MODE;
+
+/* Transaction type for batch transaction */
+typedef enum
+{
+	I2C_TRANSACTION_WRITE,
+	I2C_TRANSACTION_READ,
+	I2C_TRANSACTION_CONT_WRITE,
+	I2C_TRANSACTION_CONT_READ,
+	I2C_TRANSACTION_WRITE_AND_READ
+}I2C_TRANSACTION_TYPE;
+
+typedef struct
+{
+   kal_uint8 *data;
+   kal_uint32 data_len;
+}i2c_single_write_struct, i2c_single_read_struct;
+/* For I2C_CMD_CONT_WRITE, I2C_CMD_CONT_READ command. */
+typedef struct
+{
+   kal_uint8 *data;
+   kal_uint32 data_len;
+   kal_uint32 transfer_num;
+}i2c_cont_write_struct, i2c_cont_read_struct;
+/* For I2C_CMD_WRITE_AND_READ command. */
+typedef struct
+{
+   kal_uint8 *indata;
+   kal_uint32 indata_len;
+   kal_uint8 *outdata;
+   kal_uint32 outdata_len;
+}i2c_write_and_read_struct;
+/* */
+typedef union
+{
+	i2c_single_write_struct single_write;
+  i2c_single_read_struct single_read;
+  i2c_cont_write_struct cont_write;
+  i2c_cont_write_struct cont_read;
+  i2c_write_and_read_struct write_and_read;
+}i2c_transaction_data_struct;
+/* For I2C_CMD_SINGLE_BATCH command. */
+typedef struct
+{
+   I2C_TRANSACTION_TYPE transaction_type;
+   i2c_transaction_data_struct transaction_data;
+}i2c_batch_data_struct;
+
+typedef enum
+{
+	// Module source clock is 15.36Mhz
+	I2C_100KB,       //99.74KB
+	I2C_200KB,       //196.9KB
+	I2C_300KB,       //295.4KB
+	I2C_400KB,	      //384.0KB
+	/* HS Mode */
+	I2C_960KB,       //960.0KB
+	I2C_1280KB,      //1280.0KB
+	I2C_1536KB,      //1536.0KB
+	I2C_1920KB,      //1920.0KB
+	I2C_2560KB,      //2560.0KB
+	I2C_3840KB       //3840.0KB
+
+}I2C_SPEED_ENUM;
+
+typedef struct
+{
+	//kal_uint8 sccb_mode; // Transaction mode for existing SCCB APIs
+
+	kal_bool get_handle_wait; //When get handle wait until the I2C is avaliable
+
+	kal_uint8 slave_address;	//the address of the slave device
+
+	kal_uint8 delay_len;	//number of half pulse between transfers in a trasaction
+
+	I2C_TRANSACTION_MODE transaction_mode;	//I2C_TRANSACTION_FAST_MODE or I2C_TRANSACTION_HIGH_SPEED_MODE
+
+	kal_uint16 Fast_Mode_Speed;	//The speed of I2C fast mode(Kb)
+
+	kal_uint16 HS_Mode_Speed;	//The speed of I2C high speed mode(Kb)
+}i2c_config_struct;
+
+typedef struct
+{
+	i2c_config_struct  i2c_config;
+
+	kal_uint8 fs_sample_cnt_div;     //these two parameters are used to specify I2C clock rate
+	kal_uint8 fs_step_cnt_div;       //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
+
+	kal_uint8 hs_sample_cnt_div;     //these two parameters are used to specify I2C clock rate
+	kal_uint8 hs_step_cnt_div;       //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
+
+	I2C_TRANSACTION_RESULT transaction_result; /* The result of the end of transaction
+	                                               (I2C_TRANSACTION_COMPLETE|I2C_TRANSACTION_FAIL) */
+
+}i2c_handle_struct;
+
+typedef struct
+{
+	volatile I2C_STATE  state;
+	DCL_I2C_OWNER	    owner;
+
+	kal_uint8	number_of_read;
+	kal_uint8*	read_buffer;
+
+}i2c_status_struct;
+
+
+
+#ifndef DRV_I2C_OFF
+#ifndef BASE_MADDR_MDINFRA_I2C
+#define BASE_MADDR_MDINFRA_I2C 0xA0400000
+#endif
+#define I2C_base BASE_MADDR_MDINFRA_I2C
+/* Register Definitions */
+#define REG_I2C_DATA_PORT             (I2C_base + 0x00)
+#define REG_I2C_SLAVE_ADDR            (I2C_base + 0x04)
+#define REG_I2C_INT_MASK              (I2C_base + 0x08)
+#define REG_I2C_INT_STA               (I2C_base + 0x0c)
+#define REG_I2C_CONTROL               (I2C_base + 0x10)
+#define REG_I2C_TRANSFER_LEN          (I2C_base + 0x14)
+#define REG_I2C_TRANSAC_LEN           (I2C_base + 0x18)
+#define REG_I2C_DELAY_LEN             (I2C_base + 0x1c)
+#define REG_I2C_TIMING                (I2C_base + 0x20)
+#define REG_I2C_START                 (I2C_base + 0x24)
+#define REG_I2C_FIFO_STAT             (I2C_base + 0x30)
+#define REG_I2C_FIFO_THRESH           (I2C_base + 0x34)
+#define REG_I2C_FIFO_ADDR_CLR         (I2C_base + 0x38)
+#define REG_I2C_IO_CONFIG             (I2C_base + 0x40)
+#define REG_I2C_MULTI_MASTER          (I2C_base + 0x44)
+#define REG_I2C_HS_MODE               (I2C_base + 0x48)
+#define REG_I2C_SOFTRESET             (I2C_base + 0x50)
+#define REG_I2C_TRANSFER_LEN_AUX      (I2C_base + 0x6C)     ///new from MT6256E2
+#define REG_I2C_HW_Version            (I2C_base + 0x78)
+#define REG_I2C_DBG_STA               (I2C_base + 0x64)     //only for debug
+#define REG_I2C_TIMEOUT_TIMING        (I2C_base + 0x74)     //timeout timing reg
+#define REG_SW_I2C_EN				  (I2C_base	+ 0x80)
+#define REG_SW_I2C_SCL_WR			  (I2C_base	+ 0x84)
+#define REG_SW_I2C_SDA_WR			  (I2C_base	+ 0x88)
+#define REG_SW_I2C_RD				  (I2C_base	+ 0x8C)
+
+#endif //  DRV_I2C_OFF
+
+/* Register masks */
+#define I2C_1_BIT_MASK                0x01
+#define I2C_3_BIT_MASK                0x07
+#define I2C_4_BIT_MASK                0x0f
+#define I2C_6_BIT_MASK                0x3f
+#define I2C_8_BIT_MASK                0xff
+#define I2C_16_BIT_MASK               0xffff
+
+#define I2C_RX_FIFO_THRESH_MASK       0x0007
+#define I2C_RX_FIFO_THRESH_SHIFT      0
+#define I2C_TX_FIFO_THRESH_MASK       0x0700
+#define I2C_TX_FIFO_THRESH_SHIFT      8
+
+#define I2C_AUX_LEN_MASK              0x1f00
+#define I2C_AUX_LEN_SHIFT             8
+
+#define I2C_SAMPLE_CNT_DIV_MASK       0x0700
+#define I2C_SAMPLE_CNT_DIV_SHIFT      8
+#define I2C_DATA_READ_TIME_MASK       0x7000
+#define I2C_DATA_READ_TIME_SHIFT      12
+
+#define I2C_MASTER_READ               0x01
+#define I2C_MASTER_WRITE              0x00
+
+//#define I2C_CTL_MODE_BIT            0x01
+#define I2C_CTL_RS_STOP_BIT           0x02
+#define I2C_CTL_DMA_EN_BIT            0x04
+#define I2C_CTL_CLK_EXT_EN_BIT        0x08
+#define I2C_CTL_DIR_CHANGE_BIT        0x10
+#define I2C_CTL_ACK_ERR_DET_BIT       0x20
+#define I2C_CTL_TRANSFER_LEN_CHG_BIT  0x40
+
+#define I2C_DATA_READ_ADJ_BIT         0x8000
+
+#define I2C_SCL_MODE_BIT              0x01
+#define I2C_SDA_MODE_BIT              0x02
+#define I2C_BUS_DETECT_EN_BIT         0x04
+
+#define I2C_ARBITRATION_BIT           0x01
+#define I2C_CLOCK_SYNC_BIT            0x02
+#define I2C_BUS_BUSY_DET_BIT          0x04
+
+#define I2C_HS_EN_BIT                 0x01
+#define I2C_HS_NACK_ERR_DET_EN_BIT    0x02
+#define I2C_HS_MASTER_CODE_MASK       0x0070
+#define I2C_HS_MASTER_CODE_SHIFT      4
+#define I2C_HS_STEP_CNT_DIV_MASK      0x0700
+#define I2C_HS_STEP_CNT_DIV_SHIFT     8
+#define I2C_HS_SAMPLE_CNT_DIV_MASK    0x7000
+#define I2C_HS_SAMPLE_CNT_DIV_SHIFT   12
+
+/* I2C Status */
+#define I2C_FIFO_FULL_STATUS          0x01
+#define I2C_FIFO_EMPTY_STATUS         0x02
+
+/* Register Settings */
+#define SET_I2C_SLAVE_ADDRESS(n,rw)       do{DRV_I2C_SetData16(REG_I2C_SLAVE_ADDR, I2C_8_BIT_MASK, (((n>>1)<<1) + rw));} while(0)
+
+#define DISABLE_I2C_INT                   do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK, 0);} while(0)
+#define ENABLE_I2C_INT                    do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK,I2C_1_BIT_MASK);} while(0)
+
+#define CLEAR_I2C_STA                     do{DRV_I2C_WriteReg16(REG_I2C_INT_STA, I2C_4_BIT_MASK);} while(0)
+
+//#define SET_I2C_FAST_SPEED_MODE	REG_I2C_CONTROL &= ~I2C_CTL_MODE_BIT;
+//#define SET_I2C_HIGH_SPEED_MODE	REG_I2C_CONTROL |= I2C_CTL_MODE_BIT;
+
+#define SET_I2C_ST_BETWEEN_TRANSFER       do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0)
+#define SET_I2C_RS_BETWEEN_TRANSFER       do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0)
+#define ENABLE_I2C_DMA_TRANSFER           do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0)
+#define ENABLE_I2C_CLOCK_EXTENSION        do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0)
+#define ENABLE_I2C_DIR_CHANGE             do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0)
+#define ENABLE_I2C_ACK_ERR_DET            do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0)
+#define ENABLE_I2C_TRANSFER_LEN_CHG       do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0)
+#define ENABLE_I2C_BUS_BUSY_RESET         do{DRV_I2C_SetBits16(REG_I2C_CONTROL, 0x80);} while(0)
+#define ENABLE_I2C_TIMEOUT                do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0) 
+
+#define DISABLE_I2C_DMA_TRANSFER          do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0)
+#define DISABLE_I2C_CLOCK_EXTENSION       do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0)
+#define DISABLE_I2C_DIR_CHANGE            do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0)
+#define DISABLE_I2C_ACK_ERR_DET           do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0)
+#define DISABLE_I2C_TRANSFER_LEN_CHG      do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0)
+#define DISABLE_I2C_BUS_BUSY_RESET        do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, 0x80);} while(0)
+#define DISABLE_I2C_TIMEOUT               do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0) 
+
+#ifdef DRV_I2C_MAX_65535_TRANSFER_LENGTH
+#define SET_I2C_TRANSFER_LENGTH(n)        do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_16_BIT_MASK, (n));} while(0)
+#define SET_I2C_AUX_TRANSFER_LENGTH(n)    do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN_AUX, I2C_16_BIT_MASK, (n));} while(0)
+#else
+#define SET_I2C_TRANSFER_LENGTH(n)        do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_8_BIT_MASK, (n));} while(0)
+#define SET_I2C_AUX_TRANSFER_LENGTH(n)    do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_AUX_LEN_MASK, ((n)<<I2C_AUX_LEN_SHIFT));} while(0)
+#endif
+
+#define SET_I2C_TRANSACTION_LENGTH(n)     do{DRV_I2C_SetData16(REG_I2C_TRANSAC_LEN, I2C_8_BIT_MASK, (n));} while(0)
+#define SET_I2C_DELAY_LENGTH(n)           do{DRV_I2C_SetData16(REG_I2C_DELAY_LEN, I2C_8_BIT_MASK, (n));} while(0)
+
+#define SET_I2C_STEP_CNT_DIV(n)           do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_6_BIT_MASK, (n));} while(0)
+#define SET_I2C_SAMPLE_CNT_DIV(n)         do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_SAMPLE_CNT_DIV_SHIFT));} while(0)
+#define SET_I2C_DATA_READ_TIME(n)         do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_DATA_READ_TIME_MASK, ((n)<<I2C_DATA_READ_TIME_SHIFT));} while(0)
+#define ENABLE_I2C_DATA_READ_ADJ          do{DRV_I2C_SetBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0)
+#define DISABLE_I2C_DATA_READ_ADJ         do{DRV_I2C_ClearBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0)
+
+#define START_I2C_TRANSACTION             do{DRV_I2C_WriteReg16(REG_I2C_START, 0x01);} while(0)
+
+// #define I2C_FIFO_FULL                     ((REG_I2C_FIFO_STAT>>1)&0x01)
+// #define I2C_FIFO_EMPTY                    (REG_I2C_FIFO_STAT & 0x01)
+
+#define SET_I2C_RX_FIFO_THRESH(n)         do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_RX_FIFO_THRESH_MASK, ((n)<< I2C_RX_FIFO_THRESH_SHIFT));} while(0)
+#define SET_I2C_TX_FIFO_THRESH(n)         do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_TX_FIFO_THRESH_MASK, ((n)<< I2C_TX_FIFO_THRESH_SHIFT));} while(0)
+
+#define CLEAR_I2C_FIFO                    do{DRV_I2C_WriteReg16(REG_I2C_FIFO_ADDR_CLR, 0x01);} while(0)
+
+#define SET_I2C_SCL_NORMAL_MODE           do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0)
+#define SET_I2C_SCL_WIRED_AND_MODE        do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0)
+#define SET_I2C_SDA_NORMAL_MODE           do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0)
+#define SET_I2C_SDA_WIRED_AND_MODE        do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0)
+#define ENABLE_I2C_BUS_DETECT             do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0)
+#define DISABLE_I2C_BUS_DETECT            do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0)
+
+#define ENABLE_I2C_CLOCK_SYNC             do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0)
+#define ENABLE_DATA_ARBITION              do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0)
+#define ENABLE_I2C_BUS_BUSY_DET           do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0)
+#define DISABLE_I2C_CLOCK_SYNC            do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0)
+#define DISABLE_DATA_ARBITION             do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0)
+#define DISABLE_I2C_BUS_BUSY_DET          do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0)
+
+#define SET_I2C_HIGH_SPEED_MODE_800KB     do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0703);} while(0)
+#define SET_I2C_HIGH_SPEED_MODE_1000KB    do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0503);} while(0)
+
+#define SET_I2C_FAST_MODE                 do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0)
+#define SET_I2C_HS_MODE                   do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0)
+#define ENABLE_I2C_NAKERR_DET             do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0)
+#define DISABLE_I2C_NAKERR_DET            do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0)
+#define SET_I2C_HS_MASTER_CODE(n)         do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_MASTER_CODE_MASK, ((n)<<I2C_HS_MASTER_CODE_SHIFT));} while(0)
+
+#define SET_I2C_HS_STEP_CNT_DIV(n)        do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_STEP_CNT_DIV_MASK, ((n)<<I2C_HS_STEP_CNT_DIV_SHIFT));} while(0)
+#define SET_I2C_HS_SAMPLE_CNT_DIV(n)      do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_HS_SAMPLE_CNT_DIV_SHIFT));} while(0)
+
+#define RESET_I2C                         do{DRV_I2C_WriteReg16(REG_I2C_SOFTRESET, 0x01);} while(0)
+#define SET_I2C_SW_MODE					  do{DRV_I2C_WriteReg16(REG_SW_I2C_EN, 0x1);}while(0)
+#define SET_I2C_HW_MODE					  do{DRV_I2C_WriteReg16(REG_SW_I2C_EN, 0x0);}while(0)
+
+
+/****** SW definitions******/
+#define I2C_READ_BIT            0x01
+#define I2C_WRITE_BIT           0x00
+
+#define I2C_TRANSAC_COMPLETE    0x01
+#define I2C_TRANSAC_ACK_ERR     0x02
+#define I2C_HS_NACK_ERR         0x04
+#define I2C_TIMEOUT         	0x10
+
+//extern kal_bool dcl_i2c_init_done_flag;
+//extern i2c_handle_struct i2c_handle[DCL_I2C_NUM_OF_OWNER];
+
+void dcl_i2c_init(void);
+void dcl_i2c_deinit(void);
+extern void dcl_i2c_hw_cfg (DCL_I2C_OWNER owner, I2C_TRANSACTION_TYPE type, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len, kal_uint32 transfer_num);
+void dcl_i2c_set_transaction_speed(DCL_I2C_OWNER owner,I2C_TRANSACTION_MODE mode,kal_uint16* Fast_Mode_Speed,kal_uint16* HS_Mode_Speed);
+extern kal_uint32 dcl_i2c_wait_transaction_complete_and_lock(DCL_I2C_OWNER owner);
+void dcl_i2c_wait_transaction_complete(kal_uint32 savedMask);
+
+#endif // #ifndef __I2C_H__
+
diff --git a/mcu/driver/devdrv/i2c/inc/drv_i2c_trace.h b/mcu/driver/devdrv/i2c/inc/drv_i2c_trace.h
new file mode 100644
index 0000000..6fbd4f7
--- /dev/null
+++ b/mcu/driver/devdrv/i2c/inc/drv_i2c_trace.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   i2c_trace.h
+ *
+ *
+ * Description:
+ * ------------
+ *   I2C Driver tracer
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+#if !defined(__I2C_TRACE_H__)
+#define __I2C_TRACE_H__
+#if !defined(GEN_FOR_PC)
+#include "kal_public_defs.h"
+#endif
+#include "dhl_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined (__DHL_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif
+#endif
+#if !(defined(GEN_FOR_PC)||defined(__MAUI_BASIC__))
+#include"drv_i2c_trace_mod_i2c_utmd.h"
+#endif
+#endif  /* !__IDC_TRACE_H__ */
diff --git a/mcu/driver/devdrv/i2c/inc/drv_i2c_trace_mod_i2c_utmd.json b/mcu/driver/devdrv/i2c/inc/drv_i2c_trace_mod_i2c_utmd.json
new file mode 100644
index 0000000..8bdbfa0
--- /dev/null
+++ b/mcu/driver/devdrv/i2c/inc/drv_i2c_trace_mod_i2c_utmd.json
@@ -0,0 +1,138 @@
+{
+  "endGen": "-",
+  "legacyParameters": {},
+  "module": "MOD_I2C",
+  "startGen": "Legacy",
+  "traceClassDefs": [
+    {
+      "TRACE_INFO": {
+        "debugLevel": "Low",
+        "tag": [
+          "Baseline",
+          "TRACE_INFO"
+        ],
+        "traceType": "Public"
+      }
+    },
+    {
+      "TRACE_WARNING": {
+        "debugLevel": "Medium",
+        "tag": [
+          "Baseline",
+          "TRACE_WARNING"
+        ],
+        "traceType": "Public"
+      }
+    },
+    {
+      "TRACE_ERROR": {
+        "debugLevel": "High",
+        "tag": [
+          "Baseline",
+          "TRACE_ERROR"
+        ],
+        "traceType": "Public"
+      }
+    },
+    {
+      "TRACE_FUNC": {
+        "debugLevel": "Low",
+        "tag": [
+          "Baseline",
+          "TRACE_FUNC"
+        ],
+        "traceType": "Public"
+      }
+    },
+    {
+      "TRACE_STATE": {
+        "debugLevel": "Low",
+        "tag": [
+          "Baseline",
+          "TRACE_STATE"
+        ],
+        "traceType": "Public"
+      }
+    }
+  ],
+  "traceDefs": [
+    {
+      "I2C_INVALID_HANDLE_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,invalid I2C handle:%x",
+        "traceClass": "TRACE_ERROR"
+      }
+    },
+    {
+      "I2C_NOT_OPENED_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,I2C status is not opened",
+        "traceClass": "TRACE_ERROR"
+      }
+    },
+    {
+      "I2C_INVALID_OWNER_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,I2C owner ID [%x] is invalid",
+        "traceClass": "TRACE_ERROR"
+      }
+    },
+    {
+      "I2C_CONFIG_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,owner id=%x,slave_address=%x,transaction_mode=%x,Fast_Mode_Speed=%x,HS_Mode_Speed=%x",
+        "traceClass": "TRACE_INFO"
+      }
+    },
+    {
+      "I2C_CMD_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] DclSI2C_Control cmd: %x",
+        "traceClass": "TRACE_INFO"
+      }
+    },
+    {
+      "I2C_TRANSACTION_TIMETOUT_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] I2C driver wait transaction complete timeout!",
+        "traceClass": "TRACE_ERROR"
+      }
+    },
+    {
+      "I2C_TRANSACTION_COMPLETE_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] I2C driver transaction complete !",
+        "traceClass": "TRACE_STATE"
+      }
+    },
+    {
+      "I2C_TRANSACTION_ERROR_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] I2C driver transaction error: sta=%x !",
+        "traceClass": "TRACE_ERROR"
+      }
+    },
+    {
+      "I2C_INIT_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,i2c init done!",
+        "traceClass": "TRACE_STATE"
+      }
+    },
+    {
+      "I2C_DEINIT_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,i2c de-init done!",
+        "traceClass": "TRACE_STATE"
+      }
+    },
+    {
+      "I2C_CLOSE_MSG": {
+        "apiType": "index",
+        "format": "[DCL_I2C] %s,i2c close done!",
+        "traceClass": "TRACE_STATE"
+      }
+    }
+  ],
+  "traceFamily": "PS"
+}
\ No newline at end of file
diff --git a/mcu/driver/devdrv/i2c/src/dcl_i2c.c b/mcu/driver/devdrv/i2c/src/dcl_i2c.c
new file mode 100644
index 0000000..5d50928
--- /dev/null
+++ b/mcu/driver/devdrv/i2c/src/dcl_i2c.c
@@ -0,0 +1,505 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *    dcl_i2c.c
+ *
+ * Project:
+ * --------
+ *   MOLYA_Software
+ *
+ * Description:
+ * ------------
+ *   This Module defines DCL (Driver Common Layer) of the I2C driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "drv_features.h"
+#include "drv_comm.h"
+
+#include "dcl.h"
+
+#include "kal_general_types.h"
+#include "dcl_i2c_owner.h"
+#include "drv_i2c.h"
+#include "kal_public_api.h"
+
+#if !defined(DRV_I2C_OFF)
+
+// Global variable for DCL I2C API usage
+#define DCL_I2C_DEV_MAGIC_NUM		(0x50000000)
+#define MAX_DCL_I2C_HANDLE			DCL_I2C_NUM_OF_OWNER
+
+extern i2c_handle_struct i2c_handle[DCL_I2C_NUM_OF_OWNER];
+extern i2c_status_struct dcl_i2c_status;
+
+DCL_STATUS _ConvertDclReturnStatus(I2C_TRANSACTION_RESULT result)
+{
+    if (result == I2C_TRANSACTION_COMPLETE)
+    {
+        return STATUS_OK;
+    }
+    else
+    {
+        if (result == I2C_TRANSACTION_IS_BUSY)
+            return STATUS_DEVICE_IS_BUSY;
+        else if (result == I2C_TRANSACTION_ACKERR)
+            return STATUS_ACKERR;
+        else if (result == I2C_TRANSACTION_HS_NACKERR)
+            return STATUS_HS_NACKERR;
+        else
+            return STATUS_FAIL;
+    }
+
+    //return STATUS_OK;
+}
+
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_Initialize
+*
+* DESCRIPTION
+*  This function is to initialize S/W I2C module
+*
+* PARAMETERS
+*  None
+*
+* RETURNS
+*  STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_Initialize(void)
+{
+	//*/ DclSI2C_Initialize() should be called only once, when system init /*//
+	dcl_i2c_init();
+
+	return STATUS_OK;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_Open
+*
+* DESCRIPTION
+*  This function is to open the I2C module and return a handle
+*
+* PARAMETERS
+*  dev: only valid for DCL_I2C
+*  flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+*  DCL_HANDLE_INVALID: Open failed
+*  Other value: A valid handle
+*
+*************************************************************************/
+
+DCL_HANDLE DclSI2C_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+	kal_uint32 i2c_owner = flags & 0xFF;  //*/ DCL_I2C_OWNER should be transfered through the low 8bit of flags /*//
+	
+	if (i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed)  //*/ when system init or called DclSI2C_Close(), config->Fast_Mode_Speed == 0 /*// 
+	{
+		return DCL_HANDLE_OCCUPIED;		//*/ This Handle has been opened /*//
+	}
+			
+	//*/ Tricky! when != 0, indicate that the owner has owned a handle, to avoid one owner call DclSI2C_Open() more than once. /*//
+	i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed = 1;
+		
+	return (DCL_I2C_DEV_MAGIC_NUM | i2c_owner);
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_ReadData
+*
+* DESCRIPTION
+*  This function is not supported for the I2C module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_WriteData
+*
+* DESCRIPTION
+*  This function is not supported for the I2C module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options){
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_Configure
+*
+* DESCRIPTION
+*  This function is to configure the I2C module.
+*
+* PARAMETERS
+*  handle: the returned handle value of DclSI2C_Open
+*  configure: a structure which include the I2C configuration.  
+*
+* RETURNS
+*  STATUS_OK: Successfully configure I2C module.
+*  STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
+*  STATUS_NOT_OPENED: The module has not been opened.
+*  STATUS_INVALID_CONFIGURATION: The configuration is invalid.
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure){
+
+	// Check magic number
+	if ((handle & DCL_I2C_DEV_MAGIC_NUM) != DCL_I2C_DEV_MAGIC_NUM)
+	{
+		MD_TRC(I2C_INVALID_HANDLE_MSG,__FUNCTION__, handle);
+		return STATUS_INVALID_DCL_HANDLE;
+	}
+
+	{
+		I2C_CONFIG_T* prI2CConfig = (I2C_CONFIG_T*) configure;
+		DCL_I2C_OWNER i2c_owner = prI2CConfig->eOwner;
+		
+		//*/ check if the handle is opened /*//
+		if (i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed == 0)
+		{
+			MD_TRC(I2C_NOT_OPENED_MSG,__FUNCTION__);
+			return STATUS_NOT_OPENED;
+		}
+		// Check owner
+		if (i2c_owner >= (kal_uint8)DCL_I2C_NUM_OF_OWNER )
+		{
+			MD_TRC(I2C_INVALID_OWNER_MSG,__FUNCTION__,i2c_owner);
+			return STATUS_INVALID_CONFIGURATION;
+		}
+
+		i2c_handle[i2c_owner].i2c_config.get_handle_wait = (kal_bool)prI2CConfig->fgGetHandleWait;
+
+ 		i2c_handle[i2c_owner].i2c_config.slave_address = prI2CConfig->u1SlaveAddress;
+ 		i2c_handle[i2c_owner].i2c_config.delay_len = prI2CConfig->u1DelayLen;
+ 		
+		i2c_handle[i2c_owner].i2c_config.transaction_mode = (I2C_TRANSACTION_MODE)prI2CConfig->eTransactionMode;
+		
+		i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed = prI2CConfig->u4FastModeSpeed;
+		i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed = prI2CConfig->u4HSModeSpeed;
+		
+        MD_TRC(I2C_CONFIG_MSG,__FUNCTION__,i2c_owner,i2c_handle[i2c_owner].i2c_config.slave_address,i2c_handle[i2c_owner].i2c_config.transaction_mode,i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed,i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed);
+        dcl_i2c_set_transaction_speed(i2c_owner,i2c_handle[i2c_owner].i2c_config.transaction_mode,&(i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed),&(i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed));          
+
+        prI2CConfig->u4FastModeSpeed = i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed;
+        prI2CConfig->u4HSModeSpeed = i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed;
+	}
+
+	return STATUS_OK;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_RegisterCallback
+*
+* DESCRIPTION
+*  This function is to set callback function for the I2C module.
+*
+* PARAMETERS
+*  handle: the returned handle value of DclSI2C_Open
+*  event: Supported events:
+*  callback: the callback function for registered events
+*
+* RETURNS
+*  STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback){
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_Control
+*
+* DESCRIPTION
+*  This function is to send command to control the I2C module.
+*
+* PARAMETERS
+*  handle: The handle value returned from DclSI2C_Open
+*  cmd: A control command for I2C module
+*          1. I2C_CMD_GET_TRANSACTION_MODE: to get transaction mode
+*          2. I2C_CMD_SET_TRANSACTION_SPEED: to set transaction speed
+*          3. I2C_CMD_SINGLE_WRITE: to perform a single WRITE
+*          4. I2C_CMD_SINGLE_READ: to perform a single READ
+*          5. I2C_CMD_CONT_WRITE: to perform a continuous WRITE
+*          6. I2C_CMD_CONT_READ: to  perform a continuous READ
+*          7. I2C_CMD_WRITE_AND_READ: to perform a specific sequence "WRITE then READ"
+*          8. I2C_CMD_ENABLE_DMA: to enable/disable DMA
+*  data: The data of the control command
+*          1. I2C_CMD_GET_TRANSACTION_MODE: pointer to a I2C_CTRL_GET_TRANSACTION_MODE_T structure
+*          2. I2C_CMD_SET_TRANSACTION_SPEED: pointer to a I2C_CTRL_SET_TRANSACTION_SPEED_T structure
+*          3. I2C_CMD_SINGLE_WRITE: pointer to a I2C_CTRL_SINGLE_WRITE_T structure
+*          4. I2C_CMD_SINGLE_READ: pointer to a I2C_CTRL_SINGLE_READ_T structure
+*          5. I2C_CMD_CONT_WRITE: pointer to a I2C_CTRL_CONT_WRITE_T structure
+*          6. I2C_CMD_CONT_READ: pointer to a I2C_CTRL_CONT_READ_T structure
+*          7. I2C_CMD_WRITE_AND_READ: pointer to a I2C_CTRL_WRITE_AND_READE_T structure
+*          8. I2C_CMD_ENABLE_DMA: pointer to a I2C_CTRL_ENABLE_DMA_T structure
+*
+* RETURNS
+*  STATUS_OK: command is executed successfully.
+*  STATUS_FAIL: command is failed.
+*  STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+	DCL_I2C_OWNER i2c_owner;  
+	
+	// Check magic number
+	if ((handle & DCL_I2C_DEV_MAGIC_NUM) != DCL_I2C_DEV_MAGIC_NUM)
+	{
+		MD_TRC(I2C_INVALID_HANDLE_MSG,__FUNCTION__, handle);
+		return STATUS_INVALID_DCL_HANDLE;
+	}
+			
+	//*/ check if the handle is opened /*//
+	if ((i2c_handle[(kal_uint8)(handle & 0xFF)].i2c_config.Fast_Mode_Speed) == 0)
+	{
+		MD_TRC(I2C_NOT_OPENED_MSG,__FUNCTION__);
+		return STATUS_NOT_OPENED;
+	}
+	
+	i2c_owner = (DCL_I2C_OWNER)(handle & 0xFF);
+	MD_TRC(I2C_CMD_MSG,cmd);
+	switch (cmd)
+	{
+		case I2C_CMD_GET_TRANSACTION_MODE:
+		{
+			I2C_CTRL_GET_TRANSACTION_MODE_T *prGetTransactionMode;
+			prGetTransactionMode = &(data->rGetTransactionMode);
+			
+			prGetTransactionMode->eTransactionMode = (DCL_I2C_TRANSACTION_MODE)i2c_handle[i2c_owner].i2c_config.transaction_mode;
+			return STATUS_OK;
+		}
+		//break;
+		case I2C_CMD_SET_TRANSACTION_SPEED:
+		{
+			I2C_CTRL_SET_TRANSACTION_SPEED_T *prSetTransactionSpeed;
+			prSetTransactionSpeed = &(data->rSetTransactionSpeed);
+
+            i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed = prSetTransactionSpeed->u4FastModeSpeed;
+            i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed = prSetTransactionSpeed->u4HSModeSpeed;
+            
+            dcl_i2c_set_transaction_speed(i2c_owner,i2c_handle[i2c_owner].i2c_config.transaction_mode,&(i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed),&(i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed));          
+            
+            prSetTransactionSpeed->u4FastModeSpeed = i2c_handle[i2c_owner].i2c_config.Fast_Mode_Speed;
+            prSetTransactionSpeed->u4HSModeSpeed = i2c_handle[i2c_owner].i2c_config.HS_Mode_Speed;
+
+			return STATUS_OK;
+		}
+		//break;
+		case I2C_CMD_SINGLE_WRITE:
+        case I2C_CMD_SINGLE_READ:
+        case I2C_CMD_CONT_WRITE:
+        case I2C_CMD_CONT_READ:
+        case I2C_CMD_WRITE_AND_READ:
+		{
+            kal_uint32 savedMask;
+			I2C_CTRL_SINGLE_WRITE_T *prSingleWrite;
+			I2C_CTRL_SINGLE_READ_T *prSingleRead;
+			I2C_CTRL_CONT_WRITE_T *prContWrite; 
+            I2C_CTRL_CONT_READ_T *prContRead;
+			I2C_CTRL_WRITE_AND_READE_T *prWriteAndRead;
+			
+            savedMask=dcl_i2c_wait_transaction_complete_and_lock(i2c_owner);
+            if (dcl_i2c_status.owner!=i2c_owner)
+            {
+                return STATUS_DEVICE_IS_BUSY;
+            }
+			switch(cmd){
+				case I2C_CMD_SINGLE_WRITE:
+					prSingleWrite= &(data->rSingleWrite);
+					dcl_i2c_hw_cfg (i2c_owner, I2C_TRANSACTION_WRITE, prSingleWrite->pu1Data, prSingleWrite->u4DataLen, NULL, 0, 1); 
+					break;
+				case I2C_CMD_SINGLE_READ: 
+					prSingleRead= &(data->rSingleRead);
+					dcl_i2c_hw_cfg (i2c_owner, I2C_TRANSACTION_READ, NULL, 0, prSingleRead->pu1Data, prSingleRead->u4DataLen, 1);
+					break;					
+				case I2C_CMD_CONT_WRITE:
+					
+					prContWrite	= &(data->rContWrite);
+					dcl_i2c_hw_cfg (i2c_owner, I2C_TRANSACTION_CONT_WRITE, prContWrite->pu1Data, prContWrite->u4DataLen, NULL, 0, prContWrite->u4TransferNum);
+					break;
+				case I2C_CMD_CONT_READ:
+					 
+					prContRead= &(data->rContRead);
+					dcl_i2c_hw_cfg (i2c_owner, I2C_TRANSACTION_CONT_READ, NULL, 0, prContRead->pu1Data, prContRead->u4DataLen, prContRead->u4TransferNum);
+					break;
+				case I2C_CMD_WRITE_AND_READ:
+					
+					prWriteAndRead= &(data->rWriteAndRead);
+					dcl_i2c_hw_cfg (i2c_owner, I2C_TRANSACTION_WRITE_AND_READ, prWriteAndRead->pu1OutData, prWriteAndRead->u4OutDataLen, prWriteAndRead->pu1InData, prWriteAndRead->u4InDataLen, 2);  
+					break;
+				default:
+					break;
+			}
+            dcl_i2c_wait_transaction_complete(savedMask);
+            return _ConvertDclReturnStatus(i2c_handle[i2c_owner].transaction_result);			
+		}
+		//break;
+		case I2C_CMD_SET_SLAVE_ADDRESS:
+		{
+			I2C_CTRL_SET_SLAVE_ADDRESS_T *prSetSlaveAddress;
+			prSetSlaveAddress = &(data->rSetSlaveAddress);
+
+            i2c_handle[i2c_owner].i2c_config.slave_address=prSetSlaveAddress->u1SlaveAddress;
+			return STATUS_OK;
+		}
+	//	break;
+		default:
+			return STATUS_INVALID_CMD;
+	//	break;
+	}
+	return STATUS_FAIL;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSI2C_Close
+*
+* DESCRIPTION
+*  This function is to close the I2C module.
+*
+* PARAMETERS
+*  handle: the returned handle value of DclSI2C_Open
+*
+* RETURNS
+*  STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclSI2C_Close(DCL_HANDLE handle)
+{
+	i2c_config_struct* config = &i2c_handle[(kal_uint8)(handle & 0xFF)].i2c_config;
+
+	// Check magic number
+	if ((handle & DCL_I2C_DEV_MAGIC_NUM) != DCL_I2C_DEV_MAGIC_NUM)
+	{
+		return STATUS_INVALID_DCL_HANDLE;
+	}
+
+	MD_TRC(I2C_CLOSE_MSG,__FUNCTION__);	
+	//*/ check if the handle is opened, if i2c handle is opened, the related Fast_Mode_Speed not equal to zero /*//
+	if (config->Fast_Mode_Speed == 0)
+	{
+		return STATUS_NOT_OPENED;
+	}
+	dcl_i2c_deinit();
+	config->Fast_Mode_Speed = 0;
+
+	return STATUS_OK;
+}
+
+#else //#if (!defined(DRV_I2C_OFF) && defined(DCL_I2C_INTERFACE))
+
+DCL_STATUS DclSI2C_Initialize(void)
+{
+    return STATUS_FAIL;
+}
+
+DCL_HANDLE DclSI2C_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+    return 0;
+}
+DCL_STATUS DclSI2C_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSI2C_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSI2C_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+    return STATUS_FAIL;
+}
+
+DCL_STATUS DclSI2C_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSI2C_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+    return STATUS_FAIL;
+}
+DCL_STATUS DclSI2C_Close(DCL_HANDLE handle)
+{
+    return STATUS_FAIL;
+}
+#endif
+
diff --git a/mcu/driver/devdrv/i2c/src/drv_i2c.c b/mcu/driver/devdrv/i2c/src/drv_i2c.c
new file mode 100644
index 0000000..889cd1d
--- /dev/null
+++ b/mcu/driver/devdrv/i2c/src/drv_i2c.c
@@ -0,0 +1,438 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   drv_i2c.c
+ *
+ *
+ * Description:
+ * ------------
+ *   I2C Driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+#include "drv_comm.h"
+#include "reg_base.h"
+#include "drv_i2c.h"    //*/ the new sccb_v2.h should be named i2c.h /*//
+#include "drvpdn.h"
+
+#include "dcl_i2c_owner.h"
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "drvpdn_inline.h"
+#include <ex_item.h>
+#include <ex_public.h>
+
+#if (!defined(DRV_I2C_OFF))
+#if defined(__MD95__)
+#define I2C_POWER_OFF()	do{PDN_SET(PDN_I2C_BCLK);}while(0)  /* Power off I2C */
+#define I2C_POWER_ON()  do{PDN_CLR(PDN_I2C_BCLK);}while(0)  /* Power on I2C */	
+#else
+#define I2C_POWER_OFF()	
+#define I2C_POWER_ON()
+#endif
+/// I2C internal global variables
+i2c_handle_struct i2c_handle[DCL_I2C_NUM_OF_OWNER];
+i2c_status_struct dcl_i2c_status;
+kal_bool i2c_lock_status = KAL_FALSE;
+kal_spinlockid i2c_lock_id = 0;
+
+
+//*/ abstract the HW register config API /*//
+//called in i2c_write -> dcl_i2c_hw_cfg (owner, I2C_TRANSACTION_WRITE, para, datalen, NULL, 0, 1);
+//called in i2c_read -> dcl_i2c_hw_cfg (owner, I2C_TRANSACTION_READ, NULL, 0, para, datalen, 1);
+//called in i2c_cont_write -> dcl_i2c_hw_cfg (owner, I2C_TRANSACTION_CONT_WRITE, para, datalen_in_transfer, NULL, 0, transfer_num);
+//called in i2c_cont_read -> dcl_i2c_hw_cfg (owner, I2C_TRANSACTION_CONT_READ, NULL, 0, para, datalen_in_transfer, transfer_num);
+//called in i2c_write_and_read -> dcl_i2c_hw_cfg (owner, I2C_TRANSACTION_WRITE_AND_READ, write_buffer, write_len, read_buffer, read_len, 2);
+void dcl_i2c_hw_cfg (DCL_I2C_OWNER owner, I2C_TRANSACTION_TYPE type, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len, kal_uint32 transfer_num)
+{ 
+	i2c_handle_struct* handle=&i2c_handle[owner];
+	i2c_config_struct* config=&handle->i2c_config;
+	kal_uint32 count_write, count_read, i;
+
+    if (read_len>DRV_I2C_FIFO_DEPTH || write_len>DRV_I2C_FIFO_DEPTH) //if u want a transcation with len>8, please enable DMA.
+    {
+        ASSERT(0);
+    }
+	count_write = write_len*transfer_num;
+	count_read = read_len*transfer_num;
+	
+	CLEAR_I2C_FIFO;
+	CLEAR_I2C_STA;
+	DISABLE_I2C_INT;
+	
+	SET_I2C_STEP_CNT_DIV(handle->fs_step_cnt_div);
+	SET_I2C_SAMPLE_CNT_DIV(handle->fs_sample_cnt_div);
+	
+	SET_I2C_TRANSACTION_LENGTH(transfer_num);
+	
+	if (handle->i2c_config.transaction_mode == I2C_TRANSACTION_FAST_MODE)
+	{
+		SET_I2C_FAST_MODE;
+		SET_I2C_ST_BETWEEN_TRANSFER;
+		if (config->delay_len>0)
+		{
+			SET_I2C_DELAY_LENGTH(config->delay_len-1);
+		}
+		if ((config->delay_len == 0)&&((type == I2C_TRANSACTION_CONT_WRITE)||(type == I2C_TRANSACTION_CONT_READ)))
+		{
+			SET_I2C_RS_BETWEEN_TRANSFER;
+		}
+	}
+	else if (handle->i2c_config.transaction_mode == I2C_TRANSACTION_HIGH_SPEED_MODE)
+	{
+		SET_I2C_HS_STEP_CNT_DIV(handle->hs_step_cnt_div);
+		SET_I2C_HS_SAMPLE_CNT_DIV(handle->hs_sample_cnt_div);
+		SET_I2C_HS_MODE;
+		SET_I2C_RS_BETWEEN_TRANSFER;
+	}
+
+	DISABLE_I2C_DIR_CHANGE;	
+    DISABLE_I2C_DMA_TRANSFER;
+
+	if ((type == I2C_TRANSACTION_WRITE)||(type == I2C_TRANSACTION_CONT_WRITE))
+	{
+		SET_I2C_SLAVE_ADDRESS(config->slave_address,I2C_WRITE_BIT);
+		SET_I2C_TRANSFER_LENGTH(write_len);
+        dcl_i2c_status.number_of_read=0;
+
+		for (i=0;i<count_write;i++) 
+		{
+			DRV_I2C_WriteReg16(REG_I2C_DATA_PORT, *(write_buffer+i));
+		} 
+	}
+	else if ((type == I2C_TRANSACTION_READ)||(type == I2C_TRANSACTION_CONT_READ))
+	{
+		SET_I2C_SLAVE_ADDRESS(config->slave_address,I2C_READ_BIT);
+		SET_I2C_TRANSFER_LENGTH(read_len);
+		dcl_i2c_status.number_of_read = count_read;	
+        dcl_i2c_status.read_buffer=read_buffer;
+	}
+	else if (type == I2C_TRANSACTION_WRITE_AND_READ)
+	{	
+		SET_I2C_SLAVE_ADDRESS(config->slave_address,I2C_WRITE_BIT);
+		SET_I2C_TRANSFER_LENGTH(write_len);
+		SET_I2C_AUX_TRANSFER_LENGTH(read_len);
+		ENABLE_I2C_DIR_CHANGE;
+		SET_I2C_RS_BETWEEN_TRANSFER;
+
+		dcl_i2c_status.number_of_read = read_len;
+        dcl_i2c_status.read_buffer=read_buffer;
+		for (i=0;i<write_len;i++)
+		{
+			DRV_I2C_WriteReg16(REG_I2C_DATA_PORT, (*(write_buffer+i)));
+		}  
+	}
+	START_I2C_TRANSACTION;	
+}
+
+
+void _dcl_i2c_status_handler(kal_uint32 sta)
+{
+	kal_uint32 i;
+	kal_uint8* read_buffer=dcl_i2c_status.read_buffer;
+    kal_uint32 number_of_read=dcl_i2c_status.number_of_read;
+	i2c_handle_struct* handle=&i2c_handle[dcl_i2c_status.owner];
+
+	if (sta == I2C_TRANSAC_COMPLETE) //This transaction is done now
+	{
+		for (i=0;i<number_of_read;i++)
+		{
+			read_buffer[i]=(DRV_I2C_ReadReg16(REG_I2C_DATA_PORT) & 0xff); //copy the read data to the previous transcation owner
+		}
+		handle->transaction_result = I2C_TRANSACTION_COMPLETE;
+	}
+	else
+	{
+		if (sta & I2C_TRANSAC_ACK_ERR)
+			handle->transaction_result = I2C_TRANSACTION_ACKERR;
+		else if (sta & I2C_HS_NACK_ERR)
+			handle->transaction_result = I2C_TRANSACTION_HS_NACKERR;
+		else //if got this, check register INTR_STAT to debug
+			handle->transaction_result = I2C_TRANSACTION_FAIL;
+	}
+	dcl_i2c_status.state=I2C_READY_STATE;
+}
+
+void _dcl_i2c_lisr(kal_uint32 vector)
+{
+	kal_uint32 savedMask;
+	kal_uint32 sta;
+	//test lisr executive time
+	//kal_uint32 start_qbit,end_qbit;//
+
+ 	//start_qbit = HW_TDMA_GET_TQCNT();//
+ 	
+	savedMask = SaveAndSetIRQMask();
+
+	sta = DRV_I2C_ReadReg16(REG_I2C_INT_STA); //sta=REG_I2C_INT_STA;
+
+	{
+        _dcl_i2c_status_handler(sta);
+	}
+ 	
+	RestoreIRQMask(savedMask);
+	//end_qbit = HW_TDMA_GET_TQCNT();//
+}
+
+
+void dcl_i2c_init(void)
+{
+    if(dcl_i2c_status.state != I2C_IDLE_STATE)
+	{
+		return;
+	}
+        
+	dcl_i2c_status.state=I2C_READY_STATE;
+	I2C_POWER_ON();
+
+	SET_I2C_HW_MODE;
+	ENABLE_I2C_ACK_ERR_DET; //Always enable ack error detection
+	ENABLE_I2C_NAKERR_DET;  //Always enable nack error detection
+	
+	// create mutex
+	if(i2c_lock_status == KAL_FALSE && !INT_QueryExceptionStatus())
+	{
+		i2c_lock_id = kal_create_spinlock("DRV_I2C");
+		i2c_lock_status = KAL_TRUE;
+	}
+	MD_TRC(I2C_INIT_MSG,__FUNCTION__);
+}
+
+void dcl_i2c_deinit(void)
+{
+	RESET_I2C;
+	kal_mem_set(&dcl_i2c_status,0, sizeof(i2c_status_struct));
+	MD_TRC(I2C_DEINIT_MSG,__FUNCTION__);
+	I2C_POWER_OFF();
+}
+
+
+//----------------------------I2C internal arbiteration------------------------------
+//--When return from this function, I bit is turned off!!--
+kal_uint32 dcl_i2c_wait_transaction_complete_and_lock(DCL_I2C_OWNER owner)
+{
+	if (!(kal_if_lisr()))
+	{
+		while(1)
+		{
+			if (dcl_i2c_status.state==I2C_READY_STATE)
+			{
+					kal_take_spinlock(i2c_lock_id, KAL_INFINITE_WAIT);
+					dcl_i2c_status.state=I2C_BUSY_STATE; //Lock it
+					dcl_i2c_status.owner=owner;
+					kal_give_spinlock(i2c_lock_id);
+					return 0;//will restore it at:  dcl_i2c_wait_transaction_complete
+			}
+			else if (i2c_handle[owner].i2c_config.get_handle_wait==KAL_FALSE)
+			{
+				return 0;
+			}
+			
+		}//end of while
+	}
+	else
+	{
+		if (dcl_i2c_status.state!=I2C_READY_STATE)
+		{
+			ASSERT(0);
+		}
+
+		dcl_i2c_status.state=I2C_BUSY_STATE; //Lock it
+		dcl_i2c_status.owner=owner;
+	}
+
+	return 0;
+}
+
+
+
+void dcl_i2c_wait_transaction_complete(kal_uint32 savedMask)
+{
+	kal_uint32 sta=0,timer=0;
+	kal_uint32 i=0;
+	kal_uint8* read_buffer=dcl_i2c_status.read_buffer;
+    kal_uint32 number_of_read=dcl_i2c_status.number_of_read;
+	i2c_handle_struct* handle=&i2c_handle[dcl_i2c_status.owner];
+
+	timer = 10000;
+	do
+	{
+		sta = DRV_I2C_ReadReg16(REG_I2C_INT_STA); 
+		timer--;
+	} while((!(sta & I2C_TRANSAC_COMPLETE)) && (timer!=0));
+
+	if(timer == 0){
+		MD_TRC(I2C_TRANSACTION_TIMETOUT_MSG,);
+		handle->transaction_result = I2C_TRANSACTION_FAIL;
+		return;
+	}
+
+	if (sta == I2C_TRANSAC_COMPLETE) //This transaction is done now
+	{
+		for (i=0;i<number_of_read;i++)
+		{
+			read_buffer[i]=(DRV_I2C_ReadReg16(REG_I2C_DATA_PORT) & 0xff); //copy the read data to the previous transcation owner
+		}
+		handle->transaction_result = I2C_TRANSACTION_COMPLETE;
+		MD_TRC(I2C_TRANSACTION_COMPLETE_MSG,);
+	}
+	else
+	{
+		MD_TRC(I2C_TRANSACTION_ERROR_MSG,sta);	
+		if (sta & I2C_TRANSAC_ACK_ERR)
+			handle->transaction_result = I2C_TRANSACTION_ACKERR;
+		else if (sta & I2C_HS_NACK_ERR)
+			handle->transaction_result = I2C_TRANSACTION_HS_NACKERR;
+		else //if got this, check register INTR_STAT to debug
+			handle->transaction_result = I2C_TRANSACTION_FAIL;
+		
+	}
+	kal_take_spinlock(i2c_lock_id, KAL_INFINITE_WAIT);
+	dcl_i2c_status.state=I2C_READY_STATE;
+	kal_give_spinlock(i2c_lock_id);
+
+}
+
+
+
+//----------------------------I2C Configuration APIs-------------------------------
+void dcl_i2c_set_transaction_speed(DCL_I2C_OWNER owner,I2C_TRANSACTION_MODE mode,kal_uint16* Fast_Mode_Speed,kal_uint16* HS_Mode_Speed)
+{
+	kal_uint32	step_cnt_div;
+	kal_uint32	sample_cnt_div;
+	kal_uint32	temp;
+
+	//Fast Mode Speed
+	for (sample_cnt_div=1;sample_cnt_div<=8;sample_cnt_div++)
+	{
+		if (NULL != Fast_Mode_Speed)
+		{
+			temp=((*Fast_Mode_Speed)*2*sample_cnt_div);	
+		}
+		else
+		{
+			temp = 1*2*sample_cnt_div;
+		}
+		step_cnt_div=(I2C_CLOCK_RATE+temp-1)/temp;	//cast the <1 part
+   
+		if (step_cnt_div<=64) 
+		{
+			break;
+		}
+	}
+	if (step_cnt_div>64 && sample_cnt_div>8)
+	{
+		step_cnt_div=64;
+		sample_cnt_div=8;
+	}
+
+
+    
+	if (NULL != Fast_Mode_Speed)
+	{
+        *Fast_Mode_Speed = I2C_CLOCK_RATE/2/sample_cnt_div/step_cnt_div; 
+        i2c_handle[owner].fs_sample_cnt_div=sample_cnt_div-1;
+        i2c_handle[owner].fs_step_cnt_div=step_cnt_div-1;
+        i2c_handle[owner].i2c_config.transaction_mode=I2C_TRANSACTION_FAST_MODE;
+ 
+	}
+  
+	//HS Mode Speed
+	if (mode==I2C_TRANSACTION_HIGH_SPEED_MODE) 
+	{ 
+		for (sample_cnt_div=1;sample_cnt_div<=8;sample_cnt_div++)
+		{
+			if (NULL != HS_Mode_Speed)
+			{
+				temp=((*HS_Mode_Speed)*2*sample_cnt_div);	
+			}
+			else
+			{
+				temp=(1*2*sample_cnt_div);	
+			}
+			step_cnt_div=(I2C_CLOCK_RATE+temp-1)/temp;
+			if (step_cnt_div<=8) 
+			{
+				break;
+			}
+		}
+		if (NULL != HS_Mode_Speed)
+		{
+			*HS_Mode_Speed=I2C_CLOCK_RATE/2/sample_cnt_div/step_cnt_div; 
+            i2c_handle[owner].hs_sample_cnt_div=sample_cnt_div-1;
+            i2c_handle[owner].hs_step_cnt_div=step_cnt_div-1;
+            i2c_handle[owner].i2c_config.transaction_mode=I2C_TRANSACTION_HIGH_SPEED_MODE;
+		}
+	}
+}
+
+
+#endif
+
+