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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/idc/inc/drv_idc.h b/mcu/driver/devdrv/idc/inc/drv_idc.h
new file mode 100644
index 0000000..628c0cc
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/drv_idc.h
@@ -0,0 +1,31 @@
+#ifndef __DRV_IDC_H__
+#define __DRV_IDC_H__
+
+#include "kal_general_types.h"
+
+void drv_sleep_notify(void);
+void drv_idc_set_ilm(kal_bool ilm_mode);
+
+typedef enum{
+
+EVENT_LTE =0,
+EVENT_NR,
+EVENT_COMMON,
+
+}EVENT_TYPE_ID;
+
+typedef enum{
+
+IDC_RAT_LTE =0,
+IDC_RAT_NR,
+
+}IDC_RAT_ID;
+
+typedef enum{
+
+IDC_L1_GPS =0,
+IDC_L5_GPS,
+
+}IDC_L1_L5_GPS_ID;
+
+#endif
diff --git a/mcu/driver/devdrv/idc/inc/idc_internal.h b/mcu/driver/devdrv/idc/inc/idc_internal.h
new file mode 100644
index 0000000..b09f1e7
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/idc_internal.h
@@ -0,0 +1,241 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idc_internal.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for IDC.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+#ifndef __IDC_INTERNAL_H__
+#define __IDC_INTERNAL_H__
+
+#include "dcl.h"
+
+#include "kal_general_types.h"
+#include "drv_comm.h"
+
+#include "dcl_idc.h"
+
+#define IDC_PM_NUM 5
+#define IDC_NEW_PM_IDX 4
+#define IDC_UART_TXFIFO_SIZE 128
+#define IDC_MAX_NUM_BYTE 9
+
+#if defined(__MD97__) || (defined(__MD97P__))
+#define IDC_MAX_EVENT_NUM 32
+
+//Petrus
+#define IDC_LTE_STA_EVENT_IDX 1
+#define IDC_LTE_MAX_EVENT_IDX 15
+#define IDC_NR_STA_EVENT_IDX 17
+#define IDC_NR_MAX_EVENT_IDX 31
+#define IDC_COMMON_STA_EVENT_IDX 16
+
+#if !defined(MT6297)
+#define IDC_SRAM_WRAP_IDX 0xC
+//#define IDC_PM_NUM 11 // 4+1+6
+#define IDC_NEW_PM_ERR_NUM 6
+#define IDC_NEW_PM_ERR_STA_IDX 5
+#define IDC_NEW_PM_ERR_STOP_IDX 10
+#define IDC_NEW_PM_ERR1_IDX 5
+#define IDC_NEW_PM_ERR2_IDX 8
+#define IDC_NEW_PM_ERR3_IDX 9
+#define IDC_NEW_PM_ERR4_IDX 10
+#define IDC_NEW_PM_ERR5_IDX 6
+#define IDC_NEW_PM_ERR6_IDX 7
+#define IDC_MAX_SRAM_SIZE 156
+#define IDC_MAX_SRAM_IDX 39
+#define IDC_UART_RXFIFO_SIZE 64
+#define IDC_MAX_CC_NUM 6
+#define IDC_MAX_REMAPPING_NUM 64
+#define IDC_MAX_CC_COMBINATION 4096
+#define IDC_NEW_PM_BNUM 7
+#else
+#define IDC_SRAM_WRAP_IDX 0x0
+//#define IDC_PM_NUM 8 // 4+1+3
+#define IDC_NEW_PM_ERR_NUM 3
+#define IDC_NEW_PM_ERR_STA_IDX 5
+#define IDC_NEW_PM_ERR_STOP_IDX 7
+#define IDC_NEW_PM_ERR1_IDX 5
+#define IDC_NEW_PM_ERR2_IDX 6
+#define IDC_NEW_PM_ERR3_IDX 7
+#define IDC_MAX_SRAM_SIZE 128
+#define IDC_MAX_SRAM_IDX 32
+#define IDC_UART_RXFIFO_SIZE 32
+#define IDC_MAX_CC_NUM 5
+#define IDC_MAX_REMAPPING_NUM 32
+#define IDC_MAX_CC_COMBINATION 1024
+#define IDC_NEW_PM_BNUM 4
+#endif
+
+#else
+#define IDC_MAX_EVENT_NUM 16
+#define IDC_MAX_SRAM_SIZE 78
+#endif
+
+
+void drv_idc_init(kal_bool is_sm);
+void drv_idc_init_uart(void);
+void drv_idc_init_m2c_bridge(void);
+void drv_idc_init_isr(void);
+void drv_idc_uart_activate(void);
+void drv_idc_get_support(IDC_SUPPORT_T *support);
+void drv_idc_conn_txrx_count(kal_bool is_start);
+void drv_idc_open(kal_uint32 mod_id);
+void drv_idc_close(void);
+void drv_idc_set_dcb_config(IDC_CTRL_DCB_CONFIG_T idc_config);
+void drv_idc_get_dcb_config(IDC_CTRL_DCB_CONFIG_T *DCB);
+void drv_idc_set_baudrate(kal_uint32 baudrate);
+void drv_idc_set_fifo_trigger(kal_uint8 rx_threshold);
+void drv_idc_set_pm_config(kal_uint8 pm_idx, kal_uint8 priority, kal_uint8 priority_bit_en, kal_uint8 pattern, kal_uint8 pattern_bit_en);
+void drv_idc_get_pm_config(kal_uint8 pm_idx, kal_uint8 *priority, kal_uint8 *priority_bit_en, kal_uint8 *pattern, kal_uint8 *pattern_bit_en);
+void drv_idc_send_event(IDC_EVENT_T event, kal_bool sleep_mode);
+kal_bool drv_idc_send_event_95(IDC_EVENT_T event, kal_bool sleep_mode);
+kal_bool drv_idc_send_event_97(IDC_EVENT_T event, kal_bool sleep_mode);
+void drv_idc_schedule_event(IDC_EVENT_T event);
+kal_bool drv_idc_schedule_event_95(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd);
+kal_bool drv_idc_schedule_event_97(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd);
+kal_bool drv_idc_schedule_gps_blank_event(kal_uint8 rat_status, kal_bool gps_mode, kal_uint32 frc_time);
+void drv_idc_schedule_update(kal_uint32 time);
+void drv_idc_schedule_update_95(kal_uint32 time);
+void drv_idc_schedule_update_97(kal_uint32 time);
+void drv_idc_stop_event(kal_uint32 bitmap);
+void drv_idc_stop_event_97(kal_uint32 bitmap);
+void drv_idc_purge(UART_buffer dir);
+void drv_idc_get_schedule_status(kal_uint32 schedule_status);
+void drv_idc_get_schedule_status_2(kal_uint32 schedule_status);
+kal_bool drv_idc_check_event_send_out(void);
+DCL_STATUS drv_idc_set_pin_config(IDC_PIN_MODE_T pin_mode);
+DCL_STATUS drv_idc_get_pin_config(IDC_PIN_MODE_T *pin_mode);
+void idc_uart_lisr(kal_uint32 vector);
+void idc_uart_hisr(void);
+void idc_pm_lisr(kal_uint32 vector);
+void idc_pm_hisr(void);
+void idc_send_rx_data_by_ilm(void);
+void idc_send_rx_data_by_ilm_95(void);
+void drv_idc_return_drop_cmd(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd);
+int drv_idc_register_pm_callback(kal_uint8 pm_idx, IDC_DRV_TO_EL1_CALLBACK func_ptr , kal_bool private_data) ;
+int drv_idc_register_pm_callback_95(kal_uint8 pm_idx, IDC_DRV_TO_EL1_CALLBACK func_ptr , void *private_data);
+int drv_idc_unregister_pm_callback(kal_uint8 pm_idx) ;
+void drv_idc_set_new_pm_config(kal_uint8 pattern0, kal_uint8 pattern1);
+void drv_idc_get_new_pm_config(kal_uint8 *pattern0, kal_uint8 *pattern1);
+void drv_idc_force_on_rf(kal_uint8 rf_path);
+void drv_idc_set_remapping_config(kal_uint8 remapping_table, kal_uint8 remapping_table_en);
+
+//__MD97__
+void idc_set_immediate_event(kal_uint32 event_idx, kal_uint8* buf, kal_uint32 byte_num, kal_uint32 start_sram_idx, kal_uint32 end_sram_idx);
+
+
+//Petrus
+void drv_idc_set_sram_wrap_idx(kal_uint32 start_idx);
+void drv_idc_schedule_update_n_return_rftx(kal_uint32 time, kal_uint8 *rf_path);
+kal_bool drv_idc_schedule_event_lte_nr(IDC_EVENT_T event, kal_uint8 event_type,IDC_CTRL_DROP_CMD_T *drop_cmd);
+void drv_idc_return_drop_cmd_lte_nr(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd, kal_uint8 event_type);
+void idc_auto_tx_lisr(kal_uint32 vector);
+void drv_idc_auto_tx_config(kal_uint8 tx_susp_quota, kal_uint8 reset_quota);
+void drv_idc_auto_tx_en(kal_uint8 auto_tx_en);
+void drv_idc_auto_tx_dis(void);
+void drv_idc_set_enable_rat(kal_uint8 rat_status);
+void drv_idc_set_disable_rat(kal_uint8 rat_status);
+void drv_idc_wakeup_notify(kal_uint8 rat_status);
+void drv_idc_sleep_notify(kal_uint8 rat_status);
+
+//GPS_B13_B14
+void drv_idc_gps_b13_b14_set(kal_uint8 rat_status, kal_uint16 raw_data);
+//GPS_L1_L5
+kal_bool drv_idc_schedule_gps_l1_l5_blank_event(kal_uint8 rat_status, kal_uint8 raw_data, kal_uint32 frc_time);
+
+struct idc_drv_to_el1_callback {
+ IDC_DRV_TO_EL1_CALLBACK callback_func ;
+ #if defined(__MD93__)
+ kal_bool private_data ;
+ #elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ void *private_data ;
+ #endif
+};
+
+typedef struct
+{
+ kal_uint32 owner_id;
+ kal_uint8 main_state;
+ kal_bool intr_en;
+ kal_uint8 schedule_state;
+ kal_uint8 event_cnt;
+ kal_uint8 event_pending_cnt; // Pend an event when SRAM is full
+ kal_uint32 event_offset_table[IDC_MAX_EVENT_NUM];
+#if defined(__MD93__)
+ kal_uint16 event_data_table[IDC_MAX_EVENT_NUM];
+#elif defined(__MD95__) || defined(__MD97__) || (defined(__MD97P__))
+ kal_uint8 event_data_table[IDC_MAX_EVENT_NUM][9];
+ kal_uint8 sram_table_usage[IDC_MAX_SRAM_SIZE];
+ kal_uint32 event_byte_num[IDC_MAX_EVENT_NUM];
+ kal_uint32 event_sram_sta_idx[IDC_MAX_EVENT_NUM];
+ kal_uint8 sram_w_index;
+#endif
+ kal_uint8 event_w_index;
+ kal_uint32 event_longest_time;
+ kal_uint8 event_longest_index;
+ kal_uint32 event_usage_bit_map;
+ kal_uint32 event_pending_offset_table[IDC_MAX_EVENT_NUM]; // Store the index that indicates which event is pending
+ kal_uint16 event_pending_data_table[IDC_MAX_EVENT_NUM];
+ kal_uint32 rx_buf;
+ kal_uint32 phy_time;//use for gen93/gen95
+ kal_uint32 frc_time;//use for gen97
+ kal_uint8 event_w_index_lte;
+ kal_uint8 event_w_index_nr;
+ kal_uint8 event_w_index_com;
+ IDC_CTRL_DCB_CONFIG_T DCB;
+ IDC_PIN_MODE_T pin_mode;
+ struct idc_drv_to_el1_callback pm_cb_handle[IDC_PM_NUM];
+} idc_struct_t;
+
+typedef struct
+{
+#if defined(__MD93__)
+ kal_uint8 type;
+ kal_uint16 msg;
+#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ kal_uint32 type:4;
+ kal_uint32 elen:3;
+ kal_uint32 sub_type:6;
+ kal_uint32 msg2:10;
+ kal_uint32 msg1;
+#endif
+} IDC_ILM_MSG_T;
+
+typedef enum
+{
+ IDC_OPEN,
+ IDC_IN_USE,
+ IDC_IN_SLEEP,
+ IDC_SUSPEND,
+ IDC_CLOSED
+} IDC_MAIN_STATE_T;
+
+typedef enum
+{
+ IDC_PLAN,
+ IDC_RUN
+} IDC_SCHEDULE_STATE_T;
+#endif
diff --git a/mcu/driver/devdrv/idc/inc/idc_reg.h b/mcu/driver/devdrv/idc/inc/idc_reg.h
new file mode 100644
index 0000000..ebf4209
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/idc_reg.h
@@ -0,0 +1,415 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idc_reg.h
+ *
+ * Project:
+ * --------
+ * MOLY_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for UART driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __IDC_REG_H__
+#define __IDC_REG_H__
+
+
+#define IDC_CTRL_BASE (L1_BASE_NADDR_IDC_CTRL)
+#define IDC_CTRL_BASE_D ((L1_BASE_MADDR_IDC_CTRL & ~MDSYS_PERI_ACC_TYPE_MASK) | MDSYS_PERI_DEVICE_TYPE)
+#define IDC_UART_BASE (L1_BASE_NADDR_IDC_UART)
+
+// Clock Gating Reg
+#define PDN_LTE_TMR_MASK (0x00000200)
+
+#if defined(__MD97__) || (defined(__MD97P__))
+#define MODEML1_AO_CONFIG_BASE (0xB8020000)
+#define IDC_FRC_READY (1 << 31)
+#define IDC_FRC_OFFSET 0x3FFFFFFF
+#define IDC_FRC_WRAP 0x40000000
+#else
+#define MODEML1_AO_CONFIG_BASE (0xB6020000)
+#endif
+#define MDL1AO_CLK_STA (MODEML1_AO_CONFIG_BASE + 0x18)
+#define MDL1AO_PDN_STA (MODEML1_AO_CONFIG_BASE + 0x50)
+#define MDL1AO_PDN_CLR (MODEML1_AO_CONFIG_BASE + 0x58)
+#define PDN_IDC_CTRL_MASK (0x00000800)
+#define PDN_IDC_UART_MASK (0x00004000)
+
+//GPS_B13_B14
+#define GPS_B13_B14_REG (0xC0003328)
+#define GPS_LTE_MASK (0xFFFC)
+#define GPS_NR_MASK (0xFFFB)
+#define GPS_LTE_OFS (0x3)
+#define GPS_NR_OFS (0x4)
+
+//GEN97_PETRUS
+// IDC_CTRL
+#define IDC_CTRL_WRAP_REG (IDC_CTRL_BASE + 0x2C) //set SRAM wrap start_idx
+// IDC_UART
+#define IDC_STATUS_1 (IDC_UART_BASE + 0x134) // show NEW_PM ERR status
+#define IDC_TX_AUTO_DIS (IDC_UART_BASE + 0x138)
+#define IDC_HW_TX_FORCFE_ON_MASK (IDC_UART_BASE + 0x13C)
+#define IDC_HW_TX_FORCE_ON (IDC_UART_BASE + 0x140)
+#define IDC_CAL_WINDOW_CFG (IDC_UART_BASE + 0x144)
+#define IDC_TX_SUSP_QUOTA_CFG (IDC_UART_BASE + 0x148)
+#define IDC_TX_FORCFE_ON_INT_MASK (IDC_UART_BASE + 0x14C)
+#define IDC_HW_IDC_FORCFE_ON_CLR (IDC_UART_BASE + 0x150)
+
+#define CAL_WINDOW_RF0 (IDC_UART_BASE + 0x20C)
+#define TX_SUSP_QUOTA_RF0 (IDC_UART_BASE + 0x210)
+#define CAL_WINDOW_RF1 (IDC_UART_BASE + 0x214)
+#define TX_SUSP_QUOTA_RF1 (IDC_UART_BASE + 0x218)
+
+// IDC_CTRL (Strongly Order)
+#define IDC_CTRL_SCH_STOP (IDC_CTRL_BASE + 0x04)
+#define IDC_CTRL_SCH_STATUS (IDC_CTRL_BASE + 0x08)
+#define IDC_CTRL_DATA_CNT_CTRL (IDC_CTRL_BASE + 0x0C)
+#define IDC_CTRL_DATA_CNT (IDC_CTRL_BASE + 0x10)
+#define IDC_CTRL_FRC_REG (IDC_CTRL_BASE + 0x24)
+#define IDC_CTRL_SCH_STATUS2 (IDC_CTRL_BASE + 0x28)
+
+#define IDC_CTRL_EVT_DATA0 (IDC_CTRL_BASE + 0x100)
+#define IDC_CTRL_EVT_DATA(_n) (IDC_CTRL_EVT_DATA0 + ((_n) << 2))
+
+#define IDC_CTRL_EVENT_SETETING0 (IDC_CTRL_BASE + 0x200)
+#define IDC_CTRL_EVENT_SETETING(_n) (IDC_CTRL_EVENT_SETETING0 + ((_n) << 2))
+
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+#define IDC_CTRL_EVENT_MEM_POS0 (IDC_CTRL_BASE + 0x300)
+#define IDC_CTRL_EVENT_MEM_POS(_n) (IDC_CTRL_EVENT_MEM_POS0 + ((_n) << 2))
+#endif
+
+#if defined(__MD93__)
+#define IDC_CTRL_GPS_EVENT_BASE (IDC_CTRL_BASE + 0x300)
+#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+#define IDC_CTRL_GPS_EVENT_BASE (IDC_CTRL_BASE + 0x400)
+#endif
+
+#define IDC_CTRL_GPS_EVENT_OFF (IDC_CTRL_GPS_EVENT_BASE)
+#define IDC_CTRL_GPS_EVENT_ON (IDC_CTRL_GPS_EVENT_BASE + 0x04)
+#define IDC_CTRL_GPS_EVENT_STATUS (IDC_CTRL_GPS_EVENT_BASE + 0x08)
+#define IDC_CTRL_GPS_EVENT_STOP (IDC_CTRL_GPS_EVENT_BASE + 0x0C)
+#define IDC_CTRL_GPS_EVENT_L5_OFF (IDC_CTRL_GPS_EVENT_BASE + 0x10)
+#define IDC_CTRL_GPS_EVENT_L5_ON (IDC_CTRL_GPS_EVENT_BASE + 0x14)
+#define IDC_CTRL_GPS_EVENT_L5_STATUS (IDC_CTRL_GPS_EVENT_BASE + 0x18)
+#define IDC_CTRL_GPS_EVENT_L5_STOP (IDC_CTRL_GPS_EVENT_BASE + 0x1C)
+
+
+
+#define IDC_CTRL_DUMMY (IDC_CTRL_BASE + 0x14)
+#define IDC_CTRL_RSV0 (IDC_CTRL_BASE + 0x18)
+#define IDC_CTRL_RSV1 (IDC_CTRL_BASE + 0x1C)
+#define IDC_CTRL_DBG_FLAG (IDC_CTRL_BASE + 0x20)
+
+
+// IDC_CTRL (Device Type)
+#define IDC_CTRL_SCH_STOP_D (IDC_CTRL_BASE_D + 0x04)
+#define IDC_CTRL_SCH_STATUS_D (IDC_CTRL_BASE_D + 0x08)
+#define IDC_CTRL_DATA_CNT_CTRL_D (IDC_CTRL_BASE_D + 0x0C)
+#define IDC_CTRL_DATA_CNT_D (IDC_CTRL_BASE_D + 0x10)
+#define IDC_CTRL_EVT_DATA0_D (IDC_CTRL_BASE_D + 0x100)
+#define IDC_CTRL_EVT_DATA_D(_n) (IDC_CTRL_EVT_DATA0_D + ((_n) << 2))
+#define IDC_CTRL_EVENT_SETETING0_D (IDC_CTRL_BASE_D + 0x200)
+#define IDC_CTRL_EVENT_SETETING_D(_n) (IDC_CTRL_EVENT_SETETING0_D + ((_n) << 2))
+
+#define IDC_CTRL_GPS_EVENT_BASE_D (IDC_CTRL_BASE_D + 0x300)
+#define IDC_CTRL_GPS_EVENT_OFF_D (IDC_CTRL_GPS_EVENT_BASE_D)
+#define IDC_CTRL_GPS_EVENT_ON_D (IDC_CTRL_GPS_EVENT_BASE_D + 0x04)
+#define IDC_CTRL_GPS_EVENT_STATUS_D (IDC_CTRL_GPS_EVENT_BASE_D + 0x08)
+
+#define IDC_CTRL_DUMMY_D (IDC_CTRL_BASE_D + 0x14)
+#define IDC_CTRL_RSV0_D (IDC_CTRL_BASE_D + 0x18)
+#define IDC_CTRL_RSV1_D (IDC_CTRL_BASE_D + 0x1C)
+#define IDC_CTRL_DBG_FLAG_D (IDC_CTRL_BASE_D + 0x20)
+
+
+// IDC_UART
+#define IDC_UART_RBR (IDC_UART_BASE + 0x00)
+#define IDC_UART_THR (IDC_UART_BASE + 0x00)
+#define IDC_UART_DLL (IDC_UART_BASE + 0x00)
+#define IDC_UART_DLM (IDC_UART_BASE + 0x04)
+#define IDC_UART_IER (IDC_UART_BASE + 0x04)
+#define IDC_UART_IIR (IDC_UART_BASE + 0x08)
+#define IDC_UART_FCR (IDC_UART_BASE + 0x08)
+#define IDC_UART_LCR (IDC_UART_BASE + 0x0C)
+#define IDC_UART_MCR (IDC_UART_BASE + 0x10)
+#define IDC_UART_LSR (IDC_UART_BASE + 0x14)
+#define IDC_UART_MSR (IDC_UART_BASE + 0x18)
+#define IDC_UART_HIGHSPEED (IDC_UART_BASE + 0x24)
+#define IDC_UART_SAMPLE_COUNT (IDC_UART_BASE + 0x28)
+#define IDC_UART_SAMPLE_POINT (IDC_UART_BASE + 0x2C)
+#define IDC_UART_RXTRIG (IDC_UART_BASE + 0x50)
+#define IDC_UART_FRACDIV_L_TX (IDC_UART_BASE + 0x54)
+#define IDC_UART_FRACDIV_M_TX (IDC_UART_BASE + 0x58)
+#define IDC_UART_FRACDIV_L_RX (IDC_UART_BASE + 0x84)
+#define IDC_UART_FRACDIV_M_RX (IDC_UART_BASE + 0x88)
+#define IDC_UART_FCR_RD (IDC_UART_BASE + 0x5C)
+#define IDC_PM_STATUS (IDC_UART_BASE + 0xBC)
+#define IDC_PRI0 (IDC_UART_BASE + 0xC0)
+#define IDC_PRI0_BITEN (IDC_UART_BASE + 0xC4)
+#define IDC_PAT0 (IDC_UART_BASE + 0xC8)
+#define IDC_PAT0_BITEN (IDC_UART_BASE + 0xCC)
+#define IDC_PRI(_n) (IDC_PRI0 + ((_n) << 4))
+#define IDC_PRI_BITEN(_n) (IDC_PRI0_BITEN + ((_n) << 4))
+#define IDC_PAT(_n) (IDC_PAT0 + ((_n) << 4))
+#define IDC_PAT_BITEN(_n) (IDC_PAT0_BITEN + ((_n) << 4))
+
+#define IDC_NEW_PM_ERR_RX_BUFF (IDC_UART_BASE + 0x100)
+#define IDC_CC_STATUS (IDC_UART_BASE + 0x104)
+#define IDC_NEW_PAT0 (IDC_UART_BASE + 0x108)
+#define IDC_NEW_PAT1 (IDC_UART_BASE + 0x10C)
+#define IDC_INT_MASK_STATUS (IDC_UART_BASE + 0x110)
+#define IDC_INT_MASK_SET (IDC_UART_BASE + 0x114)
+#define IDC_INT_MASK_CLR (IDC_UART_BASE + 0x118)
+#define IDC_FORCE_TRIGGER_RF (IDC_UART_BASE + 0x11C)
+#define IDC_NEW_PM_DEBUG (IDC_UART_BASE + 0x120)
+#define IDC_REMAPPING_CFG (IDC_UART_BASE + 0x124)
+#define IDC_REMAPPING_EN (IDC_UART_BASE + 0x128)
+#define IDC_CC4_STATUS (IDC_UART_BASE + 0x130) // show cc4~cc5 status
+
+//DEBUG
+#define IDC_UART_SCR (IDC_UART_BASE + 0x1C)
+#define IDC_TX_WOFFSET (IDC_UART_BASE + 0x70)
+#define IDC_OP_RX_REQ (IDC_UART_BASE + 0x74)
+#define IDC_RX_ROFFSET (IDC_UART_BASE + 0x78)
+#define IDC_RX_WOFFSET (IDC_UART_BASE + 0x7C)
+#define IDC_UART_GUARD (IDC_UART_BASE + 0x3C)
+#define IDC_UART_ESCAPE_EN (IDC_UART_BASE + 0x44)
+#define IDC_UART_SLEEP_EN (IDC_UART_BASE + 0x48)
+#define IDC_UART_DEBUG_1 (IDC_UART_BASE + 0x64)
+#define IDC_UART_DEBUG_8 (IDC_UART_BASE + 0x80)
+#define IDC_UART_DEBUG_10 (IDC_UART_BASE + 0x204)
+#define IDC_UART_SLEEP_CTRL (IDC_UART_BASE + 0xB0)
+#define IDC_UART_MISC_CTRL (IDC_UART_BASE + 0xB4)
+#define IDC_UART_DLL_backup (IDC_UART_BASE + 0x90)
+#define IDC_UART_DLM_backup (IDC_UART_BASE + 0x94)
+#define IDC_UART_EFR_backup (IDC_UART_BASE + 0x98)
+#define IDC_UART_FEATURE_SEL (IDC_UART_BASE + 0x9C)
+
+//M2C Bridge
+#define M2C_IDC2PTA_BRIDGE_BASE 0xC0211000
+#define M2C_IDC2PTA_BRIDGE_SPM_ACK (M2C_IDC2PTA_BRIDGE_BASE + 0xF00)
+#define M2C_IDC2PTA_BRIDGE_M2C_EN (M2C_IDC2PTA_BRIDGE_BASE + 0x500)
+#define M2C_IDC2PTA_BRIDGE_M2C_TIME (M2C_IDC2PTA_BRIDGE_BASE + 0x504)
+#define M2C_IDC2PTA_BRIDGE_M2C_DBG1 (M2C_IDC2PTA_BRIDGE_BASE + 0x800)
+#define M2C_IDC2PTA_BRIDGE_M2C_DBG2 (M2C_IDC2PTA_BRIDGE_BASE + 0x900)
+
+#define M2C_SPM_ACK (0x7 << 2)
+#define M2C_EN 0x7ff
+#define M2C_TIME 0x040404
+
+//IER
+#define IDC_UART_IER_ALLOFF 0x0000
+#define IDC_UART_IER_ERBFI 0x0001
+#define IDC_UART_IER_ETBEI 0x0002
+#define IDC_UART_IER_INT_MASK 0x00ef
+
+//HIGHSPEED
+#define IDC_UART_HIGHSPEED_X 0x0003 // baud = clock/UART_RATE_STEP_COUNT
+
+//FCR
+#define IDC_UART_FCR_FIFOEN 0x0001
+#define IDC_UART_FCR_CLRR 0x0002
+#define IDC_UART_FCR_CLRT 0x0004
+#define IDC_UART_FCR_FIFOINI 0x0007
+#define IDC_UART_FCR_RXTRIG 0x00c0
+
+#define IDC_UART_TxFIFO_DEPTH 32
+#define IDC_UART_RxFIFO_DEPTH 32
+
+//IIR (RO)
+#define IDC_UART_IIR_INT_INVALID 0x0001
+#define IDC_UART_IIR_THR_EMPTY 0x0002 // TX Empty
+#define IDC_UART_IIR_RDA 0x0004 // Receive Data Available
+#define IDC_UART_IIR_RDT 0x000c // Receive Data Timeout
+#define IDC_UART_IIR_INT_MASK 0x003f
+
+//===============================LCR================================
+//WLS
+#define IDC_UART_WLS_8 0x0003
+#define IDC_UART_WLS_7 0x0002
+#define IDC_UART_WLS_6 0x0001
+#define IDC_UART_WLS_5 0x0000
+#define IDC_UART_DATA_MASK 0x0003
+
+//Parity
+#define IDC_UART_NONE_PARITY 0x0000
+#define IDC_UART_ODD_PARITY 0x0008
+#define IDC_UART_EVEN_PARITY 0x0018
+#define IDC_UART_ONE_PARITY 0x0028
+#define IDC_UART_ZERO_PARITY 0x0038
+#define IDC_UART_PARITY_MASK 0x0038
+
+//Stop bits
+#define IDC_UART_1_STOP 0x0000
+#define IDC_UART_1_5_STOP 0x0004 // Only valid for 5 data bits
+#define IDC_UART_2_STOP 0x0004
+#define IDC_UART_STOP_MASK 0x0004
+
+#define IDC_UART_LCR_DLAB 0x0080
+//===============================LCR================================
+
+//LSR
+#define IDC_UART_LSR_DR 0x0001
+#define IDC_UART_LSR_TEMT 0x0040
+
+#endif // __IDC_REG_H__
diff --git a/mcu/driver/devdrv/idc/inc/idc_suart.h b/mcu/driver/devdrv/idc/inc/idc_suart.h
new file mode 100644
index 0000000..3fcc21c
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/idc_suart.h
@@ -0,0 +1,40 @@
+#ifndef __IDC_SUART_H__
+#define __IDC_SUART_H__
+
+#include "reg_base.h"
+
+
+#define REG_PERISYS_IDC_SUART_RBR_THR_DLL_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x00)
+#define REG_PERISYS_IDC_SUART_IER_DLM_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x04)
+#define REG_PERISYS_IDC_SUART_IIR_FCR_EFR_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x08)
+#define REG_PERISYS_IDC_SUART_LCR_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x0C)
+#define REG_PERISYS_IDC_SUART_MCR_XON1_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x10)
+#define REG_PERISYS_IDC_SUART_LSR_XON2_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x14)
+#define REG_PERISYS_IDC_SUART_MSR_XOFF1_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x18)
+#define REG_PERISYS_IDC_SUART_SCR_XOFF2_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x1C)
+#define REG_PERISYS_IDC_SUART_AUTOBAUD_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x20)
+#define REG_PERISYS_IDC_SUART_RATE_STEP_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x24)
+#define REG_PERISYS_IDC_SUART_STEP_COUNT_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x28)
+#define REG_PERISYS_IDC_SUART_SAMPLE_COUNT_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x2C)
+#define REG_PERISYS_IDC_SUART_AUTOBAUD_DATA_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x30)
+#define REG_PERISYS_IDC_SUART_RATE_FIX_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x34)
+#define REG_PERISYS_IDC_SUART_AUTOBAUD_RATE_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x38)
+#define REG_PERISYS_IDC_SUART_GUARD_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x3C)
+#define REG_PERISYS_IDC_SUART_ESC_CHAR_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x40)
+#define REG_PERISYS_IDC_SUART_ESC_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x44)
+#define REG_PERISYS_IDC_SUART_SLEEP_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x48)
+#define REG_PERISYS_IDC_SUART_RXDMA_EN_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x4C)
+#define REG_PERISYS_IDC_SUART_RXTRIG_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x50)
+#define REG_PERISYS_IDC_SUART_RXTIMEOUT_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x54)
+#define REG_PERISYS_IDC_SUART_RXDMA_CTRL_ADDR (BASE_ADDR_PERISYS_IDC_SUART+0x58)
+#define REG_PERISYS_IDC_SUART_DUMMY (BASE_ADDR_PERISYS_IDC_SUART+0x5c)
+#define REG_PERISYS_IDC_SUART_START_PRI (BASE_ADDR_PERISYS_IDC_SUART+0x60)
+#define REG_PERISYS_IDC_SUART_START_PRI_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x64)
+#define REG_PERISYS_IDC_SUART_START_PAT (BASE_ADDR_PERISYS_IDC_SUART+0x68)
+#define REG_PERISYS_IDC_SUART_START_PAT_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x6C)
+#define REG_PERISYS_IDC_SUART_FINISH_PRI (BASE_ADDR_PERISYS_IDC_SUART+0x70)
+#define REG_PERISYS_IDC_SUART_FINISH_PRI_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x74)
+#define REG_PERISYS_IDC_SUART_FINISH_PAT (BASE_ADDR_PERISYS_IDC_SUART+0x78)
+#define REG_PERISYS_IDC_SUART_FINISH_PAT_BITEN (BASE_ADDR_PERISYS_IDC_SUART+0x7C)
+
+#endif
diff --git a/mcu/driver/devdrv/idc/inc/idc_trace.h b/mcu/driver/devdrv/idc/inc/idc_trace.h
new file mode 100644
index 0000000..dbf510d
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/idc_trace.h
@@ -0,0 +1,16 @@
+#if !defined(__IDC_TRACE_H__)
+#define __IDC_TRACE_H__
+#if !defined(GEN_FOR_PC)
+#include "kal_public_defs.h"
+#endif
+#include "dhl_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined (__DHL_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif
+#endif
+#if !defined(GEN_FOR_PC)
+#if !defined(__MAUI_BASIC__)
+#include"idc_trace_mod_idc_utmd.h"
+#endif
+#endif
+#endif /* !__IDC_TRACE_H__ */
diff --git a/mcu/driver/devdrv/idc/inc/idc_trace_mod_idc_utmd.json b/mcu/driver/devdrv/idc/inc/idc_trace_mod_idc_utmd.json
new file mode 100644
index 0000000..5cd505b
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/idc_trace_mod_idc_utmd.json
@@ -0,0 +1,825 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_IDC",
+ "startGen": "Legacy",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Medium",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "CoreDesign"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "DesignInfo"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "InternalDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "IDC_START_COUNT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Start counting CONNSYS TX/RX",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_END_COUNT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] End counting CONNSYS TX/RX (%d/%d)",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "IDC_TDM_HI_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] TDM_REQ_HI_Entry",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "IDC_TDM_LO_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] TDM_REQ_LO_Entry",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "IDC_TDM_INIT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] TDM_REQ Init",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "IDC_UART_INIT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC UART Init",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_0_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event, schedule_num %d, num_event %d",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "IDC_SCHEDULE_1_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Offset = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_2_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Tx Schedule Event, Schedule Offset = %d, Schedule data = %x %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_LTE_NR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Tx Schedule Event, Schedule Offset = %d, Schedule data = %x %x, Event type = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_IN_SLEEP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule in RAT sleep, Event type = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SET_RAT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Set RAT status, RAT status = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SET_RAT_SLEEP_NOTIFY_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Set RAT status in sleep notify, RAT status = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SET_RAT_WAKEUP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Set RAT status in wakeup, RAT status = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DIS_RAT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Disable RAT status, RAT status = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SET_RAT_ERR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Set RAT status Error, RAT status = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SET_IDC_INIT_FLAG_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] SET IDC_INIT_FLAG in : %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_CLR_IDC_INIT_FLAG_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] CLR IDC_INIT_FLAG in : %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_B13_B14_SET_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC_GPS_B13_B14_SET RESULT: %x, RAT_STATUS : %x, RAW_DATA : %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_CLOSE_RX_FIFO_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] CLOSE RX_FIFO in : %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_UPDATE_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Tx PHY_TIME Update from EL1C, PHY_TIME = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_START_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Start Schedule %d 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_STATUS_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Get Schedule Status 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "IDC_SCHEDULE_STATUS_2_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Get Schedule Status_2 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_FAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event fail, Offset = %d, cmd type = %d, cmd sub_type = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_FAIL_LTE_NR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event fail, Offset = %d, cmd type = %d, cmd sub_type = %d, event_type = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_EVNET_TYPE_ERR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event type error, event_type = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_EVENT_FULL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event fail, EVENT_FULL",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_BEFORE_CLR_RX_FIFO_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] DR Issue dump: BEFORE_CLR_RX_FIFO, FCR_RD(0x5C) = %x, OP_RX_REQ(0x74) = %x, R_OFFSET(0x78) = %x, W_OFFSET(0x7C) = %x, CLK1 = %x. CLK2 = %x, SCR(0x1C) = %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_AFTER_CLR_RX_FIFO_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] DR Issue dump: AFTER_CLR_RX_FIFO, FCR_RD(0x5C) = %x, OP_RX_REQ(0x74) = %x, R_OFFSET(0x78) = %x, W_OFFSET(0x7C) = %x, CLK1 = %x. CLK2 = %x, SCR(0x1C) = %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DR_ISSUE_DUMP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] DR Issue dump: In %s, FCR_RD(0x5C) = %x, OP_RX_REQ(0x74) = %x, R_OFFSET(0x78) = %x, W_OFFSET(0x7C) = %x, CLK1 = %x. CLK2 = %x, SCR(0x1C) = %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DR_ISSUE_HIT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] DR_ISSUE HIT!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DR_ISSUE_RECOVER_SUCCESS_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] DR_ISSUE after clear RXFIFO workaround, RX status recover success!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DR_ISSUE_RECOVER_FAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] DR_ISSUE after clear RXFIFO workaround, RX status recover fail!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_EVENT_IDX_NOT_FOUND_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event fail, EVENT_IDX_NOT_FOUND",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_SRAM_FULL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event fail, SRAM_FULL",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SCHEDULE_NO_SEQUENTIAL_SRAM_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule Event fail, NO_SEQUENTIAL_SRAM",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_NEW_PM_ERROR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] NEW_PM_ERROR occurs : pm_status: %x, error_rx_buf: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_INTERNAL_PIN_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Switch to internal pins",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_ALREADY_SET_PIN_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Already set pins",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_EXTERNAL_PIN_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Switch to external pins",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_LISR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IIR = %x, IER = %x, LSR = %x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "IDC_RX_HISR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] HISR without Read Data, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "IDC_RX_WARNING_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] [Warning]IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "IDC_RX_HISTORY_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Receive %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "IDC_RX_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Receive %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_80211_RX_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Receive 802_11_RX %x %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_80211_TX_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Receive 802_11_TX %x %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_CONSYS_TX_GRANT_NTF_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Receive 802_11_TX %x %x %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_SEND_ILM_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] MSG Send to EL1: %x, type:%x, msg:%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_NOT_SEND_ILM_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] MSG Not Send to EL1: %x, type:%x, msg:%x",
+ "traceClass": "TRACE_WARNING"
+ }
+ },
+ {
+ "IDC_RX_95_SEND_ILM_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] MSG Send to EL1: %x, type:%x, sub_type:%x, msg1:%x, msg2:%x, len:%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_95_NOT_SEND_ILM_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] MSG Not Send to EL1: %x, type:%x, sub_type:%x, msg1:%x, msg2:%x, len:%d",
+ "traceClass": "TRACE_WARNING"
+ }
+ },
+ {
+ "IDC_RX_ABNORMAL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC rx_buf receive 2 abnormal byte : %x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "IDC_TX_COUNT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Tx count: 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_EVENTS_STILL_BUSY_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Some events are expired in scheduler & stopped. Status = 0x%x, Status2 = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_EVENTS_STILL_BUSY_2_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Some events are expired in scheduler & stopped. expire_event_status = 0x%x, event_status = 0x%x, expire_event_status_2 = 0x%x, event_status_2 = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_TXFIFO_CNT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] TX_FIFO_CNT = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SLEEP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In drv_idc_init, sleep mode = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_NONSLEEP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In drv_idc_init, NONSLEEP LAST TIME, no need re-init IDC_UART, sleep mode = %d, LTE_FLAG = %d, NR_FLAG = %d, INIT_FLAG = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_ACTIVATE_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In drv_idc_activate",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_SUSPEND_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] UART RX suspends due to too many IDC commands received in 100 us",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "IDC_ILM_DISABLE_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC_ILM disable by EL1",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_ILM_ENABLE_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC_ILM enable by EL1",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_RESUME_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] UART RX resume",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_WAKEUP_RX_RESUME_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] UART RX resume beacause sleep mode wake up",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_WAIT_IER_OFF_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Writing IER is not complete, count = %d",
+ "traceClass": "TRACE_WARNING"
+ }
+ },
+ {
+ "IDC_CLEAN_RXFIFO_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Clean RxFIFO in : %s",
+ "traceClass": "TRACE_WARNING"
+ }
+ },
+ {
+ "IDC_UNMASK_UART_ISR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Unmask UART ISR in : %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_FUN_ENTER_CONCURRENTLY_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] The IDC CTRL FUNC entering concurrently(%x, %x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_LEAVE_FUN_NOT_MATCH_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] The IDC CTRL leave FUNC(%x) don't match enter func(%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_BLANK_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS event trigger, RAT = (%x) , gps_mode = (%x) , gps_status = (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_BLANK_DETAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS BLANK schedule event, ALL_BM = (%x) ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_BLANK_FAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS BLANK schedule fail, LINE = (%x), Satus = (%x) , Current_frc = (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_BLANK_TRIG_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS BLANK schedule event trigger, Current_frc : (%x), On/off : (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_BLANK_DROP0_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS BLANK DROP event FRC less than Current_FRC+50us,LINE = (%x), Event_frc : (%x), : Current_frc(%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_BLANK_DROP1_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS BLANK DROP event FRC more than Current_FRC+10ms,,LINE = (%x), Event_frc : (%x), : Current_frc(%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_L1_L5_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS L1/L5 schedule event, RAT = (%x) , DATA = (%x), TIME = (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_L1_L5_DETAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS L1/L5 schedule event, ALL_BM = (%x) , LTE_BM = (%x), NR_BM = (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GPS_L1_L5_TRIG_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS L1/L5 schedule event trigger, L1/L5 : (%x), On/off : (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+
+ {
+ "IDC_GPS_L1_L5_FAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GPS L1/L5 schedule fail, LINE = (%x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SRAM_FULL_DATA_IN_EVENT_BUFFER": {
+ "apiType": "index",
+ "format": "[DRV_IDC]SRAM is full, Incoming event put in event_buf",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DATA_IN_EVENT_BUFFER": {
+ "apiType": "index",
+ "format": "[DRV_IDC]This event put in event_buf, offset: %d, data: %x %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_DATA_IN_EVENT_BUFFER_DISPLACE_HAPPEN": {
+ "apiType": "index",
+ "format": "[DRV_IDC][DISPLACE]This event put in event_buf, offset: %d, data: %x %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RESCHEDULE_EVENT_IN_EVENT_BUFFER": {
+ "apiType": "index",
+ "format": "[DRV_IDC][RESCHEDULE]This event rescheduled in SRAM, offset: %d, data: %x %x",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "IDC_SCHEDULE_OVER_10MS_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] EL1C schedule over 10ms, PHY_TIME = %d, Schedule Offset = %d, Schedule data = %x %x",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "IDC_STOP_AND_FLUSH_EVENT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC_STOP_AND_FLUSH_EVENT, Schedule data = 0x%x, Schedule Offset = 0x%x, phy_time = 0x%x, real_phy_time = 0x%x, Wrap_case = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_POLL_TIME_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] POLLING TIME in idc_stop_event, time slot: %d, before time: %x, after time: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_POLL_APB_CNT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] POLLING APB CNT in idc_stop_event= %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_GET_ATOMIC_LOCK_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] GET %s ATOMIC LOCK in : %s %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RELEASE_ATOMIC_LOCK_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] RELEASE %s ATOMIC LOCK in : %s %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_TAKE_FLAG_FAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] TAKE FLAG FAIL in : %s",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_PROFILE_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] PROFILE in %s, time slot : %d, before time: %x, after time: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_LISR_STA_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IIR_B : %x, IER_B : %x, LSR_B : %x, IIR_A : %x, IER_A : %x, LSR_A : %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_ILMNUM_ABNORMAL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] ilm_num is abnormal in %d!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SEND_EVENT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In Send_event function , event_num = %d, data: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x !!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SEND_EVENT_FAIL_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In Send_event function , but Send_event fail. last time send_event is still busy , event_num = %d, data: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x !!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SEND_EVENT_DROP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule CMD drop in send_event function!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SEND_EVENT_RESCHEDULE_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Schedule CMD re-schedule success in send_event function!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SEND_EVENT_DUMP_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In Send_event function, dump IDC_UART_REG[0x28: 0x%x, 0x2c: 0x%x, 0x3c: 0x%x, 0x44: 0x%x, 0x48: 0x%x, 0x64: 0x%x, 0x80: 0x%x, 0xb0:0x%x, 0xb4:0x%x, 0x204: 0x%x, 0x90:0x%x, 0x94:0x%x, 0x98:0x%x, 0x9c:0x%x], MDL1_AO_REG[0x18: 0x%x, 0x50: 0x%x], IDC_CTRL_REG[0x24: 0x%x]!!!",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_RX_FIFO_DATA_CNT_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC_RX_FIFO_DATA_CNT_MSG : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_NEW_CMD_ERROR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] new_cmd error cnt: %d ,occur in %d byte, error byte :%x, error byte in %d history",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_IDC_PM_LISR_STS_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In idc_pm_lisr sts: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_SEND_EVENT_SLEEP_MODE_STS_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] IDC_SEND_EVENT, SLEEP_MODE : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_IDC_SET_NEW_PM_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In idc_set_new_pm_config: %x, %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_FORCE_ON_TX_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] Force on Tx path by EL1 : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_AUTO_TX_CONFIG_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] AUTO_TX CONFIG by EL1 tx_susp_quota: %d, reset_quota : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_AUTO_TX_EN_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] AUTO_TX EN/DIS by EL1 : %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "IDC_AUTO_TX_LISR_MSG": {
+ "apiType": "index",
+ "format": "[DRV_IDC] In AUTO_TX_LISR, tx_susp_int : 0x%x, reset_int: 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ }
+ ],
+ "traceFamily": "PS"
+}
diff --git a/mcu/driver/devdrv/idc/inc/pf_bsictrl_apb2.h b/mcu/driver/devdrv/idc/inc/pf_bsictrl_apb2.h
new file mode 100644
index 0000000..12a4604
--- /dev/null
+++ b/mcu/driver/devdrv/idc/inc/pf_bsictrl_apb2.h
@@ -0,0 +1,40 @@
+#ifndef __BSICTRL_APB2_H__
+#define __BSICTRL_APB2_H__
+
+#include "reg_base.h"
+
+#define BASE_ADDR_BSI_DSPIO_IND 0x00000000
+
+#define REG_PERISYS_PFBSI_APB2_IMM_CTRL (BASE_ADDR_PERISYS_PFBSI_APB2 +0x0)
+#define REG_PERISYS_PFBSI_APB2_IMM_WDATA (BASE_ADDR_PERISYS_PFBSI_APB2 +0x4)
+#define REG_PERISYS_PFBSI_APB2_RDINT (BASE_ADDR_PERISYS_PFBSI_APB2 +0x8)
+#define REG_PERISYS_PFBSI_APB2_IMM_RDATA_3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0xC)
+#define REG_PERISYS_PFBSI_APB2_IMM_RDATA_3532 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x10)
+#define REG_PERISYS_PFBSI_APB2_SCH_CTRL (BASE_ADDR_PERISYS_PFBSI_APB2 +0x14)
+#define REG_PERISYS_PFBSI_APB2_SCH_RDATA0_3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x18)
+#define REG_PERISYS_PFBSI_APB2_SCH_RDATA0_3532 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x1C)
+#define REG_PERISYS_PFBSI_APB2_SCH_RDATA1_3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x20)
+#define REG_PERISYS_PFBSI_APB2_SCH_RDATA1_3532 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x24)
+#define REG_PERISYS_PFBSI_APB2_TX_GLO_OS0 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x28)
+#define REG_PERISYS_PFBSI_APB2_RX_GLO_OS0 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x2C)
+#define REG_PERISYS_PFBSI_APB2_TX_GLO_OS1 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x30)
+#define REG_PERISYS_PFBSI_APB2_RX_GLO_OS1 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x34)
+#define REG_PERISYS_PFBSI_APB2_SCH_START_3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x38)
+#define REG_PERISYS_PFBSI_APB2_SCH_START_6332 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x3C)
+#define REG_PERISYS_PFBSI_APB2_SCH_STOP_3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x40)
+#define REG_PERISYS_PFBSI_APB2_SCH_STOP_6332 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x44)
+#define REG_PERISYS_PFBSI_APB2_SCH_STATUS_3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x48)
+#define REG_PERISYS_PFBSI_APB2_SCH_STATUS_6332 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x4C)
+#define REG_PERISYS_PFBSI_APB2_IND_ADDR (BASE_ADDR_PERISYS_PFBSI_APB2 +0x50)
+#define REG_PERISYS_PFBSI_APB2_IND_DATA (BASE_ADDR_PERISYS_PFBSI_APB2 +0x54)
+#define REG_PERISYS_PFBSI_APB2_IND_RD (BASE_ADDR_PERISYS_PFBSI_APB2 +0x58)
+#define REG_PERISYS_PFBSI_APB2_CLSNINT_CTRL (BASE_ADDR_PERISYS_PFBSI_APB2 +0x5C)
+#define REG_PERISYS_PFBSI_APB2_CLSNINT_SCH3100 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x60)
+#define REG_PERISYS_PFBSI_APB2_CLSNINT_SCH6332 (BASE_ADDR_PERISYS_PFBSI_APB2 +0x64)
+#define REG_PERISYS_PFBSI_APB2_SRAM_DELSEL (BASE_ADDR_PERISYS_PFBSI_APB2 +0x68)
+#define REG_PERISYS_PFBSI_APB2_MBIST_BACKGROUND (BASE_ADDR_PERISYS_PFBSI_APB2 +0x6C)
+#define REG_PERISYS_PFBSI_APB2_POR_EN (BASE_ADDR_PERISYS_PFBSI_APB2 +0x70)
+#define REG_PERISYS_PFBSI_APB2_IDC_DATA_CNT (BASE_ADDR_PERISYS_PFBSI_APB2 +0x74)
+#define REG_PERISYS_PFBSI_APB2_IDC_DATA_CNT_CTRL (BASE_ADDR_PERISYS_PFBSI_APB2 +0x78)
+
+#endif