[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6325.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6325.c
new file mode 100644
index 0000000..e367991
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6325.c
@@ -0,0 +1,1287 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6325.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6325
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+#include "dhl_trace.h"
+#if defined(PMIC_6325_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+//#define PMIC_INTERNAL_SRAM
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define BANKS_NUM 1
+#define PMIC6325_MAX_REG_NUM 0x0F50 // 0x0000~0x0F48
+//#define PMIC_MAX_REG_NUM 0x40FF // Register BUCK1, Register ANALDO, Register DIGLDO (0x0470)
+
+#define MT6325_HW_CID_E1 0x2510
+#define MT6325_HW_CID_E2 0x2520
+#define MT6325_HW_CID_E3 0x2530
+#define MT6325_SW_CID_E1 0x2510
+#define MT6325_SW_CID_E2 0x2520
+#define MT6325_SW_CID_E3 0x2530
+
+#define PMIC_READ 0
+#define PMIC_WRITE 1
+
+#define PMIC_6325 0x6325
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+extern kal_bool pmic6325_reg_write(kal_uint16 reg, kal_uint16 val);
+extern kal_bool pmic6325_reg_read(kal_uint16 reg, kal_uint16 *pVal);
+
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+//#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+//__attribute__ ((zero_init))
+//#endif /* __MTK_TARGET__ */
+kal_uint8 pmic6325_hw_version;
+kal_uint8 pmic6325_sw_version;
+kal_uint16 pmic6325_reg[PMIC6325_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+const PMIC_FLAG_TABLE_ENTRY pmic6325_flags_table[] =
+{
+ {MT6325_HWCID, MT6325_HWCID_MASK, MT6325_HWCID_SHIFT, },
+ {MT6325_SWCID, MT6325_SWCID_MASK, MT6325_SWCID_SHIFT, },
+ {MT6325_VPA_ANA_CON1, MT6325_RG_VPA_MODESET_MASK, MT6325_RG_VPA_MODESET_SHIFT, },
+ {MT6325_VRF18_0_ANA_CON1, MT6325_RG_VRF18_0_MODESET_MASK, MT6325_RG_VRF18_0_MODESET_SHIFT, },
+ {MT6325_VRF18_0_CON7, MT6325_VRF18_0_EN_CTRL_MASK, MT6325_VRF18_0_EN_CTRL_SHIFT, },
+ {MT6325_VRF18_0_CON7, MT6325_VRF18_0_VOSEL_CTRL_MASK, MT6325_VRF18_0_VOSEL_CTRL_SHIFT, },
+ {MT6325_VRF18_0_CON8, MT6325_VRF18_0_EN_SEL_MASK, MT6325_VRF18_0_EN_SEL_SHIFT, },
+ {MT6325_VRF18_0_CON8, MT6325_VRF18_0_VOSEL_SEL_MASK, MT6325_VRF18_0_VOSEL_SEL_SHIFT, },
+ {MT6325_VRF18_0_CON9, MT6325_VRF18_0_EN_MASK, MT6325_VRF18_0_EN_SHIFT, },
+ {MT6325_VRF18_0_CON11, MT6325_VRF18_0_VOSEL_MASK, MT6325_VRF18_0_VOSEL_SHIFT, },
+ {MT6325_VRF18_0_CON12, MT6325_VRF18_0_VOSEL_ON_MASK, MT6325_VRF18_0_VOSEL_ON_SHIFT, },
+ {MT6325_VRF18_0_CON13, MT6325_VRF18_0_VOSEL_SLEEP_MASK, MT6325_VRF18_0_VOSEL_SLEEP_SHIFT, },
+ {MT6325_VRF18_0_CON18, MT6325_VRF18_0_VSLEEP_EN_MASK, MT6325_VRF18_0_VSLEEP_EN_SHIFT, },
+ {MT6325_VPA_CON8, MT6325_VPA_EN_SEL_MASK, MT6325_VPA_EN_SEL_SHIFT, },
+ {MT6325_VPA_CON8, MT6325_VPA_VOSEL_SEL_MASK, MT6325_VPA_VOSEL_SEL_SHIFT, },
+ {MT6325_VPA_CON9, MT6325_VPA_EN_MASK, MT6325_VPA_EN_SHIFT, },
+ {MT6325_VPA_CON11, MT6325_VPA_VOSEL_MASK, MT6325_VPA_VOSEL_SHIFT, },
+ {MT6325_VPA_CON12, MT6325_VPA_VOSEL_ON_MASK, MT6325_VPA_VOSEL_ON_SHIFT, },
+ {MT6325_VPA_CON13, MT6325_VPA_VOSEL_SLEEP_MASK, MT6325_VPA_VOSEL_SLEEP_SHIFT, },
+ {MT6325_LDO_CON0, MT6325_RG_VTCXO0_MODE_SET_MASK, MT6325_RG_VTCXO0_MODE_SET_SHIFT, },
+ {MT6325_LDO_CON0, MT6325_RG_VTCXO0_EN_MASK, MT6325_RG_VTCXO0_EN_SHIFT, },
+ {MT6325_LDO_CON0, MT6325_RG_VTCXO0_MODE_CTRL_MASK, MT6325_RG_VTCXO0_MODE_CTRL_SHIFT, },
+ {MT6325_LDO_CON0, MT6325_RG_VTCXO0_ON_CTRL_MASK, MT6325_RG_VTCXO0_ON_CTRL_SHIFT, },
+ {MT6325_LDO_CON0, MT6325_RG_VTCXO0_SRCLK_MODE_SEL_MASK, MT6325_RG_VTCXO0_SRCLK_MODE_SEL_SHIFT, },
+ {MT6325_LDO_CON0, MT6325_QI_VTCXO0_MODE_MASK, MT6325_QI_VTCXO0_MODE_SHIFT, },
+ {MT6325_LDO_CON1, MT6325_RG_VTCXO1_MODE_SET_MASK, MT6325_RG_VTCXO1_MODE_SET_SHIFT, },
+ {MT6325_LDO_CON1, MT6325_RG_VTCXO1_EN_MASK, MT6325_RG_VTCXO1_EN_SHIFT, },
+ {MT6325_LDO_CON1, MT6325_RG_VTCXO1_MODE_CTRL_MASK, MT6325_RG_VTCXO1_MODE_CTRL_SHIFT, },
+ {MT6325_LDO_CON1, MT6325_RG_VTCXO1_ON_CTRL_MASK, MT6325_RG_VTCXO1_ON_CTRL_SHIFT, },
+ {MT6325_LDO_CON1, MT6325_RG_VTCXO1_SRCLK_MODE_SEL_MASK, MT6325_RG_VTCXO1_SRCLK_MODE_SEL_SHIFT, },
+ {MT6325_LDO_CON1, MT6325_QI_VTCXO1_MODE_MASK, MT6325_QI_VTCXO1_MODE_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_RG_VRF18_1_MODE_SET_MASK, MT6325_RG_VRF18_1_MODE_SET_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_RG_VRF18_1_EN_MASK, MT6325_RG_VRF18_1_EN_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_RG_VRF18_1_MODE_CTRL_MASK, MT6325_RG_VRF18_1_MODE_CTRL_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_RG_VRF18_1_ON_CTRL_MASK, MT6325_RG_VRF18_1_ON_CTRL_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_RG_VRF18_1_SRCLK_MODE_SEL_MASK, MT6325_RG_VRF18_1_SRCLK_MODE_SEL_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_QI_VRF18_1_MODE_MASK, MT6325_QI_VRF18_1_MODE_SHIFT, },
+ {MT6325_LDO_CON8, MT6325_RG_VRF18_1_SRCLK_EN_SEL_MASK, MT6325_RG_VRF18_1_SRCLK_EN_SEL_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_MODE_SET_MASK, MT6325_RG_VSIM1_MODE_SET_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_EN_MASK, MT6325_RG_VSIM1_EN_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_MODE_CTRL_MASK, MT6325_RG_VSIM1_MODE_CTRL_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_ON_CTRL_MASK, MT6325_RG_VSIM1_ON_CTRL_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_SRCLK_MODE_SEL_MASK, MT6325_RG_VSIM1_SRCLK_MODE_SEL_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_QI_VSIM1_MODE_MASK, MT6325_QI_VSIM1_MODE_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_STBTD_MASK, MT6325_RG_VSIM1_STBTD_SHIFT, },
+ {MT6325_LDO_CON17, MT6325_RG_VSIM1_SRCLK_EN_SEL_MASK, MT6325_RG_VSIM1_SRCLK_EN_SEL_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_MODE_SET_MASK, MT6325_RG_VSIM2_MODE_SET_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_EN_MASK, MT6325_RG_VSIM2_EN_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_MODE_CTRL_MASK, MT6325_RG_VSIM2_MODE_CTRL_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_ON_CTRL_MASK, MT6325_RG_VSIM2_ON_CTRL_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_SRCLK_MODE_SEL_MASK, MT6325_RG_VSIM2_SRCLK_MODE_SEL_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_QI_VSIM2_MODE_MASK, MT6325_QI_VSIM2_MODE_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_STBTD_MASK, MT6325_RG_VSIM2_STBTD_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_RG_VSIM2_SRCLK_EN_SEL_MASK, MT6325_RG_VSIM2_SRCLK_EN_SEL_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_QI_VSIM2_STB_MASK, MT6325_QI_VSIM2_STB_SHIFT, },
+ {MT6325_LDO_CON18, MT6325_QI_VSIM2_EN_MASK, MT6325_QI_VSIM2_EN_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_MODE_SET_MASK, MT6325_RG_VMIPI_MODE_SET_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_EN_MASK, MT6325_RG_VMIPI_EN_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_MODE_CTRL_MASK, MT6325_RG_VMIPI_MODE_CTRL_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_ON_CTRL_MASK, MT6325_RG_VMIPI_ON_CTRL_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_SRCLK_MODE_SEL_MASK, MT6325_RG_VMIPI_SRCLK_MODE_SEL_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_QI_VMIPI_MODE_MASK, MT6325_QI_VMIPI_MODE_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_STBTD_MASK, MT6325_RG_VMIPI_STBTD_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_RG_VMIPI_SRCLK_EN_SEL_MASK, MT6325_RG_VMIPI_SRCLK_EN_SEL_SHIFT, },
+ {MT6325_LDO_CON19, MT6325_QI_VMIPI_EN_MASK, MT6325_QI_VMIPI_EN_SHIFT, },
+ {MT6325_LDO_VCON9, MT6325_RG_VSIM2_VOSEL_MASK, MT6325_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6325_LDO_VCON9, MT6325_RG_VSIM1_VOSEL_MASK, MT6325_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6325_LDO_OCFB1, MT6325_RG_VSIM2_OCFB_EN_MASK, MT6325_RG_VSIM2_OCFB_EN_SHIFT, },
+ {MT6325_LDO_OCFB1, MT6325_RG_VSIM1_OCFB_EN_MASK, MT6325_RG_VSIM1_OCFB_EN_SHIFT, },
+ {MT6325_SPK_CON8, MT6325_RG_SPK_CCODE_MASK, MT6325_RG_SPK_CCODE_SHIFT, },
+ {MT6325_SPK_CON8, MT6325_RG_SPK_EN_VIEW_VCM_MASK, MT6325_RG_SPK_EN_VIEW_VCM_SHIFT, },
+ {MT6325_SPK_CON8, MT6325_RG_SPK_FBRC_EN_MASK, MT6325_RG_SPK_FBRC_EN_SHIFT, },
+ {MT6325_SPK_CON9, MT6325_SPK_TEST_MODE0_MASK, MT6325_SPK_TEST_MODE0_SHIFT, },
+ {MT6325_SPK_CON10, MT6325_SPK_TD_DONE_MASK, MT6325_SPK_TD_DONE_SHIFT, },
+ {MT6325_AUXADC_RQST1_SET, MT6325_AUXADC_RQST1_SET_MASK, MT6325_AUXADC_RQST1_SET_SHIFT, },
+ {MT6325_AUXADC_RQST1_CLR, MT6325_AUXADC_RQST1_CLR_MASK, MT6325_AUXADC_RQST1_CLR_SHIFT, },
+ {MT6325_AUXADC_ADC15, MT6325_RG_ADC_OUT_MD_MASK, MT6325_RG_ADC_OUT_MD_SHIFT, },
+ {MT6325_AUXADC_ADC16, MT6325_RG_ADC_RDY_MD_MASK, MT6325_RG_ADC_RDY_MD_SHIFT, },
+ {MT6325_AUXADC_CON20, MT6325_RG_MD_RQST_MASK, MT6325_RG_MD_RQST_SHIFT, },
+ {MT6325_AUXADC_CON27, MT6325_RG_VREF18_ENB_MD_MASK, MT6325_RG_VREF18_ENB_MD_SHIFT, },
+};
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+
+// Write Whole Bytes
+void dcl_pmic6325_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ pmic6325_reg[addr] = val;
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+// Write register field
+void dcl_pmic6325_field_write(PMIC6325_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6325_flags_table;
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic6325_reg[pTable[flag].offset];
+
+ pmic6325_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic6325_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6325_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic6325_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic6325_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ kal_uint32 savedMask = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ pmic6325_reg[addr] = reg_temp;
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic6325_field_read(PMIC6325_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6325_flags_table;
+ kal_uint32 savedMask = 0;
+ DCL_UINT16 reg_return = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6325_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic6325_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_return;
+}
+
+
+// Exported for EM used
+void pmic6325_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic6325_byte_write(reg, val);
+}
+
+kal_uint16 pmic6325_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic6325_byte_return(reg);
+}
+
+PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6325_get_HW_ECO_version(void)
+{
+ return pmic6325_hw_version;
+}
+
+PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6325_get_SW_version(void)
+{
+ return pmic6325_sw_version;
+}
+
+/*
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_750000_V, PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_00_950000_V, PMU_VOLT_01_000000_V, PMU_VOLT_01_050000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_150000_V, PMU_VOLT_01_200000_V, PMU_VOLT_01_250000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_350000_V, PMU_VOLT_01_400000_V, PMU_VOLT_01_450000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_550000_V, PMU_VOLT_01_600000_V, PMU_VOLT_01_650000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_750000_V, PMU_VOLT_01_800000_V, PMU_VOLT_01_850000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_01_950000_V, PMU_VOLT_02_000000_V, PMU_VOLT_02_050000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_150000_V, PMU_VOLT_02_200000_V, PMU_VOLT_02_250000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_350000_V, PMU_VOLT_02_400000_V, PMU_VOLT_02_450000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_550000_V, PMU_VOLT_02_600000_V, PMU_VOLT_02_650000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_750000_V, PMU_VOLT_02_800000_V, PMU_VOLT_02_850000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_02_950000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_050000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_150000_V, PMU_VOLT_03_200000_V, PMU_VOLT_03_250000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_350000_V, PMU_VOLT_03_400000_V, PMU_VOLT_03_450000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_550000_V, PMU_VOLT_03_600000_V, PMU_VOLT_03_650000_V,
+
+};
+*/
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+
+};
+
+// 3'b001: 1.65, 3'b010: 1.8 V, 3'b011: 1.85 V, 3'b101: 2.75V, 3'b110: 3.0 V, 3'b111: 3.1 V
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_01_650000_V, PMU_VOLT_01_800000_V, PMU_VOLT_01_850000_V,
+ PMU_VOLT_INVALID, PMU_VOLT_02_750000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_100000_V,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+};
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC6325_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18_1:
+ {
+ dcl_pmic6325_field_write(MT6325_VRF18_0_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VRF18_1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VMIPI_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6325_field_write(MT6325_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VRF18_1_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_SEL *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ // 1'b0: SW control by VSIM1_MODE_SET, 1'b1: HW control by SRCLKEN
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6325_field_write(MT6325_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_EN_CTRL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnCtrl);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18_1:
+ {
+ // 0: SW control1: HW control
+ dcl_pmic6325_field_write(MT6325_VRF18_0_EN_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VRF18_1_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6325_field_write(MT6325_RG_VMIPI_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_EN_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18_1:
+ {
+ dcl_pmic6325_field_write(MT6325_VRF18_0_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VRF18_1_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VMIPI_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SRCLK_MODE_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetSrclkModeSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM1_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VSIM2_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ dcl_pmic6325_field_write(MT6325_RG_VRF18_0_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6325_field_write(MT6325_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+
+ dcl_pmic6325_byte_write(MT6325_TOP_CLKSQ_SET, (0x1 << 3));
+ dcl_pmic6325_byte_write(MT6325_AUXADC_CON27, (0x0 << MT6325_RG_VREF18_ENB_MD_SHIFT));
+ dcl_pmic6325_field_write(MT6325_RG_MD_RQST, 0x0); // Need Set 0 first
+
+ dcl_pmic6325_field_write(MT6325_RG_MD_RQST, pAdcCtrl->enable);
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic6325_field_read(MT6325_RG_ADC_RDY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic6325_field_read(MT6325_RG_ADC_OUT_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ dcl_pmic6325_field_write(MT6325_RG_MD_RQST, 0x0);
+ dcl_pmic6325_byte_write(MT6325_TOP_CLKSQ_CLR, (0x1 << 3));
+ dcl_pmic6325_byte_write(MT6325_AUXADC_CON27, (0x1 << MT6325_RG_VREF18_ENB_MD_SHIFT));
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_HW_VERSION:
+ {
+ PMU_CTRL_MISC_GET_HW_VERSION *pMiscCtrl = &(data->rPMUMiscGetHwVersion);
+ if(pMiscCtrl->chip_name == PMIC_MT_6325)
+ {
+ pMiscCtrl->version = pmic6325_hw_version;
+ }
+ return_val = STATUS_OK;
+ }
+ break;
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+ pmic6325_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic6325_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+
+ return return_val;
+
+}
+
+extern void dcl_pmic6325_modem_only_init(void);
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+extern kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+
+
+void dcl_pmic6325_internal_init(void)
+{
+}
+
+#if defined(__DHL_MODULE__)
+extern kal_bool dhl_register_custom_mem_read(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_READ_MEM_CALLBACK read_cb);
+extern kal_bool dhl_register_custom_mem_write(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_WRITE_MEM_CALLBACK write_cb);
+extern void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len);
+extern void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr);
+#endif
+
+void dcl_pmic6325_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC6325_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+#if defined(__DHL_MODULE__)
+ dhl_register_custom_mem_read(DHL_CUSTOM_MEM_PMIC, PMIC_Read_Callback_For_DHL);
+ dhl_register_custom_mem_write(DHL_CUSTOM_MEM_PMIC, PMIC_Write_Callback_For_DHL);
+#endif
+ pmic_wrap_dump_init();
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic6325_hw_version = PMIC_ECO_E1;
+ pmic6325_sw_version = PMIC_ECO_E1;
+
+ // Get MT6325 ECO version
+ {
+ kal_uint16 pmic6325_hw_eco_version = 0;
+ kal_uint16 pmic6325_sw_eco_version = 0;
+ pmic6325_hw_eco_version = dcl_pmic6325_byte_return(MT6325_HWCID);
+ pmic6325_sw_eco_version = dcl_pmic6325_byte_return(MT6325_SWCID);
+
+ if (pmic6325_hw_eco_version == MT6325_HW_CID_E1)
+ {
+ pmic6325_hw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6325_hw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6325_sw_eco_version == MT6325_SW_CID_E1)
+ {
+ pmic6325_sw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6325_sw_version = PMIC_ECO_E2;
+ }
+ }
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+ dcl_pmic6325_modem_only_init();
+#endif
+ dcl_pmic6325_internal_init();
+
+ // pmic6325_customization_init();
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+#if defined(__DHL_MODULE__)
+kal_uint32 pmic_read_data;
+void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len)
+{
+ kal_uint32 write_buffer_addr = 0;
+ kal_uint32 read_data_addr = (kal_uint32)read_addr;
+ // Write Workaround
+ if(read_data_addr & 0x00000001)
+ {
+ write_buffer_addr = (read_data_addr & 0xFFFF0000) >> 16;
+ read_data_addr = (read_data_addr & 0x0000FFFE);
+ PMIC_Config_Interface(PMIC_WRITE, read_data_addr, (kal_uint32)write_buffer_addr, NULL, option);
+ }
+ PMIC_Config_Interface(PMIC_READ, read_data_addr, 0, &pmic_read_data, option);
+ *read_buffer_addr = (kal_uint32*)&pmic_read_data;
+ *read_buffer_len = 4;
+}
+
+void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr)
+{
+ PMIC_Config_Interface(PMIC_WRITE, (kal_uint32)write_addr, (kal_uint32)write_buffer_addr, NULL, option);
+}
+#endif // End of #if defined(__DHL_MODULE__)
+kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name)
+{
+ // Check argument validation
+ if((action & ~(0x1)) != 0) return 0; // Write should be 1 bit
+ if((address & ~(0xffff)) != 0) return 0; // Address should no larger than 0xFFFF
+ if((wdata & ~(0xffff)) != 0) return 0; // Write DATA should be no larger than 0xFFFF
+
+ if(action == PMIC_READ)
+ {
+ if(chip_name == PMIC_6325)
+ {
+ *rdata = (kal_uint32)DRV_Read_PMIC_Data(address);
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ else if(action == PMIC_WRITE)
+ {
+ if(chip_name == PMIC_6325)
+ {
+ DRV_Write_PMIC_Data(address, wdata);
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ return 1;
+}
+
+DCL_BOOL dcl_pmic_init_done_query(void)
+{
+ if(pmic_init_done == DCL_TRUE)
+ {
+ return DCL_TRUE;
+ }
+ else
+ {
+ return DCL_FALSE;
+ }
+}
+
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic6325_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic6325_byte_write(pmic_addr, value);
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i;
+ for (i = 0; i < PMIC6325_MAX_REG_NUM; i += 2){
+ pmic6325_reg[i] = dcl_pmic6325_byte_return(i);
+ }
+}
+
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VPA_SW;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VPA_SW;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VPA_SW;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VRF1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VRF1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VRF1;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.regval = 0x7; // (0x0~0xF)
+DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.regval = 0x7; // (0x0~0xF)
+DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+// val.regval will be your request value ( no need do any shift)
+DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VRF1;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VSIM1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VSIM2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VSIM1;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VSIM2;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6325_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6325_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6325_init.c
new file mode 100644
index 0000000..7e14e45
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6325_init.c
@@ -0,0 +1,303 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6325_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6325
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+void PMIC_DRV_SetData(DCL_UINT32 addr, DCL_UINT32 bitmask, DCL_UINT16 value, DCL_UINT32 bank)
+{
+ DCL_UINT32 temp;
+ addr |= (bank << 31);
+ temp = (~(bitmask)) & DRV_Read_PMIC_Data(addr);
+ temp |= ((value) & (bitmask));
+ DRV_Write_PMIC_Data(addr,temp);
+}
+
+// MT6325 ECO_E1
+void dcl_pmic6325_modem_only_init(void)
+{
+ // RG_EN_DRVSEL[4:4] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x4 , 0x10 , 0x10 , 0x0);
+
+ // RG_RSTB_DRV_SEL[5:5] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x4 , 0x20 , 0x20 , 0x0);
+
+ // DDUVLO_DEB_EN[0:0] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xA , 0x1 , 0x1 , 0x0);
+
+ // VDVFS11_PG_H2L_EN[0:0] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x1 , 0x1 , 0x0);
+
+ // VDVFS12_PG_H2L_EN[1:1] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x2 , 0x2 , 0x0);
+
+ // VCORE1_PG_H2L_EN[4:4] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x10 , 0x10 , 0x0);
+
+ // VCORE2_PG_H2L_EN[5:5] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x20 , 0x20 , 0x0);
+
+ // VGPU_PG_H2L_EN[6:6] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x40 , 0x40 , 0x0);
+
+ // VIO18_PG_H2L_EN[7:7] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x80 , 0x80 , 0x0);
+
+ // VAUD28_PG_H2L_EN[8:8] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x100 , 0x100 , 0x0);
+
+ // VTCXO_PG_H2L_EN[9:9] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x200 , 0x200 , 0x0);
+
+ // VUSB_PG_H2L_EN[10:10] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x400 , 0x400 , 0x0);
+
+ // VSRAM_DVFS1_PG_H2L_EN[11:11] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x800 , 0x800 , 0x0);
+
+ // VIO28_PG_H2L_EN[12:12] = 0x1
+ PMIC_DRV_SetData(0xC , 0x1000 , 0x1000 , 0x0);
+
+ // VDRAM_PG_H2L_EN[13:13] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xC , 0x2000 , 0x2000 , 0x0);
+
+ // UVLO_L2H_DEB_EN[5:5] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x10 , 0x20 , 0x20 , 0x0);
+
+ // STRUP_PWROFF_SEQ_EN[0:0] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x16 , 0x1 , 0x1 , 0x0);
+
+ // STRUP_PWROFF_PREOFF_EN[1:1] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x16 , 0x2 , 0x2 , 0x0);
+
+ // RG_TESTMODE_SWEN[11:11] = 0x0 => CC
+ PMIC_DRV_SetData(0x1E , 0x800 , 0x0 , 0x0);
+
+ // RG_SRCLKEN_IN0_HW_MODE[4:4] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x204 , 0x10 , 0x10 , 0x0);
+
+ // RG_SRCLKEN_IN1_HW_MODE[5:5] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x204 , 0x20 , 0x20 , 0x0);
+
+ // RG_OSC_SEL_HW_MODE[6:6] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x204 , 0x40 , 0x40 , 0x0);
+
+ // RG_SMT_WDTRSTB_IN[0:0] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x222 , 0x1 , 0x1 , 0x0);
+
+ // RG_SMT_SRCLKEN_IN0[2:2] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x222 , 0x4 , 0x4 , 0x0);
+
+ // RG_SMT_SRCLKEN_IN1[3:3] = 0x1 => Ricky
+ PMIC_DRV_SetData(0x222 , 0x8 , 0x8 , 0x0);
+
+ // RG_RTC_75K_CK_PDN[2:2] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x23E , 0x4 , 0x4 , 0x0);
+
+ // RG_RTCDET_CK_PDN[3:3] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x23E , 0x8 , 0x8 , 0x0);
+
+ // VDVFS11_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x4B6 , 0x7F , 0x4 , 0x0);
+
+ // VDVFS11_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x4B6 , 0x7F00 , 0x400 , 0x0);
+
+ // VDVFS12_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x4DC , 0x7F , 0x4 , 0x0);
+
+ // VDVFS12_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x4DC , 0x7F00 , 0x400 , 0x0);
+
+ // VSRAM_DVFS1_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x502 , 0x7F , 0x4 , 0x0);
+
+ // VSRAM_DVFS1_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x502 , 0x7F00 , 0x400 , 0x0);
+
+ // VDRAM_EN_CTRL[0:0] = 0x0 => YP
+ PMIC_DRV_SetData(0x522 , 0x1 , 0x0 , 0x0);
+
+ // VDRAM_VOSEL_CTRL[1:1] = 0x1 => YP
+ PMIC_DRV_SetData(0x522 , 0x2 , 0x2 , 0x0);
+
+ // VDRAM_SFCHG_FRATE[6:0] = 0x23 => ShangYing; Falling slewrate=2.0us/step
+ PMIC_DRV_SetData(0x528 , 0x7F , 0x23 , 0x0);
+
+ // VDRAM_SFCHG_FEN[7:7] = 0x1 => ShangYing; Soft change falling enable.
+ PMIC_DRV_SetData(0x528 , 0x80 , 0x80 , 0x0);
+
+ // VDRAM_SFCHG_RRATE[14:8] = 0x6 => ShangYing; Rising slewrate=0.4us/step
+ PMIC_DRV_SetData(0x528 , 0x7F00 , 0x600 , 0x0);
+
+ // VDRAM_SFCHG_REN[15:15] = 0x1 => ShangYing; Soft change raising enable.
+ PMIC_DRV_SetData(0x528 , 0x8000 , 0x8000 , 0x0);
+
+ // VDRAM_VOSEL_SLEEP[6:0] = 0x0 => YP
+ PMIC_DRV_SetData(0x52E , 0x7F , 0x0 , 0x0);
+
+ // VDRAM_TRANS_TD[1:0] = 0x3 => ShangYing; Pulse width=50uS
+ PMIC_DRV_SetData(0x538 , 0x3 , 0x3 , 0x0);
+
+ // VDRAM_TRANS_CTRL[5:4] = 0x1 => ShangYing; Force PWM when DVFS falling enable.
+ PMIC_DRV_SetData(0x538 , 0x30 , 0x10 , 0x0);
+
+ // VDRAM_VSLEEP_EN[8:8] = 0x1 => ShangYing; Sleep mode enable
+ PMIC_DRV_SetData(0x538 , 0x100 , 0x100 , 0x0);
+
+ // VRF18_0_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x54E , 0x7F , 0x4 , 0x0);
+
+ // VRF18_0_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x54E , 0x7F00 , 0x400 , 0x0);
+
+ // VGPU_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x614 , 0x7F , 0x4 , 0x0);
+
+ // VGPU_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x614 , 0x7F00 , 0x400 , 0x0);
+
+ // VCORE1_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x63A , 0x7F , 0x4 , 0x0);
+
+ // VCORE1_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x63A , 0x7F00 , 0x400 , 0x0);
+
+ // VCORE2_VOSEL_CTRL[1:1] = 0x1 => YP
+ PMIC_DRV_SetData(0x65A , 0x2 , 0x2 , 0x0);
+
+ // VCORE2_SFCHG_FRATE[6:0] = 0x23 => ShangYing; Falling slewrate=2.0us/step
+ PMIC_DRV_SetData(0x660 , 0x7F , 0x23 , 0x0);
+
+ // VCORE2_SFCHG_FEN[7:7] = 0x1 => ShangYing; Soft change falling enable.
+ PMIC_DRV_SetData(0x660 , 0x80 , 0x80 , 0x0);
+
+ // VCORE2_SFCHG_RRATE[14:8] = 0x8 => ShangYing; Rising slewrate=0.5us/step
+ PMIC_DRV_SetData(0x660 , 0x7F00 , 0x800 , 0x0);
+
+ // VCORE2_SFCHG_REN[15:15] = 0x1 => ShangYing; Soft change raising enable.
+ PMIC_DRV_SetData(0x660 , 0x8000 , 0x8000 , 0x0);
+
+ // VCORE2_VOSEL[6:0] = 0x44 => YP
+ PMIC_DRV_SetData(0x662 , 0x7F , 0x44 , 0x0);
+
+ // VCORE2_VOSEL_ON[6:0] = 0x44 => YP
+ PMIC_DRV_SetData(0x664 , 0x7F , 0x44 , 0x0);
+
+ // VCORE2_VOSEL_SLEEP[6:0] = 0x0 => YP
+ PMIC_DRV_SetData(0x666 , 0x7F , 0x0 , 0x0);
+
+ // VCORE2_TRANS_TD[1:0] = 0x3 => ShangYing; Pulse width=50uS
+ PMIC_DRV_SetData(0x670 , 0x3 , 0x3 , 0x0);
+
+ // VCORE2_TRANS_CTRL[5:4] = 0x1 => ShangYing; Force PWM when DVFS falling enable.
+ PMIC_DRV_SetData(0x670 , 0x30 , 0x10 , 0x0);
+
+ // VCORE2_VSLEEP_EN[8:8] = 0x1 => ShangYing; Sleep mode enable
+ PMIC_DRV_SetData(0x670 , 0x100 , 0x100 , 0x0);
+
+ // VIO18_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x68A , 0x7F , 0x4 , 0x0);
+
+ // VIO18_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x68A , 0x7F00 , 0x400 , 0x0);
+
+ // VIO18_VSLEEP_EN[8:8] = 0x1 => Johnson; SLEEP mode setting
+ PMIC_DRV_SetData(0x69A , 0x100 , 0x100 , 0x0);
+
+ // VPA_SFCHG_FRATE[6:0] = 0x4
+ PMIC_DRV_SetData(0x6B0 , 0x7F , 0x4 , 0x0);
+
+ // VPA_SFCHG_RRATE[14:8] = 0x4
+ PMIC_DRV_SetData(0x6B0 , 0x7F00 , 0x400 , 0x0);
+
+ // QI_VPA_BURSTL[13:12] = 0x1 => Johnson; SLEEP mode setting
+ PMIC_DRV_SetData(0x6C4 , 0x3000 , 0x1000 , 0x0);
+
+ // RG_VBIASN_EN[1:1] = 0x0 => Fandy, disable
+ PMIC_DRV_SetData(0xA38 , 0x2 , 0x0 , 0x0);
+
+ // FG_SLP_EN[8:8] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xCBC , 0x100 , 0x100 , 0x0);
+
+ // FG_ZCV_DET_EN[9:9] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xCBC , 0x200 , 0x200 , 0x0);
+
+ // RG_FG_AUXADC_R[10:10] = 0x1 => Ricky
+ PMIC_DRV_SetData(0xCBC , 0x400 , 0x400 , 0x0);
+
+ // FG_SLP_CUR_TH[15:0] = 0x24 => Ricky
+ PMIC_DRV_SetData(0xCC0 , 0xFFFF , 0x24 , 0x0);
+
+ // FG_SLP_TIME[7:0] = 0x14 => Ricky
+ PMIC_DRV_SetData(0xCC2 , 0xFF , 0x14 , 0x0);
+
+ // FG_DET_TIME[15:8] = 0xFF => Ricky
+ PMIC_DRV_SetData(0xCC4 , 0xFF00 , 0xFF00 , 0x0);
+
+}
\ No newline at end of file
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6331_32.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6331_32.c
new file mode 100644
index 0000000..5b3fe70
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6331_32.c
@@ -0,0 +1,1373 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6331_32.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6331/6332
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+
+#if defined(PMIC_6331_REG_API) || defined(PMIC_6332_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+#define __MD1__
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define BANKS_NUM 1
+#define PMIC6331_MAX_REG_NUM 0x0800 // 0x0001~0x07FF
+#define PMIC6332_MAX_REG_NUM 0x0800 // 0x0001~0x07FF
+#define GPIO_MAX_REG_NUM 0x0100 // 0x0001~0x00FF
+//#define PMIC_MAX_REG_NUM 0x40FF // Register BUCK1, Register ANALDO, Register DIGLDO (0x0470)
+
+#define MT6331_HW_CID_E1 0x1031
+#define MT6331_HW_CID_E2 0x2031
+#define MT6331_HW_CID_E3 0x3031
+#define MT6331_SW_CID_E1 0x1031
+#define MT6331_SW_CID_E2 0x2031
+#define MT6331_SW_CID_E3 0x3031
+#define MT6332_HW_CID_E1 0x1032
+#define MT6332_HW_CID_E2 0x2032
+#define MT6332_HW_CID_E3 0x3032
+#define MT6332_SW_CID_E1 0x1032
+#define MT6332_SW_CID_E2 0x2032
+#define MT6332_SW_CID_E3 0x3032
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+extern kal_bool pmic6331_reg_write(kal_uint16 reg, kal_uint16 val);
+extern kal_bool pmic6331_reg_read(kal_uint16 reg, kal_uint16 *pVal);
+extern kal_bool pmic6332_reg_write(kal_uint16 reg, kal_uint16 val);
+extern kal_bool pmic6332_reg_read(kal_uint16 reg, kal_uint16 *pVal);
+
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+kal_uint8 pmic6331_hw_version;
+kal_uint8 pmic6331_sw_version;
+kal_uint8 pmic6332_hw_version;
+kal_uint8 pmic6332_sw_version;
+kal_uint16 pmic6331_reg[PMIC6331_MAX_REG_NUM];
+kal_uint16 pmic6332_reg[PMIC6332_MAX_REG_NUM];
+kal_uint16 pmic6331_gpio_reg[GPIO_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+const PMIC_FLAG_TABLE_ENTRY pmic6331_flags_table[] =
+{
+ {MT6331_HWCID, MT6331_HWCID_MASK, MT6331_HWCID_SHIFT, },
+ {MT6331_SWCID, MT6331_SWCID_MASK, MT6331_SWCID_SHIFT, },
+ {MT6331_ANALDO_CON2, MT6331_RG_VTCXO2_LP_CTRL_MASK, MT6331_RG_VTCXO2_LP_CTRL_SHIFT, },
+ {MT6331_ANALDO_CON2, MT6331_RG_VTCXO2_LP_SET_MASK, MT6331_RG_VTCXO2_LP_SET_SHIFT, },
+ {MT6331_ANALDO_CON2, MT6331_RG_VTCXO2_EN_MASK, MT6331_RG_VTCXO2_EN_SHIFT, },
+ {MT6331_ANALDO_CON2, MT6331_RG_VTCXO2_ON_CTRL_MASK, MT6331_RG_VTCXO2_ON_CTRL_SHIFT, },
+ {MT6331_ANALDO_CON2, MT6331_RG_VTCXO2_SRCLK_EN_SEL_MASK, MT6331_RG_VTCXO2_SRCLK_EN_SEL_SHIFT, },
+ {MT6331_SYSLDO_CON5, MT6331_RG_VMIPI_EN_MASK, MT6331_RG_VMIPI_EN_SHIFT, },
+ {MT6331_SYSLDO_CON5, MT6331_RG_VMIPI_ON_CTRL_MASK, MT6331_RG_VMIPI_ON_CTRL_SHIFT, },
+ {MT6331_SYSLDO_CON5, MT6331_RG_VMIPI_SRCLK_EN_SEL_MASK, MT6331_RG_VMIPI_SRCLK_EN_SEL_SHIFT, },
+ {MT6331_DIGLDO_CON8, MT6331_RG_VSIM1_LP_CTRL_MASK, MT6331_RG_VSIM1_LP_CTRL_SHIFT, },
+ {MT6331_DIGLDO_CON8, MT6331_RG_VSIM1_LP_MODE_SET_MASK, MT6331_RG_VSIM1_LP_MODE_SET_SHIFT, },
+ {MT6331_DIGLDO_CON8, MT6331_RG_VSIM1_EN_MASK, MT6331_RG_VSIM1_EN_SHIFT, },
+ {MT6331_DIGLDO_CON9, MT6331_RG_VSIM2_LP_CTRL_MASK, MT6331_RG_VSIM2_LP_CTRL_SHIFT, },
+ {MT6331_DIGLDO_CON9, MT6331_RG_VSIM2_LP_MODE_SET_MASK, MT6331_RG_VSIM2_LP_MODE_SET_SHIFT, },
+ {MT6331_DIGLDO_CON9, MT6331_RG_VSIM2_EN_MASK, MT6331_RG_VSIM2_EN_SHIFT, },
+ {MT6331_DIGLDO_CON21, MT6331_RG_VSIM1_VOSEL_MASK, MT6331_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6331_DIGLDO_CON22, MT6331_RG_VSIM2_VOSEL_MASK, MT6331_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6331_AUXADC_ADC15, MT6331_AUXADC_ADC_OUT_CH7_BY_MD_MASK, MT6331_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6331_AUXADC_ADC15, MT6331_AUXADC_ADC_RDY_CH7_BY_MD_MASK, MT6331_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6331_AUXADC_ADC17, MT6331_AUXADC_ADC_OUT_CH4_BY_MD_MASK, MT6331_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT, },
+ {MT6331_AUXADC_ADC17, MT6331_AUXADC_ADC_RDY_CH4_BY_MD_MASK, MT6331_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT, },
+ {MT6331_AUXADC_RQST1_SET, MT6331_AUXADC_RQST1_SET_MASK, MT6331_AUXADC_RQST1_SET_SHIFT, },
+ {MT6331_AUXADC_RQST1_CLR, MT6331_AUXADC_RQST1_CLR_MASK, MT6331_AUXADC_RQST1_CLR_SHIFT, },
+};
+
+const PMIC_FLAG_TABLE_ENTRY pmic6332_flags_table[] =
+{
+ {MT6332_HWCID, MT6332_HWCID_MASK, MT6332_HWCID_SHIFT, },
+ {MT6332_SWCID, MT6332_SWCID_MASK, MT6332_SWCID_SHIFT, },
+ {MT6332_TOP_CKPDN_CON2, MT6332_TOP_CKPDN_CON2_RSV_MASK, MT6332_TOP_CKPDN_CON2_RSV_SHIFT, },
+ {MT6332_VRF1_CON4, MT6332_RG_VRF1_MODESET_MASK, MT6332_RG_VRF1_MODESET_SHIFT, },
+ {MT6332_VRF1_CON7, MT6332_VRF1_EN_CTRL_MASK, MT6332_VRF1_EN_CTRL_SHIFT, },
+ {MT6332_VRF1_CON7, MT6332_VRF1_VOSEL_CTRL_MASK, MT6332_VRF1_VOSEL_CTRL_SHIFT, },
+ {MT6332_VRF1_CON8, MT6332_VRF1_EN_SEL_MASK, MT6332_VRF1_EN_SEL_SHIFT, },
+ {MT6332_VRF1_CON8, MT6332_VRF1_VOSEL_SEL_MASK, MT6332_VRF1_VOSEL_SEL_SHIFT, },
+ {MT6332_VRF1_CON9, MT6332_VRF1_EN_MASK, MT6332_VRF1_EN_SHIFT, },
+ {MT6332_VRF1_CON11, MT6332_VRF1_VOSEL_MASK, MT6332_VRF1_VOSEL_SHIFT, },
+ {MT6332_VRF1_CON12, MT6332_VRF1_VOSEL_ON_MASK, MT6332_VRF1_VOSEL_ON_SHIFT, },
+ {MT6332_VRF1_CON13, MT6332_VRF1_VOSEL_SLEEP_MASK, MT6332_VRF1_VOSEL_SLEEP_SHIFT, },
+ {MT6332_VRF1_CON18, MT6332_VRF1_VSLEEP_EN_MASK, MT6332_VRF1_VSLEEP_EN_SHIFT, },
+ {MT6332_VRF2_CON4, MT6332_RG_VRF2_MODESET_MASK, MT6332_RG_VRF2_MODESET_SHIFT, },
+ {MT6332_VRF2_CON7, MT6332_VRF2_EN_CTRL_MASK, MT6332_VRF2_EN_CTRL_SHIFT, },
+ {MT6332_VRF2_CON7, MT6332_VRF2_VOSEL_CTRL_MASK, MT6332_VRF2_VOSEL_CTRL_SHIFT, },
+ {MT6332_VRF2_CON8, MT6332_VRF2_EN_SEL_MASK, MT6332_VRF2_EN_SEL_SHIFT, },
+ {MT6332_VRF2_CON8, MT6332_VRF2_VOSEL_SEL_MASK, MT6332_VRF2_VOSEL_SEL_SHIFT, },
+ {MT6332_VRF2_CON9, MT6332_VRF2_EN_MASK, MT6332_VRF2_EN_SHIFT, },
+ {MT6332_VRF2_CON11, MT6332_VRF2_VOSEL_MASK, MT6332_VRF2_VOSEL_SHIFT, },
+ {MT6332_VRF2_CON12, MT6332_VRF2_VOSEL_ON_MASK, MT6332_VRF2_VOSEL_ON_SHIFT, },
+ {MT6332_VRF2_CON13, MT6332_VRF2_VOSEL_SLEEP_MASK, MT6332_VRF2_VOSEL_SLEEP_SHIFT, },
+ {MT6332_VRF2_CON18, MT6332_VRF2_VSLEEP_EN_MASK, MT6332_VRF2_VSLEEP_EN_SHIFT, },
+ {MT6332_VPA_CON4, MT6332_RG_VPA_MODESET_MASK, MT6332_RG_VPA_MODESET_SHIFT, },
+ {MT6332_VPA_CON9, MT6332_VPA_EN_MASK, MT6332_VPA_EN_SHIFT, },
+ {MT6332_VPA_CON11, MT6332_VPA_VOSEL_MASK, MT6332_VPA_VOSEL_SHIFT, },
+};
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+
+// Write Whole Bytes
+void dcl_pmic6331_32_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ if(addr <= PMIC6331_MAX_REG_NUM)
+ {
+ pmic6331_reg[addr] = val;
+ }
+
+ if(addr >= MT6332_PMIC_REG_BASE && addr <= (MT6332_PMIC_REG_BASE + PMIC6332_MAX_REG_NUM))
+ {
+ pmic6332_reg[addr - MT6332_PMIC_REG_BASE] = val;
+ }
+
+#if defined(__MD1__)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+#else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
+#endif
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+// Write register field
+void dcl_pmic6331_field_write(PMIC6331_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6331_flags_table;
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic6331_reg[pTable[flag].offset];
+
+ pmic6331_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic6331_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+#if defined(__MD1__)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6331_reg[pTable[flag].offset], 0x00);
+#else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6331_reg[pTable[flag].offset], 0x00);
+#endif
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic6331_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+void dcl_pmic6332_field_write(PMIC6332_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6332_flags_table;
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic6332_reg[pTable[flag].offset];
+
+ pmic6332_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic6332_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+#if defined(__MD1__)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6332_reg[pTable[flag].offset], 0x00);
+#else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6332_reg[pTable[flag].offset], 0x00);
+#endif
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic6332_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+// Write register field for GPIO
+void dcl_pmic6331_gpio_field_write(PMIC6331_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6331_flags_table;
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic6331_gpio_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ pmic6331_gpio_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic6331_gpio_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+#if defined(__MD1__)
+ // DrvPWRAP_WACS0(PMIC_WRAP_WRITE, GPIO_BASE + pTable[flag].offset, pmic6331_gpio_reg[pTable[flag].offset], 0x00);
+#else
+ // DrvPWRAP_WACS1(PMIC_WRAP_WRITE, GPIO_BASE + pTable[flag].offset, pmic6331_gpio_reg[pTable[flag].offset], 0x00);
+#endif
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ // pmic_reg_log.reg_addr = GPIO_BASE + pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic6331_gpio_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic6331_32_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ kal_uint32 savedMask = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+#if defined(__MD1__)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+#else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+#endif
+
+ if(addr <= PMIC6331_MAX_REG_NUM)
+ {
+ pmic6331_reg[addr] = reg_temp;
+ }
+
+ if(addr >= MT6332_PMIC_REG_BASE && addr <= (MT6332_PMIC_REG_BASE + PMIC6332_MAX_REG_NUM))
+ {
+ pmic6332_reg[addr - MT6332_PMIC_REG_BASE] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic6331_field_read(PMIC6331_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6331_flags_table;
+ kal_uint32 savedMask = 0;
+ DCL_UINT16 reg_return = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+#if defined(__MD1__)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6331_reg[pTable[flag].offset]);
+#else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6331_reg[pTable[flag].offset]);
+#endif
+
+ reg_return = ((pmic6331_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_return;
+}
+
+DCL_UINT16 dcl_pmic6332_field_read(PMIC6332_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6332_flags_table;
+ kal_uint32 savedMask = 0;
+ DCL_UINT16 reg_return = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+#if defined(__MD1__)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6332_reg[pTable[flag].offset]);
+#else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6332_reg[pTable[flag].offset]);
+#endif
+
+ reg_return = ((pmic6332_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic6331_32_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic6331_32_byte_write(reg, val);
+}
+
+kal_uint16 pmic6331_32_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic6331_32_byte_return(reg);
+}
+
+PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6331_get_ECO_version(void)
+{
+ return pmic6331_hw_version;
+}
+
+PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6332_get_ECO_version(void)
+{
+ return pmic6332_hw_version;
+}
+
+/*
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_750000_V, PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_00_950000_V, PMU_VOLT_01_000000_V, PMU_VOLT_01_050000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_150000_V, PMU_VOLT_01_200000_V, PMU_VOLT_01_250000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_350000_V, PMU_VOLT_01_400000_V, PMU_VOLT_01_450000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_550000_V, PMU_VOLT_01_600000_V, PMU_VOLT_01_650000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_750000_V, PMU_VOLT_01_800000_V, PMU_VOLT_01_850000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_01_950000_V, PMU_VOLT_02_000000_V, PMU_VOLT_02_050000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_150000_V, PMU_VOLT_02_200000_V, PMU_VOLT_02_250000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_350000_V, PMU_VOLT_02_400000_V, PMU_VOLT_02_450000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_550000_V, PMU_VOLT_02_600000_V, PMU_VOLT_02_650000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_750000_V, PMU_VOLT_02_800000_V, PMU_VOLT_02_850000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_02_950000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_050000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_150000_V, PMU_VOLT_03_200000_V, PMU_VOLT_03_250000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_350000_V, PMU_VOLT_03_400000_V, PMU_VOLT_03_450000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_550000_V, PMU_VOLT_03_600000_V, PMU_VOLT_03_650000_V,
+
+};
+*/
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+};
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC6331_32_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF1:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF2:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VMIPI_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM1_LP_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM2_LP_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_SEL *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF1_VSLEEP_EN, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM1_LP_MODE_SET, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM2_LP_MODE_SET, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6332_field_write(MT6332_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_ON_CTRL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL *pLdoBuckCtrl=&(data->rPMULdoBuckSetOnCtrl);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMIPI:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6331_field_write(MT6331_RG_VMIPI_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic6332_field_write(MT6332_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF1:
+ {
+ dcl_pmic6332_field_write(MT6332_RG_VRF1_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF2:
+ {
+ dcl_pmic6332_field_write(MT6332_RG_VRF2_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_EN_CTRL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnCtrl);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF1:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF1_EN_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF2:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF2_EN_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_EN_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF1:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF1_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF2:
+ {
+ dcl_pmic6332_field_write(MT6332_VRF2_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SRCLK_EN_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetSrclkEnSel);
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF1:
+ {
+ dcl_pmic6331_field_write(MT6331_RG_VMIPI_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF1_SET_MODESET_CKPDN_SET:
+ {
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET *pVrf1Ctrl = &(data->rPMUVrf1SetModesetCkpdnSet);
+ // Only control [10:7]
+ dcl_pmic6331_32_byte_write(MT6332_TOP_CKPDN_CON2_SET , ((pVrf1Ctrl->regval & 0xF) << 7));
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF1_SET_MODESET_CKPDN_CLR:
+ {
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR *pVrf1Ctrl = &(data->rPMUVrf1SetModesetCkpdnClr);
+ // Only control [10:7]
+ dcl_pmic6331_32_byte_write(MT6332_TOP_CKPDN_CON2_CLR , ((pVrf1Ctrl->regval & 0xF) << 7));
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF1_GET_MODESET_CKPDN:
+ {
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN *pVrf1Ctrl = &(data->rPMUVrf1GetModesetCkpdn);
+ pVrf1Ctrl->regval = (dcl_pmic6331_32_byte_return(MT6332_TOP_CKPDN_CON2) & 0x0780) >> 7;
+ return_val = STATUS_OK;
+ }
+ break;
+
+ /*
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+
+ dcl_pmic6331_32_byte_write(TOP_CKPDN1_SET, (0x1 << RG_CLKSQ_EN_AUX_MD_SHIFT));
+ dcl_pmic6331_32_byte_write(AUXADC_CON27, (0x0 << 15));
+ dcl_pmic6331_field_write(RG_MD_RQST, 0x0); // Need Set 0 first
+
+ dcl_pmic6331_field_write(RG_MD_RQST, pAdcCtrl->enable);
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+#if defined(FPGA_CTP)
+ dbg_print("[PMIC_WRAP_MD] ADC Data Status = %x\n", dcl_pmic6331_field_read(RG_ADC_RDY_MD));
+#endif
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic6331_field_read(RG_ADC_RDY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic6331_field_read(RG_ADC_OUT_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ dcl_pmic6331_field_write(RG_MD_RQST, 0x0);
+ dcl_pmic6331_32_byte_write(TOP_CKPDN1_CLR, (0x1 << RG_CLKSQ_EN_AUX_MD_SHIFT));
+ dcl_pmic6331_32_byte_write(AUXADC_CON27, (0x1 << 15));
+
+ return_val = STATUS_OK;
+ }
+ break;
+ */
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+ pmic6331_32_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic6331_32_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+
+ return return_val;
+
+}
+
+extern void dcl_pmic6331_modem_only_init(void);
+extern void dcl_pmic6332_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+
+
+void dcl_pmic6331_internal_init(void)
+{
+}
+
+void dcl_pmic6332_internal_init(void)
+{
+}
+
+void dcl_pmic6331_32_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC6331_32_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic6331_hw_version = PMIC_ECO_E1;
+ pmic6331_sw_version = PMIC_ECO_E1;
+ pmic6332_hw_version = PMIC_ECO_E1;
+ pmic6332_sw_version = PMIC_ECO_E1;
+
+ // Get MT6331/MT6332 ECO version
+ {
+ kal_uint16 pmic6331_hw_eco_version = 0;
+ kal_uint16 pmic6331_sw_eco_version = 0;
+ kal_uint16 pmic6332_hw_eco_version = 0;
+ kal_uint16 pmic6332_sw_eco_version = 0;
+ pmic6331_hw_eco_version = dcl_pmic6331_32_byte_return(MT6331_HWCID);
+ pmic6332_hw_eco_version = dcl_pmic6331_32_byte_return(MT6332_HWCID);
+ pmic6331_sw_eco_version = dcl_pmic6331_32_byte_return(MT6331_SWCID);
+ pmic6332_sw_eco_version = dcl_pmic6331_32_byte_return(MT6332_SWCID);
+
+ if (pmic6331_hw_eco_version == MT6331_HW_CID_E1)
+ {
+ pmic6331_hw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6331_hw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6331_sw_eco_version == MT6331_SW_CID_E1)
+ {
+ pmic6331_sw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6331_sw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6332_hw_eco_version == MT6332_SW_CID_E1)
+ {
+ pmic6332_hw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6332_hw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6332_sw_eco_version == MT6331_SW_CID_E1)
+ {
+ pmic6332_sw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6332_sw_version = PMIC_ECO_E2;
+ }
+
+ }
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+ dcl_pmic6331_modem_only_init();
+ dcl_pmic6332_modem_only_init();
+#endif
+ dcl_pmic6331_internal_init();
+ dcl_pmic6332_internal_init();
+
+ // pmic6331_customization_init();
+ // pmic6332_customization_init();
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+}
+
+DCL_BOOL dcl_pmic_init_done_query(void)
+{
+ if(pmic_init_done == DCL_TRUE)
+ {
+ return DCL_TRUE;
+ }
+ else
+ {
+ return DCL_FALSE;
+ }
+}
+
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic6331_32_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic6331_32_byte_write(pmic_addr, value);
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i;
+ for (i = 0; i < PMIC6331_MAX_REG_NUM; i += 2){
+ pmic6331_reg[i] = dcl_pmic6331_32_byte_return(i);
+ }
+ for (i = MT6332_PMIC_REG_BASE; i < (MT6332_PMIC_REG_BASE + PMIC6332_MAX_REG_NUM); i += 2){
+ pmic6332_reg[i - MT6332_PMIC_REG_BASE] = dcl_pmic6331_32_byte_return(i);
+ }
+}
+
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VPA_SW;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VPA_SW;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VPA_SW;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VRF1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VRF1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VRF1;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.regval = 0x7; // (0x0~0xF)
+DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.regval = 0x7; // (0x0~0xF)
+DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+// val.regval will be your request value ( no need do any shift)
+DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VRF1;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VSIM1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VSIM2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VSIM1;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VSIM2;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6331_REG_API) || defined(PMIC_6332_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6331_32_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6331_32_init.c
new file mode 100644
index 0000000..c978e52
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6331_32_init.c
@@ -0,0 +1 @@
+/* Empty File */
\ No newline at end of file
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6331_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6331_init.c
new file mode 100644
index 0000000..56ac1a7
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6331_init.c
@@ -0,0 +1,230 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6331_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6331
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+static void PMIC_DRV_SetData(DCL_UINT32 addr, DCL_UINT32 bitmask, DCL_UINT16 value, DCL_UINT32 bank)
+{
+ DCL_UINT32 temp;
+ addr |= (bank << 31);
+ temp = (~(bitmask)) & DRV_Read_PMIC_Data(addr);
+ temp |= ((value) & (bitmask));
+ DRV_Write_PMIC_Data(addr,temp);
+}
+
+// MT6331 ECO_E1
+void dcl_pmic6331_modem_only_init(void)
+{
+ // RG_EN_DRVSEL[4:4] = 0x1
+ PMIC_DRV_SetData(0x4 , 0x10 , 0x10 , 0x0);
+
+ // RG_RSTB_DRV_SEL[5:5] = 0x1
+ PMIC_DRV_SetData(0x4 , 0x20 , 0x20 , 0x0);
+
+ // VDVFS11_PG_H2L_EN[0:0] = 0x1
+ PMIC_DRV_SetData(0xC , 0x1 , 0x1 , 0x0);
+
+ // VDVFS12_PG_H2L_EN[1:1] = 0x1
+ PMIC_DRV_SetData(0xC , 0x2 , 0x2 , 0x0);
+
+ // VDVFS13_PG_H2L_EN[2:2] = 0x1
+ PMIC_DRV_SetData(0xC , 0x4 , 0x4 , 0x0);
+
+ // VDVFS14_PG_H2L_EN[3:3] = 0x1
+ PMIC_DRV_SetData(0xC , 0x8 , 0x8 , 0x0);
+
+ // VCORE1_PG_H2L_EN[4:4] = 0x1
+ PMIC_DRV_SetData(0xC , 0x10 , 0x10 , 0x0);
+
+ // VCORE2_PG_H2L_EN[5:5] = 0x1
+ PMIC_DRV_SetData(0xC , 0x20 , 0x20 , 0x0);
+
+ // VGPU_PG_H2L_EN[6:6] = 0x1
+ PMIC_DRV_SetData(0xC , 0x40 , 0x40 , 0x0);
+
+ // VIO18_PG_H2L_EN[7:7] = 0x1
+ PMIC_DRV_SetData(0xC , 0x80 , 0x80 , 0x0);
+
+ // VAUD32_PG_H2L_EN[8:8] = 0x1
+ PMIC_DRV_SetData(0xC , 0x100 , 0x100 , 0x0);
+
+ // VTCXO1_PG_H2L_EN[9:9] = 0x1
+ PMIC_DRV_SetData(0xC , 0x200 , 0x200 , 0x0);
+
+ // VUSB_PG_H2L_EN[10:10] = 0x1
+ PMIC_DRV_SetData(0xC , 0x400 , 0x400 , 0x0);
+
+ // VSRAM_DVFS1_PG_H2L_EN[11:11] = 0x1
+ PMIC_DRV_SetData(0xC , 0x800 , 0x800 , 0x0);
+
+ // VIO28_PG_H2L_EN[12:12] = 0x1
+ PMIC_DRV_SetData(0xC , 0x1000 , 0x1000 , 0x0);
+
+ // UVLO_L2H_DEB_EN[5:5] = 0x1
+ PMIC_DRV_SetData(0x10 , 0x20 , 0x20 , 0x0);
+
+ // STRUP_PWROFF_SEQ_EN[0:0] = 0x1
+ PMIC_DRV_SetData(0x16 , 0x1 , 0x1 , 0x0);
+
+ // STRUP_PWROFF_PREOFF_EN[1:1] = 0x1
+ PMIC_DRV_SetData(0x16 , 0x2 , 0x2 , 0x0);
+
+ // RG_SRCLKEN_IN1_HW_MODE[4:4] = 0x1
+ PMIC_DRV_SetData(0x106 , 0x10 , 0x10 , 0x0);
+
+ // RG_SRCLKEN_IN2_HW_MODE[5:5] = 0x1
+ PMIC_DRV_SetData(0x106 , 0x20 , 0x20 , 0x0);
+
+ // RG_OSC_SEL_HW_MODE[6:6] = 0x1
+ PMIC_DRV_SetData(0x106 , 0x40 , 0x40 , 0x0);
+
+ // RG_SMT_WDTRSTB_IN[0:0] = 0x1
+ PMIC_DRV_SetData(0x124 , 0x1 , 0x1 , 0x0);
+
+ // RG_SMT_SRCLKEN_IN1[2:2] = 0x1
+ PMIC_DRV_SetData(0x124 , 0x4 , 0x4 , 0x0);
+
+ // RG_SMT_SRCLKEN_IN2[3:3] = 0x1
+ PMIC_DRV_SetData(0x124 , 0x8 , 0x8 , 0x0);
+
+ // RG_RTC_75K_CK_PDN[2:2] = 0x1
+ PMIC_DRV_SetData(0x13E , 0x4 , 0x4 , 0x0);
+
+ // RG_RTCDET_CK_PDN[3:3] = 0x1
+ PMIC_DRV_SetData(0x13E , 0x8 , 0x8 , 0x0);
+
+ // RG_STRUP_AUXADC_CK_PDN[6:6] = 0x1
+ PMIC_DRV_SetData(0x144 , 0x40 , 0x40 , 0x0);
+
+ // RG_75K_32K_SEL[10:10] = 0x1
+ PMIC_DRV_SetData(0x14A , 0x400 , 0x400 , 0x0);
+
+ // VDVFS11_VOSEL[6:0] = 0x44
+ PMIC_DRV_SetData(0x24C , 0x7F , 0x44 , 0x0);
+
+ // VDVFS11_VOSEL_ON[6:0] = 0x44
+ PMIC_DRV_SetData(0x24E , 0x7F , 0x44 , 0x0);
+
+ // VCORE2_VOSEL[6:0] = 0x44
+ PMIC_DRV_SetData(0x36A , 0x7F , 0x44 , 0x0);
+
+ // VCORE2_VOSEL_ON[6:0] = 0x44
+ PMIC_DRV_SetData(0x36C , 0x7F , 0x44 , 0x0);
+
+ // VCORE2_VSLEEP_EN[8:8] = 0x1
+ PMIC_DRV_SetData(0x378 , 0x100 , 0x100 , 0x0);
+
+ // RG_VSRAM_DVFS1_VOSEL[15:9] = 0x44
+ PMIC_DRV_SetData(0x534 , 0xFE00 , 0x8800 , 0x0);
+
+ // AUXADC_TRIM_CH0_SEL[1:0] = 0x1
+ PMIC_DRV_SetData(0x73E , 0x3 , 0x1 , 0x0);
+
+ // AUXADC_TRIM_CH1_SEL[3:2] = 0x1
+ PMIC_DRV_SetData(0x73E , 0xC , 0x4 , 0x0);
+
+ // AUXADC_TRIM_CH2_SEL[5:4] = 0x1
+ PMIC_DRV_SetData(0x73E , 0x30 , 0x10 , 0x0);
+
+ // AUXADC_TRIM_CH3_SEL[7:6] = 0x1
+ PMIC_DRV_SetData(0x73E , 0xC0 , 0x40 , 0x0);
+
+ // AUXADC_TRIM_CH4_SEL[9:8] = 0x1
+ PMIC_DRV_SetData(0x73E , 0x300 , 0x100 , 0x0);
+
+ // AUXADC_TRIM_CH5_SEL[11:10] = 0x1
+ PMIC_DRV_SetData(0x73E , 0xC00 , 0x400 , 0x0);
+
+ // AUXADC_TRIM_CH6_SEL[13:12] = 0x1
+ PMIC_DRV_SetData(0x73E , 0x3000 , 0x1000 , 0x0);
+
+ // AUXADC_TRIM_CH7_SEL[15:14] = 0x2
+ PMIC_DRV_SetData(0x73E , 0xC000 , 0x8000 , 0x0);
+
+ // AUXADC_TRIM_CH8_SEL[1:0] = 0x1
+ PMIC_DRV_SetData(0x740 , 0x3 , 0x1 , 0x0);
+
+ // AUXADC_TRIM_CH9_SEL[3:2] = 0x1
+ PMIC_DRV_SetData(0x740 , 0xC , 0x4 , 0x0);
+
+ // AUXADC_TRIM_CH10_SEL[5:4] = 0x1
+ PMIC_DRV_SetData(0x740 , 0x30 , 0x10 , 0x0);
+
+ // AUXADC_TRIM_CH11_SEL[7:6] = 0x1
+ PMIC_DRV_SetData(0x740 , 0xC0 , 0x40 , 0x0);
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6332_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6332_init.c
new file mode 100644
index 0000000..4fa96a8
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6332_init.c
@@ -0,0 +1,203 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6332_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6332
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+static void PMIC_DRV_SetData(DCL_UINT32 addr, DCL_UINT32 bitmask, DCL_UINT16 value, DCL_UINT32 bank)
+{
+ DCL_UINT32 temp;
+ addr |= (bank << 31);
+ temp = (~(bitmask)) & DRV_Read_PMIC_Data(addr);
+ temp |= ((value) & (bitmask));
+ DRV_Write_PMIC_Data(addr,temp);
+}
+
+// MT6332 ECO_E1
+void dcl_pmic6332_modem_only_init(void)
+{
+ // RG_SRCLKEN_IN1_HW_MODE[4:4] = 0x1
+ PMIC_DRV_SetData(0x8004 , 0x10 , 0x10 , 0x0);
+
+ // RG_SRCLKEN_IN2_HW_MODE[5:5] = 0x1
+ PMIC_DRV_SetData(0x8004 , 0x20 , 0x20 , 0x0);
+
+ // RG_OSC_SEL_HW_MODE[6:6] = 0x1
+ PMIC_DRV_SetData(0x8004 , 0x40 , 0x40 , 0x0);
+
+ // RG_SMT_WDTRSTB_IN[0:0] = 0x1
+ PMIC_DRV_SetData(0x801A , 0x1 , 0x1 , 0x0);
+
+ // RG_AUXADC_12M_CK_PDN[9:9] = 0x1
+ PMIC_DRV_SetData(0x8094 , 0x200 , 0x200 , 0x0);
+
+ // VDRAM_VSLEEP_EN[8:8] = 0x1
+ PMIC_DRV_SetData(0x845C , 0x100 , 0x100 , 0x0);
+
+ // VSRAM_DVFS2_VSLEEP_EN[8:8] = 0x0
+ PMIC_DRV_SetData(0x8498 , 0x100 , 0x0 , 0x0);
+
+ // VRF1_EN_CTRL[0:0] = 0x1 => VRF1 Follow SRCLKEN1(A0)
+ PMIC_DRV_SetData(0x84AA , 0x1 , 0x1 , 0x0);
+
+ // VRF1_VOSEL[6:0] = 0x53 => VRF=1.828V
+ PMIC_DRV_SetData(0x84B2 , 0x7F , 0x53 , 0x0);
+
+ // VRF1_VOSEL_ON[6:0] = 0x53 => VRF=1.828V
+ PMIC_DRV_SetData(0x84B4 , 0x7F , 0x53 , 0x0);
+
+ // VRF2_VOSEL[6:0] = 0x53 => VRF=1.828V
+ PMIC_DRV_SetData(0x84DE , 0x7F , 0x53 , 0x0);
+
+ // VRF2_VOSEL_ON[6:0] = 0x53 => VRF=1.828V
+ PMIC_DRV_SetData(0x84E0 , 0x7F , 0x53 , 0x0);
+
+ // VPA_DVS_TRANS_CTRL[5:4] = 0x3 => DVS performance tuning
+ PMIC_DRV_SetData(0x8526 , 0x30 , 0x30 , 0x0);
+
+ // AUXADC_TRIM_CH2_SEL[5:4] = 0x1
+ PMIC_DRV_SetData(0x886E , 0x30 , 0x10 , 0x0);
+
+ // AUXADC_TRIM_CH3_SEL[7:6] = 0x1
+ PMIC_DRV_SetData(0x886E , 0xC0 , 0x40 , 0x0);
+
+ // AUXADC_TRIM_CH4_SEL[9:8] = 0x1
+ PMIC_DRV_SetData(0x886E , 0x300 , 0x100 , 0x0);
+
+ // AUXADC_TRIM_CH5_SEL[11:10] = 0x1
+ PMIC_DRV_SetData(0x886E , 0xC00 , 0x400 , 0x0);
+
+ // AUXADC_TRIM_CH6_SEL[13:12] = 0x1
+ PMIC_DRV_SetData(0x886E , 0x3000 , 0x1000 , 0x0);
+
+ // AUXADC_TRIM_CH7_SEL[15:14] = 0x2
+ PMIC_DRV_SetData(0x886E , 0xC000 , 0x8000 , 0x0);
+
+ // AUXADC_TRIM_CH8_SEL[1:0] = 0x1
+ PMIC_DRV_SetData(0x8870 , 0x3 , 0x1 , 0x0);
+
+ // AUXADC_TRIM_CH9_SEL[3:2] = 0x1
+ PMIC_DRV_SetData(0x8870 , 0xC , 0x4 , 0x0);
+
+ // AUXADC_TRIM_CH10_SEL[5:4] = 0x1
+ PMIC_DRV_SetData(0x8870 , 0x30 , 0x10 , 0x0);
+
+ // AUXADC_TRIM_CH11_SEL[7:6] = 0x1
+ PMIC_DRV_SetData(0x8870 , 0xC0 , 0x40 , 0x0);
+
+ // RG_EN_DRVSEL[4:4] = 0x1
+ PMIC_DRV_SetData(0x8C0A , 0x10 , 0x10 , 0x0);
+
+ // RG_RSTB_DRV_SEL[5:5] = 0x1
+ PMIC_DRV_SetData(0x8C0A , 0x20 , 0x20 , 0x0);
+
+ // VSBST_PG_H2L_EN[8:8] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x100 , 0x100 , 0x0);
+
+ // VUSB33_PG_H2L_EN[9:9] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x200 , 0x200 , 0x0);
+
+ // VSRAM_DVFS2_PG_H2L_EN[10:10] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x400 , 0x400 , 0x0);
+
+ // VDRAM_PG_H2L_EN[11:11] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x800 , 0x800 , 0x0);
+
+ // VDVFS2_PG_H2L_EN[12:12] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x1000 , 0x1000 , 0x0);
+
+ // EXT_PMIC_EN_INT_PG_H2L_EN[13:13] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x2000 , 0x2000 , 0x0);
+
+ // VAUXB32_PG_H2L_EN[14:14] = 0x1
+ PMIC_DRV_SetData(0x8C12 , 0x4000 , 0x4000 , 0x0);
+
+ // STRUP_CON8_RSV0[14:8] = 0x1
+ PMIC_DRV_SetData(0x8C16 , 0x7F00 , 0x100 , 0x0);
+
+ // STRUP_AUXADC_RSTB_SEL[7:7] = 0x1
+ PMIC_DRV_SetData(0x8C18 , 0x80 , 0x80 , 0x0);
+
+ // STRUP_PWROFF_SEQ_EN[0:0] = 0x1
+ PMIC_DRV_SetData(0x8C1A , 0x1 , 0x1 , 0x0);
+
+ // STRUP_PWROFF_PREOFF_EN[1:1] = 0x1
+ PMIC_DRV_SetData(0x8C1A , 0x2 , 0x2 , 0x0);
+
+ // RG_VBIF28_ON_CTRL[11:11] = 0x1
+ PMIC_DRV_SetData(0x8CB8 , 0x800 , 0x800 , 0x0);
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6335_37.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6335_37.c
new file mode 100644
index 0000000..4e12d1d
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6335_37.c
@@ -0,0 +1,2625 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6335_37.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6335/6337
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+
+#if defined(PMIC_6335_REG_API) || defined(PMIC_6337_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+
+#define PMIC6335_MAX_REG_NUM 0x2C30 // 0x0000~0x2C2E
+#define PMIC6337_MAX_REG_NUM 0x1E10 // 0x8000~0x9E00
+
+
+#define MT6335_HW_CID_E1 0x1035
+#define MT6335_HW_CID_E2 0x2035
+#define MT6335_HW_CID_E3 0x3035
+#define MT6335_SW_CID_E1 0x1035
+#define MT6335_SW_CID_E2 0x2035
+#define MT6335_SW_CID_E3 0x3035
+#define MT6337_HW_CID_E1 0x1037
+#define MT6337_HW_CID_E2 0x2037
+#define MT6337_HW_CID_E3 0x3037
+#define MT6337_SW_CID_E1 0x1037
+#define MT6337_SW_CID_E2 0x2037
+#define MT6337_SW_CID_E3 0x3037
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+extern kal_bool pmic6335_reg_write(kal_uint16 reg, kal_uint16 val);
+extern kal_bool pmic6335_reg_read(kal_uint16 reg, kal_uint16 *pVal);
+extern kal_bool pmic6337_reg_write(kal_uint16 reg, kal_uint16 val);
+extern kal_bool pmic6337_reg_read(kal_uint16 reg, kal_uint16 *pVal);
+
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic6335_hw_version;
+kal_uint8 pmic6335_sw_version;
+kal_uint8 pmic6337_hw_version;
+kal_uint8 pmic6337_sw_version;
+kal_uint16 pmic6335_reg[PMIC6335_MAX_REG_NUM];
+kal_uint16 pmic6337_reg[PMIC6337_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+const PMIC_FLAG_TABLE_ENTRY pmic6335_flags_table[] =
+{
+ {MT6335_HWCID, MT6335_HWCID_MASK, MT6335_HWCID_SHIFT, },
+ {MT6335_SWCID, MT6335_SWCID_MASK, MT6335_SWCID_SHIFT, },
+ {MT6335_TOP_CON, MT6335_RG_SRCLKEN_IN0_EN_MASK, MT6335_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6335_TOP_CON, MT6335_RG_SRCLKEN_IN1_EN_MASK, MT6335_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6335_TOP_CON, MT6335_RG_SRCLKEN_IN0_HW_MODE_MASK, MT6335_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6335_TOP_CON, MT6335_RG_SRCLKEN_IN1_HW_MODE_MASK, MT6335_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6335_BUCK_VMD1_CON0, MT6335_RG_BUCK_VMD1_EN_MASK, MT6335_RG_BUCK_VMD1_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_CON0, MT6335_RG_BUCK_VMD1_LP_MASK, MT6335_RG_BUCK_VMD1_LP_SHIFT, },
+ {MT6335_BUCK_VMD1_CON1, MT6335_RG_BUCK_VMD1_VOSEL_MASK, MT6335_RG_BUCK_VMD1_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMD1_CON2, MT6335_RG_BUCK_VMD1_VOSEL_SLEEP_MASK, MT6335_RG_BUCK_VMD1_VOSEL_SLEEP_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, MT6335_RG_BUCK_VMD1_SW_OP_EN_MASK, MT6335_RG_BUCK_VMD1_SW_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, MT6335_RG_BUCK_VMD1_HW0_OP_EN_MASK, MT6335_RG_BUCK_VMD1_HW0_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, MT6335_RG_BUCK_VMD1_HW1_OP_EN_MASK, MT6335_RG_BUCK_VMD1_HW1_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, MT6335_RG_BUCK_VMD1_HW2_OP_EN_MASK, MT6335_RG_BUCK_VMD1_HW2_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN_SET, MT6335_RG_BUCK_VMD1_OP_EN_SET_MASK, MT6335_RG_BUCK_VMD1_OP_EN_SET_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN_CLR, MT6335_RG_BUCK_VMD1_OP_EN_CLR_MASK, MT6335_RG_BUCK_VMD1_OP_EN_CLR_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, MT6335_RG_BUCK_VMD1_HW0_OP_CFG_MASK, MT6335_RG_BUCK_VMD1_HW0_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, MT6335_RG_BUCK_VMD1_HW1_OP_CFG_MASK, MT6335_RG_BUCK_VMD1_HW1_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, MT6335_RG_BUCK_VMD1_HW2_OP_CFG_MASK, MT6335_RG_BUCK_VMD1_HW2_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, MT6335_RG_BUCK_VMD1_ON_OP_MASK, MT6335_RG_BUCK_VMD1_ON_OP_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, MT6335_RG_BUCK_VMD1_LP_OP_MASK, MT6335_RG_BUCK_VMD1_LP_OP_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG_SET, MT6335_RG_BUCK_VMD1_OP_CFG_SET_MASK, MT6335_RG_BUCK_VMD1_OP_CFG_SET_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG_CLR, MT6335_RG_BUCK_VMD1_OP_CFG_CLR_MASK, MT6335_RG_BUCK_VMD1_OP_CFG_CLR_SHIFT, },
+ {MT6335_BUCK_VMD1_DBG0, MT6335_DA_NI_VMD1_VOSEL_MASK, MT6335_DA_NI_VMD1_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMD1_DBG0, MT6335_DA_NI_VMD1_VOSEL_GRAY_MASK, MT6335_DA_NI_VMD1_VOSEL_GRAY_SHIFT, },
+ {MT6335_BUCK_VMD1_DBG1, MT6335_DA_QI_VMD1_EN_MASK, MT6335_DA_QI_VMD1_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON0, MT6335_RG_BUCK_VMODEM_EN_MASK, MT6335_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON0, MT6335_RG_BUCK_VMODEM_LP_MASK, MT6335_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON1, MT6335_RG_BUCK_VMODEM_VOSEL_MASK, MT6335_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON2, MT6335_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, MT6335_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, MT6335_RG_BUCK_VMODEM_SW_OP_EN_MASK, MT6335_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, MT6335_RG_BUCK_VMODEM_HW0_OP_EN_MASK, MT6335_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, MT6335_RG_BUCK_VMODEM_HW1_OP_EN_MASK, MT6335_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, MT6335_RG_BUCK_VMODEM_HW2_OP_EN_MASK, MT6335_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN_SET, MT6335_RG_BUCK_VMODEM_OP_EN_SET_MASK, MT6335_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN_CLR, MT6335_RG_BUCK_VMODEM_OP_EN_CLR_MASK, MT6335_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, MT6335_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, MT6335_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, MT6335_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, MT6335_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, MT6335_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, MT6335_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, MT6335_RG_BUCK_VMODEM_ON_OP_MASK, MT6335_RG_BUCK_VMODEM_ON_OP_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, MT6335_RG_BUCK_VMODEM_LP_OP_MASK, MT6335_RG_BUCK_VMODEM_LP_OP_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG_SET, MT6335_RG_BUCK_VMODEM_OP_CFG_SET_MASK, MT6335_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG_CLR, MT6335_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, MT6335_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6335_BUCK_VMODEM_DBG0, MT6335_DA_NI_VMODEM_VOSEL_MASK, MT6335_DA_NI_VMODEM_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMODEM_DBG0, MT6335_DA_NI_VMODEM_VOSEL_GRAY_MASK, MT6335_DA_NI_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6335_BUCK_VMODEM_DBG1, MT6335_DA_QI_VMODEM_EN_MASK, MT6335_DA_QI_VMODEM_EN_SHIFT, },
+ {MT6335_BUCK_VPA1_CON0, MT6335_RG_BUCK_VPA1_EN_MASK, MT6335_RG_BUCK_VPA1_EN_SHIFT, },
+ {MT6335_BUCK_VPA1_CON1, MT6335_RG_BUCK_VPA1_VOSEL_MASK, MT6335_RG_BUCK_VPA1_VOSEL_SHIFT, },
+ {MT6335_BUCK_VPA2_CON0, MT6335_RG_BUCK_VPA2_EN_MASK, MT6335_RG_BUCK_VPA2_EN_SHIFT, },
+ {MT6335_BUCK_VPA2_CON1, MT6335_RG_BUCK_VPA2_VOSEL_MASK, MT6335_RG_BUCK_VPA2_VOSEL_SHIFT, },
+ {MT6335_SMPS_ANA_CON13, MT6335_RG_VMODEM_SLEEP_VOLTAGE_MASK, MT6335_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
+ {MT6335_SMPS_ANA_CON13, MT6335_RG_VMD1_SLEEP_VOLTAGE_MASK, MT6335_RG_VMD1_SLEEP_VOLTAGE_SHIFT, },
+ {MT6335_SMPS_ANA_CON14, MT6335_RG_VSRAM_VMD_SLEEP_VOLTAGE_MASK, MT6335_RG_VSRAM_VMD_SLEEP_VOLTAGE_SHIFT, },
+ {MT6335_VPA1_ANA_CON0, MT6335_RG_VPA1_MODESET_MASK, MT6335_RG_VPA1_MODESET_SHIFT, },
+ {MT6335_VPA2_ANA_CON0, MT6335_RG_VPA2_MODESET_MASK, MT6335_RG_VPA2_MODESET_SHIFT, },
+ {MT6335_LDO_VSIM1_CON0, MT6335_RG_VSIM1_SW_EN_MASK, MT6335_RG_VSIM1_SW_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_CON0, MT6335_RG_VSIM1_SW_LP_MASK, MT6335_RG_VSIM1_SW_LP_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, MT6335_RG_VSIM1_SW_OP_EN_MASK, MT6335_RG_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, MT6335_RG_VSIM1_HW0_OP_EN_MASK, MT6335_RG_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, MT6335_RG_VSIM1_HW1_OP_EN_MASK, MT6335_RG_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, MT6335_RG_VSIM1_HW2_OP_EN_MASK, MT6335_RG_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN_SET, MT6335_RG_VSIM1_OP_EN_SET_MASK, MT6335_RG_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN_CLR, MT6335_RG_VSIM1_OP_EN_CLR_MASK, MT6335_RG_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, MT6335_RG_VSIM1_HW0_OP_CFG_MASK, MT6335_RG_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, MT6335_RG_VSIM1_HW1_OP_CFG_MASK, MT6335_RG_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, MT6335_RG_VSIM1_HW2_OP_CFG_MASK, MT6335_RG_VSIM1_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, MT6335_RG_VSIM1_GO_ON_OP_MASK, MT6335_RG_VSIM1_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, MT6335_RG_VSIM1_GO_LP_OP_MASK, MT6335_RG_VSIM1_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG_SET, MT6335_RG_VSIM1_OP_CFG_SET_MASK, MT6335_RG_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG_CLR, MT6335_RG_VSIM1_OP_CFG_CLR_MASK, MT6335_RG_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSIM1_CON2, MT6335_RG_VSIM1_OCFB_EN_MASK, MT6335_RG_VSIM1_OCFB_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_CON0, MT6335_RG_VSIM2_SW_EN_MASK, MT6335_RG_VSIM2_SW_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_CON0, MT6335_RG_VSIM2_SW_LP_MASK, MT6335_RG_VSIM2_SW_LP_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, MT6335_RG_VSIM2_SW_OP_EN_MASK, MT6335_RG_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, MT6335_RG_VSIM2_HW0_OP_EN_MASK, MT6335_RG_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, MT6335_RG_VSIM2_HW1_OP_EN_MASK, MT6335_RG_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, MT6335_RG_VSIM2_HW2_OP_EN_MASK, MT6335_RG_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN_SET, MT6335_RG_VSIM2_OP_EN_SET_MASK, MT6335_RG_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN_CLR, MT6335_RG_VSIM2_OP_EN_CLR_MASK, MT6335_RG_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, MT6335_RG_VSIM2_HW0_OP_CFG_MASK, MT6335_RG_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, MT6335_RG_VSIM2_HW1_OP_CFG_MASK, MT6335_RG_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, MT6335_RG_VSIM2_HW2_OP_CFG_MASK, MT6335_RG_VSIM2_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, MT6335_RG_VSIM2_GO_ON_OP_MASK, MT6335_RG_VSIM2_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, MT6335_RG_VSIM2_GO_LP_OP_MASK, MT6335_RG_VSIM2_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG_SET, MT6335_RG_VSIM2_OP_CFG_SET_MASK, MT6335_RG_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG_CLR, MT6335_RG_VSIM2_OP_CFG_CLR_MASK, MT6335_RG_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSIM2_CON2, MT6335_RG_VSIM2_OCFB_EN_MASK, MT6335_RG_VSIM2_OCFB_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_CON0, MT6335_RG_VMIPI_SW_EN_MASK, MT6335_RG_VMIPI_SW_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_CON0, MT6335_RG_VMIPI_SW_LP_MASK, MT6335_RG_VMIPI_SW_LP_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, MT6335_RG_VMIPI_SW_OP_EN_MASK, MT6335_RG_VMIPI_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, MT6335_RG_VMIPI_HW0_OP_EN_MASK, MT6335_RG_VMIPI_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, MT6335_RG_VMIPI_HW1_OP_EN_MASK, MT6335_RG_VMIPI_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, MT6335_RG_VMIPI_HW2_OP_EN_MASK, MT6335_RG_VMIPI_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN_SET, MT6335_RG_VMIPI_OP_EN_SET_MASK, MT6335_RG_VMIPI_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN_CLR, MT6335_RG_VMIPI_OP_EN_CLR_MASK, MT6335_RG_VMIPI_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, MT6335_RG_VMIPI_HW0_OP_CFG_MASK, MT6335_RG_VMIPI_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, MT6335_RG_VMIPI_HW1_OP_CFG_MASK, MT6335_RG_VMIPI_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, MT6335_RG_VMIPI_HW2_OP_CFG_MASK, MT6335_RG_VMIPI_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, MT6335_RG_VMIPI_GO_ON_OP_MASK, MT6335_RG_VMIPI_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, MT6335_RG_VMIPI_GO_LP_OP_MASK, MT6335_RG_VMIPI_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG_SET, MT6335_RG_VMIPI_OP_CFG_SET_MASK, MT6335_RG_VMIPI_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG_CLR, MT6335_RG_VMIPI_OP_CFG_CLR_MASK, MT6335_RG_VMIPI_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VFE28_CON0, MT6335_RG_VFE28_SW_EN_MASK, MT6335_RG_VFE28_SW_EN_SHIFT, },
+ {MT6335_LDO_VFE28_CON0, MT6335_RG_VFE28_SW_LP_MASK, MT6335_RG_VFE28_SW_LP_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, MT6335_RG_VFE28_SW_OP_EN_MASK, MT6335_RG_VFE28_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, MT6335_RG_VFE28_HW0_OP_EN_MASK, MT6335_RG_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, MT6335_RG_VFE28_HW1_OP_EN_MASK, MT6335_RG_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, MT6335_RG_VFE28_HW2_OP_EN_MASK, MT6335_RG_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN_SET, MT6335_RG_VFE28_OP_EN_SET_MASK, MT6335_RG_VFE28_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN_CLR, MT6335_RG_VFE28_OP_EN_CLR_MASK, MT6335_RG_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, MT6335_RG_VFE28_HW0_OP_CFG_MASK, MT6335_RG_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, MT6335_RG_VFE28_HW1_OP_CFG_MASK, MT6335_RG_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, MT6335_RG_VFE28_HW2_OP_CFG_MASK, MT6335_RG_VFE28_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, MT6335_RG_VFE28_GO_ON_OP_MASK, MT6335_RG_VFE28_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, MT6335_RG_VFE28_GO_LP_OP_MASK, MT6335_RG_VFE28_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG_SET, MT6335_RG_VFE28_OP_CFG_SET_MASK, MT6335_RG_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG_CLR, MT6335_RG_VFE28_OP_CFG_CLR_MASK, MT6335_RG_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_1_CON0, MT6335_RG_VRF18_1_SW_EN_MASK, MT6335_RG_VRF18_1_SW_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_CON0, MT6335_RG_VRF18_1_SW_LP_MASK, MT6335_RG_VRF18_1_SW_LP_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, MT6335_RG_VRF18_1_SW_OP_EN_MASK, MT6335_RG_VRF18_1_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, MT6335_RG_VRF18_1_HW0_OP_EN_MASK, MT6335_RG_VRF18_1_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, MT6335_RG_VRF18_1_HW1_OP_EN_MASK, MT6335_RG_VRF18_1_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, MT6335_RG_VRF18_1_HW2_OP_EN_MASK, MT6335_RG_VRF18_1_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN_SET, MT6335_RG_VRF18_1_OP_EN_SET_MASK, MT6335_RG_VRF18_1_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN_CLR, MT6335_RG_VRF18_1_OP_EN_CLR_MASK, MT6335_RG_VRF18_1_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, MT6335_RG_VRF18_1_HW0_OP_CFG_MASK, MT6335_RG_VRF18_1_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, MT6335_RG_VRF18_1_HW1_OP_CFG_MASK, MT6335_RG_VRF18_1_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, MT6335_RG_VRF18_1_HW2_OP_CFG_MASK, MT6335_RG_VRF18_1_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, MT6335_RG_VRF18_1_GO_ON_OP_MASK, MT6335_RG_VRF18_1_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, MT6335_RG_VRF18_1_GO_LP_OP_MASK, MT6335_RG_VRF18_1_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG_SET, MT6335_RG_VRF18_1_OP_CFG_SET_MASK, MT6335_RG_VRF18_1_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG_CLR, MT6335_RG_VRF18_1_OP_CFG_CLR_MASK, MT6335_RG_VRF18_1_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_2_CON0, MT6335_RG_VRF18_2_SW_EN_MASK, MT6335_RG_VRF18_2_SW_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_CON0, MT6335_RG_VRF18_2_SW_LP_MASK, MT6335_RG_VRF18_2_SW_LP_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, MT6335_RG_VRF18_2_SW_OP_EN_MASK, MT6335_RG_VRF18_2_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, MT6335_RG_VRF18_2_HW0_OP_EN_MASK, MT6335_RG_VRF18_2_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, MT6335_RG_VRF18_2_HW1_OP_EN_MASK, MT6335_RG_VRF18_2_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, MT6335_RG_VRF18_2_HW2_OP_EN_MASK, MT6335_RG_VRF18_2_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN_SET, MT6335_RG_VRF18_2_OP_EN_SET_MASK, MT6335_RG_VRF18_2_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN_CLR, MT6335_RG_VRF18_2_OP_EN_CLR_MASK, MT6335_RG_VRF18_2_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, MT6335_RG_VRF18_2_HW0_OP_CFG_MASK, MT6335_RG_VRF18_2_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, MT6335_RG_VRF18_2_HW1_OP_CFG_MASK, MT6335_RG_VRF18_2_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, MT6335_RG_VRF18_2_HW2_OP_CFG_MASK, MT6335_RG_VRF18_2_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, MT6335_RG_VRF18_2_GO_ON_OP_MASK, MT6335_RG_VRF18_2_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, MT6335_RG_VRF18_2_GO_LP_OP_MASK, MT6335_RG_VRF18_2_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG_SET, MT6335_RG_VRF18_2_OP_CFG_SET_MASK, MT6335_RG_VRF18_2_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG_CLR, MT6335_RG_VRF18_2_OP_CFG_CLR_MASK, MT6335_RG_VRF18_2_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VRF12_CON0, MT6335_RG_VRF12_SW_EN_MASK, MT6335_RG_VRF12_SW_EN_SHIFT, },
+ {MT6335_LDO_VRF12_CON0, MT6335_RG_VRF12_SW_LP_MASK, MT6335_RG_VRF12_SW_LP_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, MT6335_RG_VRF12_SW_OP_EN_MASK, MT6335_RG_VRF12_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, MT6335_RG_VRF12_HW0_OP_EN_MASK, MT6335_RG_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, MT6335_RG_VRF12_HW1_OP_EN_MASK, MT6335_RG_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, MT6335_RG_VRF12_HW2_OP_EN_MASK, MT6335_RG_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN_SET, MT6335_RG_VRF12_OP_EN_SET_MASK, MT6335_RG_VRF12_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN_CLR, MT6335_RG_VRF12_OP_EN_CLR_MASK, MT6335_RG_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, MT6335_RG_VRF12_HW0_OP_CFG_MASK, MT6335_RG_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, MT6335_RG_VRF12_HW1_OP_CFG_MASK, MT6335_RG_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, MT6335_RG_VRF12_HW2_OP_CFG_MASK, MT6335_RG_VRF12_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, MT6335_RG_VRF12_GO_ON_OP_MASK, MT6335_RG_VRF12_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, MT6335_RG_VRF12_GO_LP_OP_MASK, MT6335_RG_VRF12_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG_SET, MT6335_RG_VRF12_OP_CFG_SET_MASK, MT6335_RG_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG_CLR, MT6335_RG_VRF12_OP_CFG_CLR_MASK, MT6335_RG_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON0, MT6335_RG_VSRAM_VMD_SW_EN_MASK, MT6335_RG_VSRAM_VMD_SW_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON0, MT6335_RG_VSRAM_VMD_SW_LP_MASK, MT6335_RG_VSRAM_VMD_SW_LP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON1, MT6335_RG_VSRAM_VMD_VOSEL_MASK, MT6335_RG_VSRAM_VMD_VOSEL_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON2, MT6335_RG_VSRAM_VMD_VOSEL_SLEEP_MASK, MT6335_RG_VSRAM_VMD_VOSEL_SLEEP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, MT6335_RG_VSRAM_VMD_SW_OP_EN_MASK, MT6335_RG_VSRAM_VMD_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, MT6335_RG_VSRAM_VMD_HW0_OP_EN_MASK, MT6335_RG_VSRAM_VMD_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, MT6335_RG_VSRAM_VMD_HW1_OP_EN_MASK, MT6335_RG_VSRAM_VMD_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, MT6335_RG_VSRAM_VMD_HW2_OP_EN_MASK, MT6335_RG_VSRAM_VMD_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN_SET, MT6335_RG_VSRAM_VMD_OP_EN_SET_MASK, MT6335_RG_VSRAM_VMD_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN_CLR, MT6335_RG_VSRAM_VMD_OP_EN_CLR_MASK, MT6335_RG_VSRAM_VMD_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, MT6335_RG_VSRAM_VMD_HW0_OP_CFG_MASK, MT6335_RG_VSRAM_VMD_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, MT6335_RG_VSRAM_VMD_HW1_OP_CFG_MASK, MT6335_RG_VSRAM_VMD_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, MT6335_RG_VSRAM_VMD_HW2_OP_CFG_MASK, MT6335_RG_VSRAM_VMD_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, MT6335_RG_VSRAM_VMD_GO_ON_OP_MASK, MT6335_RG_VSRAM_VMD_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, MT6335_RG_VSRAM_VMD_GO_LP_OP_MASK, MT6335_RG_VSRAM_VMD_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG_SET, MT6335_RG_VSRAM_VMD_OP_CFG_SET_MASK, MT6335_RG_VSRAM_VMD_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG_CLR, MT6335_RG_VSRAM_VMD_OP_CFG_CLR_MASK, MT6335_RG_VSRAM_VMD_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_DBG0, MT6335_DA_NI_VSRAM_VMD_VOSEL_GRAY_MASK, MT6335_DA_NI_VSRAM_VMD_VOSEL_GRAY_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_DBG0, MT6335_DA_NI_VSRAM_VMD_VOSEL_MASK, MT6335_DA_NI_VSRAM_VMD_VOSEL_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_DBG1, MT6335_DA_QI_VSRAM_VMD_EN_MASK, MT6335_DA_QI_VSRAM_VMD_EN_SHIFT, },
+ {MT6335_ALDO_1_ANA_CON3, MT6335_RG_VXO22_VOSEL_MASK, MT6335_RG_VXO22_VOSEL_SHIFT, },
+ {MT6335_DLDO_ANA_CON4, MT6335_RG_VSIM1_VOSEL_MASK, MT6335_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6335_DLDO_ANA_CON16, MT6335_RG_VSIM2_VOSEL_MASK, MT6335_RG_VSIM2_VOSEL_SHIFT, },
+ //{MT6335_DCXO_CW00, MT6335_XO_BB_LPM_EN_MASK, MT6335_XO_BB_LPM_EN_SHIFT, },
+ //{MT6335_DCXO_CW00_SET, MT6335_DCXO_CW00_SET_MASK, MT6335_DCXO_CW00_SET_SHIFT, },
+ //{MT6335_DCXO_CW00_CLR, MT6335_DCXO_CW00_CLR_MASK, MT6335_DCXO_CW00_CLR_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_EN32K_MAN_MASK, MT6335_XO_EN32K_MAN_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_EN32K_M_MASK, MT6335_XO_EN32K_M_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_XMODE_MAN_MASK, MT6335_XO_XMODE_MAN_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_XMODE_M_MASK, MT6335_XO_XMODE_M_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_STRUP_MODE_MASK, MT6335_XO_STRUP_MODE_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_AAC_FPM_TIME_MASK, MT6335_XO_AAC_FPM_TIME_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_AAC_MODE_LPM_MASK, MT6335_XO_AAC_MODE_LPM_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_AAC_MODE_FPM_MASK, MT6335_XO_AAC_MODE_FPM_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_EN26M_OFFSQ_EN_MASK, MT6335_XO_EN26M_OFFSQ_EN_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_LDOCAL_EN_MASK, MT6335_XO_LDOCAL_EN_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_CBANK_SYNC_DYN_MASK, MT6335_XO_CBANK_SYNC_DYN_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_26MLP_MAN_EN_MASK, MT6335_XO_26MLP_MAN_EN_SHIFT, },
+ //{MT6335_DCXO_CW02, MT6335_XO_BUFLDOK_EN_MASK, MT6335_XO_BUFLDOK_EN_SHIFT, },
+ //{MT6335_DCXO_CW04, MT6335_XO_CDAC_FPM_MASK, MT6335_XO_CDAC_FPM_SHIFT, },
+ //{MT6335_DCXO_CW04, MT6335_XO_CDAC_LPM_MASK, MT6335_XO_CDAC_LPM_SHIFT, },
+ //{MT6335_DCXO_CW05, MT6335_XO_32KDIV_NFRAC_FPM_MASK, MT6335_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ //{MT6335_DCXO_CW05, MT6335_XO_COFST_FPM_MASK, MT6335_XO_COFST_FPM_SHIFT, },
+ //{MT6335_DCXO_CW06, MT6335_XO_32KDIV_NFRAC_LPM_MASK, MT6335_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ //{MT6335_DCXO_CW06, MT6335_XO_COFST_LPM_MASK, MT6335_XO_COFST_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_CORE_BYPCAS_LPM_MASK, MT6335_XO_CORE_BYPCAS_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_CORE_GMX2_LPM_MASK, MT6335_XO_CORE_GMX2_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_CORE_IDAC_LPM_MASK, MT6335_XO_CORE_IDAC_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_AAC_COMP_HV_LPM_MASK, MT6335_XO_AAC_COMP_HV_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_AAC_VSEL_LPM_MASK, MT6335_XO_AAC_VSEL_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_AAC_HV_LPM_MASK, MT6335_XO_AAC_HV_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_AAC_IBIAS_LPM_MASK, MT6335_XO_AAC_IBIAS_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_AAC_VOFST_LPM_MASK, MT6335_XO_AAC_VOFST_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_AAC_FPM_SWEN_MASK, MT6335_XO_AAC_FPM_SWEN_SHIFT, },
+ //{MT6335_DCXO_CW09, MT6335_XO_SWRST_MASK, MT6335_XO_SWRST_SHIFT, },
+ {MT6335_AUXADC_ADC17, MT6335_AUXADC_ADC_OUT_CH7_BY_MD_MASK, MT6335_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6335_AUXADC_ADC17, MT6335_AUXADC_ADC_RDY_CH7_BY_MD_MASK, MT6335_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6335_AUXADC_RQST1_SET, MT6335_AUXADC_RQST1_SET_MASK, MT6335_AUXADC_RQST1_SET_SHIFT, },
+ {MT6335_AUXADC_RQST1_CLR, MT6335_AUXADC_RQST1_CLR_MASK, MT6335_AUXADC_RQST1_CLR_SHIFT, },
+};
+#elif defined (DRV_PMIC_WRAP_6799_REG)
+const PMIC_FLAG_TABLE_ENTRY pmic6335_flags_table[] =
+{
+ {PMIC_HWCID_ADDR, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {PMIC_SWCID_ADDR, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {MT6335_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6335_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6335_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6335_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6335_BUCK_VMD1_CON0, PMIC_RG_BUCK_VMD1_EN_MASK, PMIC_RG_BUCK_VMD1_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_CON0, PMIC_RG_BUCK_VMD1_LP_MASK, PMIC_RG_BUCK_VMD1_LP_SHIFT, },
+ {MT6335_BUCK_VMD1_CON1, PMIC_RG_BUCK_VMD1_VOSEL_MASK, PMIC_RG_BUCK_VMD1_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMD1_CON2, PMIC_RG_BUCK_VMD1_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMD1_VOSEL_SLEEP_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, PMIC_RG_BUCK_VMD1_SW_OP_EN_MASK, PMIC_RG_BUCK_VMD1_SW_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, PMIC_RG_BUCK_VMD1_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMD1_HW0_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, PMIC_RG_BUCK_VMD1_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMD1_HW1_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN, PMIC_RG_BUCK_VMD1_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMD1_HW2_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN_SET, PMIC_RG_BUCK_VMD1_OP_EN_SET_MASK, PMIC_RG_BUCK_VMD1_OP_EN_SET_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_EN_CLR, PMIC_RG_BUCK_VMD1_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMD1_OP_EN_CLR_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, PMIC_RG_BUCK_VMD1_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMD1_HW0_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, PMIC_RG_BUCK_VMD1_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMD1_HW1_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, PMIC_RG_BUCK_VMD1_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMD1_HW2_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, PMIC_RG_BUCK_VMD1_ON_OP_MASK, PMIC_RG_BUCK_VMD1_ON_OP_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG, PMIC_RG_BUCK_VMD1_LP_OP_MASK, PMIC_RG_BUCK_VMD1_LP_OP_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG_SET, PMIC_RG_BUCK_VMD1_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMD1_OP_CFG_SET_SHIFT, },
+ {MT6335_BUCK_VMD1_OP_CFG_CLR, PMIC_RG_BUCK_VMD1_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMD1_OP_CFG_CLR_SHIFT, },
+ {MT6335_BUCK_VMD1_DBG0, PMIC_DA_NI_VMD1_VOSEL_MASK, PMIC_DA_NI_VMD1_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMD1_DBG0, PMIC_DA_NI_VMD1_VOSEL_GRAY_MASK, PMIC_DA_NI_VMD1_VOSEL_GRAY_SHIFT, },
+ {MT6335_BUCK_VMD1_DBG1, PMIC_DA_QI_VMD1_EN_MASK, PMIC_DA_QI_VMD1_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMODEM_CON2, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6335_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6335_BUCK_VMODEM_DBG0, PMIC_DA_NI_VMODEM_VOSEL_MASK, PMIC_DA_NI_VMODEM_VOSEL_SHIFT, },
+ {MT6335_BUCK_VMODEM_DBG0, PMIC_DA_NI_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_NI_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6335_BUCK_VMODEM_DBG1, PMIC_DA_QI_VMODEM_EN_MASK, PMIC_DA_QI_VMODEM_EN_SHIFT, },
+ {MT6335_BUCK_VPA1_CON0, PMIC_RG_BUCK_VPA1_EN_MASK, PMIC_RG_BUCK_VPA1_EN_SHIFT, },
+ {MT6335_BUCK_VPA1_CON1, PMIC_RG_BUCK_VPA1_VOSEL_MASK, PMIC_RG_BUCK_VPA1_VOSEL_SHIFT, },
+// {MT6335_BUCK_VPA2_CON0, PMIC_RG_BUCK_VPA2_EN_MASK, PMIC_RG_BUCK_VPA2_EN_SHIFT, },
+// {MT6335_BUCK_VPA2_CON1, PMIC_RG_BUCK_VPA2_VOSEL_MASK, PMIC_RG_BUCK_VPA2_VOSEL_SHIFT, },
+ {MT6335_SMPS_ANA_CON13, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
+ {MT6335_SMPS_ANA_CON13, PMIC_RG_VMD1_SLEEP_VOLTAGE_MASK, PMIC_RG_VMD1_SLEEP_VOLTAGE_SHIFT, },
+ {MT6335_SMPS_ANA_CON14, PMIC_RG_VSRAM_VMD_SLEEP_VOLTAGE_MASK, PMIC_RG_VSRAM_VMD_SLEEP_VOLTAGE_SHIFT, },
+ {MT6335_VPA1_ANA_CON0, PMIC_RG_VPA1_MODESET_MASK, PMIC_RG_VPA1_MODESET_SHIFT, },
+// {MT6335_VPA2_ANA_CON0, PMIC_RG_VPA2_MODESET_MASK, PMIC_RG_VPA2_MODESET_SHIFT, },
+ {MT6335_LDO_VSIM1_CON0, PMIC_RG_VSIM1_SW_EN_MASK, PMIC_RG_VSIM1_SW_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_CON0, PMIC_RG_VSIM1_SW_LP_MASK, PMIC_RG_VSIM1_SW_LP_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, PMIC_RG_VSIM1_SW_OP_EN_MASK, PMIC_RG_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, PMIC_RG_VSIM1_HW0_OP_EN_MASK, PMIC_RG_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, PMIC_RG_VSIM1_HW1_OP_EN_MASK, PMIC_RG_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN, PMIC_RG_VSIM1_HW2_OP_EN_MASK, PMIC_RG_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN_SET, PMIC_RG_VSIM1_OP_EN_SET_MASK, PMIC_RG_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_EN_CLR, PMIC_RG_VSIM1_OP_EN_CLR_MASK, PMIC_RG_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, PMIC_RG_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, PMIC_RG_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, PMIC_RG_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_VSIM1_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, PMIC_RG_VSIM1_GO_ON_OP_MASK, PMIC_RG_VSIM1_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG, PMIC_RG_VSIM1_GO_LP_OP_MASK, PMIC_RG_VSIM1_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG_SET, PMIC_RG_VSIM1_OP_CFG_SET_MASK, PMIC_RG_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSIM1_CON2, PMIC_RG_VSIM1_OCFB_EN_MASK, PMIC_RG_VSIM1_OCFB_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_CON0, PMIC_RG_VSIM2_SW_EN_MASK, PMIC_RG_VSIM2_SW_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_CON0, PMIC_RG_VSIM2_SW_LP_MASK, PMIC_RG_VSIM2_SW_LP_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, PMIC_RG_VSIM2_SW_OP_EN_MASK, PMIC_RG_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, PMIC_RG_VSIM2_HW0_OP_EN_MASK, PMIC_RG_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, PMIC_RG_VSIM2_HW1_OP_EN_MASK, PMIC_RG_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN, PMIC_RG_VSIM2_HW2_OP_EN_MASK, PMIC_RG_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN_SET, PMIC_RG_VSIM2_OP_EN_SET_MASK, PMIC_RG_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_EN_CLR, PMIC_RG_VSIM2_OP_EN_CLR_MASK, PMIC_RG_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, PMIC_RG_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, PMIC_RG_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, PMIC_RG_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_VSIM2_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, PMIC_RG_VSIM2_GO_ON_OP_MASK, PMIC_RG_VSIM2_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG, PMIC_RG_VSIM2_GO_LP_OP_MASK, PMIC_RG_VSIM2_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG_SET, PMIC_RG_VSIM2_OP_CFG_SET_MASK, PMIC_RG_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSIM2_CON2, PMIC_RG_VSIM2_OCFB_EN_MASK, PMIC_RG_VSIM2_OCFB_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_CON0, PMIC_RG_VMIPI_SW_EN_MASK, PMIC_RG_VMIPI_SW_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_CON0, PMIC_RG_VMIPI_SW_LP_MASK, PMIC_RG_VMIPI_SW_LP_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, PMIC_RG_VMIPI_SW_OP_EN_MASK, PMIC_RG_VMIPI_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, PMIC_RG_VMIPI_HW0_OP_EN_MASK, PMIC_RG_VMIPI_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, PMIC_RG_VMIPI_HW1_OP_EN_MASK, PMIC_RG_VMIPI_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN, PMIC_RG_VMIPI_HW2_OP_EN_MASK, PMIC_RG_VMIPI_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN_SET, PMIC_RG_VMIPI_OP_EN_SET_MASK, PMIC_RG_VMIPI_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_EN_CLR, PMIC_RG_VMIPI_OP_EN_CLR_MASK, PMIC_RG_VMIPI_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, PMIC_RG_VMIPI_HW0_OP_CFG_MASK, PMIC_RG_VMIPI_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, PMIC_RG_VMIPI_HW1_OP_CFG_MASK, PMIC_RG_VMIPI_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, PMIC_RG_VMIPI_HW2_OP_CFG_MASK, PMIC_RG_VMIPI_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, PMIC_RG_VMIPI_GO_ON_OP_MASK, PMIC_RG_VMIPI_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG, PMIC_RG_VMIPI_GO_LP_OP_MASK, PMIC_RG_VMIPI_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG_SET, PMIC_RG_VMIPI_OP_CFG_SET_MASK, PMIC_RG_VMIPI_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VMIPI_OP_CFG_CLR, PMIC_RG_VMIPI_OP_CFG_CLR_MASK, PMIC_RG_VMIPI_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VFE28_CON0, PMIC_RG_VFE28_SW_EN_MASK, PMIC_RG_VFE28_SW_EN_SHIFT, },
+ {MT6335_LDO_VFE28_CON0, PMIC_RG_VFE28_SW_LP_MASK, PMIC_RG_VFE28_SW_LP_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, PMIC_RG_VFE28_SW_OP_EN_MASK, PMIC_RG_VFE28_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, PMIC_RG_VFE28_HW0_OP_EN_MASK, PMIC_RG_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, PMIC_RG_VFE28_HW1_OP_EN_MASK, PMIC_RG_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN, PMIC_RG_VFE28_HW2_OP_EN_MASK, PMIC_RG_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN_SET, PMIC_RG_VFE28_OP_EN_SET_MASK, PMIC_RG_VFE28_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VFE28_OP_EN_CLR, PMIC_RG_VFE28_OP_EN_CLR_MASK, PMIC_RG_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, PMIC_RG_VFE28_HW0_OP_CFG_MASK, PMIC_RG_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, PMIC_RG_VFE28_HW1_OP_CFG_MASK, PMIC_RG_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, PMIC_RG_VFE28_HW2_OP_CFG_MASK, PMIC_RG_VFE28_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, PMIC_RG_VFE28_GO_ON_OP_MASK, PMIC_RG_VFE28_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG, PMIC_RG_VFE28_GO_LP_OP_MASK, PMIC_RG_VFE28_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG_SET, PMIC_RG_VFE28_OP_CFG_SET_MASK, PMIC_RG_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VFE28_OP_CFG_CLR, PMIC_RG_VFE28_OP_CFG_CLR_MASK, PMIC_RG_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_1_CON0, PMIC_RG_VRF18_1_SW_EN_MASK, PMIC_RG_VRF18_1_SW_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_CON0, PMIC_RG_VRF18_1_SW_LP_MASK, PMIC_RG_VRF18_1_SW_LP_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, PMIC_RG_VRF18_1_SW_OP_EN_MASK, PMIC_RG_VRF18_1_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, PMIC_RG_VRF18_1_HW0_OP_EN_MASK, PMIC_RG_VRF18_1_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, PMIC_RG_VRF18_1_HW1_OP_EN_MASK, PMIC_RG_VRF18_1_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN, PMIC_RG_VRF18_1_HW2_OP_EN_MASK, PMIC_RG_VRF18_1_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN_SET, PMIC_RG_VRF18_1_OP_EN_SET_MASK, PMIC_RG_VRF18_1_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_EN_CLR, PMIC_RG_VRF18_1_OP_EN_CLR_MASK, PMIC_RG_VRF18_1_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, PMIC_RG_VRF18_1_HW0_OP_CFG_MASK, PMIC_RG_VRF18_1_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, PMIC_RG_VRF18_1_HW1_OP_CFG_MASK, PMIC_RG_VRF18_1_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, PMIC_RG_VRF18_1_HW2_OP_CFG_MASK, PMIC_RG_VRF18_1_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, PMIC_RG_VRF18_1_GO_ON_OP_MASK, PMIC_RG_VRF18_1_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG, PMIC_RG_VRF18_1_GO_LP_OP_MASK, PMIC_RG_VRF18_1_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG_SET, PMIC_RG_VRF18_1_OP_CFG_SET_MASK, PMIC_RG_VRF18_1_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VRF18_1_OP_CFG_CLR, PMIC_RG_VRF18_1_OP_CFG_CLR_MASK, PMIC_RG_VRF18_1_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_2_CON0, PMIC_RG_VRF18_2_SW_EN_MASK, PMIC_RG_VRF18_2_SW_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_CON0, PMIC_RG_VRF18_2_SW_LP_MASK, PMIC_RG_VRF18_2_SW_LP_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, PMIC_RG_VRF18_2_SW_OP_EN_MASK, PMIC_RG_VRF18_2_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, PMIC_RG_VRF18_2_HW0_OP_EN_MASK, PMIC_RG_VRF18_2_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, PMIC_RG_VRF18_2_HW1_OP_EN_MASK, PMIC_RG_VRF18_2_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN, PMIC_RG_VRF18_2_HW2_OP_EN_MASK, PMIC_RG_VRF18_2_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN_SET, PMIC_RG_VRF18_2_OP_EN_SET_MASK, PMIC_RG_VRF18_2_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_EN_CLR, PMIC_RG_VRF18_2_OP_EN_CLR_MASK, PMIC_RG_VRF18_2_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, PMIC_RG_VRF18_2_HW0_OP_CFG_MASK, PMIC_RG_VRF18_2_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, PMIC_RG_VRF18_2_HW1_OP_CFG_MASK, PMIC_RG_VRF18_2_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, PMIC_RG_VRF18_2_HW2_OP_CFG_MASK, PMIC_RG_VRF18_2_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, PMIC_RG_VRF18_2_GO_ON_OP_MASK, PMIC_RG_VRF18_2_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG, PMIC_RG_VRF18_2_GO_LP_OP_MASK, PMIC_RG_VRF18_2_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG_SET, PMIC_RG_VRF18_2_OP_CFG_SET_MASK, PMIC_RG_VRF18_2_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VRF18_2_OP_CFG_CLR, PMIC_RG_VRF18_2_OP_CFG_CLR_MASK, PMIC_RG_VRF18_2_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VRF12_CON0, PMIC_RG_VRF12_SW_EN_MASK, PMIC_RG_VRF12_SW_EN_SHIFT, },
+ {MT6335_LDO_VRF12_CON0, PMIC_RG_VRF12_SW_LP_MASK, PMIC_RG_VRF12_SW_LP_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, PMIC_RG_VRF12_SW_OP_EN_MASK, PMIC_RG_VRF12_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, PMIC_RG_VRF12_HW0_OP_EN_MASK, PMIC_RG_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, PMIC_RG_VRF12_HW1_OP_EN_MASK, PMIC_RG_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN, PMIC_RG_VRF12_HW2_OP_EN_MASK, PMIC_RG_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN_SET, PMIC_RG_VRF12_OP_EN_SET_MASK, PMIC_RG_VRF12_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VRF12_OP_EN_CLR, PMIC_RG_VRF12_OP_EN_CLR_MASK, PMIC_RG_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, PMIC_RG_VRF12_HW0_OP_CFG_MASK, PMIC_RG_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, PMIC_RG_VRF12_HW1_OP_CFG_MASK, PMIC_RG_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, PMIC_RG_VRF12_HW2_OP_CFG_MASK, PMIC_RG_VRF12_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, PMIC_RG_VRF12_GO_ON_OP_MASK, PMIC_RG_VRF12_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG, PMIC_RG_VRF12_GO_LP_OP_MASK, PMIC_RG_VRF12_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG_SET, PMIC_RG_VRF12_OP_CFG_SET_MASK, PMIC_RG_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VRF12_OP_CFG_CLR, PMIC_RG_VRF12_OP_CFG_CLR_MASK, PMIC_RG_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON0, PMIC_RG_VSRAM_VMD_SW_EN_MASK, PMIC_RG_VSRAM_VMD_SW_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON0, PMIC_RG_VSRAM_VMD_SW_LP_MASK, PMIC_RG_VSRAM_VMD_SW_LP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON1, PMIC_RG_VSRAM_VMD_VOSEL_MASK, PMIC_RG_VSRAM_VMD_VOSEL_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_CON2, PMIC_RG_VSRAM_VMD_VOSEL_SLEEP_MASK, PMIC_RG_VSRAM_VMD_VOSEL_SLEEP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, PMIC_RG_VSRAM_VMD_SW_OP_EN_MASK, PMIC_RG_VSRAM_VMD_SW_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, PMIC_RG_VSRAM_VMD_HW0_OP_EN_MASK, PMIC_RG_VSRAM_VMD_HW0_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, PMIC_RG_VSRAM_VMD_HW1_OP_EN_MASK, PMIC_RG_VSRAM_VMD_HW1_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN, PMIC_RG_VSRAM_VMD_HW2_OP_EN_MASK, PMIC_RG_VSRAM_VMD_HW2_OP_EN_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN_SET, PMIC_RG_VSRAM_VMD_OP_EN_SET_MASK, PMIC_RG_VSRAM_VMD_OP_EN_SET_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_EN_CLR, PMIC_RG_VSRAM_VMD_OP_EN_CLR_MASK, PMIC_RG_VSRAM_VMD_OP_EN_CLR_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, PMIC_RG_VSRAM_VMD_HW0_OP_CFG_MASK, PMIC_RG_VSRAM_VMD_HW0_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, PMIC_RG_VSRAM_VMD_HW1_OP_CFG_MASK, PMIC_RG_VSRAM_VMD_HW1_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, PMIC_RG_VSRAM_VMD_HW2_OP_CFG_MASK, PMIC_RG_VSRAM_VMD_HW2_OP_CFG_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, PMIC_RG_VSRAM_VMD_GO_ON_OP_MASK, PMIC_RG_VSRAM_VMD_GO_ON_OP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG, PMIC_RG_VSRAM_VMD_GO_LP_OP_MASK, PMIC_RG_VSRAM_VMD_GO_LP_OP_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG_SET, PMIC_RG_VSRAM_VMD_OP_CFG_SET_MASK, PMIC_RG_VSRAM_VMD_OP_CFG_SET_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_OP_CFG_CLR, PMIC_RG_VSRAM_VMD_OP_CFG_CLR_MASK, PMIC_RG_VSRAM_VMD_OP_CFG_CLR_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_DBG0, PMIC_DA_NI_VSRAM_VMD_VOSEL_GRAY_MASK, PMIC_DA_NI_VSRAM_VMD_VOSEL_GRAY_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_DBG0, PMIC_DA_NI_VSRAM_VMD_VOSEL_MASK, PMIC_DA_NI_VSRAM_VMD_VOSEL_SHIFT, },
+ {MT6335_LDO_VSRAM_VMD_DBG1, PMIC_DA_QI_VSRAM_VMD_EN_MASK, PMIC_DA_QI_VSRAM_VMD_EN_SHIFT, },
+ {MT6335_ALDO_1_ANA_CON3, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {MT6335_DLDO_ANA_CON4, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6335_DLDO_ANA_CON16, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ //{MT6335_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
+ //{MT6335_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ //{MT6335_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
+ //{MT6335_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
+ //{MT6335_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ //{MT6335_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ //{MT6335_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ //{MT6335_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ //{MT6335_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ //{MT6335_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
+ //{MT6335_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {MT6335_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6335_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6335_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
+ {MT6335_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
+};
+#endif
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic6335_37_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if(addr < PMIC6335_MAX_REG_NUM)
+ {
+ pmic6335_reg[addr] = val;
+ }
+
+ if(addr >= MT6337_PMIC_REG_BASE && addr < (MT6337_PMIC_REG_BASE + PMIC6337_MAX_REG_NUM))
+ {
+ pmic6337_reg[addr - MT6337_PMIC_REG_BASE] = val;
+ }
+
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic6335_37_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if(addr < PMIC6335_MAX_REG_NUM)
+ {
+ pmic6335_reg[addr] = val;
+ }
+
+ if(addr >= MT6337_PMIC_REG_BASE && addr < (MT6337_PMIC_REG_BASE + PMIC6337_MAX_REG_NUM))
+ {
+ pmic6337_reg[addr - MT6337_PMIC_REG_BASE] = val;
+ }
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic6335_field_write(PMIC6335_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6335_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic6335_reg[pTable[flag].offset];
+
+ pmic6335_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic6335_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6335_reg[pTable[flag].offset], 0x00);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6335_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic6335_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+}
+
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic6335_37_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC6335_MAX_REG_NUM)
+ {
+ pmic6335_reg[addr] = reg_temp;
+ }
+
+ if(addr >= MT6337_PMIC_REG_BASE && addr < (MT6337_PMIC_REG_BASE + PMIC6337_MAX_REG_NUM))
+ {
+ pmic6337_reg[addr - MT6337_PMIC_REG_BASE] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic6335_37_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC6335_MAX_REG_NUM)
+ {
+ pmic6335_reg[addr] = reg_temp;
+ }
+
+ if(addr >= MT6337_PMIC_REG_BASE && addr < (MT6337_PMIC_REG_BASE + PMIC6337_MAX_REG_NUM))
+ {
+ pmic6337_reg[addr - MT6337_PMIC_REG_BASE] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic6335_field_read(PMIC6335_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6335_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6335_reg[pTable[flag].offset]);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6335_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic6335_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic6335_37_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic6335_37_byte_write_nolock(reg, val);
+}
+
+kal_uint16 pmic6335_37_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic6335_37_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_860000_V, PMU_VOLT_02_760000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_100000_V,
+};
+
+/*2'b01: 2.375V
+ 2'b10: 2.2V*/
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_02_375000_V, PMU_VOLT_02_200000_V,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_400000_V, PMU_VOLT_00_450000_V, PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V,
+};
+
+const DCL_UINT32 vmd1_vosel[] =
+{
+ PMU_VOLT_00_400000_V, PMU_VOLT_00_450000_V, PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V,
+};
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_400000_V, PMU_VOLT_00_450000_V, PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA2), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+#endif
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMD1), vmd1_vosel, NULL, GETARRNUM(vmd1_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC6335_37_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMD1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VPA1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ case VPA2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VPA2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+#endif
+ case VMIPI:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_VMIPI_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSIM1_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSIM2_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VFE28_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VRF18_1_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VRF18_2_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VRF12_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSRAM_VMD_SW_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMD1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VSIM1_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VSIM2_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VMIPI_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VFE28_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VRF18_1_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VRF18_2_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write( MT6335_RG_VRF12_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6335_field_write(MT6335_RG_VSRAM_VMD_SW_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_RG_BUCK_VMD1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_RG_VSRAM_VMD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMD1_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSRAM_VMD_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_RG_BUCK_VMD1_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_RG_VSRAM_VMD_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMD1_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSRAM_VMD_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_VPA1_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ case VPA2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VPA2_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+#endif
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ pmic6335_37_EM_reg_write(MT6335_BUCK_VMD1_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic6335_37_EM_reg_write(MT6335_BUCK_VMODEM_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VSIM1_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VSIM2_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VMIPI_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VFE28_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VRF18_1_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VRF18_2_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VRF12_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pmic6335_37_EM_reg_write(MT6335_LDO_VSRAM_VMD_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 mode =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ kal_uint16 value =0;
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_BUCK_VMD1_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_BUCK_VMD1_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_BUCK_VMODEM_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_BUCK_VMODEM_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_LDO_VMIPI_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_LDO_VMIPI_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_LDO_VFE28_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_LDO_VFE28_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_LDO_VRF18_1_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_LDO_VRF18_1_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_LDO_VRF18_2_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_LDO_VRF18_2_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_LDO_VRF12_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_LDO_VRF12_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ value = pmic6335_37_EM_reg_read(MT6335_LDO_VSRAM_VMD_OP_CFG);
+ value &= ~((1<< HW0_OP_CFG_SHIFT)|(1<< HW1_OP_CFG_SHIFT)|(1<< HW2_OP_CFG_SHIFT));
+ value |= mode;
+ pmic6335_37_EM_reg_write(MT6335_LDO_VSRAM_VMD_OP_CFG, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_ON_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMD1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMD1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VMIPI_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VMIPI_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic6335_field_write( MT6335_RG_VSRAM_VMD_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VSRAM_VMD_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_LP_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMD1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMD1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VMIPI_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VMIPI_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VRF18_2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic6335_field_write( MT6335_RG_VSRAM_VMD_OP_CFG_SET,1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic6335_field_write( MT6335_RG_VSRAM_VMD_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VPA1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ case VPA2:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_BUCK_VPA2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+#endif
+ case VXO22:
+ {
+ dcl_pmic6335_field_write(MT6335_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_DA_NI_VMD1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_DA_NI_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6335_field_read( MT6335_DA_NI_VSRAM_VMD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SLEEP_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_VMODEM_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_VMD1_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_VSRAM_VMD_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ /*
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ */
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ pmic6335_37_EM_reg_write(MT6335_TOP_CLKSQ_SET, (0x1 << MT6335_RG_CLKSQ_EN_AUX_MD_SHIFT));
+ pmic6335_37_EM_reg_write(MT6335_AUXADC_RQST1_CLR, (pAdcCtrl->enable << MT6335_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ pmic6335_37_EM_reg_write(MT6335_AUXADC_RQST1_SET, (0x1 << MT6335_AUXADC_RQST_CH7_BY_MD_SHIFT));
+#else
+ pmic6335_37_EM_reg_write(PMIC_TOP_CLKSQ_SET_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+ pmic6335_37_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ pmic6335_37_EM_reg_write(PMIC_AUXADC_RQST1_SET_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+#endif
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic6335_field_read(MT6335_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic6335_field_read(MT6335_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ pmic6335_37_EM_reg_write(MT6335_AUXADC_RQST1_CLR, (0x1 << MT6335_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic6335_37_EM_reg_write(MT6335_TOP_CLKSQ_CLR, (0x1 << MT6335_RG_CLKSQ_EN_AUX_MD_SHIFT));
+#else
+ pmic6335_37_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic6335_37_EM_reg_write(PMIC_TOP_CLKSQ_CLR_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+#endif
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl-> mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl-> mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl-> mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic6335_field_write( MT6335_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl-> mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ /*0x2200 , 0x2202 ,0x2204, 0x2208, 0x220C,0x220E,0x2210,0x2216, 0x222C, 0x2212*/
+ if( pChrCtrl->offset == 0x2200 || pChrCtrl->offset == 0x2202 || pChrCtrl->offset == 0x2204 || pChrCtrl->offset == 0x2208 || pChrCtrl->offset == 0x220C ||
+ pChrCtrl->offset == 0x220E || pChrCtrl->offset == 0x2210 || pChrCtrl->offset == 0x2216 || pChrCtrl->offset == 0x222C || pChrCtrl->offset == 0x2212 )
+ {
+ pmic6335_37_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+ else
+ ASSERT(0);
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic6335_37_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic6335_37_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ ASSERT(0);
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic6335_37_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic6335_modem_only_init(void);
+extern void dcl_pmic6335_modem_only_init_v1(void);
+extern void dcl_pmic6337_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic6335_37_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic6335_37_byte_write(pmic_addr, value);
+}
+
+
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+void DRV_Configure_Modem_Related_Buck(void)
+{
+ //Configure V_MD1 as 0.8V, V_MODEM as 0.8V, V_SRAM as 0.9V
+ //0x0E5E RG_BUCK_VMD1_VOSEL 0x40 (0x40*0.00625+0.4 =0.8V)
+ //0x0E60 RG_BUCK_VMD1_VOSEL_SLEEP 0x0 (0x0 *0.00625+0.4 =0.4V)
+ //0x0E80 RG_BUCK_VMODEM_VOSEL 0x40 (0x40*0.00625+0.4 =0.8V
+ //0x0E82 RG_BUCK_VMODEM_VOSEL_SLEEP 0x0 (0x0 *0.00625+0.4 =0.4V)
+ //0x171A RG_VSRAM_VMD_VOSEL 0x50 (0x50*0.00625+0.4 =0.9V)
+ //0x171C RG_VSRAM_VMD_VOSEL_SLEEP 0x0 (0x0 *0.00625+0.4 =0.4V)
+
+ DRV_Write_PMIC_Data(0x0E5E, 0x40);
+ DRV_Write_PMIC_Data(0x0E80, 0x40);
+ DRV_Write_PMIC_Data(0x171A, 0x50);
+}
+
+kal_uint32 vmd1, vmodem, vsram_vmd;
+void DRV_Dump_Modem_Related_Buck(void)
+{
+// kal_uint32 vmd1,vmodem,vsram_vmd;
+
+ //0x0E78 6 0 DA_NI_VMD1_VOSEL RO PRIVATE BUCK VMD1 VOUT selection in binary format VOUT = 0.4V + 6.25mV * VOSEL
+ //0x0E9A 6 0 DA_NI_VMODEM_VOSEL RO PRIVATE BUCK VMODEM VOUT selection in binary format VOUT = 0.4V + 6.25mV * VOSEL
+ //0x1734 LDO_VSRAM_VMD_DBG0 16 LDO VSRAM_VMD DEBUG 0 DA_NI_VSRAM_VMD_VOSEL_GRAY RO PRIVATE
+
+ vmd1 = DRV_Read_PMIC_Data(0x0E78);
+ vmodem = DRV_Read_PMIC_Data(0x0E9A);
+ vsram_vmd = DRV_Read_PMIC_Data(0x1734);
+}
+#endif
+void dcl_pmic6335_37_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC6335_37_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic6335_hw_version = PMIC_ECO_E1;
+ pmic6335_sw_version = PMIC_ECO_E1;
+ pmic6337_hw_version = PMIC_ECO_E1;
+ pmic6337_sw_version = PMIC_ECO_E1;
+
+ // Get MT6335/MT6337 ECO version
+ {
+ kal_uint16 pmic6335_hw_eco_version = 0;
+ kal_uint16 pmic6335_sw_eco_version = 0;
+ kal_uint16 pmic6337_hw_eco_version = 0;
+ kal_uint16 pmic6337_sw_eco_version = 0;
+ pmic6335_hw_eco_version = dcl_pmic6335_37_byte_return(MT6335_HWCID);
+ pmic6337_hw_eco_version = dcl_pmic6335_37_byte_return(MT6337_HWCID);
+ pmic6335_sw_eco_version = dcl_pmic6335_37_byte_return(MT6335_SWCID);
+ pmic6337_sw_eco_version = dcl_pmic6335_37_byte_return(MT6337_SWCID);
+
+ if (pmic6335_hw_eco_version == MT6335_HW_CID_E1)
+ {
+ pmic6335_hw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6335_hw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6335_sw_eco_version == MT6335_SW_CID_E1)
+ {
+ pmic6335_sw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6335_sw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6337_hw_eco_version == MT6337_SW_CID_E1)
+ {
+ pmic6337_hw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6337_hw_version = PMIC_ECO_E2;
+ }
+
+ if (pmic6337_sw_eco_version == MT6335_SW_CID_E1)
+ {
+ pmic6337_sw_version = PMIC_ECO_E1;
+ }
+ else
+ {
+ pmic6337_sw_version = PMIC_ECO_E2;
+ }
+ }
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6335_modem_only_init();
+ else
+*/
+ dcl_pmic6335_modem_only_init_v1();
+
+ dcl_pmic6337_modem_only_init();
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+#if defined (DRV_PMIC_WRAP_ELBRUS_REG)
+ DRV_Configure_Modem_Related_Buck();
+ DRV_Dump_Modem_Related_Buck();
+#endif
+
+}
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+
+void PMIC_Read_All(void)
+{
+
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC6335_MAX_REG_NUM; i += 2){
+ pmic6335_reg[i] = dcl_pmic6335_37_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+
+ for (i = MT6337_PMIC_REG_BASE; i < (MT6337_PMIC_REG_BASE + PMIC6337_MAX_REG_NUM); i += 2){
+ pmic6337_reg[i - MT6337_PMIC_REG_BASE] = dcl_pmic6335_37_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#endif
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6335_REG_API) || defined(PMIC_6337_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6335_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6335_init.c
new file mode 100644
index 0000000..925f2ed
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6335_init.c
@@ -0,0 +1,152 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6335_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6335
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6335 ECO_E1
+void dcl_pmic6335_modem_only_init(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+}
+
+void dcl_pmic6335_modem_only_init_v1(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6337_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6337_init.c
new file mode 100644
index 0000000..1801a75
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6337_init.c
@@ -0,0 +1,179 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6337_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6337
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+static void PMIC_DRV_SetData(DCL_UINT32 addr, DCL_UINT32 bitmask, DCL_UINT16 value, DCL_UINT32 bank)
+{
+ DCL_UINT32 temp;
+ addr |= (bank << 31);
+ temp = (~(bitmask)) & DRV_Read_PMIC_Data(addr);
+ temp |= ((value) & (bitmask));
+ DRV_Write_PMIC_Data(addr,temp);
+}
+
+void dcl_pmic6337_modem_only_init(void)
+{
+ // RG_SRCLKEN_IN0_HW_MODE[4:4] = 0x1 => Joseph/ OSC CLK wi SRCLKEN
+ PMIC_DRV_SetData(0x8006 , 0x10 , 0x10 , 0x0);
+
+ // RG_VOWEN_HW_MODE[5:5] = 0x1 => Joseph/ OSC CLK wi SRCLKEN
+ PMIC_DRV_SetData(0x8006 , 0x20 , 0x20 , 0x0);
+
+ // RG_OSC_SEL_HW_MODE[6:6] = 0x1 => Joseph/ OSC CLK wi SRCLKEN
+ PMIC_DRV_SetData(0x8006 , 0x40 , 0x40 , 0x0);
+
+ // RG_TRIM_75K_CK_PDN[4:4] = 0x1 => Joseph/power down (FT trim use)
+ PMIC_DRV_SetData(0x8200 , 0x10 , 0x10 , 0x0);
+
+ // RG_AUDIF_CK_PDN[11:11] = 0x1 => Joseph/power down
+ PMIC_DRV_SetData(0x8200 , 0x800 , 0x800 , 0x0);
+
+ // RG_INTRP_PRE_OC_CK_PDN[3:3] = 0x1 => Joseph/power down (37 no use)
+ PMIC_DRV_SetData(0x8206 , 0x8 , 0x8 , 0x0);
+
+ // RG_LDO_CALI_75K_CK_PDN[8:8] = 0x1 => Joseph/power down (37 no use)
+ PMIC_DRV_SetData(0x8206 , 0x100 , 0x100 , 0x0);
+
+ // RG_ACCDET_CK_PDN[11:11] = 0x0 => Joseph/power on (ACCDET use)
+ PMIC_DRV_SetData(0x8206 , 0x800 , 0x0 , 0x0);
+
+ // RG_REG_CK_PDN_HWEN[7:7] = 0x1 => Joseph/RG CLK HW
+ PMIC_DRV_SetData(0x8218 , 0x80 , 0x80 , 0x0);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+ // RG_VA18_HW0_OP_EN[1:1] = 0x1 => Joseph/LDO LP wi SRCLKEN
+ PMIC_DRV_SetData(0x9008 , 0x2 , 0x2 , 0x0);
+
+ // RG_VA18_HW0_OP_CFG[1:1] = 0x1 => Joseph/LDO LP wi SRCLKEN
+ PMIC_DRV_SetData(0x900E , 0x2 , 0x2 , 0x0);
+
+ // AUXADC_AVG_NUM_LARGE[5:3] = 0x7 => Jyun-Jia/256 average
+ PMIC_DRV_SetData(0x943A , 0x38 , 0x38 , 0x0);
+
+ // AUXADC_TRIM_CH3_SEL[7:6] = 0x0 => Jyun-Jia/ efuse ch0
+ PMIC_DRV_SetData(0x9444 , 0xC0 , 0x0 , 0x0);
+
+ // AUXADC_TRIM_CH4_SEL[9:8] = 0x1 => Jyun-Jia/ efuse ch4
+ PMIC_DRV_SetData(0x9444 , 0x300 , 0x100 , 0x0);
+
+ // AUXADC_TRIM_CH5_SEL[11:10] = 0x2 => Jyun-Jia/ efuse ch7
+ PMIC_DRV_SetData(0x9444 , 0xC00 , 0x800 , 0x0);
+
+ // AUXADC_TRIM_CH6_SEL[13:12] = 0x0 => Jyun-Jia/ efuse ch0
+ PMIC_DRV_SetData(0x9444 , 0x3000 , 0x0 , 0x0);
+
+ // AUXADC_TRIM_CH7_SEL[15:14] = 0x2 => Jyun-Jia/ efuse ch7
+ PMIC_DRV_SetData(0x9444 , 0xC000 , 0x8000 , 0x0);
+
+ // AUXADC_TRIM_CH9_SEL[3:2] = 0x2 => Jyun-Jia/ efuse ch7
+ PMIC_DRV_SetData(0x9446 , 0xC , 0x8 , 0x0);
+
+ // AUXADC_TRIM_CH12_SEL[9:8] = 0x2 => Jyun-Jia/ efuse ch7
+ PMIC_DRV_SetData(0x9446 , 0x300 , 0x200 , 0x0);
+
+ // GPIO_PULLEN0[10:0] = 0x0 => Joseph/ no pull
+ PMIC_DRV_SetData(0x9C06 , 0x7FF , 0x0 , 0x0);
+
+ // GPIO8_MODE[11:9] = 0x1 => Joseph/ MTKIF
+ PMIC_DRV_SetData(0x9C28 , 0xE00 , 0x200 , 0x0);
+
+ // GPIO9_MODE[14:12] = 0x1 => Joseph/ MTKIF
+ PMIC_DRV_SetData(0x9C28 , 0x7000 , 0x1000 , 0x0);
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6339.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6339.c
new file mode 100644
index 0000000..ae665fd
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6339.c
@@ -0,0 +1,730 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6339.c
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * This is pmic6339 driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ ****************************************************************************/
+
+#include "reg_base.h"
+#include "intrCtrl.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "kal_public_api.h"
+#include "drv_bsi.h"
+#include "i2c_pmic.h"
+
+#define PMIC_MAX_REG_NUM PMIC_REG_NUM
+
+#ifdef PMIC_6339_DEBUG
+static kal_uint16 pmic6339_reg[PMIC_MAX_REG_NUM];
+#endif
+
+static const DCL_UINT32 vio28_vosel[] =
+{
+ PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
+};
+
+static const DCL_UINT32 vcore_vosel[]=
+{
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_725000_V, PMU_VOLT_00_775000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_875000_V, PMU_VOLT_00_850000_V, PMU_VOLT_00_800000_V, PMU_VOLT_00_825000_V,
+ PMU_VOLT_01_075000_V, PMU_VOLT_01_050000_V, PMU_VOLT_01_000000_V, PMU_VOLT_01_025000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_00_925000_V, PMU_VOLT_00_975000_V, PMU_VOLT_00_950000_V,
+ PMU_VOLT_01_475000_V, PMU_VOLT_01_450000_V, PMU_VOLT_01_400000_V, PMU_VOLT_01_425000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_325000_V, PMU_VOLT_01_375000_V, PMU_VOLT_01_350000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_125000_V, PMU_VOLT_01_175000_V, PMU_VOLT_01_150000_V,
+ PMU_VOLT_01_275000_V, PMU_VOLT_01_250000_V, PMU_VOLT_01_200000_V, PMU_VOLT_01_225000_V,
+};
+
+static const DCL_UINT32 vsim_vosel[] =
+{
+ PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
+};
+
+static const DCL_UINT32 vmc_io_vosel[] =
+{
+ PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_02_000000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
+};
+
+static const DCL_UINT32 vmch_vosel[] =
+{
+ PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
+};
+
+static const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VIO28), vio28_vosel, NULL, GETARRNUM(vio28_vosel)},
+ {ENC(LDO_BUCK_SET_VOLTAGE, VCORE), vcore_vosel, NULL, GETARRNUM(vcore_vosel)},
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM), vsim_vosel, NULL, GETARRNUM(vsim_vosel)},
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim_vosel, NULL, GETARRNUM(vsim_vosel)},
+ {ENC(LDO_BUCK_SET_VOLTAGE, VMC), vmc_io_vosel, NULL, GETARRNUM(vmc_io_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VMCH), vmch_vosel, NULL, GETARRNUM(vmch_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(VPA_SET_VOLTAGE_SELECTION_TABLE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+};
+DCL_UINT16 pmu_parameter_size=0;
+DCL_UINT16 pmic_CID0 = 0xFFFF;
+DCL_UINT16 pmic_ECO_VERSION = 0xFFFF;
+
+
+const PMU_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {CID0, CID0_ADDR, CID0_MASK, CID0_SHIFT},
+ {ECO_VERSION, ECO_VERSION_ADDR, ECO_VERSION_MASK, ECO_VERSION_SHIFT},
+ {RG_VIO28_VOSEL, RG_VIO28_VOSEL_ADDR, RG_VIO28_VOSEL_MASK, RG_VIO28_VOSEL_SHIFT},
+ {RG_VIO28_EN, RG_VIO28_EN_ADDR, RG_VIO28_EN_MASK, RG_VIO28_EN_SHIFT},
+ {RG_VUSB11_EN, RG_VUSB11_EN_ADDR, RG_VUSB11_EN_MASK, RG_VUSB11_EN_SHIFT},
+ {RG_VCORE_VOSEL, RG_VCORE_VOSEL_ADDR, RG_VCORE_VOSEL_MASK, RG_VCORE_VOSEL_SHIFT},
+ {RG_VRF18_MODESET, RG_VRF18_MODESET_ADDR, RG_VRF18_MODESET_MASK, RG_VRF18_MODESET_SHIFT},
+ {RG_VRF18_ON_CTRL, RG_VRF18_ON_CTRL_ADDR, RG_VRF18_ON_CTRL_MASK, RG_VRF18_ON_CTRL_SHIFT},
+ {RG_VRF18_EN, RG_VRF18_EN_ADDR, RG_VRF18_EN_MASK, RG_VRF18_EN_SHIFT},
+ {VRF18_srclken_sel, VRF18_srclken_sel_ADDR, VRF18_srclken_sel_MASK, VRF18_srclken_sel_SHIFT},
+ {RG_VRF18_2_MODESET, RG_VRF18_2_MODESET_ADDR, RG_VRF18_2_MODESET_MASK, RG_VRF18_2_MODESET_SHIFT},
+ {RG_VRF18_2_ON_CTRL, RG_VRF18_2_ON_CTRL_ADDR, RG_VRF18_2_ON_CTRL_MASK, RG_VRF18_2_ON_CTRL_SHIFT},
+ {RG_VRF18_2_EN, RG_VRF18_2_EN_ADDR, RG_VRF18_2_EN_MASK, RG_VRF18_2_EN_SHIFT},
+ {VRF18_2_srclken_sel, VRF18_2_srclken_sel_ADDR, VRF18_2_srclken_sel_MASK, VRF18_2_srclken_sel_SHIFT},
+ {RG_VPA_MODESET, RG_VPA_MODESET_ADDR, RG_VPA_MODESET_MASK, RG_VPA_MODESET_SHIFT},
+ {VPA_VOSEL_MAP_EN, VPA_VOSEL_MAP_EN_ADDR, VPA_VOSEL_MAP_EN_MASK, VPA_VOSEL_MAP_EN_SHIFT},
+ {RG_VPA_EN, RG_VPA_EN_ADDR, RG_VPA_EN_MASK, RG_VPA_EN_SHIFT},
+ {VPA_VOSEL, VPA_VOSEL_ADDR, VPA_VOSEL_MASK, VPA_VOSEL_SHIFT},
+ {RG_VRF18_BK_LDO, RG_VRF18_BK_LDO_ADDR, RG_VRF18_BK_LDO_MASK, RG_VRF18_BK_LDO_SHIFT},
+ {RG_VRF18_2_BK_LDO, RG_VRF18_2_BK_LDO_ADDR, RG_VRF18_2_BK_LDO_MASK, RG_VRF18_2_BK_LDO_SHIFT},
+ {RG_VSIM1_EN, RG_VSIM1_EN_ADDR, RG_VSIM1_EN_MASK, RG_VSIM1_EN_SHIFT},
+ {RG_VSIM2_EN, RG_VSIM2_EN_ADDR, RG_VSIM2_EN_MASK, RG_VSIM2_EN_SHIFT},
+ {RG_VSIM1_VOSEL, RG_VSIM1_VOSEL_ADDR, RG_VSIM1_VOSEL_MASK, RG_VSIM1_VOSEL_SHIFT},
+ {RG_VSIM2_VOSEL, RG_VSIM2_VOSEL_ADDR, RG_VSIM2_VOSEL_MASK, RG_VSIM2_VOSEL_SHIFT},
+ {RG_VMC_VOSEL, RG_VMC_VOSEL_ADDR, RG_VMC_VOSEL_MASK, RG_VMC_VOSEL_SHIFT},
+ {RG_VMC_EN, RG_VMC_EN_ADDR, RG_VMC_EN_MASK, RG_VMC_EN_SHIFT},
+ {RG_VMCH_VOSEL, RG_VMCH_VOSEL_ADDR, RG_VMCH_VOSEL_MASK, RG_VMCH_VOSEL_SHIFT},
+ {RG_VMCH_EN, RG_VMCH_EN_ADDR, RG_VMCH_EN_MASK, RG_VMCH_EN_SHIFT},
+ {RG_VMIPI_EN, RG_VMIPI_EN_ADDR, RG_VMIPI_EN_MASK, RG_VMIPI_EN_SHIFT},
+ {VPA_TABLE0, VPA_TABLE0_ADDR, VPA_TABLE0_MASK, VPA_TABLE0_SHIFT},
+ {VPA_TABLE1, VPA_TABLE1_ADDR, VPA_TABLE1_MASK, VPA_TABLE1_SHIFT},
+ {VPA_TABLE2, VPA_TABLE2_ADDR, VPA_TABLE2_MASK, VPA_TABLE2_SHIFT},
+ {VPA_TABLE3, VPA_TABLE3_ADDR, VPA_TABLE3_MASK, VPA_TABLE3_SHIFT},
+ {VPA_TABLE4, VPA_TABLE4_ADDR, VPA_TABLE4_MASK, VPA_TABLE4_SHIFT},
+ {VPA_TABLE5, VPA_TABLE5_ADDR, VPA_TABLE5_MASK, VPA_TABLE5_SHIFT},
+ {VPA_TABLE6, VPA_TABLE6_ADDR, VPA_TABLE6_MASK, VPA_TABLE6_SHIFT},
+ {VPA_TABLE7, VPA_TABLE7_ADDR, VPA_TABLE7_MASK, VPA_TABLE7_SHIFT},
+ {VPA_MAP_SEL, VPA_MAP_SEL_ADDR, VPA_MAP_SEL_MASK, VPA_MAP_SEL_SHIFT},
+};
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+// Write Whole Bytes
+static void dcl_pmic6339_write_reg(DCL_UINT8 addr, DCL_UINT16 val)
+{
+ drv_bsi_pmic6339_reg_write(addr,val);
+ #ifdef PMIC_6339_DEBUG
+ pmic6339_reg[addr]=val;
+ #endif
+}
+
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+static DCL_UINT16 dcl_pmic6339_read_reg(DCL_UINT8 addr)
+{
+ kal_uint16 val;
+ val=drv_bsi_pmic6339_reg_read(addr);
+ #ifdef PMIC_6339_DEBUG
+ pmic6339_reg[addr]=val;
+ #endif
+ return val;
+}
+
+// Write register field
+static void dcl_pmic6339_field_write(PMU_FLAGS_LIST_ENUM flag, kal_uint16 sel)
+{
+ kal_uint32 i, table_size = 0,mask;
+ kal_uint16 val;
+
+ table_size = GETARRNUM(pmic_flags_table);
+ for (i = 0; i < table_size; i++)
+ {
+ if (flag == pmic_flags_table[i].flagname)
+ {
+ break;
+ }
+ }
+ if (i >= table_size){ ASSERT(0); }// Flag Unknown
+
+ mask=SaveAndSetIRQMask();
+ val=dcl_pmic6339_read_reg(pmic_flags_table[i].offset)&(~(pmic_flags_table[i].mask));
+ val|=(sel<<pmic_flags_table[i].shift)&pmic_flags_table[i].mask;
+ dcl_pmic6339_write_reg(pmic_flags_table[i].offset,val);
+ RestoreIRQMask(mask);
+ return;
+}
+DCL_STATUS PMIC6339_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+ {
+ dcl_pmic6339_field_write(RG_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VRF18_2:
+ {
+ dcl_pmic6339_field_write(RG_VRF18_2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VSIM:
+ {
+ dcl_pmic6339_field_write(RG_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VSIM2:
+ {
+ dcl_pmic6339_field_write(RG_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMC:
+ {
+ dcl_pmic6339_field_write(RG_VMC_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMCH:
+ {
+ dcl_pmic6339_field_write(RG_VMCH_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMIPI:
+ {
+ dcl_pmic6339_field_write(RG_VMIPI_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VIO28:
+ {
+ dcl_pmic6339_field_write(RG_VIO28_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VCORE:
+ {
+ dcl_pmic6339_field_write(RG_VCORE_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VSIM:
+ {
+ dcl_pmic6339_field_write(RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VSIM2:
+ {
+ dcl_pmic6339_field_write(RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMC:
+ {
+ dcl_pmic6339_field_write(RG_VMC_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMCH:
+ {
+ dcl_pmic6339_field_write(RG_VMCH_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VPA:
+ {
+ dcl_pmic6339_field_write(VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+ case VRF18_SET_BUCK_LDO_MODE:
+ {
+ PMU_CTRL_VRF18_SET_BUCK_LDO_MODE *pVrf18Ctrl = &(data->rPMUVrf18SetBuckLdoMode);
+ switch(pVrf18Ctrl->vrf18Idx)
+ {
+ case PMIC_VRF18_1:
+ {
+ dcl_pmic6339_field_write(RG_VRF18_BK_LDO, pVrf18Ctrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case PMIC_VRF18_2:
+ {
+ dcl_pmic6339_field_write(RG_VRF18_2_BK_LDO, pVrf18Ctrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+ case VRF18_SET_FPWM:
+ {
+ PMU_CTRL_VRF18_SET_FPWM *pVrf18SetFpwm = (PMU_CTRL_VRF18_SET_FPWM *)data;
+ dcl_pmic6339_field_write(RG_VRF18_MODESET, pVrf18SetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VRF18_2_SET_FPWM:
+ {
+ PMU_CTRL_VRF18_SET_FPWM *pVrf18SetFpwm = (PMU_CTRL_VRF18_SET_FPWM *)data;
+ dcl_pmic6339_field_write(RG_VRF18_2_MODESET, pVrf18SetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VPA_SET_FPWM:
+ {
+ PMU_CTRL_VPA_SET_FPWM *pVpaSetFpwm = (PMU_CTRL_VPA_SET_FPWM *)data;
+ dcl_pmic6339_field_write(RG_VPA_MODESET, pVpaSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case LDO_BUCK_SET_ON_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_ON_SEL *pLdoBuckCtrl=&(data->rPMULdoBuckSetOnSel);
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+ {
+ // ENABLE_WITH_SRCLKEN = 0, but 6329 SRCLKEN = 1, therefore we need NOT pLdoBuckCtrl->onsel
+ dcl_pmic6339_field_write(RG_VRF18_ON_CTRL, !(pLdoBuckCtrl->onSel));
+ return_val = STATUS_OK;
+ }
+ break;
+ case VRF18_2:
+ {
+ // ENABLE_WITH_SRCLKEN = 0, but 6329 SRCLKEN = 1, therefore we need NOT pLdoBuckCtrl->onsel
+ dcl_pmic6339_field_write(RG_VRF18_2_ON_CTRL, !(pLdoBuckCtrl->onSel));
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+ case LDO_BUCK_SET_SRCLKEN_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SRCLKEN_SEL *pLdoBuckCtrl=&(data->rPMULdoBuckSetSrclkenSel);
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+ {
+ dcl_pmic6339_field_write(VRF18_srclken_sel, pLdoBuckCtrl->SrclkenSel);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VRF18_2:
+ {
+ dcl_pmic6339_field_write(VRF18_2_srclken_sel, pLdoBuckCtrl->SrclkenSel);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaCtrl = &(data->rPMUVpaSetEn);
+ dcl_pmic6339_field_write(RG_VPA_EN, pVpaCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VPA_SET_VOSEL_MAP_EN:
+ {
+ PMU_CTRL_VPA_SET_VOSEL_MAP_EN *pVpaCtrl = &(data->rPMUVpaSetVoselMapEn);
+ dcl_pmic6339_field_write(VPA_VOSEL_MAP_EN, pVpaCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VPA_SET_VOLTAGE_SELECTION_TABLE:
+ {
+ PMU_CTRL_VPA_SET_VOLTAGE_SELECTION_TABLE *pVpaCtrl = &(data->rPMUVpaSetVoltageSelectionTable);
+ regVal = PMU_Parameter_to_Value(ENC(VPA_SET_VOLTAGE_SELECTION_TABLE, VPA), pVpaCtrl->voltage);
+ switch(pVpaCtrl->table_entry)
+ {
+ case PMU_VPA0:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE0, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case PMU_VPA1:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE1, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case PMU_VPA2:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE2, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMU_VPA3:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE3, regVal);
+ return_val = STATUS_OK;
+ }
+
+ break;
+ case PMU_VPA4:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE4, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case PMU_VPA5:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE5, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case PMU_VPA6:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE6, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ case PMU_VPA7:
+ {
+ dcl_pmic6339_field_write(VPA_TABLE7, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+
+ }
+ break;
+
+ case VPA_SET_MAP_SEL:
+ {
+ PMU_CTRL_VPA_SET_MAP_SEL *pVpaCtrl = &(data->rPMUVpaSetMapSel);
+ dcl_pmic6339_field_write(VPA_MAP_SEL, pVpaCtrl->table_entry);
+ }
+ break;
+
+
+/* case VPA_SET_VOLTAGE: // VPA voltage will be auto set by HW, this command is not necessary for HW driver
+ {
+ PMU_CTRL_VPA_SET_VOLTAGE *pVpaCtrl = &(data->rPMUVpaSetVoltage);
+
+ regVal = PMU_Parameter_to_Value(ENC(cmd,0), pVpaCtrl->voltage);
+ dcl_pmic6339_field_write(VPA_VOSEL, regVal);
+ }
+ break;*/
+ case MISC_GET_CID:
+ {
+ PMU_CTRL_MISC_GET_CID *pMiscCtrl = &(data->rPMUMiscGetCid);
+ pMiscCtrl->cid_value = pmic_CID0;
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_ECO_VERSION:
+ {
+ PMU_CTRL_MISC_GET_ECO_VERSION *pMiscCtrl = &(data->rPMUMiscGetEcoVersion);
+ pMiscCtrl->eco_version = pmic_ECO_VERSION;
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+ dcl_pmic6339_write_reg(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = dcl_pmic6339_read_reg(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ return return_val;
+
+}
+
+// extern void dcl_pmic6339_internal_init(void); // Move to bootloader
+extern void pmu_drv_tool_customization_init(void);
+extern void PMIC_Read_All(void);
+extern void PMIC_VCORE_INIT(kal_uint32 value, kal_uint32 ver);
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+//DCL_UINT16 pmu_parameter_size=0;
+
+void dcl_pmic6339_init(void){
+ static kal_uint8 pmic6339_init=0;
+ if(0==pmic6339_init){
+ pmu_control_handler = PMIC6339_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+ pmic6339_init=1;
+ drv_bsi_pmic_init();//init BSI
+ pmic_CID0 = dcl_pmic6339_read_reg(CID0_ADDR);
+ pmic_ECO_VERSION = dcl_pmic6339_read_reg(ECO_VERSION_ADDR);
+ if(pmic_ECO_VERSION == 0x01)
+ {
+ // Turn on VIO28_EN as long as E1.
+ dcl_pmic6339_field_write(RG_VIO28_EN, 0x01);
+ }
+#if defined(PMIC_INIT_PHONE)
+#if !defined(MT6290M_SP_BB) && !defined(MT6290ME2_SP)
+ // Turn off VUSB11 for Custom Phone Project
+ dcl_pmic6339_field_write(RG_VUSB11_EN, 0x00);
+#endif
+#endif
+ // dcl_pmic6339_internal_init(); // Move to bootloader
+// pmic6339_customization_init();
+ pmu_drv_tool_customization_init();
+ #ifdef PMIC_6339_DEBUG
+ {
+ kal_uint32 i;
+ for (i = 0;i < PMIC_MAX_REG_NUM;i++){
+ pmic6339_reg[i] = dcl_pmic6339_read_reg(i);
+ }
+ }
+ #endif
+ }
+}
+
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i++){
+ pmic6339_reg[i] = dcl_pmic6339_read_reg(i);
+ }
+}
+#if defined(MT6290_DEMO_BB) || defined(MT6290M_DEMO_BB) || defined(MT6290E2_EVB) || defined(MT6290ME2_EVB) // EVB
+void PMIC_VCORE_INIT(kal_uint32 value, kal_uint32 ver)
+{
+ value = 0;
+ ver = 0;
+}
+#else
+extern const char EXTbuck_i2cdev_exist;
+void PMIC_VCORE_INIT(kal_uint32 value, kal_uint32 ver)
+{
+#include "i2c_pmic.h"
+#define NCP6335_SLAVE_ADDR 0x1C
+ kal_uint8 val;
+ I2C_STATUS sts;
+ int gpio15;
+ GPIO_CTRL_READ_T data;
+ DCL_HANDLE handle = DclGPIO_Open(DCL_GPIO, EXTbuck_i2cdev_exist & (~0x80));
+ DclGPIO_Control(handle, GPIO_CMD_READ, (DCL_CTRL_DATA_T *)&data);
+ gpio15 = data.u1IOData;
+
+ if(gpio15 == 1)
+ {
+ DclGPIO_Control(handle,GPIO_CMD_SET_PULL_HIGH, (DCL_CTRL_DATA_T *)&data);
+ }
+ /* read NCP6335 reg 0*/
+ sts = i2c_pmic_reg_read(NCP6335_SLAVE_ADDR , 0x0 , &val);
+ if (sts == I2C_ACKERR)
+ {
+ /*
+ * Error Handing.
+ * ¨Ò¦p ¦pªG¬OACK_ERR , ¥i¥H¦AŪ¤@¦¸double check ¤@¤U ¡A ¦pªGÁÙ¬OACK_ERR , ¥i»{¬° slave ¤£¦s¦b
+ */
+ sts = i2c_pmic_reg_read(NCP6335_SLAVE_ADDR , 0x0 , &val);
+ if(sts == I2C_ACKERR)
+ {
+ if(ver == 1 && gpio15 == 1)
+ {
+ ASSERT(0);
+ }
+ else
+ {
+ // NCP6335 Not Exist
+ switch(value)
+ {
+ case 0:
+ case 1:
+ dcl_pmic6339_write_reg(0x65, 0x09); // 1.05V
+ break;
+ case 2:
+ case 3:
+ dcl_pmic6339_write_reg(0x65, 0x0A); // 1.0V
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ else if(sts == I2C_PASS)
+ {
+ // NCP6335 Exist
+ // 1.05V, Depend on binning IC E-fuse
+ i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x10, 0xC8);
+ // 0.85V, initial setting
+ i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x11, 0xA8);
+ // Common register initial
+ i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x14, 0x01);
+ switch(value)
+ {
+ case 0:
+ case 1:
+ i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x10, 0xC8); // 1.05V
+ dcl_pmic6339_write_reg(0x65, 0x09); // 1.05V
+ //dcl_pmic6339_write_reg(0x63, 0x00); // Shutdown VCORE
+ break;
+ case 2:
+ case 3:
+ i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x10, 0xC0); // 1.00V
+ dcl_pmic6339_write_reg(0x65, 0x0A); // 1.0V
+ //dcl_pmic6339_write_reg(0x63, 0x00); // Shutdown VCORE
+ break;
+ default:
+ break;
+ }
+ }
+ else if(sts == I2C_FAIL)
+ {
+ ASSERT(0);
+ }
+
+}
+#endif // End of #if defined(MT6290_DEMO_BB) || defined(MT6290M_DEMO_BB) || defined(MT6290E2_EVB) || defined(MT6290ME2_EVB) // EVB
\ No newline at end of file
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6339_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6339_init.c
new file mode 100644
index 0000000..22f6aaf
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6339_init.c
@@ -0,0 +1,444 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmu_init.c
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * This file provide for pmu initial setting
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#include "init.h"
+#include "dcl.h"
+#include "drv_bsi.h"
+
+//#define PMIC_INIT_FOR_DRVTEST
+
+static void PMIC_DRV_SetData(DCL_UINT32 addr, DCL_UINT32 bitmask, DCL_UINT16 value, DCL_UINT32 bank)
+{
+ DCL_UINT32 temp;
+ temp = (~(bitmask)) & drv_bsi_pmic6339_reg_read(addr);
+ temp |= ((value) & (bitmask));
+ drv_bsi_pmic6339_reg_write(addr,temp);
+}
+
+//MT6339_E1_20130722_I_phone_initial_setting_LPG.txt
+void dcl_pmic_internal_init(void)
+{
+#if defined(PMIC_INIT_PHONE)
+//debug_MT6339 Register Mapping E1 20130724_I_phone_initial_setting_LPG.txt
+ {
+ //<ECO_E1>
+ //address,mask,value,ap shift,ap mask,ap value, bank
+ PMIC_DRV_SetData(0x0010,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0015,0x3,0x2,0x0); // UVLO 2.6V
+ PMIC_DRV_SetData(0x0021,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0024,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0024,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x0029,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002A,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0032,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0038,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x003B,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0044,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x0044,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0048,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0049,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004E,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0056,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0057,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0066,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0066,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0066,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0066,0x8,0x0,0x0);
+ PMIC_DRV_SetData(0x0066,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x0067,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0067,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x006C,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x007C,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x40,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0081,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0081,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0081,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0081,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0081,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0090,0x100,0x0,0x0);
+ PMIC_DRV_SetData(0x0090,0x200,0x200,0x0);
+ PMIC_DRV_SetData(0x0090,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x0090,0x8000,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0095,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x80,0x80,0x0);
+ PMIC_DRV_SetData(0x0095,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x0095,0x200,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x8000,0x8000,0x0);
+ PMIC_DRV_SetData(0x009C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x00AA,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C0,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x00C0,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x00C0,0x1000,0x1000,0x0);
+ PMIC_DRV_SetData(0x00C0,0x4000,0x0,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C2,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x00C2,0x400,0x400,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x00C8,0x20,0x20,0x0);
+ PMIC_DRV_SetData(0x00D6,0x10,0x10,0x0);
+ }
+#elif defined(PMIC_INIT_DONGLE)
+//debug_MT6339 Register Mapping E1 20130724_I_dongle_intial_setting_LPG.txt
+ {
+ //<ECO_E1>
+ //address,mask,value,ap shift,ap mask,ap value, bank
+ PMIC_DRV_SetData(0x0010,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0021,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0024,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0024,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x0029,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002A,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x003B,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0044,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x0044,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0048,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0049,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004E,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0054,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0056,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0057,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0066,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0066,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0066,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0066,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0066,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x0067,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0067,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x006C,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0090,0x100,0x0,0x0);
+ PMIC_DRV_SetData(0x0090,0x200,0x200,0x0);
+ PMIC_DRV_SetData(0x0090,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x0090,0x8000,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0095,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x80,0x80,0x0);
+ PMIC_DRV_SetData(0x0095,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x0095,0x200,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x8000,0x8000,0x0);
+ PMIC_DRV_SetData(0x009C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x00AA,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C0,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x00C0,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x00C0,0x1000,0x1000,0x0);
+ PMIC_DRV_SetData(0x00C0,0x4000,0x0,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C2,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x00C2,0x400,0x400,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x00C8,0x20,0x20,0x0);
+ PMIC_DRV_SetData(0x00D6,0x10,0x10,0x0);
+ }
+#elif defined(PMIC_INIT_DONGLE_ON_EVB)
+//debug_MT6339 Register Mapping E1 20130724_I_EVB_dongle_initial_setting_LPG.txt
+ {
+ //<ECO_E1>
+ //address,mask,value,ap shift,ap mask,ap value, bank
+ PMIC_DRV_SetData(0x0010,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0021,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0024,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0024,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x0029,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002A,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x003B,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0044,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x0044,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0048,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0049,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004E,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0056,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0057,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0065,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0065,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0066,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0066,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0066,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0066,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0066,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x0067,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0067,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x006C,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x007C,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x40,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0081,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0081,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0081,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0081,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0081,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0090,0x100,0x0,0x0);
+ PMIC_DRV_SetData(0x0090,0x200,0x200,0x0);
+ PMIC_DRV_SetData(0x0090,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x0090,0x8000,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0095,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x80,0x80,0x0);
+ PMIC_DRV_SetData(0x0095,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x0095,0x200,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x8000,0x8000,0x0);
+ PMIC_DRV_SetData(0x009C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x00AA,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C0,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x00C0,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x00C0,0x1000,0x1000,0x0);
+ PMIC_DRV_SetData(0x00C0,0x4000,0x0,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C2,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x00C2,0x400,0x400,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x00C8,0x20,0x20,0x0);
+ PMIC_DRV_SetData(0x00D6,0x10,0x10,0x0);
+ }
+#elif defined(PMIC_INIT_ROUTER_ON_EVB)
+//debug_MT6339 Register Mapping E1 20130724_I_EVB_hotspot_initial_setting_LPG.txt
+ {
+ //<ECO_E1>
+ //address,mask,value,ap shift,ap mask,ap value, bank
+ PMIC_DRV_SetData(0x0010,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0021,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0024,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0024,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x0029,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002A,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x003B,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0044,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x0044,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0048,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0049,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004E,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0056,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0057,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0065,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0065,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0066,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0066,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0066,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0066,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0066,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x0067,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0067,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x006C,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x007C,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x40,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0081,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0081,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0081,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0081,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0081,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0090,0x100,0x0,0x0);
+ PMIC_DRV_SetData(0x0090,0x200,0x200,0x0);
+ PMIC_DRV_SetData(0x0090,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x0090,0x8000,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0095,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x80,0x80,0x0);
+ PMIC_DRV_SetData(0x0095,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x0095,0x200,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x8000,0x8000,0x0);
+ PMIC_DRV_SetData(0x009C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x00AA,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C0,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x00C0,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x00C0,0x1000,0x1000,0x0);
+ PMIC_DRV_SetData(0x00C0,0x4000,0x0,0x0);
+ PMIC_DRV_SetData(0x00C2,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x00C2,0x400,0x400,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x00C8,0x20,0x20,0x0);
+ PMIC_DRV_SetData(0x00D6,0x10,0x10,0x0);
+ }
+#else
+//debug_MT6339 Register Mapping E1 20130724_I_EVB_phone_initial_setting_LPG.txt
+ {
+ //<ECO_E1>
+ //address,mask,value,ap shift,ap mask,ap value, bank
+ PMIC_DRV_SetData(0x0010,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0021,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0024,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0024,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x0029,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002A,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x002B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x003B,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0044,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x0044,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0048,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0049,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004B,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x004E,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0056,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0057,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0065,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x0065,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0065,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0066,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x0066,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0066,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0066,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0066,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x0067,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0067,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x006C,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x007C,0x1,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x4,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x10,0x0,0x0);
+ PMIC_DRV_SetData(0x007C,0x20,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x40,0x0,0x0);
+ PMIC_DRV_SetData(0x007D,0x80,0x0,0x0);
+ PMIC_DRV_SetData(0x0081,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0081,0x2,0x2,0x0);
+ PMIC_DRV_SetData(0x0081,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x0081,0x8,0x8,0x0);
+ PMIC_DRV_SetData(0x0081,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x0090,0x100,0x0,0x0);
+ PMIC_DRV_SetData(0x0090,0x200,0x200,0x0);
+ PMIC_DRV_SetData(0x0090,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x0090,0x8000,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x0095,0x2,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x80,0x80,0x0);
+ PMIC_DRV_SetData(0x0095,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x0095,0x200,0x0,0x0);
+ PMIC_DRV_SetData(0x0095,0x8000,0x8000,0x0);
+ PMIC_DRV_SetData(0x009C,0x1,0x1,0x0);
+ PMIC_DRV_SetData(0x00AA,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C0,0x10,0x10,0x0);
+ PMIC_DRV_SetData(0x00C0,0x40,0x40,0x0);
+ PMIC_DRV_SetData(0x00C0,0x1000,0x1000,0x0);
+ PMIC_DRV_SetData(0x00C0,0x4000,0x0,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4,0x4,0x0);
+ PMIC_DRV_SetData(0x00C2,0x100,0x100,0x0);
+ PMIC_DRV_SetData(0x00C2,0x400,0x400,0x0);
+ PMIC_DRV_SetData(0x00C2,0x4000,0x4000,0x0);
+ PMIC_DRV_SetData(0x00C8,0x20,0x20,0x0);
+ PMIC_DRV_SetData(0x00D6,0x10,0x10,0x0);
+ }
+#endif
+#if defined(MT6290M_SP_BB) || defined(MT6290ME2_SP)
+ // For Dual Talk
+ PMIC_DRV_SetData(0x0024,0x2,0x2,0x0);
+#endif
+}
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6351.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6351.c
new file mode 100644
index 0000000..d7782b7
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6351.c
@@ -0,0 +1,1955 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6351.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6351
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+#include "dhl_trace.h"
+#if defined(PMIC_6351_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+//#define PMIC_INTERNAL_SRAM
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define BANKS_NUM 1
+#define PMIC6351_MAX_REG_NUM 0x0FF0 // 0x0000~0x0F48
+//#define PMIC_MAX_REG_NUM 0x40FF // Register BUCK1, Register ANALDO, Register DIGLDO (0x0470)
+
+#define MT6351_HW_CID_E1 0x5110
+#define MT6351_HW_CID_E2 0x5120
+#define MT6351_HW_CID_E3 0x5130
+#define MT6351_SW_CID_E1 0x5110
+#define MT6351_SW_CID_E2 0x5120
+#define MT6351_SW_CID_E3 0x5130
+
+#define PMIC_READ 0
+#define PMIC_WRITE 1
+
+#define PMIC_6351 0x6351
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+extern kal_bool pmic6351_reg_write(kal_uint16 reg, kal_uint16 val);
+extern kal_bool pmic6351_reg_read(kal_uint16 reg, kal_uint16 *pVal);
+
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+//#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+//__attribute__ ((zero_init))
+//#endif /* __MTK_TARGET__ */
+kal_uint8 pmic6351_hw_version;
+kal_uint8 pmic6351_sw_version;
+kal_uint16 pmic6351_reg[PMIC6351_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+const PMIC_FLAG_TABLE_ENTRY pmic6351_flags_table[] =
+{
+ {MT6351_HWCID, MT6351_HWCID_MASK, MT6351_HWCID_SHIFT, },
+ {MT6351_SWCID, MT6351_SWCID_MASK, MT6351_SWCID_SHIFT, },
+ {MT6351_VPA_ANA_CON0, MT6351_RG_VPA_MODESET_MASK, MT6351_RG_VPA_MODESET_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON0, MT6351_BUCK_VMODEM_EN_CTRL_MASK, MT6351_BUCK_VMODEM_EN_CTRL_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON0, MT6351_BUCK_VMODEM_VOSEL_CTRL_MASK, MT6351_BUCK_VMODEM_VOSEL_CTRL_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON2, MT6351_BUCK_VMODEM_EN_MASK, MT6351_BUCK_VMODEM_EN_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON2, MT6351_DA_QI_VMODEM_EN_MASK, MT6351_DA_QI_VMODEM_EN_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON4, MT6351_BUCK_VMODEM_VOSEL_MASK, MT6351_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON5, MT6351_BUCK_VMODEM_VOSEL_ON_MASK, MT6351_BUCK_VMODEM_VOSEL_ON_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON6, MT6351_BUCK_VMODEM_VOSEL_SLEEP_MASK, MT6351_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6351_BUCK_VMODEM_CON8, MT6351_DA_NI_VMODEM_VOSEL_SYNC_MASK, MT6351_DA_NI_VMODEM_VOSEL_SYNC_SHIFT, },
+ {MT6351_BUCK_VMD1_CON0, MT6351_BUCK_VMD1_EN_CTRL_MASK, MT6351_BUCK_VMD1_EN_CTRL_SHIFT, },
+ {MT6351_BUCK_VMD1_CON0, MT6351_BUCK_VMD1_VOSEL_CTRL_MASK, MT6351_BUCK_VMD1_VOSEL_CTRL_SHIFT, },
+ {MT6351_BUCK_VMD1_CON2, MT6351_BUCK_VMD1_EN_MASK, MT6351_BUCK_VMD1_EN_SHIFT, },
+ {MT6351_BUCK_VMD1_CON2, MT6351_DA_QI_VMD1_EN_MASK, MT6351_DA_QI_VMD1_EN_SHIFT, },
+ {MT6351_BUCK_VMD1_CON4, MT6351_BUCK_VMD1_VOSEL_MASK, MT6351_BUCK_VMD1_VOSEL_SHIFT, },
+ {MT6351_BUCK_VMD1_CON5, MT6351_BUCK_VMD1_VOSEL_ON_MASK, MT6351_BUCK_VMD1_VOSEL_ON_SHIFT, },
+ {MT6351_BUCK_VMD1_CON6, MT6351_BUCK_VMD1_VOSEL_SLEEP_MASK, MT6351_BUCK_VMD1_VOSEL_SLEEP_SHIFT, },
+ {MT6351_BUCK_VMD1_CON8, MT6351_DA_NI_VMD1_VOSEL_SYNC_MASK, MT6351_DA_NI_VMD1_VOSEL_SYNC_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON0, MT6351_BUCK_VSRAM_MD_EN_CTRL_MASK, MT6351_BUCK_VSRAM_MD_EN_CTRL_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON0, MT6351_BUCK_VSRAM_MD_VOSEL_CTRL_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_CTRL_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON2, MT6351_BUCK_VSRAM_MD_EN_MASK, MT6351_BUCK_VSRAM_MD_EN_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON2, MT6351_DA_QI_VSRAM_MD_EN_MASK, MT6351_DA_QI_VSRAM_MD_EN_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON4, MT6351_BUCK_VSRAM_MD_VOSEL_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON5, MT6351_BUCK_VSRAM_MD_VOSEL_ON_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_ON_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON6, MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
+ {MT6351_BUCK_VSRAM_MD_CON8, MT6351_DA_NI_VSRAM_MD_VOSEL_SYNC_MASK, MT6351_DA_NI_VSRAM_MD_VOSEL_SYNC_SHIFT, },
+ {MT6351_BUCK_VPA_CON0, MT6351_BUCK_VPA_EN_CTRL_MASK, MT6351_BUCK_VPA_EN_CTRL_SHIFT, },
+ {MT6351_BUCK_VPA_CON0, MT6351_BUCK_VPA_VOSEL_CTRL_MASK, MT6351_BUCK_VPA_VOSEL_CTRL_SHIFT, },
+ {MT6351_BUCK_VPA_CON1, MT6351_BUCK_VPA_EN_SEL_MASK, MT6351_BUCK_VPA_EN_SEL_SHIFT, },
+ {MT6351_BUCK_VPA_CON1, MT6351_BUCK_VPA_VOSEL_SEL_MASK, MT6351_BUCK_VPA_VOSEL_SEL_SHIFT, },
+ {MT6351_BUCK_VPA_CON2, MT6351_BUCK_VPA_EN_MASK, MT6351_BUCK_VPA_EN_SHIFT, },
+ {MT6351_BUCK_VPA_CON4, MT6351_BUCK_VPA_VOSEL_MASK, MT6351_BUCK_VPA_VOSEL_SHIFT, },
+ {MT6351_BUCK_VPA_CON5, MT6351_BUCK_VPA_VOSEL_ON_MASK, MT6351_BUCK_VPA_VOSEL_ON_SHIFT, },
+ {MT6351_BUCK_VPA_CON6, MT6351_BUCK_VPA_VOSEL_SLEEP_MASK, MT6351_BUCK_VPA_VOSEL_SLEEP_SHIFT, },
+ {MT6351_BUCK_VPA_CON8, MT6351_DA_NI_VPA_VOSEL_SYNC_MASK, MT6351_DA_NI_VPA_VOSEL_SYNC_SHIFT, },
+ {MT6351_BUCK_VPA_CON9, MT6351_DA_QI_VPA_DVS_EN_MASK, MT6351_DA_QI_VPA_DVS_EN_SHIFT, },
+ {MT6351_BUCK_VPA_CON9, MT6351_BUCK_VPA_VSLEEP_EN_MASK, MT6351_BUCK_VPA_VSLEEP_EN_SHIFT, },
+ {MT6351_BUCK_VPA_CON9, MT6351_BUCK_VPA_R2R_PDN_MASK, MT6351_BUCK_VPA_R2R_PDN_SHIFT, },
+ {MT6351_BUCK_VPA_CON9, MT6351_BUCK_VPA_VSLEEP_SEL_MASK, MT6351_BUCK_VPA_VSLEEP_SEL_SHIFT, },
+ {MT6351_LDO_VA18_CON0, MT6351_RG_VA18_MODE_CTRL_MASK, MT6351_RG_VA18_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VA18_CON0, MT6351_RG_VA18_ON_CTRL_MASK, MT6351_RG_VA18_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VA18_CON0, MT6351_RG_VA18_SRCLK_MODE_SEL_MASK, MT6351_RG_VA18_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VA18_CON0, MT6351_DA_QI_VA18_MODE_MASK, MT6351_DA_QI_VA18_MODE_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_MODE_SET_MASK, MT6351_RG_VTCXO24_MODE_SET_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_EN_MASK, MT6351_RG_VTCXO24_EN_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_MODE_CTRL_MASK, MT6351_RG_VTCXO24_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_ON_CTRL_MASK, MT6351_RG_VTCXO24_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_SWITCH_MASK, MT6351_RG_VTCXO24_SWITCH_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_SRCLK_MODE_SEL_MASK, MT6351_RG_VTCXO24_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_DA_QI_VTCXO24_MODE_MASK, MT6351_DA_QI_VTCXO24_MODE_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_STBTD_MASK, MT6351_RG_VTCXO24_STBTD_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_SRCLK_EN_SEL_MASK, MT6351_RG_VTCXO24_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VTCXO24_CON0, MT6351_DA_QI_VTCXO24_EN_MASK, MT6351_DA_QI_VTCXO24_EN_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_MODE_SET_MASK, MT6351_RG_VTCXO28_MODE_SET_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_EN_MASK, MT6351_RG_VTCXO28_EN_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_MODE_CTRL_MASK, MT6351_RG_VTCXO28_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_ON_CTRL_MASK, MT6351_RG_VTCXO28_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_SRCLK_MODE_SEL_MASK, MT6351_RG_VTCXO28_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_DA_QI_VTCXO28_MODE_MASK, MT6351_DA_QI_VTCXO28_MODE_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_STBTD_MASK, MT6351_RG_VTCXO28_STBTD_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_SRCLK_EN_SEL_MASK, MT6351_RG_VTCXO28_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON0, MT6351_DA_QI_VTCXO28_EN_MASK, MT6351_DA_QI_VTCXO28_EN_SHIFT, },
+ {MT6351_LDO_VTCXO28_CON1, MT6351_DA_QI_VTCXO28_OCFB_EN_MASK, MT6351_DA_QI_VTCXO28_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VCAMA_CON0, MT6351_RG_VCAMA_ON_CTRL_MASK, MT6351_RG_VCAMA_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VCAMA_CON1, MT6351_RG_VCAMA_OCFB_EN_MASK, MT6351_RG_VCAMA_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VCAMA_CON1, MT6351_DA_QI_VCAMA_OCFB_EN_MASK, MT6351_DA_QI_VCAMA_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_MODE_SET_MASK, MT6351_RG_VSIM1_MODE_SET_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_EN_MASK, MT6351_RG_VSIM1_EN_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_MODE_CTRL_MASK, MT6351_RG_VSIM1_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_ON_CTRL_MASK, MT6351_RG_VSIM1_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_SRCLK_MODE_SEL_MASK, MT6351_RG_VSIM1_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_STBTD_MASK, MT6351_RG_VSIM1_STBTD_SHIFT, },
+ {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_SRCLK_EN_SEL_MASK, MT6351_RG_VSIM1_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VSIM1_CON1, MT6351_RG_VSIM1_OCFB_EN_MASK, MT6351_RG_VSIM1_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VSIM1_CON1, MT6351_DA_QI_VSIM1_OCFB_EN_MASK, MT6351_DA_QI_VSIM1_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_MODE_SET_MASK, MT6351_RG_VSIM2_MODE_SET_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_EN_MASK, MT6351_RG_VSIM2_EN_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_MODE_CTRL_MASK, MT6351_RG_VSIM2_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_ON_CTRL_MASK, MT6351_RG_VSIM2_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_SRCLK_MODE_SEL_MASK, MT6351_RG_VSIM2_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_STBTD_MASK, MT6351_RG_VSIM2_STBTD_SHIFT, },
+ {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_SRCLK_EN_SEL_MASK, MT6351_RG_VSIM2_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VSIM2_CON1, MT6351_RG_VSIM2_OCFB_EN_MASK, MT6351_RG_VSIM2_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VSIM2_CON1, MT6351_DA_QI_VSIM2_OCFB_EN_MASK, MT6351_DA_QI_VSIM2_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_MODE_SET_MASK, MT6351_RG_VIBR_MODE_SET_SHIFT, },
+ {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_EN_MASK, MT6351_RG_VIBR_EN_SHIFT, },
+ {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_MODE_CTRL_MASK, MT6351_RG_VIBR_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_ON_CTRL_MASK, MT6351_RG_VIBR_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_THER_SDN_EN_MASK, MT6351_RG_VIBR_THER_SDN_EN_SHIFT, },
+ {MT6351_LDO_VIBR_CON1, MT6351_RG_VIBR_OCFB_EN_MASK, MT6351_RG_VIBR_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VIBR_CON2, MT6351_RG_VIBR_DUMMY_LOAD_MASK, MT6351_RG_VIBR_DUMMY_LOAD_SHIFT, },
+ {MT6351_LDO_VIBR_CON2, MT6351_DA_QI_VIBR_DUMMY_LOAD_MASK, MT6351_DA_QI_VIBR_DUMMY_LOAD_SHIFT, },
+ {MT6351_LDO_VCAMD_CON0, MT6351_RG_VCAMD_MODE_SET_MASK, MT6351_RG_VCAMD_MODE_SET_SHIFT, },
+ {MT6351_LDO_VCAMD_CON0, MT6351_RG_VCAMD_EN_MASK, MT6351_RG_VCAMD_EN_SHIFT, },
+ {MT6351_LDO_VCAMD_CON0, MT6351_RG_VCAMD_STBTD_MASK, MT6351_RG_VCAMD_STBTD_SHIFT, },
+ {MT6351_LDO_VCAMD_CON0, MT6351_DA_QI_VCAMD_STB_MASK, MT6351_DA_QI_VCAMD_STB_SHIFT, },
+ {MT6351_LDO_VCAMD_CON0, MT6351_DA_QI_VCAMD_EN_MASK, MT6351_DA_QI_VCAMD_EN_SHIFT, },
+ {MT6351_LDO_VCAMD_CON1, MT6351_DA_QI_VCAMD_OCFB_EN_MASK, MT6351_DA_QI_VCAMD_OCFB_EN_SHIFT, },
+ {MT6351_LDO_VCAMD_CON2, MT6351_RG_VCAMD_DUMMY_LOAD_SRCLKEN_SEL_MASK, MT6351_RG_VCAMD_DUMMY_LOAD_SRCLKEN_SEL_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_MODE_SET_MASK, MT6351_RG_VRF18_MODE_SET_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_EN_MASK, MT6351_RG_VRF18_EN_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_MODE_CTRL_MASK, MT6351_RG_VRF18_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_ON_CTRL_MASK, MT6351_RG_VRF18_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_SRCLK_MODE_SEL_MASK, MT6351_RG_VRF18_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_DA_QI_VRF18_MODE_MASK, MT6351_DA_QI_VRF18_MODE_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_STBTD_MASK, MT6351_RG_VRF18_STBTD_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_SRCLK_EN_SEL_MASK, MT6351_RG_VRF18_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_DA_QI_VRF18_STB_MASK, MT6351_DA_QI_VRF18_STB_SHIFT, },
+ {MT6351_LDO_VRF18_CON0, MT6351_DA_QI_VRF18_EN_MASK, MT6351_DA_QI_VRF18_EN_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_MODE_SET_MASK, MT6351_RG_VRF12_MODE_SET_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_EN_MASK, MT6351_RG_VRF12_EN_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_MODE_CTRL_MASK, MT6351_RG_VRF12_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_ON_CTRL_MASK, MT6351_RG_VRF12_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_SRCLK_MODE_SEL_MASK, MT6351_RG_VRF12_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_DA_QI_VRF12_MODE_MASK, MT6351_DA_QI_VRF12_MODE_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_STBTD_MASK, MT6351_RG_VRF12_STBTD_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_SRCLK_EN_SEL_MASK, MT6351_RG_VRF12_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VRF12_CON0, MT6351_DA_QI_VRF12_EN_MASK, MT6351_DA_QI_VRF12_EN_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_MODE_SET_MASK, MT6351_RG_VMIPI_MODE_SET_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_EN_MASK, MT6351_RG_VMIPI_EN_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_MODE_CTRL_MASK, MT6351_RG_VMIPI_MODE_CTRL_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_ON_CTRL_MASK, MT6351_RG_VMIPI_ON_CTRL_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_SRCLK_MODE_SEL_MASK, MT6351_RG_VMIPI_SRCLK_MODE_SEL_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_DA_QI_VMIPI_MODE_MASK, MT6351_DA_QI_VMIPI_MODE_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_STBTD_MASK, MT6351_RG_VMIPI_STBTD_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_SRCLK_EN_SEL_MASK, MT6351_RG_VMIPI_SRCLK_EN_SEL_SHIFT, },
+ {MT6351_LDO_VMIPI_CON0, MT6351_DA_QI_VMIPI_EN_MASK, MT6351_DA_QI_VMIPI_EN_SHIFT, },
+ {MT6351_LDO_VMIPI_CON1, MT6351_DA_QI_VMIPI_OCFB_EN_MASK, MT6351_DA_QI_VMIPI_OCFB_EN_SHIFT, },
+ {MT6351_VTCXO28_ANA_CON0, MT6351_RG_VTCXO28_VOSEL_MASK, MT6351_RG_VTCXO28_VOSEL_SHIFT, },
+ {MT6351_VTCXO24_ANA_CON0, MT6351_RG_VTCXO24_VOSEL_MASK, MT6351_RG_VTCXO24_VOSEL_SHIFT, },
+ {MT6351_VSIM1_ANA_CON0, MT6351_RG_VSIM1_VOSEL_MASK, MT6351_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6351_VSIM2_ANA_CON0, MT6351_RG_VSIM2_CAL_MASK, MT6351_RG_VSIM2_CAL_SHIFT, },
+ {MT6351_VSIM2_ANA_CON0, MT6351_RG_VSIM2_VOSEL_MASK, MT6351_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6351_VSIM2_ANA_CON1, MT6351_RG_VSIM2_STB_SEL_MASK, MT6351_RG_VSIM2_STB_SEL_SHIFT, },
+ {MT6351_VSIM2_ANA_CON1, MT6351_RG_VSIM2_OC_TRIM_MASK, MT6351_RG_VSIM2_OC_TRIM_SHIFT, },
+ {MT6351_VEFUSE_ANA_CON0, MT6351_RG_VEFUSE_CAL_MASK, MT6351_RG_VEFUSE_CAL_SHIFT, },
+ {MT6351_VEFUSE_ANA_CON1, MT6351_RG_VEFUSE_STB_SEL_MASK, MT6351_RG_VEFUSE_STB_SEL_SHIFT, },
+ {MT6351_VEFUSE_ANA_CON1, MT6351_RG_VEFUSE_OC_TRIM_MASK, MT6351_RG_VEFUSE_OC_TRIM_SHIFT, },
+ {MT6351_VRF18_ANA_CON0, MT6351_RG_VRF18_VOSEL_MASK, MT6351_RG_VRF18_VOSEL_SHIFT, },
+ {MT6351_VRF12_ANA_CON0, MT6351_RG_VRF12_VOSEL_MASK, MT6351_RG_VRF12_VOSEL_SHIFT, },
+ {MT6351_VMIPI_ANA_CON0, MT6351_RG_VMIPI_VOSEL_MASK, MT6351_RG_VMIPI_VOSEL_SHIFT, },
+ {MT6351_BIF_CON30, MT6351_BIF_TEST_MODE0_MASK, MT6351_BIF_TEST_MODE0_SHIFT, },
+ {MT6351_BIF_CON30, MT6351_BIF_TEST_MODE4_MASK, MT6351_BIF_TEST_MODE4_SHIFT, },
+ {MT6351_BIF_CON30, MT6351_BIF_TEST_MODE5_MASK, MT6351_BIF_TEST_MODE5_SHIFT, },
+ {MT6351_BIF_CON30, MT6351_BIF_BAT_LOST_SW_MASK, MT6351_BIF_BAT_LOST_SW_SHIFT, },
+ {MT6351_BIF_CON31, MT6351_BIF_IRQ_MASK, MT6351_BIF_IRQ_SHIFT, },
+ {MT6351_BIF_CON31, MT6351_BIF_TIMEOUT_MASK, MT6351_BIF_TIMEOUT_SHIFT, },
+ {MT6351_AUXADC_ADC17, MT6351_AUXADC_ADC_OUT_CH7_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC17, MT6351_AUXADC_ADC_RDY_CH7_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC19, MT6351_AUXADC_ADC_OUT_CH4_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC19, MT6351_AUXADC_ADC_RDY_CH4_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC22, MT6351_AUXADC_ADC_OUT_CH0_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH0_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC22, MT6351_AUXADC_ADC_RDY_CH0_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH0_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC24, MT6351_AUXADC_ADC_OUT_CH1_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH1_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC24, MT6351_AUXADC_ADC_RDY_CH1_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH1_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC36, MT6351_AUXADC_ADC_OUT_DCXO_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_DCXO_BY_MD_SHIFT, },
+ {MT6351_AUXADC_ADC36, MT6351_AUXADC_ADC_RDY_DCXO_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_DCXO_BY_MD_SHIFT, },
+ {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH0_BY_MD_MASK, MT6351_AUXADC_RQST_CH0_BY_MD_SHIFT, },
+ {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH1_BY_MD_MASK, MT6351_AUXADC_RQST_CH1_BY_MD_SHIFT, },
+ {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH4_BY_MD_MASK, MT6351_AUXADC_RQST_CH4_BY_MD_SHIFT, },
+ {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH7_BY_MD_MASK, MT6351_AUXADC_RQST_CH7_BY_MD_SHIFT, },
+ {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_DCXO_BY_MD_MASK, MT6351_AUXADC_RQST_DCXO_BY_MD_SHIFT, },
+ {MT6351_AUXADC_RQST1_SET, MT6351_AUXADC_RQST1_SET_MASK, MT6351_AUXADC_RQST1_SET_SHIFT, },
+ {MT6351_AUXADC_RQST1_CLR, MT6351_AUXADC_RQST1_CLR_MASK, MT6351_AUXADC_RQST1_CLR_SHIFT, },
+};
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+
+// Write Whole Bytes
+void dcl_pmic6351_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+ if(addr <= PMIC6351_MAX_REG_NUM)
+ {
+ pmic6351_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+// Write register field
+void dcl_pmic6351_field_write(PMIC6351_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6351_flags_table;
+ kal_uint32 savedMask = 0;
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic6351_reg[pTable[flag].offset];
+
+ pmic6351_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic6351_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6351_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic6351_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+}
+
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic6351_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ kal_uint32 savedMask = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr <= PMIC6351_MAX_REG_NUM)
+ {
+ pmic6351_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic6351_field_read(PMIC6351_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6351_flags_table;
+ kal_uint32 savedMask = 0;
+ DCL_UINT16 reg_return = 0;
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ savedMask = SaveAndSetIRQMask();
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6351_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic6351_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
+ pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
+#endif
+
+#if !defined(__UBL__) && !defined(__FUE__)
+ RestoreIRQMask(savedMask);
+#endif //#if !defined(__UBL__) && !defined(__FUE__)
+
+ return reg_return;
+}
+
+
+// Exported for EM used
+void pmic6351_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic6351_byte_write(reg, val);
+}
+
+kal_uint16 pmic6351_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic6351_byte_return(reg);
+}
+
+PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6351_get_HW_ECO_version(void)
+{
+ return pmic6351_hw_version;
+}
+
+PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6351_get_SW_version(void)
+{
+ return pmic6351_sw_version;
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_860000_V, PMU_VOLT_02_760000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_100000_V,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+};
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC6351_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+// case VRF18_1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+// case VRF18_2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VMIPI_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMD1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO28:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+// case VRF18_1:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6351_field_write(MT6351_RG_VRF18_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+// case VRF18_2:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6351_field_write(MT6351_RG_VRF12_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic6351_field_write(MT6351_RG_VMIPI_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO28:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_MODE_SET, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_SEL *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+// case VRF18_1:
+ {
+ // 1'b0: SW control by VSIM1_MODE_SET, 1'b1: HW control by SRCLKEN
+ dcl_pmic6351_field_write(MT6351_RG_VRF18_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VRF12:
+// case VRF18_2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF12_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case VSIM1:
+ {
+ // 1'b0: SW control by VSIM1_MODE_SET, 1'b1: HW control by SRCLKEN
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VMIPI_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO28:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_MODE_CTRL, pLdoBuckCtrl->onSel);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO28:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_DA_NI_VSRAM_MD_VOSEL_SYNC);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_DA_NI_VMD1_VOSEL_SYNC);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_DA_NI_VMODEM_VOSEL_SYNC);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_CTRL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselCtrl);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL_CTRL);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMD1:
+ {
+ pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL_CTRL);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMODEM:
+ {
+ pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL_CTRL);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_ON:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_ON *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselOn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL_ON);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL_ON);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL_ON);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_CTRL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselCtrl);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMD1:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMODEM:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_ON:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_ON *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselOn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL_ON, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL_ON, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL_ON, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSRAM_MD:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMD1:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_EN_CTRL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnCtrl);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+// case VRF18_1:
+ {
+ // 0: SW control1: HW control
+ dcl_pmic6351_field_write(MT6351_RG_VRF18_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+// case VRF18_2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF12_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_RG_VMIPI_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_EN_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMD1:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_BUCK_VMD1_EN_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VMODEM:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_EN_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VTCXO24:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VTCXO28:
+ {
+ // 0: SW control, 1: HW
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_ON_CTRL, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+
+ case LDO_BUCK_SET_EN_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+// case VRF18_1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF18_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+// case VRF18_2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF12_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VMIPI_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO28:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SRCLK_MODE_SEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetSrclkModeSel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VRF18:
+// case VRF18_1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF18_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+ case VRF12:
+// case VRF18_2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VRF12_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM1_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VSIM2_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VMIPI_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO28:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO28_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VTCXO24_SWITCH:
+ {
+ PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetVtcxoSwith);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+
+ case VTCXO24:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VTCXO24_SWITCH, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic6351_field_write(MT6351_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6351_field_write(MT6351_BUCK_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ /*
+ 1. AUXADC_RQST1_CLR[7] 1'h1
+ 2. AUXADC_RQST1_SET[7] 1'h1
+ 3. After 10us
+ 4. Polling ready, AUXADC_ADC_RDY_Ch7_BY_MD
+ 5. After AUXADC_ADC_RDY_Ch7_BY_MD = 1, get data by AUXADC_ADC_OUT_CH7_BY_MD
+ 6. AUXADC_RQST1_CLR[7] 1'h1
+ */
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ dcl_pmic6351_byte_write(MT6351_TOP_CLKSQ_SET, (0x1 << 3));
+ dcl_pmic6351_byte_write(MT6351_AUXADC_RQST1_CLR, (pAdcCtrl->enable << 7));
+ dcl_pmic6351_byte_write(MT6351_AUXADC_RQST1_SET, (0x1 << 7));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic6351_field_read(MT6351_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ dcl_pmic6351_byte_write(MT6351_AUXADC_RQST1_CLR, (0x1 << 7));
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ dcl_pmic6351_byte_write(MT6351_TOP_CLKSQ_CLR, (0x1 << 3));
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_HW_VERSION:
+ {
+ PMU_CTRL_MISC_GET_HW_VERSION *pMiscCtrl = &(data->rPMUMiscGetHwVersion);
+ if(pMiscCtrl->chip_name == PMIC_6351)
+ {
+ pMiscCtrl->version = pmic6351_hw_version;
+ }
+ return_val = STATUS_OK;
+ }
+ break;
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+ pmic6351_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic6351_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+
+ return return_val;
+}
+
+extern void dcl_pmic6351_modem_only_init(void);
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+extern kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+
+
+void dcl_pmic6351_internal_init(void)
+{
+}
+
+#if defined(__DHL_MODULE__)
+extern kal_bool dhl_register_custom_mem_read(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_READ_MEM_CALLBACK read_cb);
+extern kal_bool dhl_register_custom_mem_write(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_WRITE_MEM_CALLBACK write_cb);
+extern void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len);
+extern void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr);
+#endif
+
+void dcl_pmic6351_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC6351_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+#if defined(__DHL_MODULE__)
+ dhl_register_custom_mem_read(DHL_CUSTOM_MEM_PMIC, PMIC_Read_Callback_For_DHL);
+ dhl_register_custom_mem_write(DHL_CUSTOM_MEM_PMIC, PMIC_Write_Callback_For_DHL);
+#endif
+ pmic_wrap_dump_init();
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic6351_hw_version = PMIC_ECO_E1;
+ pmic6351_sw_version = PMIC_ECO_E1;
+
+ // Get MT6351 ECO version
+ {
+ kal_uint16 pmic6351_hw_eco_version = 0;
+ kal_uint16 pmic6351_sw_eco_version = 0;
+ pmic6351_hw_eco_version = dcl_pmic6351_byte_return(MT6351_HWCID);
+ pmic6351_sw_eco_version = dcl_pmic6351_byte_return(MT6351_SWCID);
+
+ if (pmic6351_hw_eco_version == MT6351_HW_CID_E1)
+ {
+ pmic6351_hw_version = PMIC_ECO_E1;
+ }
+ else if (pmic6351_hw_eco_version == MT6351_HW_CID_E2)
+ {
+ pmic6351_hw_version = PMIC_ECO_E2;
+ }
+ else
+ {
+ pmic6351_hw_version = PMIC_ECO_E3;
+ }
+
+ if (pmic6351_sw_eco_version == MT6351_SW_CID_E1)
+ {
+ pmic6351_sw_version = PMIC_ECO_E1;
+ }
+ else if (pmic6351_sw_eco_version == MT6351_SW_CID_E2)
+ {
+ pmic6351_sw_version = PMIC_ECO_E2;
+ }
+ else
+ {
+ pmic6351_sw_version = PMIC_ECO_E3;
+ }
+ }
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+ dcl_pmic6351_modem_only_init();
+#endif
+ dcl_pmic6351_internal_init();
+
+ // pmic6351_customization_init();
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+#if defined(__DHL_MODULE__)
+kal_uint32 pmic_read_data;
+void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len)
+{
+ kal_uint32 write_buffer_addr = 0;
+ kal_uint32 read_data_addr = (kal_uint32)read_addr;
+ // Write Workaround
+ if(read_data_addr & 0x00000001)
+ {
+ write_buffer_addr = (read_data_addr & 0xFFFF0000) >> 16;
+ read_data_addr = (read_data_addr & 0x0000FFFE);
+ PMIC_Config_Interface(PMIC_WRITE, read_data_addr, (kal_uint32)write_buffer_addr, NULL, option);
+ }
+ PMIC_Config_Interface(PMIC_READ, read_data_addr, 0, &pmic_read_data, option);
+ *read_buffer_addr = (kal_uint32*)&pmic_read_data;
+ *read_buffer_len = 4;
+}
+
+void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr)
+{
+ PMIC_Config_Interface(PMIC_WRITE, (kal_uint32)write_addr, (kal_uint32)write_buffer_addr, NULL, option);
+}
+#endif // End of #if defined(__DHL_MODULE__)
+kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name)
+{
+ // Check argument validation
+ if((action & ~(0x1)) != 0) return 0; // Write should be 1 bit
+ if((address & ~(0xffff)) != 0) return 0; // Address should no larger than 0xFFFF
+ if((wdata & ~(0xffff)) != 0) return 0; // Write DATA should be no larger than 0xFFFF
+
+ if(action == PMIC_READ)
+ {
+ if(chip_name == PMIC_6351)
+ {
+ *rdata = (kal_uint32)DRV_Read_PMIC_Data(address);
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ else if(action == PMIC_WRITE)
+ {
+ if(chip_name == PMIC_6351)
+ {
+ DRV_Write_PMIC_Data(address, wdata);
+ }
+ else
+ {
+ ASSERT(0);
+ }
+ }
+ return 1;
+}
+
+DCL_BOOL dcl_pmic_init_done_query(void)
+{
+ if(pmic_init_done == DCL_TRUE)
+ {
+ return DCL_TRUE;
+ }
+ else
+ {
+ return DCL_FALSE;
+ }
+}
+
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic6351_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic6351_byte_write(pmic_addr, value);
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i;
+ for (i = 0; i < PMIC6351_MAX_REG_NUM; i += 2){
+ pmic6351_reg[i] = dcl_pmic6351_byte_return(i);
+ }
+}
+
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VPA_SW;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VPA_SW;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VPA_SW;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VRF1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VRF1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VRF1;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.regval = 0x7; // (0x0~0xF)
+DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.regval = 0x7; // (0x0~0xF)
+DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+// val.regval will be your request value ( no need do any shift)
+DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VRF2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_MODESET val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VRF1;
+val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.sel = SRCLKEN_IN1_SEL;
+/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+val.mod = VMIPI;
+DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VSIM1;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+val.mod = VSIM2;
+DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VSIM1;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod=VSIM2;
+val.voltage = PMU_VOLT_01_800000_V;
+/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+{
+DCL_HANDLE handle;
+PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN val;
+handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+val.mod = VTCXO24;
+val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+DclPMU_Control(handle, LDO_BUCK_SET_VTCXO24_SWITCH, (DCL_CTRL_DATA_T *)&val);
+DclPMU_Close(handle);
+}
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6351_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6351_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6351_init.c
new file mode 100644
index 0000000..a576a5e
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6351_init.c
@@ -0,0 +1,804 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2015
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6351_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6351
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+void PMIC_DRV_SetData(DCL_UINT32 addr, DCL_UINT32 bitmask, DCL_UINT16 value, DCL_UINT32 bank)
+{
+ DCL_UINT32 temp;
+ addr |= (bank << 31);
+ temp = (~(bitmask)) & DRV_Read_PMIC_Data(addr);
+ temp |= ((value) & (bitmask));
+ DRV_Write_PMIC_Data(addr,temp);
+}
+// MT6351 ECO_E1
+void dcl_pmic6351_modem_only_init(void)
+{
+ // DDUVLO_DEB_EN[0:0] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0x8 , 0x1 , 0x1 , 0x0);
+
+ // RG_STRUP_VUSB33_PG_H2L_EN[1:1] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x2 , 0x2 , 0x0);
+
+ // RG_STRUP_VGPU_PG_H2L_EN[2:2] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x4 , 0x4 , 0x0);
+
+ // RG_STRUP_VDRAM_PG_H2L_EN[3:3] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x8 , 0x8 , 0x0);
+
+ // RG_STRUP_VSRAM_PROC_PG_H2L_EN[4:4] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x10 , 0x10 , 0x0);
+
+ // RG_STRUP_VSRAM_MD_PG_H2L_EN[5:5] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x20 , 0x20 , 0x0);
+
+ // RG_STRUP_VA10_PG_H2L_EN[7:7] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x80 , 0x80 , 0x0);
+
+ // RG_STRUP_VEMC_PG_H2L_EN[8:8] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x100 , 0x100 , 0x0);
+
+ // RG_STRUP_VS2_PG_H2L_EN[10:10] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x400 , 0x400 , 0x0);
+
+ // RG_STRUP_VMODEM_PG_H2L_EN[11:11] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x800 , 0x800 , 0x0);
+
+ // RG_STRUP_VMD1_PG_H2L_EN[12:12] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x1000 , 0x1000 , 0x0);
+
+ // RG_STRUP_VCORE_PG_H2L_EN[13:13] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x2000 , 0x2000 , 0x0);
+
+ // RG_STRUP_VA18_PG_H2L_EN[14:14] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x4000 , 0x4000 , 0x0);
+
+ // RG_STRUP_VS1_PG_H2L_EN[15:15] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0xA , 0x8000 , 0x8000 , 0x0);
+
+ // UVLO_L2H_DEB_EN[5:5] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0x18 , 0x20 , 0x20 , 0x0);
+
+ // STRUP_AUXADC_RSTB_SEL[7:7] = 0x1 => 6/2,Dennis
+ PMIC_DRV_SetData(0x1C , 0x80 , 0x80 , 0x0);
+
+ // STRUP_PWROFF_SEQ_EN[0:0] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0x1E , 0x1 , 0x1 , 0x0);
+
+ // STRUP_PWROFF_PREOFF_EN[1:1] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0x1E , 0x2 , 0x2 , 0x0);
+
+ // RG_STRUP_ENVTEM_CTRL[15:15] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0x2C , 0x8000 , 0x8000 , 0x0);
+
+ // RG_EN_DRVSEL[2:2] = 0x1 => 6/1,Seven,PMU EN Driver Ability
+ PMIC_DRV_SetData(0x32 , 0x4 , 0x4 , 0x0);
+
+ // RG_RST_DRVSEL[3:3] = 0x1 => 6/1,Seven,RESETB Driver Ability
+ PMIC_DRV_SetData(0x32 , 0x8 , 0x8 , 0x0);
+
+ // RG_SRCLKEN_IN0_HW_MODE[4:4] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x204 , 0x10 , 0x10 , 0x0);
+
+ // RG_SRCLKEN_IN1_HW_MODE[5:5] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x204 , 0x20 , 0x20 , 0x0);
+
+ // RG_OSC_SEL_HW_MODE[6:6] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x204 , 0x40 , 0x40 , 0x0);
+
+ // RG_SMT_WDTRSTB_IN[0:0] = 0x1 => 6/1,Seven
+ PMIC_DRV_SetData(0x226 , 0x1 , 0x1 , 0x0);
+
+ // RG_SMT_SPI_CLK[0:0] = 0x1 => 6/1,Check with Juinn-Ting
+ PMIC_DRV_SetData(0x228 , 0x1 , 0x1 , 0x0);
+
+ // RG_SMT_SPI_CSN[1:1] = 0x1 => 6/1,Check with Juinn-Ting
+ PMIC_DRV_SetData(0x228 , 0x2 , 0x2 , 0x0);
+
+ // RG_SMT_SPI_MOSI[2:2] = 0x1 => 6/1,Check with Juinn-Ting
+ PMIC_DRV_SetData(0x228 , 0x4 , 0x4 , 0x0);
+
+ // RG_SMT_SPI_MISO[3:3] = 0x1 => 6/1,Check with Juinn-Ting
+ PMIC_DRV_SetData(0x228 , 0x8 , 0x8 , 0x0);
+
+ // RG_AUXADC_SMPS_CK_PDN[9:9] = 0x0 => 9/7 Peter SW,for AUXADC need always on
+ PMIC_DRV_SetData(0x23A , 0x200 , 0x0 , 0x0);
+
+ // RG_AUXADC_26M_CK_PDN[11:11] = 0x1
+ PMIC_DRV_SetData(0x23A , 0x800 , 0x800 , 0x0);
+
+ // RG_RTC_75K_CK_PDN[2:2] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x240 , 0x4 , 0x4 , 0x0);
+
+ // RG_RTCDET_CK_PDN[3:3] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x240 , 0x8 , 0x8 , 0x0);
+
+ // RG_AUXADC_CK_PDN[10:10] = 0x0
+ PMIC_DRV_SetData(0x240 , 0x400 , 0x0 , 0x0);
+
+ // RG_RTC_EOSC32_CK_PDN[13:13] = 0x1 => Juinn-Ting(if 32 less keep default Value)
+ PMIC_DRV_SetData(0x246 , 0x2000 , 0x2000 , 0x0);
+
+ // RG_TRIM_75K_CK_PDN[14:14] = 0x1 => Juinn-Ting
+ PMIC_DRV_SetData(0x246 , 0x4000 , 0x4000 , 0x0);
+
+ // RG_EFUSE_CK_PDN[2:2] = 0x0
+ PMIC_DRV_SetData(0x24C , 0x4 , 0x0 , 0x0);
+
+ // RG_BUCK_VSRAM_MD_9M_CK_PDN[5:5] = 0x0
+ PMIC_DRV_SetData(0x258 , 0x20 , 0x0 , 0x0);
+
+ // RG_AUD18M_CK_PDN[8:8] = 0x1
+ PMIC_DRV_SetData(0x258 , 0x100 , 0x100 , 0x0);
+
+ // RG_BUCK_AUD_1M_CK_PDN[14:14] = 0x0
+ PMIC_DRV_SetData(0x258 , 0x4000 , 0x0 , 0x0);
+
+ // RG_75K_32K_SEL[9:9] = 0x1 => Angela
+ PMIC_DRV_SetData(0x25E , 0x200 , 0x200 , 0x0);
+
+ // RG_AUXADC_CK_CKSEL[10:10] = 0x0
+ PMIC_DRV_SetData(0x25E , 0x400 , 0x0 , 0x0);
+
+ // RG_AUXADC_CK_PDN_HWEN[3:3] = 0x0
+ PMIC_DRV_SetData(0x282 , 0x8 , 0x0 , 0x0);
+
+ // RG_AUXADC_SMPS_CK_PDN_HWEN[4:4] = 0x0 => 9/7,Peter SW,For Auxadc need always on
+ PMIC_DRV_SetData(0x282 , 0x10 , 0x0 , 0x0);
+
+ // RG_AUXADC_26M_CK_PDN_HWEN[10:10] = 0x0 => ZF
+ PMIC_DRV_SetData(0x282 , 0x400 , 0x0 , 0x0);
+
+ // RG_AUXADC_CK_CKSEL_HWEN[11:11] = 0x0 => ZF
+ PMIC_DRV_SetData(0x282 , 0x800 , 0x0 , 0x0);
+
+ // RG_AUD18M_CK_PDN_HWEN[4:4] = 0x0
+ PMIC_DRV_SetData(0x28E , 0x10 , 0x0 , 0x0);
+
+ // BUCK_VPA_VOSEL_DLC001[13:8] = 0x8 => 6/24,Paul
+ PMIC_DRV_SetData(0x410 , 0x3F00 , 0x800 , 0x0);
+
+ // BUCK_VPA_DVS_TRANS_CTRL[5:4] = 0x3 => 6/24,Paul
+ PMIC_DRV_SetData(0x414 , 0x30 , 0x30 , 0x0);
+
+ // BUCK_VPA_EN_OC_SDN_SEL[7:7] = 0x1 => 9/14,Stephen PA OC Shutdown by Filed Test need disable
+ PMIC_DRV_SetData(0x422 , 0x80 , 0x80 , 0x0);
+
+ // BUCK_VPA_OC_WND[3:2] = 0x0 => 6/1 Paul OC Shutdiwn debounce Time 16us to 128us
+ PMIC_DRV_SetData(0x436 , 0xC , 0x0 , 0x0);
+
+ // RG_VCORE_CSL[14:11] = 0xF => 6/1,Tim,OC Level Adjust
+ PMIC_DRV_SetData(0x450 , 0x7800 , 0x7800 , 0x0);
+
+ // RG_VCORE_ADRC_FEN[3:3] = 0x1 => 6/1,Tim,Bandwidth Extend
+ PMIC_DRV_SetData(0x452 , 0x8 , 0x8 , 0x0);
+
+ // RG_VCORE_NLIM_GATING[7:7] = 0x1 => 8/17,Tim
+ PMIC_DRV_SetData(0x456 , 0x80 , 0x80 , 0x0);
+
+ // RG_VCORE_VDIFF_ENLOWIQ[1:1] = 0x1 => 6/1,Tim,Ultra Low Iq
+ PMIC_DRV_SetData(0x45C , 0x2 , 0x2 , 0x0);
+
+ // RG_VCORE_RSV[15:0] = 0x400 => 6/1,Tim,Enable Pre-OC
+ PMIC_DRV_SetData(0x45E , 0xFFFF , 0x400 , 0x0);
+
+ // RG_VGPU_CSL[14:11] = 0xF => 6/1,Tim,OC Level Adjust
+ PMIC_DRV_SetData(0x464 , 0x7800 , 0x7800 , 0x0);
+
+ // RG_VGPU_ADRC_FEN[3:3] = 0x1 => 6/1,Tim,Bandwidth Extend
+ PMIC_DRV_SetData(0x466 , 0x8 , 0x8 , 0x0);
+
+ // RG_VGPU_PFMOC[11:9] = 0x5 => 8/24,Tim PFM OC Adjust for DVS Performance
+ PMIC_DRV_SetData(0x466 , 0xE00 , 0xA00 , 0x0);
+
+ // RG_VGPU_NLIM_GATING[7:7] = 0x1 => 8/17,Tim
+ PMIC_DRV_SetData(0x46A , 0x80 , 0x80 , 0x0);
+
+ // RG_VGPU_VDIFF_ENLOWIQ[1:1] = 0x1 => 6/1,Tim,Ultra Low Iq
+ PMIC_DRV_SetData(0x470 , 0x2 , 0x2 , 0x0);
+
+ // RG_VGPU_RSV[15:0] = 0x400 => 6/1,Tim,Enable Pre-OC
+ PMIC_DRV_SetData(0x472 , 0xFFFF , 0x400 , 0x0);
+
+ // RG_VSRAM_MD_CSL[14:11] = 0xF => 6/1, Johnson, OC performance fine tune
+ PMIC_DRV_SetData(0x478 , 0x7800 , 0x7800 , 0x0);
+
+ // RG_VSRAM_MD_PFMOC[8:6] = 0x2 => 6/1, Johnson, PFM ripple performance fine tune
+ PMIC_DRV_SetData(0x47A , 0x1C0 , 0x80 , 0x0);
+
+ // RG_VSRAM_MD_NLIM_GATING[1:1] = 0x1 => 6/24,Johnson,for transient mode transition Vo ringing, performance concern.
+ PMIC_DRV_SetData(0x47E , 0x2 , 0x2 , 0x0);
+
+ // RG_VSRAM_MD_PFM_RIP[6:4] = 0x1 => 6/1, Johnson, performance fine tune.(PFM ripple)
+ PMIC_DRV_SetData(0x480 , 0x70 , 0x10 , 0x0);
+
+ // RG_VSRAM_MD_VDIFF_ENLOWIQ[1:1] = 0x1 => 6/1, Johnson, performance improvement. (iq, mode transition and pfm ripple H/L
+ PMIC_DRV_SetData(0x484 , 0x2 , 0x2 , 0x0);
+
+ // RG_VMODEM_CSL[14:11] = 0xF => 6/1, Johnson, OC performance fine tune
+ PMIC_DRV_SetData(0x48C , 0x7800 , 0x7800 , 0x0);
+
+ // RG_VMODEM_PFMOC[8:6] = 0x2 => 6/1, Johnson, PFM ripple performance fine tune
+ PMIC_DRV_SetData(0x48E , 0x1C0 , 0x80 , 0x0);
+
+ // RG_VMODEM_NLIM_GATING[1:1] = 0x1 => 6/24,Johnson,for transient mode transition Vo ringing, performance concern.
+ PMIC_DRV_SetData(0x492 , 0x2 , 0x2 , 0x0);
+
+ // RG_VMODEM_PFM_RIP[6:4] = 0x1 => 6/1, Johnson, performance fine tune.(PFM ripple)
+ PMIC_DRV_SetData(0x494 , 0x70 , 0x10 , 0x0);
+
+ // RG_VMODEM_VDIFF_ENLOWIQ[1:1] = 0x1 => 6/1, Johnson, performance improvement. (iq, mode transition and pfm ripple H/L
+ PMIC_DRV_SetData(0x498 , 0x2 , 0x2 , 0x0);
+
+ // RG_VMD1_CSL[14:11] = 0xF => 6/1, Johnson, OC performance fine tune
+ PMIC_DRV_SetData(0x4A0 , 0x7800 , 0x7800 , 0x0);
+
+ // RG_VMD1_PFMOC[8:6] = 0x2 => 6/1, Johnson, PFM ripple performance fine tune
+ PMIC_DRV_SetData(0x4A2 , 0x1C0 , 0x80 , 0x0);
+
+ // RG_VMD1_NLIM_GATING[1:1] = 0x1 => 6/24,Johnson,for transient mode transition Vo ringing, performance concern.
+ PMIC_DRV_SetData(0x4A6 , 0x2 , 0x2 , 0x0);
+
+ // RG_VMD1_PFM_RIP[6:4] = 0x1 => 6/1, Johnson, performance fine tune.(PFM ripple)
+ PMIC_DRV_SetData(0x4A8 , 0x70 , 0x10 , 0x0);
+
+ // RG_VMD1_VDIFF_ENLOWIQ[1:1] = 0x1 => 6/1, Johnson, performance improvement. (iq, mode transition and pfm ripple H/L
+ PMIC_DRV_SetData(0x4AC , 0x2 , 0x2 , 0x0);
+
+ // RG_VS1_PFMOC[8:6] = 0x6 => 7/15,Lan improve ZXOS Detect
+ PMIC_DRV_SetData(0x4B6 , 0x1C0 , 0x180 , 0x0);
+
+ // RG_VS1_RSV[15:0] = 0x10 => 6/2, Hung Mu Chou, OC Level Adjust
+ PMIC_DRV_SetData(0x4C2 , 0xFFFF , 0x10 , 0x0);
+
+ // RG_VS2_CSL[14:11] = 0xF => 7/15,Lan improve ZXOS Detect
+ PMIC_DRV_SetData(0x4C8 , 0x7800 , 0x7800 , 0x0);
+
+ // RG_VS2_PFMOC[8:6] = 0x5 => 7/15,Lan improve ZXOS Detect
+ PMIC_DRV_SetData(0x4CA , 0x1C0 , 0x140 , 0x0);
+
+ // RG_VS2_NLIM_GATING[1:1] = 0x1 => 6/1 Lan NLIM_Gating Enable
+ PMIC_DRV_SetData(0x4CE , 0x2 , 0x2 , 0x0);
+
+ // RG_VS2_PFM_RIP[6:4] = 0x1 => 6/1 Lan PWM/PFM Output accuracy adjust
+ PMIC_DRV_SetData(0x4D0 , 0x70 , 0x10 , 0x0);
+
+ // RG_VPA_CC[1:0] = 0x3 => 6/24 Paul VPA compensation C adjust
+ PMIC_DRV_SetData(0x4DC , 0x3 , 0x3 , 0x0);
+
+ // RG_VPA_CSMIR[5:4] = 0x2 => 8/27,Paul reduce 20% Current sensing ratio
+ PMIC_DRV_SetData(0x4DC , 0x30 , 0x20 , 0x0);
+
+ // RG_VPA_AZC_EN[10:10] = 0x0 => 6/3,Paul
+ PMIC_DRV_SetData(0x4DC , 0x400 , 0x0 , 0x0);
+
+ // RG_VPA_RZSEL[15:14] = 0x1 => 8/27,Paul Compensation resistance 310k>210K
+ PMIC_DRV_SetData(0x4DC , 0xC000 , 0x4000 , 0x0);
+
+ // RG_VPA_MIN_PK[15:14] = 0x0 => 6/1 Paul MIN Peak Current 250mA to 100mA
+ PMIC_DRV_SetData(0x4E0 , 0xC000 , 0x0 , 0x0);
+
+ // RG_VPA_RSV2[15:8] = 0x88 => 8/10,Paul, Auto Change Slope compensation
+ PMIC_DRV_SetData(0x4E2 , 0xFF00 , 0x8800 , 0x0);
+
+ // BUCK_VCORE_VOSEL_CTRL[1:1] = 0x1 => 6/1,Tim,Sleep mode by HW Control
+ PMIC_DRV_SetData(0x600 , 0x2 , 0x2 , 0x0);
+
+ // BUCK_VCORE_SFCHG_FRATE[6:0] = 0x11 => 6/1,Tim,DVS Falling Slew Rate
+ PMIC_DRV_SetData(0x606 , 0x7F , 0x11 , 0x0);
+
+ // BUCK_VCORE_SFCHG_RRATE[14:8] = 0x4 => 6/1,Tim,DVS Rising Slew Rate
+ PMIC_DRV_SetData(0x606 , 0x7F00 , 0x400 , 0x0);
+
+ // BUCK_VCORE_VOSEL_SLEEP[6:0] = 0x10 => 6/1,Tim Sleep mode voltage for JADE(0.7V)
+ PMIC_DRV_SetData(0x60C , 0x7F , 0x10 , 0x0);
+
+ // BUCK_VCORE_TRANS_TD[1:0] = 0x3 => 6/1,Tim
+ PMIC_DRV_SetData(0x612 , 0x3 , 0x3 , 0x0);
+
+ // BUCK_VCORE_TRANS_CTRL[5:4] = 0x1 => 8/17,Tim
+ PMIC_DRV_SetData(0x612 , 0x30 , 0x10 , 0x0);
+
+ // BUCK_VCORE_VSLEEP_EN[8:8] = 0x1 => 6/1,Tim,Sleep mode by HW Control
+ PMIC_DRV_SetData(0x612 , 0x100 , 0x100 , 0x0);
+
+ // BUCK_VGPU_SFCHG_FRATE[6:0] = 0x11 => 6/1,Tim,DVS Falling Slew Rate
+ PMIC_DRV_SetData(0x61A , 0x7F , 0x11 , 0x0);
+
+ // BUCK_VGPU_SFCHG_RRATE[14:8] = 0x4 => 6/1,Tim,DVS Rising Slew Rate
+ PMIC_DRV_SetData(0x61A , 0x7F00 , 0x400 , 0x0);
+
+ // BUCK_VGPU_VOSEL_SLEEP[6:0] = 0x10 => 6/1,Tim Sleep mode voltage for JADE(0.7V)
+ PMIC_DRV_SetData(0x620 , 0x7F , 0x10 , 0x0);
+
+ // BUCK_VGPU_TRANS_TD[1:0] = 0x3 => 6/1,Tim
+ PMIC_DRV_SetData(0x626 , 0x3 , 0x3 , 0x0);
+
+ // BUCK_VGPU_TRANS_CTRL[5:4] = 0x1 => 8/17,Tim
+ PMIC_DRV_SetData(0x626 , 0x30 , 0x10 , 0x0);
+
+ // BUCK_VMODEM_SFCHG_FRATE[6:0] = 0x11 => 6/1, Johnson,softchange for DVS/DVFS slew rate falling 2.0us/step
+ PMIC_DRV_SetData(0x62E , 0x7F , 0x11 , 0x0);
+
+ // BUCK_VMODEM_SFCHG_RRATE[14:8] = 0x4 => 6/1, Johnson,softchange for DVS/DVFS slew rate rising 0.5us/step
+ PMIC_DRV_SetData(0x62E , 0x7F00 , 0x400 , 0x0);
+
+ // BUCK_VMODEM_VOSEL_SLEEP[6:0] = 0x10 => 6/1, Johnson SRCLKEN sleep V is 0.7V
+ PMIC_DRV_SetData(0x634 , 0x7F , 0x10 , 0x0);
+
+ // BUCK_VMODEM_TRANS_TD[1:0] = 0x3 => 6/1, Johnson, falling for DVFS/DVS discharge extension time control
+ PMIC_DRV_SetData(0x63A , 0x3 , 0x3 , 0x0);
+
+ // BUCK_VMODEM_TRANS_CTRL[5:4] = 0x1 => 6/1, Johnson, falling for DVFS/DVS discharge slew rate control
+ PMIC_DRV_SetData(0x63A , 0x30 , 0x10 , 0x0);
+
+ // BUCK_VMODEM_VSLEEP_EN[8:8] = 0x1 => 6/1, Johnson, r2r power down with srclken sleep hw mode
+ PMIC_DRV_SetData(0x63A , 0x100 , 0x100 , 0x0);
+
+ // BUCK_VMD1_SFCHG_FRATE[6:0] = 0x11 => 6/1, Johnson,softchange for DVS/DVFS slew rate falling 2.0us/step
+ PMIC_DRV_SetData(0x642 , 0x7F , 0x11 , 0x0);
+
+ // BUCK_VMD1_SFCHG_RRATE[14:8] = 0x4 => 6/1, Johnson,softchange for DVS/DVFS slew rate rising 0.5us/step
+ PMIC_DRV_SetData(0x642 , 0x7F00 , 0x400 , 0x0);
+
+ // BUCK_VMD1_VOSEL_ON[6:0] = 0x30 => 6/1, Johnson SRCLKEN normal v is 0.9V
+ PMIC_DRV_SetData(0x646 , 0x7F , 0x30 , 0x0);
+
+ // BUCK_VMD1_VOSEL_SLEEP[6:0] = 0x10 => 6/1, Johnson SRCLKEN sleep V is 0.7V
+ PMIC_DRV_SetData(0x648 , 0x7F , 0x10 , 0x0);
+
+ // BUCK_VMD1_TRANS_TD[1:0] = 0x3 => 6/1, Johnson, falling for DVFS/DVS discharge extension time control
+ PMIC_DRV_SetData(0x64E , 0x3 , 0x3 , 0x0);
+
+ // BUCK_VMD1_TRANS_CTRL[5:4] = 0x1 => 6/1, Johnson, falling for DVFS/DVS discharge slew rate control
+ PMIC_DRV_SetData(0x64E , 0x30 , 0x10 , 0x0);
+
+ // BUCK_VMD1_VSLEEP_EN[8:8] = 0x1 => 6/1, Johnson, r2r power down with srclken sleep hw mode, after vo sel
+ PMIC_DRV_SetData(0x64E , 0x100 , 0x100 , 0x0);
+
+ // BUCK_VSRAM_MD_SFCHG_FRATE[6:0] = 0x11 => 6/1, Johnson,softchange for DVS/DVFS slew rate falling 2.0us/step
+ PMIC_DRV_SetData(0x656 , 0x7F , 0x11 , 0x0);
+
+ // BUCK_VSRAM_MD_SFCHG_RRATE[14:8] = 0x4 => 6/1, Johnson,softchange for DVS/DVFS slew rate rising 0.5us/step
+ PMIC_DRV_SetData(0x656 , 0x7F00 , 0x400 , 0x0);
+
+ // BUCK_VSRAM_MD_VOSEL_SLEEP[6:0] = 0x10 => 6/1, Johnson SRCLKEN sleep V is 0.7V
+ PMIC_DRV_SetData(0x65C , 0x7F , 0x10 , 0x0);
+
+ // BUCK_VSRAM_MD_TRANS_TD[1:0] = 0x3 => 6/1, Johnson, falling for DVFS/DVS discharge extension time control
+ PMIC_DRV_SetData(0x662 , 0x3 , 0x3 , 0x0);
+
+ // BUCK_VSRAM_MD_TRANS_CTRL[5:4] = 0x1 => 6/1, Johnson, falling for DVFS/DVS discharge slew rate control
+ PMIC_DRV_SetData(0x662 , 0x30 , 0x10 , 0x0);
+
+ // BUCK_VSRAM_MD_VSLEEP_EN[8:8] = 0x1 => 6/1, Johnson, r2r power down with srclken sleep hw mode, after vo sel
+ PMIC_DRV_SetData(0x662 , 0x100 , 0x100 , 0x0);
+
+ // BUCK_VS1_VSLEEP_EN[8:8] = 0x1 => 6/1,Lan,r2r power down with srclken sleep hw mode
+ PMIC_DRV_SetData(0x676 , 0x100 , 0x100 , 0x0);
+
+ // BUCK_VS2_VSLEEP_EN[8:8] = 0x1 => 6/1,Lan,r2r power down with srclken sleep hw mode
+ PMIC_DRV_SetData(0x68A , 0x100 , 0x100 , 0x0);
+
+ // BUCK_VPA_SFCHG_FRATE[6:0] = 0x0 => 6/3,Paul
+ PMIC_DRV_SetData(0x692 , 0x7F , 0x0 , 0x0);
+
+ // BUCK_VPA_SFCHG_RRATE[14:8] = 0x1 => 6/3,Paul
+ PMIC_DRV_SetData(0x692 , 0x7F00 , 0x100 , 0x0);
+
+ // BUCK_VPA_TRANS_TD[1:0] = 0x0 => 624,Paul
+ PMIC_DRV_SetData(0x69E , 0x3 , 0x0 , 0x0);
+
+ // BUCK_VSRAM_PROC_VOSEL_CTRL[1:1] = 0x1 => 6/5,Chia Lin
+ PMIC_DRV_SetData(0x6A0 , 0x2 , 0x2 , 0x0);
+
+ // BUCK_VSRAM_PROC_SFCHG_FRATE[6:0] = 0x11 => 6/5,Chia Lin
+ PMIC_DRV_SetData(0x6A6 , 0x7F , 0x11 , 0x0);
+
+ // BUCK_VSRAM_PROC_SFCHG_RRATE[14:8] = 0x4 => 6/5,Chia Lin
+ PMIC_DRV_SetData(0x6A6 , 0x7F00 , 0x400 , 0x0);
+
+ // BUCK_VSRAM_PROC_VOSEL_SLEEP[6:0] = 0x35 => 6/5,Chia Lin(Sleep mode voltage 0.93125V)
+ PMIC_DRV_SetData(0x6AC , 0x7F , 0x35 , 0x0);
+
+ // BUCK_VSRAM_PROC_TRANS_TD[1:0] = 0x3 => 6/5,Chia Lin
+ PMIC_DRV_SetData(0x6B2 , 0x3 , 0x3 , 0x0);
+
+ // BUCK_VSRAM_PROC_TRANS_CTRL[5:4] = 0x1 => 6/5,Chia Lin
+ PMIC_DRV_SetData(0x6B2 , 0x30 , 0x10 , 0x0);
+
+ // BUCK_VSRAM_PROC_VSLEEP_EN[8:8] = 0x0 => 7/15,Chia Lin
+ PMIC_DRV_SetData(0x6B2 , 0x100 , 0x0 , 0x0);
+
+ // RG_VA18_MODE_CTRL[2:2] = 0x1 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA00 , 0x4 , 0x4 , 0x0);
+
+ // RG_VA18_SRCLK_MODE_SEL[7:5] = 0x0 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA00 , 0xE0 , 0x0 , 0x0);
+
+ // RG_VA18_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA02 , 0x200 , 0x200 , 0x0);
+
+ // RG_VTCXO24_ON_CTRL[3:3] = 0x1 => 6/2,CW
+ //PMIC_DRV_SetData(0xA04 , 0x8 , 0x8 , 0x0);
+
+ // RG_VTCXO24_SRCLK_EN_SEL[13:11] = 0x0 => 6/2,CW,RF Power Control request
+ //PMIC_DRV_SetData(0xA04 , 0x3800 , 0x0 , 0x0);
+
+ // RG_VTCXO24_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA06 , 0x200 , 0x200 , 0x0);
+
+ // RG_VTCXO28_ON_CTRL[3:3] = 0x1 => 6/2,CW
+ PMIC_DRV_SetData(0xA08 , 0x8 , 0x8 , 0x0);
+
+ // RG_VTCXO28_SRCLK_EN_SEL[13:11] = 0x1 => 6/2,CW,RF Power Control request
+ PMIC_DRV_SetData(0xA08 , 0x3800 , 0x800 , 0x0);
+
+ // RG_VTCXO28_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA0A , 0x200 , 0x200 , 0x0);
+
+ // RG_VCN28_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA0E , 0x200 , 0x200 , 0x0);
+
+ // RG_VCAMA_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA14 , 0x200 , 0x200 , 0x0);
+
+ // RG_VUSB33_MODE_CTRL[2:2] = 0x1 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA16 , 0x4 , 0x4 , 0x0);
+
+ // RG_VUSB33_SRCLK_MODE_SEL[7:5] = 0x0 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA16 , 0xE0 , 0x0 , 0x0);
+
+ // RG_VUSB33_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA18 , 0x200 , 0x200 , 0x0);
+
+ // RG_VSIM1_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA1E , 0x200 , 0x200 , 0x0);
+
+ // RG_VSIM2_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA24 , 0x200 , 0x200 , 0x0);
+
+ // RG_VEMC_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA2A , 0x200 , 0x200 , 0x0);
+
+ // RG_VMCH_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA30 , 0x200 , 0x200 , 0x0);
+
+ // RG_VIO28_MODE_CTRL[2:2] = 0x1 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA34 , 0x4 , 0x4 , 0x0);
+
+ // RG_VIO28_SRCLK_MODE_SEL[7:5] = 0x0 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA34 , 0xE0 , 0x0 , 0x0);
+
+ // RG_VIO28_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA36 , 0x200 , 0x200 , 0x0);
+
+ // RG_VIBR_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA3C , 0x200 , 0x200 , 0x0);
+
+ // RG_VRF18_ON_CTRL[3:3] = 0x1 => 6/2,CW
+ PMIC_DRV_SetData(0xA46 , 0x8 , 0x8 , 0x0);
+
+ // RG_VRF18_SRCLK_EN_SEL[13:11] = 0x1 => 6/2,CW,RF Power Control request
+ PMIC_DRV_SetData(0xA46 , 0x3800 , 0x800 , 0x0);
+
+ // RG_VRF18_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA48 , 0x200 , 0x200 , 0x0);
+
+ // RG_VIO18_MODE_CTRL[2:2] = 0x1 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA4C , 0x4 , 0x4 , 0x0);
+
+ // RG_VIO18_SRCLK_MODE_SEL[7:5] = 0x0 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA4C , 0xE0 , 0x0 , 0x0);
+
+ // RG_VIO18_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA4E , 0x200 , 0x200 , 0x0);
+
+ // RG_VCN18_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA54 , 0x200 , 0x200 , 0x0);
+
+ // RG_VCAMIO_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA5A , 0x200 , 0x200 , 0x0);
+
+ // RG_VXO22_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA66 , 0x200 , 0x200 , 0x0);
+
+ // RG_VRF12_ON_CTRL[3:3] = 0x1 => 6/2,CW
+ PMIC_DRV_SetData(0xA68 , 0x8 , 0x8 , 0x0);
+
+ // RG_VRF12_SRCLK_EN_SEL[13:11] = 0x1 => 6/2,CW,RF Power Control request
+ PMIC_DRV_SetData(0xA68 , 0x3800 , 0x800 , 0x0);
+
+ // RG_VA10_MODE_CTRL[2:2] = 0x1 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA6E , 0x4 , 0x4 , 0x0);
+
+ // RG_VA10_SRCLK_MODE_SEL[7:5] = 0x0 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA6E , 0xE0 , 0x0 , 0x0);
+
+ // RG_VDRAM_EN[1:1] = 0x1 => 6/5,Chia Lin Same as Fly suspend mode
+ PMIC_DRV_SetData(0xA74 , 0x2 , 0x2 , 0x0);
+
+ // RG_VDRAM_MODE_CTRL[2:2] = 0x1 => 6/5,Chia Lin Same as Fly suspend mode
+ PMIC_DRV_SetData(0xA74 , 0x4 , 0x4 , 0x0);
+
+ // RG_VDRAM_ON_CTRL[3:3] = 0x0 => 6/5,Chia Lin Same as Fly suspend mode
+ PMIC_DRV_SetData(0xA74 , 0x8 , 0x0 , 0x0);
+
+ // RG_VDRAM_SRCLK_MODE_SEL[7:5] = 0x0 => 6/5,Chia Lin Same as Fly suspend mode
+ PMIC_DRV_SetData(0xA74 , 0xE0 , 0x0 , 0x0);
+
+ // RG_VMIPI_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA7C , 0x200 , 0x200 , 0x0);
+
+ // RG_VGP3_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA82 , 0x200 , 0x200 , 0x0);
+
+ // RG_VBIF28_ON_CTRL[3:3] = 0x0 => 6/1,Seven,
+ PMIC_DRV_SetData(0xA86 , 0x8 , 0x0 , 0x0);
+
+ // RG_VBIF28_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA88 , 0x200 , 0x200 , 0x0);
+
+ // RG_VEFUSE_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA8E , 0x200 , 0x200 , 0x0);
+
+ // RG_VCN33_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA94 , 0x200 , 0x200 , 0x0);
+
+ // RG_VLDO28_MODE_CTRL[2:2] = 0x1 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA9C , 0x4 , 0x4 , 0x0);
+
+ // RG_VLDO28_SRCLK_MODE_SEL[7:5] = 0x0 => 7/28 Chia Lin
+ PMIC_DRV_SetData(0xA9C , 0xE0 , 0x0 , 0x0);
+
+ // RG_VLDO28_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xA9E , 0x200 , 0x200 , 0x0);
+
+ // RG_VMC_OCFB_EN[9:9] = 0x1 => 6/1 Fandy Enable OCFB
+ PMIC_DRV_SetData(0xAAC , 0x200 , 0x200 , 0x0);
+
+ // RG_VA10_VOSEL[10:8] = 0x2 => 6/8,KH for JADE VA10=1V
+ PMIC_DRV_SetData(0xB10 , 0x700 , 0x200 , 0x0);
+
+ // RG_VDRAM_RSV[9:2] = 0xF0 => 6/1 Fandy improve Fast Transient
+ PMIC_DRV_SetData(0xB24 , 0x3FC , 0x3C0 , 0x0);
+
+ // FG_SLP_EN[8:8] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xCC4 , 0x100 , 0x100 , 0x0);
+
+ // FG_ZCV_DET_EN[9:9] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xCC4 , 0x200 , 0x200 , 0x0);
+
+ // FG_SLP_CUR_TH[15:0] = 0x1F => 6/1,Filby
+ PMIC_DRV_SetData(0xCC8 , 0xFFFF , 0x1F , 0x0);
+
+ // FG_SLP_TIME[7:0] = 0x14 => 6/1,Filby
+ PMIC_DRV_SetData(0xCCA , 0xFF , 0x14 , 0x0);
+
+ // FG_DET_TIME[15:8] = 0xFF => 6/1,Filby
+ PMIC_DRV_SetData(0xCCC , 0xFF00 , 0xFF00 , 0x0);
+
+ // FG_ZCV_CAR_TH_33_19[14:0] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xCE2 , 0x7FFF , 0x1 , 0x0);
+
+ // FG_ZCV_CAR_TH_18_03[15:0] = 0xBCAC => 6/1,Filby
+ PMIC_DRV_SetData(0xCE4 , 0xFFFF , 0xBCAC , 0x0);
+
+ // AUXADC_CK_AON_GPS[13:13] = 0x0 => Check with Peter
+ PMIC_DRV_SetData(0xEA2 , 0x2000 , 0x0 , 0x0);
+
+ // AUXADC_CK_AON_MD[14:14] = 0x0 => Check with Peter
+ PMIC_DRV_SetData(0xEA2 , 0x4000 , 0x0 , 0x0);
+
+ // AUXADC_CK_AON[15:15] = 0x0 => Check with Peter
+ PMIC_DRV_SetData(0xEA2 , 0x8000 , 0x0 , 0x0);
+
+ // AUXADC_AVG_NUM_SEL[11:0] = 0x83 => 6/1,Filby,Resolution Adjust
+ PMIC_DRV_SetData(0xEAA , 0xFFF , 0x83 , 0x0);
+
+ // AUXADC_AVG_NUM_SEL_LBAT[13:13] = 0x0 => 8/3,Filby,Resolution Adjust
+ PMIC_DRV_SetData(0xEAA , 0x2000 , 0x0 , 0x0);
+
+ // AUXADC_AVG_NUM_SEL_WAKEUP[15:15] = 0x1 => 6/1,Filby,Resolution Adjust
+ PMIC_DRV_SetData(0xEAA , 0x8000 , 0x8000 , 0x0);
+
+ // AUXADC_TRIM_CH2_SEL[5:4] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB2 , 0x30 , 0x10 , 0x0);
+
+ // AUXADC_TRIM_CH3_SEL[7:6] = 0x3 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB2 , 0xC0 , 0xC0 , 0x0);
+
+ // AUXADC_TRIM_CH4_SEL[9:8] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB2 , 0x300 , 0x100 , 0x0);
+
+ // AUXADC_TRIM_CH5_SEL[11:10] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB2 , 0xC00 , 0x400 , 0x0);
+
+ // AUXADC_TRIM_CH6_SEL[13:12] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB2 , 0x3000 , 0x1000 , 0x0);
+
+ // AUXADC_TRIM_CH7_SEL[15:14] = 0x2 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB2 , 0xC000 , 0x8000 , 0x0);
+
+ // AUXADC_TRIM_CH8_SEL[1:0] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB4 , 0x3 , 0x1 , 0x0);
+
+ // AUXADC_TRIM_CH9_SEL[3:2] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB4 , 0xC , 0x4 , 0x0);
+
+ // AUXADC_TRIM_CH10_SEL[5:4] = 0x1 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB4 , 0x30 , 0x10 , 0x0);
+
+ // AUXADC_TRIM_CH11_SEL[7:6] = 0x3 => 6/1,Filby
+ PMIC_DRV_SetData(0xEB4 , 0xC0 , 0xC0 , 0x0);
+
+ // AUXADC_START_SHADE_EN[14:14] = 0x1 => TBD(Wei-Lin)
+ PMIC_DRV_SetData(0xEC6 , 0x4000 , 0x4000 , 0x0);
+
+ // AUXADC_MDBG_DET_PRD[9:0] = 0x40 => 6/2,Dennis
+ PMIC_DRV_SetData(0xF16 , 0x3FF , 0x40 , 0x0);
+
+ // AUXADC_MDBG_DET_EN[15:15] = 0x1 => 6/2,Dennis
+ PMIC_DRV_SetData(0xF16 , 0x8000 , 0x8000 , 0x0);
+
+ // AUXADC_MDRT_DET_PRD[9:0] = 0x40 => 6/2,Dennis
+ PMIC_DRV_SetData(0xF1C , 0x3FF , 0x40 , 0x0);
+
+ // AUXADC_MDRT_DET_EN[15:15] = 0x1 => 6/2,Dennis
+ PMIC_DRV_SetData(0xF1C , 0x8000 , 0x8000 , 0x0);
+
+ // AUXADC_MDRT_DET_WKUP_EN[2:2] = 0x1 => 6/2,Dennis
+ PMIC_DRV_SetData(0xF20 , 0x4 , 0x4 , 0x0);
+
+ // RG_VCDT_HV_VTH[7:4] = 0xB => Zax: VCDT_HV_th=7V (customized setting for VBUS OVP)
+ PMIC_DRV_SetData(0xF7A , 0xF0 , 0xB0 , 0x0);
+
+ // RG_VBAT_OV_VTH[4:1] = 0x4 => Zax: 4.45V for 4.35v battery (customized setting based on CV_VTH, shall set OV_VTH=CV_VTH+100mV)
+
+ PMIC_DRV_SetData(0xF84 , 0x1E , 0x8 , 0x0);
+
+ // RG_CHRWDT_TD[3:0] = 0x3 => Zax:WDT=32s
+ PMIC_DRV_SetData(0xF92 , 0xF , 0x3 , 0x0);
+
+ // RG_BC11_RST[1:1] = 0x1 => Zax:Disable BC1.1 timer
+ PMIC_DRV_SetData(0xFA0 , 0x2 , 0x2 , 0x0);
+
+ // RG_CSDAC_STP_DEC[6:4] = 0x0 => Zax:Reduce ICHG current ripple
+ PMIC_DRV_SetData(0xFA4 , 0x70 , 0x0 , 0x0);
+
+ // RG_CSDAC_MODE[2:2] = 0x1 => Zax:Align 6323
+ PMIC_DRV_SetData(0xFAA , 0x4 , 0x4 , 0x0);
+
+ // RG_HWCV_EN[6:6] = 0x1 => Zax:Align 6323
+ PMIC_DRV_SetData(0xFAA , 0x40 , 0x40 , 0x0);
+
+ // RG_ULC_DET_EN[7:7] = 0x1 => Zax: need to enable for supporting bad TA
+ PMIC_DRV_SetData(0xFAA , 0x80 , 0x80 , 0x0);
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6355.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6355.c
new file mode 100644
index 0000000..11ac04c
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6355.c
@@ -0,0 +1,2405 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6355_37.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6355
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+
+#if defined(PMIC_6355_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+
+extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
+extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
+extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
+extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic_hw_version;
+kal_uint8 pmic_sw_version;
+kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {PMIC_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {PMIC_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {PMIC_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {PMIC_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {PMIC_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {PMIC_BUCK_VMODEM_CON2, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {PMIC_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {PMIC_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
+ {PMIC_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
+ {PMIC_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
+ {PMIC_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
+ {PMIC_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_VSLEEP_SEL_MASK, PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT, },
+ {PMIC_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
+ {PMIC_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
+ {PMIC_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
+ {PMIC_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
+ {PMIC_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
+ {PMIC_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
+ {PMIC_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
+ {PMIC_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
+ {PMIC_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
+ {PMIC_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
+ {PMIC_SMPS_ANA_CON4, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
+ {PMIC_SMPS_ANA_CON14, PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_MASK, PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_SHIFT, },
+ {PMIC_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
+ {PMIC_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
+ {PMIC_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_ON_OP_MASK, PMIC_RG_LDO_VSIM1_ON_OP_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_LP_OP_MASK, PMIC_RG_LDO_VSIM1_LP_OP_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VSIM1_CON2, PMIC_DA_QI_VSIM1_OCFB_EN_MASK, PMIC_DA_QI_VSIM1_OCFB_EN_SHIFT, },
+ {PMIC_DLDO_ANA_CON2, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {PMIC_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
+ {PMIC_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_ON_OP_MASK, PMIC_RG_LDO_VSIM2_ON_OP_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_LP_OP_MASK, PMIC_RG_LDO_VSIM2_LP_OP_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VSIM2_CON2, PMIC_DA_QI_VSIM2_OCFB_EN_MASK, PMIC_DA_QI_VSIM2_OCFB_EN_SHIFT, },
+ {PMIC_DLDO_ANA_CON4, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ {PMIC_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_EN_MASK, PMIC_RG_LDO_VMIPI_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_LP_MASK, PMIC_RG_LDO_VMIPI_LP_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_SW_OP_EN_MASK, PMIC_RG_LDO_VMIPI_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW0_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW1_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW2_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_EN_SET, PMIC_RG_LDO_VMIPI_OP_EN_SET_MASK, PMIC_RG_LDO_VMIPI_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_EN_CLR, PMIC_RG_LDO_VMIPI_OP_EN_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_ON_OP_MASK, PMIC_RG_LDO_VMIPI_ON_OP_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_LP_OP_MASK, PMIC_RG_LDO_VMIPI_LP_OP_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG_SET, PMIC_RG_LDO_VMIPI_OP_CFG_SET_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VMIPI_OP_CFG_CLR, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VMIPI_CON1, PMIC_DA_QI_VMIPI_MODE_MASK, PMIC_DA_QI_VMIPI_MODE_SHIFT, },
+ {PMIC_LDO_VMIPI_CON1, PMIC_DA_QI_VMIPI_EN_MASK, PMIC_DA_QI_VMIPI_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_CON2, PMIC_RG_LDO_VMIPI_OCFB_EN_MASK, PMIC_RG_LDO_VMIPI_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VMIPI_CON2, PMIC_DA_QI_VMIPI_OCFB_EN_MASK, PMIC_DA_QI_VMIPI_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_CON0, PMIC_RG_LDO_VTCXO24_EN_MASK, PMIC_RG_LDO_VTCXO24_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_CON0, PMIC_RG_LDO_VTCXO24_LP_MASK, PMIC_RG_LDO_VTCXO24_LP_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_SW_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_HW0_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_HW1_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_HW2_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_EN_SET, PMIC_RG_LDO_VTCXO24_OP_EN_SET_MASK, PMIC_RG_LDO_VTCXO24_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_EN_CLR, PMIC_RG_LDO_VTCXO24_OP_EN_CLR_MASK, PMIC_RG_LDO_VTCXO24_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_MASK, PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_MASK, PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_MASK, PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_ON_OP_MASK, PMIC_RG_LDO_VTCXO24_ON_OP_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_LP_OP_MASK, PMIC_RG_LDO_VTCXO24_LP_OP_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG_SET, PMIC_RG_LDO_VTCXO24_OP_CFG_SET_MASK, PMIC_RG_LDO_VTCXO24_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VTCXO24_OP_CFG_CLR, PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_MASK, PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VTCXO24_CON1, PMIC_DA_QI_VTCXO24_MODE_MASK, PMIC_DA_QI_VTCXO24_MODE_SHIFT, },
+ {PMIC_LDO_VTCXO24_CON1, PMIC_DA_QI_VTCXO24_EN_MASK, PMIC_DA_QI_VTCXO24_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_CON2, PMIC_RG_LDO_VTCXO24_OCFB_EN_MASK, PMIC_RG_LDO_VTCXO24_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VTCXO24_CON2, PMIC_DA_QI_VTCXO24_OCFB_EN_MASK, PMIC_DA_QI_VTCXO24_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
+ {PMIC_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
+ {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VFE28_CON1, PMIC_DA_QI_VFE28_MODE_MASK, PMIC_DA_QI_VFE28_MODE_SHIFT, },
+ {PMIC_LDO_VFE28_CON1, PMIC_DA_QI_VFE28_EN_MASK, PMIC_DA_QI_VFE28_EN_SHIFT, },
+ {PMIC_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VFE28_CON2, PMIC_DA_QI_VFE28_OCFB_EN_MASK, PMIC_DA_QI_VFE28_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_CON0, PMIC_RG_LDO_VRF18_1_EN_MASK, PMIC_RG_LDO_VRF18_1_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_CON0, PMIC_RG_LDO_VRF18_1_LP_MASK, PMIC_RG_LDO_VRF18_1_LP_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_EN_SET, PMIC_RG_LDO_VRF18_1_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_1_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_EN_CLR, PMIC_RG_LDO_VRF18_1_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_1_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_ON_OP_MASK, PMIC_RG_LDO_VRF18_1_ON_OP_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_LP_OP_MASK, PMIC_RG_LDO_VRF18_1_LP_OP_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG_SET, PMIC_RG_LDO_VRF18_1_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_1_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VRF18_1_OP_CFG_CLR, PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VRF18_1_CON1, PMIC_DA_QI_VRF18_1_MODE_MASK, PMIC_DA_QI_VRF18_1_MODE_SHIFT, },
+ {PMIC_LDO_VRF18_1_CON1, PMIC_DA_QI_VRF18_1_EN_MASK, PMIC_DA_QI_VRF18_1_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_CON2, PMIC_RG_LDO_VRF18_1_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_1_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VRF18_1_CON2, PMIC_DA_QI_VRF18_1_OCFB_EN_MASK, PMIC_DA_QI_VRF18_1_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_CON0, PMIC_RG_LDO_VRF18_2_EN_MASK, PMIC_RG_LDO_VRF18_2_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_CON0, PMIC_RG_LDO_VRF18_2_LP_MASK, PMIC_RG_LDO_VRF18_2_LP_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_EN_SET, PMIC_RG_LDO_VRF18_2_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_2_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_EN_CLR, PMIC_RG_LDO_VRF18_2_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_2_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_ON_OP_MASK, PMIC_RG_LDO_VRF18_2_ON_OP_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_LP_OP_MASK, PMIC_RG_LDO_VRF18_2_LP_OP_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG_SET, PMIC_RG_LDO_VRF18_2_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_2_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VRF18_2_OP_CFG_CLR, PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VRF18_2_CON1, PMIC_DA_QI_VRF18_2_MODE_MASK, PMIC_DA_QI_VRF18_2_MODE_SHIFT, },
+ {PMIC_LDO_VRF18_2_CON1, PMIC_DA_QI_VRF18_2_EN_MASK, PMIC_DA_QI_VRF18_2_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_CON2, PMIC_RG_LDO_VRF18_2_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_2_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VRF18_2_CON2, PMIC_DA_QI_VRF18_2_OCFB_EN_MASK, PMIC_DA_QI_VRF18_2_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
+ {PMIC_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
+ {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_ON_OP_MASK, PMIC_RG_LDO_VRF12_ON_OP_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_LP_OP_MASK, PMIC_RG_LDO_VRF12_LP_OP_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VRF12_CON1, PMIC_DA_QI_VRF12_MODE_MASK, PMIC_DA_QI_VRF12_MODE_SHIFT, },
+ {PMIC_LDO_VRF12_CON1, PMIC_DA_QI_VRF12_EN_MASK, PMIC_DA_QI_VRF12_EN_SHIFT, },
+ {PMIC_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VRF12_CON2, PMIC_DA_QI_VRF12_OCFB_EN_MASK, PMIC_DA_QI_VRF12_OCFB_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_CON0, PMIC_RG_LDO_VSRAM_MD_EN_MASK, PMIC_RG_LDO_VSRAM_MD_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_CON0, PMIC_RG_LDO_VSRAM_MD_LP_MASK, PMIC_RG_LDO_VSRAM_MD_LP_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_CON1, PMIC_RG_LDO_VSRAM_MD_VOSEL_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_CON2, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_EN_SET, PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_MASK, PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_EN_CLR, PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_MASK, PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_ON_OP_MASK, PMIC_RG_LDO_VSRAM_MD_ON_OP_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_LP_OP_MASK, PMIC_RG_LDO_VSRAM_MD_LP_OP_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG_SET, PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_MASK, PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_OP_CFG_CLR, PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_CON3, PMIC_DA_QI_VSRAM_MD_MODE_MASK, PMIC_DA_QI_VSRAM_MD_MODE_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_DBG0, PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_MASK, PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_DBG0, PMIC_DA_QI_VSRAM_MD_VOSEL_MASK, PMIC_DA_QI_VSRAM_MD_VOSEL_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_DBG1, PMIC_DA_QI_VSRAM_MD_EN_MASK, PMIC_DA_QI_VSRAM_MD_EN_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_DBG1, PMIC_DA_QI_VSRAM_MD_STB_MASK, PMIC_DA_QI_VSRAM_MD_STB_SHIFT, },
+ {PMIC_LDO_VSRAM_MD_DBG1, PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_MASK, PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_SHIFT, },
+ {PMIC_ALDO_ANA_CON4, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
+ {PMIC_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
+ {PMIC_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ {PMIC_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
+ {PMIC_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
+ {PMIC_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ {PMIC_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ {PMIC_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ {PMIC_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ {PMIC_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ {PMIC_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
+ {PMIC_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
+ {PMIC_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {PMIC_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
+ {PMIC_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
+ {PMIC_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
+ {PMIC_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {PMIC_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {PMIC_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
+ {PMIC_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
+};
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic_field_write(PMIC6355_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write register field
+void dcl_pmic_field_write_nolock(PMIC6355_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic_field_read(PMIC6355_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+ else
+ DrvPWRAP_WACS1(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic_byte_write_nolock(reg, val);
+// dcl_pmic_byte_write(reg, val);
+}
+
+kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_200000_V, PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_400000_V, PMU_VOLT_00_450000_V, PMU_VOLT_00_500000_V, PMU_VOLT_00_525000_V,
+ PMU_VOLT_00_550000_V, PMU_VOLT_00_568000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V,
+};
+
+const DCL_UINT32 vmd1_vosel[] =
+{
+ PMU_VOLT_00_400000_V, PMU_VOLT_INVALID, PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V,
+};
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VFE28_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF12_OP_EN_SET, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VFE28_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF12_OP_EN_CLR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_EN, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VFE28_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF12_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_CFG_SET, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VFE28_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VRF12_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_CFG_CLR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_ON_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_LP_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VTCXO24:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18_2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_SET,1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VXO22:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_QI_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SLEEP_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSRAM_MD_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ /*
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ */
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_TOP_CLKSQ_SET, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_SET, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_TOP_CLKSQ_CLR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ ASSERT(0);
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic_byte_write(pmic_addr, value);
+}
+
+void dcl_pmic_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic_hw_version = dcl_pmic_byte_return(PMIC_HWCID);
+ if (pmic_hw_version == 0x0)
+ ASSERT(0);
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6355_modem_only_init();
+ else
+*/
+ dcl_pmic_modem_only_init();
+
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
+ pmic_reg[i] = dcl_pmic_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6355_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6355_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6355_init.c
new file mode 100644
index 0000000..a52bcd2
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6355_init.c
@@ -0,0 +1,130 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6355_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6355
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6355 ECO_E1
+void dcl_pmic_modem_only_init(void)
+{
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6356.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6356.c
new file mode 100644
index 0000000..ae1ef2d
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6356.c
@@ -0,0 +1,2173 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6355_37.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6355
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+
+#if defined(PMIC_6356_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+
+extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
+extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
+extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
+extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic_hw_version;
+kal_uint8 pmic_sw_version;
+kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {MT6356_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {MT6356_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6356_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6356_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6356_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
+ {MT6356_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
+ {MT6356_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
+ {MT6356_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
+ {MT6356_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6356_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6356_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6356_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6356_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6356_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
+ {MT6356_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6356_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
+ {MT6356_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
+ {MT6356_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_VSLEEP_SEL_MASK, PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT, },
+ {MT6356_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
+ {MT6356_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
+ {MT6356_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
+ {MT6356_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
+ {MT6356_BUCK_VS2_CON1, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT, },
+ {MT6356_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
+ {MT6356_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
+ {MT6356_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
+ {MT6356_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
+ {MT6356_BUCK_VS2_ELR0, PMIC_RG_BUCK_VS2_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOSEL_SHIFT, },
+ {MT6356_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
+ {MT6356_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
+ {MT6356_SMPS_ANA_CON1, PMIC_RG_VCORE_SLEEP_VOLTAGE_MASK, PMIC_RG_VCORE_SLEEP_VOLTAGE_SHIFT, },
+ {MT6356_SMPS_ANA_CON1, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
+ {MT6356_VCORE_VPROC_ANA_CON0, PMIC_RG_VCORE_FPWM_MASK, PMIC_RG_VCORE_FPWM_SHIFT, },
+ {MT6356_VCORE_VPROC_ANA_CON0, PMIC_RG_VPROC_FPWM_MASK, PMIC_RG_VPROC_FPWM_SHIFT, },
+ {MT6356_VMODEM_ANA_CON0, PMIC_RG_VMODEM_MODESET_MASK, PMIC_RG_VMODEM_MODESET_SHIFT, },
+ {MT6356_VS2_ANA_CON2, PMIC_RG_VS2_MODESET_MASK, PMIC_RG_VS2_MODESET_SHIFT, },
+ {MT6356_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
+ {MT6356_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
+ {MT6356_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_ON_OP_MASK, PMIC_RG_LDO_VSIM1_ON_OP_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_LP_OP_MASK, PMIC_RG_LDO_VSIM1_LP_OP_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6356_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6356_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VSIM1_CON2, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
+ {MT6356_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6356_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
+ {MT6356_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_ON_OP_MASK, PMIC_RG_LDO_VSIM2_ON_OP_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_LP_OP_MASK, PMIC_RG_LDO_VSIM2_LP_OP_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6356_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6356_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VSIM2_CON2, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
+ {MT6356_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6356_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_EN_MASK, PMIC_RG_LDO_VMIPI_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_LP_MASK, PMIC_RG_LDO_VMIPI_LP_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_SW_OP_EN_MASK, PMIC_RG_LDO_VMIPI_SW_OP_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW0_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW1_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW2_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_EN_SET, PMIC_RG_LDO_VMIPI_OP_EN_SET_MASK, PMIC_RG_LDO_VMIPI_OP_EN_SET_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_EN_CLR, PMIC_RG_LDO_VMIPI_OP_EN_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_EN_CLR_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_ON_OP_MASK, PMIC_RG_LDO_VMIPI_ON_OP_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_LP_OP_MASK, PMIC_RG_LDO_VMIPI_LP_OP_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG_SET, PMIC_RG_LDO_VMIPI_OP_CFG_SET_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_SET_SHIFT, },
+ {MT6356_LDO_VMIPI_OP_CFG_CLR, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_SHIFT, },
+ {MT6356_LDO_VMIPI_CON1, PMIC_DA_VMIPI_MODE_MASK, PMIC_DA_VMIPI_MODE_SHIFT, },
+ {MT6356_LDO_VMIPI_CON1, PMIC_DA_VMIPI_EN_MASK, PMIC_DA_VMIPI_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_CON2, PMIC_RG_LDO_VMIPI_OCFB_EN_MASK, PMIC_RG_LDO_VMIPI_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VMIPI_CON2, PMIC_DA_VMIPI_OCFB_EN_MASK, PMIC_DA_VMIPI_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
+ {MT6356_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
+ {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
+ {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6356_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
+ {MT6356_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6356_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6356_LDO_VFE28_CON1, PMIC_DA_VFE28_MODE_MASK, PMIC_DA_VFE28_MODE_SHIFT, },
+ {MT6356_LDO_VFE28_CON1, PMIC_DA_VFE28_EN_MASK, PMIC_DA_VFE28_EN_SHIFT, },
+ {MT6356_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VFE28_CON2, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
+ {MT6356_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
+ {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
+ {MT6356_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_ON_OP_MASK, PMIC_RG_LDO_VRF18_ON_OP_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_LP_OP_MASK, PMIC_RG_LDO_VRF18_LP_OP_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
+ {MT6356_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
+ {MT6356_LDO_VRF18_CON1, PMIC_DA_VRF18_MODE_MASK, PMIC_DA_VRF18_MODE_SHIFT, },
+ {MT6356_LDO_VRF18_CON1, PMIC_DA_VRF18_EN_MASK, PMIC_DA_VRF18_EN_SHIFT, },
+ {MT6356_LDO_VRF18_CON2, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VRF18_CON2, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
+ {MT6356_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
+ {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6356_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
+ {MT6356_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_ON_OP_MASK, PMIC_RG_LDO_VRF12_ON_OP_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_LP_OP_MASK, PMIC_RG_LDO_VRF12_LP_OP_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6356_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6356_LDO_VRF12_CON1, PMIC_DA_VRF12_MODE_MASK, PMIC_DA_VRF12_MODE_SHIFT, },
+ {MT6356_LDO_VRF12_CON1, PMIC_DA_VRF12_EN_MASK, PMIC_DA_VRF12_EN_SHIFT, },
+ {MT6356_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
+ {MT6356_LDO_VRF12_CON2, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
+ {MT6356_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
+ {MT6356_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
+ {MT6356_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ {MT6356_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
+ {MT6356_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
+ {MT6356_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ {MT6356_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ {MT6356_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ {MT6356_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ {MT6356_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ {MT6356_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
+ {MT6356_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
+ {MT6356_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {MT6356_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
+ {MT6356_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
+ {MT6356_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
+ {MT6356_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6356_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6356_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
+ {MT6356_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
+};
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic_field_write(PMIC6356_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write register field
+void dcl_pmic_field_write_nolock(PMIC6356_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic_field_read(PMIC6356_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic_byte_write_nolock(reg, val);
+// dcl_pmic_byte_write(reg, val);
+}
+
+kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VS2_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_ON_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_LP_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMIPI:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VXO22:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SLEEP_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ /*
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ */
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_TOP_CLKSQ_SET_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_SET_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_TOP_CLKSQ_CLR_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ ASSERT(0);
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic_byte_write(pmic_addr, value);
+}
+
+void dcl_pmic_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic_hw_version = dcl_pmic_byte_return(MT6356_HWCID);
+ if (pmic_hw_version == 0x0)
+ ASSERT(0);
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6355_modem_only_init();
+ else
+*/
+ dcl_pmic_modem_only_init();
+
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
+ pmic_reg[i] = dcl_pmic_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6356_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6356_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6356_init.c
new file mode 100644
index 0000000..8dd1a07
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6356_init.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6355_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6355
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6356 ECO_E1
+void dcl_pmic_modem_only_init(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6357.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6357.c
new file mode 100644
index 0000000..3ab6b30
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6357.c
@@ -0,0 +1,2268 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6355_37.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6355
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+
+#if defined(PMIC_6357_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+
+extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
+extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
+extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
+extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic_hw_version;
+kal_uint8 pmic_sw_version;
+kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {MT6357_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {MT6357_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6357_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6357_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6357_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
+ {MT6357_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
+ {MT6357_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
+ {MT6357_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
+ {MT6357_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6357_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6357_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6357_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6357_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6357_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
+ {MT6357_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6357_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
+ {MT6357_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
+ {MT6357_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_VSLEEP_SEL_MASK, PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT, },
+ {MT6357_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
+ {MT6357_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
+ {MT6357_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
+ {MT6357_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
+ {MT6357_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
+ {MT6357_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
+ {MT6357_SMPS_ANA_CON1, PMIC_RG_VCORE_SLEEP_VOLTAGE_MASK, PMIC_RG_VCORE_SLEEP_VOLTAGE_SHIFT, },
+ {MT6357_SMPS_ANA_CON1, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
+ {MT6357_VMODEM_ANA_CON0, PMIC_RG_VMODEM_FPWM_MASK, PMIC_RG_VMODEM_FPWM_SHIFT, },
+ {MT6357_VCORE_VPROC_ANA_CON0, PMIC_RG_VCORE_FPWM_MASK, PMIC_RG_VCORE_FPWM_SHIFT, },
+ {MT6357_VCORE_VPROC_ANA_CON0, PMIC_RG_VPROC_FPWM_MASK, PMIC_RG_VPROC_FPWM_SHIFT, },
+ {MT6357_LDO_VSRAM_CON1, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT, },
+ {MT6357_VMODEM_ANA_CON0, PMIC_RG_VMODEM_FCOT_MASK, PMIC_RG_VMODEM_FCOT_SHIFT, },
+ {MT6357_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
+ {MT6357_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
+ {MT6357_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
+// {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_ON_OP_MASK, PMIC_RG_LDO_VSIM1_ON_OP_SHIFT, },
+// {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_LP_OP_MASK, PMIC_RG_LDO_VSIM1_LP_OP_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6357_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6357_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VSIM1_CON2, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
+ {MT6357_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6357_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
+ {MT6357_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
+// {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_ON_OP_MASK, PMIC_RG_LDO_VSIM2_ON_OP_SHIFT, },
+// {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_LP_OP_MASK, PMIC_RG_LDO_VSIM2_LP_OP_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6357_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6357_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VSIM2_CON2, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
+ {MT6357_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6357_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
+ {MT6357_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
+ {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
+ {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6357_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
+ {MT6357_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
+// {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
+// {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
+ {MT6357_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6357_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6357_LDO_VFE28_CON1, PMIC_DA_VFE28_MODE_MASK, PMIC_DA_VFE28_MODE_SHIFT, },
+ {MT6357_LDO_VFE28_CON1, PMIC_DA_VFE28_EN_MASK, PMIC_DA_VFE28_EN_SHIFT, },
+ {MT6357_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VFE28_CON2, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
+ {MT6357_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
+ {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
+ {MT6357_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
+ {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
+ {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
+ {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
+// {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_ON_OP_MASK, PMIC_RG_LDO_VRF18_ON_OP_SHIFT, },
+// {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_LP_OP_MASK, PMIC_RG_LDO_VRF18_LP_OP_SHIFT, },
+ {MT6357_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
+ {MT6357_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
+ {MT6357_LDO_VRF18_CON1, PMIC_DA_VRF18_MODE_MASK, PMIC_DA_VRF18_MODE_SHIFT, },
+ {MT6357_LDO_VRF18_CON1, PMIC_DA_VRF18_EN_MASK, PMIC_DA_VRF18_EN_SHIFT, },
+ {MT6357_LDO_VRF18_CON2, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VRF18_CON2, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
+ {MT6357_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
+ {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6357_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
+ {MT6357_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
+// {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_ON_OP_MASK, PMIC_RG_LDO_VRF12_ON_OP_SHIFT, },
+// {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_LP_OP_MASK, PMIC_RG_LDO_VRF12_LP_OP_SHIFT, },
+ {MT6357_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6357_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6357_LDO_VRF12_CON1, PMIC_DA_VRF12_MODE_MASK, PMIC_DA_VRF12_MODE_SHIFT, },
+ {MT6357_LDO_VRF12_CON1, PMIC_DA_VRF12_EN_MASK, PMIC_DA_VRF12_EN_SHIFT, },
+ {MT6357_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
+ {MT6357_LDO_VRF12_CON2, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
+ {MT6357_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
+ {MT6357_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
+ {MT6357_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ {MT6357_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
+ {MT6357_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
+ {MT6357_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ {MT6357_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ {MT6357_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ {MT6357_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ {MT6357_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ {MT6357_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
+ {MT6357_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
+ {MT6357_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {MT6357_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
+ {MT6357_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
+ {MT6357_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
+ {MT6357_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6357_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6357_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
+ {MT6357_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
+ {MT6357_VRF18_ANA_CON0, PMIC_RG_VRF18_VOCAL_MASK, PMIC_RG_VRF18_VOCAL_SHIFT, },
+ {MT6357_VRF12_ANA_CON0, PMIC_RG_VRF12_VOCAL_MASK, PMIC_RG_VRF12_VOCAL_SHIFT, },
+ {MT6357_VRF18_ELR_0, PMIC_RG_VRF18_VOTRIM_MASK, PMIC_RG_VRF18_VOTRIM_SHIFT, },
+ {MT6357_VRF12_ELR_0, PMIC_RG_VRF12_VOTRIM_MASK, PMIC_RG_VRF12_VOTRIM_SHIFT, },
+ {MT6357_BUCK_TOP_OC_CON0, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT, },
+};
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic_field_write(PMIC6357_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write register field
+void dcl_pmic_field_write_nolock(PMIC6357_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic_field_read(PMIC6357_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic_byte_write_nolock(reg, val);
+// dcl_pmic_byte_write(reg, val);
+}
+
+kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_ON_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_LP_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VXO22:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SLEEP_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ /*
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ */
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+//TBD pmic_EM_reg_write(PMIC_TOP_CLKSQ_SET_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_SET_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+//TBD pmic_EM_reg_write(PMIC_TOP_CLKSQ_CLR_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_FPWM *pLdoBuckSetFpwm = &(data->rPMULdoBuckSetFpwm);
+
+ switch(pLdoBuckSetFpwm->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_FPWM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC_FPWM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FPWM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ ASSERT(0);
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case LDO_BUCK_SET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOCAL *pLdoBuckSetVocal = &(data->rPMULdoBuckSetVocal);
+
+ switch(pLdoBuckSetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOCAL *pLdoBuckGetVocal = &(data->rPMULdoBuckGetVocal);
+
+ switch(pLdoBuckGetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOTRIM *pLdoBuckSetVotrim = &(data->rPMULdoBuckSetVotrim);
+
+ switch(pLdoBuckSetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOTRIM *pLdoBuckGetVotrim = &(data->rPMULdoBuckGetVotrim);
+
+ switch(pLdoBuckGetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS *pLdoBuckSetVpaOcSdnStatus = &(data->rPMULdoBuckSetVpaOcSdnStatus);
+
+ switch(pLdoBuckSetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS, pLdoBuckSetVpaOcSdnStatus->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS *pLdoBuckGetVpaOcSdnStatus = &(data->rPMULdoBuckGetVpaOcSdnStatus);
+
+ switch(pLdoBuckGetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ pLdoBuckGetVpaOcSdnStatus->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic_byte_write(pmic_addr, value);
+}
+
+void dcl_pmic_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic_hw_version = dcl_pmic_byte_return(MT6357_HWCID);
+ if (pmic_hw_version == 0x0)
+ ASSERT(0);
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6355_modem_only_init();
+ else
+*/
+ dcl_pmic_modem_only_init();
+
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
+ pmic_reg[i] = dcl_pmic_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6357_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6357_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6357_init.c
new file mode 100644
index 0000000..bcb8eda
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6357_init.c
@@ -0,0 +1,136 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6355_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6355
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6356 ECO_E1
+void dcl_pmic_modem_only_init(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6358.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6358.c
new file mode 100644
index 0000000..77d9439
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6358.c
@@ -0,0 +1,2493 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6358.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6358
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+
+#if defined(PMIC_6358_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+
+extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
+extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
+extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
+extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic_hw_version;
+kal_uint8 pmic_sw_version;
+kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {MT6358_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {MT6358_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {MT6358_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6358_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6358_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6358_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6358_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6358_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6358_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
+ {MT6358_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
+ {MT6358_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
+ {MT6358_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
+ {MT6358_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6358_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6358_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6358_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6358_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6358_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
+ {MT6358_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6358_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
+ {MT6358_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
+ {MT6358_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
+ {MT6358_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
+ {MT6358_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
+ {MT6358_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
+ {MT6358_BUCK_VS2_CON1, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT, },
+ {MT6358_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
+ {MT6358_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
+ {MT6358_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
+ {MT6358_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
+ {MT6358_BUCK_VS2_ELR0, PMIC_RG_BUCK_VS2_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOSEL_SHIFT, },
+ {MT6358_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
+ {MT6358_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
+ {MT6358_SMPS_ANA_CON1, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
+ {MT6358_VCORE_VGPU_ANA_CON0, PMIC_RG_VCORE_FPWM_MASK, PMIC_RG_VCORE_FPWM_SHIFT, },
+ {MT6358_VCORE_VGPU_ANA_CON0, PMIC_RG_VCORE_FCOT_MASK, PMIC_RG_VCORE_FCOT_SHIFT, },
+ {MT6358_VMODEM_ANA_CON0, PMIC_RG_VMODEM_FPWM_MASK, PMIC_RG_VMODEM_FPWM_SHIFT, },
+ {MT6358_VMODEM_ANA_CON0, PMIC_RG_VMODEM_FCOT_MASK, PMIC_RG_VMODEM_FCOT_SHIFT, },
+ {MT6358_VS2_ANA_CON2, PMIC_RG_VS2_FPWM_MASK, PMIC_RG_VS2_FPWM_SHIFT, },
+ {MT6358_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
+ {MT6358_LDO_VSRAM_CON2, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT, },
+ {MT6358_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
+ {MT6358_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6358_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6358_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VSIM1_CON2, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
+ {MT6358_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6358_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
+ {MT6358_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6358_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6358_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VSIM2_CON2, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
+ {MT6358_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6358_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
+ {MT6358_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
+ {MT6358_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
+ {MT6358_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6358_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6358_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6358_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
+ {MT6358_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6358_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6358_LDO_VFE28_CON1, PMIC_DA_VFE28_MODE_MASK, PMIC_DA_VFE28_MODE_SHIFT, },
+ {MT6358_LDO_VFE28_CON1, PMIC_DA_VFE28_EN_MASK, PMIC_DA_VFE28_EN_SHIFT, },
+ {MT6358_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VFE28_CON2, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
+ {MT6358_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
+ {MT6358_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
+ {MT6358_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
+ {MT6358_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
+ {MT6358_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
+ {MT6358_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
+ {MT6358_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
+ {MT6358_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
+ {MT6358_LDO_VRF18_CON1, PMIC_DA_VRF18_MODE_MASK, PMIC_DA_VRF18_MODE_SHIFT, },
+ {MT6358_LDO_VRF18_CON1, PMIC_DA_VRF18_EN_MASK, PMIC_DA_VRF18_EN_SHIFT, },
+ {MT6358_LDO_VRF18_CON2, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VRF18_CON2, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
+ {MT6358_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
+ {MT6358_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6358_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
+ {MT6358_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6358_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6358_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6358_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
+ {MT6358_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6358_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6358_LDO_VRF12_CON1, PMIC_DA_VRF12_MODE_MASK, PMIC_DA_VRF12_MODE_SHIFT, },
+ {MT6358_LDO_VRF12_CON1, PMIC_DA_VRF12_EN_MASK, PMIC_DA_VRF12_EN_SHIFT, },
+ {MT6358_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
+ {MT6358_LDO_VRF12_CON2, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
+ {MT6358_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
+ {MT6358_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
+ {MT6358_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ {MT6358_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
+ {MT6358_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
+ {MT6358_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ {MT6358_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ {MT6358_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ {MT6358_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ {MT6358_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ {MT6358_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
+ {MT6358_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
+ {MT6358_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {MT6358_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
+ {MT6358_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
+ {MT6358_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
+ {MT6358_AUXADC_ADC16, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6358_AUXADC_ADC16, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6358_AUXADC_RQST1, PMIC_AUXADC_RQST_CH7_BY_MD_MASK, PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT, },
+ {MT6358_VRF18_ANA_CON0, PMIC_RG_VRF18_VOCAL_MASK, PMIC_RG_VRF18_VOCAL_SHIFT, },
+ {MT6358_VRF12_ANA_CON0, PMIC_RG_VRF12_VOCAL_MASK, PMIC_RG_VRF12_VOCAL_SHIFT, },
+ {MT6358_VRF18_ELR_0, PMIC_RG_VRF18_VOTRIM_MASK, PMIC_RG_VRF18_VOTRIM_SHIFT, },
+ {MT6358_VRF12_ELR_0, PMIC_RG_VRF12_VOTRIM_MASK, PMIC_RG_VRF12_VOTRIM_SHIFT, },
+ {MT6358_BUCK_TOP_OC_CON0, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT, },
+ {MT6358_BUCK_TOP_ELR0, PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK, PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT, },
+ {MT6358_LDO_VSRAM_CON3, PMIC_RG_LDO_VSRAM_GPU_VOSEL_MASK, PMIC_RG_LDO_VSRAM_GPU_VOSEL_SHIFT, },
+ {MT6358_LDO_VSRAM_GPU_CON2, PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_SHIFT, },
+ {MT6358_LDO_VSRAM_GPU_DBG0, PMIC_DA_VSRAM_GPU_VOSEL_MASK, PMIC_DA_VSRAM_GPU_VOSEL_SHIFT, },
+ {MT6358_LDO_VSRAM_OTHERS_CON2, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_SHIFT, },
+ {MT6358_LDO_VSRAM_OTHERS_DBG0, PMIC_DA_VSRAM_OTHERS_VOSEL_MASK, PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT, },
+};
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic_field_write(PMIC6358_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write register field
+void dcl_pmic_field_write_nolock(PMIC6358_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic_field_read(PMIC6358_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic_byte_write_nolock(reg, val);
+// dcl_pmic_byte_write(reg, val);
+}
+
+kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_01_800000_V, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_GPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_GPU_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VCORE_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_GPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_GPU_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_GPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_GPU_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_GPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_GPU_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FPWM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VS2_FPWM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_COT:
+ {
+ PMU_CTRL_LDO_BUCK_SET_COT *pLdoBuckCtrl = &(data->rPMULdoBuckSetCotset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_FCOT, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCOT, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_COT:
+ {
+ PMU_CTRL_LDO_BUCK_GET_COT *pLdoBuckCtrl = &(data->rPMULdoBuckGetCot);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VCORE_FCOT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VMODEM_FCOT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
+ (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_ON_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_OFF)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_GO_LP_OP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ if(pLdoBuckCtrl->mode == Prefer_NO_LP)
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
+ else
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VXO22:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_GPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_GPU_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_OTHERS_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_SLEEP_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ /*
+ case VPA_SET_EN:
+ {
+ PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
+ dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+ */
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ //PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ ASSERT(0);
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_AUXADC_RQST_CH7_BY_MD_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ ASSERT(0);
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ ASSERT(0);
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_FPWM *pLdoBuckSetFpwm = &(data->rPMULdoBuckSetFpwm);
+
+ switch(pLdoBuckSetFpwm->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_FPWM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FPWM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_FPWM *pLdoBuckCtrl = &(data->rPMULdoBuckGetFpwm);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VCORE_FPWM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VMODEM_FPWM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ ASSERT(0);
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case LDO_BUCK_SET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOCAL *pLdoBuckSetVocal = &(data->rPMULdoBuckSetVocal);
+
+ switch(pLdoBuckSetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOCAL *pLdoBuckGetVocal = &(data->rPMULdoBuckGetVocal);
+
+ switch(pLdoBuckGetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOTRIM *pLdoBuckSetVotrim = &(data->rPMULdoBuckSetVotrim);
+
+ switch(pLdoBuckSetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOTRIM *pLdoBuckGetVotrim = &(data->rPMULdoBuckGetVotrim);
+
+ switch(pLdoBuckGetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS *pLdoBuckSetVpaOcSdnStatus = &(data->rPMULdoBuckSetVpaOcSdnStatus);
+
+ switch(pLdoBuckSetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS, pLdoBuckSetVpaOcSdnStatus->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS *pLdoBuckGetVpaOcSdnStatus = &(data->rPMULdoBuckGetVpaOcSdnStatus);
+
+ switch(pLdoBuckGetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ pLdoBuckGetVpaOcSdnStatus->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN *pLdoBuckSetVpaOcSdnEn = &(data->rPMULdoBuckSetVpaOcSdnEn);
+
+ switch(pLdoBuckSetVpaOcSdnEn->mod)
+ {
+ case VPA_OC_SDN_EN:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN, pLdoBuckSetVpaOcSdnEn->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_EN:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN *pLdoBuckGetVpaOcSdnEn = &(data->rPMULdoBuckGetVpaOcSdnEn);
+
+ switch(pLdoBuckGetVpaOcSdnEn->mod)
+ {
+ case VPA_OC_SDN_EN:
+ {
+ pLdoBuckGetVpaOcSdnEn->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic_byte_write(pmic_addr, value);
+}
+
+void dcl_pmic_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic_hw_version = dcl_pmic_byte_return(MT6358_HWCID);
+ if (pmic_hw_version == 0x0)
+ ASSERT(0);
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6355_modem_only_init();
+ else
+*/
+ dcl_pmic_modem_only_init();
+
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
+ pmic_reg[i] = dcl_pmic_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6358_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6358_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6358_init.c
new file mode 100644
index 0000000..4d0c86d
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6358_init.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2013
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6358_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6358
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6358 ECO_E1
+void dcl_pmic_modem_only_init(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6359.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6359.c
new file mode 100644
index 0000000..c921eaa
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6359.c
@@ -0,0 +1,3105 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6359.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6359
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+#include "event_info_utility.h" // for MODEM_WARNING_MESSAGE
+
+#if defined(PMIC_6359_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+
+extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
+extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
+extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
+extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+/* All buck/ldo use the same sw/hw OP_EN control, so use vcore as reference
+ * bit shift
+ */
+typedef enum
+{
+ RG_BUCK_LDO_HW0_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW1_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW2_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW3_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW4_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW5_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW6_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW7_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW8_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW9_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW10_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW11_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW12_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW13_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW14_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_EN_SHIFT,
+ RG_BUCK_LDO_SW_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_SW_OP_EN_SHIFT,
+}PMIC_BUCK_LDO_OP_EN_SHIFT_ENUM;
+
+typedef enum
+{
+ RG_BUCK_LDO_HW0_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW1_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW2_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW3_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW4_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW5_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW6_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW7_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW8_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW9_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW10_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW11_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW12_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW13_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW14_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_CFG_SHIFT,
+}PMIC_BUCK_LDO_OP_CFG_SHIFT_ENUM;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic_hw_version;
+kal_uint8 pmic_sw_version;
+kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {MT6359_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {MT6359_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_TOP_ELR2, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
+ {MT6359_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
+ {MT6359_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6359_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
+ {MT6359_BUCK_VS2_CON1, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
+ {MT6359_BUCK_VS2_ELR0, PMIC_RG_BUCK_VS2_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
+ {MT6359_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
+ {MT6359_VMODEM_ANA_CON3, PMIC_RG_VMODEM_FCCM_MASK, PMIC_RG_VMODEM_FCCM_SHIFT, },
+ {MT6359_VS2_ANA_CON2, PMIC_RG_VS2_FPWM_MASK, PMIC_RG_VS2_FPWM_SHIFT, },
+ {MT6359_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
+ {MT6359_LDO_VSRAM_OTHERS_ELR, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT, },
+ {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_MON, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
+ {MT6359_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_MON, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
+ {MT6359_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VFE28_MON, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF18_MON, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF12_MON, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
+ {MT6359_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
+ {MT6359_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ {MT6359_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_RG_XO_CBANK_POL_MASK, PMIC_RG_XO_CBANK_POL_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_RG_XO_PCTAT_CCOMP_MASK, PMIC_RG_XO_PCTAT_CCOMP_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_RG_XO_VTEST_SEL_MUX_MASK, PMIC_RG_XO_VTEST_SEL_MUX_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_PCTAT_EN_MAN_MASK, PMIC_XO_PCTAT_EN_MAN_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_PCTAT_EN_M_MASK, PMIC_XO_PCTAT_EN_M_SHIFT, },
+ {MT6359_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ {MT6359_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ {MT6359_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ {MT6359_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ {MT6359_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ {MT6359_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_SYNC_M_MASK, PMIC_XO_CORE_TURBO_EN_SYNC_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_PCTAT_IS_EN_MASK, PMIC_RG_XO_PCTAT_IS_EN_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_CMP_GSEL_MASK, PMIC_RG_XO_CMP_GSEL_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_VBSEL_SYNC_M_MASK, PMIC_XO_CORE_VBSEL_SYNC_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_FPMBIAS_EN_M_MASK, PMIC_XO_CORE_FPMBIAS_EN_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_LPMCF_SYNC_FPM_MASK, PMIC_XO_CORE_LPMCF_SYNC_FPM_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_LPMCF_SYNC_LPM_MASK, PMIC_XO_CORE_LPMCF_SYNC_LPM_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_CORE_LPM_ISEL_MAN_MASK, PMIC_RG_XO_CORE_LPM_ISEL_MAN_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_CORE_LPM_IDAC_MASK, PMIC_RG_XO_CORE_LPM_IDAC_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_32KDIV_SWRST_MASK, PMIC_XO_32KDIV_SWRST_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_32KDIV_RATIO_MAN_MASK, PMIC_XO_32KDIV_RATIO_MAN_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_32KDIV_TEST_EN_MASK, PMIC_XO_32KDIV_TEST_EN_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_CTL_SYNC_BUF_MAN_MASK, PMIC_XO_CTL_SYNC_BUF_MAN_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_CTL_SYNC_BUF_EN_M_MASK, PMIC_XO_CTL_SYNC_BUF_EN_M_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_RG_XO_HV_PBUF_VSET_MASK, PMIC_RG_XO_HV_PBUF_VSET_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF6_MODE_MASK, PMIC_XO_EXTBUF6_MODE_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF6_EN_M_MASK, PMIC_XO_EXTBUF6_EN_M_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF7_MODE_MASK, PMIC_XO_EXTBUF7_MODE_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF7_EN_M_MASK, PMIC_XO_EXTBUF7_EN_M_SHIFT, },
+ {MT6359_DCXO_CW16, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
+ {MT6359_DCXO_CW16, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
+ {MT6359_DCXO_CW17, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
+ {MT6359_AUXADC_ADC16, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6359_AUXADC_ADC16, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6359_AUXADC_RQST1, PMIC_AUXADC_RQST_CH7_BY_MD_MASK, PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT, },
+ {MT6359_VRF18_ANA_CON0, PMIC_RG_VRF18_VOCAL_MASK, PMIC_RG_VRF18_VOCAL_SHIFT, },
+ {MT6359_VRF12_ANA_CON0, PMIC_RG_VRF12_VOCAL_MASK, PMIC_RG_VRF12_VOCAL_SHIFT, },
+ {MT6359_VRF18_ELR_0, PMIC_RG_VRF18_VOTRIM_MASK, PMIC_RG_VRF18_VOTRIM_SHIFT, },
+ {MT6359_VRF18_ELR_2, PMIC_RG_VRF12_VOTRIM_MASK, PMIC_RG_VRF12_VOTRIM_SHIFT, },
+ {MT6359_BUCK_TOP_OC_CON0, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT, },
+ {MT6359_BUCK_TOP_ELR0, PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK, PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT, },
+ {MT6359_LDO_VSRAM_MD_ELR, PMIC_RG_LDO_VSRAM_MD_VOSEL_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_MD_VOSEL0, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_MD_VOSEL1, PMIC_DA_VSRAM_MD_VOSEL_MASK, PMIC_DA_VSRAM_MD_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_OTHERS_VOSEL0, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_OTHERS_VOSEL1, PMIC_DA_VSRAM_OTHERS_VOSEL_MASK, PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_OP_MODE_MASK, PMIC_RG_LDO_VRF18_OP_MODE_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_OP_MODE_MASK, PMIC_RG_LDO_VRF12_OP_MODE_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_OP_MODE_MASK, PMIC_RG_LDO_VFE28_OP_MODE_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VGPU11_CON0, PMIC_RG_BUCK_VGPU11_EN_MASK, PMIC_RG_BUCK_VGPU11_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_CON0, PMIC_RG_BUCK_VGPU11_LP_MASK, PMIC_RG_BUCK_VGPU11_LP_SHIFT, },
+ {MT6359_BUCK_VGPU11_CON1, PMIC_RG_BUCK_VGPU11_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VGPU11_ELR0, PMIC_RG_BUCK_VGPU11_VOSEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_SW_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW0_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW1_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW2_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN_SET, PMIC_RG_BUCK_VGPU11_OP_EN_SET_MASK, PMIC_RG_BUCK_VGPU11_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN_CLR, PMIC_RG_BUCK_VGPU11_OP_EN_CLR_MASK, PMIC_RG_BUCK_VGPU11_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG_SET, PMIC_RG_BUCK_VGPU11_OP_CFG_SET_MASK, PMIC_RG_BUCK_VGPU11_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG_CLR, PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG0, PMIC_DA_VGPU11_VOSEL_MASK, PMIC_DA_VGPU11_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG0, PMIC_DA_VGPU11_VOSEL_GRAY_MASK, PMIC_DA_VGPU11_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG1, PMIC_DA_VGPU11_EN_MASK, PMIC_DA_VGPU11_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG1, PMIC_DA_VGPU11_STB_MASK, PMIC_DA_VGPU11_STB_SHIFT, },
+ {MT6359_VGPUVCORE_ANA_CON2, PMIC_RG_VGPU11_FCCM_MASK, PMIC_RG_VGPU11_FCCM_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VGPU12_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VGPU12_CON0, PMIC_RG_BUCK_VGPU12_EN_MASK, PMIC_RG_BUCK_VGPU12_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_CON0, PMIC_RG_BUCK_VGPU12_LP_MASK, PMIC_RG_BUCK_VGPU12_LP_SHIFT, },
+ {MT6359_BUCK_VGPU12_CON1, PMIC_RG_BUCK_VGPU12_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VGPU12_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VGPU12_ELR0, PMIC_RG_BUCK_VGPU12_VOSEL_MASK, PMIC_RG_BUCK_VGPU12_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_SW_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW0_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW1_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW2_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN_SET, PMIC_RG_BUCK_VGPU12_OP_EN_SET_MASK, PMIC_RG_BUCK_VGPU12_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN_CLR, PMIC_RG_BUCK_VGPU12_OP_EN_CLR_MASK, PMIC_RG_BUCK_VGPU12_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG_SET, PMIC_RG_BUCK_VGPU12_OP_CFG_SET_MASK, PMIC_RG_BUCK_VGPU12_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG_CLR, PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG0, PMIC_DA_VGPU12_VOSEL_MASK, PMIC_DA_VGPU12_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG0, PMIC_DA_VGPU12_VOSEL_GRAY_MASK, PMIC_DA_VGPU12_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG1, PMIC_DA_VGPU12_EN_MASK, PMIC_DA_VGPU12_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG1, PMIC_DA_VGPU12_STB_MASK, PMIC_DA_VGPU12_STB_SHIFT, },
+ {MT6359_VGPUVCORE_ANA_CON8, PMIC_RG_VGPU12_FCCM_MASK, PMIC_RG_VGPU12_FCCM_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC1_ELR, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_MASK, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC1_VOSEL0, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC1_VOSEL1, PMIC_DA_VSRAM_PROC1_VOSEL_MASK, PMIC_DA_VSRAM_PROC1_VOSEL_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPROC1_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VPROC1_CON0, PMIC_RG_BUCK_VPROC1_EN_MASK, PMIC_RG_BUCK_VPROC1_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_CON0, PMIC_RG_BUCK_VPROC1_LP_MASK, PMIC_RG_BUCK_VPROC1_LP_SHIFT, },
+ {MT6359_BUCK_VPROC1_CON1, PMIC_RG_BUCK_VPROC1_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPROC1_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VPROC1_ELR0, PMIC_RG_BUCK_VPROC1_VOSEL_MASK, PMIC_RG_BUCK_VPROC1_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_SW_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN_SET, PMIC_RG_BUCK_VPROC1_OP_EN_SET_MASK, PMIC_RG_BUCK_VPROC1_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN_CLR, PMIC_RG_BUCK_VPROC1_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPROC1_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG_SET, PMIC_RG_BUCK_VPROC1_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPROC1_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG_CLR, PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG0, PMIC_DA_VPROC1_VOSEL_MASK, PMIC_DA_VPROC1_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG0, PMIC_DA_VPROC1_VOSEL_GRAY_MASK, PMIC_DA_VPROC1_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG1, PMIC_DA_VPROC1_EN_MASK, PMIC_DA_VPROC1_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG1, PMIC_DA_VPROC1_STB_MASK, PMIC_DA_VPROC1_STB_SHIFT, },
+ {MT6359_VPROC1_ANA_CON3, PMIC_RG_VPROC1_FCCM_MASK, PMIC_RG_VPROC1_FCCM_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC2_ELR, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_MASK, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC2_VOSEL0, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC2_VOSEL1, PMIC_DA_VSRAM_PROC2_VOSEL_MASK, PMIC_DA_VSRAM_PROC2_VOSEL_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPROC2_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VPROC2_CON0, PMIC_RG_BUCK_VPROC2_EN_MASK, PMIC_RG_BUCK_VPROC2_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_CON0, PMIC_RG_BUCK_VPROC2_LP_MASK, PMIC_RG_BUCK_VPROC2_LP_SHIFT, },
+ {MT6359_BUCK_VPROC2_CON1, PMIC_RG_BUCK_VPROC2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPROC2_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VPROC2_ELR0, PMIC_RG_BUCK_VPROC2_VOSEL_MASK, PMIC_RG_BUCK_VPROC2_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_SW_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN_SET, PMIC_RG_BUCK_VPROC2_OP_EN_SET_MASK, PMIC_RG_BUCK_VPROC2_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN_CLR, PMIC_RG_BUCK_VPROC2_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPROC2_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG_SET, PMIC_RG_BUCK_VPROC2_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPROC2_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG_CLR, PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG0, PMIC_DA_VPROC2_VOSEL_MASK, PMIC_DA_VPROC2_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG0, PMIC_DA_VPROC2_VOSEL_GRAY_MASK, PMIC_DA_VPROC2_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG1, PMIC_DA_VPROC2_EN_MASK, PMIC_DA_VPROC2_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG1, PMIC_DA_VPROC2_STB_MASK, PMIC_DA_VPROC2_STB_SHIFT, },
+ {MT6359_VPROC2_ANA_CON3, PMIC_RG_VPROC2_FCCM_MASK, PMIC_RG_VPROC2_FCCM_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPU_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VPU_CON0, PMIC_RG_BUCK_VPU_EN_MASK, PMIC_RG_BUCK_VPU_EN_SHIFT, },
+ {MT6359_BUCK_VPU_CON0, PMIC_RG_BUCK_VPU_LP_MASK, PMIC_RG_BUCK_VPU_LP_SHIFT, },
+ {MT6359_BUCK_VPU_CON1, PMIC_RG_BUCK_VPU_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPU_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VPU_ELR0, PMIC_RG_BUCK_VPU_VOSEL_MASK, PMIC_RG_BUCK_VPU_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_SW_OP_EN_MASK, PMIC_RG_BUCK_VPU_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN_SET, PMIC_RG_BUCK_VPU_OP_EN_SET_MASK, PMIC_RG_BUCK_VPU_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN_CLR, PMIC_RG_BUCK_VPU_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPU_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG_SET, PMIC_RG_BUCK_VPU_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPU_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG_CLR, PMIC_RG_BUCK_VPU_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPU_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VPU_DBG0, PMIC_DA_VPU_VOSEL_MASK, PMIC_DA_VPU_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPU_DBG0, PMIC_DA_VPU_VOSEL_GRAY_MASK, PMIC_DA_VPU_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VPU_DBG1, PMIC_DA_VPU_EN_MASK, PMIC_DA_VPU_EN_SHIFT, },
+ {MT6359_BUCK_VPU_DBG1, PMIC_DA_VPU_STB_MASK, PMIC_DA_VPU_STB_SHIFT, },
+ {MT6359_VPU_ANA_CON3, PMIC_RG_VPU_FCCM_MASK, PMIC_RG_VPU_FCCM_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW0_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW1_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW2_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE_SET, PMIC_RG_BUCK_VPU_OP_MODE_SET_MASK, PMIC_RG_BUCK_VPU_OP_MODE_SET_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE_CLR, PMIC_RG_BUCK_VPU_OP_MODE_CLR_MASK, PMIC_RG_BUCK_VPU_OP_MODE_CLR_SHIFT, },
+};
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic_field_write(PMIC6359_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write register field
+void dcl_pmic_field_write_nolock(PMIC6359_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic_field_read(PMIC6359_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+// else
+// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic_byte_write_nolock(reg, val);
+// dcl_pmic_byte_write(reg, val);
+}
+
+kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_01_800000_V, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VGPU11), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VGPU12), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_PROC1), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_PROC2), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ /* Enable BUCK_VPA_CK_SW_MODE before Enable VPA */
+ if (pLdoBuckCtrl->enable == 0x1)
+ dcl_pmic_byte_write_nolock(MT6359_BUCK_VPA_DBG1, 0x3000);
+
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+
+ /* Disable BUCK_VPA_CK_SW_MODE after Disable VPA */
+ if (pLdoBuckCtrl->enable == 0x0)
+ dcl_pmic_byte_write_nolock(MT6359_BUCK_VPA_DBG1, 0x0);
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ /* Clear INT_STATUS_VSIM1_OC before Enable VSIM1 */
+ if (pLdoBuckCtrl->enable == 0x1)
+ dcl_pmic_byte_write_nolock(MT6359_LDO_TOP_INT_STATUS1, 0x10);
+
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ /* Clear INT_STATUS_VSIM2_OC before Enable VSIM2 */
+ if (pLdoBuckCtrl->enable == 0x1)
+ dcl_pmic_byte_write_nolock(MT6359_LDO_TOP_INT_STATUS1, 0x20);
+
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPU_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VCORE_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPU_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VS2_FPWM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU11_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU12_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC1_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC2_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPU_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << RG_BUCK_LDO_SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << RG_BUCK_LDO_HW0_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_en << RG_BUCK_LDO_HW1_OP_EN_SHIFT) | (pLdoBuckCtrl->hw2_op_en << RG_BUCK_LDO_HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << RG_BUCK_LDO_SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << RG_BUCK_LDO_HW0_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_en << RG_BUCK_LDO_HW1_OP_EN_SHIFT) | (pLdoBuckCtrl->hw2_op_en << RG_BUCK_LDO_HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << RG_BUCK_LDO_HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << RG_BUCK_LDO_HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << RG_BUCK_LDO_HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << RG_BUCK_LDO_HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << RG_BUCK_LDO_HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << RG_BUCK_LDO_HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VXO22:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_OTHERS_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VGPU11_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VGPU12_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_PROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_PROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPU_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ //PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "ADC_SET_RQST error");
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_AUXADC_RQST_CH7_BY_MD_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "ADC_GET_RDY_MD error");
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "ADC_GET_OUT_MD error");
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_FPWM *pLdoBuckSetFpwm = &(data->rPMULdoBuckSetFpwm);
+
+ switch(pLdoBuckSetFpwm->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU11_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU12_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC1_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC2_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPU_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_FPWM *pLdoBuckCtrl = &(data->rPMULdoBuckGetFpwm);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VMODEM_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VGPU11_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VGPU12_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPROC1_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPROC2_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPU_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "MISC_SET_REGISTER_VALUE error");
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case LDO_BUCK_SET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOCAL *pLdoBuckSetVocal = &(data->rPMULdoBuckSetVocal);
+
+ switch(pLdoBuckSetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOCAL *pLdoBuckGetVocal = &(data->rPMULdoBuckGetVocal);
+
+ switch(pLdoBuckGetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOTRIM *pLdoBuckSetVotrim = &(data->rPMULdoBuckSetVotrim);
+
+ switch(pLdoBuckSetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOTRIM *pLdoBuckGetVotrim = &(data->rPMULdoBuckGetVotrim);
+
+ switch(pLdoBuckGetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS *pLdoBuckSetVpaOcSdnStatus = &(data->rPMULdoBuckSetVpaOcSdnStatus);
+
+ switch(pLdoBuckSetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS, pLdoBuckSetVpaOcSdnStatus->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS *pLdoBuckGetVpaOcSdnStatus = &(data->rPMULdoBuckGetVpaOcSdnStatus);
+
+ switch(pLdoBuckGetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ pLdoBuckGetVpaOcSdnStatus->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN *pLdoBuckSetVpaOcSdnEn = &(data->rPMULdoBuckSetVpaOcSdnEn);
+
+ switch(pLdoBuckSetVpaOcSdnEn->mod)
+ {
+ case VPA_OC_SDN_EN:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN, pLdoBuckSetVpaOcSdnEn->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_EN:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN *pLdoBuckGetVpaOcSdnEn = &(data->rPMULdoBuckGetVpaOcSdnEn);
+
+ switch(pLdoBuckGetVpaOcSdnEn->mod)
+ {
+ case VPA_OC_SDN_EN:
+ {
+ pLdoBuckGetVpaOcSdnEn->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_MODE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_MODE *pLdoBuckSetOpMode = &(data->rPMULdoBuckSetOpMode);
+
+ switch(pLdoBuckSetOpMode->mod)
+ {
+ case VRF18:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_MODE, pLdoBuckSetOpMode->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_MODE, pLdoBuckSetOpMode->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_MODE, pLdoBuckSetOpMode->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_BUCK_HW_OP_MODE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_BUCK_HW_OP_MODE *pLdoBuckSetBuckHwOpMode = &(data->rPMULdoBuckSetBuckHwOpMode);
+
+ kal_uint16 value =((pLdoBuckSetBuckHwOpMode->hw0_op_mode << PMIC_RG_BUCK_VPU_HW0_OP_MODE_SHIFT) |
+ (pLdoBuckSetBuckHwOpMode->hw1_op_mode << PMIC_RG_BUCK_VPU_HW1_OP_MODE_SHIFT) |
+ (pLdoBuckSetBuckHwOpMode->hw2_op_mode << PMIC_RG_BUCK_VPU_HW2_OP_MODE_SHIFT));
+
+ switch(pLdoBuckSetBuckHwOpMode->mod)
+ {
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_MODE_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_BUCK_HW_OP_MODE:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_BUCK_HW_OP_MODE *pLdoBuckClrBuckHwOpMode = &(data->rPMULdoBuckClrBuckHwOpMode);
+
+ kal_uint16 value =((pLdoBuckClrBuckHwOpMode->hw0_op_mode << PMIC_RG_BUCK_VPU_HW0_OP_MODE_SHIFT) |
+ (pLdoBuckClrBuckHwOpMode->hw1_op_mode << PMIC_RG_BUCK_VPU_HW1_OP_MODE_SHIFT) |
+ (pLdoBuckClrBuckHwOpMode->hw2_op_mode << PMIC_RG_BUCK_VPU_HW2_OP_MODE_SHIFT));
+
+ switch(pLdoBuckClrBuckHwOpMode->mod)
+ {
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_MODE_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOTER_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOTER_VOLTAGE *pLdoBuckSetVoterVoltage = &(data->rPMULdoBuckSetVoterVoltage);
+
+ switch(pLdoBuckSetVoterVoltage->mod)
+ {
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckSetVoterVoltage->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckSetVoterVoltage->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case MISC_GET_CID:
+ {
+ PMU_CTRL_MISC_GET_CID *pMiscGetCtrl = &(data->rPMUMiscGetCid);
+ pMiscGetCtrl->cid_value = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_HWCID);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic_byte_write(pmic_addr, value);
+}
+
+void dcl_pmic_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic_hw_version = dcl_pmic_byte_return(MT6359_HWCID);
+ if (pmic_hw_version == 0x0) {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "Get HWCID error");
+ }
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6355_modem_only_init();
+ else
+*/
+ dcl_pmic_modem_only_init();
+
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
+ pmic_reg[i] = dcl_pmic_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6359_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6359_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6359_init.c
new file mode 100644
index 0000000..b8e0722
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6359_init.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2018
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6359_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6359
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6359 ECO_E1
+void dcl_pmic_modem_only_init(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6359p.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6359p.c
new file mode 100644
index 0000000..08a50fe
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6359p.c
@@ -0,0 +1,3239 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2019
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6359p.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6359P
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ *
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+ *
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+ *
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+ * removed!
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+ * removed!
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+ * removed!
+ *
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+ * removed!
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+ *
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
+ *
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+ *
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if defined(FPGA_CTP)
+#include <common.h>
+#endif
+
+#include "reg_base.h"
+#include "drv_comm.h"
+#include "init.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "pmic_wrap.h"
+#include "kal_public_api.h"
+#include "us_timer.h"
+#include "event_info_utility.h" // for MODEM_WARNING_MESSAGE
+
+#if defined(PMIC_6359P_REG_API)
+
+// Start PMIC_UNIT_TEST
+//#define PMIC_UNIT_TEST
+// ARM Section RW/RO/ZI Use Internal SRAM
+#define PMIC_INTERNAL_SRAM
+
+#if !defined(__FUE__)
+#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
+#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#else /*defined(__FUE__)*/
+#define SAVEANDSETIRQMASK() 0
+#define RESTOREIRQMASK(mask) {}
+#endif /*defined(__FUE__)*/
+
+#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
+
+//////////////////////////////////////////////////
+// Exported APIs //
+//////////////////////////////////////////////////
+
+extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
+extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
+extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
+extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
+extern DCL_BOOL dcl_pmic_init_done_query(void);
+typedef enum
+{
+ AUXADC_READ_INIT = 0,
+ AUXADC_READ_REQUEST = 1,
+ AUXADC_READ_READY = 2,
+ AUXADC_READ_BUSY = 3,
+ AUXADC_READ_DATA = 4
+}AUXADC_FSM;
+
+typedef struct
+{
+ kal_uint32 command_flag;
+ kal_uint32 reg_before_write;
+ kal_uint32 write_value;
+ kal_uint32 address_offset;
+ kal_uint32 reg_mask;
+ kal_uint32 reg_shift;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_data;
+}PMIC_REG_LOG;
+
+/* All buck/ldo use the same sw/hw OP_EN control, so use vcore as reference
+ * bit shift
+ */
+typedef enum
+{
+ RG_BUCK_LDO_HW0_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW1_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW2_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW3_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW4_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW5_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW6_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW7_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW8_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW9_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW10_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW11_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW12_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW13_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_EN_SHIFT,
+ RG_BUCK_LDO_HW14_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_EN_SHIFT,
+ RG_BUCK_LDO_SW_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_SW_OP_EN_SHIFT,
+}PMIC_BUCK_LDO_OP_EN_SHIFT_ENUM;
+
+typedef enum
+{
+ RG_BUCK_LDO_HW0_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW1_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW2_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW3_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW4_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW5_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW6_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW7_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW8_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW9_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW10_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW11_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW12_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW13_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_CFG_SHIFT,
+ RG_BUCK_LDO_HW14_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_CFG_SHIFT,
+}PMIC_BUCK_LDO_OP_CFG_SHIFT_ENUM;
+
+typedef enum
+{
+ RG_BUCK_LDO_HW0_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW1_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW2_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW3_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW4_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW5_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW6_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW7_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW8_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW9_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW10_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW11_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW12_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW13_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT,
+ RG_BUCK_LDO_HW14_OP_MODE_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT,
+}PMIC_BUCK_LDO_OP_MODE_SHIFT_ENUM;
+
+AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
+PMIC_REG_LOG pmic_reg_log;
+
+#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
+__attribute__ ((zero_init))
+#endif /* __MTK_TARGET__ */
+
+kal_uint8 pmic_hw_version;
+kal_uint8 pmic_sw_version;
+kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
+DCL_BOOL pmic_init_done = DCL_FALSE;
+
+kal_spinlockid dcl_pmic_access_spinlock;
+extern kal_spinlockid dcl_pmic_control_spinlock;
+
+const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
+{
+ {MT6359_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
+ {MT6359_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
+ {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_TOP_ELR2, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
+ {MT6359_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
+ {MT6359_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
+ {MT6359_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
+ {MT6359_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
+ {MT6359_BUCK_VS2_CON1, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
+ {MT6359_BUCK_VS2_ELR0, PMIC_RG_BUCK_VS2_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
+ {MT6359_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
+ {MT6359_VMODEM_ANA_CON3, PMIC_RG_VMODEM_FCCM_MASK, PMIC_RG_VMODEM_FCCM_SHIFT, },
+ {MT6359_VS2_ANA_CON2, PMIC_RG_VS2_FPWM_MASK, PMIC_RG_VS2_FPWM_SHIFT, },
+ {MT6359_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
+ {MT6359_LDO_VSRAM_OTHERS_ELR, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT, },
+ {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VSIM1_MON, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
+ {MT6359_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
+ {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VSIM2_MON, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
+ {MT6359_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VFE28_MON, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF18_MON, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
+ {MT6359_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
+ {MT6359_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
+ {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
+ {MT6359_LDO_VRF12_MON, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
+ {MT6359_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
+ {MT6359_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
+ {MT6359_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
+ {MT6359_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_RG_XO_CBANK_POL_MASK, PMIC_RG_XO_CBANK_POL_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_RG_XO_PCTAT_CCOMP_MASK, PMIC_RG_XO_PCTAT_CCOMP_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_RG_XO_VTEST_SEL_MUX_MASK, PMIC_RG_XO_VTEST_SEL_MUX_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_PCTAT_EN_MAN_MASK, PMIC_XO_PCTAT_EN_MAN_SHIFT, },
+ {MT6359_DCXO_CW02, PMIC_XO_PCTAT_EN_M_MASK, PMIC_XO_PCTAT_EN_M_SHIFT, },
+ {MT6359_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
+ {MT6359_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
+ {MT6359_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
+ {MT6359_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
+ {MT6359_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
+ {MT6359_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_SYNC_M_MASK, PMIC_XO_CORE_TURBO_EN_SYNC_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_PCTAT_IS_EN_MASK, PMIC_RG_XO_PCTAT_IS_EN_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_CMP_GSEL_MASK, PMIC_RG_XO_CMP_GSEL_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_VBSEL_SYNC_M_MASK, PMIC_XO_CORE_VBSEL_SYNC_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_FPMBIAS_EN_M_MASK, PMIC_XO_CORE_FPMBIAS_EN_M_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_LPMCF_SYNC_FPM_MASK, PMIC_XO_CORE_LPMCF_SYNC_FPM_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_XO_CORE_LPMCF_SYNC_LPM_MASK, PMIC_XO_CORE_LPMCF_SYNC_LPM_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_CORE_LPM_ISEL_MAN_MASK, PMIC_RG_XO_CORE_LPM_ISEL_MAN_SHIFT, },
+ {MT6359_DCXO_CW07, PMIC_RG_XO_CORE_LPM_IDAC_MASK, PMIC_RG_XO_CORE_LPM_IDAC_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_32KDIV_SWRST_MASK, PMIC_XO_32KDIV_SWRST_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_32KDIV_RATIO_MAN_MASK, PMIC_XO_32KDIV_RATIO_MAN_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_32KDIV_TEST_EN_MASK, PMIC_XO_32KDIV_TEST_EN_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_CTL_SYNC_BUF_MAN_MASK, PMIC_XO_CTL_SYNC_BUF_MAN_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_CTL_SYNC_BUF_EN_M_MASK, PMIC_XO_CTL_SYNC_BUF_EN_M_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_RG_XO_HV_PBUF_VSET_MASK, PMIC_RG_XO_HV_PBUF_VSET_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF6_MODE_MASK, PMIC_XO_EXTBUF6_MODE_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF6_EN_M_MASK, PMIC_XO_EXTBUF6_EN_M_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF7_MODE_MASK, PMIC_XO_EXTBUF7_MODE_SHIFT, },
+ {MT6359_DCXO_CW09, PMIC_XO_EXTBUF7_EN_M_MASK, PMIC_XO_EXTBUF7_EN_M_SHIFT, },
+ {MT6359_DCXO_CW16, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
+ {MT6359_DCXO_CW16, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
+ {MT6359_DCXO_CW17, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
+ {MT6359_AUXADC_ADC16, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
+ {MT6359_AUXADC_ADC16, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
+ {MT6359_AUXADC_RQST1, PMIC_AUXADC_RQST_CH7_BY_MD_MASK, PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT, },
+ {MT6359_VRF18_ANA_CON0, PMIC_RG_VRF18_VOCAL_MASK, PMIC_RG_VRF18_VOCAL_SHIFT, },
+ {MT6359_VRF12_ANA_CON0, PMIC_RG_VRF12_VOCAL_MASK, PMIC_RG_VRF12_VOCAL_SHIFT, },
+ {MT6359_VRF18_ELR_0, PMIC_RG_VRF18_VOTRIM_MASK, PMIC_RG_VRF18_VOTRIM_SHIFT, },
+ {MT6359_VRF18_ELR_2, PMIC_RG_VRF12_VOTRIM_MASK, PMIC_RG_VRF12_VOTRIM_SHIFT, },
+ {MT6359_BUCK_TOP_OC_CON0, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT, },
+ {MT6359_BUCK_TOP_ELR0, PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK, PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT, },
+ {MT6359_LDO_VSRAM_MD_ELR, PMIC_RG_LDO_VSRAM_MD_VOSEL_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_MD_VOSEL0, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_MD_VOSEL1, PMIC_DA_VSRAM_MD_VOSEL_MASK, PMIC_DA_VSRAM_MD_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_OTHERS_VOSEL0, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_OTHERS_VOSEL1, PMIC_DA_VSRAM_OTHERS_VOSEL_MASK, PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT, },
+ {MT6359_LDO_VRF18_CON1, PMIC_RG_LDO_VRF18_OP_MODE_MASK, PMIC_RG_LDO_VRF18_OP_MODE_SHIFT, },
+ {MT6359_LDO_VRF12_CON1, PMIC_RG_LDO_VRF12_OP_MODE_MASK, PMIC_RG_LDO_VRF12_OP_MODE_SHIFT, },
+ {MT6359_LDO_VFE28_CON1, PMIC_RG_LDO_VFE28_OP_MODE_MASK, PMIC_RG_LDO_VFE28_OP_MODE_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VGPU11_CON0, PMIC_RG_BUCK_VGPU11_EN_MASK, PMIC_RG_BUCK_VGPU11_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_CON0, PMIC_RG_BUCK_VGPU11_LP_MASK, PMIC_RG_BUCK_VGPU11_LP_SHIFT, },
+ {MT6359_BUCK_VGPU11_CON1, PMIC_RG_BUCK_VGPU11_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VGPU11_ELR0, PMIC_RG_BUCK_VGPU11_VOSEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_SW_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW0_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW1_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW2_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN_SET, PMIC_RG_BUCK_VGPU11_OP_EN_SET_MASK, PMIC_RG_BUCK_VGPU11_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_EN_CLR, PMIC_RG_BUCK_VGPU11_OP_EN_CLR_MASK, PMIC_RG_BUCK_VGPU11_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG_SET, PMIC_RG_BUCK_VGPU11_OP_CFG_SET_MASK, PMIC_RG_BUCK_VGPU11_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VGPU11_OP_CFG_CLR, PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG0, PMIC_DA_VGPU11_VOSEL_MASK, PMIC_DA_VGPU11_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG0, PMIC_DA_VGPU11_VOSEL_GRAY_MASK, PMIC_DA_VGPU11_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG1, PMIC_DA_VGPU11_EN_MASK, PMIC_DA_VGPU11_EN_SHIFT, },
+ {MT6359_BUCK_VGPU11_DBG1, PMIC_DA_VGPU11_STB_MASK, PMIC_DA_VGPU11_STB_SHIFT, },
+ {MT6359_VGPUVCORE_ANA_CON2, PMIC_RG_VGPU11_FCCM_MASK, PMIC_RG_VGPU11_FCCM_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VGPU12_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VGPU12_CON0, PMIC_RG_BUCK_VGPU12_EN_MASK, PMIC_RG_BUCK_VGPU12_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_CON0, PMIC_RG_BUCK_VGPU12_LP_MASK, PMIC_RG_BUCK_VGPU12_LP_SHIFT, },
+ {MT6359_BUCK_VGPU12_CON1, PMIC_RG_BUCK_VGPU12_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VGPU12_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VGPU12_ELR0, PMIC_RG_BUCK_VGPU12_VOSEL_MASK, PMIC_RG_BUCK_VGPU12_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_SW_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW0_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW1_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW2_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN_SET, PMIC_RG_BUCK_VGPU12_OP_EN_SET_MASK, PMIC_RG_BUCK_VGPU12_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_EN_CLR, PMIC_RG_BUCK_VGPU12_OP_EN_CLR_MASK, PMIC_RG_BUCK_VGPU12_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG_SET, PMIC_RG_BUCK_VGPU12_OP_CFG_SET_MASK, PMIC_RG_BUCK_VGPU12_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VGPU12_OP_CFG_CLR, PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG0, PMIC_DA_VGPU12_VOSEL_MASK, PMIC_DA_VGPU12_VOSEL_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG0, PMIC_DA_VGPU12_VOSEL_GRAY_MASK, PMIC_DA_VGPU12_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG1, PMIC_DA_VGPU12_EN_MASK, PMIC_DA_VGPU12_EN_SHIFT, },
+ {MT6359_BUCK_VGPU12_DBG1, PMIC_DA_VGPU12_STB_MASK, PMIC_DA_VGPU12_STB_SHIFT, },
+ {MT6359_VGPUVCORE_ANA_CON8, PMIC_RG_VGPU12_FCCM_MASK, PMIC_RG_VGPU12_FCCM_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC1_ELR, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_MASK, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC1_VOSEL0, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC1_VOSEL1, PMIC_DA_VSRAM_PROC1_VOSEL_MASK, PMIC_DA_VSRAM_PROC1_VOSEL_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPROC1_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VPROC1_CON0, PMIC_RG_BUCK_VPROC1_EN_MASK, PMIC_RG_BUCK_VPROC1_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_CON0, PMIC_RG_BUCK_VPROC1_LP_MASK, PMIC_RG_BUCK_VPROC1_LP_SHIFT, },
+ {MT6359_BUCK_VPROC1_CON1, PMIC_RG_BUCK_VPROC1_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPROC1_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VPROC1_ELR0, PMIC_RG_BUCK_VPROC1_VOSEL_MASK, PMIC_RG_BUCK_VPROC1_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_SW_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN_SET, PMIC_RG_BUCK_VPROC1_OP_EN_SET_MASK, PMIC_RG_BUCK_VPROC1_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_EN_CLR, PMIC_RG_BUCK_VPROC1_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPROC1_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG_SET, PMIC_RG_BUCK_VPROC1_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPROC1_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VPROC1_OP_CFG_CLR, PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG0, PMIC_DA_VPROC1_VOSEL_MASK, PMIC_DA_VPROC1_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG0, PMIC_DA_VPROC1_VOSEL_GRAY_MASK, PMIC_DA_VPROC1_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG1, PMIC_DA_VPROC1_EN_MASK, PMIC_DA_VPROC1_EN_SHIFT, },
+ {MT6359_BUCK_VPROC1_DBG1, PMIC_DA_VPROC1_STB_MASK, PMIC_DA_VPROC1_STB_SHIFT, },
+ {MT6359_VPROC1_ANA_CON3, PMIC_RG_VPROC1_FCCM_MASK, PMIC_RG_VPROC1_FCCM_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC2_ELR, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_MASK, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC2_VOSEL0, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_SHIFT, },
+ {MT6359_LDO_VSRAM_PROC2_VOSEL1, PMIC_DA_VSRAM_PROC2_VOSEL_MASK, PMIC_DA_VSRAM_PROC2_VOSEL_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPROC2_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VPROC2_CON0, PMIC_RG_BUCK_VPROC2_EN_MASK, PMIC_RG_BUCK_VPROC2_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_CON0, PMIC_RG_BUCK_VPROC2_LP_MASK, PMIC_RG_BUCK_VPROC2_LP_SHIFT, },
+ {MT6359_BUCK_VPROC2_CON1, PMIC_RG_BUCK_VPROC2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPROC2_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VPROC2_ELR0, PMIC_RG_BUCK_VPROC2_VOSEL_MASK, PMIC_RG_BUCK_VPROC2_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_SW_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN_SET, PMIC_RG_BUCK_VPROC2_OP_EN_SET_MASK, PMIC_RG_BUCK_VPROC2_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_EN_CLR, PMIC_RG_BUCK_VPROC2_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPROC2_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG_SET, PMIC_RG_BUCK_VPROC2_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPROC2_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VPROC2_OP_CFG_CLR, PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG0, PMIC_DA_VPROC2_VOSEL_MASK, PMIC_DA_VPROC2_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG0, PMIC_DA_VPROC2_VOSEL_GRAY_MASK, PMIC_DA_VPROC2_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG1, PMIC_DA_VPROC2_EN_MASK, PMIC_DA_VPROC2_EN_SHIFT, },
+ {MT6359_BUCK_VPROC2_DBG1, PMIC_DA_VPROC2_STB_MASK, PMIC_DA_VPROC2_STB_SHIFT, },
+ {MT6359_VPROC2_ANA_CON3, PMIC_RG_VPROC2_FCCM_MASK, PMIC_RG_VPROC2_FCCM_SHIFT, },
+ {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPU_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
+ {MT6359_BUCK_VPU_CON0, PMIC_RG_BUCK_VPU_EN_MASK, PMIC_RG_BUCK_VPU_EN_SHIFT, },
+ {MT6359_BUCK_VPU_CON0, PMIC_RG_BUCK_VPU_LP_MASK, PMIC_RG_BUCK_VPU_LP_SHIFT, },
+ {MT6359_BUCK_VPU_CON1, PMIC_RG_BUCK_VPU_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPU_VOSEL_SLEEP_SHIFT, },
+ {MT6359_BUCK_VPU_ELR0, PMIC_RG_BUCK_VPU_VOSEL_MASK, PMIC_RG_BUCK_VPU_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_SW_OP_EN_MASK, PMIC_RG_BUCK_VPU_SW_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW0_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW1_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW2_OP_EN_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN_SET, PMIC_RG_BUCK_VPU_OP_EN_SET_MASK, PMIC_RG_BUCK_VPU_OP_EN_SET_SHIFT, },
+ {MT6359_BUCK_VPU_OP_EN_CLR, PMIC_RG_BUCK_VPU_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPU_OP_EN_CLR_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW0_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW1_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW2_OP_CFG_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG_SET, PMIC_RG_BUCK_VPU_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPU_OP_CFG_SET_SHIFT, },
+ {MT6359_BUCK_VPU_OP_CFG_CLR, PMIC_RG_BUCK_VPU_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPU_OP_CFG_CLR_SHIFT, },
+ {MT6359_BUCK_VPU_DBG0, PMIC_DA_VPU_VOSEL_MASK, PMIC_DA_VPU_VOSEL_SHIFT, },
+ {MT6359_BUCK_VPU_DBG0, PMIC_DA_VPU_VOSEL_GRAY_MASK, PMIC_DA_VPU_VOSEL_GRAY_SHIFT, },
+ {MT6359_BUCK_VPU_DBG1, PMIC_DA_VPU_EN_MASK, PMIC_DA_VPU_EN_SHIFT, },
+ {MT6359_BUCK_VPU_DBG1, PMIC_DA_VPU_STB_MASK, PMIC_DA_VPU_STB_SHIFT, },
+ {MT6359_VPU_ANA_CON3, PMIC_RG_VPU_FCCM_MASK, PMIC_RG_VPU_FCCM_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW0_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW1_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW2_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE_SET, PMIC_RG_BUCK_VPU_OP_MODE_SET_MASK, PMIC_RG_BUCK_VPU_OP_MODE_SET_SHIFT, },
+ {MT6359_BUCK_VPU_OP_MODE_CLR, PMIC_RG_BUCK_VPU_OP_MODE_CLR_MASK, PMIC_RG_BUCK_VPU_OP_MODE_CLR_SHIFT, },
+ {MT6359_BUCK_VCORE_CON0, PMIC_RG_BUCK_VCORE_EN_MASK, PMIC_RG_BUCK_VCORE_EN_SHIFT, },
+ {MT6359_BUCK_VCORE_CON0, PMIC_RG_BUCK_VCORE_LP_MASK, PMIC_RG_BUCK_VCORE_LP_SHIFT, },
+ {MT6359_VIO18_ANA_CON0, PMIC_RG_VIO18_VOCAL_MASK, PMIC_RG_VIO18_VOCAL_SHIFT, },
+ {MT6359_VIO18_ANA_CON0, PMIC_RG_VIO18_VOSEL_MASK, PMIC_RG_VIO18_VOSEL_SHIFT, },
+ {MT6359_VRF18_ELR_1, PMIC_RG_VIO18_VOTRIM_MASK, PMIC_RG_VIO18_VOTRIM_SHIFT, },
+};
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_HANDLE current_dcl_handle = 0;
+#endif
+
+//#define DCL_PMIC_PERMISSION_CONTROL
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
+#endif
+
+//////////////////////////////////////////////////
+// WRITE APIs //
+//////////////////////////////////////////////////
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
+{
+ DCL_BOOL ret = DCL_FALSE;
+ kal_uint8 c = ((offset>>8) & 0xFF);
+
+ switch(c)
+ {
+ case 0x82:
+ {
+ //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
+ if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x90:
+ {
+ //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
+ if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x98:
+ {
+ //Audio Analog : 0x9800~0x9852
+ if(offset >= 0x9800 && offset <= 0x9852)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0x9A:
+ {
+ //Audio DRE : 0x9A00 ~0x9A0A
+ if(offset >= 0x9A00 && offset <= 0x9A0A)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ case 0xE0:
+ case 0xE1:
+ {
+ //Audio digital : 0xE000 ~0xE138
+ if(offset >= 0xE000 && offset <= 0xE138)
+ ret=DCL_TRUE;
+ }
+ break;
+
+ default:
+ ret=DCL_FALSE;
+ break;
+ }
+ return ret;
+}
+#endif
+// Write Whole Bytes
+void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write Whole Bytes
+void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
+{
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = val;
+ }
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+
+// Write register field
+void dcl_pmic_field_write(PMIC6359_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+}
+
+// Write register field
+void dcl_pmic_field_write_nolock(PMIC6359_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ pmic_reg_log.command_flag = flag;
+ pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
+
+ pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
+ pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
+
+ DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
+
+ pmic_reg_log.write_value = sel;
+ pmic_reg_log.address_offset = pTable[flag].offset;
+ pmic_reg_log.reg_mask = pTable[flag].mask;
+ pmic_reg_log.reg_shift = pTable[flag].shift;
+ pmic_reg_log.reg_addr = pTable[flag].offset;
+ pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+}
+//////////////////////////////////////////////////
+// READ APIs //
+//////////////////////////////////////////////////
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
+
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ kal_give_spinlock(dcl_pmic_access_spinlock);
+
+ return reg_temp;
+}
+
+// Read Whole Bytes
+DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
+{
+ DCL_UINT16 reg_temp;
+ DCL_UINT32 idx, type;
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, ®_temp);
+
+ if(addr < PMIC_MAX_REG_NUM)
+ {
+ pmic_reg[addr] = reg_temp;
+ }
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_temp;
+}
+
+// Read register field
+DCL_UINT16 dcl_pmic_field_read(PMIC6359_FLAGS_LIST_ENUM flag)
+{
+ const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
+ DCL_UINT16 reg_return = 0;
+ DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+ DCL_UINT32 idx = pmic_access_duration_index[type];
+
+ if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
+ type = PMIC_LOG_TYPE_HRT_DOMAIN;
+ else
+ type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
+
+ idx = pmic_access_duration_index[type];
+
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
+#endif
+
+ DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
+
+ reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
+ pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
+#endif
+
+ return reg_return;
+}
+
+// Exported for EM used
+void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
+ dcl_pmic_byte_write_nolock(reg, val);
+}
+
+kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
+ return dcl_pmic_byte_return_nolock(reg);
+}
+
+const DCL_UINT32 vpa_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
+ PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vsim1_vosel[] =
+{
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
+ PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vxo22_vosel[] =
+{
+ PMU_VOLT_01_800000_V, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+ PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+const DCL_UINT32 vmodem_vosel[] =
+{
+ PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+const DCL_UINT32 vsram_vmd_vosel[] =
+{
+ PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
+ PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
+};
+
+PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
+{
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
+ {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VGPU11), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VGPU12), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_PROC1), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+ {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_PROC2), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
+};
+
+
+extern PMU_CONTROL_HANDLER pmu_control_handler;
+
+DCL_UINT16 pmu_parameter_size = 0;
+
+DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
+{
+ DCL_UINT16 regVal;
+ DCL_INT32 return_val = STATUS_FAIL;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = handle;
+#endif
+ switch(cmd)
+ {
+ case LDO_BUCK_SET_EN: //Enable control in SW mode
+ {
+ PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VCORE_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ /* Enable BUCK_VPA_CK_SW_MODE before Enable VPA */
+ if (pLdoBuckCtrl->enable == 0x1)
+ dcl_pmic_byte_write_nolock(MT6359_BUCK_VPA_DBG1, 0x3000);
+
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
+
+ /* Disable BUCK_VPA_CK_SW_MODE after Disable VPA */
+ if (pLdoBuckCtrl->enable == 0x0)
+ dcl_pmic_byte_write_nolock(MT6359_BUCK_VPA_DBG1, 0x0);
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ /* Clear INT_STATUS_VSIM1_OC before Enable VSIM1 */
+ if (pLdoBuckCtrl->enable == 0x1)
+ dcl_pmic_byte_write_nolock(MT6359_LDO_TOP_INT_STATUS1, 0x10);
+
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ /* Clear INT_STATUS_VSIM2_OC before Enable VSIM2 */
+ if (pLdoBuckCtrl->enable == 0x1)
+ dcl_pmic_byte_write_nolock(MT6359_LDO_TOP_INT_STATUS1, 0x20);
+
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_LP_MODE_SET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VCORE_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ { // 1'b0:Normal mode, 1'b1:Low power mode
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_LP, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OCFB_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPU_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VIO18:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VIO18_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VCORE_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VIO18:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VIO18_VOSEL, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPU_VOSEL_SLEEP);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOSEL_SLEEP:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_VOSEL_SLEEP, pLdoBuckCtrl->code);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_MODESET:
+ {
+ PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VS2_FPWM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU11_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU12_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC1_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC2_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPU_FCCM, pLdoBuckCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << RG_BUCK_LDO_SW_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw0_op_en << RG_BUCK_LDO_HW0_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_en << RG_BUCK_LDO_HW1_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_en << RG_BUCK_LDO_HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VCORE_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_EN_SET_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_OP_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
+
+ kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << RG_BUCK_LDO_SW_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw0_op_en << RG_BUCK_LDO_HW0_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_en << RG_BUCK_LDO_HW1_OP_EN_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_en << RG_BUCK_LDO_HW2_OP_EN_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VCORE_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_EN_CLR_ADDR, mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << RG_BUCK_LDO_HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << RG_BUCK_LDO_HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << RG_BUCK_LDO_HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VCORE_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_CFG_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_CFG:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
+
+ kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << RG_BUCK_LDO_HW0_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw1_op_cfg << RG_BUCK_LDO_HW1_OP_CFG_SHIFT) |
+ (pLdoBuckCtrl->hw2_op_cfg << RG_BUCK_LDO_HW2_OP_CFG_SHIFT));
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VCORE:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VCORE_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM1:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF18:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_CFG_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
+ regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VSIM1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSIM2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPA_SW:
+ {
+ dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VXO22:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_MD:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_MD_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_OTHERS:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_OTHERS_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VGPU11_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VGPU12_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_PROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPROC1_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VSRAM_PROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_PROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPROC2_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPU_VOSEL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case VPA_GET_VOLTAGE_LIST:
+ {
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
+ pVpaCtrl->pVoltageList = vpa_vosel;
+ pVpaCtrl->number = GETARRNUM(vpa_vosel);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_SET_RQST:
+ {
+ //PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
+ if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
+ {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "ADC_SET_RQST error");
+ }
+ // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+ pmic_EM_reg_write(PMIC_AUXADC_RQST_CH7_BY_MD_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
+ AUXADC_Status = AUXADC_READ_REQUEST;
+ return_val = STATUS_OK;
+ }
+ break;
+
+
+ case ADC_GET_RDY_MD:
+ {
+ PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
+ pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
+ if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
+ {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "ADC_GET_RDY_MD error");
+ }
+
+ if(pAdcCtrl->status == DCL_TRUE)
+ {
+ AUXADC_Status = AUXADC_READ_READY;
+ }
+ else
+ {
+ AUXADC_Status = AUXADC_READ_BUSY;
+ }
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case ADC_GET_OUT_MD:
+ {
+ PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
+ if(AUXADC_Status != AUXADC_READ_READY)
+ {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "ADC_GET_OUT_MD error");
+ }
+ pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
+ AUXADC_Status = AUXADC_READ_DATA;
+ // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
+
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_EN:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case TOP_SET_SRCLKEN_IN_MODE:
+ {
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
+
+ switch(pTopSrclkenCtrl->mod)
+ {
+ case PMIC_SRCLKEN_IN0:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case PMIC_SRCLKEN_IN1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_FPWM *pLdoBuckSetFpwm = &(data->rPMULdoBuckSetFpwm);
+
+ switch(pLdoBuckSetFpwm->mod)
+ {
+ case VMODEM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU11_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VGPU12_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC1_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPROC2_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VPU_FCCM, pLdoBuckSetFpwm->enable);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_FPWM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_FPWM *pLdoBuckCtrl = &(data->rPMULdoBuckGetFpwm);
+
+ switch(pLdoBuckCtrl->mod)
+ {
+ case VMODEM:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VMODEM_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU11:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VGPU11_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VGPU12:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VGPU12_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC1:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPROC1_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPROC2:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPROC2_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPU_FCCM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case DCXO_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
+
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ break;
+
+ case DCXO_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case MISC_SET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
+#endif
+ {
+ pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
+ return_val = STATUS_OK;
+ }
+#if defined(DCL_PMIC_PERMISSION_CONTROL)
+ else
+ {
+ illegal_misc_set_register_value.offset = pChrCtrl->offset;
+ illegal_misc_set_register_value.value = pChrCtrl->value;
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "MISC_SET_REGISTER_VALUE error");
+ }
+#endif
+ }
+ break;
+
+ case MISC_GET_REGISTER_VALUE:
+ {
+ PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
+ pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case LDO_BUCK_SET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOCAL *pLdoBuckSetVocal = &(data->rPMULdoBuckSetVocal);
+
+ switch(pLdoBuckSetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VIO18_VOCAL:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VIO18_VOCAL, pLdoBuckSetVocal->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOCAL:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOCAL *pLdoBuckGetVocal = &(data->rPMULdoBuckGetVocal);
+
+ switch(pLdoBuckGetVocal->mod)
+ {
+ case VRF18_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VIO18_VOCAL:
+ {
+ pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VIO18_VOCAL);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+
+ case LDO_BUCK_SET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOTRIM *pLdoBuckSetVotrim = &(data->rPMULdoBuckSetVotrim);
+
+ switch(pLdoBuckSetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VIO18_VOTRIM:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_VIO18_VOTRIM, pLdoBuckSetVotrim->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VOTRIM:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VOTRIM *pLdoBuckGetVotrim = &(data->rPMULdoBuckGetVotrim);
+
+ switch(pLdoBuckGetVotrim->mod)
+ {
+ case VRF18_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VIO18_VOTRIM:
+ {
+ pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VIO18_VOTRIM);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS *pLdoBuckSetVpaOcSdnStatus = &(data->rPMULdoBuckSetVpaOcSdnStatus);
+
+ switch(pLdoBuckSetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS, pLdoBuckSetVpaOcSdnStatus->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_STATUS:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS *pLdoBuckGetVpaOcSdnStatus = &(data->rPMULdoBuckGetVpaOcSdnStatus);
+
+ switch(pLdoBuckGetVpaOcSdnStatus->mod)
+ {
+ case VPA_OC_SDN_STATUS:
+ {
+ pLdoBuckGetVpaOcSdnStatus->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VPA_OC_SDN_EN:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN *pLdoBuckSetVpaOcSdnEn = &(data->rPMULdoBuckSetVpaOcSdnEn);
+
+ switch(pLdoBuckSetVpaOcSdnEn->mod)
+ {
+ case VPA_OC_SDN_EN:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN, pLdoBuckSetVpaOcSdnEn->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_GET_VPA_OC_SDN_EN:
+ {
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN *pLdoBuckGetVpaOcSdnEn = &(data->rPMULdoBuckGetVpaOcSdnEn);
+
+ switch(pLdoBuckGetVpaOcSdnEn->mod)
+ {
+ case VPA_OC_SDN_EN:
+ {
+ pLdoBuckGetVpaOcSdnEn->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_OP_MODE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_OP_MODE *pLdoBuckSetOpMode = &(data->rPMULdoBuckSetOpMode);
+
+ switch(pLdoBuckSetOpMode->mod)
+ {
+ case VRF18:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_MODE, pLdoBuckSetOpMode->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VRF12:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_MODE, pLdoBuckSetOpMode->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VFE28:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_MODE, pLdoBuckSetOpMode->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_HW_OP_MODE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_MODE *pLdoBuckSetHwOpMode = &(data->rPMULdoBuckSetHwOpMode);
+
+ kal_uint16 value =((pLdoBuckSetHwOpMode->hw0_op_mode << RG_BUCK_LDO_HW0_OP_MODE_SHIFT) |
+ (pLdoBuckSetHwOpMode->hw1_op_mode << RG_BUCK_LDO_HW1_OP_MODE_SHIFT) |
+ (pLdoBuckSetHwOpMode->hw2_op_mode << RG_BUCK_LDO_HW2_OP_MODE_SHIFT));
+
+ switch(pLdoBuckSetHwOpMode->mod)
+ {
+ case VCORE:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VCORE_OP_MODE_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_MODE_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_MODE_SET_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_CLR_HW_OP_MODE:
+ {
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_MODE *pLdoBuckClrHwOpMode = &(data->rPMULdoBuckClrHwOpMode);
+
+ kal_uint16 value =((pLdoBuckClrHwOpMode->hw0_op_mode << RG_BUCK_LDO_HW0_OP_MODE_SHIFT) |
+ (pLdoBuckClrHwOpMode->hw1_op_mode << RG_BUCK_LDO_HW1_OP_MODE_SHIFT) |
+ (pLdoBuckClrHwOpMode->hw2_op_mode << RG_BUCK_LDO_HW2_OP_MODE_SHIFT));
+
+ switch(pLdoBuckClrHwOpMode->mod)
+ {
+ case VCORE:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VCORE_OP_MODE_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VMODEM:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_MODE_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VPU:
+ {
+ pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_MODE_CLR_ADDR, value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case LDO_BUCK_SET_VOTER_VOLTAGE:
+ {
+ PMU_CTRL_LDO_BUCK_SET_VOTER_VOLTAGE *pLdoBuckSetVoterVoltage = &(data->rPMULdoBuckSetVoterVoltage);
+
+ switch(pLdoBuckSetVoterVoltage->mod)
+ {
+ case VS1:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckSetVoterVoltage->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ case VS2:
+ {
+ dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckSetVoterVoltage->value);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+ }
+ break;
+
+ case MISC_GET_CID:
+ {
+ PMU_CTRL_MISC_GET_CID *pMiscGetCtrl = &(data->rPMUMiscGetCid);
+ pMiscGetCtrl->cid_value = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_HWCID);
+ return_val = STATUS_OK;
+ }
+ break;
+
+ default:
+ return_val = STATUS_UNSUPPORTED;
+ break;
+ }
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ current_dcl_handle = 0;
+#endif
+ return return_val;
+
+}
+
+extern void dcl_pmic_modem_only_init(void);
+extern void PMIC_Read_All(void);
+#if defined(PMIC_UNIT_TEST)
+extern void PMIC_Read_All(void);
+extern void PMIC_Unit_Test(void);
+#endif
+DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
+{
+ return dcl_pmic_byte_return(pmic_addr);
+}
+
+void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
+{
+ dcl_pmic_byte_write(pmic_addr, value);
+}
+
+void dcl_pmic_init(void){
+ extern void pmic_wrap_dump_init(void);
+ pmu_control_handler = PMIC_control_handler;
+ pmu_parameter_size = GETARRNUM(pmu_parameter_table);
+
+ pmic_wrap_dump_init();
+
+ dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
+ dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
+
+#if !defined(__SMART_PHONE_MODEM__)
+ DrvPWRAP_Init();
+#endif
+ pmic_hw_version = dcl_pmic_byte_return(MT6359_HWCID);
+ if (pmic_hw_version == 0x0) {
+ DEBUG_ASSERT(0);
+ MODEM_WARNING_MESSAGE(0, "Get HWCID error");
+ }
+
+#if defined(__IC_SLT__) || !defined(__HIF_CCCI_SUPPORT__)
+ dcl_pmic_byte_write(PMIC_TMA_KEY_ADDR, 0x9CA6);
+#endif
+
+ PMIC_Read_All();
+
+#if !defined(__SMART_PHONE_MODEM__)
+
+/*
+ if(DrvPWRAP_CheckCIPHER() == 1)
+ dcl_pmic6355_modem_only_init();
+ else
+*/
+ dcl_pmic_modem_only_init();
+
+#endif
+
+#if defined(PMIC_UNIT_TEST)
+ PMIC_Read_All();
+ PMIC_Unit_Test();
+ PMIC_Read_All();
+#endif
+ pmic_init_done = DCL_TRUE;
+
+}
+
+void PMIC_Read_All(void)
+{
+ volatile kal_uint32 i,j;
+ j=0;
+ for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
+ pmic_reg[i] = dcl_pmic_byte_return(i);
+ while(j!=0x200){j++;}
+ j=0;
+ }
+}
+#if defined(PMIC_UNIT_TEST)
+void PMIC_Unit_Test(void)
+{
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VPA_SW;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VPA_SW;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
+ PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
+ PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
+ PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
+ PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
+ PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
+ PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
+ PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
+ PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
+ PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
+ PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
+ PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
+ PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
+ PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
+ PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
+ PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VPA_SW;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.regval = 0x7; // (0x0~0xF)
+ DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ // val.regval will be your request value ( no need do any shift)
+ DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VRF2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_MODESET val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod = VRF1;
+ val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
+ DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.sel = SRCLKEN_IN1_SEL;
+ /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
+ val.mod = VMIPI;
+ DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM1;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
+ val.mod = VSIM2;
+ DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM1;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+
+ {
+ DCL_HANDLE handle;
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
+ handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+ val.mod=VSIM2;
+ val.voltage = PMU_VOLT_01_800000_V;
+ /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
+ DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(handle);
+ }
+}
+#endif // End of #if defined(PMIC_UNIT_TEST)
+
+#endif // End of #if defined(PMIC_6359P_REG_API)
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmic6359p_init.c b/mcu/driver/devdrv/pmic/src/dcl_pmic6359p_init.c
new file mode 100644
index 0000000..68b711f
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmic6359p_init.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2019
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6359p_init.c
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6359P
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "init.h"
+#include "dcl.h"
+
+extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+// MT6359 ECO_E3
+void dcl_pmic_modem_only_init(void)
+{
+ /* change PMIC initial setting to preloader for all SW load.
+ If you want to change pmic setting, please contact PT Lead & PMIC AP SW */
+
+}
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmu.c b/mcu/driver/devdrv/pmic/src/dcl_pmu.c
new file mode 100644
index 0000000..771117c
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmu.c
@@ -0,0 +1,389 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu.c
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * This Module defines DCL (Driver Common Layer) of the PMIC driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ ****************************************************************************/
+#include "kal_debug.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "dcl.h"
+#include "dcl_pmu_sw.h"
+#include "dcl_pmu_common_sw.h"
+#include "us_timer.h"
+
+#ifndef DRV_PMIC_OFF
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+PMIC_ACCESS_DURATION_DBG pmic_access_duration_log[PMIC_LOG_TYPE_MAX][PMIC_DURATION_LOG_MAX][MAX_PMIC_DURATION_INFO_SIZE];
+DCL_UINT32 pmic_access_duration_index [PMIC_LOG_TYPE_MAX] = {0};
+DCL_UINT32 pmic_access_timing_issue_log [PMIC_LOG_TYPE_MAX][MAX_PMIC_DURATION_INFO_SIZE];
+DCL_UINT32 pmic_access_timing_issue_index [PMIC_LOG_TYPE_MAX]= {0};
+#endif // End of #if defined(DCL_PMIC_ACCESS_TIME_LOG)
+
+kal_spinlockid dcl_pmic_control_spinlock;
+kal_atomic_uint32 dcl_pmic_hrt_flag = 0;
+
+PMU_CONTROL_HANDLER pmu_control_handler = 0;
+static DCL_UINT32 dcl_pmu_handle_count = 0;
+
+#if defined(DCL_PMIC_MODULE_CONTROL)
+DCL_FLAGS dcl_pmu_handle_flags = FLAGS_NONE;
+
+DCL_FLAGS DclPMU_GetCurrentHandlerFlag(DCL_HANDLE handle)
+{
+ if( handle == dcl_pmu_handle_count )
+ return dcl_pmu_handle_flags ;
+
+ return FLAGS_NONE;
+}
+#endif
+
+kal_atomic_uint32 DclPMU_GetHrtFlag(void)
+{
+ return kal_atomic_read(&dcl_pmic_hrt_flag);
+}
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_Initialize
+*
+* DESCRIPTION
+* This function is to initialize PMU module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclPMU_Initialize(void)
+{
+#if defined(MT6353)
+extern void dcl_pmic6353_init(void);
+ dcl_pmic6353_init();
+#else
+extern void dcl_pmic_init(void);
+ dcl_pmic_init();
+#endif
+
+ return STATUS_OK;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_Open
+*
+* DESCRIPTION
+* This function is to open the PMU module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_PMU
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed.
+* other value: a valid handle
+*
+*************************************************************************/
+DCL_HANDLE DclPMU_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+ kal_uint32 handle;
+ kal_uint32 savedMask=0;
+
+ if (dev != DCL_PMU){
+ return DCL_HANDLE_INVALID; // Incorrecr device ID
+ }
+ savedMask = kal_hrt_SaveAndSetIRQMask();
+ dcl_pmu_handle_count++;
+ handle = dcl_pmu_handle_count;
+#if defined(DCL_PMIC_MODULE_CONTROL)
+ dcl_pmu_handle_flags = flags;
+#endif
+ kal_hrt_RestoreIRQMask(savedMask);
+
+ // Register DCL default lisr
+ return handle;
+}
+/*************************************************************************
+* FUNCTION
+* DclPMU_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclPMU_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclPMU_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_Configure
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclPMU_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the PMU module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPMU_Open
+* event: Supported events:
+* EVENT_PMU_TIMEOUT: Watch dog time out interrupt
+* callback: the callback function for registered events
+*
+* RETURNS
+* STATUS_OK: Successfully register the callback function.
+* STATUS_INVALID_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_INVALID_EVENT: The event parameter is invalid.
+* STATUS_UNSUPPORTED: The function is NOT supported
+*
+*************************************************************************/
+DCL_STATUS DclPMU_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_Control
+*
+* DESCRIPTION
+* This function is to send command to control the PMU module.
+*
+* PARAMETERS
+* handle: The handle value returned from DclPMU_Open
+* cmd: a control command for PMU module
+* PMU38: Refer dcl_pmu38.c
+*
+*
+* data: The data of the control command
+* PMU38: Refer dcl_pmu38.c
+*
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+DCL_STATUS DclPMU_Control_Wrap(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data, PMIC_LOG_TYPE_ENUM type)
+{
+
+#if defined(DCL_PMIC_ACCESS_TIME_LOG)
+ DCL_STATUS pmu_control_status;
+ DCL_UINT32 duration_idx = pmic_access_duration_index[type];
+ DCL_UINT32 issue_idx = pmic_access_timing_issue_index[type];
+
+
+ if(type == PMIC_LOG_TYPE_NORMAL_DOMAIN)
+ kal_take_spinlock(dcl_pmic_control_spinlock, KAL_INFINITE_WAIT);
+
+ pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].start_time = ust_get_current_time();
+
+ pmu_control_status = pmu_control_handler(handle,cmd,data);
+
+ pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].end_time = ust_get_current_time();
+ pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].cmd = cmd;
+ pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].start_time, pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].end_time);
+
+ if(pmic_access_duration_log[type][PMIC_DCL_DBG][duration_idx].duration_time > PMIC_ACCESS_DURATION_THRESHOLD)
+ {
+ pmic_access_timing_issue_log[type][issue_idx] = duration_idx;
+ issue_idx++;
+ issue_idx = issue_idx &(MAX_PMIC_DURATION_INFO_SIZE - 1);
+ pmic_access_timing_issue_index[type] = issue_idx;
+ }
+
+ duration_idx++;
+ duration_idx = duration_idx &(MAX_PMIC_DURATION_INFO_SIZE - 1);
+ pmic_access_duration_index[type] = duration_idx;
+
+ if(type == PMIC_LOG_TYPE_NORMAL_DOMAIN)
+ kal_give_spinlock(dcl_pmic_control_spinlock);
+
+ return pmu_control_status;
+
+#else
+ return pmu_control_handler(handle, cmd, data);
+#endif
+}
+
+DCL_STATUS DclPMU_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ DCL_STATUS pmu_control_status;
+
+ if (kal_get_current_domain() == KAL_DOMAIN_NORMAL)
+ {
+ pmu_control_status = DclPMU_Control_Wrap(handle, cmd, data, PMIC_LOG_TYPE_NORMAL_DOMAIN);
+ } else { //HRT/CHRT domain
+ kal_atomic_inc(&dcl_pmic_hrt_flag);
+ pmu_control_status = DclPMU_Control_Wrap(handle, cmd, data, PMIC_LOG_TYPE_HRT_DOMAIN);
+ kal_atomic_dec(&dcl_pmic_hrt_flag);
+ }
+
+ return pmu_control_status;
+}
+/*************************************************************************
+* FUNCTION
+* DclPMU_Close
+*
+* DESCRIPTION
+* This function is to close the PMU module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPMU_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclPMU_Close(DCL_HANDLE handle)
+{
+ return STATUS_OK;
+}
+
+
+#else // DRV_PMIC_OFF
+DCL_STATUS DclPMU_Initialize(void)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_HANDLE DclPMU_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclPMU_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclPMU_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclPMU_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclPMU_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclPMU_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclPMU_Close(DCL_HANDLE handle)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+#endif // DRV_PMIC_OFF
+
+
diff --git a/mcu/driver/devdrv/pmic/src/dcl_pmu_common.c b/mcu/driver/devdrv/pmic/src/dcl_pmu_common.c
new file mode 100644
index 0000000..775b8d6
--- /dev/null
+++ b/mcu/driver/devdrv/pmic/src/dcl_pmu_common.c
@@ -0,0 +1,172 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu_common.c
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * This Module is for PMU common functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ ****************************************************************************/
+
+#include "dcl_pmu_sw.h"
+#include "kal_public_api.h"
+
+extern PMU_MOD_BASEADDR_ENTRY pmu_ldo_bb_profile[];
+extern DCL_UINT8 pmuModtoIdx[];
+
+extern PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[];
+extern DCL_UINT16 pmu_parameter_size;
+
+#if defined(PMIC_PRESENT)
+DCL_UINT16 PMU_get_Parameter_Idx(DCL_CTRL_CMD cmd)
+{
+ PMU_PARAMETER_TABLE_ENTRY *ptable = pmu_parameter_table;
+ DCL_UINT32 i,size = pmu_parameter_size;
+
+ for(i = 0;i < size;i++)
+ {
+ if ((ptable[i].cmd & MODMASK) == ALLMOD)
+ {
+ if((ptable[i].cmd & CMDMASK) == (cmd & CMDMASK))
+ break;
+ }
+ else
+ {
+ if (ptable[i].cmd == (DCL_UINT32)cmd)
+ break;
+ }
+ }
+
+ if (i >= size)
+ return PARAMETER_UNKNOWN;
+
+ return i;
+}
+
+DCL_UINT16 PMU_Parameter_to_Value(DCL_CTRL_CMD cmd,DCL_UINT32 val)
+{
+ PMU_PARAMETER_TABLE_ENTRY *ptable;
+ DCL_UINT32 *parameter;
+ DCL_UINT16 *pval;
+ DCL_UINT32 idx,i,size = pmu_parameter_size;
+
+ idx = PMU_get_Parameter_Idx(cmd);
+
+ //¨S¦³³o²Õ³]©wÈ
+ if (idx ==PARAMETER_UNKNOWN)
+ return PARAMETER_UNKNOWN;
+
+ ptable = &pmu_parameter_table[idx];
+
+
+ parameter = (DCL_UINT32 *)ptable->pVals;
+ size = ptable->size;
+
+ for(i = 0;i < size;i++)
+ {
+ if (val == parameter[i])
+ {
+ if (ptable->pRegVals == NULL)
+ {
+ return i;
+ }
+ else
+ {
+ pval = (DCL_UINT16 *)ptable->pRegVals;
+ return pval[i];
+ }
+ }
+ }
+
+ //¦³³o²Õ³]©wÈ,¦ý§ä¤£¨ìmatch value
+ ASSERT(0);
+ return 0;
+}
+
+DCL_UINT32 PMU_Value_to_Parameter(DCL_CTRL_CMD cmd,DCL_UINT32 val)
+{
+ PMU_PARAMETER_TABLE_ENTRY *ptable;
+ DCL_UINT32 *parameter;
+ DCL_UINT16 *pval;
+ DCL_UINT32 idx, i, size;
+
+ idx = PMU_get_Parameter_Idx(cmd);
+
+ //¨S¦³³o²Õ³]©wÈ
+ if (idx == PARAMETER_UNKNOWN)
+ return PARAMETERVAL_UNKNOWN;
+
+ ptable = &pmu_parameter_table[idx];
+
+ parameter = (DCL_UINT32 *)ptable->pVals;
+ pval = (DCL_UINT16 *)ptable->pRegVals;
+ size = ptable->size;
+
+ if (pval == NULL)
+ {
+ return parameter[val];
+ }
+ else
+ {
+ for(i = 0;i < size;i++)
+ {
+ if (pval[i] == val)
+ return parameter[i];
+ }
+ }
+
+ return PARAMETER_UNKNOWN;
+}
+#endif // End of #if defined(PMIC_PRESENT)
+
+
+
+
+
+