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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70^! / . / mcu / driver / devdrv / spmi
commit6c1fd8fba87d5723e0e5614ae30b4258b603cb70[log] [tgz]
authorrjw <rjw@exm.com>Wed Nov 30 14:33:01 2022 +0800
committerrjw <rjw@exm.com>Wed Nov 30 14:33:01 2022 +0800
treef240d48a5b4cfc313708afa1dd3fe327b4db6d5d
parenta0d9f599de441a0ad7b363fe8f9a9a6bae676d2f [diff]
[Feature]Upload Modem source code

Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37

diff --git a/mcu/driver/devdrv/spmi/inc/mt6315_upmu_hw.h b/mcu/driver/devdrv/spmi/inc/mt6315_upmu_hw.h
new file mode 100644
index 0000000..aa3f866
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/inc/mt6315_upmu_hw.h

@@ -0,0 +1,6733 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#ifndef _MT_PMIC_UPMU_HW_MT6315_H_
+#define _MT_PMIC_UPMU_HW_MT6315_H_
+
+#define PMU_FLAG_TABLE_ENTRY struct pmu_flag_table_entry_t
+#define PMU_FLAGS_LIST_ENUM enum PMU_FLAGS_LIST
+
+#define MT6315_PMIC_REG_BASE			((unsigned int)(0x0))
+
+#define MT6315_TOP0_ID                    (MT6315_PMIC_REG_BASE+0x0)
+#define MT6315_TOP0_ID_H                  (MT6315_PMIC_REG_BASE+0x1)
+#define MT6315_TOP0_REV0                  (MT6315_PMIC_REG_BASE+0x2)
+#define MT6315_TOP0_REV0_H                (MT6315_PMIC_REG_BASE+0x3)
+#define MT6315_TOP0_DSN_DBI               (MT6315_PMIC_REG_BASE+0x4)
+#define MT6315_TOP0_DSN_DBI_H             (MT6315_PMIC_REG_BASE+0x5)
+#define MT6315_TOP0_DSN_DXI               (MT6315_PMIC_REG_BASE+0x6)
+#define MT6315_TOP0_DMY                   (MT6315_PMIC_REG_BASE+0x7)
+#define MT6315_HWCID_L                    (MT6315_PMIC_REG_BASE+0x8)
+#define MT6315_HWCID_H                    (MT6315_PMIC_REG_BASE+0x9)
+#define MT6315_SWCID_L                    (MT6315_PMIC_REG_BASE+0xa)
+#define MT6315_SWCID_H                    (MT6315_PMIC_REG_BASE+0xb)
+#define MT6315_POFFSTS                    (MT6315_PMIC_REG_BASE+0xc)
+#define MT6315_PSTSCTL                    (MT6315_PMIC_REG_BASE+0xd)
+#define MT6315_PG_DEB_STS0                (MT6315_PMIC_REG_BASE+0xe)
+#define MT6315_PG_SDN_STS0                (MT6315_PMIC_REG_BASE+0xf)
+#define MT6315_OC_SDN_STS0                (MT6315_PMIC_REG_BASE+0x10)
+#define MT6315_THERMALSTATUS              (MT6315_PMIC_REG_BASE+0x11)
+#define MT6315_THERMALDEB                 (MT6315_PMIC_REG_BASE+0x12)
+#define MT6315_TOP_CON                    (MT6315_PMIC_REG_BASE+0x13)
+#define MT6315_TEST_OUT                   (MT6315_PMIC_REG_BASE+0x14)
+#define MT6315_TEST_CON0                  (MT6315_PMIC_REG_BASE+0x15)
+#define MT6315_TEST_CON1                  (MT6315_PMIC_REG_BASE+0x16)
+#define MT6315_TEST_CON2                  (MT6315_PMIC_REG_BASE+0x17)
+#define MT6315_TEST_CON3                  (MT6315_PMIC_REG_BASE+0x18)
+#define MT6315_TEST_CON4                  (MT6315_PMIC_REG_BASE+0x19)
+#define MT6315_TEST_CON5                  (MT6315_PMIC_REG_BASE+0x1a)
+#define MT6315_TEST_CON6                  (MT6315_PMIC_REG_BASE+0x1b)
+#define MT6315_TEST_CON7                  (MT6315_PMIC_REG_BASE+0x1c)
+#define MT6315_TEST_CON8                  (MT6315_PMIC_REG_BASE+0x1d)
+#define MT6315_TEST_CON9                  (MT6315_PMIC_REG_BASE+0x1e)
+#define MT6315_TESTMODE_SW                (MT6315_PMIC_REG_BASE+0x1f)
+#define MT6315_TDSEL_CON                  (MT6315_PMIC_REG_BASE+0x20)
+#define MT6315_RDSEL_CON                  (MT6315_PMIC_REG_BASE+0x21)
+#define MT6315_SMT_CON0                   (MT6315_PMIC_REG_BASE+0x22)
+#define MT6315_EH_CON0                    (MT6315_PMIC_REG_BASE+0x23)
+#define MT6315_RSEL_CON0                  (MT6315_PMIC_REG_BASE+0x24)
+#define MT6315_TOP_RSV0                   (MT6315_PMIC_REG_BASE+0x25)
+#define MT6315_TOP_RSV1                   (MT6315_PMIC_REG_BASE+0x26)
+#define MT6315_DRV_CON0                   (MT6315_PMIC_REG_BASE+0x27)
+#define MT6315_FILTER_CON0                (MT6315_PMIC_REG_BASE+0x28)
+#define MT6315_FILTER_CON1                (MT6315_PMIC_REG_BASE+0x29)
+#define MT6315_TOP_STATUS                 (MT6315_PMIC_REG_BASE+0x2a)
+#define MT6315_TOP_STATUS_SET             (MT6315_PMIC_REG_BASE+0x2b)
+#define MT6315_TOP_STATUS_CLR             (MT6315_PMIC_REG_BASE+0x2c)
+#define MT6315_TOP_PWOFF_CON              (MT6315_PMIC_REG_BASE+0x2d)
+#define MT6315_TOP_TRAP                   (MT6315_PMIC_REG_BASE+0x2e)
+#define MT6315_TOP1_ID                    (MT6315_PMIC_REG_BASE+0x80)
+#define MT6315_TOP1_ID_H                  (MT6315_PMIC_REG_BASE+0x81)
+#define MT6315_TOP1_REV0                  (MT6315_PMIC_REG_BASE+0x82)
+#define MT6315_TOP1_REV0_H                (MT6315_PMIC_REG_BASE+0x83)
+#define MT6315_TOP1_DSN_DBI               (MT6315_PMIC_REG_BASE+0x84)
+#define MT6315_TOP1_DSN_DBI_H             (MT6315_PMIC_REG_BASE+0x85)
+#define MT6315_TOP1_DSN_DXI               (MT6315_PMIC_REG_BASE+0x86)
+#define MT6315_GPIO_DIR                   (MT6315_PMIC_REG_BASE+0x87)
+#define MT6315_GPIO_DIR_SET               (MT6315_PMIC_REG_BASE+0x88)
+#define MT6315_GPIO_DIR_CLR               (MT6315_PMIC_REG_BASE+0x89)
+#define MT6315_GPIO_PULLEN0               (MT6315_PMIC_REG_BASE+0x8a)
+#define MT6315_GPIO_PULLEN0_SET           (MT6315_PMIC_REG_BASE+0x8b)
+#define MT6315_GPIO_PULLEN0_CLR           (MT6315_PMIC_REG_BASE+0x8c)
+#define MT6315_GPIO_PULLSEL0              (MT6315_PMIC_REG_BASE+0x8d)
+#define MT6315_GPIO_PULLSEL0_SET          (MT6315_PMIC_REG_BASE+0x8e)
+#define MT6315_GPIO_PULLSEL0_CLR          (MT6315_PMIC_REG_BASE+0x8f)
+#define MT6315_GPIO_DINV                  (MT6315_PMIC_REG_BASE+0x90)
+#define MT6315_GPIO_DINV_SET              (MT6315_PMIC_REG_BASE+0x91)
+#define MT6315_GPIO_DINV_CLR              (MT6315_PMIC_REG_BASE+0x92)
+#define MT6315_GPIO_DOUT                  (MT6315_PMIC_REG_BASE+0x93)
+#define MT6315_GPIO_DOUT_SET              (MT6315_PMIC_REG_BASE+0x94)
+#define MT6315_GPIO_DOUT_CLR              (MT6315_PMIC_REG_BASE+0x95)
+#define MT6315_GPIO_PI                    (MT6315_PMIC_REG_BASE+0x96)
+#define MT6315_GPIO_POE                   (MT6315_PMIC_REG_BASE+0x97)
+#define MT6315_GPIO_MODE0                 (MT6315_PMIC_REG_BASE+0x98)
+#define MT6315_GPIO_MODE0_SET             (MT6315_PMIC_REG_BASE+0x99)
+#define MT6315_GPIO_MODE0_CLR             (MT6315_PMIC_REG_BASE+0x9a)
+#define MT6315_GPIO_MODE1                 (MT6315_PMIC_REG_BASE+0x9b)
+#define MT6315_GPIO_MODE1_SET             (MT6315_PMIC_REG_BASE+0x9c)
+#define MT6315_GPIO_MODE1_CLR             (MT6315_PMIC_REG_BASE+0x9d)
+#define MT6315_GPIO_RSV                   (MT6315_PMIC_REG_BASE+0x9e)
+#define MT6315_GPIO_CON                   (MT6315_PMIC_REG_BASE+0x9f)
+#define MT6315_TOP2_ID                    (MT6315_PMIC_REG_BASE+0x100)
+#define MT6315_TOP2_ID_H                  (MT6315_PMIC_REG_BASE+0x101)
+#define MT6315_TOP2_REV0                  (MT6315_PMIC_REG_BASE+0x102)
+#define MT6315_TOP2_REV0_H                (MT6315_PMIC_REG_BASE+0x103)
+#define MT6315_TOP2_DSN_DBI               (MT6315_PMIC_REG_BASE+0x104)
+#define MT6315_TOP2_DSN_DBI_H             (MT6315_PMIC_REG_BASE+0x105)
+#define MT6315_TOP2_DSN_DXI               (MT6315_PMIC_REG_BASE+0x106)
+#define MT6315_TOP_PAM0                   (MT6315_PMIC_REG_BASE+0x107)
+#define MT6315_TOP_PAM0_H                 (MT6315_PMIC_REG_BASE+0x108)
+#define MT6315_TOP_PAM1                   (MT6315_PMIC_REG_BASE+0x109)
+#define MT6315_TOP_PAM1_H                 (MT6315_PMIC_REG_BASE+0x10a)
+#define MT6315_TOP_CKPDN_CON0             (MT6315_PMIC_REG_BASE+0x10b)
+#define MT6315_TOP_CKPDN_CON0_SET         (MT6315_PMIC_REG_BASE+0x10c)
+#define MT6315_TOP_CKPDN_CON0_CLR         (MT6315_PMIC_REG_BASE+0x10d)
+#define MT6315_TOP_CKPDN_CON1             (MT6315_PMIC_REG_BASE+0x10e)
+#define MT6315_TOP_CKPDN_CON1_SET         (MT6315_PMIC_REG_BASE+0x10f)
+#define MT6315_TOP_CKPDN_CON1_CLR         (MT6315_PMIC_REG_BASE+0x110)
+#define MT6315_TOP_CKSEL_CON0             (MT6315_PMIC_REG_BASE+0x111)
+#define MT6315_TOP_CKSEL_CON0_SET         (MT6315_PMIC_REG_BASE+0x112)
+#define MT6315_TOP_CKSEL_CON0_CLR         (MT6315_PMIC_REG_BASE+0x113)
+#define MT6315_TOP_CKDIVSEL_CON0          (MT6315_PMIC_REG_BASE+0x114)
+#define MT6315_TOP_CKDIVSEL_CON0_SET      (MT6315_PMIC_REG_BASE+0x115)
+#define MT6315_TOP_CKDIVSEL_CON0_CLR      (MT6315_PMIC_REG_BASE+0x116)
+#define MT6315_TOP_CKHWEN_CON0            (MT6315_PMIC_REG_BASE+0x117)
+#define MT6315_TOP_CKHWEN_CON0_SET        (MT6315_PMIC_REG_BASE+0x118)
+#define MT6315_TOP_CKHWEN_CON0_CLR        (MT6315_PMIC_REG_BASE+0x119)
+#define MT6315_TOP_SMPS_OSC_DBG           (MT6315_PMIC_REG_BASE+0x11a)
+#define MT6315_TOP_CKTST_CON0             (MT6315_PMIC_REG_BASE+0x11b)
+#define MT6315_TOP_CKTST_CON1             (MT6315_PMIC_REG_BASE+0x11c)
+#define MT6315_TOP_CLK_CON0               (MT6315_PMIC_REG_BASE+0x11d)
+#define MT6315_TOP_RST_CON0               (MT6315_PMIC_REG_BASE+0x11e)
+#define MT6315_TOP_RST_CON0_SET           (MT6315_PMIC_REG_BASE+0x11f)
+#define MT6315_TOP_RST_CON0_CLR           (MT6315_PMIC_REG_BASE+0x120)
+#define MT6315_TOP_RST_CON1               (MT6315_PMIC_REG_BASE+0x121)
+#define MT6315_TOP_RST_CON1_SET           (MT6315_PMIC_REG_BASE+0x122)
+#define MT6315_TOP_RST_CON1_CLR           (MT6315_PMIC_REG_BASE+0x123)
+#define MT6315_TOP_RST_CON2               (MT6315_PMIC_REG_BASE+0x124)
+#define MT6315_TOP_RST_CON3               (MT6315_PMIC_REG_BASE+0x125)
+#define MT6315_TOP_RST_MISC               (MT6315_PMIC_REG_BASE+0x126)
+#define MT6315_TOP_RST_MISC_SET           (MT6315_PMIC_REG_BASE+0x127)
+#define MT6315_TOP_RST_MISC_CLR           (MT6315_PMIC_REG_BASE+0x128)
+#define MT6315_TOP_RST_STATUS             (MT6315_PMIC_REG_BASE+0x129)
+#define MT6315_TOP_RST_STATUS_SET         (MT6315_PMIC_REG_BASE+0x12a)
+#define MT6315_TOP_RST_STATUS_CLR         (MT6315_PMIC_REG_BASE+0x12b)
+#define MT6315_TOP_FQMTR_CON0             (MT6315_PMIC_REG_BASE+0x12c)
+#define MT6315_TOP_FQMTR_CON1             (MT6315_PMIC_REG_BASE+0x12d)
+#define MT6315_TOP_FQMTR_CON2             (MT6315_PMIC_REG_BASE+0x12e)
+#define MT6315_TOP_FQMTR_DAT0             (MT6315_PMIC_REG_BASE+0x12f)
+#define MT6315_TOP_FQMTR_DAT1             (MT6315_PMIC_REG_BASE+0x130)
+#define MT6315_TOP2_ELR_NUM               (MT6315_PMIC_REG_BASE+0x131)
+#define MT6315_TOP2_ELR0                  (MT6315_PMIC_REG_BASE+0x132)
+#define MT6315_TOP2_ELR1                  (MT6315_PMIC_REG_BASE+0x133)
+#define MT6315_TOP2_ELR2                  (MT6315_PMIC_REG_BASE+0x134)
+#define MT6315_TOP2_ELR3                  (MT6315_PMIC_REG_BASE+0x135)
+#define MT6315_TOP2_ELR4                  (MT6315_PMIC_REG_BASE+0x136)
+#define MT6315_TOP2_ELR5                  (MT6315_PMIC_REG_BASE+0x137)
+#define MT6315_TOP2_ELR6                  (MT6315_PMIC_REG_BASE+0x138)
+#define MT6315_TOP2_ELR7                  (MT6315_PMIC_REG_BASE+0x139)
+#define MT6315_TOP3_ID                    (MT6315_PMIC_REG_BASE+0x180)
+#define MT6315_TOP3_ID_H                  (MT6315_PMIC_REG_BASE+0x181)
+#define MT6315_TOP3_REV0                  (MT6315_PMIC_REG_BASE+0x182)
+#define MT6315_TOP3_REV0_H                (MT6315_PMIC_REG_BASE+0x183)
+#define MT6315_TOP3_DSN_DBI               (MT6315_PMIC_REG_BASE+0x184)
+#define MT6315_TOP3_DSN_DBI_H             (MT6315_PMIC_REG_BASE+0x185)
+#define MT6315_TOP3_DSN_DXI               (MT6315_PMIC_REG_BASE+0x186)
+#define MT6315_TOP_INT_CON0               (MT6315_PMIC_REG_BASE+0x187)
+#define MT6315_TOP_INT_CON0_SET           (MT6315_PMIC_REG_BASE+0x188)
+#define MT6315_TOP_INT_CON0_CLR           (MT6315_PMIC_REG_BASE+0x189)
+#define MT6315_TOP_INT_MASK_CON0          (MT6315_PMIC_REG_BASE+0x18a)
+#define MT6315_TOP_INT_MASK_CON0_SET      (MT6315_PMIC_REG_BASE+0x18b)
+#define MT6315_TOP_INT_MASK_CON0_CLR      (MT6315_PMIC_REG_BASE+0x18c)
+#define MT6315_TOP_INT_STATUS0            (MT6315_PMIC_REG_BASE+0x18d)
+#define MT6315_TOP_INT_RAW_STATUS0        (MT6315_PMIC_REG_BASE+0x18e)
+#define MT6315_TOP_INT_CON1               (MT6315_PMIC_REG_BASE+0x18f)
+#define MT6315_PMRC_CON0                  (MT6315_PMIC_REG_BASE+0x190)
+#define MT6315_PMRC_CON0_SET              (MT6315_PMIC_REG_BASE+0x191)
+#define MT6315_PMRC_CON0_CLR              (MT6315_PMIC_REG_BASE+0x192)
+#define MT6315_PMRC_CON1                  (MT6315_PMIC_REG_BASE+0x193)
+#define MT6315_PMRC_CON1_SET              (MT6315_PMIC_REG_BASE+0x194)
+#define MT6315_PMRC_CON1_CLR              (MT6315_PMIC_REG_BASE+0x195)
+#define MT6315_VDIG18_CON0                (MT6315_PMIC_REG_BASE+0x196)
+#define MT6315_VDIG18_CON1                (MT6315_PMIC_REG_BASE+0x197)
+#define MT6315_PLT0_ID_ANA_ID             (MT6315_PMIC_REG_BASE+0x380)
+#define MT6315_PLT0_ID_DIG_ID             (MT6315_PMIC_REG_BASE+0x381)
+#define MT6315_PLT0_REV0                  (MT6315_PMIC_REG_BASE+0x382)
+#define MT6315_PLT0_REV1                  (MT6315_PMIC_REG_BASE+0x383)
+#define MT6315_PLT0_REV2                  (MT6315_PMIC_REG_BASE+0x384)
+#define MT6315_PLT0_REV3                  (MT6315_PMIC_REG_BASE+0x385)
+#define MT6315_PLT0_DSN_DXI               (MT6315_PMIC_REG_BASE+0x386)
+#define MT6315_TOP_CLK_TRIM_0             (MT6315_PMIC_REG_BASE+0x387)
+#define MT6315_TOP_CLK_TRIM_1             (MT6315_PMIC_REG_BASE+0x388)
+#define MT6315_TOP_CLK_TRIM_2             (MT6315_PMIC_REG_BASE+0x389)
+#define MT6315_TOP_CLK_TRIM_3             (MT6315_PMIC_REG_BASE+0x38a)
+#define MT6315_PLT_CON0                   (MT6315_PMIC_REG_BASE+0x38b)
+#define MT6315_OTP_CON0                   (MT6315_PMIC_REG_BASE+0x38c)
+#define MT6315_OTP_CON1                   (MT6315_PMIC_REG_BASE+0x38d)
+#define MT6315_OTP_CON2                   (MT6315_PMIC_REG_BASE+0x38e)
+#define MT6315_OTP_CON3                   (MT6315_PMIC_REG_BASE+0x38f)
+#define MT6315_OTP_CON4                   (MT6315_PMIC_REG_BASE+0x390)
+#define MT6315_OTP_CON5                   (MT6315_PMIC_REG_BASE+0x391)
+#define MT6315_OTP_CON6                   (MT6315_PMIC_REG_BASE+0x392)
+#define MT6315_OTP_CON7                   (MT6315_PMIC_REG_BASE+0x393)
+#define MT6315_OTP_CON8                   (MT6315_PMIC_REG_BASE+0x394)
+#define MT6315_OTP_CON9                   (MT6315_PMIC_REG_BASE+0x395)
+#define MT6315_OTP_CON10                  (MT6315_PMIC_REG_BASE+0x396)
+#define MT6315_OTP_CON11                  (MT6315_PMIC_REG_BASE+0x397)
+#define MT6315_OTP_CON12                  (MT6315_PMIC_REG_BASE+0x398)
+#define MT6315_OTP_CON13                  (MT6315_PMIC_REG_BASE+0x399)
+#define MT6315_OTP_CON14                  (MT6315_PMIC_REG_BASE+0x39a)
+#define MT6315_OTP_CON15                  (MT6315_PMIC_REG_BASE+0x39b)
+#define MT6315_OTP_CON16                  (MT6315_PMIC_REG_BASE+0x39c)
+#define MT6315_OTP_CON17                  (MT6315_PMIC_REG_BASE+0x39d)
+#define MT6315_OTP_CON18                  (MT6315_PMIC_REG_BASE+0x39e)
+#define MT6315_TOP_TMA_KEY                (MT6315_PMIC_REG_BASE+0x39f)
+#define MT6315_TOP_TMA_KEY_H              (MT6315_PMIC_REG_BASE+0x3a0)
+#define MT6315_TOP_ANA_KEY                (MT6315_PMIC_REG_BASE+0x3a1)
+#define MT6315_TOP_ANA_KEY_H              (MT6315_PMIC_REG_BASE+0x3a2)
+#define MT6315_TOP_MDB_CONF0              (MT6315_PMIC_REG_BASE+0x3a3)
+#define MT6315_TOP_MDB_CONF0_H            (MT6315_PMIC_REG_BASE+0x3a4)
+#define MT6315_TOP_MDB_CONF1              (MT6315_PMIC_REG_BASE+0x3a5)
+#define MT6315_TOP_MDB_CONF1_H            (MT6315_PMIC_REG_BASE+0x3a6)
+#define MT6315_TOP_MDB_CONF2              (MT6315_PMIC_REG_BASE+0x3a7)
+#define MT6315_TOP_DIG_WPK                (MT6315_PMIC_REG_BASE+0x3a8)
+#define MT6315_TOP_DIG_WPK_H              (MT6315_PMIC_REG_BASE+0x3a9)
+#define MT6315_SPMI_EXT_ADDR0             (MT6315_PMIC_REG_BASE+0x3aa)
+#define MT6315_SPMI_EXT_ADDR0_H           (MT6315_PMIC_REG_BASE+0x3ab)
+#define MT6315_SPMI_EXT_ADDR1             (MT6315_PMIC_REG_BASE+0x3ac)
+#define MT6315_SPMI_EXT_ADDR2             (MT6315_PMIC_REG_BASE+0x3ad)
+#define MT6315_SPMI_EXT_ADDR2_H           (MT6315_PMIC_REG_BASE+0x3ae)
+#define MT6315_SPMI_RCS_FUN0              (MT6315_PMIC_REG_BASE+0x3af)
+#define MT6315_SPMI_RCS_FUN1              (MT6315_PMIC_REG_BASE+0x3b0)
+#define MT6315_SPMI_RCS_FUN2              (MT6315_PMIC_REG_BASE+0x3b1)
+#define MT6315_SPMI_WR_ADDR               (MT6315_PMIC_REG_BASE+0x3b2)
+#define MT6315_SPMI_WR_ADDR_H             (MT6315_PMIC_REG_BASE+0x3b3)
+#define MT6315_SPMI_DEBUG_ADDR0           (MT6315_PMIC_REG_BASE+0x3b4)
+#define MT6315_SPMI_DEBUG_ADDR0_H         (MT6315_PMIC_REG_BASE+0x3b5)
+#define MT6315_SPMI_DEBUG_DATA0           (MT6315_PMIC_REG_BASE+0x3b6)
+#define MT6315_SPMI_DEBUG_CMD0            (MT6315_PMIC_REG_BASE+0x3b7)
+#define MT6315_SPMI_DEBUG_ADDR1           (MT6315_PMIC_REG_BASE+0x3b8)
+#define MT6315_SPMI_DEBUG_ADDR1_H         (MT6315_PMIC_REG_BASE+0x3b9)
+#define MT6315_SPMI_DEBUG_DATA1           (MT6315_PMIC_REG_BASE+0x3ba)
+#define MT6315_SPMI_DEBUG_CMD1            (MT6315_PMIC_REG_BASE+0x3bb)
+#define MT6315_SPMI_DEBUG_ADDR2           (MT6315_PMIC_REG_BASE+0x3bc)
+#define MT6315_SPMI_DEBUG_ADDR2_H         (MT6315_PMIC_REG_BASE+0x3bd)
+#define MT6315_SPMI_DEBUG_DATA2           (MT6315_PMIC_REG_BASE+0x3be)
+#define MT6315_SPMI_DEBUG_CMD2            (MT6315_PMIC_REG_BASE+0x3bf)
+#define MT6315_SPMI_DEBUG_ADDR3           (MT6315_PMIC_REG_BASE+0x3c0)
+#define MT6315_SPMI_DEBUG_ADDR3_H         (MT6315_PMIC_REG_BASE+0x3c1)
+#define MT6315_SPMI_DEBUG_DATA3           (MT6315_PMIC_REG_BASE+0x3c2)
+#define MT6315_SPMI_DEBUG_CMD3            (MT6315_PMIC_REG_BASE+0x3c3)
+#define MT6315_SPMI_PTRY_ERR0             (MT6315_PMIC_REG_BASE+0x3c4)
+#define MT6315_SPMI_PTRY_ERR1             (MT6315_PMIC_REG_BASE+0x3c5)
+#define MT6315_SPMI_PTRY_ERR1_H           (MT6315_PMIC_REG_BASE+0x3c6)
+#define MT6315_SPMI_PTRY_ERR2             (MT6315_PMIC_REG_BASE+0x3c7)
+#define MT6315_SPMI_PTRY_ERR3             (MT6315_PMIC_REG_BASE+0x3c8)
+#define MT6315_SPMI_PTRY_ERR3_H           (MT6315_PMIC_REG_BASE+0x3c9)
+#define MT6315_SPMI_PTRY_ERR4             (MT6315_PMIC_REG_BASE+0x3ca)
+#define MT6315_SPMI_PTRY_ERR5             (MT6315_PMIC_REG_BASE+0x3cb)
+#define MT6315_SPMI_PTRY_ERR5_H           (MT6315_PMIC_REG_BASE+0x3cc)
+#define MT6315_SPMI_PTRY_ERR6             (MT6315_PMIC_REG_BASE+0x3cd)
+#define MT6315_SPMI_PTRY_ERR7             (MT6315_PMIC_REG_BASE+0x3ce)
+#define MT6315_SPMI_PTRY_ERR7_H           (MT6315_PMIC_REG_BASE+0x3cf)
+#define MT6315_PLT0_ELR_NUM               (MT6315_PMIC_REG_BASE+0x3d0)
+#define MT6315_PLT0_ELR0                  (MT6315_PMIC_REG_BASE+0x3d1)
+#define MT6315_PLT0_ELR1                  (MT6315_PMIC_REG_BASE+0x3d2)
+#define MT6315_PSC_TOP_ID_ANA             (MT6315_PMIC_REG_BASE+0x900)
+#define MT6315_PSC_TOP_ID_DIG             (MT6315_PMIC_REG_BASE+0x901)
+#define MT6315_PSC_TOP_REV0               (MT6315_PMIC_REG_BASE+0x902)
+#define MT6315_PSC_TOP_REV1               (MT6315_PMIC_REG_BASE+0x903)
+#define MT6315_PSC_TOP_DBI0               (MT6315_PMIC_REG_BASE+0x904)
+#define MT6315_PSC_TOP_DBI1               (MT6315_PMIC_REG_BASE+0x905)
+#define MT6315_PSC_TOP_DXI                (MT6315_PMIC_REG_BASE+0x906)
+#define MT6315_PSC_TPM0                   (MT6315_PMIC_REG_BASE+0x907)
+#define MT6315_PSC_TPM1                   (MT6315_PMIC_REG_BASE+0x908)
+#define MT6315_PSC_TPM2                   (MT6315_PMIC_REG_BASE+0x909)
+#define MT6315_PSC_TOP_RSTCTL             (MT6315_PMIC_REG_BASE+0x90a)
+#define MT6315_PSC_TOP_MON_CTL            (MT6315_PMIC_REG_BASE+0x90b)
+#define MT6315_PSEQ_ID_ANA                (MT6315_PMIC_REG_BASE+0x980)
+#define MT6315_PSEQ_ID_DIG                (MT6315_PMIC_REG_BASE+0x981)
+#define MT6315_PSEQ_REV0                  (MT6315_PMIC_REG_BASE+0x982)
+#define MT6315_PSEQ_REV1                  (MT6315_PMIC_REG_BASE+0x983)
+#define MT6315_PSEQ_DBI0                  (MT6315_PMIC_REG_BASE+0x984)
+#define MT6315_PSEQ_DBI1                  (MT6315_PMIC_REG_BASE+0x985)
+#define MT6315_PSEQ_DXI                   (MT6315_PMIC_REG_BASE+0x986)
+#define MT6315_PPCCTL                     (MT6315_PMIC_REG_BASE+0x987)
+#define MT6315_STRUP_CON0                 (MT6315_PMIC_REG_BASE+0x988)
+#define MT6315_STRUP_CON1                 (MT6315_PMIC_REG_BASE+0x989)
+#define MT6315_STRUP_PGENB0               (MT6315_PMIC_REG_BASE+0x98a)
+#define MT6315_STRUP_OCENB0               (MT6315_PMIC_REG_BASE+0x98b)
+#define MT6315_BUCK_KEYPWR                (MT6315_PMIC_REG_BASE+0x98c)
+#define MT6315_PPCTST0                    (MT6315_PMIC_REG_BASE+0x98d)
+#define MT6315_PPCCTL2                    (MT6315_PMIC_REG_BASE+0x98e)
+#define MT6315_STRUP_CON4                 (MT6315_PMIC_REG_BASE+0x98f)
+#define MT6315_STRUP_CON5                 (MT6315_PMIC_REG_BASE+0x990)
+#define MT6315_STRUP_CON6                 (MT6315_PMIC_REG_BASE+0x991)
+#define MT6315_CPSWKEY                    (MT6315_PMIC_REG_BASE+0x992)
+#define MT6315_CPSWKEY_H                  (MT6315_PMIC_REG_BASE+0x993)
+#define MT6315_STS_PDN_ENCODE             (MT6315_PMIC_REG_BASE+0x994)
+#define MT6315_PSEQ_ELR_NUM               (MT6315_PMIC_REG_BASE+0x995)
+#define MT6315_PSEQ_ELR0                  (MT6315_PMIC_REG_BASE+0x996)
+#define MT6315_PSEQ_ELR1                  (MT6315_PMIC_REG_BASE+0x997)
+#define MT6315_PSEQ_ELR2                  (MT6315_PMIC_REG_BASE+0x998)
+#define MT6315_PSEQ_ELR3                  (MT6315_PMIC_REG_BASE+0x999)
+#define MT6315_PSEQ_ELR4                  (MT6315_PMIC_REG_BASE+0x99a)
+#define MT6315_PSEQ_ELR5                  (MT6315_PMIC_REG_BASE+0x99b)
+#define MT6315_CPSUSA_ELR0                (MT6315_PMIC_REG_BASE+0x99c)
+#define MT6315_CPSUSA_ELR1                (MT6315_PMIC_REG_BASE+0x99d)
+#define MT6315_CPSUSA_ELR2                (MT6315_PMIC_REG_BASE+0x99e)
+#define MT6315_CPSUSA_ELR3                (MT6315_PMIC_REG_BASE+0x99f)
+#define MT6315_CPSDSA_ELR0                (MT6315_PMIC_REG_BASE+0x9a0)
+#define MT6315_CPSDSA_ELR1                (MT6315_PMIC_REG_BASE+0x9a1)
+#define MT6315_CPSDSA_ELR2                (MT6315_PMIC_REG_BASE+0x9a2)
+#define MT6315_CPSDSA_ELR3                (MT6315_PMIC_REG_BASE+0x9a3)
+#define MT6315_STRUP_ANA0_ANA_ID          (MT6315_PMIC_REG_BASE+0xa00)
+#define MT6315_STRUP_ANA0_DIG_ID          (MT6315_PMIC_REG_BASE+0xa01)
+#define MT6315_STRUP_ANA0_DSN_REV0        (MT6315_PMIC_REG_BASE+0xa02)
+#define MT6315_STRUP_ANA0_DSN_REV1        (MT6315_PMIC_REG_BASE+0xa03)
+#define MT6315_STRUP_ANA0_DBI0            (MT6315_PMIC_REG_BASE+0xa04)
+#define MT6315_STRUP_ANA0_DBI1            (MT6315_PMIC_REG_BASE+0xa05)
+#define MT6315_STRUP_ANA0_DXI             (MT6315_PMIC_REG_BASE+0xa06)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON0 (MT6315_PMIC_REG_BASE+0xa07)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON1 (MT6315_PMIC_REG_BASE+0xa08)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON2 (MT6315_PMIC_REG_BASE+0xa09)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON3 (MT6315_PMIC_REG_BASE+0xa0a)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON4 (MT6315_PMIC_REG_BASE+0xa0b)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON5 (MT6315_PMIC_REG_BASE+0xa0c)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON6 (MT6315_PMIC_REG_BASE+0xa0d)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON7 (MT6315_PMIC_REG_BASE+0xa0e)
+#define MT6315_STRUP_TOP_A10876A_ANA_CON8 (MT6315_PMIC_REG_BASE+0xa0f)
+#define MT6315_STRUP_ANA0_ELR_NUM         (MT6315_PMIC_REG_BASE+0xa10)
+#define MT6315_STRUP_TOP_A10876A_ELR_0    (MT6315_PMIC_REG_BASE+0xa11)
+#define MT6315_STRUP_TOP_A10876A_ELR_1    (MT6315_PMIC_REG_BASE+0xa12)
+#define MT6315_STRUP_TOP_A10876A_ELR_2    (MT6315_PMIC_REG_BASE+0xa13)
+#define MT6315_STRUP_TOP_A10876A_ELR_3    (MT6315_PMIC_REG_BASE+0xa14)
+#define MT6315_STRUP_TOP_A10876A_ELR_4    (MT6315_PMIC_REG_BASE+0xa15)
+#define MT6315_STRUP_TOP_A10876A_ELR_5    (MT6315_PMIC_REG_BASE+0xa16)
+#define MT6315_STRUP_TOP_A10876A_ELR_6    (MT6315_PMIC_REG_BASE+0xa17)
+#define MT6315_STRUP_TOP_A10876A_ELR_7    (MT6315_PMIC_REG_BASE+0xa18)
+#define MT6315_STRUP_TOP_A10876A_ELR_8    (MT6315_PMIC_REG_BASE+0xa19)
+#define MT6315_STRUP_TOP_A10876A_ELR_9    (MT6315_PMIC_REG_BASE+0xa1a)
+#define MT6315_BUCK_TOP_ANA_ID            (MT6315_PMIC_REG_BASE+0x1400)
+#define MT6315_BUCK_TOP_DIG_ID            (MT6315_PMIC_REG_BASE+0x1401)
+#define MT6315_BUCK_TOP_REV0              (MT6315_PMIC_REG_BASE+0x1402)
+#define MT6315_BUCK_TOP_REV1              (MT6315_PMIC_REG_BASE+0x1403)
+#define MT6315_BUCK_TOP_DBI0              (MT6315_PMIC_REG_BASE+0x1404)
+#define MT6315_BUCK_TOP_DBI1              (MT6315_PMIC_REG_BASE+0x1405)
+#define MT6315_BUCK_TOP_DXI               (MT6315_PMIC_REG_BASE+0x1406)
+#define MT6315_BUCK_TOP_PAM0              (MT6315_PMIC_REG_BASE+0x1407)
+#define MT6315_BUCK_TOP_PAM1              (MT6315_PMIC_REG_BASE+0x1408)
+#define MT6315_BUCK_TOP_PAM2              (MT6315_PMIC_REG_BASE+0x1409)
+#define MT6315_BUCK_TOP_PAM3              (MT6315_PMIC_REG_BASE+0x140a)
+#define MT6315_BUCK_TOP_CLK_CON0          (MT6315_PMIC_REG_BASE+0x140b)
+#define MT6315_BUCK_TOP_CLK_CON0_SET      (MT6315_PMIC_REG_BASE+0x140c)
+#define MT6315_BUCK_TOP_CLK_CON0_CLR      (MT6315_PMIC_REG_BASE+0x140d)
+#define MT6315_BUCK_TOP_CLK_HWEN_CON0     (MT6315_PMIC_REG_BASE+0x140e)
+#define MT6315_BUCK_TOP_CLK_HWEN_CON0_SET (MT6315_PMIC_REG_BASE+0x140f)
+#define MT6315_BUCK_TOP_CLK_HWEN_CON0_CLR (MT6315_PMIC_REG_BASE+0x1410)
+#define MT6315_BUCK_TOP_CLK_DCM_CON       (MT6315_PMIC_REG_BASE+0x1411)
+#define MT6315_BUCK_TOP_SYNC_CON          (MT6315_PMIC_REG_BASE+0x1412)
+#define MT6315_BUCK_TOP_STB_CON           (MT6315_PMIC_REG_BASE+0x1413)
+#define MT6315_BUCK_TOP_VGP2_MINFREQ_CON0 (MT6315_PMIC_REG_BASE+0x1414)
+#define MT6315_BUCK_TOP_VGP2_MINFREQ_CON1 (MT6315_PMIC_REG_BASE+0x1415)
+#define MT6315_BUCK_TOP_OC_CON0           (MT6315_PMIC_REG_BASE+0x1416)
+#define MT6315_BUCK_TOP_KEY_PROT0         (MT6315_PMIC_REG_BASE+0x1417)
+#define MT6315_BUCK_TOP_KEY_PROT1         (MT6315_PMIC_REG_BASE+0x1418)
+#define MT6315_BUCK_TOP_WDTDBG0           (MT6315_PMIC_REG_BASE+0x1419)
+#define MT6315_BUCK_TOP_WDTDBG1           (MT6315_PMIC_REG_BASE+0x141a)
+#define MT6315_BUCK_TOP_WDTDBG2           (MT6315_PMIC_REG_BASE+0x141b)
+#define MT6315_BUCK_TOP_WDTDBG3           (MT6315_PMIC_REG_BASE+0x141c)
+#define MT6315_BUCK_TOP_WDTDBG4           (MT6315_PMIC_REG_BASE+0x141d)
+#define MT6315_BUCK_TOP_WDTDBG5           (MT6315_PMIC_REG_BASE+0x141e)
+#define MT6315_BUCK_TOP_WDTDBG6           (MT6315_PMIC_REG_BASE+0x141f)
+#define MT6315_BUCK_TOP_WDTDBG7           (MT6315_PMIC_REG_BASE+0x1420)
+#define MT6315_BUCK_TOP_DBG               (MT6315_PMIC_REG_BASE+0x1421)
+#define MT6315_BUCK_TOP_CON0              (MT6315_PMIC_REG_BASE+0x1440)
+#define MT6315_BUCK_TOP_CON0_SET          (MT6315_PMIC_REG_BASE+0x1441)
+#define MT6315_BUCK_TOP_CON0_CLR          (MT6315_PMIC_REG_BASE+0x1442)
+#define MT6315_BUCK_TOP_CON1              (MT6315_PMIC_REG_BASE+0x1443)
+#define MT6315_BUCK_TOP_CON1_SET          (MT6315_PMIC_REG_BASE+0x1444)
+#define MT6315_BUCK_TOP_CON1_CLR          (MT6315_PMIC_REG_BASE+0x1445)
+#define MT6315_BUCK_TOP_ELR_NUM           (MT6315_PMIC_REG_BASE+0x1448)
+#define MT6315_BUCK_TOP_ELR0              (MT6315_PMIC_REG_BASE+0x1449)
+#define MT6315_BUCK_TOP_ELR1              (MT6315_PMIC_REG_BASE+0x144a)
+#define MT6315_BUCK_TOP_ELR2              (MT6315_PMIC_REG_BASE+0x144b)
+#define MT6315_BUCK_TOP_ELR3              (MT6315_PMIC_REG_BASE+0x144c)
+#define MT6315_BUCK_TOP_ELR4              (MT6315_PMIC_REG_BASE+0x144d)
+#define MT6315_BUCK_TOP_ELR5              (MT6315_PMIC_REG_BASE+0x144e)
+#define MT6315_BUCK_TOP_ELR6              (MT6315_PMIC_REG_BASE+0x144f)
+#define MT6315_BUCK_TOP_ELR7              (MT6315_PMIC_REG_BASE+0x1450)
+#define MT6315_BUCK_TOP_ELR8              (MT6315_PMIC_REG_BASE+0x1451)
+#define MT6315_BUCK_TOP_ELR9              (MT6315_PMIC_REG_BASE+0x1452)
+#define MT6315_BUCK_TOP_ELR10             (MT6315_PMIC_REG_BASE+0x1453)
+#define MT6315_BUCK_TOP_ELR11             (MT6315_PMIC_REG_BASE+0x1454)
+#define MT6315_BUCK_TOP_ELR12             (MT6315_PMIC_REG_BASE+0x1455)
+#define MT6315_BUCK_TOP_ELR13             (MT6315_PMIC_REG_BASE+0x1456)
+#define MT6315_BUCK_TOP_ELR14             (MT6315_PMIC_REG_BASE+0x1457)
+#define MT6315_BUCK_TOP_ELR15             (MT6315_PMIC_REG_BASE+0x1458)
+#define MT6315_BUCK_VBUCK1_ANA_ID         (MT6315_PMIC_REG_BASE+0x1480)
+#define MT6315_BUCK_VBUCK1_DIG_ID         (MT6315_PMIC_REG_BASE+0x1481)
+#define MT6315_BUCK_VBUCK1_REV0           (MT6315_PMIC_REG_BASE+0x1482)
+#define MT6315_BUCK_VBUCK1_REV1           (MT6315_PMIC_REG_BASE+0x1483)
+#define MT6315_BUCK_VBUCK1_DBI0           (MT6315_PMIC_REG_BASE+0x1484)
+#define MT6315_BUCK_VBUCK1_DBI1           (MT6315_PMIC_REG_BASE+0x1485)
+#define MT6315_BUCK_VBUCK1_DXI            (MT6315_PMIC_REG_BASE+0x1486)
+#define MT6315_BUCK_VBUCK1_CON1           (MT6315_PMIC_REG_BASE+0x1487)
+#define MT6315_BUCK_VBUCK1_CON2           (MT6315_PMIC_REG_BASE+0x1488)
+#define MT6315_BUCK_VBUCK1_SLP_CON        (MT6315_PMIC_REG_BASE+0x1489)
+#define MT6315_BUCK_VBUCK1_DVS_CON        (MT6315_PMIC_REG_BASE+0x148a)
+#define MT6315_BUCK_VBUCK1_CFG0           (MT6315_PMIC_REG_BASE+0x148b)
+#define MT6315_BUCK_VBUCK1_CFG1           (MT6315_PMIC_REG_BASE+0x148c)
+#define MT6315_BUCK_VBUCK1_OP_EN_0        (MT6315_PMIC_REG_BASE+0x148d)
+#define MT6315_BUCK_VBUCK1_OP_EN_0_SET    (MT6315_PMIC_REG_BASE+0x148e)
+#define MT6315_BUCK_VBUCK1_OP_EN_0_CLR    (MT6315_PMIC_REG_BASE+0x148f)
+#define MT6315_BUCK_VBUCK1_OP_EN_1        (MT6315_PMIC_REG_BASE+0x1490)
+#define MT6315_BUCK_VBUCK1_OP_EN_1_SET    (MT6315_PMIC_REG_BASE+0x1491)
+#define MT6315_BUCK_VBUCK1_OP_EN_1_CLR    (MT6315_PMIC_REG_BASE+0x1492)
+#define MT6315_BUCK_VBUCK1_OP_CFG_0       (MT6315_PMIC_REG_BASE+0x1493)
+#define MT6315_BUCK_VBUCK1_OP_CFG_0_SET   (MT6315_PMIC_REG_BASE+0x1494)
+#define MT6315_BUCK_VBUCK1_OP_CFG_0_CLR   (MT6315_PMIC_REG_BASE+0x1495)
+#define MT6315_BUCK_VBUCK1_OP_MODE_0      (MT6315_PMIC_REG_BASE+0x1496)
+#define MT6315_BUCK_VBUCK1_OP_MODE_0_SET  (MT6315_PMIC_REG_BASE+0x1497)
+#define MT6315_BUCK_VBUCK1_OP_MODE_0_CLR  (MT6315_PMIC_REG_BASE+0x1498)
+#define MT6315_BUCK_VBUCK1_DBG0           (MT6315_PMIC_REG_BASE+0x1499)
+#define MT6315_BUCK_VBUCK1_DBG1           (MT6315_PMIC_REG_BASE+0x149a)
+#define MT6315_BUCK_VBUCK1_DBG2           (MT6315_PMIC_REG_BASE+0x149b)
+#define MT6315_BUCK_VBUCK1_DBG3           (MT6315_PMIC_REG_BASE+0x149c)
+#define MT6315_BUCK_VBUCK1_DBG4           (MT6315_PMIC_REG_BASE+0x149d)
+#define MT6315_BUCK_VBUCK1_DBG5           (MT6315_PMIC_REG_BASE+0x149e)
+#define MT6315_BUCK_VBUCK1_STALL_TRACK0   (MT6315_PMIC_REG_BASE+0x149f)
+#define MT6315_BUCK_VBUCK2_ANA_ID         (MT6315_PMIC_REG_BASE+0x1500)
+#define MT6315_BUCK_VBUCK2_DIG_ID         (MT6315_PMIC_REG_BASE+0x1501)
+#define MT6315_BUCK_VBUCK2_REV0           (MT6315_PMIC_REG_BASE+0x1502)
+#define MT6315_BUCK_VBUCK2_REV1           (MT6315_PMIC_REG_BASE+0x1503)
+#define MT6315_BUCK_VBUCK2_DBI0           (MT6315_PMIC_REG_BASE+0x1504)
+#define MT6315_BUCK_VBUCK2_DBI1           (MT6315_PMIC_REG_BASE+0x1505)
+#define MT6315_BUCK_VBUCK2_DXI            (MT6315_PMIC_REG_BASE+0x1506)
+#define MT6315_BUCK_VBUCK2_CON1           (MT6315_PMIC_REG_BASE+0x1507)
+#define MT6315_BUCK_VBUCK2_CON2           (MT6315_PMIC_REG_BASE+0x1508)
+#define MT6315_BUCK_VBUCK2_SLP_CON        (MT6315_PMIC_REG_BASE+0x1509)
+#define MT6315_BUCK_VBUCK2_DVS_CON        (MT6315_PMIC_REG_BASE+0x150a)
+#define MT6315_BUCK_VBUCK2_CFG0           (MT6315_PMIC_REG_BASE+0x150b)
+#define MT6315_BUCK_VBUCK2_CFG1           (MT6315_PMIC_REG_BASE+0x150c)
+#define MT6315_BUCK_VBUCK2_OP_EN_0        (MT6315_PMIC_REG_BASE+0x150d)
+#define MT6315_BUCK_VBUCK2_OP_EN_0_SET    (MT6315_PMIC_REG_BASE+0x150e)
+#define MT6315_BUCK_VBUCK2_OP_EN_0_CLR    (MT6315_PMIC_REG_BASE+0x150f)
+#define MT6315_BUCK_VBUCK2_OP_EN_1        (MT6315_PMIC_REG_BASE+0x1510)
+#define MT6315_BUCK_VBUCK2_OP_EN_1_SET    (MT6315_PMIC_REG_BASE+0x1511)
+#define MT6315_BUCK_VBUCK2_OP_EN_1_CLR    (MT6315_PMIC_REG_BASE+0x1512)
+#define MT6315_BUCK_VBUCK2_OP_CFG_0       (MT6315_PMIC_REG_BASE+0x1513)
+#define MT6315_BUCK_VBUCK2_OP_CFG_0_SET   (MT6315_PMIC_REG_BASE+0x1514)
+#define MT6315_BUCK_VBUCK2_OP_CFG_0_CLR   (MT6315_PMIC_REG_BASE+0x1515)
+#define MT6315_BUCK_VBUCK2_OP_MODE_0      (MT6315_PMIC_REG_BASE+0x1516)
+#define MT6315_BUCK_VBUCK2_OP_MODE_0_SET  (MT6315_PMIC_REG_BASE+0x1517)
+#define MT6315_BUCK_VBUCK2_OP_MODE_0_CLR  (MT6315_PMIC_REG_BASE+0x1518)
+#define MT6315_BUCK_VBUCK2_DBG0           (MT6315_PMIC_REG_BASE+0x1519)
+#define MT6315_BUCK_VBUCK2_DBG1           (MT6315_PMIC_REG_BASE+0x151a)
+#define MT6315_BUCK_VBUCK2_DBG2           (MT6315_PMIC_REG_BASE+0x151b)
+#define MT6315_BUCK_VBUCK2_DBG3           (MT6315_PMIC_REG_BASE+0x151c)
+#define MT6315_BUCK_VBUCK2_DBG4           (MT6315_PMIC_REG_BASE+0x151d)
+#define MT6315_BUCK_VBUCK2_DBG5           (MT6315_PMIC_REG_BASE+0x151e)
+#define MT6315_BUCK_VBUCK2_STALL_TRACK0   (MT6315_PMIC_REG_BASE+0x151f)
+#define MT6315_BUCK_VBUCK3_ANA_ID         (MT6315_PMIC_REG_BASE+0x1580)
+#define MT6315_BUCK_VBUCK3_DIG_ID         (MT6315_PMIC_REG_BASE+0x1581)
+#define MT6315_BUCK_VBUCK3_REV0           (MT6315_PMIC_REG_BASE+0x1582)
+#define MT6315_BUCK_VBUCK3_REV1           (MT6315_PMIC_REG_BASE+0x1583)
+#define MT6315_BUCK_VBUCK3_DBI0           (MT6315_PMIC_REG_BASE+0x1584)
+#define MT6315_BUCK_VBUCK3_DBI1           (MT6315_PMIC_REG_BASE+0x1585)
+#define MT6315_BUCK_VBUCK3_DXI            (MT6315_PMIC_REG_BASE+0x1586)
+#define MT6315_BUCK_VBUCK3_CON1           (MT6315_PMIC_REG_BASE+0x1587)
+#define MT6315_BUCK_VBUCK3_CON2           (MT6315_PMIC_REG_BASE+0x1588)
+#define MT6315_BUCK_VBUCK3_SLP_CON        (MT6315_PMIC_REG_BASE+0x1589)
+#define MT6315_BUCK_VBUCK3_DVS_CON        (MT6315_PMIC_REG_BASE+0x158a)
+#define MT6315_BUCK_VBUCK3_CFG0           (MT6315_PMIC_REG_BASE+0x158b)
+#define MT6315_BUCK_VBUCK3_CFG1           (MT6315_PMIC_REG_BASE+0x158c)
+#define MT6315_BUCK_VBUCK3_OP_EN_0        (MT6315_PMIC_REG_BASE+0x158d)
+#define MT6315_BUCK_VBUCK3_OP_EN_0_SET    (MT6315_PMIC_REG_BASE+0x158e)
+#define MT6315_BUCK_VBUCK3_OP_EN_0_CLR    (MT6315_PMIC_REG_BASE+0x158f)
+#define MT6315_BUCK_VBUCK3_OP_EN_1        (MT6315_PMIC_REG_BASE+0x1590)
+#define MT6315_BUCK_VBUCK3_OP_EN_1_SET    (MT6315_PMIC_REG_BASE+0x1591)
+#define MT6315_BUCK_VBUCK3_OP_EN_1_CLR    (MT6315_PMIC_REG_BASE+0x1592)
+#define MT6315_BUCK_VBUCK3_OP_CFG_0       (MT6315_PMIC_REG_BASE+0x1593)
+#define MT6315_BUCK_VBUCK3_OP_CFG_0_SET   (MT6315_PMIC_REG_BASE+0x1594)
+#define MT6315_BUCK_VBUCK3_OP_CFG_0_CLR   (MT6315_PMIC_REG_BASE+0x1595)
+#define MT6315_BUCK_VBUCK3_OP_MODE_0      (MT6315_PMIC_REG_BASE+0x1596)
+#define MT6315_BUCK_VBUCK3_OP_MODE_0_SET  (MT6315_PMIC_REG_BASE+0x1597)
+#define MT6315_BUCK_VBUCK3_OP_MODE_0_CLR  (MT6315_PMIC_REG_BASE+0x1598)
+#define MT6315_BUCK_VBUCK3_DBG0           (MT6315_PMIC_REG_BASE+0x1599)
+#define MT6315_BUCK_VBUCK3_DBG1           (MT6315_PMIC_REG_BASE+0x159a)
+#define MT6315_BUCK_VBUCK3_DBG2           (MT6315_PMIC_REG_BASE+0x159b)
+#define MT6315_BUCK_VBUCK3_DBG3           (MT6315_PMIC_REG_BASE+0x159c)
+#define MT6315_BUCK_VBUCK3_DBG4           (MT6315_PMIC_REG_BASE+0x159d)
+#define MT6315_BUCK_VBUCK3_DBG5           (MT6315_PMIC_REG_BASE+0x159e)
+#define MT6315_BUCK_VBUCK3_TRACK0         (MT6315_PMIC_REG_BASE+0x159f)
+#define MT6315_BUCK_VBUCK3_TRACK1         (MT6315_PMIC_REG_BASE+0x15a0)
+#define MT6315_BUCK_VBUCK3_TRACK2         (MT6315_PMIC_REG_BASE+0x15a1)
+#define MT6315_BUCK_VBUCK3_TRACK3         (MT6315_PMIC_REG_BASE+0x15a2)
+#define MT6315_BUCK_VBUCK4_ANA_ID         (MT6315_PMIC_REG_BASE+0x1600)
+#define MT6315_BUCK_VBUCK4_DIG_ID         (MT6315_PMIC_REG_BASE+0x1601)
+#define MT6315_BUCK_VBUCK4_REV0           (MT6315_PMIC_REG_BASE+0x1602)
+#define MT6315_BUCK_VBUCK4_REV1           (MT6315_PMIC_REG_BASE+0x1603)
+#define MT6315_BUCK_VBUCK4_DBI0           (MT6315_PMIC_REG_BASE+0x1604)
+#define MT6315_BUCK_VBUCK4_DBI1           (MT6315_PMIC_REG_BASE+0x1605)
+#define MT6315_BUCK_VBUCK4_DXI            (MT6315_PMIC_REG_BASE+0x1606)
+#define MT6315_BUCK_VBUCK4_CON1           (MT6315_PMIC_REG_BASE+0x1607)
+#define MT6315_BUCK_VBUCK4_CON2           (MT6315_PMIC_REG_BASE+0x1608)
+#define MT6315_BUCK_VBUCK4_SLP_CON        (MT6315_PMIC_REG_BASE+0x1609)
+#define MT6315_BUCK_VBUCK4_DVS_CON        (MT6315_PMIC_REG_BASE+0x160a)
+#define MT6315_BUCK_VBUCK4_CFG0           (MT6315_PMIC_REG_BASE+0x160b)
+#define MT6315_BUCK_VBUCK4_CFG1           (MT6315_PMIC_REG_BASE+0x160c)
+#define MT6315_BUCK_VBUCK4_OP_EN_0        (MT6315_PMIC_REG_BASE+0x160d)
+#define MT6315_BUCK_VBUCK4_OP_EN_0_SET    (MT6315_PMIC_REG_BASE+0x160e)
+#define MT6315_BUCK_VBUCK4_OP_EN_0_CLR    (MT6315_PMIC_REG_BASE+0x160f)
+#define MT6315_BUCK_VBUCK4_OP_EN_1        (MT6315_PMIC_REG_BASE+0x1610)
+#define MT6315_BUCK_VBUCK4_OP_EN_1_SET    (MT6315_PMIC_REG_BASE+0x1611)
+#define MT6315_BUCK_VBUCK4_OP_EN_1_CLR    (MT6315_PMIC_REG_BASE+0x1612)
+#define MT6315_BUCK_VBUCK4_OP_CFG_0       (MT6315_PMIC_REG_BASE+0x1613)
+#define MT6315_BUCK_VBUCK4_OP_CFG_0_SET   (MT6315_PMIC_REG_BASE+0x1614)
+#define MT6315_BUCK_VBUCK4_OP_CFG_0_CLR   (MT6315_PMIC_REG_BASE+0x1615)
+#define MT6315_BUCK_VBUCK4_OP_MODE_0      (MT6315_PMIC_REG_BASE+0x1616)
+#define MT6315_BUCK_VBUCK4_OP_MODE_0_SET  (MT6315_PMIC_REG_BASE+0x1617)
+#define MT6315_BUCK_VBUCK4_OP_MODE_0_CLR  (MT6315_PMIC_REG_BASE+0x1618)
+#define MT6315_BUCK_VBUCK4_DBG0           (MT6315_PMIC_REG_BASE+0x1619)
+#define MT6315_BUCK_VBUCK4_DBG1           (MT6315_PMIC_REG_BASE+0x161a)
+#define MT6315_BUCK_VBUCK4_DBG2           (MT6315_PMIC_REG_BASE+0x161b)
+#define MT6315_BUCK_VBUCK4_DBG3           (MT6315_PMIC_REG_BASE+0x161c)
+#define MT6315_BUCK_VBUCK4_DBG4           (MT6315_PMIC_REG_BASE+0x161d)
+#define MT6315_BUCK_VBUCK4_DBG5           (MT6315_PMIC_REG_BASE+0x161e)
+#define MT6315_BUCK_VBUCK4_TRACK0         (MT6315_PMIC_REG_BASE+0x161f)
+#define MT6315_BUCK_VBUCK4_TRACK1         (MT6315_PMIC_REG_BASE+0x1620)
+#define MT6315_BUCK_VBUCK4_TRACK2         (MT6315_PMIC_REG_BASE+0x1621)
+#define MT6315_BUCK_VBUCK4_TRACK3         (MT6315_PMIC_REG_BASE+0x1622)
+#define MT6315_BUCK_ANA0_ANA_ID           (MT6315_PMIC_REG_BASE+0x1680)
+#define MT6315_BUCK_ANA0_DIG_ID           (MT6315_PMIC_REG_BASE+0x1681)
+#define MT6315_BUCK_ANA0_DSN_REV0         (MT6315_PMIC_REG_BASE+0x1682)
+#define MT6315_BUCK_ANA0_DSN_REV1         (MT6315_PMIC_REG_BASE+0x1683)
+#define MT6315_BUCK_ANA0_DBI0             (MT6315_PMIC_REG_BASE+0x1684)
+#define MT6315_BUCK_ANA0_DBI1             (MT6315_PMIC_REG_BASE+0x1685)
+#define MT6315_BUCK_ANA0_DXI              (MT6315_PMIC_REG_BASE+0x1686)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON0   (MT6315_PMIC_REG_BASE+0x1687)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON1   (MT6315_PMIC_REG_BASE+0x1688)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON2   (MT6315_PMIC_REG_BASE+0x1689)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON3   (MT6315_PMIC_REG_BASE+0x168a)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON4   (MT6315_PMIC_REG_BASE+0x168b)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON5   (MT6315_PMIC_REG_BASE+0x168c)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON6   (MT6315_PMIC_REG_BASE+0x168d)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON7   (MT6315_PMIC_REG_BASE+0x168e)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON8   (MT6315_PMIC_REG_BASE+0x168f)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON9   (MT6315_PMIC_REG_BASE+0x1690)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON10  (MT6315_PMIC_REG_BASE+0x1691)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON11  (MT6315_PMIC_REG_BASE+0x1692)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON12  (MT6315_PMIC_REG_BASE+0x1693)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON13  (MT6315_PMIC_REG_BASE+0x1694)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON14  (MT6315_PMIC_REG_BASE+0x1695)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON15  (MT6315_PMIC_REG_BASE+0x1696)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON16  (MT6315_PMIC_REG_BASE+0x1697)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON17  (MT6315_PMIC_REG_BASE+0x1698)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON18  (MT6315_PMIC_REG_BASE+0x1699)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON19  (MT6315_PMIC_REG_BASE+0x169a)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON20  (MT6315_PMIC_REG_BASE+0x169b)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON21  (MT6315_PMIC_REG_BASE+0x169c)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON22  (MT6315_PMIC_REG_BASE+0x169d)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON23  (MT6315_PMIC_REG_BASE+0x169e)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON24  (MT6315_PMIC_REG_BASE+0x169f)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON25  (MT6315_PMIC_REG_BASE+0x16a0)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON26  (MT6315_PMIC_REG_BASE+0x16a1)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON27  (MT6315_PMIC_REG_BASE+0x16a2)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON28  (MT6315_PMIC_REG_BASE+0x16a3)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON29  (MT6315_PMIC_REG_BASE+0x16a4)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON30  (MT6315_PMIC_REG_BASE+0x16a5)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON31  (MT6315_PMIC_REG_BASE+0x16a6)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON32  (MT6315_PMIC_REG_BASE+0x16a7)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON33  (MT6315_PMIC_REG_BASE+0x16a8)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON34  (MT6315_PMIC_REG_BASE+0x16a9)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON35  (MT6315_PMIC_REG_BASE+0x16aa)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON36  (MT6315_PMIC_REG_BASE+0x16ab)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON37  (MT6315_PMIC_REG_BASE+0x16ac)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON38  (MT6315_PMIC_REG_BASE+0x16ad)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON39  (MT6315_PMIC_REG_BASE+0x16ae)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON40  (MT6315_PMIC_REG_BASE+0x16af)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON41  (MT6315_PMIC_REG_BASE+0x16b0)
+#define MT6315_BUCK_TOP_4PHASE_ANA_CON42  (MT6315_PMIC_REG_BASE+0x16b1)
+#define MT6315_BUCK_ANA0_ELR_NUM          (MT6315_PMIC_REG_BASE+0x16b2)
+#define MT6315_BUCK_TOP_4PHASE_ELR_0      (MT6315_PMIC_REG_BASE+0x16b3)
+#define MT6315_BUCK_TOP_4PHASE_ELR_1      (MT6315_PMIC_REG_BASE+0x16b4)
+#define MT6315_BUCK_TOP_4PHASE_ELR_2      (MT6315_PMIC_REG_BASE+0x16b5)
+#define MT6315_BUCK_TOP_4PHASE_ELR_3      (MT6315_PMIC_REG_BASE+0x16b6)
+#define MT6315_BUCK_TOP_4PHASE_ELR_4      (MT6315_PMIC_REG_BASE+0x16b7)
+#define MT6315_BUCK_TOP_4PHASE_ELR_5      (MT6315_PMIC_REG_BASE+0x16b8)
+#define MT6315_BUCK_TOP_4PHASE_ELR_6      (MT6315_PMIC_REG_BASE+0x16b9)
+#define MT6315_BUCK_TOP_4PHASE_ELR_7      (MT6315_PMIC_REG_BASE+0x16ba)
+#define MT6315_BUCK_TOP_4PHASE_ELR_8      (MT6315_PMIC_REG_BASE+0x16bb)
+#define MT6315_BUCK_TOP_4PHASE_ELR_9      (MT6315_PMIC_REG_BASE+0x16bc)
+#define MT6315_BUCK_TOP_4PHASE_ELR_10     (MT6315_PMIC_REG_BASE+0x16bd)
+#define MT6315_BUCK_TOP_4PHASE_ELR_11     (MT6315_PMIC_REG_BASE+0x16be)
+#define MT6315_BUCK_TOP_4PHASE_ELR_12     (MT6315_PMIC_REG_BASE+0x16bf)
+#define MT6315_BUCK_TOP_4PHASE_ELR_13     (MT6315_PMIC_REG_BASE+0x16c0)
+#define MT6315_BUCK_TOP_4PHASE_ELR_14     (MT6315_PMIC_REG_BASE+0x16c1)
+#define MT6315_BUCK_TOP_4PHASE_ELR_15     (MT6315_PMIC_REG_BASE+0x16c2)
+#define MT6315_BUCK_TOP_4PHASE_ELR_16     (MT6315_PMIC_REG_BASE+0x16c3)
+#define MT6315_BUCK_TOP_4PHASE_ELR_17     (MT6315_PMIC_REG_BASE+0x16c4)
+#define MT6315_BUCK_TOP_4PHASE_ELR_18     (MT6315_PMIC_REG_BASE+0x16c5)
+#define MT6315_BUCK_TOP_4PHASE_ELR_19     (MT6315_PMIC_REG_BASE+0x16c6)
+#define MT6315_BUCK_TOP_4PHASE_ELR_20     (MT6315_PMIC_REG_BASE+0x16c7)
+#define MT6315_BUCK_TOP_4PHASE_ELR_21     (MT6315_PMIC_REG_BASE+0x16c8)
+#define MT6315_BUCK_TOP_4PHASE_ELR_22     (MT6315_PMIC_REG_BASE+0x16c9)
+#define MT6315_BUCK_TOP_4PHASE_ELR_23     (MT6315_PMIC_REG_BASE+0x16ca)
+#define MT6315_BUCK_TOP_4PHASE_ELR_24     (MT6315_PMIC_REG_BASE+0x16cb)
+#define MT6315_BUCK_TOP_4PHASE_ELR_25     (MT6315_PMIC_REG_BASE+0x16cc)
+#define MT6315_BUCK_TOP_4PHASE_ELR_26     (MT6315_PMIC_REG_BASE+0x16cd)
+#define MT6315_BUCK_TOP_4PHASE_ELR_27     (MT6315_PMIC_REG_BASE+0x16ce)
+#define MT6315_BUCK_TOP_4PHASE_ELR_28     (MT6315_PMIC_REG_BASE+0x16cf)
+#define MT6315_BUCK_TOP_4PHASE_ELR_29     (MT6315_PMIC_REG_BASE+0x16d0)
+//mask is HEX;  shift is Integer
+#define MT6315_PMIC_TOP0_ANA_ID_ADDR                        \
+	MT6315_TOP0_ID
+#define MT6315_PMIC_TOP0_ANA_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP0_ANA_ID_SHIFT                       0
+#define MT6315_PMIC_TOP0_DIG_ID_ADDR                        \
+	MT6315_TOP0_ID_H
+#define MT6315_PMIC_TOP0_DIG_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP0_DIG_ID_SHIFT                       0
+#define MT6315_PMIC_TOP0_ANA_MINOR_REV_ADDR                 \
+	MT6315_TOP0_REV0
+#define MT6315_PMIC_TOP0_ANA_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP0_ANA_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP0_ANA_MAJOR_REV_ADDR                 \
+	MT6315_TOP0_REV0
+#define MT6315_PMIC_TOP0_ANA_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP0_ANA_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP0_DIG_MINOR_REV_ADDR                 \
+	MT6315_TOP0_REV0_H
+#define MT6315_PMIC_TOP0_DIG_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP0_DIG_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP0_DIG_MAJOR_REV_ADDR                 \
+	MT6315_TOP0_REV0_H
+#define MT6315_PMIC_TOP0_DIG_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP0_DIG_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP0_DSN_CBS_ADDR                       \
+	MT6315_TOP0_DSN_DBI
+#define MT6315_PMIC_TOP0_DSN_CBS_MASK                       0x3
+#define MT6315_PMIC_TOP0_DSN_CBS_SHIFT                      0
+#define MT6315_PMIC_TOP0_DSN_BIX_ADDR                       \
+	MT6315_TOP0_DSN_DBI
+#define MT6315_PMIC_TOP0_DSN_BIX_MASK                       0x3
+#define MT6315_PMIC_TOP0_DSN_BIX_SHIFT                      2
+#define MT6315_PMIC_TOP0_DSN_ESP_ADDR                       \
+	MT6315_TOP0_DSN_DBI_H
+#define MT6315_PMIC_TOP0_DSN_ESP_MASK                       0xFF
+#define MT6315_PMIC_TOP0_DSN_ESP_SHIFT                      0
+#define MT6315_PMIC_TOP0_DSN_FPI_ADDR                       \
+	MT6315_TOP0_DSN_DXI
+#define MT6315_PMIC_TOP0_DSN_FPI_MASK                       0xFF
+#define MT6315_PMIC_TOP0_DSN_FPI_SHIFT                      0
+#define MT6315_PMIC_TOP0_DUMMY_ADDR                         \
+	MT6315_TOP0_DMY
+#define MT6315_PMIC_TOP0_DUMMY_MASK                         0xFF
+#define MT6315_PMIC_TOP0_DUMMY_SHIFT                        0
+#define MT6315_PMIC_HWCID_L_ADDR                            \
+	MT6315_HWCID_L
+#define MT6315_PMIC_HWCID_L_MASK                            0xFF
+#define MT6315_PMIC_HWCID_L_SHIFT                           0
+#define MT6315_PMIC_HWCID_H_ADDR                            \
+	MT6315_HWCID_H
+#define MT6315_PMIC_HWCID_H_MASK                            0xFF
+#define MT6315_PMIC_HWCID_H_SHIFT                           0
+#define MT6315_PMIC_SWCID_L_ADDR                            \
+	MT6315_SWCID_L
+#define MT6315_PMIC_SWCID_L_MASK                            0xFF
+#define MT6315_PMIC_SWCID_L_SHIFT                           0
+#define MT6315_PMIC_SWCID_H_ADDR                            \
+	MT6315_SWCID_H
+#define MT6315_PMIC_SWCID_H_MASK                            0xFF
+#define MT6315_PMIC_SWCID_H_SHIFT                           0
+#define MT6315_PMIC_STS_OVLO_ADDR                           \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_OVLO_MASK                           0x1
+#define MT6315_PMIC_STS_OVLO_SHIFT                          0
+#define MT6315_PMIC_STS_UVLO_ADDR                           \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_UVLO_MASK                           0x1
+#define MT6315_PMIC_STS_UVLO_SHIFT                          1
+#define MT6315_PMIC_STS_PGFAIL_ADDR                         \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_PGFAIL_MASK                         0x1
+#define MT6315_PMIC_STS_PGFAIL_SHIFT                        2
+#define MT6315_PMIC_STS_PSOC_ADDR                           \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_PSOC_MASK                           0x1
+#define MT6315_PMIC_STS_PSOC_SHIFT                          3
+#define MT6315_PMIC_STS_THRDN_ADDR                          \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_THRDN_MASK                          0x1
+#define MT6315_PMIC_STS_THRDN_SHIFT                         4
+#define MT6315_PMIC_STS_NORMOFF_ADDR                        \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_NORMOFF_MASK                        0x1
+#define MT6315_PMIC_STS_NORMOFF_SHIFT                       5
+#define MT6315_PMIC_STS_ABNORMOFF_ADDR                      \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_ABNORMOFF_MASK                      0x1
+#define MT6315_PMIC_STS_ABNORMOFF_SHIFT                     6
+#define MT6315_PMIC_STS_KEYPWR_ADDR                         \
+	MT6315_POFFSTS
+#define MT6315_PMIC_STS_KEYPWR_MASK                         0x1
+#define MT6315_PMIC_STS_KEYPWR_SHIFT                        7
+#define MT6315_PMIC_RG_POFFSTS_CLR_ADDR                     \
+	MT6315_PSTSCTL
+#define MT6315_PMIC_RG_POFFSTS_CLR_MASK                     0x1
+#define MT6315_PMIC_RG_POFFSTS_CLR_SHIFT                    0
+#define MT6315_PMIC_VBUCK1_PG_DEB_ADDR                      \
+	MT6315_PG_DEB_STS0
+#define MT6315_PMIC_VBUCK1_PG_DEB_MASK                      0x1
+#define MT6315_PMIC_VBUCK1_PG_DEB_SHIFT                     0
+#define MT6315_PMIC_VBUCK2_PG_DEB_ADDR                      \
+	MT6315_PG_DEB_STS0
+#define MT6315_PMIC_VBUCK2_PG_DEB_MASK                      0x1
+#define MT6315_PMIC_VBUCK2_PG_DEB_SHIFT                     1
+#define MT6315_PMIC_VBUCK3_PG_DEB_ADDR                      \
+	MT6315_PG_DEB_STS0
+#define MT6315_PMIC_VBUCK3_PG_DEB_MASK                      0x1
+#define MT6315_PMIC_VBUCK3_PG_DEB_SHIFT                     2
+#define MT6315_PMIC_VBUCK4_PG_DEB_ADDR                      \
+	MT6315_PG_DEB_STS0
+#define MT6315_PMIC_VBUCK4_PG_DEB_MASK                      0x1
+#define MT6315_PMIC_VBUCK4_PG_DEB_SHIFT                     3
+#define MT6315_PMIC_STRUP_VBUCK1_PG_STATUS_ADDR             \
+	MT6315_PG_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK1_PG_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK1_PG_STATUS_SHIFT            0
+#define MT6315_PMIC_STRUP_VBUCK2_PG_STATUS_ADDR             \
+	MT6315_PG_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK2_PG_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK2_PG_STATUS_SHIFT            1
+#define MT6315_PMIC_STRUP_VBUCK3_PG_STATUS_ADDR             \
+	MT6315_PG_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK3_PG_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK3_PG_STATUS_SHIFT            2
+#define MT6315_PMIC_STRUP_VBUCK4_PG_STATUS_ADDR             \
+	MT6315_PG_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK4_PG_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK4_PG_STATUS_SHIFT            3
+#define MT6315_PMIC_STRUP_VBUCK1_OC_STATUS_ADDR             \
+	MT6315_OC_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK1_OC_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK1_OC_STATUS_SHIFT            0
+#define MT6315_PMIC_STRUP_VBUCK2_OC_STATUS_ADDR             \
+	MT6315_OC_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK2_OC_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK2_OC_STATUS_SHIFT            1
+#define MT6315_PMIC_STRUP_VBUCK3_OC_STATUS_ADDR             \
+	MT6315_OC_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK3_OC_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK3_OC_STATUS_SHIFT            2
+#define MT6315_PMIC_STRUP_VBUCK4_OC_STATUS_ADDR             \
+	MT6315_OC_SDN_STS0
+#define MT6315_PMIC_STRUP_VBUCK4_OC_STATUS_MASK             0x1
+#define MT6315_PMIC_STRUP_VBUCK4_OC_STATUS_SHIFT            3
+#define MT6315_PMIC_STRUP_THERMAL0_STATUS_ADDR              \
+	MT6315_THERMALSTATUS
+#define MT6315_PMIC_STRUP_THERMAL0_STATUS_MASK              0x1
+#define MT6315_PMIC_STRUP_THERMAL0_STATUS_SHIFT             0
+#define MT6315_PMIC_STRUP_THERMAL1_STATUS_ADDR              \
+	MT6315_THERMALSTATUS
+#define MT6315_PMIC_STRUP_THERMAL1_STATUS_MASK              0x1
+#define MT6315_PMIC_STRUP_THERMAL1_STATUS_SHIFT             1
+#define MT6315_PMIC_STRUP_THERMAL2_STATUS_ADDR              \
+	MT6315_THERMALSTATUS
+#define MT6315_PMIC_STRUP_THERMAL2_STATUS_MASK              0x1
+#define MT6315_PMIC_STRUP_THERMAL2_STATUS_SHIFT             2
+#define MT6315_PMIC_STRUP_THERMAL3_STATUS_ADDR              \
+	MT6315_THERMALSTATUS
+#define MT6315_PMIC_STRUP_THERMAL3_STATUS_MASK              0x1
+#define MT6315_PMIC_STRUP_THERMAL3_STATUS_SHIFT             3
+#define MT6315_PMIC_STRUP_THERMAL4_STATUS_ADDR              \
+	MT6315_THERMALSTATUS
+#define MT6315_PMIC_STRUP_THERMAL4_STATUS_MASK              0x1
+#define MT6315_PMIC_STRUP_THERMAL4_STATUS_SHIFT             4
+#define MT6315_PMIC_PMU_THERMAL0_DEB_ADDR                   \
+	MT6315_THERMALDEB
+#define MT6315_PMIC_PMU_THERMAL0_DEB_MASK                   0x1
+#define MT6315_PMIC_PMU_THERMAL0_DEB_SHIFT                  0
+#define MT6315_PMIC_PMU_THERMAL1_DEB_ADDR                   \
+	MT6315_THERMALDEB
+#define MT6315_PMIC_PMU_THERMAL1_DEB_MASK                   0x1
+#define MT6315_PMIC_PMU_THERMAL1_DEB_SHIFT                  1
+#define MT6315_PMIC_PMU_THERMAL2_DEB_ADDR                   \
+	MT6315_THERMALDEB
+#define MT6315_PMIC_PMU_THERMAL2_DEB_MASK                   0x1
+#define MT6315_PMIC_PMU_THERMAL2_DEB_SHIFT                  2
+#define MT6315_PMIC_PMU_THERMAL3_DEB_ADDR                   \
+	MT6315_THERMALDEB
+#define MT6315_PMIC_PMU_THERMAL3_DEB_MASK                   0x1
+#define MT6315_PMIC_PMU_THERMAL3_DEB_SHIFT                  3
+#define MT6315_PMIC_PMU_THERMAL4_DEB_ADDR                   \
+	MT6315_THERMALDEB
+#define MT6315_PMIC_PMU_THERMAL4_DEB_MASK                   0x1
+#define MT6315_PMIC_PMU_THERMAL4_DEB_SHIFT                  4
+#define MT6315_PMIC_RG_SRCLKEN_IN_EN_ADDR                   \
+	MT6315_TOP_CON
+#define MT6315_PMIC_RG_SRCLKEN_IN_EN_MASK                   0x1
+#define MT6315_PMIC_RG_SRCLKEN_IN_EN_SHIFT                  0
+#define MT6315_PMIC_RG_SRCLKEN_IN_HW_MODE_ADDR              \
+	MT6315_TOP_CON
+#define MT6315_PMIC_RG_SRCLKEN_IN_HW_MODE_MASK              0x1
+#define MT6315_PMIC_RG_SRCLKEN_IN_HW_MODE_SHIFT             1
+#define MT6315_PMIC_RG_SRCLKEN_IN_SYNC_EN_ADDR              \
+	MT6315_TOP_CON
+#define MT6315_PMIC_RG_SRCLKEN_IN_SYNC_EN_MASK              0x1
+#define MT6315_PMIC_RG_SRCLKEN_IN_SYNC_EN_SHIFT             2
+#define MT6315_PMIC_RG_OSC_EN_AUTO_OFF_ADDR                 \
+	MT6315_TOP_CON
+#define MT6315_PMIC_RG_OSC_EN_AUTO_OFF_MASK                 0x1
+#define MT6315_PMIC_RG_OSC_EN_AUTO_OFF_SHIFT                3
+#define MT6315_PMIC_TEST_OUT_ADDR                           \
+	MT6315_TEST_OUT
+#define MT6315_PMIC_TEST_OUT_MASK                           0xFF
+#define MT6315_PMIC_TEST_OUT_SHIFT                          0
+#define MT6315_PMIC_RG_MON_GRP_SEL_ADDR                     \
+	MT6315_TEST_CON0
+#define MT6315_PMIC_RG_MON_GRP_SEL_MASK                     0x1F
+#define MT6315_PMIC_RG_MON_GRP_SEL_SHIFT                    0
+#define MT6315_PMIC_RG_MON_FLAG_SEL_ADDR                    \
+	MT6315_TEST_CON1
+#define MT6315_PMIC_RG_MON_FLAG_SEL_MASK                    0xFF
+#define MT6315_PMIC_RG_MON_FLAG_SEL_SHIFT                   0
+#define MT6315_PMIC_RG_DBG0_OUT_SEL_ADDR                    \
+	MT6315_TEST_CON2
+#define MT6315_PMIC_RG_DBG0_OUT_SEL_MASK                    0x7
+#define MT6315_PMIC_RG_DBG0_OUT_SEL_SHIFT                   0
+#define MT6315_PMIC_RG_DBG1_OUT_SEL_ADDR                    \
+	MT6315_TEST_CON2
+#define MT6315_PMIC_RG_DBG1_OUT_SEL_MASK                    0x7
+#define MT6315_PMIC_RG_DBG1_OUT_SEL_SHIFT                   4
+#define MT6315_PMIC_RG_DBG2_OUT_SEL_ADDR                    \
+	MT6315_TEST_CON3
+#define MT6315_PMIC_RG_DBG2_OUT_SEL_MASK                    0x7
+#define MT6315_PMIC_RG_DBG2_OUT_SEL_SHIFT                   0
+#define MT6315_PMIC_RG_DBG3_OUT_SEL_ADDR                    \
+	MT6315_TEST_CON3
+#define MT6315_PMIC_RG_DBG3_OUT_SEL_MASK                    0x7
+#define MT6315_PMIC_RG_DBG3_OUT_SEL_SHIFT                   4
+#define MT6315_PMIC_RG_NANDTREE_MODE_ADDR                   \
+	MT6315_TEST_CON4
+#define MT6315_PMIC_RG_NANDTREE_MODE_MASK                   0x1
+#define MT6315_PMIC_RG_NANDTREE_MODE_SHIFT                  1
+#define MT6315_PMIC_RG_EFUSE_MODE_ADDR                      \
+	MT6315_TEST_CON4
+#define MT6315_PMIC_RG_EFUSE_MODE_MASK                      0x1
+#define MT6315_PMIC_RG_EFUSE_MODE_SHIFT                     2
+#define MT6315_PMIC_RG_TEST_STRUP_ADDR                      \
+	MT6315_TEST_CON4
+#define MT6315_PMIC_RG_TEST_STRUP_MASK                      0x1
+#define MT6315_PMIC_RG_TEST_STRUP_SHIFT                     3
+#define MT6315_PMIC_RG_ATST_KEY0_ADDR                       \
+	MT6315_TEST_CON5
+#define MT6315_PMIC_RG_ATST_KEY0_MASK                       0xFF
+#define MT6315_PMIC_RG_ATST_KEY0_SHIFT                      0
+#define MT6315_PMIC_RG_ATST_KEY1_ADDR                       \
+	MT6315_TEST_CON6
+#define MT6315_PMIC_RG_ATST_KEY1_MASK                       0xFF
+#define MT6315_PMIC_RG_ATST_KEY1_SHIFT                      0
+#define MT6315_PMIC_RG_ATST_KEY2_ADDR                       \
+	MT6315_TEST_CON7
+#define MT6315_PMIC_RG_ATST_KEY2_MASK                       0xFF
+#define MT6315_PMIC_RG_ATST_KEY2_SHIFT                      0
+#define MT6315_PMIC_RG_ATST_KEY3_ADDR                       \
+	MT6315_TEST_CON8
+#define MT6315_PMIC_RG_ATST_KEY3_MASK                       0xFF
+#define MT6315_PMIC_RG_ATST_KEY3_SHIFT                      0
+#define MT6315_PMIC_RG_SYS_LATCH_EN_SW_SEL_ADDR             \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_SYS_LATCH_EN_SW_SEL_MASK             0x1
+#define MT6315_PMIC_RG_SYS_LATCH_EN_SW_SEL_SHIFT            0
+#define MT6315_PMIC_RG_SYS_LATCH_EN_SW_ADDR                 \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_SYS_LATCH_EN_SW_MASK                 0x1
+#define MT6315_PMIC_RG_SYS_LATCH_EN_SW_SHIFT                1
+#define MT6315_PMIC_RG_PG_OUT_SW_SEL_ADDR                   \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_PG_OUT_SW_SEL_MASK                   0x1
+#define MT6315_PMIC_RG_PG_OUT_SW_SEL_SHIFT                  2
+#define MT6315_PMIC_RG_PG_OUT_SW_ADDR                       \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_PG_OUT_SW_MASK                       0x1
+#define MT6315_PMIC_RG_PG_OUT_SW_SHIFT                      3
+#define MT6315_PMIC_RG_PG_OUT_DBG_SEL_ADDR                  \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_PG_OUT_DBG_SEL_MASK                  0x1
+#define MT6315_PMIC_RG_PG_OUT_DBG_SEL_SHIFT                 4
+#define MT6315_PMIC_RG_ANA_IO_SW_SEL_ADDR                   \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_ANA_IO_SW_SEL_MASK                   0x1
+#define MT6315_PMIC_RG_ANA_IO_SW_SEL_SHIFT                  5
+#define MT6315_PMIC_RG_ANA_IO_SW_ADDR                       \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_ANA_IO_SW_MASK                       0x1
+#define MT6315_PMIC_RG_ANA_IO_SW_SHIFT                      6
+#define MT6315_PMIC_RG_OSC_EN_DBG_SEL_ADDR                  \
+	MT6315_TEST_CON9
+#define MT6315_PMIC_RG_OSC_EN_DBG_SEL_MASK                  0x1
+#define MT6315_PMIC_RG_OSC_EN_DBG_SEL_SHIFT                 7
+#define MT6315_PMIC_TESTMODE_SW_ADDR                        \
+	MT6315_TESTMODE_SW
+#define MT6315_PMIC_TESTMODE_SW_MASK                        0x1
+#define MT6315_PMIC_TESTMODE_SW_SHIFT                       0
+#define MT6315_PMIC_PMU_TEST_MODE_SCAN_ADDR                 \
+	MT6315_TESTMODE_SW
+#define MT6315_PMIC_PMU_TEST_MODE_SCAN_MASK                 0x1
+#define MT6315_PMIC_PMU_TEST_MODE_SCAN_SHIFT                1
+#define MT6315_PMIC_RG_PMU_TDSEL_ADDR                       \
+	MT6315_TDSEL_CON
+#define MT6315_PMIC_RG_PMU_TDSEL_MASK                       0x1
+#define MT6315_PMIC_RG_PMU_TDSEL_SHIFT                      0
+#define MT6315_PMIC_RG_SIF_TDSEL_ADDR                       \
+	MT6315_TDSEL_CON
+#define MT6315_PMIC_RG_SIF_TDSEL_MASK                       0x1
+#define MT6315_PMIC_RG_SIF_TDSEL_SHIFT                      1
+#define MT6315_PMIC_RG_PMU_RDSEL_ADDR                       \
+	MT6315_RDSEL_CON
+#define MT6315_PMIC_RG_PMU_RDSEL_MASK                       0x1
+#define MT6315_PMIC_RG_PMU_RDSEL_SHIFT                      0
+#define MT6315_PMIC_RG_SIF_RDSEL_ADDR                       \
+	MT6315_RDSEL_CON
+#define MT6315_PMIC_RG_SIF_RDSEL_MASK                       0x1
+#define MT6315_PMIC_RG_SIF_RDSEL_SHIFT                      1
+#define MT6315_PMIC_RG_SMT_SRCLKEN_IN_ADDR                  \
+	MT6315_SMT_CON0
+#define MT6315_PMIC_RG_SMT_SRCLKEN_IN_MASK                  0x1
+#define MT6315_PMIC_RG_SMT_SRCLKEN_IN_SHIFT                 0
+#define MT6315_PMIC_RG_SMT_SCLK_ADDR                        \
+	MT6315_SMT_CON0
+#define MT6315_PMIC_RG_SMT_SCLK_MASK                        0x1
+#define MT6315_PMIC_RG_SMT_SCLK_SHIFT                       1
+#define MT6315_PMIC_RG_SMT_SDAT_ADDR                        \
+	MT6315_SMT_CON0
+#define MT6315_PMIC_RG_SMT_SDAT_MASK                        0x1
+#define MT6315_PMIC_RG_SMT_SDAT_SHIFT                       2
+#define MT6315_PMIC_RG_SMT_PMIC_INT_ADDR                    \
+	MT6315_SMT_CON0
+#define MT6315_PMIC_RG_SMT_PMIC_INT_MASK                    0x1
+#define MT6315_PMIC_RG_SMT_PMIC_INT_SHIFT                   3
+#define MT6315_PMIC_RG_SMT_WDTRSTB_IN_ADDR                  \
+	MT6315_SMT_CON0
+#define MT6315_PMIC_RG_SMT_WDTRSTB_IN_MASK                  0x1
+#define MT6315_PMIC_RG_SMT_WDTRSTB_IN_SHIFT                 4
+#define MT6315_PMIC_RG_EH_SRCLKEN_IN_ADDR                   \
+	MT6315_EH_CON0
+#define MT6315_PMIC_RG_EH_SRCLKEN_IN_MASK                   0x1
+#define MT6315_PMIC_RG_EH_SRCLKEN_IN_SHIFT                  0
+#define MT6315_PMIC_RG_EH_PMIC_INT_ADDR                     \
+	MT6315_EH_CON0
+#define MT6315_PMIC_RG_EH_PMIC_INT_MASK                     0x1
+#define MT6315_PMIC_RG_EH_PMIC_INT_SHIFT                    1
+#define MT6315_PMIC_RG_EH1_SRCLKEN_IN_ADDR                  \
+	MT6315_EH_CON0
+#define MT6315_PMIC_RG_EH1_SRCLKEN_IN_MASK                  0x1
+#define MT6315_PMIC_RG_EH1_SRCLKEN_IN_SHIFT                 2
+#define MT6315_PMIC_RG_EH1_PMIC_INT_ADDR                    \
+	MT6315_EH_CON0
+#define MT6315_PMIC_RG_EH1_PMIC_INT_MASK                    0x1
+#define MT6315_PMIC_RG_EH1_PMIC_INT_SHIFT                   3
+#define MT6315_PMIC_RG_EH2_SRCLKEN_IN_ADDR                  \
+	MT6315_EH_CON0
+#define MT6315_PMIC_RG_EH2_SRCLKEN_IN_MASK                  0x1
+#define MT6315_PMIC_RG_EH2_SRCLKEN_IN_SHIFT                 4
+#define MT6315_PMIC_RG_EH2_PMIC_INT_ADDR                    \
+	MT6315_EH_CON0
+#define MT6315_PMIC_RG_EH2_PMIC_INT_MASK                    0x1
+#define MT6315_PMIC_RG_EH2_PMIC_INT_SHIFT                   5
+#define MT6315_PMIC_RG_RSEL_SRCLKEN_IN_ADDR                 \
+	MT6315_RSEL_CON0
+#define MT6315_PMIC_RG_RSEL_SRCLKEN_IN_MASK                 0x1
+#define MT6315_PMIC_RG_RSEL_SRCLKEN_IN_SHIFT                0
+#define MT6315_PMIC_RG_RSEL_PMIC_INT_ADDR                   \
+	MT6315_RSEL_CON0
+#define MT6315_PMIC_RG_RSEL_PMIC_INT_MASK                   0x1
+#define MT6315_PMIC_RG_RSEL_PMIC_INT_SHIFT                  1
+#define MT6315_PMIC_RG_RSEL_WDTRSTB_IN_ADDR                 \
+	MT6315_RSEL_CON0
+#define MT6315_PMIC_RG_RSEL_WDTRSTB_IN_MASK                 0x1
+#define MT6315_PMIC_RG_RSEL_WDTRSTB_IN_SHIFT                2
+#define MT6315_PMIC_RG_TOP_RSV0_ADDR                        \
+	MT6315_TOP_RSV0
+#define MT6315_PMIC_RG_TOP_RSV0_MASK                        0x1
+#define MT6315_PMIC_RG_TOP_RSV0_SHIFT                       0
+#define MT6315_PMIC_RG_TOP_RSV1_ADDR                        \
+	MT6315_TOP_RSV1
+#define MT6315_PMIC_RG_TOP_RSV1_MASK                        0x1
+#define MT6315_PMIC_RG_TOP_RSV1_SHIFT                       0
+#define MT6315_PMIC_RG_OCTL_SRCLKEN_IN_ADDR                 \
+	MT6315_DRV_CON0
+#define MT6315_PMIC_RG_OCTL_SRCLKEN_IN_MASK                 0xF
+#define MT6315_PMIC_RG_OCTL_SRCLKEN_IN_SHIFT                0
+#define MT6315_PMIC_RG_OCTL_PMIC_INT_ADDR                   \
+	MT6315_DRV_CON0
+#define MT6315_PMIC_RG_OCTL_PMIC_INT_MASK                   0xF
+#define MT6315_PMIC_RG_OCTL_PMIC_INT_SHIFT                  4
+#define MT6315_PMIC_RG_SRCLKEN_IN_FILTER_EN_ADDR            \
+	MT6315_FILTER_CON0
+#define MT6315_PMIC_RG_SRCLKEN_IN_FILTER_EN_MASK            0x1
+#define MT6315_PMIC_RG_SRCLKEN_IN_FILTER_EN_SHIFT           0
+#define MT6315_PMIC_RG_SCLK_FILTER_EN_ADDR                  \
+	MT6315_FILTER_CON0
+#define MT6315_PMIC_RG_SCLK_FILTER_EN_MASK                  0x1
+#define MT6315_PMIC_RG_SCLK_FILTER_EN_SHIFT                 1
+#define MT6315_PMIC_RG_SDAT_FILTER_EN_ADDR                  \
+	MT6315_FILTER_CON0
+#define MT6315_PMIC_RG_SDAT_FILTER_EN_MASK                  0x1
+#define MT6315_PMIC_RG_SDAT_FILTER_EN_SHIFT                 2
+#define MT6315_PMIC_RG_PMIC_INT_FILTER_EN_ADDR              \
+	MT6315_FILTER_CON0
+#define MT6315_PMIC_RG_PMIC_INT_FILTER_EN_MASK              0x1
+#define MT6315_PMIC_RG_PMIC_INT_FILTER_EN_SHIFT             3
+#define MT6315_PMIC_RG_WDTRSTB_IN_FILTER_EN_ADDR            \
+	MT6315_FILTER_CON0
+#define MT6315_PMIC_RG_WDTRSTB_IN_FILTER_EN_MASK            0x1
+#define MT6315_PMIC_RG_WDTRSTB_IN_FILTER_EN_SHIFT           4
+#define MT6315_PMIC_RG_SRCLKEN_IN_RCSEL_ADDR                \
+	MT6315_FILTER_CON1
+#define MT6315_PMIC_RG_SRCLKEN_IN_RCSEL_MASK                0x1
+#define MT6315_PMIC_RG_SRCLKEN_IN_RCSEL_SHIFT               0
+#define MT6315_PMIC_RG_SCLK_RCSEL_ADDR                      \
+	MT6315_FILTER_CON1
+#define MT6315_PMIC_RG_SCLK_RCSEL_MASK                      0x1
+#define MT6315_PMIC_RG_SCLK_RCSEL_SHIFT                     1
+#define MT6315_PMIC_RG_SDAT_RCSEL_ADDR                      \
+	MT6315_FILTER_CON1
+#define MT6315_PMIC_RG_SDAT_RCSEL_MASK                      0x1
+#define MT6315_PMIC_RG_SDAT_RCSEL_SHIFT                     2
+#define MT6315_PMIC_RG_PMIC_INT_RCSEL_ADDR                  \
+	MT6315_FILTER_CON1
+#define MT6315_PMIC_RG_PMIC_INT_RCSEL_MASK                  0x1
+#define MT6315_PMIC_RG_PMIC_INT_RCSEL_SHIFT                 3
+#define MT6315_PMIC_RG_WDTRSTB_IN_RCSEL_ADDR                \
+	MT6315_FILTER_CON1
+#define MT6315_PMIC_RG_WDTRSTB_IN_RCSEL_MASK                0x1
+#define MT6315_PMIC_RG_WDTRSTB_IN_RCSEL_SHIFT               4
+#define MT6315_PMIC_TOP_STATUS_ADDR                         \
+	MT6315_TOP_STATUS
+#define MT6315_PMIC_TOP_STATUS_MASK                         0xFF
+#define MT6315_PMIC_TOP_STATUS_SHIFT                        0
+#define MT6315_PMIC_TOP_STATUS_SET_ADDR                     \
+	MT6315_TOP_STATUS_SET
+#define MT6315_PMIC_TOP_STATUS_SET_MASK                     0x3
+#define MT6315_PMIC_TOP_STATUS_SET_SHIFT                    0
+#define MT6315_PMIC_TOP_STATUS_CLR_ADDR                     \
+	MT6315_TOP_STATUS_CLR
+#define MT6315_PMIC_TOP_STATUS_CLR_MASK                     0x3
+#define MT6315_PMIC_TOP_STATUS_CLR_SHIFT                    0
+#define MT6315_PMIC_RG_SEQ_OFF_ADDR                         \
+	MT6315_TOP_PWOFF_CON
+#define MT6315_PMIC_RG_SEQ_OFF_MASK                         0x1
+#define MT6315_PMIC_RG_SEQ_OFF_SHIFT                        0
+#define MT6315_PMIC_VM_MODE_ADDR                            \
+	MT6315_TOP_TRAP
+#define MT6315_PMIC_VM_MODE_MASK                            0x3
+#define MT6315_PMIC_VM_MODE_SHIFT                           0
+#define MT6315_PMIC_TOP1_ANA_ID_ADDR                        \
+	MT6315_TOP1_ID
+#define MT6315_PMIC_TOP1_ANA_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP1_ANA_ID_SHIFT                       0
+#define MT6315_PMIC_TOP1_DIG_ID_ADDR                        \
+	MT6315_TOP1_ID_H
+#define MT6315_PMIC_TOP1_DIG_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP1_DIG_ID_SHIFT                       0
+#define MT6315_PMIC_TOP1_ANA_MINOR_REV_ADDR                 \
+	MT6315_TOP1_REV0
+#define MT6315_PMIC_TOP1_ANA_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP1_ANA_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP1_ANA_MAJOR_REV_ADDR                 \
+	MT6315_TOP1_REV0
+#define MT6315_PMIC_TOP1_ANA_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP1_ANA_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP1_DIG_MINOR_REV_ADDR                 \
+	MT6315_TOP1_REV0_H
+#define MT6315_PMIC_TOP1_DIG_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP1_DIG_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP1_DIG_MAJOR_REV_ADDR                 \
+	MT6315_TOP1_REV0_H
+#define MT6315_PMIC_TOP1_DIG_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP1_DIG_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP1_DSN_CBS_ADDR                       \
+	MT6315_TOP1_DSN_DBI
+#define MT6315_PMIC_TOP1_DSN_CBS_MASK                       0x3
+#define MT6315_PMIC_TOP1_DSN_CBS_SHIFT                      0
+#define MT6315_PMIC_TOP1_DSN_BIX_ADDR                       \
+	MT6315_TOP1_DSN_DBI
+#define MT6315_PMIC_TOP1_DSN_BIX_MASK                       0x3
+#define MT6315_PMIC_TOP1_DSN_BIX_SHIFT                      2
+#define MT6315_PMIC_TOP1_DSN_ESP_ADDR                       \
+	MT6315_TOP1_DSN_DBI_H
+#define MT6315_PMIC_TOP1_DSN_ESP_MASK                       0xFF
+#define MT6315_PMIC_TOP1_DSN_ESP_SHIFT                      0
+#define MT6315_PMIC_TOP1_DSN_FPI_ADDR                       \
+	MT6315_TOP1_DSN_DXI
+#define MT6315_PMIC_TOP1_DSN_FPI_MASK                       0xFF
+#define MT6315_PMIC_TOP1_DSN_FPI_SHIFT                      0
+#define MT6315_PMIC_GPIO_DIR0_ADDR                          \
+	MT6315_GPIO_DIR
+#define MT6315_PMIC_GPIO_DIR0_MASK                          0xF
+#define MT6315_PMIC_GPIO_DIR0_SHIFT                         0
+#define MT6315_PMIC_GPIO_DIR0_SET_ADDR                      \
+	MT6315_GPIO_DIR_SET
+#define MT6315_PMIC_GPIO_DIR0_SET_MASK                      0xF
+#define MT6315_PMIC_GPIO_DIR0_SET_SHIFT                     0
+#define MT6315_PMIC_GPIO_DIR0_CLR_ADDR                      \
+	MT6315_GPIO_DIR_CLR
+#define MT6315_PMIC_GPIO_DIR0_CLR_MASK                      0xF
+#define MT6315_PMIC_GPIO_DIR0_CLR_SHIFT                     0
+#define MT6315_PMIC_GPIO_PULLEN0_ADDR                       \
+	MT6315_GPIO_PULLEN0
+#define MT6315_PMIC_GPIO_PULLEN0_MASK                       0xF
+#define MT6315_PMIC_GPIO_PULLEN0_SHIFT                      0
+#define MT6315_PMIC_GPIO_PULLEN0_SET_ADDR                   \
+	MT6315_GPIO_PULLEN0_SET
+#define MT6315_PMIC_GPIO_PULLEN0_SET_MASK                   0xF
+#define MT6315_PMIC_GPIO_PULLEN0_SET_SHIFT                  0
+#define MT6315_PMIC_GPIO_PULLEN0_CLR_ADDR                   \
+	MT6315_GPIO_PULLEN0_CLR
+#define MT6315_PMIC_GPIO_PULLEN0_CLR_MASK                   0xF
+#define MT6315_PMIC_GPIO_PULLEN0_CLR_SHIFT                  0
+#define MT6315_PMIC_GPIO_PULLSEL0_ADDR                      \
+	MT6315_GPIO_PULLSEL0
+#define MT6315_PMIC_GPIO_PULLSEL0_MASK                      0xF
+#define MT6315_PMIC_GPIO_PULLSEL0_SHIFT                     0
+#define MT6315_PMIC_GPIO_PULLSEL0_SET_ADDR                  \
+	MT6315_GPIO_PULLSEL0_SET
+#define MT6315_PMIC_GPIO_PULLSEL0_SET_MASK                  0xF
+#define MT6315_PMIC_GPIO_PULLSEL0_SET_SHIFT                 0
+#define MT6315_PMIC_GPIO_PULLSEL0_CLR_ADDR                  \
+	MT6315_GPIO_PULLSEL0_CLR
+#define MT6315_PMIC_GPIO_PULLSEL0_CLR_MASK                  0xF
+#define MT6315_PMIC_GPIO_PULLSEL0_CLR_SHIFT                 0
+#define MT6315_PMIC_GPIO_DINV0_ADDR                         \
+	MT6315_GPIO_DINV
+#define MT6315_PMIC_GPIO_DINV0_MASK                         0xF
+#define MT6315_PMIC_GPIO_DINV0_SHIFT                        0
+#define MT6315_PMIC_GPIO_DINV0_SET_ADDR                     \
+	MT6315_GPIO_DINV_SET
+#define MT6315_PMIC_GPIO_DINV0_SET_MASK                     0xF
+#define MT6315_PMIC_GPIO_DINV0_SET_SHIFT                    0
+#define MT6315_PMIC_GPIO_DINV0_CLR_ADDR                     \
+	MT6315_GPIO_DINV_CLR
+#define MT6315_PMIC_GPIO_DINV0_CLR_MASK                     0xF
+#define MT6315_PMIC_GPIO_DINV0_CLR_SHIFT                    0
+#define MT6315_PMIC_GPIO_DOUT0_ADDR                         \
+	MT6315_GPIO_DOUT
+#define MT6315_PMIC_GPIO_DOUT0_MASK                         0xF
+#define MT6315_PMIC_GPIO_DOUT0_SHIFT                        0
+#define MT6315_PMIC_GPIO_DOUT0_SET_ADDR                     \
+	MT6315_GPIO_DOUT_SET
+#define MT6315_PMIC_GPIO_DOUT0_SET_MASK                     0xF
+#define MT6315_PMIC_GPIO_DOUT0_SET_SHIFT                    0
+#define MT6315_PMIC_GPIO_DOUT0_CLR_ADDR                     \
+	MT6315_GPIO_DOUT_CLR
+#define MT6315_PMIC_GPIO_DOUT0_CLR_MASK                     0xF
+#define MT6315_PMIC_GPIO_DOUT0_CLR_SHIFT                    0
+#define MT6315_PMIC_GPIO_PI0_ADDR                           \
+	MT6315_GPIO_PI
+#define MT6315_PMIC_GPIO_PI0_MASK                           0xF
+#define MT6315_PMIC_GPIO_PI0_SHIFT                          0
+#define MT6315_PMIC_GPIO_POE0_ADDR                          \
+	MT6315_GPIO_POE
+#define MT6315_PMIC_GPIO_POE0_MASK                          0xF
+#define MT6315_PMIC_GPIO_POE0_SHIFT                         0
+#define MT6315_PMIC_GPIO0_MODE_ADDR                         \
+	MT6315_GPIO_MODE0
+#define MT6315_PMIC_GPIO0_MODE_MASK                         0x7
+#define MT6315_PMIC_GPIO0_MODE_SHIFT                        0
+#define MT6315_PMIC_GPIO1_MODE_ADDR                         \
+	MT6315_GPIO_MODE0
+#define MT6315_PMIC_GPIO1_MODE_MASK                         0x7
+#define MT6315_PMIC_GPIO1_MODE_SHIFT                        4
+#define MT6315_PMIC_GPIO_MODE0_SET_ADDR                     \
+	MT6315_GPIO_MODE0_SET
+#define MT6315_PMIC_GPIO_MODE0_SET_MASK                     0xFF
+#define MT6315_PMIC_GPIO_MODE0_SET_SHIFT                    0
+#define MT6315_PMIC_GPIO_MODE0_CLR_ADDR                     \
+	MT6315_GPIO_MODE0_CLR
+#define MT6315_PMIC_GPIO_MODE0_CLR_MASK                     0xFF
+#define MT6315_PMIC_GPIO_MODE0_CLR_SHIFT                    0
+#define MT6315_PMIC_GPIO2_MODE_ADDR                         \
+	MT6315_GPIO_MODE1
+#define MT6315_PMIC_GPIO2_MODE_MASK                         0x7
+#define MT6315_PMIC_GPIO2_MODE_SHIFT                        0
+#define MT6315_PMIC_GPIO3_MODE_ADDR                         \
+	MT6315_GPIO_MODE1
+#define MT6315_PMIC_GPIO3_MODE_MASK                         0x7
+#define MT6315_PMIC_GPIO3_MODE_SHIFT                        4
+#define MT6315_PMIC_GPIO_MODE1_SET_ADDR                     \
+	MT6315_GPIO_MODE1_SET
+#define MT6315_PMIC_GPIO_MODE1_SET_MASK                     0xFF
+#define MT6315_PMIC_GPIO_MODE1_SET_SHIFT                    0
+#define MT6315_PMIC_GPIO_MODE1_CLR_ADDR                     \
+	MT6315_GPIO_MODE1_CLR
+#define MT6315_PMIC_GPIO_MODE1_CLR_MASK                     0xFF
+#define MT6315_PMIC_GPIO_MODE1_CLR_SHIFT                    0
+#define MT6315_PMIC_GPIO_RSV_ADDR                           \
+	MT6315_GPIO_RSV
+#define MT6315_PMIC_GPIO_RSV_MASK                           0x1
+#define MT6315_PMIC_GPIO_RSV_SHIFT                          0
+#define MT6315_PMIC_RG_PAD_IE_FORCE_ADDR                    \
+	MT6315_GPIO_CON
+#define MT6315_PMIC_RG_PAD_IE_FORCE_MASK                    0x1
+#define MT6315_PMIC_RG_PAD_IE_FORCE_SHIFT                   0
+#define MT6315_PMIC_TOP2_ANA_ID_ADDR                        \
+	MT6315_TOP2_ID
+#define MT6315_PMIC_TOP2_ANA_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP2_ANA_ID_SHIFT                       0
+#define MT6315_PMIC_TOP2_DIG_ID_ADDR                        \
+	MT6315_TOP2_ID_H
+#define MT6315_PMIC_TOP2_DIG_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP2_DIG_ID_SHIFT                       0
+#define MT6315_PMIC_TOP2_ANA_MINOR_REV_ADDR                 \
+	MT6315_TOP2_REV0
+#define MT6315_PMIC_TOP2_ANA_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP2_ANA_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP2_ANA_MAJOR_REV_ADDR                 \
+	MT6315_TOP2_REV0
+#define MT6315_PMIC_TOP2_ANA_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP2_ANA_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP2_DIG_MINOR_REV_ADDR                 \
+	MT6315_TOP2_REV0_H
+#define MT6315_PMIC_TOP2_DIG_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP2_DIG_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP2_DIG_MAJOR_REV_ADDR                 \
+	MT6315_TOP2_REV0_H
+#define MT6315_PMIC_TOP2_DIG_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP2_DIG_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP2_DSN_CBS_ADDR                       \
+	MT6315_TOP2_DSN_DBI
+#define MT6315_PMIC_TOP2_DSN_CBS_MASK                       0x3
+#define MT6315_PMIC_TOP2_DSN_CBS_SHIFT                      0
+#define MT6315_PMIC_TOP2_DSN_BIX_ADDR                       \
+	MT6315_TOP2_DSN_DBI
+#define MT6315_PMIC_TOP2_DSN_BIX_MASK                       0x3
+#define MT6315_PMIC_TOP2_DSN_BIX_SHIFT                      2
+#define MT6315_PMIC_TOP2_DSN_ESP_ADDR                       \
+	MT6315_TOP2_DSN_DBI_H
+#define MT6315_PMIC_TOP2_DSN_ESP_MASK                       0xFF
+#define MT6315_PMIC_TOP2_DSN_ESP_SHIFT                      0
+#define MT6315_PMIC_TOP2_DSN_FPI_ADDR                       \
+	MT6315_TOP2_DSN_DXI
+#define MT6315_PMIC_TOP2_DSN_FPI_MASK                       0xFF
+#define MT6315_PMIC_TOP2_DSN_FPI_SHIFT                      0
+#define MT6315_PMIC_TOP_CLK_OFFSET_ADDR                     \
+	MT6315_TOP_PAM0
+#define MT6315_PMIC_TOP_CLK_OFFSET_MASK                     0xFF
+#define MT6315_PMIC_TOP_CLK_OFFSET_SHIFT                    0
+#define MT6315_PMIC_TOP_RST_OFFSET_ADDR                     \
+	MT6315_TOP_PAM0_H
+#define MT6315_PMIC_TOP_RST_OFFSET_MASK                     0xFF
+#define MT6315_PMIC_TOP_RST_OFFSET_SHIFT                    0
+#define MT6315_PMIC_TOP_INT_OFFSET_ADDR                     \
+	MT6315_TOP_PAM1
+#define MT6315_PMIC_TOP_INT_OFFSET_MASK                     0xFF
+#define MT6315_PMIC_TOP_INT_OFFSET_SHIFT                    0
+#define MT6315_PMIC_TOP_INT_LEN_ADDR                        \
+	MT6315_TOP_PAM1_H
+#define MT6315_PMIC_TOP_INT_LEN_MASK                        0xFF
+#define MT6315_PMIC_TOP_INT_LEN_SHIFT                       0
+#define MT6315_PMIC_RG_TRIM_128K_CK_PDN_ADDR                \
+	MT6315_TOP_CKPDN_CON0
+#define MT6315_PMIC_RG_TRIM_128K_CK_PDN_MASK                0x1
+#define MT6315_PMIC_RG_TRIM_128K_CK_PDN_SHIFT               0
+#define MT6315_PMIC_RG_TRIM_4M_CK_PDN_ADDR                  \
+	MT6315_TOP_CKPDN_CON0
+#define MT6315_PMIC_RG_TRIM_4M_CK_PDN_MASK                  0x1
+#define MT6315_PMIC_RG_TRIM_4M_CK_PDN_SHIFT                 1
+#define MT6315_PMIC_RG_RSV_CK_PDN_ADDR                      \
+	MT6315_TOP_CKPDN_CON0
+#define MT6315_PMIC_RG_RSV_CK_PDN_MASK                      0x1
+#define MT6315_PMIC_RG_RSV_CK_PDN_SHIFT                     2
+#define MT6315_PMIC_RG_FQMTR_32K_CK_PDN_ADDR                \
+	MT6315_TOP_CKPDN_CON0
+#define MT6315_PMIC_RG_FQMTR_32K_CK_PDN_MASK                0x1
+#define MT6315_PMIC_RG_FQMTR_32K_CK_PDN_SHIFT               3
+#define MT6315_PMIC_RG_FQMTR_CK_PDN_ADDR                    \
+	MT6315_TOP_CKPDN_CON0
+#define MT6315_PMIC_RG_FQMTR_CK_PDN_MASK                    0x1
+#define MT6315_PMIC_RG_FQMTR_CK_PDN_SHIFT                   4
+#define MT6315_PMIC_RG_INTRP_CK_PDN_ADDR                    \
+	MT6315_TOP_CKPDN_CON0
+#define MT6315_PMIC_RG_INTRP_CK_PDN_MASK                    0x1
+#define MT6315_PMIC_RG_INTRP_CK_PDN_SHIFT                   5
+#define MT6315_PMIC_TOP_CKPDN_CON0_SET_ADDR                 \
+	MT6315_TOP_CKPDN_CON0_SET
+#define MT6315_PMIC_TOP_CKPDN_CON0_SET_MASK                 0xFF
+#define MT6315_PMIC_TOP_CKPDN_CON0_SET_SHIFT                0
+#define MT6315_PMIC_TOP_CKPDN_CON0_CLR_ADDR                 \
+	MT6315_TOP_CKPDN_CON0_CLR
+#define MT6315_PMIC_TOP_CKPDN_CON0_CLR_MASK                 0xFF
+#define MT6315_PMIC_TOP_CKPDN_CON0_CLR_SHIFT                0
+#define MT6315_PMIC_RG_PMU128K_CK_PDN_ADDR                  \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_PMU128K_CK_PDN_MASK                  0x1
+#define MT6315_PMIC_RG_PMU128K_CK_PDN_SHIFT                 0
+#define MT6315_PMIC_RG_PMU32K_CK_PDN_ADDR                   \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_PMU32K_CK_PDN_MASK                   0x1
+#define MT6315_PMIC_RG_PMU32K_CK_PDN_SHIFT                  1
+#define MT6315_PMIC_RG_EFUSE_CK_PDN_ADDR                    \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_EFUSE_CK_PDN_MASK                    0x1
+#define MT6315_PMIC_RG_EFUSE_CK_PDN_SHIFT                   2
+#define MT6315_PMIC_RG_SMPS4M_CK_PDN_ADDR                   \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_SMPS4M_CK_PDN_MASK                   0x1
+#define MT6315_PMIC_RG_SMPS4M_CK_PDN_SHIFT                  3
+#define MT6315_PMIC_RG_SMPS1M_CK_PDN_ADDR                   \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_SMPS1M_CK_PDN_MASK                   0x1
+#define MT6315_PMIC_RG_SMPS1M_CK_PDN_SHIFT                  4
+#define MT6315_PMIC_RG_RFFE_CK_PDN_ADDR                     \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_RFFE_CK_PDN_MASK                     0x1
+#define MT6315_PMIC_RG_RFFE_CK_PDN_SHIFT                    5
+#define MT6315_PMIC_RG_SPMI_CK_PDN_ADDR                     \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_SPMI_CK_PDN_MASK                     0x1
+#define MT6315_PMIC_RG_SPMI_CK_PDN_SHIFT                    6
+#define MT6315_PMIC_RG_I2C_CK_PDN_ADDR                      \
+	MT6315_TOP_CKPDN_CON1
+#define MT6315_PMIC_RG_I2C_CK_PDN_MASK                      0x1
+#define MT6315_PMIC_RG_I2C_CK_PDN_SHIFT                     7
+#define MT6315_PMIC_TOP_CKPDN_CON1_SET_ADDR                 \
+	MT6315_TOP_CKPDN_CON1_SET
+#define MT6315_PMIC_TOP_CKPDN_CON1_SET_MASK                 0xFF
+#define MT6315_PMIC_TOP_CKPDN_CON1_SET_SHIFT                0
+#define MT6315_PMIC_TOP_CKPDN_CON1_CLR_ADDR                 \
+	MT6315_TOP_CKPDN_CON1_CLR
+#define MT6315_PMIC_TOP_CKPDN_CON1_CLR_MASK                 0xFF
+#define MT6315_PMIC_TOP_CKPDN_CON1_CLR_SHIFT                0
+#define MT6315_PMIC_RG_EFUSE_CK_CKSEL_ADDR                  \
+	MT6315_TOP_CKSEL_CON0
+#define MT6315_PMIC_RG_EFUSE_CK_CKSEL_MASK                  0x1
+#define MT6315_PMIC_RG_EFUSE_CK_CKSEL_SHIFT                 0
+#define MT6315_PMIC_RG_FQMTR_CK_CKSEL_ADDR                  \
+	MT6315_TOP_CKSEL_CON0
+#define MT6315_PMIC_RG_FQMTR_CK_CKSEL_MASK                  0x7
+#define MT6315_PMIC_RG_FQMTR_CK_CKSEL_SHIFT                 1
+#define MT6315_PMIC_RG_PMU32K_CK_CKSEL_ADDR                 \
+	MT6315_TOP_CKSEL_CON0
+#define MT6315_PMIC_RG_PMU32K_CK_CKSEL_MASK                 0x1
+#define MT6315_PMIC_RG_PMU32K_CK_CKSEL_SHIFT                4
+#define MT6315_PMIC_RG_TOP_CKSEL_CON0_RSV_ADDR              \
+	MT6315_TOP_CKSEL_CON0
+#define MT6315_PMIC_RG_TOP_CKSEL_CON0_RSV_MASK              0x7
+#define MT6315_PMIC_RG_TOP_CKSEL_CON0_RSV_SHIFT             5
+#define MT6315_PMIC_TOP_CKSEL_CON0_SET_ADDR                 \
+	MT6315_TOP_CKSEL_CON0_SET
+#define MT6315_PMIC_TOP_CKSEL_CON0_SET_MASK                 0xFF
+#define MT6315_PMIC_TOP_CKSEL_CON0_SET_SHIFT                0
+#define MT6315_PMIC_TOP_CKSEL_CON0_CLR_ADDR                 \
+	MT6315_TOP_CKSEL_CON0_CLR
+#define MT6315_PMIC_TOP_CKSEL_CON0_CLR_MASK                 0xFF
+#define MT6315_PMIC_TOP_CKSEL_CON0_CLR_SHIFT                0
+#define MT6315_PMIC_RG_REG_CK_DIVSEL_ADDR                   \
+	MT6315_TOP_CKDIVSEL_CON0
+#define MT6315_PMIC_RG_REG_CK_DIVSEL_MASK                   0x3
+#define MT6315_PMIC_RG_REG_CK_DIVSEL_SHIFT                  0
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_RSV_ADDR              \
+	MT6315_TOP_CKDIVSEL_CON0
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_RSV_MASK              0x3F
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_RSV_SHIFT             2
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_SET_ADDR              \
+	MT6315_TOP_CKDIVSEL_CON0_SET
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_SET_MASK              0xFF
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_SET_SHIFT             0
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_CLR_ADDR              \
+	MT6315_TOP_CKDIVSEL_CON0_CLR
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_CLR_MASK              0xFF
+#define MT6315_PMIC_TOP_CKDIVSEL_CON0_CLR_SHIFT             0
+#define MT6315_PMIC_RG_EFUSE_CK_PDN_HWEN_ADDR               \
+	MT6315_TOP_CKHWEN_CON0
+#define MT6315_PMIC_RG_EFUSE_CK_PDN_HWEN_MASK               0x1
+#define MT6315_PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT              0
+#define MT6315_PMIC_RG_SMPS4M_CK_PDN_HWEN_ADDR              \
+	MT6315_TOP_CKHWEN_CON0
+#define MT6315_PMIC_RG_SMPS4M_CK_PDN_HWEN_MASK              0x1
+#define MT6315_PMIC_RG_SMPS4M_CK_PDN_HWEN_SHIFT             1
+#define MT6315_PMIC_RG_SMPS1M_CK_PDN_HWEN_ADDR              \
+	MT6315_TOP_CKHWEN_CON0
+#define MT6315_PMIC_RG_SMPS1M_CK_PDN_HWEN_MASK              0x1
+#define MT6315_PMIC_RG_SMPS1M_CK_PDN_HWEN_SHIFT             2
+#define MT6315_PMIC_TOP_CKHWEN_CON0_RSV_ADDR                \
+	MT6315_TOP_CKHWEN_CON0
+#define MT6315_PMIC_TOP_CKHWEN_CON0_RSV_MASK                0x7
+#define MT6315_PMIC_TOP_CKHWEN_CON0_RSV_SHIFT               3
+#define MT6315_PMIC_TOP_CKHWEN_CON0_SET_ADDR                \
+	MT6315_TOP_CKHWEN_CON0_SET
+#define MT6315_PMIC_TOP_CKHWEN_CON0_SET_MASK                0xFF
+#define MT6315_PMIC_TOP_CKHWEN_CON0_SET_SHIFT               0
+#define MT6315_PMIC_TOP_CKHWEN_CON0_CLR_ADDR                \
+	MT6315_TOP_CKHWEN_CON0_CLR
+#define MT6315_PMIC_TOP_CKHWEN_CON0_CLR_MASK                0xFF
+#define MT6315_PMIC_TOP_CKHWEN_CON0_CLR_SHIFT               0
+#define MT6315_PMIC_DA_SMPS_OSC_EN_ADDR                     \
+	MT6315_TOP_SMPS_OSC_DBG
+#define MT6315_PMIC_DA_SMPS_OSC_EN_MASK                     0x1
+#define MT6315_PMIC_DA_SMPS_OSC_EN_SHIFT                    0
+#define MT6315_PMIC_SMPS4M_CKEN_BUCK_ADDR                   \
+	MT6315_TOP_SMPS_OSC_DBG
+#define MT6315_PMIC_SMPS4M_CKEN_BUCK_MASK                   0x1
+#define MT6315_PMIC_SMPS4M_CKEN_BUCK_SHIFT                  1
+#define MT6315_PMIC_SMPS1M_CKEN_BUCK_ADDR                   \
+	MT6315_TOP_SMPS_OSC_DBG
+#define MT6315_PMIC_SMPS1M_CKEN_BUCK_MASK                   0x1
+#define MT6315_PMIC_SMPS1M_CKEN_BUCK_SHIFT                  2
+#define MT6315_PMIC_RG_PMU128K_CK_TST_DIS_ADDR              \
+	MT6315_TOP_CKTST_CON0
+#define MT6315_PMIC_RG_PMU128K_CK_TST_DIS_MASK              0x1
+#define MT6315_PMIC_RG_PMU128K_CK_TST_DIS_SHIFT             0
+#define MT6315_PMIC_RG_SMPS_CK_TST_DIS_ADDR                 \
+	MT6315_TOP_CKTST_CON0
+#define MT6315_PMIC_RG_SMPS_CK_TST_DIS_MASK                 0x1
+#define MT6315_PMIC_RG_SMPS_CK_TST_DIS_SHIFT                1
+#define MT6315_PMIC_TOP_CKTST_CON0_RSV_ADDR                 \
+	MT6315_TOP_CKTST_CON0
+#define MT6315_PMIC_TOP_CKTST_CON0_RSV_MASK                 0x3F
+#define MT6315_PMIC_TOP_CKTST_CON0_RSV_SHIFT                2
+#define MT6315_PMIC_RG_PMU128K_CK_TSTSEL_ADDR               \
+	MT6315_TOP_CKTST_CON1
+#define MT6315_PMIC_RG_PMU128K_CK_TSTSEL_MASK               0x1
+#define MT6315_PMIC_RG_PMU128K_CK_TSTSEL_SHIFT              0
+#define MT6315_PMIC_RG_SMPS_CK_TSTSEL_ADDR                  \
+	MT6315_TOP_CKTST_CON1
+#define MT6315_PMIC_RG_SMPS_CK_TSTSEL_MASK                  0x1
+#define MT6315_PMIC_RG_SMPS_CK_TSTSEL_SHIFT                 1
+#define MT6315_PMIC_RG_EFUSE_CK_TSTSEL_ADDR                 \
+	MT6315_TOP_CKTST_CON1
+#define MT6315_PMIC_RG_EFUSE_CK_TSTSEL_MASK                 0x1
+#define MT6315_PMIC_RG_EFUSE_CK_TSTSEL_SHIFT                2
+#define MT6315_PMIC_RG_FQMTR_CK_TSTSEL_ADDR                 \
+	MT6315_TOP_CKTST_CON1
+#define MT6315_PMIC_RG_FQMTR_CK_TSTSEL_MASK                 0x1
+#define MT6315_PMIC_RG_FQMTR_CK_TSTSEL_SHIFT                3
+#define MT6315_PMIC_RG_OSC_EN_SW_SEL_ADDR                   \
+	MT6315_TOP_CLK_CON0
+#define MT6315_PMIC_RG_OSC_EN_SW_SEL_MASK                   0x1
+#define MT6315_PMIC_RG_OSC_EN_SW_SEL_SHIFT                  0
+#define MT6315_PMIC_RG_OSC_EN_SW_ADDR                       \
+	MT6315_TOP_CLK_CON0
+#define MT6315_PMIC_RG_OSC_EN_SW_MASK                       0x1
+#define MT6315_PMIC_RG_OSC_EN_SW_SHIFT                      1
+#define MT6315_PMIC_RG_BUCK_LP_EN_ADDR                      \
+	MT6315_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK_LP_EN_MASK                      0x1
+#define MT6315_PMIC_RG_BUCK_LP_EN_SHIFT                     4
+#define MT6315_PMIC_RG_SRCLKEN_LP_EN_ADDR                   \
+	MT6315_TOP_CLK_CON0
+#define MT6315_PMIC_RG_SRCLKEN_LP_EN_MASK                   0x1
+#define MT6315_PMIC_RG_SRCLKEN_LP_EN_SHIFT                  5
+#define MT6315_PMIC_RG_BUCK_OSC_CTRL_ONLY_ADDR              \
+	MT6315_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK_OSC_CTRL_ONLY_MASK              0x1
+#define MT6315_PMIC_RG_BUCK_OSC_CTRL_ONLY_SHIFT             6
+#define MT6315_PMIC_RG_EFUSE_MAN_RST_ADDR                   \
+	MT6315_TOP_RST_CON0
+#define MT6315_PMIC_RG_EFUSE_MAN_RST_MASK                   0x1
+#define MT6315_PMIC_RG_EFUSE_MAN_RST_SHIFT                  0
+#define MT6315_PMIC_RG_FQMTR_RST_ADDR                       \
+	MT6315_TOP_RST_CON0
+#define MT6315_PMIC_RG_FQMTR_RST_MASK                       0x1
+#define MT6315_PMIC_RG_FQMTR_RST_SHIFT                      2
+#define MT6315_PMIC_RG_CLK_TRIM_128K_RST_ADDR               \
+	MT6315_TOP_RST_CON0
+#define MT6315_PMIC_RG_CLK_TRIM_128K_RST_MASK               0x1
+#define MT6315_PMIC_RG_CLK_TRIM_128K_RST_SHIFT              4
+#define MT6315_PMIC_RG_CLK_TRIM_4M_RST_ADDR                 \
+	MT6315_TOP_RST_CON0
+#define MT6315_PMIC_RG_CLK_TRIM_4M_RST_MASK                 0x1
+#define MT6315_PMIC_RG_CLK_TRIM_4M_RST_SHIFT                5
+#define MT6315_PMIC_RG_BUCK_SRCLKEN_RST_ADDR                \
+	MT6315_TOP_RST_CON0
+#define MT6315_PMIC_RG_BUCK_SRCLKEN_RST_MASK                0x1
+#define MT6315_PMIC_RG_BUCK_SRCLKEN_RST_SHIFT               6
+#define MT6315_PMIC_TOP_RST_CON0_SET_ADDR                   \
+	MT6315_TOP_RST_CON0_SET
+#define MT6315_PMIC_TOP_RST_CON0_SET_MASK                   0xFF
+#define MT6315_PMIC_TOP_RST_CON0_SET_SHIFT                  0
+#define MT6315_PMIC_TOP_RST_CON0_CLR_ADDR                   \
+	MT6315_TOP_RST_CON0_CLR
+#define MT6315_PMIC_TOP_RST_CON0_CLR_MASK                   0xFF
+#define MT6315_PMIC_TOP_RST_CON0_CLR_SHIFT                  0
+#define MT6315_PMIC_RG_BUCK_PROT_PMPP_RST_ADDR              \
+	MT6315_TOP_RST_CON1
+#define MT6315_PMIC_RG_BUCK_PROT_PMPP_RST_MASK              0x1
+#define MT6315_PMIC_RG_BUCK_PROT_PMPP_RST_SHIFT             0
+#define MT6315_PMIC_RG_FT_VR_SYSRSTB_ADDR                   \
+	MT6315_TOP_RST_CON1
+#define MT6315_PMIC_RG_FT_VR_SYSRSTB_MASK                   0x1
+#define MT6315_PMIC_RG_FT_VR_SYSRSTB_SHIFT                  1
+#define MT6315_PMIC_TOP_RST_CON1_RSV_ADDR                   \
+	MT6315_TOP_RST_CON1
+#define MT6315_PMIC_TOP_RST_CON1_RSV_MASK                   0x7
+#define MT6315_PMIC_TOP_RST_CON1_RSV_SHIFT                  2
+#define MT6315_PMIC_TOP_RST_CON1_SET_ADDR                   \
+	MT6315_TOP_RST_CON1_SET
+#define MT6315_PMIC_TOP_RST_CON1_SET_MASK                   0xFF
+#define MT6315_PMIC_TOP_RST_CON1_SET_SHIFT                  0
+#define MT6315_PMIC_TOP_RST_CON1_CLR_ADDR                   \
+	MT6315_TOP_RST_CON1_CLR
+#define MT6315_PMIC_TOP_RST_CON1_CLR_MASK                   0xFF
+#define MT6315_PMIC_TOP_RST_CON1_CLR_SHIFT                  0
+#define MT6315_PMIC_TOP_RST_CON2_RSV_ADDR                   \
+	MT6315_TOP_RST_CON2
+#define MT6315_PMIC_TOP_RST_CON2_RSV_MASK                   0xF
+#define MT6315_PMIC_TOP_RST_CON2_RSV_SHIFT                  4
+#define MT6315_PMIC_RG_GPIO_RST_SEL_ADDR                    \
+	MT6315_TOP_RST_CON3
+#define MT6315_PMIC_RG_GPIO_RST_SEL_MASK                    0x1
+#define MT6315_PMIC_RG_GPIO_RST_SEL_SHIFT                   0
+#define MT6315_PMIC_RG_WDTRSTB_EN_ADDR                      \
+	MT6315_TOP_RST_MISC
+#define MT6315_PMIC_RG_WDTRSTB_EN_MASK                      0x1
+#define MT6315_PMIC_RG_WDTRSTB_EN_SHIFT                     0
+#define MT6315_PMIC_RG_WDTRSTB_DEB_ADDR                     \
+	MT6315_TOP_RST_MISC
+#define MT6315_PMIC_RG_WDTRSTB_DEB_MASK                     0x1
+#define MT6315_PMIC_RG_WDTRSTB_DEB_SHIFT                    1
+#define MT6315_PMIC_WDTRSTB_STATUS_ADDR                     \
+	MT6315_TOP_RST_MISC
+#define MT6315_PMIC_WDTRSTB_STATUS_MASK                     0x1
+#define MT6315_PMIC_WDTRSTB_STATUS_SHIFT                    2
+#define MT6315_PMIC_WDTRSTB_STATUS_CLR_ADDR                 \
+	MT6315_TOP_RST_MISC
+#define MT6315_PMIC_WDTRSTB_STATUS_CLR_MASK                 0x1
+#define MT6315_PMIC_WDTRSTB_STATUS_CLR_SHIFT                3
+#define MT6315_PMIC_TOP_RST_MISC_SET_ADDR                   \
+	MT6315_TOP_RST_MISC_SET
+#define MT6315_PMIC_TOP_RST_MISC_SET_MASK                   0xFF
+#define MT6315_PMIC_TOP_RST_MISC_SET_SHIFT                  0
+#define MT6315_PMIC_TOP_RST_MISC_CLR_ADDR                   \
+	MT6315_TOP_RST_MISC_CLR
+#define MT6315_PMIC_TOP_RST_MISC_CLR_MASK                   0xFF
+#define MT6315_PMIC_TOP_RST_MISC_CLR_SHIFT                  0
+#define MT6315_PMIC_VPWRIN_RSTB_STATUS_ADDR                 \
+	MT6315_TOP_RST_STATUS
+#define MT6315_PMIC_VPWRIN_RSTB_STATUS_MASK                 0x1
+#define MT6315_PMIC_VPWRIN_RSTB_STATUS_SHIFT                0
+#define MT6315_PMIC_UVLO_RSTB_STATUS_ADDR                   \
+	MT6315_TOP_RST_STATUS
+#define MT6315_PMIC_UVLO_RSTB_STATUS_MASK                   0x1
+#define MT6315_PMIC_UVLO_RSTB_STATUS_SHIFT                  1
+#define MT6315_PMIC_TOP_RST_STATUS_RSV_ADDR                 \
+	MT6315_TOP_RST_STATUS
+#define MT6315_PMIC_TOP_RST_STATUS_RSV_MASK                 0x3
+#define MT6315_PMIC_TOP_RST_STATUS_RSV_SHIFT                2
+#define MT6315_PMIC_TOP_RST_STATUS_SET_ADDR                 \
+	MT6315_TOP_RST_STATUS_SET
+#define MT6315_PMIC_TOP_RST_STATUS_SET_MASK                 0xFF
+#define MT6315_PMIC_TOP_RST_STATUS_SET_SHIFT                0
+#define MT6315_PMIC_TOP_RST_STATUS_CLR_ADDR                 \
+	MT6315_TOP_RST_STATUS_CLR
+#define MT6315_PMIC_TOP_RST_STATUS_CLR_MASK                 0xFF
+#define MT6315_PMIC_TOP_RST_STATUS_CLR_SHIFT                0
+#define MT6315_PMIC_FQMTR_EN_ADDR                           \
+	MT6315_TOP_FQMTR_CON0
+#define MT6315_PMIC_FQMTR_EN_MASK                           0x1
+#define MT6315_PMIC_FQMTR_EN_SHIFT                          0
+#define MT6315_PMIC_FQMTR_TCKSEL_ADDR                       \
+	MT6315_TOP_FQMTR_CON0
+#define MT6315_PMIC_FQMTR_TCKSEL_MASK                       0x7
+#define MT6315_PMIC_FQMTR_TCKSEL_SHIFT                      4
+#define MT6315_PMIC_FQMTR_BUSY_ADDR                         \
+	MT6315_TOP_FQMTR_CON0
+#define MT6315_PMIC_FQMTR_BUSY_MASK                         0x1
+#define MT6315_PMIC_FQMTR_BUSY_SHIFT                        7
+#define MT6315_PMIC_FQMTR_WINSET_0_ADDR                     \
+	MT6315_TOP_FQMTR_CON1
+#define MT6315_PMIC_FQMTR_WINSET_0_MASK                     0xFF
+#define MT6315_PMIC_FQMTR_WINSET_0_SHIFT                    0
+#define MT6315_PMIC_FQMTR_WINSET_1_ADDR                     \
+	MT6315_TOP_FQMTR_CON2
+#define MT6315_PMIC_FQMTR_WINSET_1_MASK                     0xFF
+#define MT6315_PMIC_FQMTR_WINSET_1_SHIFT                    0
+#define MT6315_PMIC_FQMTR_DATA_0_ADDR                       \
+	MT6315_TOP_FQMTR_DAT0
+#define MT6315_PMIC_FQMTR_DATA_0_MASK                       0xFF
+#define MT6315_PMIC_FQMTR_DATA_0_SHIFT                      0
+#define MT6315_PMIC_FQMTR_DATA_1_ADDR                       \
+	MT6315_TOP_FQMTR_DAT1
+#define MT6315_PMIC_FQMTR_DATA_1_MASK                       0xFF
+#define MT6315_PMIC_FQMTR_DATA_1_SHIFT                      0
+#define MT6315_PMIC_TOP2_ELR_LEN_ADDR                       \
+	MT6315_TOP2_ELR_NUM
+#define MT6315_PMIC_TOP2_ELR_LEN_MASK                       0xFF
+#define MT6315_PMIC_TOP2_ELR_LEN_SHIFT                      0
+#define MT6315_PMIC_RG_SIF_SEL_ADDR                         \
+	MT6315_TOP2_ELR0
+#define MT6315_PMIC_RG_SIF_SEL_MASK                         0x3
+#define MT6315_PMIC_RG_SIF_SEL_SHIFT                        0
+#define MT6315_PMIC_RG_SIF_PULL_AUTO_ADDR                   \
+	MT6315_TOP2_ELR0
+#define MT6315_PMIC_RG_SIF_PULL_AUTO_MASK                   0x1
+#define MT6315_PMIC_RG_SIF_PULL_AUTO_SHIFT                  2
+#define MT6315_PMIC_RG_SIF_PULL_BY_EFUSE_ADDR               \
+	MT6315_TOP2_ELR0
+#define MT6315_PMIC_RG_SIF_PULL_BY_EFUSE_MASK               0x1
+#define MT6315_PMIC_RG_SIF_PULL_BY_EFUSE_SHIFT              3
+#define MT6315_PMIC_RG_SIF_PULLEN_ADDR                      \
+	MT6315_TOP2_ELR0
+#define MT6315_PMIC_RG_SIF_PULLEN_MASK                      0x3
+#define MT6315_PMIC_RG_SIF_PULLEN_SHIFT                     4
+#define MT6315_PMIC_RG_SIF_PULLSEL_ADDR                     \
+	MT6315_TOP2_ELR0
+#define MT6315_PMIC_RG_SIF_PULLSEL_MASK                     0x3
+#define MT6315_PMIC_RG_SIF_PULLSEL_SHIFT                    6
+#define MT6315_PMIC_RG_EH_SCLK_ADDR                         \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_EH_SCLK_MASK                         0x1
+#define MT6315_PMIC_RG_EH_SCLK_SHIFT                        0
+#define MT6315_PMIC_RG_EH_SDAT_ADDR                         \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_EH_SDAT_MASK                         0x1
+#define MT6315_PMIC_RG_EH_SDAT_SHIFT                        1
+#define MT6315_PMIC_RG_EH1_SCLK_ADDR                        \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_EH1_SCLK_MASK                        0x1
+#define MT6315_PMIC_RG_EH1_SCLK_SHIFT                       2
+#define MT6315_PMIC_RG_EH1_SDAT_ADDR                        \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_EH1_SDAT_MASK                        0x1
+#define MT6315_PMIC_RG_EH1_SDAT_SHIFT                       3
+#define MT6315_PMIC_RG_EH2_SCLK_ADDR                        \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_EH2_SCLK_MASK                        0x1
+#define MT6315_PMIC_RG_EH2_SCLK_SHIFT                       4
+#define MT6315_PMIC_RG_EH2_SDAT_ADDR                        \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_EH2_SDAT_MASK                        0x1
+#define MT6315_PMIC_RG_EH2_SDAT_SHIFT                       5
+#define MT6315_PMIC_RG_RSEL_SCLK_ADDR                       \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_RSEL_SCLK_MASK                       0x1
+#define MT6315_PMIC_RG_RSEL_SCLK_SHIFT                      6
+#define MT6315_PMIC_RG_RSEL_SDAT_ADDR                       \
+	MT6315_TOP2_ELR1
+#define MT6315_PMIC_RG_RSEL_SDAT_MASK                       0x1
+#define MT6315_PMIC_RG_RSEL_SDAT_SHIFT                      7
+#define MT6315_PMIC_RG_OCTL_SCLK_ADDR                       \
+	MT6315_TOP2_ELR2
+#define MT6315_PMIC_RG_OCTL_SCLK_MASK                       0xF
+#define MT6315_PMIC_RG_OCTL_SCLK_SHIFT                      0
+#define MT6315_PMIC_RG_OCTL_SDAT_ADDR                       \
+	MT6315_TOP2_ELR2
+#define MT6315_PMIC_RG_OCTL_SDAT_MASK                       0xF
+#define MT6315_PMIC_RG_OCTL_SDAT_SHIFT                      4
+#define MT6315_PMIC_RG_TOP2_RSV0_ADDR                       \
+	MT6315_TOP2_ELR3
+#define MT6315_PMIC_RG_TOP2_RSV0_MASK                       0xFF
+#define MT6315_PMIC_RG_TOP2_RSV0_SHIFT                      0
+#define MT6315_PMIC_RG_SLV_ID_ADDR                          \
+	MT6315_TOP2_ELR4
+#define MT6315_PMIC_RG_SLV_ID_MASK                          0xFF
+#define MT6315_PMIC_RG_SLV_ID_SHIFT                         0
+#define MT6315_PMIC_RG_SLV_CON0_ADDR                        \
+	MT6315_TOP2_ELR5
+#define MT6315_PMIC_RG_SLV_CON0_MASK                        0xFF
+#define MT6315_PMIC_RG_SLV_CON0_SHIFT                       0
+#define MT6315_PMIC_RG_WDTRSTB_SRC_SEL_ADDR                 \
+	MT6315_TOP2_ELR6
+#define MT6315_PMIC_RG_WDTRSTB_SRC_SEL_MASK                 0x1
+#define MT6315_PMIC_RG_WDTRSTB_SRC_SEL_SHIFT                0
+#define MT6315_PMIC_RG_SRCLKEN_SRC_SEL_ADDR                 \
+	MT6315_TOP2_ELR6
+#define MT6315_PMIC_RG_SRCLKEN_SRC_SEL_MASK                 0x1
+#define MT6315_PMIC_RG_SRCLKEN_SRC_SEL_SHIFT                1
+#define MT6315_PMIC_RG_SHUTDOWN_SRC_SEL_ADDR                \
+	MT6315_TOP2_ELR6
+#define MT6315_PMIC_RG_SHUTDOWN_SRC_SEL_MASK                0x1
+#define MT6315_PMIC_RG_SHUTDOWN_SRC_SEL_SHIFT               2
+#define MT6315_PMIC_RG_TOP2_RSV1_ADDR                       \
+	MT6315_TOP2_ELR6
+#define MT6315_PMIC_RG_TOP2_RSV1_MASK                       0x1F
+#define MT6315_PMIC_RG_TOP2_RSV1_SHIFT                      3
+#define MT6315_PMIC_RG_TOP2_RSV2_ADDR                       \
+	MT6315_TOP2_ELR7
+#define MT6315_PMIC_RG_TOP2_RSV2_MASK                       0xFF
+#define MT6315_PMIC_RG_TOP2_RSV2_SHIFT                      0
+#define MT6315_PMIC_TOP3_ANA_ID_ADDR                        \
+	MT6315_TOP3_ID
+#define MT6315_PMIC_TOP3_ANA_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP3_ANA_ID_SHIFT                       0
+#define MT6315_PMIC_TOP3_DIG_ID_ADDR                        \
+	MT6315_TOP3_ID_H
+#define MT6315_PMIC_TOP3_DIG_ID_MASK                        0xFF
+#define MT6315_PMIC_TOP3_DIG_ID_SHIFT                       0
+#define MT6315_PMIC_TOP3_ANA_MINOR_REV_ADDR                 \
+	MT6315_TOP3_REV0
+#define MT6315_PMIC_TOP3_ANA_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP3_ANA_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP3_ANA_MAJOR_REV_ADDR                 \
+	MT6315_TOP3_REV0
+#define MT6315_PMIC_TOP3_ANA_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP3_ANA_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP3_DIG_MINOR_REV_ADDR                 \
+	MT6315_TOP3_REV0_H
+#define MT6315_PMIC_TOP3_DIG_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP3_DIG_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_TOP3_DIG_MAJOR_REV_ADDR                 \
+	MT6315_TOP3_REV0_H
+#define MT6315_PMIC_TOP3_DIG_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_TOP3_DIG_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_TOP3_DSN_CBS_ADDR                       \
+	MT6315_TOP3_DSN_DBI
+#define MT6315_PMIC_TOP3_DSN_CBS_MASK                       0x3
+#define MT6315_PMIC_TOP3_DSN_CBS_SHIFT                      0
+#define MT6315_PMIC_TOP3_DSN_BIX_ADDR                       \
+	MT6315_TOP3_DSN_DBI
+#define MT6315_PMIC_TOP3_DSN_BIX_MASK                       0x3
+#define MT6315_PMIC_TOP3_DSN_BIX_SHIFT                      2
+#define MT6315_PMIC_TOP3_DSN_ESP_ADDR                       \
+	MT6315_TOP3_DSN_DBI_H
+#define MT6315_PMIC_TOP3_DSN_ESP_MASK                       0xFF
+#define MT6315_PMIC_TOP3_DSN_ESP_SHIFT                      0
+#define MT6315_PMIC_TOP3_DSN_FPI_ADDR                       \
+	MT6315_TOP3_DSN_DXI
+#define MT6315_PMIC_TOP3_DSN_FPI_MASK                       0xFF
+#define MT6315_PMIC_TOP3_DSN_FPI_SHIFT                      0
+#define MT6315_PMIC_RG_INT_EN_VBUCK1_OC_ADDR                \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_VBUCK1_OC_MASK                0x1
+#define MT6315_PMIC_RG_INT_EN_VBUCK1_OC_SHIFT               0
+#define MT6315_PMIC_RG_INT_EN_VBUCK2_OC_ADDR                \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_VBUCK2_OC_MASK                0x1
+#define MT6315_PMIC_RG_INT_EN_VBUCK2_OC_SHIFT               1
+#define MT6315_PMIC_RG_INT_EN_VBUCK3_OC_ADDR                \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_VBUCK3_OC_MASK                0x1
+#define MT6315_PMIC_RG_INT_EN_VBUCK3_OC_SHIFT               2
+#define MT6315_PMIC_RG_INT_EN_VBUCK4_OC_ADDR                \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_VBUCK4_OC_MASK                0x1
+#define MT6315_PMIC_RG_INT_EN_VBUCK4_OC_SHIFT               3
+#define MT6315_PMIC_RG_INT_EN_TEMP_BACK_110D_ADDR           \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_TEMP_BACK_110D_MASK           0x1
+#define MT6315_PMIC_RG_INT_EN_TEMP_BACK_110D_SHIFT          4
+#define MT6315_PMIC_RG_INT_EN_TEMP_OVER_125D_ADDR           \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_TEMP_OVER_125D_MASK           0x1
+#define MT6315_PMIC_RG_INT_EN_TEMP_OVER_125D_SHIFT          5
+#define MT6315_PMIC_RG_INT_EN_RCS0_ADDR                     \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_RCS0_MASK                     0x1
+#define MT6315_PMIC_RG_INT_EN_RCS0_SHIFT                    6
+#define MT6315_PMIC_RG_INT_EN_RCS1_ADDR                     \
+	MT6315_TOP_INT_CON0
+#define MT6315_PMIC_RG_INT_EN_RCS1_MASK                     0x1
+#define MT6315_PMIC_RG_INT_EN_RCS1_SHIFT                    7
+#define MT6315_PMIC_RG_TOP_INT_EN_CON0_SET_ADDR             \
+	MT6315_TOP_INT_CON0_SET
+#define MT6315_PMIC_RG_TOP_INT_EN_CON0_SET_MASK             0xFF
+#define MT6315_PMIC_RG_TOP_INT_EN_CON0_SET_SHIFT            0
+#define MT6315_PMIC_RG_TOP_INT_EN_CON0_CLR_ADDR             \
+	MT6315_TOP_INT_CON0_CLR
+#define MT6315_PMIC_RG_TOP_INT_EN_CON0_CLR_MASK             0xFF
+#define MT6315_PMIC_RG_TOP_INT_EN_CON0_CLR_SHIFT            0
+#define MT6315_PMIC_RG_INT_MASK_VBUCK1_OC_ADDR              \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_VBUCK1_OC_MASK              0x1
+#define MT6315_PMIC_RG_INT_MASK_VBUCK1_OC_SHIFT             0
+#define MT6315_PMIC_RG_INT_MASK_VBUCK2_OC_ADDR              \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_VBUCK2_OC_MASK              0x1
+#define MT6315_PMIC_RG_INT_MASK_VBUCK2_OC_SHIFT             1
+#define MT6315_PMIC_RG_INT_MASK_VBUCK3_OC_ADDR              \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_VBUCK3_OC_MASK              0x1
+#define MT6315_PMIC_RG_INT_MASK_VBUCK3_OC_SHIFT             2
+#define MT6315_PMIC_RG_INT_MASK_VBUCK4_OC_ADDR              \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_VBUCK4_OC_MASK              0x1
+#define MT6315_PMIC_RG_INT_MASK_VBUCK4_OC_SHIFT             3
+#define MT6315_PMIC_RG_INT_MASK_TEMP_BACK_110D_ADDR         \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_TEMP_BACK_110D_MASK         0x1
+#define MT6315_PMIC_RG_INT_MASK_TEMP_BACK_110D_SHIFT        4
+#define MT6315_PMIC_RG_INT_MASK_TEMP_OVER_125D_ADDR         \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_TEMP_OVER_125D_MASK         0x1
+#define MT6315_PMIC_RG_INT_MASK_TEMP_OVER_125D_SHIFT        5
+#define MT6315_PMIC_RG_INT_MASK_RCS0_ADDR                   \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_RCS0_MASK                   0x1
+#define MT6315_PMIC_RG_INT_MASK_RCS0_SHIFT                  6
+#define MT6315_PMIC_RG_INT_MASK_RCS1_ADDR                   \
+	MT6315_TOP_INT_MASK_CON0
+#define MT6315_PMIC_RG_INT_MASK_RCS1_MASK                   0x1
+#define MT6315_PMIC_RG_INT_MASK_RCS1_SHIFT                  7
+#define MT6315_PMIC_RG_TOP_INT_MASK_CON0_SET_ADDR           \
+	MT6315_TOP_INT_MASK_CON0_SET
+#define MT6315_PMIC_RG_TOP_INT_MASK_CON0_SET_MASK           0xFF
+#define MT6315_PMIC_RG_TOP_INT_MASK_CON0_SET_SHIFT          0
+#define MT6315_PMIC_RG_TOP_INT_MASK_CON0_CLR_ADDR           \
+	MT6315_TOP_INT_MASK_CON0_CLR
+#define MT6315_PMIC_RG_TOP_INT_MASK_CON0_CLR_MASK           0xFF
+#define MT6315_PMIC_RG_TOP_INT_MASK_CON0_CLR_SHIFT          0
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK1_OC_ADDR            \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK1_OC_MASK            0x1
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK1_OC_SHIFT           0
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK2_OC_ADDR            \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK2_OC_MASK            0x1
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK2_OC_SHIFT           1
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK3_OC_ADDR            \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK3_OC_MASK            0x1
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK3_OC_SHIFT           2
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK4_OC_ADDR            \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK4_OC_MASK            0x1
+#define MT6315_PMIC_RG_INT_STATUS_VBUCK4_OC_SHIFT           3
+#define MT6315_PMIC_RG_INT_STATUS_TEMP_BACK_110D_ADDR       \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_TEMP_BACK_110D_MASK       0x1
+#define MT6315_PMIC_RG_INT_STATUS_TEMP_BACK_110D_SHIFT      4
+#define MT6315_PMIC_RG_INT_STATUS_TEMP_OVER_125D_ADDR       \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_TEMP_OVER_125D_MASK       0x1
+#define MT6315_PMIC_RG_INT_STATUS_TEMP_OVER_125D_SHIFT      5
+#define MT6315_PMIC_RG_INT_STATUS_RCS0_ADDR                 \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_RCS0_MASK                 0x1
+#define MT6315_PMIC_RG_INT_STATUS_RCS0_SHIFT                6
+#define MT6315_PMIC_RG_INT_STATUS_RCS1_ADDR                 \
+	MT6315_TOP_INT_STATUS0
+#define MT6315_PMIC_RG_INT_STATUS_RCS1_MASK                 0x1
+#define MT6315_PMIC_RG_INT_STATUS_RCS1_SHIFT                7
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK1_OC_ADDR        \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK1_OC_MASK        0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK1_OC_SHIFT       0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK2_OC_ADDR        \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK2_OC_MASK        0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK2_OC_SHIFT       1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK3_OC_ADDR        \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK3_OC_MASK        0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK3_OC_SHIFT       2
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK4_OC_ADDR        \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK4_OC_MASK        0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_VBUCK4_OC_SHIFT       3
+#define MT6315_PMIC_RG_INT_RAW_STATUS_TEMP_BACK_110D_ADDR   \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_TEMP_BACK_110D_MASK   0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_TEMP_BACK_110D_SHIFT  4
+#define MT6315_PMIC_RG_INT_RAW_STATUS_TEMP_OVER_125D_ADDR   \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_TEMP_OVER_125D_MASK   0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_TEMP_OVER_125D_SHIFT  5
+#define MT6315_PMIC_RG_INT_RAW_STATUS_RCS0_ADDR             \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_RCS0_MASK             0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_RCS0_SHIFT            6
+#define MT6315_PMIC_RG_INT_RAW_STATUS_RCS1_ADDR             \
+	MT6315_TOP_INT_RAW_STATUS0
+#define MT6315_PMIC_RG_INT_RAW_STATUS_RCS1_MASK             0x1
+#define MT6315_PMIC_RG_INT_RAW_STATUS_RCS1_SHIFT            7
+#define MT6315_PMIC_RG_INT_POLARITY_ADDR                    \
+	MT6315_TOP_INT_CON1
+#define MT6315_PMIC_RG_INT_POLARITY_MASK                    0x1
+#define MT6315_PMIC_RG_INT_POLARITY_SHIFT                   0
+#define MT6315_PMIC_PMRC_EN_ADDR                            \
+	MT6315_PMRC_CON0
+#define MT6315_PMIC_PMRC_EN_MASK                            0xFF
+#define MT6315_PMIC_PMRC_EN_SHIFT                           0
+#define MT6315_PMIC_RG_PMRC_CON0_SET_ADDR                   \
+	MT6315_PMRC_CON0_SET
+#define MT6315_PMIC_RG_PMRC_CON0_SET_MASK                   0xFF
+#define MT6315_PMIC_RG_PMRC_CON0_SET_SHIFT                  0
+#define MT6315_PMIC_RG_PMRC_CON0_CLR_ADDR                   \
+	MT6315_PMRC_CON0_CLR
+#define MT6315_PMIC_RG_PMRC_CON0_CLR_MASK                   0xFF
+#define MT6315_PMIC_RG_PMRC_CON0_CLR_SHIFT                  0
+#define MT6315_PMIC_RG_VR_SPM_MODE_ADDR                     \
+	MT6315_PMRC_CON1
+#define MT6315_PMIC_RG_VR_SPM_MODE_MASK                     0x1
+#define MT6315_PMIC_RG_VR_SPM_MODE_SHIFT                    0
+#define MT6315_PMIC_RG_TOP_SPM_MODE_ADDR                    \
+	MT6315_PMRC_CON1
+#define MT6315_PMIC_RG_TOP_SPM_MODE_MASK                    0x1
+#define MT6315_PMIC_RG_TOP_SPM_MODE_SHIFT                   1
+#define MT6315_PMIC_RG_PMRC_CON1_SET_ADDR                   \
+	MT6315_PMRC_CON1_SET
+#define MT6315_PMIC_RG_PMRC_CON1_SET_MASK                   0xFF
+#define MT6315_PMIC_RG_PMRC_CON1_SET_SHIFT                  0
+#define MT6315_PMIC_RG_PMRC_CON1_CLR_ADDR                   \
+	MT6315_PMRC_CON1_CLR
+#define MT6315_PMIC_RG_PMRC_CON1_CLR_MASK                   0xFF
+#define MT6315_PMIC_RG_PMRC_CON1_CLR_SHIFT                  0
+#define MT6315_PMIC_RG_LDO_VDIG18_LP_ADDR                   \
+	MT6315_VDIG18_CON0
+#define MT6315_PMIC_RG_LDO_VDIG18_LP_MASK                   0x1
+#define MT6315_PMIC_RG_LDO_VDIG18_LP_SHIFT                  0
+#define MT6315_PMIC_RG_LDO_VDIG18_SW_OP_EN_ADDR             \
+	MT6315_VDIG18_CON0
+#define MT6315_PMIC_RG_LDO_VDIG18_SW_OP_EN_MASK             0x1
+#define MT6315_PMIC_RG_LDO_VDIG18_SW_OP_EN_SHIFT            1
+#define MT6315_PMIC_RG_LDO_VDIG18_HW_OP_EN_ADDR             \
+	MT6315_VDIG18_CON0
+#define MT6315_PMIC_RG_LDO_VDIG18_HW_OP_EN_MASK             0x1
+#define MT6315_PMIC_RG_LDO_VDIG18_HW_OP_EN_SHIFT            2
+#define MT6315_PMIC_RG_VDIG18_MODE_SW_SEL_ADDR              \
+	MT6315_VDIG18_CON1
+#define MT6315_PMIC_RG_VDIG18_MODE_SW_SEL_MASK              0x1
+#define MT6315_PMIC_RG_VDIG18_MODE_SW_SEL_SHIFT             0
+#define MT6315_PMIC_RG_VDIG18_MODE_1_SW_ADDR                \
+	MT6315_VDIG18_CON1
+#define MT6315_PMIC_RG_VDIG18_MODE_1_SW_MASK                0x1
+#define MT6315_PMIC_RG_VDIG18_MODE_1_SW_SHIFT               1
+#define MT6315_PMIC_RG_VDIG18_MODE_2_SW_ADDR                \
+	MT6315_VDIG18_CON1
+#define MT6315_PMIC_RG_VDIG18_MODE_2_SW_MASK                0x1
+#define MT6315_PMIC_RG_VDIG18_MODE_2_SW_SHIFT               2
+#define MT6315_PMIC_RG_VDIG18_PWROFF_OP_EN_ADDR             \
+	MT6315_VDIG18_CON1
+#define MT6315_PMIC_RG_VDIG18_PWROFF_OP_EN_MASK             0x1
+#define MT6315_PMIC_RG_VDIG18_PWROFF_OP_EN_SHIFT            4
+#define MT6315_PMIC_PLT0_ANA_ID_ADDR                        \
+	MT6315_PLT0_ID_ANA_ID
+#define MT6315_PMIC_PLT0_ANA_ID_MASK                        0xFF
+#define MT6315_PMIC_PLT0_ANA_ID_SHIFT                       0
+#define MT6315_PMIC_PLT0_DIG_ID_ADDR                        \
+	MT6315_PLT0_ID_DIG_ID
+#define MT6315_PMIC_PLT0_DIG_ID_MASK                        0xFF
+#define MT6315_PMIC_PLT0_DIG_ID_SHIFT                       0
+#define MT6315_PMIC_PLT0_ANA_MINOR_REV_ADDR                 \
+	MT6315_PLT0_REV0
+#define MT6315_PMIC_PLT0_ANA_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_PLT0_ANA_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_PLT0_ANA_MAJOR_REV_ADDR                 \
+	MT6315_PLT0_REV0
+#define MT6315_PMIC_PLT0_ANA_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_PLT0_ANA_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_PLT0_DIG_MINOR_REV_ADDR                 \
+	MT6315_PLT0_REV1
+#define MT6315_PMIC_PLT0_DIG_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_PLT0_DIG_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_PLT0_DIG_MAJOR_REV_ADDR                 \
+	MT6315_PLT0_REV1
+#define MT6315_PMIC_PLT0_DIG_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_PLT0_DIG_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_PLT0_DSN_CBS_ADDR                       \
+	MT6315_PLT0_REV2
+#define MT6315_PMIC_PLT0_DSN_CBS_MASK                       0x3
+#define MT6315_PMIC_PLT0_DSN_CBS_SHIFT                      0
+#define MT6315_PMIC_PLT0_DSN_BIX_ADDR                       \
+	MT6315_PLT0_REV2
+#define MT6315_PMIC_PLT0_DSN_BIX_MASK                       0x3
+#define MT6315_PMIC_PLT0_DSN_BIX_SHIFT                      2
+#define MT6315_PMIC_PLT0_DSN_ESP_ADDR                       \
+	MT6315_PLT0_REV3
+#define MT6315_PMIC_PLT0_DSN_ESP_MASK                       0xFF
+#define MT6315_PMIC_PLT0_DSN_ESP_SHIFT                      0
+#define MT6315_PMIC_PLT0_DSN_FPI_ADDR                       \
+	MT6315_PLT0_DSN_DXI
+#define MT6315_PMIC_PLT0_DSN_FPI_MASK                       0xFF
+#define MT6315_PMIC_PLT0_DSN_FPI_SHIFT                      0
+#define MT6315_PMIC_DA_STRUP_OSC_TRIM_ADDR                  \
+	MT6315_TOP_CLK_TRIM_0
+#define MT6315_PMIC_DA_STRUP_OSC_TRIM_MASK                  0x3F
+#define MT6315_PMIC_DA_STRUP_OSC_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_OSC_128K_TRIM_EN_ADDR                \
+	MT6315_TOP_CLK_TRIM_1
+#define MT6315_PMIC_RG_OSC_128K_TRIM_EN_MASK                0x1
+#define MT6315_PMIC_RG_OSC_128K_TRIM_EN_SHIFT               0
+#define MT6315_PMIC_RG_OSC_128K_TRIM_RATE_ADDR              \
+	MT6315_TOP_CLK_TRIM_1
+#define MT6315_PMIC_RG_OSC_128K_TRIM_RATE_MASK              0x3
+#define MT6315_PMIC_RG_OSC_128K_TRIM_RATE_SHIFT             1
+#define MT6315_PMIC_DA_SMPS_OSC_TRIM_ADDR                   \
+	MT6315_TOP_CLK_TRIM_2
+#define MT6315_PMIC_DA_SMPS_OSC_TRIM_MASK                   0x3F
+#define MT6315_PMIC_DA_SMPS_OSC_TRIM_SHIFT                  0
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_EN_ADDR                 \
+	MT6315_TOP_CLK_TRIM_3
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_EN_MASK                 0x1
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_EN_SHIFT                0
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_RATE_ADDR               \
+	MT6315_TOP_CLK_TRIM_3
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_RATE_MASK               0x3
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_RATE_SHIFT              1
+#define MT6315_PMIC_RG_BUCK_BANK_LP_ACS_EN_ADDR             \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_BUCK_BANK_LP_ACS_EN_MASK             0x1
+#define MT6315_PMIC_RG_BUCK_BANK_LP_ACS_EN_SHIFT            0
+#define MT6315_PMIC_RG_PSC_BANK_LP_ACS_EN_ADDR              \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_PSC_BANK_LP_ACS_EN_MASK              0x1
+#define MT6315_PMIC_RG_PSC_BANK_LP_ACS_EN_SHIFT             1
+#define MT6315_PMIC_RG_TOP0_BANK_LP_ACS_EN_ADDR             \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_TOP0_BANK_LP_ACS_EN_MASK             0x1
+#define MT6315_PMIC_RG_TOP0_BANK_LP_ACS_EN_SHIFT            2
+#define MT6315_PMIC_RG_TOP1_BANK_LP_ACS_EN_ADDR             \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_TOP1_BANK_LP_ACS_EN_MASK             0x1
+#define MT6315_PMIC_RG_TOP1_BANK_LP_ACS_EN_SHIFT            3
+#define MT6315_PMIC_RG_TOP2_BANK_LP_ACS_EN_ADDR             \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_TOP2_BANK_LP_ACS_EN_MASK             0x1
+#define MT6315_PMIC_RG_TOP2_BANK_LP_ACS_EN_SHIFT            4
+#define MT6315_PMIC_RG_TOP3_BANK_LP_ACS_EN_ADDR             \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_TOP3_BANK_LP_ACS_EN_MASK             0x1
+#define MT6315_PMIC_RG_TOP3_BANK_LP_ACS_EN_SHIFT            5
+#define MT6315_PMIC_RG_PLT0_BANK_LP_ACS_EN_ADDR             \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_PLT0_BANK_LP_ACS_EN_MASK             0x1
+#define MT6315_PMIC_RG_PLT0_BANK_LP_ACS_EN_SHIFT            6
+#define MT6315_PMIC_RG_RSV_BANK_LP_ACS_EN_ADDR              \
+	MT6315_PLT_CON0
+#define MT6315_PMIC_RG_RSV_BANK_LP_ACS_EN_MASK              0x1
+#define MT6315_PMIC_RG_RSV_BANK_LP_ACS_EN_SHIFT             7
+#define MT6315_PMIC_RG_OTP_PA_ADDR                          \
+	MT6315_OTP_CON0
+#define MT6315_PMIC_RG_OTP_PA_MASK                          0x7F
+#define MT6315_PMIC_RG_OTP_PA_SHIFT                         0
+#define MT6315_PMIC_RG_OTP_PDIN_L_ADDR                      \
+	MT6315_OTP_CON1
+#define MT6315_PMIC_RG_OTP_PDIN_L_MASK                      0xFF
+#define MT6315_PMIC_RG_OTP_PDIN_L_SHIFT                     0
+#define MT6315_PMIC_RG_OTP_PDIN_H_ADDR                      \
+	MT6315_OTP_CON2
+#define MT6315_PMIC_RG_OTP_PDIN_H_MASK                      0xFF
+#define MT6315_PMIC_RG_OTP_PDIN_H_SHIFT                     0
+#define MT6315_PMIC_RG_OTP_PTM_ADDR                         \
+	MT6315_OTP_CON3
+#define MT6315_PMIC_RG_OTP_PTM_MASK                         0x3
+#define MT6315_PMIC_RG_OTP_PTM_SHIFT                        0
+#define MT6315_PMIC_RG_OTP_PWE_ADDR                         \
+	MT6315_OTP_CON4
+#define MT6315_PMIC_RG_OTP_PWE_MASK                         0x3
+#define MT6315_PMIC_RG_OTP_PWE_SHIFT                        0
+#define MT6315_PMIC_RG_OTP_PPROG_ADDR                       \
+	MT6315_OTP_CON5
+#define MT6315_PMIC_RG_OTP_PPROG_MASK                       0x1
+#define MT6315_PMIC_RG_OTP_PPROG_SHIFT                      0
+#define MT6315_PMIC_RG_OTP_PWE_SRC_ADDR                     \
+	MT6315_OTP_CON6
+#define MT6315_PMIC_RG_OTP_PWE_SRC_MASK                     0x1
+#define MT6315_PMIC_RG_OTP_PWE_SRC_SHIFT                    0
+#define MT6315_PMIC_RG_OTP_PROG_PKEY_ADDR                   \
+	MT6315_OTP_CON7
+#define MT6315_PMIC_RG_OTP_PROG_PKEY_MASK                   0xFF
+#define MT6315_PMIC_RG_OTP_PROG_PKEY_SHIFT                  0
+#define MT6315_PMIC_RG_OTP_PROG_PKEY_H_ADDR                 \
+	MT6315_OTP_CON8
+#define MT6315_PMIC_RG_OTP_PROG_PKEY_H_MASK                 0xFF
+#define MT6315_PMIC_RG_OTP_PROG_PKEY_H_SHIFT                0
+#define MT6315_PMIC_RG_OTP_RD_PKEY_ADDR                     \
+	MT6315_OTP_CON9
+#define MT6315_PMIC_RG_OTP_RD_PKEY_MASK                     0xFF
+#define MT6315_PMIC_RG_OTP_RD_PKEY_SHIFT                    0
+#define MT6315_PMIC_RG_OTP_RD_PKEY_H_ADDR                   \
+	MT6315_OTP_CON10
+#define MT6315_PMIC_RG_OTP_RD_PKEY_H_MASK                   0xFF
+#define MT6315_PMIC_RG_OTP_RD_PKEY_H_SHIFT                  0
+#define MT6315_PMIC_RG_OTP_RD_TRIG_ADDR                     \
+	MT6315_OTP_CON11
+#define MT6315_PMIC_RG_OTP_RD_TRIG_MASK                     0x1
+#define MT6315_PMIC_RG_OTP_RD_TRIG_SHIFT                    0
+#define MT6315_PMIC_RG_RD_RDY_BYPASS_ADDR                   \
+	MT6315_OTP_CON12
+#define MT6315_PMIC_RG_RD_RDY_BYPASS_MASK                   0x1
+#define MT6315_PMIC_RG_RD_RDY_BYPASS_SHIFT                  0
+#define MT6315_PMIC_RG_SKIP_OTP_OUT_ADDR                    \
+	MT6315_OTP_CON13
+#define MT6315_PMIC_RG_SKIP_OTP_OUT_MASK                    0x1
+#define MT6315_PMIC_RG_SKIP_OTP_OUT_SHIFT                   0
+#define MT6315_PMIC_RG_OTP_RD_SW_ADDR                       \
+	MT6315_OTP_CON14
+#define MT6315_PMIC_RG_OTP_RD_SW_MASK                       0x1
+#define MT6315_PMIC_RG_OTP_RD_SW_SHIFT                      0
+#define MT6315_PMIC_RG_OTP_DOUT_SW_ADDR                     \
+	MT6315_OTP_CON15
+#define MT6315_PMIC_RG_OTP_DOUT_SW_MASK                     0xFF
+#define MT6315_PMIC_RG_OTP_DOUT_SW_SHIFT                    0
+#define MT6315_PMIC_RG_OTP_DOUT_SW_H_ADDR                   \
+	MT6315_OTP_CON16
+#define MT6315_PMIC_RG_OTP_DOUT_SW_H_MASK                   0xFF
+#define MT6315_PMIC_RG_OTP_DOUT_SW_H_SHIFT                  0
+#define MT6315_PMIC_RG_OTP_RD_BUSY_ADDR                     \
+	MT6315_OTP_CON17
+#define MT6315_PMIC_RG_OTP_RD_BUSY_MASK                     0x1
+#define MT6315_PMIC_RG_OTP_RD_BUSY_SHIFT                    0
+#define MT6315_PMIC_RG_OTP_RD_ACK_ADDR                      \
+	MT6315_OTP_CON17
+#define MT6315_PMIC_RG_OTP_RD_ACK_MASK                      0x1
+#define MT6315_PMIC_RG_OTP_RD_ACK_SHIFT                     2
+#define MT6315_PMIC_RG_OTP_PA_SW_ADDR                       \
+	MT6315_OTP_CON18
+#define MT6315_PMIC_RG_OTP_PA_SW_MASK                       0x7F
+#define MT6315_PMIC_RG_OTP_PA_SW_SHIFT                      0
+#define MT6315_PMIC_TMA_KEY_ADDR                            \
+	MT6315_TOP_TMA_KEY
+#define MT6315_PMIC_TMA_KEY_MASK                            0xFF
+#define MT6315_PMIC_TMA_KEY_SHIFT                           0
+#define MT6315_PMIC_TMA_KEY_H_ADDR                          \
+	MT6315_TOP_TMA_KEY_H
+#define MT6315_PMIC_TMA_KEY_H_MASK                          0xFF
+#define MT6315_PMIC_TMA_KEY_H_SHIFT                         0
+#define MT6315_PMIC_ANA_WRITE_KEY_ADDR                      \
+	MT6315_TOP_ANA_KEY
+#define MT6315_PMIC_ANA_WRITE_KEY_MASK                      0xFF
+#define MT6315_PMIC_ANA_WRITE_KEY_SHIFT                     0
+#define MT6315_PMIC_ANA_WRITE_KEY_H_ADDR                    \
+	MT6315_TOP_ANA_KEY_H
+#define MT6315_PMIC_ANA_WRITE_KEY_H_MASK                    0xFF
+#define MT6315_PMIC_ANA_WRITE_KEY_H_SHIFT                   0
+#define MT6315_PMIC_TOP_MDB_RSV0_ADDR                       \
+	MT6315_TOP_MDB_CONF0
+#define MT6315_PMIC_TOP_MDB_RSV0_MASK                       0xFF
+#define MT6315_PMIC_TOP_MDB_RSV0_SHIFT                      0
+#define MT6315_PMIC_TOP_MDB_RSV0_H_ADDR                     \
+	MT6315_TOP_MDB_CONF0_H
+#define MT6315_PMIC_TOP_MDB_RSV0_H_MASK                     0xFF
+#define MT6315_PMIC_TOP_MDB_RSV0_H_SHIFT                    0
+#define MT6315_PMIC_TOP_MDB_RSV1_ADDR                       \
+	MT6315_TOP_MDB_CONF1
+#define MT6315_PMIC_TOP_MDB_RSV1_MASK                       0xFF
+#define MT6315_PMIC_TOP_MDB_RSV1_SHIFT                      0
+#define MT6315_PMIC_TOP_MDB_RSV1_H_ADDR                     \
+	MT6315_TOP_MDB_CONF1_H
+#define MT6315_PMIC_TOP_MDB_RSV1_H_MASK                     0xFF
+#define MT6315_PMIC_TOP_MDB_RSV1_H_SHIFT                    0
+#define MT6315_PMIC_RG_MDB_DM1_DS_EN_ADDR                   \
+	MT6315_TOP_MDB_CONF2
+#define MT6315_PMIC_RG_MDB_DM1_DS_EN_MASK                   0x1
+#define MT6315_PMIC_RG_MDB_DM1_DS_EN_SHIFT                  0
+#define MT6315_PMIC_RG_AUTO_LOAD_FORCE_ADDR                 \
+	MT6315_TOP_MDB_CONF2
+#define MT6315_PMIC_RG_AUTO_LOAD_FORCE_MASK                 0x1
+#define MT6315_PMIC_RG_AUTO_LOAD_FORCE_SHIFT                1
+#define MT6315_PMIC_RG_OTP_WRITE_SEL_ADDR                   \
+	MT6315_TOP_MDB_CONF2
+#define MT6315_PMIC_RG_OTP_WRITE_SEL_MASK                   0x1
+#define MT6315_PMIC_RG_OTP_WRITE_SEL_SHIFT                  2
+#define MT6315_PMIC_DIG_WPK_KEY_ADDR                        \
+	MT6315_TOP_DIG_WPK
+#define MT6315_PMIC_DIG_WPK_KEY_MASK                        0xFF
+#define MT6315_PMIC_DIG_WPK_KEY_SHIFT                       0
+#define MT6315_PMIC_DIG_WPK_KEY_H_ADDR                      \
+	MT6315_TOP_DIG_WPK_H
+#define MT6315_PMIC_DIG_WPK_KEY_H_MASK                      0xFF
+#define MT6315_PMIC_DIG_WPK_KEY_H_SHIFT                     0
+#define MT6315_PMIC_RG_EXTADR_REG0_W_ADDR                   \
+	MT6315_SPMI_EXT_ADDR0
+#define MT6315_PMIC_RG_EXTADR_REG0_W_MASK                   0xFF
+#define MT6315_PMIC_RG_EXTADR_REG0_W_SHIFT                  0
+#define MT6315_PMIC_RG_EXTADR_REG0_W_H_ADDR                 \
+	MT6315_SPMI_EXT_ADDR0_H
+#define MT6315_PMIC_RG_EXTADR_REG0_W_H_MASK                 0xFF
+#define MT6315_PMIC_RG_EXTADR_REG0_W_H_SHIFT                0
+#define MT6315_PMIC_RG_EXTADR_EXT_REG_RW_ADDR               \
+	MT6315_SPMI_EXT_ADDR1
+#define MT6315_PMIC_RG_EXTADR_EXT_REG_RW_MASK               0xFF
+#define MT6315_PMIC_RG_EXTADR_EXT_REG_RW_SHIFT              0
+#define MT6315_PMIC_RG_EXTADR_REG_RW_ADDR                   \
+	MT6315_SPMI_EXT_ADDR2
+#define MT6315_PMIC_RG_EXTADR_REG_RW_MASK                   0xFF
+#define MT6315_PMIC_RG_EXTADR_REG_RW_SHIFT                  0
+#define MT6315_PMIC_RG_EXTADR_REG_RW_H_ADDR                 \
+	MT6315_SPMI_EXT_ADDR2_H
+#define MT6315_PMIC_RG_EXTADR_REG_RW_H_MASK                 0x7
+#define MT6315_PMIC_RG_EXTADR_REG_RW_H_SHIFT                0
+#define MT6315_PMIC_RG_SPMI_RXDATA_MD_ADDR                  \
+	MT6315_SPMI_EXT_ADDR2_H
+#define MT6315_PMIC_RG_SPMI_RXDATA_MD_MASK                  0x1
+#define MT6315_PMIC_RG_SPMI_RXDATA_MD_SHIFT                 3
+#define MT6315_PMIC_RG_SPMI_DLY_SEL_ADDR                    \
+	MT6315_SPMI_EXT_ADDR2_H
+#define MT6315_PMIC_RG_SPMI_DLY_SEL_MASK                    0xF
+#define MT6315_PMIC_RG_SPMI_DLY_SEL_SHIFT                   4
+#define MT6315_PMIC_RG_RCS_ENABLE_ADDR                      \
+	MT6315_SPMI_RCS_FUN0
+#define MT6315_PMIC_RG_RCS_ENABLE_MASK                      0x1
+#define MT6315_PMIC_RG_RCS_ENABLE_SHIFT                     0
+#define MT6315_PMIC_RG_RCS_ABIT_ADDR                        \
+	MT6315_SPMI_RCS_FUN0
+#define MT6315_PMIC_RG_RCS_ABIT_MASK                        0x1
+#define MT6315_PMIC_RG_RCS_ABIT_SHIFT                       1
+#define MT6315_PMIC_RG_RCS_CMD_ADDR                         \
+	MT6315_SPMI_RCS_FUN0
+#define MT6315_PMIC_RG_RCS_CMD_MASK                         0x3
+#define MT6315_PMIC_RG_RCS_CMD_SHIFT                        2
+#define MT6315_PMIC_RG_RCS_ID_ADDR                          \
+	MT6315_SPMI_RCS_FUN0
+#define MT6315_PMIC_RG_RCS_ID_MASK                          0xF
+#define MT6315_PMIC_RG_RCS_ID_SHIFT                         4
+#define MT6315_PMIC_RG_RCS_ADDR_ADDR                        \
+	MT6315_SPMI_RCS_FUN1
+#define MT6315_PMIC_RG_RCS_ADDR_MASK                        0xFF
+#define MT6315_PMIC_RG_RCS_ADDR_SHIFT                       0
+#define MT6315_PMIC_RG_INT_RCS0_ADDR                        \
+	MT6315_SPMI_RCS_FUN2
+#define MT6315_PMIC_RG_INT_RCS0_MASK                        0x1
+#define MT6315_PMIC_RG_INT_RCS0_SHIFT                       0
+#define MT6315_PMIC_RG_INT_RCS1_ADDR                        \
+	MT6315_SPMI_RCS_FUN2
+#define MT6315_PMIC_RG_INT_RCS1_MASK                        0x1
+#define MT6315_PMIC_RG_INT_RCS1_SHIFT                       1
+#define MT6315_PMIC_RG_INT_RCS1_CLR_ADDR                    \
+	MT6315_SPMI_RCS_FUN2
+#define MT6315_PMIC_RG_INT_RCS1_CLR_MASK                    0x1
+#define MT6315_PMIC_RG_INT_RCS1_CLR_SHIFT                   2
+#define MT6315_PMIC_RG_PARTY_ERR_CLR_ADDR                   \
+	MT6315_SPMI_RCS_FUN2
+#define MT6315_PMIC_RG_PARTY_ERR_CLR_MASK                   0x1
+#define MT6315_PMIC_RG_PARTY_ERR_CLR_SHIFT                  3
+#define MT6315_PMIC_RG_ADDR_WR_MATCH_ADDR                   \
+	MT6315_SPMI_WR_ADDR
+#define MT6315_PMIC_RG_ADDR_WR_MATCH_MASK                   0xFF
+#define MT6315_PMIC_RG_ADDR_WR_MATCH_SHIFT                  0
+#define MT6315_PMIC_RG_ADDR_WR_MATCH_H_ADDR                 \
+	MT6315_SPMI_WR_ADDR_H
+#define MT6315_PMIC_RG_ADDR_WR_MATCH_H_MASK                 0xFF
+#define MT6315_PMIC_RG_ADDR_WR_MATCH_H_SHIFT                0
+#define MT6315_PMIC_RG_RXDBG_ADDR0_ADDR                     \
+	MT6315_SPMI_DEBUG_ADDR0
+#define MT6315_PMIC_RG_RXDBG_ADDR0_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR0_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_ADDR0_H_ADDR                   \
+	MT6315_SPMI_DEBUG_ADDR0_H
+#define MT6315_PMIC_RG_RXDBG_ADDR0_H_MASK                   0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR0_H_SHIFT                  0
+#define MT6315_PMIC_RG_RXDBG_DATA0_ADDR                     \
+	MT6315_SPMI_DEBUG_DATA0
+#define MT6315_PMIC_RG_RXDBG_DATA0_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_DATA0_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_CMD0_ADDR                      \
+	MT6315_SPMI_DEBUG_CMD0
+#define MT6315_PMIC_RG_RXDBG_CMD0_MASK                      0x3
+#define MT6315_PMIC_RG_RXDBG_CMD0_SHIFT                     0
+#define MT6315_PMIC_RG_RXDBG_IDX_ADDR                       \
+	MT6315_SPMI_DEBUG_CMD0
+#define MT6315_PMIC_RG_RXDBG_IDX_MASK                       0x3
+#define MT6315_PMIC_RG_RXDBG_IDX_SHIFT                      2
+#define MT6315_PMIC_RG_RXDBG_ADDR1_ADDR                     \
+	MT6315_SPMI_DEBUG_ADDR1
+#define MT6315_PMIC_RG_RXDBG_ADDR1_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR1_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_ADDR1_H_ADDR                   \
+	MT6315_SPMI_DEBUG_ADDR1_H
+#define MT6315_PMIC_RG_RXDBG_ADDR1_H_MASK                   0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR1_H_SHIFT                  0
+#define MT6315_PMIC_RG_RXDBG_DATA1_ADDR                     \
+	MT6315_SPMI_DEBUG_DATA1
+#define MT6315_PMIC_RG_RXDBG_DATA1_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_DATA1_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_CMD1_ADDR                      \
+	MT6315_SPMI_DEBUG_CMD1
+#define MT6315_PMIC_RG_RXDBG_CMD1_MASK                      0x3
+#define MT6315_PMIC_RG_RXDBG_CMD1_SHIFT                     0
+#define MT6315_PMIC_RG_RXDBG_ADDR2_ADDR                     \
+	MT6315_SPMI_DEBUG_ADDR2
+#define MT6315_PMIC_RG_RXDBG_ADDR2_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR2_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_ADDR2_H_ADDR                   \
+	MT6315_SPMI_DEBUG_ADDR2_H
+#define MT6315_PMIC_RG_RXDBG_ADDR2_H_MASK                   0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR2_H_SHIFT                  0
+#define MT6315_PMIC_RG_RXDBG_DATA2_ADDR                     \
+	MT6315_SPMI_DEBUG_DATA2
+#define MT6315_PMIC_RG_RXDBG_DATA2_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_DATA2_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_CMD2_ADDR                      \
+	MT6315_SPMI_DEBUG_CMD2
+#define MT6315_PMIC_RG_RXDBG_CMD2_MASK                      0x3
+#define MT6315_PMIC_RG_RXDBG_CMD2_SHIFT                     0
+#define MT6315_PMIC_RG_RXDBG_ADDR3_ADDR                     \
+	MT6315_SPMI_DEBUG_ADDR3
+#define MT6315_PMIC_RG_RXDBG_ADDR3_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR3_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_ADDR3_H_ADDR                   \
+	MT6315_SPMI_DEBUG_ADDR3_H
+#define MT6315_PMIC_RG_RXDBG_ADDR3_H_MASK                   0xFF
+#define MT6315_PMIC_RG_RXDBG_ADDR3_H_SHIFT                  0
+#define MT6315_PMIC_RG_RXDBG_DATA3_ADDR                     \
+	MT6315_SPMI_DEBUG_DATA3
+#define MT6315_PMIC_RG_RXDBG_DATA3_MASK                     0xFF
+#define MT6315_PMIC_RG_RXDBG_DATA3_SHIFT                    0
+#define MT6315_PMIC_RG_RXDBG_CMD3_ADDR                      \
+	MT6315_SPMI_DEBUG_CMD3
+#define MT6315_PMIC_RG_RXDBG_CMD3_MASK                      0x3
+#define MT6315_PMIC_RG_RXDBG_CMD3_SHIFT                     0
+#define MT6315_PMIC_RG_PRTY_ERR_COMD0_ADDR                  \
+	MT6315_SPMI_PTRY_ERR0
+#define MT6315_PMIC_RG_PRTY_ERR_COMD0_MASK                  0x7
+#define MT6315_PMIC_RG_PRTY_ERR_COMD0_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE0_ADDR                  \
+	MT6315_SPMI_PTRY_ERR0
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE0_MASK                  0x3
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE0_SHIFT                 3
+#define MT6315_PMIC_RG_PRTY_ERR_IDX_ADDR                    \
+	MT6315_SPMI_PTRY_ERR0
+#define MT6315_PMIC_RG_PRTY_ERR_IDX_MASK                    0x7
+#define MT6315_PMIC_RG_PRTY_ERR_IDX_SHIFT                   5
+#define MT6315_PMIC_RG_PRTY_ERR_DATA0_ADDR                  \
+	MT6315_SPMI_PTRY_ERR1
+#define MT6315_PMIC_RG_PRTY_ERR_DATA0_MASK                  0xFF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA0_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_DATA0_H_ADDR                \
+	MT6315_SPMI_PTRY_ERR1_H
+#define MT6315_PMIC_RG_PRTY_ERR_DATA0_H_MASK                0xF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA0_H_SHIFT               0
+#define MT6315_PMIC_RG_PRTY_ERR_COMD1_ADDR                  \
+	MT6315_SPMI_PTRY_ERR2
+#define MT6315_PMIC_RG_PRTY_ERR_COMD1_MASK                  0x7
+#define MT6315_PMIC_RG_PRTY_ERR_COMD1_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE1_ADDR                  \
+	MT6315_SPMI_PTRY_ERR2
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE1_MASK                  0x3
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE1_SHIFT                 3
+#define MT6315_PMIC_RG_PRTY_ERR_DATA1_ADDR                  \
+	MT6315_SPMI_PTRY_ERR3
+#define MT6315_PMIC_RG_PRTY_ERR_DATA1_MASK                  0xFF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA1_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_DATA1_H_ADDR                \
+	MT6315_SPMI_PTRY_ERR3_H
+#define MT6315_PMIC_RG_PRTY_ERR_DATA1_H_MASK                0xF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA1_H_SHIFT               0
+#define MT6315_PMIC_RG_PRTY_ERR_COMD2_ADDR                  \
+	MT6315_SPMI_PTRY_ERR4
+#define MT6315_PMIC_RG_PRTY_ERR_COMD2_MASK                  0x7
+#define MT6315_PMIC_RG_PRTY_ERR_COMD2_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE2_ADDR                  \
+	MT6315_SPMI_PTRY_ERR4
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE2_MASK                  0x3
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE2_SHIFT                 3
+#define MT6315_PMIC_RG_PRTY_ERR_DATA2_ADDR                  \
+	MT6315_SPMI_PTRY_ERR5
+#define MT6315_PMIC_RG_PRTY_ERR_DATA2_MASK                  0xFF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA2_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_DATA2_H_ADDR                \
+	MT6315_SPMI_PTRY_ERR5_H
+#define MT6315_PMIC_RG_PRTY_ERR_DATA2_H_MASK                0xF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA2_H_SHIFT               0
+#define MT6315_PMIC_RG_PRTY_ERR_COMD3_ADDR                  \
+	MT6315_SPMI_PTRY_ERR6
+#define MT6315_PMIC_RG_PRTY_ERR_COMD3_MASK                  0x7
+#define MT6315_PMIC_RG_PRTY_ERR_COMD3_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE3_ADDR                  \
+	MT6315_SPMI_PTRY_ERR6
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE3_MASK                  0x3
+#define MT6315_PMIC_RG_PRTY_ERR_TYPE3_SHIFT                 3
+#define MT6315_PMIC_RG_PRTY_ERR_DATA3_ADDR                  \
+	MT6315_SPMI_PTRY_ERR7
+#define MT6315_PMIC_RG_PRTY_ERR_DATA3_MASK                  0xFF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA3_SHIFT                 0
+#define MT6315_PMIC_RG_PRTY_ERR_DATA3_H_ADDR                \
+	MT6315_SPMI_PTRY_ERR7_H
+#define MT6315_PMIC_RG_PRTY_ERR_DATA3_H_MASK                0xF
+#define MT6315_PMIC_RG_PRTY_ERR_DATA3_H_SHIFT               0
+#define MT6315_PMIC_PLT0_ELR_LEN_ADDR                       \
+	MT6315_PLT0_ELR_NUM
+#define MT6315_PMIC_PLT0_ELR_LEN_MASK                       0xFF
+#define MT6315_PMIC_PLT0_ELR_LEN_SHIFT                      0
+#define MT6315_PMIC_RG_OSC_128K_TRIM_ADDR                   \
+	MT6315_PLT0_ELR0
+#define MT6315_PMIC_RG_OSC_128K_TRIM_MASK                   0x3F
+#define MT6315_PMIC_RG_OSC_128K_TRIM_SHIFT                  0
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_ADDR                    \
+	MT6315_PLT0_ELR1
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_MASK                    0x3F
+#define MT6315_PMIC_RG_SMPS_4M_TRIM_SHIFT                   0
+#define MT6315_PMIC_PSC_TOP_ANA_ID_ADDR                     \
+	MT6315_PSC_TOP_ID_ANA
+#define MT6315_PMIC_PSC_TOP_ANA_ID_MASK                     0xFF
+#define MT6315_PMIC_PSC_TOP_ANA_ID_SHIFT                    0
+#define MT6315_PMIC_PSC_TOP_DIG_ID_ADDR                     \
+	MT6315_PSC_TOP_ID_DIG
+#define MT6315_PMIC_PSC_TOP_DIG_ID_MASK                     0xFF
+#define MT6315_PMIC_PSC_TOP_DIG_ID_SHIFT                    0
+#define MT6315_PMIC_PSC_TOP_ANA_MINOR_REV_ADDR              \
+	MT6315_PSC_TOP_REV0
+#define MT6315_PMIC_PSC_TOP_ANA_MINOR_REV_MASK              0xF
+#define MT6315_PMIC_PSC_TOP_ANA_MINOR_REV_SHIFT             0
+#define MT6315_PMIC_PSC_TOP_ANA_MAJOR_REV_ADDR              \
+	MT6315_PSC_TOP_REV0
+#define MT6315_PMIC_PSC_TOP_ANA_MAJOR_REV_MASK              0xF
+#define MT6315_PMIC_PSC_TOP_ANA_MAJOR_REV_SHIFT             4
+#define MT6315_PMIC_PSC_TOP_DIG_MINOR_REV_ADDR              \
+	MT6315_PSC_TOP_REV1
+#define MT6315_PMIC_PSC_TOP_DIG_MINOR_REV_MASK              0xF
+#define MT6315_PMIC_PSC_TOP_DIG_MINOR_REV_SHIFT             0
+#define MT6315_PMIC_PSC_TOP_DIG_MAJOR_REV_ADDR              \
+	MT6315_PSC_TOP_REV1
+#define MT6315_PMIC_PSC_TOP_DIG_MAJOR_REV_MASK              0xF
+#define MT6315_PMIC_PSC_TOP_DIG_MAJOR_REV_SHIFT             4
+#define MT6315_PMIC_PSC_TOP_CBS_ADDR                        \
+	MT6315_PSC_TOP_DBI0
+#define MT6315_PMIC_PSC_TOP_CBS_MASK                        0x3
+#define MT6315_PMIC_PSC_TOP_CBS_SHIFT                       0
+#define MT6315_PMIC_PSC_TOP_BIX_ADDR                        \
+	MT6315_PSC_TOP_DBI0
+#define MT6315_PMIC_PSC_TOP_BIX_MASK                        0x3
+#define MT6315_PMIC_PSC_TOP_BIX_SHIFT                       2
+#define MT6315_PMIC_PSC_TOP_ESP_ADDR                        \
+	MT6315_PSC_TOP_DBI1
+#define MT6315_PMIC_PSC_TOP_ESP_MASK                        0xFF
+#define MT6315_PMIC_PSC_TOP_ESP_SHIFT                       0
+#define MT6315_PMIC_PSC_TOP_FPI_ADDR                        \
+	MT6315_PSC_TOP_DXI
+#define MT6315_PMIC_PSC_TOP_FPI_MASK                        0xFF
+#define MT6315_PMIC_PSC_TOP_FPI_SHIFT                       0
+#define MT6315_PMIC_PSC_TOP_CLK_OFFSET_ADDR                 \
+	MT6315_PSC_TPM0
+#define MT6315_PMIC_PSC_TOP_CLK_OFFSET_MASK                 0xFF
+#define MT6315_PMIC_PSC_TOP_CLK_OFFSET_SHIFT                0
+#define MT6315_PMIC_PSC_TOP_RST_OFFSET_ADDR                 \
+	MT6315_PSC_TPM1
+#define MT6315_PMIC_PSC_TOP_RST_OFFSET_MASK                 0xFF
+#define MT6315_PMIC_PSC_TOP_RST_OFFSET_SHIFT                0
+#define MT6315_PMIC_PSC_TOP_INT_OFFSET_ADDR                 \
+	MT6315_PSC_TPM2
+#define MT6315_PMIC_PSC_TOP_INT_OFFSET_MASK                 0xFF
+#define MT6315_PMIC_PSC_TOP_INT_OFFSET_SHIFT                0
+#define MT6315_PMIC_BANK_PSEQ_SWRST_ADDR                    \
+	MT6315_PSC_TOP_RSTCTL
+#define MT6315_PMIC_BANK_PSEQ_SWRST_MASK                    0x1
+#define MT6315_PMIC_BANK_PSEQ_SWRST_SHIFT                   0
+#define MT6315_PMIC_BANK_STRUP_ANA0_SWRST_ADDR              \
+	MT6315_PSC_TOP_RSTCTL
+#define MT6315_PMIC_BANK_STRUP_ANA0_SWRST_MASK              0x1
+#define MT6315_PMIC_BANK_STRUP_ANA0_SWRST_SHIFT             1
+#define MT6315_PMIC_RG_PSC_MON_GRP_SEL_ADDR                 \
+	MT6315_PSC_TOP_MON_CTL
+#define MT6315_PMIC_RG_PSC_MON_GRP_SEL_MASK                 0x7
+#define MT6315_PMIC_RG_PSC_MON_GRP_SEL_SHIFT                0
+#define MT6315_PMIC_PSEQ_ANA_ID_ADDR                        \
+	MT6315_PSEQ_ID_ANA
+#define MT6315_PMIC_PSEQ_ANA_ID_MASK                        0xFF
+#define MT6315_PMIC_PSEQ_ANA_ID_SHIFT                       0
+#define MT6315_PMIC_PSEQ_DIG_ID_ADDR                        \
+	MT6315_PSEQ_ID_DIG
+#define MT6315_PMIC_PSEQ_DIG_ID_MASK                        0xFF
+#define MT6315_PMIC_PSEQ_DIG_ID_SHIFT                       0
+#define MT6315_PMIC_PSEQ_ANA_MINOR_REV_ADDR                 \
+	MT6315_PSEQ_REV0
+#define MT6315_PMIC_PSEQ_ANA_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_PSEQ_ANA_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_PSEQ_ANA_MAJOR_REV_ADDR                 \
+	MT6315_PSEQ_REV0
+#define MT6315_PMIC_PSEQ_ANA_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_PSEQ_ANA_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_PSEQ_DIG_MINOR_REV_ADDR                 \
+	MT6315_PSEQ_REV1
+#define MT6315_PMIC_PSEQ_DIG_MINOR_REV_MASK                 0xF
+#define MT6315_PMIC_PSEQ_DIG_MINOR_REV_SHIFT                0
+#define MT6315_PMIC_PSEQ_DIG_MAJOR_REV_ADDR                 \
+	MT6315_PSEQ_REV1
+#define MT6315_PMIC_PSEQ_DIG_MAJOR_REV_MASK                 0xF
+#define MT6315_PMIC_PSEQ_DIG_MAJOR_REV_SHIFT                4
+#define MT6315_PMIC_PSEQ_CBS_ADDR                           \
+	MT6315_PSEQ_DBI0
+#define MT6315_PMIC_PSEQ_CBS_MASK                           0x3
+#define MT6315_PMIC_PSEQ_CBS_SHIFT                          0
+#define MT6315_PMIC_PSEQ_BIX_ADDR                           \
+	MT6315_PSEQ_DBI0
+#define MT6315_PMIC_PSEQ_BIX_MASK                           0x3
+#define MT6315_PMIC_PSEQ_BIX_SHIFT                          2
+#define MT6315_PMIC_PSEQ_ESP_ADDR                           \
+	MT6315_PSEQ_DBI1
+#define MT6315_PMIC_PSEQ_ESP_MASK                           0xFF
+#define MT6315_PMIC_PSEQ_ESP_SHIFT                          0
+#define MT6315_PMIC_PSEQ_FPI_ADDR                           \
+	MT6315_PSEQ_DXI
+#define MT6315_PMIC_PSEQ_FPI_MASK                           0xFF
+#define MT6315_PMIC_PSEQ_FPI_SHIFT                          0
+#define MT6315_PMIC_RG_PGODLY_INTV_ADDR                     \
+	MT6315_PPCCTL
+#define MT6315_PMIC_RG_PGODLY_INTV_MASK                     0x3
+#define MT6315_PMIC_RG_PGODLY_INTV_SHIFT                    0
+#define MT6315_PMIC_RG_RSV_SWREG_ADDR                       \
+	MT6315_STRUP_CON0
+#define MT6315_PMIC_RG_RSV_SWREG_MASK                       0xFF
+#define MT6315_PMIC_RG_RSV_SWREG_SHIFT                      0
+#define MT6315_PMIC_RG_THR_TEST_EN_ADDR                     \
+	MT6315_STRUP_CON1
+#define MT6315_PMIC_RG_THR_TEST_EN_MASK                     0x1
+#define MT6315_PMIC_RG_THR_TEST_EN_SHIFT                    0
+#define MT6315_PMIC_RG_THR_TEST_ADDR                        \
+	MT6315_STRUP_CON1
+#define MT6315_PMIC_RG_THR_TEST_MASK                        0x1F
+#define MT6315_PMIC_RG_THR_TEST_SHIFT                       1
+#define MT6315_PMIC_RG_THR_DET_DIS_ADDR                     \
+	MT6315_STRUP_CON1
+#define MT6315_PMIC_RG_THR_DET_DIS_MASK                     0x1
+#define MT6315_PMIC_RG_THR_DET_DIS_SHIFT                    6
+#define MT6315_PMIC_RG_STRUP_VBUCK4_PG_ENB_ADDR             \
+	MT6315_STRUP_PGENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK4_PG_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK4_PG_ENB_SHIFT            4
+#define MT6315_PMIC_RG_STRUP_VBUCK3_PG_ENB_ADDR             \
+	MT6315_STRUP_PGENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK3_PG_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK3_PG_ENB_SHIFT            5
+#define MT6315_PMIC_RG_STRUP_VBUCK2_PG_ENB_ADDR             \
+	MT6315_STRUP_PGENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK2_PG_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK2_PG_ENB_SHIFT            6
+#define MT6315_PMIC_RG_STRUP_VBUCK1_PG_ENB_ADDR             \
+	MT6315_STRUP_PGENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK1_PG_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK1_PG_ENB_SHIFT            7
+#define MT6315_PMIC_RG_STRUP_VBUCK4_OC_ENB_ADDR             \
+	MT6315_STRUP_OCENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK4_OC_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK4_OC_ENB_SHIFT            4
+#define MT6315_PMIC_RG_STRUP_VBUCK3_OC_ENB_ADDR             \
+	MT6315_STRUP_OCENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK3_OC_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK3_OC_ENB_SHIFT            5
+#define MT6315_PMIC_RG_STRUP_VBUCK2_OC_ENB_ADDR             \
+	MT6315_STRUP_OCENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK2_OC_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK2_OC_ENB_SHIFT            6
+#define MT6315_PMIC_RG_STRUP_VBUCK1_OC_ENB_ADDR             \
+	MT6315_STRUP_OCENB0
+#define MT6315_PMIC_RG_STRUP_VBUCK1_OC_ENB_MASK             0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK1_OC_ENB_SHIFT            7
+#define MT6315_PMIC_RG_KEYPWR_VBUCK4_EN_ADDR                \
+	MT6315_BUCK_KEYPWR
+#define MT6315_PMIC_RG_KEYPWR_VBUCK4_EN_MASK                0x1
+#define MT6315_PMIC_RG_KEYPWR_VBUCK4_EN_SHIFT               4
+#define MT6315_PMIC_RG_KEYPWR_VBUCK3_EN_ADDR                \
+	MT6315_BUCK_KEYPWR
+#define MT6315_PMIC_RG_KEYPWR_VBUCK3_EN_MASK                0x1
+#define MT6315_PMIC_RG_KEYPWR_VBUCK3_EN_SHIFT               5
+#define MT6315_PMIC_RG_KEYPWR_VBUCK2_EN_ADDR                \
+	MT6315_BUCK_KEYPWR
+#define MT6315_PMIC_RG_KEYPWR_VBUCK2_EN_MASK                0x1
+#define MT6315_PMIC_RG_KEYPWR_VBUCK2_EN_SHIFT               6
+#define MT6315_PMIC_RG_KEYPWR_VBUCK1_EN_ADDR                \
+	MT6315_BUCK_KEYPWR
+#define MT6315_PMIC_RG_KEYPWR_VBUCK1_EN_MASK                0x1
+#define MT6315_PMIC_RG_KEYPWR_VBUCK1_EN_SHIFT               7
+#define MT6315_PMIC_RG_PSEQ_FORCE_ON_ADDR                   \
+	MT6315_PPCTST0
+#define MT6315_PMIC_RG_PSEQ_FORCE_ON_MASK                   0x1
+#define MT6315_PMIC_RG_PSEQ_FORCE_ON_SHIFT                  0
+#define MT6315_PMIC_RG_PSEQ_FORCE_TEST_EN_ADDR              \
+	MT6315_PPCTST0
+#define MT6315_PMIC_RG_PSEQ_FORCE_TEST_EN_MASK              0x1
+#define MT6315_PMIC_RG_PSEQ_FORCE_TEST_EN_SHIFT             1
+#define MT6315_PMIC_RG_PSEQ_FORCE_ALL_DOFF_ADDR             \
+	MT6315_PPCTST0
+#define MT6315_PMIC_RG_PSEQ_FORCE_ALL_DOFF_MASK             0x1
+#define MT6315_PMIC_RG_PSEQ_FORCE_ALL_DOFF_SHIFT            2
+#define MT6315_PMIC_RG_PSEQ_PG_CK_SEL_ADDR                  \
+	MT6315_PPCCTL2
+#define MT6315_PMIC_RG_PSEQ_PG_CK_SEL_MASK                  0x1
+#define MT6315_PMIC_RG_PSEQ_PG_CK_SEL_SHIFT                 0
+#define MT6315_PMIC_RG_THM_SHDN_EN_ADDR                     \
+	MT6315_PPCCTL2
+#define MT6315_PMIC_RG_THM_SHDN_EN_MASK                     0x1
+#define MT6315_PMIC_RG_THM_SHDN_EN_SHIFT                    6
+#define MT6315_PMIC_RG_OVLO_RDB_TD_ADDR                     \
+	MT6315_STRUP_CON4
+#define MT6315_PMIC_RG_OVLO_RDB_TD_MASK                     0x1
+#define MT6315_PMIC_RG_OVLO_RDB_TD_SHIFT                    2
+#define MT6315_PMIC_RG_OVLO_RDB_EN_ADDR                     \
+	MT6315_STRUP_CON4
+#define MT6315_PMIC_RG_OVLO_RDB_EN_MASK                     0x1
+#define MT6315_PMIC_RG_OVLO_RDB_EN_SHIFT                    3
+#define MT6315_PMIC_DDUVLO_DEB_EN_ADDR                      \
+	MT6315_STRUP_CON5
+#define MT6315_PMIC_DDUVLO_DEB_EN_MASK                      0x1
+#define MT6315_PMIC_DDUVLO_DEB_EN_SHIFT                     4
+#define MT6315_PMIC_RG_STRUP_FT_CTRL_ADDR                   \
+	MT6315_STRUP_CON5
+#define MT6315_PMIC_RG_STRUP_FT_CTRL_MASK                   0x3
+#define MT6315_PMIC_RG_STRUP_FT_CTRL_SHIFT                  5
+#define MT6315_PMIC_STRUP_DIG_IO_PG_FORCE_ADDR              \
+	MT6315_STRUP_CON5
+#define MT6315_PMIC_STRUP_DIG_IO_PG_FORCE_MASK              0x1
+#define MT6315_PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT             7
+#define MT6315_PMIC_RG_ATST_PG_CHK_ADDR                     \
+	MT6315_STRUP_CON6
+#define MT6315_PMIC_RG_ATST_PG_CHK_MASK                     0x1
+#define MT6315_PMIC_RG_ATST_PG_CHK_SHIFT                    0
+#define MT6315_PMIC_RG_STRUP_PG_DEB_MODE_ADDR               \
+	MT6315_STRUP_CON6
+#define MT6315_PMIC_RG_STRUP_PG_DEB_MODE_MASK               0x1
+#define MT6315_PMIC_RG_STRUP_PG_DEB_MODE_SHIFT              1
+#define MT6315_PMIC_RG_CPS_W_KEY_ADDR                       \
+	MT6315_CPSWKEY
+#define MT6315_PMIC_RG_CPS_W_KEY_MASK                       0xFF
+#define MT6315_PMIC_RG_CPS_W_KEY_SHIFT                      0
+#define MT6315_PMIC_RG_CPS_W_KEY_H_ADDR                     \
+	MT6315_CPSWKEY_H
+#define MT6315_PMIC_RG_CPS_W_KEY_H_MASK                     0xFF
+#define MT6315_PMIC_RG_CPS_W_KEY_H_SHIFT                    0
+#define MT6315_PMIC_STS_PDN_ENCODE_ADDR                     \
+	MT6315_STS_PDN_ENCODE
+#define MT6315_PMIC_STS_PDN_ENCODE_MASK                     0x1F
+#define MT6315_PMIC_STS_PDN_ENCODE_SHIFT                    0
+#define MT6315_PMIC_PSEQ_ELR_LEN_ADDR                       \
+	MT6315_PSEQ_ELR_NUM
+#define MT6315_PMIC_PSEQ_ELR_LEN_MASK                       0xFF
+#define MT6315_PMIC_PSEQ_ELR_LEN_SHIFT                      0
+#define MT6315_PMIC_RG_SLOT_INTV_UP_ADDR                    \
+	MT6315_PSEQ_ELR0
+#define MT6315_PMIC_RG_SLOT_INTV_UP_MASK                    0x3
+#define MT6315_PMIC_RG_SLOT_INTV_UP_SHIFT                   0
+#define MT6315_PMIC_RG_SEQ_LEN_ADDR                         \
+	MT6315_PSEQ_ELR0
+#define MT6315_PMIC_RG_SEQ_LEN_MASK                         0x1F
+#define MT6315_PMIC_RG_SEQ_LEN_SHIFT                        2
+#define MT6315_PMIC_RG_PSEQ_ELR_RSV0_ADDR                   \
+	MT6315_PSEQ_ELR0
+#define MT6315_PMIC_RG_PSEQ_ELR_RSV0_MASK                   0x1
+#define MT6315_PMIC_RG_PSEQ_ELR_RSV0_SHIFT                  7
+#define MT6315_PMIC_RG_SLOT_INTV_DOWN_ADDR                  \
+	MT6315_PSEQ_ELR1
+#define MT6315_PMIC_RG_SLOT_INTV_DOWN_MASK                  0x3
+#define MT6315_PMIC_RG_SLOT_INTV_DOWN_SHIFT                 0
+#define MT6315_PMIC_RG_DSEQ_LEN_ADDR                        \
+	MT6315_PSEQ_ELR1
+#define MT6315_PMIC_RG_DSEQ_LEN_MASK                        0x1F
+#define MT6315_PMIC_RG_DSEQ_LEN_SHIFT                       2
+#define MT6315_PMIC_RG_PSEQ_ELR_RSV1_ADDR                   \
+	MT6315_PSEQ_ELR1
+#define MT6315_PMIC_RG_PSEQ_ELR_RSV1_MASK                   0x1
+#define MT6315_PMIC_RG_PSEQ_ELR_RSV1_SHIFT                  7
+#define MT6315_PMIC_RG_PSPG_SHDN_ENB_ADDR                   \
+	MT6315_PSEQ_ELR2
+#define MT6315_PMIC_RG_PSPG_SHDN_ENB_MASK                   0x3
+#define MT6315_PMIC_RG_PSPG_SHDN_ENB_SHIFT                  0
+#define MT6315_PMIC_RG_PSEQ_F32K_FORCE_ADDR                 \
+	MT6315_PSEQ_ELR2
+#define MT6315_PMIC_RG_PSEQ_F32K_FORCE_MASK                 0x1
+#define MT6315_PMIC_RG_PSEQ_F32K_FORCE_SHIFT                2
+#define MT6315_PMIC_RG_PSEQ_1MS_TK_EXT_ADDR                 \
+	MT6315_PSEQ_ELR2
+#define MT6315_PMIC_RG_PSEQ_1MS_TK_EXT_MASK                 0x1
+#define MT6315_PMIC_RG_PSEQ_1MS_TK_EXT_SHIFT                3
+#define MT6315_PMIC_RG_CPS_PGEXT_EN_ADDR                    \
+	MT6315_PSEQ_ELR2
+#define MT6315_PMIC_RG_CPS_PGEXT_EN_MASK                    0x1
+#define MT6315_PMIC_RG_CPS_PGEXT_EN_SHIFT                   4
+#define MT6315_PMIC_RG_SDN_DLY_ENB_ADDR                     \
+	MT6315_PSEQ_ELR2
+#define MT6315_PMIC_RG_SDN_DLY_ENB_MASK                     0x1
+#define MT6315_PMIC_RG_SDN_DLY_ENB_SHIFT                    5
+#define MT6315_PMIC_RG_STRUP_VBUCK4_PG_H2L_EN_ADDR          \
+	MT6315_PSEQ_ELR3
+#define MT6315_PMIC_RG_STRUP_VBUCK4_PG_H2L_EN_MASK          0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK4_PG_H2L_EN_SHIFT         4
+#define MT6315_PMIC_RG_STRUP_VBUCK3_PG_H2L_EN_ADDR          \
+	MT6315_PSEQ_ELR3
+#define MT6315_PMIC_RG_STRUP_VBUCK3_PG_H2L_EN_MASK          0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK3_PG_H2L_EN_SHIFT         5
+#define MT6315_PMIC_RG_STRUP_VBUCK2_PG_H2L_EN_ADDR          \
+	MT6315_PSEQ_ELR3
+#define MT6315_PMIC_RG_STRUP_VBUCK2_PG_H2L_EN_MASK          0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK2_PG_H2L_EN_SHIFT         6
+#define MT6315_PMIC_RG_STRUP_VBUCK1_PG_H2L_EN_ADDR          \
+	MT6315_PSEQ_ELR3
+#define MT6315_PMIC_RG_STRUP_VBUCK1_PG_H2L_EN_MASK          0x1
+#define MT6315_PMIC_RG_STRUP_VBUCK1_PG_H2L_EN_SHIFT         7
+#define MT6315_PMIC_RG_PSC_ELR_RSV0_ADDR                    \
+	MT6315_PSEQ_ELR4
+#define MT6315_PMIC_RG_PSC_ELR_RSV0_MASK                    0xFF
+#define MT6315_PMIC_RG_PSC_ELR_RSV0_SHIFT                   0
+#define MT6315_PMIC_RG_PSC_ELR_RSV1_ADDR                    \
+	MT6315_PSEQ_ELR5
+#define MT6315_PMIC_RG_PSC_ELR_RSV1_MASK                    0xFF
+#define MT6315_PMIC_RG_PSC_ELR_RSV1_SHIFT                   0
+#define MT6315_PMIC_RG_VBUCK1_USA_ADDR                      \
+	MT6315_CPSUSA_ELR0
+#define MT6315_PMIC_RG_VBUCK1_USA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK1_USA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK2_USA_ADDR                      \
+	MT6315_CPSUSA_ELR1
+#define MT6315_PMIC_RG_VBUCK2_USA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK2_USA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK3_USA_ADDR                      \
+	MT6315_CPSUSA_ELR2
+#define MT6315_PMIC_RG_VBUCK3_USA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK3_USA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK4_USA_ADDR                      \
+	MT6315_CPSUSA_ELR3
+#define MT6315_PMIC_RG_VBUCK4_USA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK4_USA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK1_DSA_ADDR                      \
+	MT6315_CPSDSA_ELR0
+#define MT6315_PMIC_RG_VBUCK1_DSA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK1_DSA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK2_DSA_ADDR                      \
+	MT6315_CPSDSA_ELR1
+#define MT6315_PMIC_RG_VBUCK2_DSA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK2_DSA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK3_DSA_ADDR                      \
+	MT6315_CPSDSA_ELR2
+#define MT6315_PMIC_RG_VBUCK3_DSA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK3_DSA_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK4_DSA_ADDR                      \
+	MT6315_CPSDSA_ELR3
+#define MT6315_PMIC_RG_VBUCK4_DSA_MASK                      0x1F
+#define MT6315_PMIC_RG_VBUCK4_DSA_SHIFT                     0
+#define MT6315_PMIC_STRUP_ANA0_ANA_ID_ADDR                  \
+	MT6315_STRUP_ANA0_ANA_ID
+#define MT6315_PMIC_STRUP_ANA0_ANA_ID_MASK                  0xFF
+#define MT6315_PMIC_STRUP_ANA0_ANA_ID_SHIFT                 0
+#define MT6315_PMIC_STRUP_ANA0_DIG_ID_ADDR                  \
+	MT6315_STRUP_ANA0_DIG_ID
+#define MT6315_PMIC_STRUP_ANA0_DIG_ID_MASK                  0xFF
+#define MT6315_PMIC_STRUP_ANA0_DIG_ID_SHIFT                 0
+#define MT6315_PMIC_STRUP_ANA0_ANA_MINOR_REV_ADDR           \
+	MT6315_STRUP_ANA0_DSN_REV0
+#define MT6315_PMIC_STRUP_ANA0_ANA_MINOR_REV_MASK           0xF
+#define MT6315_PMIC_STRUP_ANA0_ANA_MINOR_REV_SHIFT          0
+#define MT6315_PMIC_STRUP_ANA0_ANA_MAJOR_REV_ADDR           \
+	MT6315_STRUP_ANA0_DSN_REV0
+#define MT6315_PMIC_STRUP_ANA0_ANA_MAJOR_REV_MASK           0xF
+#define MT6315_PMIC_STRUP_ANA0_ANA_MAJOR_REV_SHIFT          4
+#define MT6315_PMIC_STRUP_ANA0_DIG_MINOR_REV_ADDR           \
+	MT6315_STRUP_ANA0_DSN_REV1
+#define MT6315_PMIC_STRUP_ANA0_DIG_MINOR_REV_MASK           0xF
+#define MT6315_PMIC_STRUP_ANA0_DIG_MINOR_REV_SHIFT          0
+#define MT6315_PMIC_STRUP_ANA0_DIG_MAJOR_REV_ADDR           \
+	MT6315_STRUP_ANA0_DSN_REV1
+#define MT6315_PMIC_STRUP_ANA0_DIG_MAJOR_REV_MASK           0xF
+#define MT6315_PMIC_STRUP_ANA0_DIG_MAJOR_REV_SHIFT          4
+#define MT6315_PMIC_STRUP_ANA0_CBS_ADDR                     \
+	MT6315_STRUP_ANA0_DBI0
+#define MT6315_PMIC_STRUP_ANA0_CBS_MASK                     0x3
+#define MT6315_PMIC_STRUP_ANA0_CBS_SHIFT                    0
+#define MT6315_PMIC_STRUP_ANA0_BIX_ADDR                     \
+	MT6315_STRUP_ANA0_DBI0
+#define MT6315_PMIC_STRUP_ANA0_BIX_MASK                     0x3
+#define MT6315_PMIC_STRUP_ANA0_BIX_SHIFT                    2
+#define MT6315_PMIC_STRUP_ANA0_ESP_ADDR                     \
+	MT6315_STRUP_ANA0_DBI1
+#define MT6315_PMIC_STRUP_ANA0_ESP_MASK                     0xFF
+#define MT6315_PMIC_STRUP_ANA0_ESP_SHIFT                    0
+#define MT6315_PMIC_STRUP_ANA0_FPI_ADDR                     \
+	MT6315_STRUP_ANA0_DXI
+#define MT6315_PMIC_STRUP_ANA0_FPI_MASK                     0xFF
+#define MT6315_PMIC_STRUP_ANA0_FPI_SHIFT                    0
+#define MT6315_PMIC_RG_VBG1_EN_ADDR                         \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBG1_EN_MASK                         0x1
+#define MT6315_PMIC_RG_VBG1_EN_SHIFT                        0
+#define MT6315_PMIC_RG_VBG2_EN_ADDR                         \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBG2_EN_MASK                         0x1
+#define MT6315_PMIC_RG_VBG2_EN_SHIFT                        1
+#define MT6315_PMIC_RG_VBGX_SEL_ADDR                        \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBGX_SEL_MASK                        0x1
+#define MT6315_PMIC_RG_VBGX_SEL_SHIFT                       2
+#define MT6315_PMIC_RG_VBG1_BYPASS_PREREG_ADDR              \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBG1_BYPASS_PREREG_MASK              0x1
+#define MT6315_PMIC_RG_VBG1_BYPASS_PREREG_SHIFT             3
+#define MT6315_PMIC_RG_VBG1_PREREG_VDB_EN_ADDR              \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBG1_PREREG_VDB_EN_MASK              0x1
+#define MT6315_PMIC_RG_VBG1_PREREG_VDB_EN_SHIFT             4
+#define MT6315_PMIC_RG_VBG2_LP_EN_ADDR                      \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBG2_LP_EN_MASK                      0x1
+#define MT6315_PMIC_RG_VBG2_LP_EN_SHIFT                     5
+#define MT6315_PMIC_RG_VBG_SCLPF_BYPASS_ADDR                \
+	MT6315_STRUP_TOP_A10876A_ANA_CON0
+#define MT6315_PMIC_RG_VBG_SCLPF_BYPASS_MASK                0x1
+#define MT6315_PMIC_RG_VBG_SCLPF_BYPASS_SHIFT               6
+#define MT6315_PMIC_RG_THERMAL_EN_ADDR                      \
+	MT6315_STRUP_TOP_A10876A_ANA_CON1
+#define MT6315_PMIC_RG_THERMAL_EN_MASK                      0x1
+#define MT6315_PMIC_RG_THERMAL_EN_SHIFT                     0
+#define MT6315_PMIC_RG_THERMAL_DET_SEL_ADDR                 \
+	MT6315_STRUP_TOP_A10876A_ANA_CON1
+#define MT6315_PMIC_RG_THERMAL_DET_SEL_MASK                 0x1
+#define MT6315_PMIC_RG_THERMAL_DET_SEL_SHIFT                1
+#define MT6315_PMIC_RG_THERMAL_TEMP_H_SEL_ADDR              \
+	MT6315_STRUP_TOP_A10876A_ANA_CON1
+#define MT6315_PMIC_RG_THERMAL_TEMP_H_SEL_MASK              0x3
+#define MT6315_PMIC_RG_THERMAL_TEMP_H_SEL_SHIFT             2
+#define MT6315_PMIC_RG_STRUP_OSC_EN_ADDR                    \
+	MT6315_STRUP_TOP_A10876A_ANA_CON2
+#define MT6315_PMIC_RG_STRUP_OSC_EN_MASK                    0x1
+#define MT6315_PMIC_RG_STRUP_OSC_EN_SHIFT                   0
+#define MT6315_PMIC_RG_SMPS_OSC_SEL_ADDR                    \
+	MT6315_STRUP_TOP_A10876A_ANA_CON2
+#define MT6315_PMIC_RG_SMPS_OSC_SEL_MASK                    0x1
+#define MT6315_PMIC_RG_SMPS_OSC_SEL_SHIFT                   1
+#define MT6315_PMIC_RG_UVLO_EN_ADDR                         \
+	MT6315_STRUP_TOP_A10876A_ANA_CON2
+#define MT6315_PMIC_RG_UVLO_EN_MASK                         0x1
+#define MT6315_PMIC_RG_UVLO_EN_SHIFT                        2
+#define MT6315_PMIC_RG_UVLO_FORCE_COMPH_ADDR                \
+	MT6315_STRUP_TOP_A10876A_ANA_CON2
+#define MT6315_PMIC_RG_UVLO_FORCE_COMPH_MASK                0x1
+#define MT6315_PMIC_RG_UVLO_FORCE_COMPH_SHIFT               3
+#define MT6315_PMIC_RG_OVLO_FORCE_COMPH_ADDR                \
+	MT6315_STRUP_TOP_A10876A_ANA_CON2
+#define MT6315_PMIC_RG_OVLO_FORCE_COMPH_MASK                0x1
+#define MT6315_PMIC_RG_OVLO_FORCE_COMPH_SHIFT               4
+#define MT6315_PMIC_RG_VBAT_FORCE_COMPH_ADDR                \
+	MT6315_STRUP_TOP_A10876A_ANA_CON2
+#define MT6315_PMIC_RG_VBAT_FORCE_COMPH_MASK                0x1
+#define MT6315_PMIC_RG_VBAT_FORCE_COMPH_SHIFT               5
+#define MT6315_PMIC_RG_ANA_TM_EN_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ANA_CON3
+#define MT6315_PMIC_RG_ANA_TM_EN_MASK                       0x1
+#define MT6315_PMIC_RG_ANA_TM_EN_SHIFT                      0
+#define MT6315_PMIC_RG_ANA_TM_SEL_ADDR                      \
+	MT6315_STRUP_TOP_A10876A_ANA_CON3
+#define MT6315_PMIC_RG_ANA_TM_SEL_MASK                      0x1
+#define MT6315_PMIC_RG_ANA_TM_SEL_SHIFT                     1
+#define MT6315_PMIC_RG_ANA_TM_MUX_SEL_ADDR                  \
+	MT6315_STRUP_TOP_A10876A_ANA_CON3
+#define MT6315_PMIC_RG_ANA_TM_MUX_SEL_MASK                  0xF
+#define MT6315_PMIC_RG_ANA_TM_MUX_SEL_SHIFT                 2
+#define MT6315_PMIC_RG_STRUP_RSV_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ANA_CON4
+#define MT6315_PMIC_RG_STRUP_RSV_MASK                       0xFF
+#define MT6315_PMIC_RG_STRUP_RSV_SHIFT                      0
+#define MT6315_PMIC_RG_PG_DISABLE_ADDR                      \
+	MT6315_STRUP_TOP_A10876A_ANA_CON5
+#define MT6315_PMIC_RG_PG_DISABLE_MASK                      0x1
+#define MT6315_PMIC_RG_PG_DISABLE_SHIFT                     0
+#define MT6315_PMIC_RG_VDIG18_DISCHARGE_EN_OPTION_ADDR      \
+	MT6315_STRUP_TOP_A10876A_ANA_CON5
+#define MT6315_PMIC_RG_VDIG18_DISCHARGE_EN_OPTION_MASK      0x1
+#define MT6315_PMIC_RG_VDIG18_DISCHARGE_EN_OPTION_SHIFT     1
+#define MT6315_PMIC_RG_VDIG18_FASTTRAN_EN_OPTION_ADDR       \
+	MT6315_STRUP_TOP_A10876A_ANA_CON5
+#define MT6315_PMIC_RG_VDIG18_FASTTRAN_EN_OPTION_MASK       0x1
+#define MT6315_PMIC_RG_VDIG18_FASTTRAN_EN_OPTION_SHIFT      2
+#define MT6315_PMIC_RG_VDIG18_RSV_ADDR                      \
+	MT6315_STRUP_TOP_A10876A_ANA_CON5
+#define MT6315_PMIC_RG_VDIG18_RSV_MASK                      0xF
+#define MT6315_PMIC_RG_VDIG18_RSV_SHIFT                     3
+#define MT6315_PMIC_RG_AUTOK_RST_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ANA_CON6
+#define MT6315_PMIC_RG_AUTOK_RST_MASK                       0x1
+#define MT6315_PMIC_RG_AUTOK_RST_SHIFT                      0
+#define MT6315_PMIC_RG_DISAUTOK_ADDR                        \
+	MT6315_STRUP_TOP_A10876A_ANA_CON6
+#define MT6315_PMIC_RG_DISAUTOK_MASK                        0x1
+#define MT6315_PMIC_RG_DISAUTOK_SHIFT                       1
+#define MT6315_PMIC_RGS_VBUCK1_PG_STATUS_ADDR               \
+	MT6315_STRUP_TOP_A10876A_ANA_CON7
+#define MT6315_PMIC_RGS_VBUCK1_PG_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK1_PG_STATUS_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK2_PG_STATUS_ADDR               \
+	MT6315_STRUP_TOP_A10876A_ANA_CON7
+#define MT6315_PMIC_RGS_VBUCK2_PG_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK2_PG_STATUS_SHIFT              1
+#define MT6315_PMIC_RGS_VBUCK3_PG_STATUS_ADDR               \
+	MT6315_STRUP_TOP_A10876A_ANA_CON7
+#define MT6315_PMIC_RGS_VBUCK3_PG_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK3_PG_STATUS_SHIFT              2
+#define MT6315_PMIC_RGS_VBUCK4_PG_STATUS_ADDR               \
+	MT6315_STRUP_TOP_A10876A_ANA_CON7
+#define MT6315_PMIC_RGS_VBUCK4_PG_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK4_PG_STATUS_SHIFT              3
+#define MT6315_PMIC_RGS_VIO18_PG_STATUS_ADDR                \
+	MT6315_STRUP_TOP_A10876A_ANA_CON7
+#define MT6315_PMIC_RGS_VIO18_PG_STATUS_MASK                0x1
+#define MT6315_PMIC_RGS_VIO18_PG_STATUS_SHIFT               4
+#define MT6315_PMIC_RGS_POFFSTS_ADDR                        \
+	MT6315_STRUP_TOP_A10876A_ANA_CON8
+#define MT6315_PMIC_RGS_POFFSTS_MASK                        0x1F
+#define MT6315_PMIC_RGS_POFFSTS_SHIFT                       0
+#define MT6315_PMIC_STRUP_ANA0_ELR_LEN_ADDR                 \
+	MT6315_STRUP_ANA0_ELR_NUM
+#define MT6315_PMIC_STRUP_ANA0_ELR_LEN_MASK                 0xFF
+#define MT6315_PMIC_STRUP_ANA0_ELR_LEN_SHIFT                0
+#define MT6315_PMIC_RG_VBG1_TC_TRIM_ADDR                    \
+	MT6315_STRUP_TOP_A10876A_ELR_0
+#define MT6315_PMIC_RG_VBG1_TC_TRIM_MASK                    0x1F
+#define MT6315_PMIC_RG_VBG1_TC_TRIM_SHIFT                   0
+#define MT6315_PMIC_RG_VBG2_TC_TRIM_ADDR                    \
+	MT6315_STRUP_TOP_A10876A_ELR_1
+#define MT6315_PMIC_RG_VBG2_TC_TRIM_MASK                    0xF
+#define MT6315_PMIC_RG_VBG2_TC_TRIM_SHIFT                   0
+#define MT6315_PMIC_RG_VBGR_IREF_TRIM_ADDR                  \
+	MT6315_STRUP_TOP_A10876A_ELR_2
+#define MT6315_PMIC_RG_VBGR_IREF_TRIM_MASK                  0xFF
+#define MT6315_PMIC_RG_VBGR_IREF_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_VBGR_VREF_TRIM_ADDR                  \
+	MT6315_STRUP_TOP_A10876A_ELR_3
+#define MT6315_PMIC_RG_VBGR_VREF_TRIM_MASK                  0xFF
+#define MT6315_PMIC_RG_VBGR_VREF_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK1_TRIM_ADDR                     \
+	MT6315_STRUP_TOP_A10876A_ELR_4
+#define MT6315_PMIC_RG_VBUCK1_TRIM_MASK                     0xF
+#define MT6315_PMIC_RG_VBUCK1_TRIM_SHIFT                    0
+#define MT6315_PMIC_RG_UVLO_VTHH_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ELR_4
+#define MT6315_PMIC_RG_UVLO_VTHH_MASK                       0x7
+#define MT6315_PMIC_RG_UVLO_VTHH_SHIFT                      4
+#define MT6315_PMIC_RG_VBUCK2_TRIM_ADDR                     \
+	MT6315_STRUP_TOP_A10876A_ELR_5
+#define MT6315_PMIC_RG_VBUCK2_TRIM_MASK                     0xF
+#define MT6315_PMIC_RG_VBUCK2_TRIM_SHIFT                    0
+#define MT6315_PMIC_RG_UVLO_VTHL_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ELR_5
+#define MT6315_PMIC_RG_UVLO_VTHL_MASK                       0x7
+#define MT6315_PMIC_RG_UVLO_VTHL_SHIFT                      4
+#define MT6315_PMIC_RG_VBUCK3_TRIM_ADDR                     \
+	MT6315_STRUP_TOP_A10876A_ELR_6
+#define MT6315_PMIC_RG_VBUCK3_TRIM_MASK                     0xF
+#define MT6315_PMIC_RG_VBUCK3_TRIM_SHIFT                    0
+#define MT6315_PMIC_RG_OVLO_VTHL_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ELR_6
+#define MT6315_PMIC_RG_OVLO_VTHL_MASK                       0x7
+#define MT6315_PMIC_RG_OVLO_VTHL_SHIFT                      4
+#define MT6315_PMIC_RG_VBUCK4_TRIM_ADDR                     \
+	MT6315_STRUP_TOP_A10876A_ELR_7
+#define MT6315_PMIC_RG_VBUCK4_TRIM_MASK                     0xF
+#define MT6315_PMIC_RG_VBUCK4_TRIM_SHIFT                    0
+#define MT6315_PMIC_RG_OVLO_VTHH_ADDR                       \
+	MT6315_STRUP_TOP_A10876A_ELR_7
+#define MT6315_PMIC_RG_OVLO_VTHH_MASK                       0x7
+#define MT6315_PMIC_RG_OVLO_VTHH_SHIFT                      4
+#define MT6315_PMIC_RG_VDIG18_TRIM_ADDR                     \
+	MT6315_STRUP_TOP_A10876A_ELR_8
+#define MT6315_PMIC_RG_VDIG18_TRIM_MASK                     0xF
+#define MT6315_PMIC_RG_VDIG18_TRIM_SHIFT                    0
+#define MT6315_PMIC_RG_OVLO_EN_ADDR                         \
+	MT6315_STRUP_TOP_A10876A_ELR_8
+#define MT6315_PMIC_RG_OVLO_EN_MASK                         0x1
+#define MT6315_PMIC_RG_OVLO_EN_SHIFT                        4
+#define MT6315_PMIC_RG_THERMAL_LOCATION_ADDR                \
+	MT6315_STRUP_TOP_A10876A_ELR_9
+#define MT6315_PMIC_RG_THERMAL_LOCATION_MASK                0x1F
+#define MT6315_PMIC_RG_THERMAL_LOCATION_SHIFT               0
+#define MT6315_PMIC_BUCK_TOP_ANA_ID_ADDR                    \
+	MT6315_BUCK_TOP_ANA_ID
+#define MT6315_PMIC_BUCK_TOP_ANA_ID_MASK                    0xFF
+#define MT6315_PMIC_BUCK_TOP_ANA_ID_SHIFT                   0
+#define MT6315_PMIC_BUCK_TOP_DIG_ID_ADDR                    \
+	MT6315_BUCK_TOP_DIG_ID
+#define MT6315_PMIC_BUCK_TOP_DIG_ID_MASK                    0xFF
+#define MT6315_PMIC_BUCK_TOP_DIG_ID_SHIFT                   0
+#define MT6315_PMIC_BUCK_TOP_ANA_MINOR_REV_ADDR             \
+	MT6315_BUCK_TOP_REV0
+#define MT6315_PMIC_BUCK_TOP_ANA_MINOR_REV_MASK             0xF
+#define MT6315_PMIC_BUCK_TOP_ANA_MINOR_REV_SHIFT            0
+#define MT6315_PMIC_BUCK_TOP_ANA_MAJOR_REV_ADDR             \
+	MT6315_BUCK_TOP_REV0
+#define MT6315_PMIC_BUCK_TOP_ANA_MAJOR_REV_MASK             0xF
+#define MT6315_PMIC_BUCK_TOP_ANA_MAJOR_REV_SHIFT            4
+#define MT6315_PMIC_BUCK_TOP_DIG_MINOR_REV_ADDR             \
+	MT6315_BUCK_TOP_REV1
+#define MT6315_PMIC_BUCK_TOP_DIG_MINOR_REV_MASK             0xF
+#define MT6315_PMIC_BUCK_TOP_DIG_MINOR_REV_SHIFT            0
+#define MT6315_PMIC_BUCK_TOP_DIG_MAJOR_REV_ADDR             \
+	MT6315_BUCK_TOP_REV1
+#define MT6315_PMIC_BUCK_TOP_DIG_MAJOR_REV_MASK             0xF
+#define MT6315_PMIC_BUCK_TOP_DIG_MAJOR_REV_SHIFT            4
+#define MT6315_PMIC_BUCK_TOP_CBS_ADDR                       \
+	MT6315_BUCK_TOP_DBI0
+#define MT6315_PMIC_BUCK_TOP_CBS_MASK                       0x3
+#define MT6315_PMIC_BUCK_TOP_CBS_SHIFT                      0
+#define MT6315_PMIC_BUCK_TOP_BIX_ADDR                       \
+	MT6315_BUCK_TOP_DBI0
+#define MT6315_PMIC_BUCK_TOP_BIX_MASK                       0x3
+#define MT6315_PMIC_BUCK_TOP_BIX_SHIFT                      2
+#define MT6315_PMIC_BUCK_TOP_ESP_ADDR                       \
+	MT6315_BUCK_TOP_DBI1
+#define MT6315_PMIC_BUCK_TOP_ESP_MASK                       0xFF
+#define MT6315_PMIC_BUCK_TOP_ESP_SHIFT                      0
+#define MT6315_PMIC_BUCK_TOP_FPI_ADDR                       \
+	MT6315_BUCK_TOP_DXI
+#define MT6315_PMIC_BUCK_TOP_FPI_MASK                       0xFF
+#define MT6315_PMIC_BUCK_TOP_FPI_SHIFT                      0
+#define MT6315_PMIC_BUCK_TOP_CLK_OFFSET_ADDR                \
+	MT6315_BUCK_TOP_PAM0
+#define MT6315_PMIC_BUCK_TOP_CLK_OFFSET_MASK                0xFF
+#define MT6315_PMIC_BUCK_TOP_CLK_OFFSET_SHIFT               0
+#define MT6315_PMIC_BUCK_TOP_RST_OFFSET_ADDR                \
+	MT6315_BUCK_TOP_PAM1
+#define MT6315_PMIC_BUCK_TOP_RST_OFFSET_MASK                0xFF
+#define MT6315_PMIC_BUCK_TOP_RST_OFFSET_SHIFT               0
+#define MT6315_PMIC_BUCK_TOP_INT_OFFSET_ADDR                \
+	MT6315_BUCK_TOP_PAM2
+#define MT6315_PMIC_BUCK_TOP_INT_OFFSET_MASK                0xFF
+#define MT6315_PMIC_BUCK_TOP_INT_OFFSET_SHIFT               0
+#define MT6315_PMIC_BUCK_TOP_INT_LEN_ADDR                   \
+	MT6315_BUCK_TOP_PAM3
+#define MT6315_PMIC_BUCK_TOP_INT_LEN_MASK                   0xFF
+#define MT6315_PMIC_BUCK_TOP_INT_LEN_SHIFT                  0
+#define MT6315_PMIC_RG_BUCK32K_CK_PDN_ADDR                  \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK32K_CK_PDN_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK32K_CK_PDN_SHIFT                 0
+#define MT6315_PMIC_RG_BUCK1M_CK_PDN_ADDR                   \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK1M_CK_PDN_MASK                   0x1
+#define MT6315_PMIC_RG_BUCK1M_CK_PDN_SHIFT                  1
+#define MT6315_PMIC_RG_BUCK4M_CK_PDN_ADDR                   \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK4M_CK_PDN_MASK                   0x1
+#define MT6315_PMIC_RG_BUCK4M_CK_PDN_SHIFT                  2
+#define MT6315_PMIC_RG_BUCK_RG_CK_PDN_ADDR                  \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK_RG_CK_PDN_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_RG_CK_PDN_SHIFT                 3
+#define MT6315_PMIC_RG_BUCK_RG_CK_SEL_ADDR                  \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK_RG_CK_SEL_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_RG_CK_SEL_SHIFT                 4
+#define MT6315_PMIC_RG_BUCK_SFCHG_SYNC_CK_FORCE_ADDR        \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK_SFCHG_SYNC_CK_FORCE_MASK        0x1
+#define MT6315_PMIC_RG_BUCK_SFCHG_SYNC_CK_FORCE_SHIFT       5
+#define MT6315_PMIC_RG_BUCK_CK_RSV_ADDR                     \
+	MT6315_BUCK_TOP_CLK_CON0
+#define MT6315_PMIC_RG_BUCK_CK_RSV_MASK                     0x3
+#define MT6315_PMIC_RG_BUCK_CK_RSV_SHIFT                    6
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_CON0_SET_ADDR           \
+	MT6315_BUCK_TOP_CLK_CON0_SET
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_CON0_SET_MASK           0xFF
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_CON0_SET_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_CON0_CLR_ADDR           \
+	MT6315_BUCK_TOP_CLK_CON0_CLR
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_CON0_CLR_MASK           0xFF
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_CON0_CLR_SHIFT          0
+#define MT6315_PMIC_RG_BUCK32K_CK_PDN_HWEN_ADDR             \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0
+#define MT6315_PMIC_RG_BUCK32K_CK_PDN_HWEN_MASK             0x1
+#define MT6315_PMIC_RG_BUCK32K_CK_PDN_HWEN_SHIFT            0
+#define MT6315_PMIC_RG_BUCK1M_CK_PDN_HWEN_ADDR              \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0
+#define MT6315_PMIC_RG_BUCK1M_CK_PDN_HWEN_MASK              0x1
+#define MT6315_PMIC_RG_BUCK1M_CK_PDN_HWEN_SHIFT             1
+#define MT6315_PMIC_RG_BUCK4M_CK_PDN_HWEN_ADDR              \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0
+#define MT6315_PMIC_RG_BUCK4M_CK_PDN_HWEN_MASK              0x1
+#define MT6315_PMIC_RG_BUCK4M_CK_PDN_HWEN_SHIFT             2
+#define MT6315_PMIC_RG_BUCK_RG_CK_PDN_HWEN_ADDR             \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0
+#define MT6315_PMIC_RG_BUCK_RG_CK_PDN_HWEN_MASK             0x1
+#define MT6315_PMIC_RG_BUCK_RG_CK_PDN_HWEN_SHIFT            3
+#define MT6315_PMIC_RG_BUCK_SLEEP_CTRL_MODE_ADDR            \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0
+#define MT6315_PMIC_RG_BUCK_SLEEP_CTRL_MODE_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_SLEEP_CTRL_MODE_SHIFT           4
+#define MT6315_PMIC_RG_BUCK_CK_PDN_HWEN_RSV_ADDR            \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0
+#define MT6315_PMIC_RG_BUCK_CK_PDN_HWEN_RSV_MASK            0x7
+#define MT6315_PMIC_RG_BUCK_CK_PDN_HWEN_RSV_SHIFT           5
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_ADDR      \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0_SET
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_MASK      0xFF
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_SHIFT     0
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_ADDR      \
+	MT6315_BUCK_TOP_CLK_HWEN_CON0_CLR
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_MASK      0xFF
+#define MT6315_PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_SHIFT     0
+#define MT6315_PMIC_RG_BUCK_DLE_DCM_ADDR                    \
+	MT6315_BUCK_TOP_CLK_DCM_CON
+#define MT6315_PMIC_RG_BUCK_DLE_DCM_MASK                    0x1
+#define MT6315_PMIC_RG_BUCK_DLE_DCM_SHIFT                   0
+#define MT6315_PMIC_RG_BUCK_INIS_SET_ADDR                   \
+	MT6315_BUCK_TOP_SYNC_CON
+#define MT6315_PMIC_RG_BUCK_INIS_SET_MASK                   0x1
+#define MT6315_PMIC_RG_BUCK_INIS_SET_SHIFT                  0
+#define MT6315_PMIC_RG_BUCK_SYNC_RSV_ADDR                   \
+	MT6315_BUCK_TOP_SYNC_CON
+#define MT6315_PMIC_RG_BUCK_SYNC_RSV_MASK                   0x7
+#define MT6315_PMIC_RG_BUCK_SYNC_RSV_SHIFT                  1
+#define MT6315_PMIC_RG_BUCK_STB_MAX_ADDR                    \
+	MT6315_BUCK_TOP_STB_CON
+#define MT6315_PMIC_RG_BUCK_STB_MAX_MASK                    0xFF
+#define MT6315_PMIC_RG_BUCK_STB_MAX_SHIFT                   0
+#define MT6315_PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX_ADDR   \
+	MT6315_BUCK_TOP_VGP2_MINFREQ_CON0
+#define MT6315_PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX_MASK   0xFF
+#define MT6315_PMIC_RG_BUCK_VGP2_MINFREQ_LATENCY_MAX_SHIFT  0
+#define MT6315_PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX_ADDR  \
+	MT6315_BUCK_TOP_VGP2_MINFREQ_CON1
+#define MT6315_PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX_MASK  0x7
+#define MT6315_PMIC_RG_BUCK_VGP2_MINFREQ_DURATION_MAX_SHIFT 0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OC_SDN_STATUS_ADDR       \
+	MT6315_BUCK_TOP_OC_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OC_SDN_STATUS_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OC_SDN_STATUS_SHIFT      0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OC_SDN_STATUS_ADDR       \
+	MT6315_BUCK_TOP_OC_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OC_SDN_STATUS_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OC_SDN_STATUS_SHIFT      1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OC_SDN_STATUS_ADDR       \
+	MT6315_BUCK_TOP_OC_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OC_SDN_STATUS_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OC_SDN_STATUS_SHIFT      2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OC_SDN_STATUS_ADDR       \
+	MT6315_BUCK_TOP_OC_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OC_SDN_STATUS_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OC_SDN_STATUS_SHIFT      3
+#define MT6315_PMIC_BUCK_TOP_WRITE_KEY_ADDR                 \
+	MT6315_BUCK_TOP_KEY_PROT0
+#define MT6315_PMIC_BUCK_TOP_WRITE_KEY_MASK                 0xFF
+#define MT6315_PMIC_BUCK_TOP_WRITE_KEY_SHIFT                0
+#define MT6315_PMIC_BUCK_TOP_WRITE_KEY_H_ADDR               \
+	MT6315_BUCK_TOP_KEY_PROT1
+#define MT6315_PMIC_BUCK_TOP_WRITE_KEY_H_MASK               0xFF
+#define MT6315_PMIC_BUCK_TOP_WRITE_KEY_H_SHIFT              0
+#define MT6315_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR           \
+	MT6315_BUCK_TOP_WDTDBG0
+#define MT6315_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_MASK           0xFF
+#define MT6315_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_SHIFT          0
+#define MT6315_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_LSB_ADDR       \
+	MT6315_BUCK_TOP_WDTDBG1
+#define MT6315_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_LSB_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_LSB_SHIFT      0
+#define MT6315_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR           \
+	MT6315_BUCK_TOP_WDTDBG2
+#define MT6315_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_MASK           0xFF
+#define MT6315_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_SHIFT          0
+#define MT6315_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_LSB_ADDR       \
+	MT6315_BUCK_TOP_WDTDBG3
+#define MT6315_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_LSB_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_LSB_SHIFT      0
+#define MT6315_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR           \
+	MT6315_BUCK_TOP_WDTDBG4
+#define MT6315_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_MASK           0xFF
+#define MT6315_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_SHIFT          0
+#define MT6315_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_LSB_ADDR       \
+	MT6315_BUCK_TOP_WDTDBG5
+#define MT6315_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_LSB_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_LSB_SHIFT      0
+#define MT6315_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR           \
+	MT6315_BUCK_TOP_WDTDBG6
+#define MT6315_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_MASK           0xFF
+#define MT6315_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_SHIFT          0
+#define MT6315_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_LSB_ADDR       \
+	MT6315_BUCK_TOP_WDTDBG7
+#define MT6315_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_LSB_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_LSB_SHIFT      0
+#define MT6315_PMIC_RGS_BUCK_TOP_DBG_ADDR                   \
+	MT6315_BUCK_TOP_DBG
+#define MT6315_PMIC_RGS_BUCK_TOP_DBG_MASK                   0xFF
+#define MT6315_PMIC_RGS_BUCK_TOP_DBG_SHIFT                  0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_EN_ADDR                  \
+	MT6315_BUCK_TOP_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_EN_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_EN_SHIFT                 0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_EN_ADDR                  \
+	MT6315_BUCK_TOP_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_EN_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_EN_SHIFT                 1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_EN_ADDR                  \
+	MT6315_BUCK_TOP_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_EN_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_EN_SHIFT                 2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_EN_ADDR                  \
+	MT6315_BUCK_TOP_CON0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_EN_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_EN_SHIFT                 3
+#define MT6315_PMIC_RG_BUCK_VBUCK_EN_SET_ADDR               \
+	MT6315_BUCK_TOP_CON0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK_EN_SET_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK_EN_SET_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK_EN_CLR_ADDR               \
+	MT6315_BUCK_TOP_CON0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK_EN_CLR_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK_EN_CLR_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_LP_ADDR                  \
+	MT6315_BUCK_TOP_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_LP_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_LP_SHIFT                 0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_LP_ADDR                  \
+	MT6315_BUCK_TOP_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_LP_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_LP_SHIFT                 1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_LP_ADDR                  \
+	MT6315_BUCK_TOP_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_LP_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_LP_SHIFT                 2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_LP_ADDR                  \
+	MT6315_BUCK_TOP_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_LP_MASK                  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_LP_SHIFT                 3
+#define MT6315_PMIC_RG_BUCK_VBUCK_LP_SET_ADDR               \
+	MT6315_BUCK_TOP_CON1_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK_LP_SET_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK_LP_SET_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK_LP_CLR_ADDR               \
+	MT6315_BUCK_TOP_CON1_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK_LP_CLR_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK_LP_CLR_SHIFT              0
+#define MT6315_PMIC_BUCK_TOP_ELR_LEN_ADDR                   \
+	MT6315_BUCK_TOP_ELR_NUM
+#define MT6315_PMIC_BUCK_TOP_ELR_LEN_MASK                   0xFF
+#define MT6315_PMIC_BUCK_TOP_ELR_LEN_SHIFT                  0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_ADDR               \
+	MT6315_BUCK_TOP_ELR0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_LSB_ADDR           \
+	MT6315_BUCK_TOP_ELR1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_LSB_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_LSB_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_ADDR               \
+	MT6315_BUCK_TOP_ELR2
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_LSB_ADDR           \
+	MT6315_BUCK_TOP_ELR3
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_LSB_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_LSB_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_ADDR               \
+	MT6315_BUCK_TOP_ELR4
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LSB_ADDR           \
+	MT6315_BUCK_TOP_ELR5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LSB_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LSB_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_ADDR               \
+	MT6315_BUCK_TOP_ELR6
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_MASK               0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SHIFT              0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LSB_ADDR           \
+	MT6315_BUCK_TOP_ELR7
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LSB_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LSB_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OC_SDN_EN_ADDR           \
+	MT6315_BUCK_TOP_ELR8
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OC_SDN_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OC_SDN_EN_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OC_SDN_EN_ADDR           \
+	MT6315_BUCK_TOP_ELR8
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OC_SDN_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OC_SDN_EN_SHIFT          1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OC_SDN_EN_ADDR           \
+	MT6315_BUCK_TOP_ELR8
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OC_SDN_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OC_SDN_EN_SHIFT          2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OC_SDN_EN_ADDR           \
+	MT6315_BUCK_TOP_ELR8
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OC_SDN_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OC_SDN_EN_SHIFT          3
+#define MT6315_PMIC_RG_BUCK_DCM_MODE_ADDR                   \
+	MT6315_BUCK_TOP_ELR8
+#define MT6315_PMIC_RG_BUCK_DCM_MODE_MASK                   0x1
+#define MT6315_PMIC_RG_BUCK_DCM_MODE_SHIFT                  4
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_LIMIT_SEL_ADDR     \
+	MT6315_BUCK_TOP_ELR9
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_LIMIT_SEL_MASK     0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_LIMIT_SEL_SHIFT    0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_LIMIT_SEL_ADDR     \
+	MT6315_BUCK_TOP_ELR9
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_LIMIT_SEL_MASK     0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_LIMIT_SEL_SHIFT    2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LIMIT_SEL_ADDR     \
+	MT6315_BUCK_TOP_ELR9
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LIMIT_SEL_MASK     0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LIMIT_SEL_SHIFT    4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LIMIT_SEL_ADDR     \
+	MT6315_BUCK_TOP_ELR9
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LIMIT_SEL_MASK     0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LIMIT_SEL_SHIFT    6
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_VLIMIT_ADDR        \
+	MT6315_BUCK_TOP_ELR10
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_VLIMIT_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_VLIMIT_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_VLIMIT_ADDR        \
+	MT6315_BUCK_TOP_ELR11
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_VLIMIT_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_VLIMIT_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_VLIMIT_ADDR        \
+	MT6315_BUCK_TOP_ELR12
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_VLIMIT_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_VLIMIT_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_VLIMIT_ADDR        \
+	MT6315_BUCK_TOP_ELR13
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_VLIMIT_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_VLIMIT_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_ONSC_TD_ADDR             \
+	MT6315_BUCK_TOP_ELR14
+#define MT6315_PMIC_RG_BUCK_VBUCK1_ONSC_TD_MASK             0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK1_ONSC_TD_SHIFT            0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_ONSC_TD_ADDR             \
+	MT6315_BUCK_TOP_ELR14
+#define MT6315_PMIC_RG_BUCK_VBUCK2_ONSC_TD_MASK             0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK2_ONSC_TD_SHIFT            2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_ONSC_TD_ADDR             \
+	MT6315_BUCK_TOP_ELR14
+#define MT6315_PMIC_RG_BUCK_VBUCK3_ONSC_TD_MASK             0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK3_ONSC_TD_SHIFT            4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_ONSC_TD_ADDR             \
+	MT6315_BUCK_TOP_ELR14
+#define MT6315_PMIC_RG_BUCK_VBUCK4_ONSC_TD_MASK             0x3
+#define MT6315_PMIC_RG_BUCK_VBUCK4_ONSC_TD_SHIFT            6
+#define MT6315_PMIC_RG_BUCK_EFUSE_RSV_ADDR                  \
+	MT6315_BUCK_TOP_ELR15
+#define MT6315_PMIC_RG_BUCK_EFUSE_RSV_MASK                  0xFF
+#define MT6315_PMIC_RG_BUCK_EFUSE_RSV_SHIFT                 0
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_ID_ADDR                 \
+	MT6315_BUCK_VBUCK1_ANA_ID
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_ID_ADDR                 \
+	MT6315_BUCK_VBUCK1_DIG_ID
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK1_REV0
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK1_REV0
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK1_ANA_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK1_REV1
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK1_REV1
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK1_DIG_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_CBS_ADDR                \
+	MT6315_BUCK_VBUCK1_DBI0
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_CBS_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_CBS_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_BIX_ADDR                \
+	MT6315_BUCK_VBUCK1_DBI0
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_BIX_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_BIX_SHIFT               2
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_ESP_ADDR                \
+	MT6315_BUCK_VBUCK1_DBI1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_ESP_MASK                0xFF
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_ESP_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_SSHUB_ADDR          \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_SSHUB_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_SSHUB_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_TRACKING_ADDR       \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_TRACKING_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_TRACKING_SHIFT      1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_PREOC_ADDR          \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_PREOC_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_PREOC_SHIFT         2
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_VOTER_ADDR          \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_VOTER_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_VOTER_SHIFT         3
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_ULTRASONIC_ADDR     \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_ULTRASONIC_MASK     0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_ULTRASONIC_SHIFT    4
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_DLC_ADDR            \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_DLC_MASK            0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_DLC_SHIFT           5
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_TRAP_ADDR           \
+	MT6315_BUCK_VBUCK1_DXI
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_TRAP_MASK           0x1
+#define MT6315_PMIC_BUCK_VBUCK1_DSN_FPI_TRAP_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR         \
+	MT6315_BUCK_VBUCK1_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SLEEP_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SLEEP_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SLEEP_LSB_ADDR     \
+	MT6315_BUCK_VBUCK1_CON2
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SLEEP_LSB_MASK     0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_VOSEL_SLEEP_LSB_SHIFT    0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SELR2R_CTRL_ADDR         \
+	MT6315_BUCK_VBUCK1_SLP_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SELR2R_CTRL_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SELR2R_CTRL_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_EN_MASK_ADDR         \
+	MT6315_BUCK_VBUCK1_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_EN_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_EN_MASK_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_UP_MASK_ADDR         \
+	MT6315_BUCK_VBUCK1_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_UP_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_UP_MASK_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_DOWN_MASK_ADDR       \
+	MT6315_BUCK_VBUCK1_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_DOWN_MASK_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_DVS_DOWN_MASK_SHIFT      2
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_RRATE_ADDR         \
+	MT6315_BUCK_VBUCK1_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_RRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_RRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_REN_ADDR           \
+	MT6315_BUCK_VBUCK1_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_REN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_REN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_FRATE_ADDR         \
+	MT6315_BUCK_VBUCK1_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_FRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_FRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_FEN_ADDR           \
+	MT6315_BUCK_VBUCK1_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_FEN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SFCHG_FEN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_EN_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_EN_SHIFT          1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_EN_SHIFT          2
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_EN_SHIFT          3
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_EN_SHIFT          4
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_EN_SHIFT          5
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_EN_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK1_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_EN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_0_SET_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_EN_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_0_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_0_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_0_CLR_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_EN_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_0_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_0_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SW_OP_EN_ADDR            \
+	MT6315_BUCK_VBUCK1_OP_EN_1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SW_OP_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_SW_OP_EN_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_1_SET_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_EN_1_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_1_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_1_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_1_CLR_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_EN_1_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_1_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_EN_1_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_CFG_SHIFT         0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_CFG_SHIFT         1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_CFG_SHIFT         2
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_CFG_SHIFT         3
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_CFG_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_CFG_SHIFT         5
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_CFG_SHIFT         6
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK1_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_CFG_SHIFT         7
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_CFG_0_SET_ADDR        \
+	MT6315_BUCK_VBUCK1_OP_CFG_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_CFG_0_SET_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_CFG_0_SET_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_CFG_0_CLR_ADDR        \
+	MT6315_BUCK_VBUCK1_OP_CFG_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_CFG_0_CLR_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_CFG_0_CLR_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW0_OP_MODE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW1_OP_MODE_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW2_OP_MODE_SHIFT        2
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW3_OP_MODE_SHIFT        3
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW4_OP_MODE_SHIFT        4
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW5_OP_MODE_SHIFT        5
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW6_OP_MODE_SHIFT        6
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK1_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_HW7_OP_MODE_SHIFT        7
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_MODE_0_SET_ADDR       \
+	MT6315_BUCK_VBUCK1_OP_MODE_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_MODE_0_SET_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_MODE_0_SET_SHIFT      0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_MODE_0_CLR_ADDR       \
+	MT6315_BUCK_VBUCK1_OP_MODE_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_MODE_0_CLR_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK1_OP_MODE_0_CLR_SHIFT      0
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_ADDR                    \
+	MT6315_BUCK_VBUCK1_DBG0
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_MASK                    0xFF
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_SHIFT                   0
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_LSB_ADDR                \
+	MT6315_BUCK_VBUCK1_DBG1
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_LSB_MASK                0x1
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_LSB_SHIFT               0
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_GRAY_ADDR               \
+	MT6315_BUCK_VBUCK1_DBG2
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_GRAY_MASK               0xFF
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_GRAY_SHIFT              0
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_GRAY_LSB_ADDR           \
+	MT6315_BUCK_VBUCK1_DBG3
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_GRAY_LSB_MASK           0x1
+#define MT6315_PMIC_DA_VBUCK1_VOSEL_GRAY_LSB_SHIFT          0
+#define MT6315_PMIC_DA_VBUCK1_EN_ADDR                       \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_EN_MASK                       0x1
+#define MT6315_PMIC_DA_VBUCK1_EN_SHIFT                      0
+#define MT6315_PMIC_DA_VBUCK1_STB_ADDR                      \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_STB_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK1_STB_SHIFT                     1
+#define MT6315_PMIC_DA_VBUCK1_LOOP_SEL_ADDR                 \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_LOOP_SEL_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK1_LOOP_SEL_SHIFT                2
+#define MT6315_PMIC_DA_VBUCK1_R2R_PDN_ADDR                  \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_R2R_PDN_MASK                  0x1
+#define MT6315_PMIC_DA_VBUCK1_R2R_PDN_SHIFT                 3
+#define MT6315_PMIC_DA_VBUCK1_DVS_EN_ADDR                   \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_DVS_EN_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK1_DVS_EN_SHIFT                  4
+#define MT6315_PMIC_DA_VBUCK1_DVS_UP_ADDR                   \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_DVS_UP_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK1_DVS_UP_SHIFT                  5
+#define MT6315_PMIC_DA_VBUCK1_DVS_DOWN_ADDR                 \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_DVS_DOWN_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK1_DVS_DOWN_SHIFT                6
+#define MT6315_PMIC_DA_VBUCK1_SSH_ADDR                      \
+	MT6315_BUCK_VBUCK1_DBG4
+#define MT6315_PMIC_DA_VBUCK1_SSH_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK1_SSH_SHIFT                     7
+#define MT6315_PMIC_DA_VBUCK1_MINFREQ_DISCHARGE_ADDR        \
+	MT6315_BUCK_VBUCK1_DBG5
+#define MT6315_PMIC_DA_VBUCK1_MINFREQ_DISCHARGE_MASK        0x1
+#define MT6315_PMIC_DA_VBUCK1_MINFREQ_DISCHARGE_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_CK_SW_MODE_ADDR          \
+	MT6315_BUCK_VBUCK1_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK1_CK_SW_MODE_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_CK_SW_MODE_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK1_CK_SW_EN_ADDR            \
+	MT6315_BUCK_VBUCK1_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK1_CK_SW_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_CK_SW_EN_SHIFT           5
+#define MT6315_PMIC_RG_BUCK_VBUCK1_TRACK_STALL_BYPASS_ADDR  \
+	MT6315_BUCK_VBUCK1_STALL_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK1_TRACK_STALL_BYPASS_MASK  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK1_TRACK_STALL_BYPASS_SHIFT 0
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_ID_ADDR                 \
+	MT6315_BUCK_VBUCK2_ANA_ID
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_ID_ADDR                 \
+	MT6315_BUCK_VBUCK2_DIG_ID
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK2_REV0
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK2_REV0
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK2_ANA_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK2_REV1
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK2_REV1
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK2_DIG_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_CBS_ADDR                \
+	MT6315_BUCK_VBUCK2_DBI0
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_CBS_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_CBS_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_BIX_ADDR                \
+	MT6315_BUCK_VBUCK2_DBI0
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_BIX_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_BIX_SHIFT               2
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_ESP_ADDR                \
+	MT6315_BUCK_VBUCK2_DBI1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_ESP_MASK                0xFF
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_ESP_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_SSHUB_ADDR          \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_SSHUB_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_SSHUB_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_TRACKING_ADDR       \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_TRACKING_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_TRACKING_SHIFT      1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_PREOC_ADDR          \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_PREOC_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_PREOC_SHIFT         2
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_VOTER_ADDR          \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_VOTER_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_VOTER_SHIFT         3
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_ULTRASONIC_ADDR     \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_ULTRASONIC_MASK     0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_ULTRASONIC_SHIFT    4
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_DLC_ADDR            \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_DLC_MASK            0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_DLC_SHIFT           5
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_TRAP_ADDR           \
+	MT6315_BUCK_VBUCK2_DXI
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_TRAP_MASK           0x1
+#define MT6315_PMIC_BUCK_VBUCK2_DSN_FPI_TRAP_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR         \
+	MT6315_BUCK_VBUCK2_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SLEEP_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SLEEP_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SLEEP_LSB_ADDR     \
+	MT6315_BUCK_VBUCK2_CON2
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SLEEP_LSB_MASK     0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_VOSEL_SLEEP_LSB_SHIFT    0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SELR2R_CTRL_ADDR         \
+	MT6315_BUCK_VBUCK2_SLP_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SELR2R_CTRL_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SELR2R_CTRL_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_EN_MASK_ADDR         \
+	MT6315_BUCK_VBUCK2_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_EN_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_EN_MASK_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_UP_MASK_ADDR         \
+	MT6315_BUCK_VBUCK2_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_UP_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_UP_MASK_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_DOWN_MASK_ADDR       \
+	MT6315_BUCK_VBUCK2_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_DOWN_MASK_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_DVS_DOWN_MASK_SHIFT      2
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_RRATE_ADDR         \
+	MT6315_BUCK_VBUCK2_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_RRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_RRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_REN_ADDR           \
+	MT6315_BUCK_VBUCK2_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_REN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_REN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_FRATE_ADDR         \
+	MT6315_BUCK_VBUCK2_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_FRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_FRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_FEN_ADDR           \
+	MT6315_BUCK_VBUCK2_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_FEN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SFCHG_FEN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_EN_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_EN_SHIFT          1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_EN_SHIFT          2
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_EN_SHIFT          3
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_EN_SHIFT          4
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_EN_SHIFT          5
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_EN_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK2_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_EN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_0_SET_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_EN_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_0_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_0_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_0_CLR_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_EN_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_0_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_0_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SW_OP_EN_ADDR            \
+	MT6315_BUCK_VBUCK2_OP_EN_1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SW_OP_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_SW_OP_EN_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_1_SET_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_EN_1_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_1_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_1_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_1_CLR_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_EN_1_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_1_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_EN_1_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_CFG_SHIFT         0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_CFG_SHIFT         1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_CFG_SHIFT         2
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_CFG_SHIFT         3
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_CFG_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_CFG_SHIFT         5
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_CFG_SHIFT         6
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK2_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_CFG_SHIFT         7
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_CFG_0_SET_ADDR        \
+	MT6315_BUCK_VBUCK2_OP_CFG_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_CFG_0_SET_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_CFG_0_SET_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_CFG_0_CLR_ADDR        \
+	MT6315_BUCK_VBUCK2_OP_CFG_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_CFG_0_CLR_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_CFG_0_CLR_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW0_OP_MODE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW1_OP_MODE_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW2_OP_MODE_SHIFT        2
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW3_OP_MODE_SHIFT        3
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW4_OP_MODE_SHIFT        4
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW5_OP_MODE_SHIFT        5
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW6_OP_MODE_SHIFT        6
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK2_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_HW7_OP_MODE_SHIFT        7
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_MODE_0_SET_ADDR       \
+	MT6315_BUCK_VBUCK2_OP_MODE_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_MODE_0_SET_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_MODE_0_SET_SHIFT      0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_MODE_0_CLR_ADDR       \
+	MT6315_BUCK_VBUCK2_OP_MODE_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_MODE_0_CLR_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK2_OP_MODE_0_CLR_SHIFT      0
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_ADDR                    \
+	MT6315_BUCK_VBUCK2_DBG0
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_MASK                    0xFF
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_SHIFT                   0
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_LSB_ADDR                \
+	MT6315_BUCK_VBUCK2_DBG1
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_LSB_MASK                0x1
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_LSB_SHIFT               0
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_GRAY_ADDR               \
+	MT6315_BUCK_VBUCK2_DBG2
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_GRAY_MASK               0xFF
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_GRAY_SHIFT              0
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_GRAY_LSB_ADDR           \
+	MT6315_BUCK_VBUCK2_DBG3
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_GRAY_LSB_MASK           0x1
+#define MT6315_PMIC_DA_VBUCK2_VOSEL_GRAY_LSB_SHIFT          0
+#define MT6315_PMIC_DA_VBUCK2_EN_ADDR                       \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_EN_MASK                       0x1
+#define MT6315_PMIC_DA_VBUCK2_EN_SHIFT                      0
+#define MT6315_PMIC_DA_VBUCK2_STB_ADDR                      \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_STB_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK2_STB_SHIFT                     1
+#define MT6315_PMIC_DA_VBUCK2_LOOP_SEL_ADDR                 \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_LOOP_SEL_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK2_LOOP_SEL_SHIFT                2
+#define MT6315_PMIC_DA_VBUCK2_R2R_PDN_ADDR                  \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_R2R_PDN_MASK                  0x1
+#define MT6315_PMIC_DA_VBUCK2_R2R_PDN_SHIFT                 3
+#define MT6315_PMIC_DA_VBUCK2_DVS_EN_ADDR                   \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_DVS_EN_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK2_DVS_EN_SHIFT                  4
+#define MT6315_PMIC_DA_VBUCK2_DVS_UP_ADDR                   \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_DVS_UP_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK2_DVS_UP_SHIFT                  5
+#define MT6315_PMIC_DA_VBUCK2_DVS_DOWN_ADDR                 \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_DVS_DOWN_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK2_DVS_DOWN_SHIFT                6
+#define MT6315_PMIC_DA_VBUCK2_SSH_ADDR                      \
+	MT6315_BUCK_VBUCK2_DBG4
+#define MT6315_PMIC_DA_VBUCK2_SSH_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK2_SSH_SHIFT                     7
+#define MT6315_PMIC_DA_VBUCK2_MINFREQ_DISCHARGE_ADDR        \
+	MT6315_BUCK_VBUCK2_DBG5
+#define MT6315_PMIC_DA_VBUCK2_MINFREQ_DISCHARGE_MASK        0x1
+#define MT6315_PMIC_DA_VBUCK2_MINFREQ_DISCHARGE_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_CK_SW_MODE_ADDR          \
+	MT6315_BUCK_VBUCK2_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK2_CK_SW_MODE_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_CK_SW_MODE_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK2_CK_SW_EN_ADDR            \
+	MT6315_BUCK_VBUCK2_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK2_CK_SW_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_CK_SW_EN_SHIFT           5
+#define MT6315_PMIC_RG_BUCK_VBUCK2_TRACK_STALL_BYPASS_ADDR  \
+	MT6315_BUCK_VBUCK2_STALL_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK2_TRACK_STALL_BYPASS_MASK  0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK2_TRACK_STALL_BYPASS_SHIFT 0
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_ID_ADDR                 \
+	MT6315_BUCK_VBUCK3_ANA_ID
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_ID_ADDR                 \
+	MT6315_BUCK_VBUCK3_DIG_ID
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK3_REV0
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK3_REV0
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK3_ANA_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK3_REV1
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK3_REV1
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK3_DIG_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_CBS_ADDR                \
+	MT6315_BUCK_VBUCK3_DBI0
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_CBS_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_CBS_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_BIX_ADDR                \
+	MT6315_BUCK_VBUCK3_DBI0
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_BIX_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_BIX_SHIFT               2
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_ESP_ADDR                \
+	MT6315_BUCK_VBUCK3_DBI1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_ESP_MASK                0xFF
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_ESP_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_SSHUB_ADDR          \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_SSHUB_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_SSHUB_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_TRACKING_ADDR       \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_TRACKING_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_TRACKING_SHIFT      1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_PREOC_ADDR          \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_PREOC_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_PREOC_SHIFT         2
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_VOTER_ADDR          \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_VOTER_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_VOTER_SHIFT         3
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_ULTRASONIC_ADDR     \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_ULTRASONIC_MASK     0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_ULTRASONIC_SHIFT    4
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_DLC_ADDR            \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_DLC_MASK            0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_DLC_SHIFT           5
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_TRAP_ADDR           \
+	MT6315_BUCK_VBUCK3_DXI
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_TRAP_MASK           0x1
+#define MT6315_PMIC_BUCK_VBUCK3_DSN_FPI_TRAP_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR         \
+	MT6315_BUCK_VBUCK3_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SLEEP_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SLEEP_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SLEEP_LSB_ADDR     \
+	MT6315_BUCK_VBUCK3_CON2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SLEEP_LSB_MASK     0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_SLEEP_LSB_SHIFT    0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SELR2R_CTRL_ADDR         \
+	MT6315_BUCK_VBUCK3_SLP_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SELR2R_CTRL_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SELR2R_CTRL_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_EN_MASK_ADDR         \
+	MT6315_BUCK_VBUCK3_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_EN_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_EN_MASK_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_UP_MASK_ADDR         \
+	MT6315_BUCK_VBUCK3_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_UP_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_UP_MASK_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_DOWN_MASK_ADDR       \
+	MT6315_BUCK_VBUCK3_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_DOWN_MASK_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_DVS_DOWN_MASK_SHIFT      2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_RRATE_ADDR         \
+	MT6315_BUCK_VBUCK3_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_RRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_RRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_REN_ADDR           \
+	MT6315_BUCK_VBUCK3_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_REN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_REN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_FRATE_ADDR         \
+	MT6315_BUCK_VBUCK3_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_FRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_FRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_FEN_ADDR           \
+	MT6315_BUCK_VBUCK3_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_FEN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SFCHG_FEN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_EN_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_EN_SHIFT          1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_EN_SHIFT          2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_EN_SHIFT          3
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_EN_SHIFT          4
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_EN_SHIFT          5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_EN_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK3_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_EN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_0_SET_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_EN_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_0_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_0_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_0_CLR_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_EN_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_0_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_0_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SW_OP_EN_ADDR            \
+	MT6315_BUCK_VBUCK3_OP_EN_1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SW_OP_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_SW_OP_EN_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_1_SET_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_EN_1_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_1_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_1_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_1_CLR_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_EN_1_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_1_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_EN_1_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_CFG_SHIFT         0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_CFG_SHIFT         1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_CFG_SHIFT         2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_CFG_SHIFT         3
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_CFG_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_CFG_SHIFT         5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_CFG_SHIFT         6
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK3_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_CFG_SHIFT         7
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_CFG_0_SET_ADDR        \
+	MT6315_BUCK_VBUCK3_OP_CFG_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_CFG_0_SET_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_CFG_0_SET_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_CFG_0_CLR_ADDR        \
+	MT6315_BUCK_VBUCK3_OP_CFG_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_CFG_0_CLR_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_CFG_0_CLR_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW0_OP_MODE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW1_OP_MODE_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW2_OP_MODE_SHIFT        2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW3_OP_MODE_SHIFT        3
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW4_OP_MODE_SHIFT        4
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW5_OP_MODE_SHIFT        5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW6_OP_MODE_SHIFT        6
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK3_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_HW7_OP_MODE_SHIFT        7
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_MODE_0_SET_ADDR       \
+	MT6315_BUCK_VBUCK3_OP_MODE_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_MODE_0_SET_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_MODE_0_SET_SHIFT      0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_MODE_0_CLR_ADDR       \
+	MT6315_BUCK_VBUCK3_OP_MODE_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_MODE_0_CLR_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_OP_MODE_0_CLR_SHIFT      0
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_ADDR                    \
+	MT6315_BUCK_VBUCK3_DBG0
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_MASK                    0xFF
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_SHIFT                   0
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_LSB_ADDR                \
+	MT6315_BUCK_VBUCK3_DBG1
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_LSB_MASK                0x1
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_LSB_SHIFT               0
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_GRAY_ADDR               \
+	MT6315_BUCK_VBUCK3_DBG2
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_GRAY_MASK               0xFF
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_GRAY_SHIFT              0
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_GRAY_LSB_ADDR           \
+	MT6315_BUCK_VBUCK3_DBG3
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_GRAY_LSB_MASK           0x1
+#define MT6315_PMIC_DA_VBUCK3_VOSEL_GRAY_LSB_SHIFT          0
+#define MT6315_PMIC_DA_VBUCK3_EN_ADDR                       \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_EN_MASK                       0x1
+#define MT6315_PMIC_DA_VBUCK3_EN_SHIFT                      0
+#define MT6315_PMIC_DA_VBUCK3_STB_ADDR                      \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_STB_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK3_STB_SHIFT                     1
+#define MT6315_PMIC_DA_VBUCK3_LOOP_SEL_ADDR                 \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_LOOP_SEL_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK3_LOOP_SEL_SHIFT                2
+#define MT6315_PMIC_DA_VBUCK3_R2R_PDN_ADDR                  \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_R2R_PDN_MASK                  0x1
+#define MT6315_PMIC_DA_VBUCK3_R2R_PDN_SHIFT                 3
+#define MT6315_PMIC_DA_VBUCK3_DVS_EN_ADDR                   \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_DVS_EN_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK3_DVS_EN_SHIFT                  4
+#define MT6315_PMIC_DA_VBUCK3_DVS_UP_ADDR                   \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_DVS_UP_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK3_DVS_UP_SHIFT                  5
+#define MT6315_PMIC_DA_VBUCK3_DVS_DOWN_ADDR                 \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_DVS_DOWN_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK3_DVS_DOWN_SHIFT                6
+#define MT6315_PMIC_DA_VBUCK3_SSH_ADDR                      \
+	MT6315_BUCK_VBUCK3_DBG4
+#define MT6315_PMIC_DA_VBUCK3_SSH_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK3_SSH_SHIFT                     7
+#define MT6315_PMIC_DA_VBUCK3_MINFREQ_DISCHARGE_ADDR        \
+	MT6315_BUCK_VBUCK3_DBG5
+#define MT6315_PMIC_DA_VBUCK3_MINFREQ_DISCHARGE_MASK        0x1
+#define MT6315_PMIC_DA_VBUCK3_MINFREQ_DISCHARGE_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_CK_SW_MODE_ADDR          \
+	MT6315_BUCK_VBUCK3_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_CK_SW_MODE_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_CK_SW_MODE_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK3_CK_SW_EN_ADDR            \
+	MT6315_BUCK_VBUCK3_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_CK_SW_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_CK_SW_EN_SHIFT           5
+#define MT6315_PMIC_RG_BUCK_VBUCK3_TRACK_EN_ADDR            \
+	MT6315_BUCK_VBUCK3_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_TRACK_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_TRACK_EN_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_TRACK_MODE_ADDR          \
+	MT6315_BUCK_VBUCK3_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_TRACK_MODE_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_TRACK_MODE_SHIFT         1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_DELTA_ADDR         \
+	MT6315_BUCK_VBUCK3_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_DELTA_MASK         0xF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_DELTA_SHIFT        4
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_OFFSET_ADDR        \
+	MT6315_BUCK_VBUCK3_TRACK1
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_OFFSET_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_OFFSET_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LB_ADDR            \
+	MT6315_BUCK_VBUCK3_TRACK2
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LB_MASK            0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_LB_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_HB_ADDR            \
+	MT6315_BUCK_VBUCK3_TRACK3
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_HB_MASK            0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK3_VOSEL_HB_SHIFT           0
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_ID_ADDR                 \
+	MT6315_BUCK_VBUCK4_ANA_ID
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_ID_ADDR                 \
+	MT6315_BUCK_VBUCK4_DIG_ID
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_ID_MASK                 0xFF
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_ID_SHIFT                0
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK4_REV0
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK4_REV0
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK4_ANA_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_MINOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK4_REV1
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_MINOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_MINOR_REV_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_MAJOR_REV_ADDR          \
+	MT6315_BUCK_VBUCK4_REV1
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_MAJOR_REV_MASK          0xF
+#define MT6315_PMIC_BUCK_VBUCK4_DIG_MAJOR_REV_SHIFT         4
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_CBS_ADDR                \
+	MT6315_BUCK_VBUCK4_DBI0
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_CBS_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_CBS_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_BIX_ADDR                \
+	MT6315_BUCK_VBUCK4_DBI0
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_BIX_MASK                0x3
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_BIX_SHIFT               2
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_ESP_ADDR                \
+	MT6315_BUCK_VBUCK4_DBI1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_ESP_MASK                0xFF
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_ESP_SHIFT               0
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_SSHUB_ADDR          \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_SSHUB_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_SSHUB_SHIFT         0
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_TRACKING_ADDR       \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_TRACKING_MASK       0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_TRACKING_SHIFT      1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_PREOC_ADDR          \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_PREOC_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_PREOC_SHIFT         2
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_VOTER_ADDR          \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_VOTER_MASK          0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_VOTER_SHIFT         3
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_ULTRASONIC_ADDR     \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_ULTRASONIC_MASK     0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_ULTRASONIC_SHIFT    4
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_DLC_ADDR            \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_DLC_MASK            0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_DLC_SHIFT           5
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_TRAP_ADDR           \
+	MT6315_BUCK_VBUCK4_DXI
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_TRAP_MASK           0x1
+#define MT6315_PMIC_BUCK_VBUCK4_DSN_FPI_TRAP_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR         \
+	MT6315_BUCK_VBUCK4_CON1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SLEEP_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SLEEP_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SLEEP_LSB_ADDR     \
+	MT6315_BUCK_VBUCK4_CON2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SLEEP_LSB_MASK     0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_SLEEP_LSB_SHIFT    0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SELR2R_CTRL_ADDR         \
+	MT6315_BUCK_VBUCK4_SLP_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SELR2R_CTRL_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SELR2R_CTRL_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_EN_MASK_ADDR         \
+	MT6315_BUCK_VBUCK4_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_EN_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_EN_MASK_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_UP_MASK_ADDR         \
+	MT6315_BUCK_VBUCK4_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_UP_MASK_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_UP_MASK_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_DOWN_MASK_ADDR       \
+	MT6315_BUCK_VBUCK4_DVS_CON
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_DOWN_MASK_MASK       0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_DVS_DOWN_MASK_SHIFT      2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_RRATE_ADDR         \
+	MT6315_BUCK_VBUCK4_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_RRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_RRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_REN_ADDR           \
+	MT6315_BUCK_VBUCK4_CFG0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_REN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_REN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_FRATE_ADDR         \
+	MT6315_BUCK_VBUCK4_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_FRATE_MASK         0x7F
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_FRATE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_FEN_ADDR           \
+	MT6315_BUCK_VBUCK4_CFG1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_FEN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SFCHG_FEN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_EN_SHIFT          0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_EN_SHIFT          1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_EN_SHIFT          2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_EN_SHIFT          3
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_EN_SHIFT          4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_EN_SHIFT          5
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_EN_SHIFT          6
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_EN_ADDR           \
+	MT6315_BUCK_VBUCK4_OP_EN_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_EN_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_EN_SHIFT          7
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_0_SET_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_EN_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_0_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_0_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_0_CLR_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_EN_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_0_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_0_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SW_OP_EN_ADDR            \
+	MT6315_BUCK_VBUCK4_OP_EN_1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SW_OP_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_SW_OP_EN_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_1_SET_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_EN_1_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_1_SET_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_1_SET_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_1_CLR_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_EN_1_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_1_CLR_MASK         0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_EN_1_CLR_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_CFG_SHIFT         0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_CFG_SHIFT         1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_CFG_SHIFT         2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_CFG_SHIFT         3
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_CFG_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_CFG_SHIFT         5
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_CFG_SHIFT         6
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_CFG_ADDR          \
+	MT6315_BUCK_VBUCK4_OP_CFG_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_CFG_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_CFG_SHIFT         7
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_CFG_0_SET_ADDR        \
+	MT6315_BUCK_VBUCK4_OP_CFG_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_CFG_0_SET_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_CFG_0_SET_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_CFG_0_CLR_ADDR        \
+	MT6315_BUCK_VBUCK4_OP_CFG_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_CFG_0_CLR_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_CFG_0_CLR_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW0_OP_MODE_SHIFT        0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW1_OP_MODE_SHIFT        1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW2_OP_MODE_SHIFT        2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW3_OP_MODE_SHIFT        3
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW4_OP_MODE_SHIFT        4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW5_OP_MODE_SHIFT        5
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW6_OP_MODE_SHIFT        6
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_MODE_ADDR         \
+	MT6315_BUCK_VBUCK4_OP_MODE_0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_MODE_MASK         0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_HW7_OP_MODE_SHIFT        7
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_MODE_0_SET_ADDR       \
+	MT6315_BUCK_VBUCK4_OP_MODE_0_SET
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_MODE_0_SET_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_MODE_0_SET_SHIFT      0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_MODE_0_CLR_ADDR       \
+	MT6315_BUCK_VBUCK4_OP_MODE_0_CLR
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_MODE_0_CLR_MASK       0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_OP_MODE_0_CLR_SHIFT      0
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_ADDR                    \
+	MT6315_BUCK_VBUCK4_DBG0
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_MASK                    0xFF
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_SHIFT                   0
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_LSB_ADDR                \
+	MT6315_BUCK_VBUCK4_DBG1
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_LSB_MASK                0x1
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_LSB_SHIFT               0
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_GRAY_ADDR               \
+	MT6315_BUCK_VBUCK4_DBG2
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_GRAY_MASK               0xFF
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_GRAY_SHIFT              0
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_GRAY_LSB_ADDR           \
+	MT6315_BUCK_VBUCK4_DBG3
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_GRAY_LSB_MASK           0x1
+#define MT6315_PMIC_DA_VBUCK4_VOSEL_GRAY_LSB_SHIFT          0
+#define MT6315_PMIC_DA_VBUCK4_EN_ADDR                       \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_EN_MASK                       0x1
+#define MT6315_PMIC_DA_VBUCK4_EN_SHIFT                      0
+#define MT6315_PMIC_DA_VBUCK4_STB_ADDR                      \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_STB_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK4_STB_SHIFT                     1
+#define MT6315_PMIC_DA_VBUCK4_LOOP_SEL_ADDR                 \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_LOOP_SEL_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK4_LOOP_SEL_SHIFT                2
+#define MT6315_PMIC_DA_VBUCK4_R2R_PDN_ADDR                  \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_R2R_PDN_MASK                  0x1
+#define MT6315_PMIC_DA_VBUCK4_R2R_PDN_SHIFT                 3
+#define MT6315_PMIC_DA_VBUCK4_DVS_EN_ADDR                   \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_DVS_EN_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK4_DVS_EN_SHIFT                  4
+#define MT6315_PMIC_DA_VBUCK4_DVS_UP_ADDR                   \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_DVS_UP_MASK                   0x1
+#define MT6315_PMIC_DA_VBUCK4_DVS_UP_SHIFT                  5
+#define MT6315_PMIC_DA_VBUCK4_DVS_DOWN_ADDR                 \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_DVS_DOWN_MASK                 0x1
+#define MT6315_PMIC_DA_VBUCK4_DVS_DOWN_SHIFT                6
+#define MT6315_PMIC_DA_VBUCK4_SSH_ADDR                      \
+	MT6315_BUCK_VBUCK4_DBG4
+#define MT6315_PMIC_DA_VBUCK4_SSH_MASK                      0x1
+#define MT6315_PMIC_DA_VBUCK4_SSH_SHIFT                     7
+#define MT6315_PMIC_DA_VBUCK4_MINFREQ_DISCHARGE_ADDR        \
+	MT6315_BUCK_VBUCK4_DBG5
+#define MT6315_PMIC_DA_VBUCK4_MINFREQ_DISCHARGE_MASK        0x1
+#define MT6315_PMIC_DA_VBUCK4_MINFREQ_DISCHARGE_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_CK_SW_MODE_ADDR          \
+	MT6315_BUCK_VBUCK4_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK4_CK_SW_MODE_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_CK_SW_MODE_SHIFT         4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_CK_SW_EN_ADDR            \
+	MT6315_BUCK_VBUCK4_DBG5
+#define MT6315_PMIC_RG_BUCK_VBUCK4_CK_SW_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_CK_SW_EN_SHIFT           5
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_EN_ADDR            \
+	MT6315_BUCK_VBUCK4_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_EN_MASK            0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_EN_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_MODE_ADDR          \
+	MT6315_BUCK_VBUCK4_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_MODE_MASK          0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_MODE_SHIFT         1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_CFG_ADDR           \
+	MT6315_BUCK_VBUCK4_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_CFG_MASK           0x1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_TRACK_CFG_SHIFT          2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_DELTA_ADDR         \
+	MT6315_BUCK_VBUCK4_TRACK0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_DELTA_MASK         0xF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_DELTA_SHIFT        4
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_OFFSET_ADDR        \
+	MT6315_BUCK_VBUCK4_TRACK1
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_OFFSET_MASK        0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_OFFSET_SHIFT       0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LB_ADDR            \
+	MT6315_BUCK_VBUCK4_TRACK2
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LB_MASK            0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_LB_SHIFT           0
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_HB_ADDR            \
+	MT6315_BUCK_VBUCK4_TRACK3
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_HB_MASK            0xFF
+#define MT6315_PMIC_RG_BUCK_VBUCK4_VOSEL_HB_SHIFT           0
+#define MT6315_PMIC_BUCK_ANA0_ANA_ID_ADDR                   \
+	MT6315_BUCK_ANA0_ANA_ID
+#define MT6315_PMIC_BUCK_ANA0_ANA_ID_MASK                   0xFF
+#define MT6315_PMIC_BUCK_ANA0_ANA_ID_SHIFT                  0
+#define MT6315_PMIC_BUCK_ANA0_DIG_ID_ADDR                   \
+	MT6315_BUCK_ANA0_DIG_ID
+#define MT6315_PMIC_BUCK_ANA0_DIG_ID_MASK                   0xFF
+#define MT6315_PMIC_BUCK_ANA0_DIG_ID_SHIFT                  0
+#define MT6315_PMIC_BUCK_ANA0_ANA_MINOR_REV_ADDR            \
+	MT6315_BUCK_ANA0_DSN_REV0
+#define MT6315_PMIC_BUCK_ANA0_ANA_MINOR_REV_MASK            0xF
+#define MT6315_PMIC_BUCK_ANA0_ANA_MINOR_REV_SHIFT           0
+#define MT6315_PMIC_BUCK_ANA0_ANA_MAJOR_REV_ADDR            \
+	MT6315_BUCK_ANA0_DSN_REV0
+#define MT6315_PMIC_BUCK_ANA0_ANA_MAJOR_REV_MASK            0xF
+#define MT6315_PMIC_BUCK_ANA0_ANA_MAJOR_REV_SHIFT           4
+#define MT6315_PMIC_BUCK_ANA0_DIG_MINOR_REV_ADDR            \
+	MT6315_BUCK_ANA0_DSN_REV1
+#define MT6315_PMIC_BUCK_ANA0_DIG_MINOR_REV_MASK            0xF
+#define MT6315_PMIC_BUCK_ANA0_DIG_MINOR_REV_SHIFT           0
+#define MT6315_PMIC_BUCK_ANA0_DIG_MAJOR_REV_ADDR            \
+	MT6315_BUCK_ANA0_DSN_REV1
+#define MT6315_PMIC_BUCK_ANA0_DIG_MAJOR_REV_MASK            0xF
+#define MT6315_PMIC_BUCK_ANA0_DIG_MAJOR_REV_SHIFT           4
+#define MT6315_PMIC_BUCK_ANA0_CBS_ADDR                      \
+	MT6315_BUCK_ANA0_DBI0
+#define MT6315_PMIC_BUCK_ANA0_CBS_MASK                      0x3
+#define MT6315_PMIC_BUCK_ANA0_CBS_SHIFT                     0
+#define MT6315_PMIC_BUCK_ANA0_BIX_ADDR                      \
+	MT6315_BUCK_ANA0_DBI0
+#define MT6315_PMIC_BUCK_ANA0_BIX_MASK                      0x3
+#define MT6315_PMIC_BUCK_ANA0_BIX_SHIFT                     2
+#define MT6315_PMIC_BUCK_ANA0_ESP_ADDR                      \
+	MT6315_BUCK_ANA0_DBI1
+#define MT6315_PMIC_BUCK_ANA0_ESP_MASK                      0xFF
+#define MT6315_PMIC_BUCK_ANA0_ESP_SHIFT                     0
+#define MT6315_PMIC_BUCK_ANA0_FPI_ADDR                      \
+	MT6315_BUCK_ANA0_DXI
+#define MT6315_PMIC_BUCK_ANA0_FPI_MASK                      0xFF
+#define MT6315_PMIC_BUCK_ANA0_FPI_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK1_NDIS_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_NDIS_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK1_NDIS_EN_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK1_SLEEP_TIME_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_SLEEP_TIME_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK1_SLEEP_TIME_SHIFT              1
+#define MT6315_PMIC_RG_VBUCK1_LOOPSEL_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_LOOPSEL_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK1_LOOPSEL_DIS_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK1_OVP_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_OVP_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK1_OVP_EN_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK1_OVP_VREFSEL_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_OVP_VREFSEL_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK1_OVP_VREFSEL_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK1_TB_DIS_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_TB_DIS_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK1_TB_DIS_SHIFT                  6
+#define MT6315_PMIC_RG_VBUCK1_TB_PFM_OFF_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON0
+#define MT6315_PMIC_RG_VBUCK1_TB_PFM_OFF_MASK               0x1
+#define MT6315_PMIC_RG_VBUCK1_TB_PFM_OFF_SHIFT              7
+#define MT6315_PMIC_RG_VBUCK1_TB_VREFSEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_TB_VREFSEL_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK1_TB_VREFSEL_SHIFT              0
+#define MT6315_PMIC_RG_VBUCK1_TON_EXTEND_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_TON_EXTEND_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK1_TON_EXTEND_EN_SHIFT           2
+#define MT6315_PMIC_RG_VBUCK1_VBAT_LOW_DIS_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_VBAT_LOW_DIS_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK1_VBAT_LOW_DIS_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK1_VBAT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_VBAT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK1_VBAT_HI_DIS_SHIFT             4
+#define MT6315_PMIC_RG_VBUCK1_VOUT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_VOUT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK1_VOUT_HI_DIS_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK1_FUGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_FUGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK1_FUGON_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK1_FLGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON1
+#define MT6315_PMIC_RG_VBUCK1_FLGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK1_FLGON_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK1_RAMP_AC_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON2
+#define MT6315_PMIC_RG_VBUCK1_RAMP_AC_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK1_RAMP_AC_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK1_URT_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON2
+#define MT6315_PMIC_RG_VBUCK1_URT_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK1_URT_EN_SHIFT                  2
+#define MT6315_PMIC_RG_VBUCK1_RETENTION_EN_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON2
+#define MT6315_PMIC_RG_VBUCK1_RETENTION_EN_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK1_RETENTION_EN_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK1_SONIC_EN_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON2
+#define MT6315_PMIC_RG_VBUCK1_SONIC_EN_MASK                 0x1
+#define MT6315_PMIC_RG_VBUCK1_SONIC_EN_SHIFT                4
+#define MT6315_PMIC_RG_VBUCK1_GROUNDSEL_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON2
+#define MT6315_PMIC_RG_VBUCK1_GROUNDSEL_MASK                0x1
+#define MT6315_PMIC_RG_VBUCK1_GROUNDSEL_SHIFT               5
+#define MT6315_PMIC_RG_VBUCK1_DLC_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON2
+#define MT6315_PMIC_RG_VBUCK1_DLC_MASK                      0x3
+#define MT6315_PMIC_RG_VBUCK1_DLC_SHIFT                     6
+#define MT6315_PMIC_RG_VBUCK1_RCB_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON3
+#define MT6315_PMIC_RG_VBUCK1_RCB_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK1_RCB_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK1_UG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON3
+#define MT6315_PMIC_RG_VBUCK1_UG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK1_UG_SR_SHIFT                   3
+#define MT6315_PMIC_RG_VBUCK1_LG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON3
+#define MT6315_PMIC_RG_VBUCK1_LG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK1_LG_SR_SHIFT                   5
+#define MT6315_PMIC_RG_VBUCK1_ECOT_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON3
+#define MT6315_PMIC_RG_VBUCK1_ECOT_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK1_ECOT_EN_SHIFT                 7
+#define MT6315_PMIC_RG_VBUCK1_OCP_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON4
+#define MT6315_PMIC_RG_VBUCK1_OCP_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK1_OCP_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK1_OCN_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON4
+#define MT6315_PMIC_RG_VBUCK1_OCN_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK1_OCN_SHIFT                     3
+#define MT6315_PMIC_RG_VBUCK1_DUMMY_LOAD_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON4
+#define MT6315_PMIC_RG_VBUCK1_DUMMY_LOAD_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK1_DUMMY_LOAD_EN_SHIFT           6
+#define MT6315_PMIC_RG_VBUCK1_RON_TM_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON4
+#define MT6315_PMIC_RG_VBUCK1_RON_TM_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK1_RON_TM_SHIFT                  7
+#define MT6315_PMIC_RG_VBUCK1_DIGMON_SEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON5
+#define MT6315_PMIC_RG_VBUCK1_DIGMON_SEL_MASK               0x3F
+#define MT6315_PMIC_RG_VBUCK1_DIGMON_SEL_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK1_OC_STATUS_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON6
+#define MT6315_PMIC_RGS_VBUCK1_OC_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK1_OC_STATUS_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK1_DIG_MON_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON6
+#define MT6315_PMIC_RGS_VBUCK1_DIG_MON_MASK                 0x1
+#define MT6315_PMIC_RGS_VBUCK1_DIG_MON_SHIFT                1
+#define MT6315_PMIC_RG_VBUCK1_UG_ONSR_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON6
+#define MT6315_PMIC_RG_VBUCK1_UG_ONSR_MASK                  0x3
+#define MT6315_PMIC_RG_VBUCK1_UG_ONSR_SHIFT                 2
+#define MT6315_PMIC_RG_VBUCK1_LXRON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON6
+#define MT6315_PMIC_RG_VBUCK1_LXRON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK1_LXRON_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK1_RSVH_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON7
+#define MT6315_PMIC_RG_VBUCK1_RSVH_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK1_RSVH_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK1_RSVL_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON8
+#define MT6315_PMIC_RG_VBUCK1_RSVL_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK1_RSVL_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK1_TM_ADDR                       \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON9
+#define MT6315_PMIC_RG_VBUCK1_TM_MASK                       0xF
+#define MT6315_PMIC_RG_VBUCK1_TM_SHIFT                      0
+#define MT6315_PMIC_RG_VBUCK1_TM_KEY_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON9
+#define MT6315_PMIC_RG_VBUCK1_TM_KEY_MASK                   0x3
+#define MT6315_PMIC_RG_VBUCK1_TM_KEY_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK2_NDIS_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_NDIS_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK2_NDIS_EN_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK2_SLEEP_TIME_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_SLEEP_TIME_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK2_SLEEP_TIME_SHIFT              1
+#define MT6315_PMIC_RG_VBUCK2_LOOPSEL_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_LOOPSEL_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK2_LOOPSEL_DIS_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK2_OVP_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_OVP_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK2_OVP_EN_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK2_OVP_VREFSEL_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_OVP_VREFSEL_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK2_OVP_VREFSEL_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK2_TB_DIS_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_TB_DIS_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK2_TB_DIS_SHIFT                  6
+#define MT6315_PMIC_RG_VBUCK2_TB_PFM_OFF_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON10
+#define MT6315_PMIC_RG_VBUCK2_TB_PFM_OFF_MASK               0x1
+#define MT6315_PMIC_RG_VBUCK2_TB_PFM_OFF_SHIFT              7
+#define MT6315_PMIC_RG_VBUCK2_TB_VREFSEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_TB_VREFSEL_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK2_TB_VREFSEL_SHIFT              0
+#define MT6315_PMIC_RG_VBUCK2_TON_EXTEND_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_TON_EXTEND_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK2_TON_EXTEND_EN_SHIFT           2
+#define MT6315_PMIC_RG_VBUCK2_VBAT_LOW_DIS_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_VBAT_LOW_DIS_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK2_VBAT_LOW_DIS_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK2_VBAT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_VBAT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK2_VBAT_HI_DIS_SHIFT             4
+#define MT6315_PMIC_RG_VBUCK2_VOUT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_VOUT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK2_VOUT_HI_DIS_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK2_FUGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_FUGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK2_FUGON_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK2_FLGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON11
+#define MT6315_PMIC_RG_VBUCK2_FLGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK2_FLGON_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK2_RAMP_AC_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON12
+#define MT6315_PMIC_RG_VBUCK2_RAMP_AC_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK2_RAMP_AC_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK2_URT_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON12
+#define MT6315_PMIC_RG_VBUCK2_URT_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK2_URT_EN_SHIFT                  2
+#define MT6315_PMIC_RG_VBUCK2_RETENTION_EN_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON12
+#define MT6315_PMIC_RG_VBUCK2_RETENTION_EN_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK2_RETENTION_EN_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK2_SONIC_EN_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON12
+#define MT6315_PMIC_RG_VBUCK2_SONIC_EN_MASK                 0x1
+#define MT6315_PMIC_RG_VBUCK2_SONIC_EN_SHIFT                4
+#define MT6315_PMIC_RG_VBUCK2_GROUNDSEL_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON12
+#define MT6315_PMIC_RG_VBUCK2_GROUNDSEL_MASK                0x1
+#define MT6315_PMIC_RG_VBUCK2_GROUNDSEL_SHIFT               5
+#define MT6315_PMIC_RG_VBUCK2_DLC_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON12
+#define MT6315_PMIC_RG_VBUCK2_DLC_MASK                      0x3
+#define MT6315_PMIC_RG_VBUCK2_DLC_SHIFT                     6
+#define MT6315_PMIC_RG_VBUCK2_RCB_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON13
+#define MT6315_PMIC_RG_VBUCK2_RCB_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK2_RCB_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK2_UG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON13
+#define MT6315_PMIC_RG_VBUCK2_UG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK2_UG_SR_SHIFT                   3
+#define MT6315_PMIC_RG_VBUCK2_LG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON13
+#define MT6315_PMIC_RG_VBUCK2_LG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK2_LG_SR_SHIFT                   5
+#define MT6315_PMIC_RG_VBUCK2_ECOT_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON13
+#define MT6315_PMIC_RG_VBUCK2_ECOT_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK2_ECOT_EN_SHIFT                 7
+#define MT6315_PMIC_RG_VBUCK2_OCP_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON14
+#define MT6315_PMIC_RG_VBUCK2_OCP_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK2_OCP_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK2_OCN_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON14
+#define MT6315_PMIC_RG_VBUCK2_OCN_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK2_OCN_SHIFT                     3
+#define MT6315_PMIC_RG_VBUCK2_DUMMY_LOAD_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON14
+#define MT6315_PMIC_RG_VBUCK2_DUMMY_LOAD_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK2_DUMMY_LOAD_EN_SHIFT           6
+#define MT6315_PMIC_RG_VBUCK2_RON_TM_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON14
+#define MT6315_PMIC_RG_VBUCK2_RON_TM_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK2_RON_TM_SHIFT                  7
+#define MT6315_PMIC_RG_VBUCK2_DIGMON_SEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON15
+#define MT6315_PMIC_RG_VBUCK2_DIGMON_SEL_MASK               0x3F
+#define MT6315_PMIC_RG_VBUCK2_DIGMON_SEL_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK2_OC_STATUS_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON16
+#define MT6315_PMIC_RGS_VBUCK2_OC_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK2_OC_STATUS_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK2_DIG_MON_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON16
+#define MT6315_PMIC_RGS_VBUCK2_DIG_MON_MASK                 0x1
+#define MT6315_PMIC_RGS_VBUCK2_DIG_MON_SHIFT                1
+#define MT6315_PMIC_RG_VBUCK2_UG_ONSR_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON16
+#define MT6315_PMIC_RG_VBUCK2_UG_ONSR_MASK                  0x3
+#define MT6315_PMIC_RG_VBUCK2_UG_ONSR_SHIFT                 2
+#define MT6315_PMIC_RG_VBUCK2_LXRON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON16
+#define MT6315_PMIC_RG_VBUCK2_LXRON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK2_LXRON_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK2_RSVH_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON17
+#define MT6315_PMIC_RG_VBUCK2_RSVH_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK2_RSVH_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK2_RSVL_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON18
+#define MT6315_PMIC_RG_VBUCK2_RSVL_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK2_RSVL_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK2_TM_ADDR                       \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON19
+#define MT6315_PMIC_RG_VBUCK2_TM_MASK                       0xF
+#define MT6315_PMIC_RG_VBUCK2_TM_SHIFT                      0
+#define MT6315_PMIC_RG_VBUCK2_TM_KEY_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON19
+#define MT6315_PMIC_RG_VBUCK2_TM_KEY_MASK                   0x3
+#define MT6315_PMIC_RG_VBUCK2_TM_KEY_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK3_NDIS_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_NDIS_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK3_NDIS_EN_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK3_SLEEP_TIME_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_SLEEP_TIME_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK3_SLEEP_TIME_SHIFT              1
+#define MT6315_PMIC_RG_VBUCK3_LOOPSEL_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_LOOPSEL_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK3_LOOPSEL_DIS_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK3_OVP_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_OVP_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK3_OVP_EN_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK3_OVP_VREFSEL_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_OVP_VREFSEL_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK3_OVP_VREFSEL_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK3_TB_DIS_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_TB_DIS_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK3_TB_DIS_SHIFT                  6
+#define MT6315_PMIC_RG_VBUCK3_TB_PFM_OFF_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON20
+#define MT6315_PMIC_RG_VBUCK3_TB_PFM_OFF_MASK               0x1
+#define MT6315_PMIC_RG_VBUCK3_TB_PFM_OFF_SHIFT              7
+#define MT6315_PMIC_RG_VBUCK3_TB_VREFSEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_TB_VREFSEL_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK3_TB_VREFSEL_SHIFT              0
+#define MT6315_PMIC_RG_VBUCK3_TON_EXTEND_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_TON_EXTEND_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK3_TON_EXTEND_EN_SHIFT           2
+#define MT6315_PMIC_RG_VBUCK3_VBAT_LOW_DIS_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_VBAT_LOW_DIS_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK3_VBAT_LOW_DIS_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK3_VBAT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_VBAT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK3_VBAT_HI_DIS_SHIFT             4
+#define MT6315_PMIC_RG_VBUCK3_VOUT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_VOUT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK3_VOUT_HI_DIS_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK3_FUGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_FUGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK3_FUGON_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK3_FLGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON21
+#define MT6315_PMIC_RG_VBUCK3_FLGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK3_FLGON_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK3_RAMP_AC_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON22
+#define MT6315_PMIC_RG_VBUCK3_RAMP_AC_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK3_RAMP_AC_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK3_URT_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON22
+#define MT6315_PMIC_RG_VBUCK3_URT_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK3_URT_EN_SHIFT                  2
+#define MT6315_PMIC_RG_VBUCK3_RETENTION_EN_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON22
+#define MT6315_PMIC_RG_VBUCK3_RETENTION_EN_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK3_RETENTION_EN_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK3_SONIC_EN_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON22
+#define MT6315_PMIC_RG_VBUCK3_SONIC_EN_MASK                 0x1
+#define MT6315_PMIC_RG_VBUCK3_SONIC_EN_SHIFT                4
+#define MT6315_PMIC_RG_VBUCK3_GROUNDSEL_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON22
+#define MT6315_PMIC_RG_VBUCK3_GROUNDSEL_MASK                0x1
+#define MT6315_PMIC_RG_VBUCK3_GROUNDSEL_SHIFT               5
+#define MT6315_PMIC_RG_VBUCK3_DLC_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON22
+#define MT6315_PMIC_RG_VBUCK3_DLC_MASK                      0x3
+#define MT6315_PMIC_RG_VBUCK3_DLC_SHIFT                     6
+#define MT6315_PMIC_RG_VBUCK3_RCB_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON23
+#define MT6315_PMIC_RG_VBUCK3_RCB_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK3_RCB_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK3_UG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON23
+#define MT6315_PMIC_RG_VBUCK3_UG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK3_UG_SR_SHIFT                   3
+#define MT6315_PMIC_RG_VBUCK3_LG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON23
+#define MT6315_PMIC_RG_VBUCK3_LG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK3_LG_SR_SHIFT                   5
+#define MT6315_PMIC_RG_VBUCK3_ECOT_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON23
+#define MT6315_PMIC_RG_VBUCK3_ECOT_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK3_ECOT_EN_SHIFT                 7
+#define MT6315_PMIC_RG_VBUCK3_OCP_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON24
+#define MT6315_PMIC_RG_VBUCK3_OCP_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK3_OCP_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK3_OCN_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON24
+#define MT6315_PMIC_RG_VBUCK3_OCN_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK3_OCN_SHIFT                     3
+#define MT6315_PMIC_RG_VBUCK3_DUMMY_LOAD_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON24
+#define MT6315_PMIC_RG_VBUCK3_DUMMY_LOAD_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK3_DUMMY_LOAD_EN_SHIFT           6
+#define MT6315_PMIC_RG_VBUCK3_RON_TM_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON24
+#define MT6315_PMIC_RG_VBUCK3_RON_TM_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK3_RON_TM_SHIFT                  7
+#define MT6315_PMIC_RG_VBUCK3_DIGMON_SEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON25
+#define MT6315_PMIC_RG_VBUCK3_DIGMON_SEL_MASK               0x3F
+#define MT6315_PMIC_RG_VBUCK3_DIGMON_SEL_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK3_OC_STATUS_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON26
+#define MT6315_PMIC_RGS_VBUCK3_OC_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK3_OC_STATUS_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK3_DIG_MON_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON26
+#define MT6315_PMIC_RGS_VBUCK3_DIG_MON_MASK                 0x1
+#define MT6315_PMIC_RGS_VBUCK3_DIG_MON_SHIFT                1
+#define MT6315_PMIC_RG_VBUCK3_UG_ONSR_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON26
+#define MT6315_PMIC_RG_VBUCK3_UG_ONSR_MASK                  0x3
+#define MT6315_PMIC_RG_VBUCK3_UG_ONSR_SHIFT                 2
+#define MT6315_PMIC_RG_VBUCK3_LXRON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON26
+#define MT6315_PMIC_RG_VBUCK3_LXRON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK3_LXRON_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK3_RSVH_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON27
+#define MT6315_PMIC_RG_VBUCK3_RSVH_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK3_RSVH_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK3_RSVL_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON28
+#define MT6315_PMIC_RG_VBUCK3_RSVL_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK3_RSVL_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK3_TM_ADDR                       \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON29
+#define MT6315_PMIC_RG_VBUCK3_TM_MASK                       0xF
+#define MT6315_PMIC_RG_VBUCK3_TM_SHIFT                      0
+#define MT6315_PMIC_RG_VBUCK3_TM_KEY_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON29
+#define MT6315_PMIC_RG_VBUCK3_TM_KEY_MASK                   0x3
+#define MT6315_PMIC_RG_VBUCK3_TM_KEY_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK4_NDIS_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_NDIS_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK4_NDIS_EN_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK4_SLEEP_TIME_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_SLEEP_TIME_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK4_SLEEP_TIME_SHIFT              1
+#define MT6315_PMIC_RG_VBUCK4_LOOPSEL_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_LOOPSEL_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK4_LOOPSEL_DIS_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK4_OVP_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_OVP_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK4_OVP_EN_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK4_OVP_VREFSEL_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_OVP_VREFSEL_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK4_OVP_VREFSEL_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK4_TB_DIS_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_TB_DIS_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK4_TB_DIS_SHIFT                  6
+#define MT6315_PMIC_RG_VBUCK4_TB_PFM_OFF_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON30
+#define MT6315_PMIC_RG_VBUCK4_TB_PFM_OFF_MASK               0x1
+#define MT6315_PMIC_RG_VBUCK4_TB_PFM_OFF_SHIFT              7
+#define MT6315_PMIC_RG_VBUCK4_TB_VREFSEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_TB_VREFSEL_MASK               0x3
+#define MT6315_PMIC_RG_VBUCK4_TB_VREFSEL_SHIFT              0
+#define MT6315_PMIC_RG_VBUCK4_TON_EXTEND_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_TON_EXTEND_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK4_TON_EXTEND_EN_SHIFT           2
+#define MT6315_PMIC_RG_VBUCK4_VBAT_LOW_DIS_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_VBAT_LOW_DIS_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK4_VBAT_LOW_DIS_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK4_VBAT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_VBAT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK4_VBAT_HI_DIS_SHIFT             4
+#define MT6315_PMIC_RG_VBUCK4_VOUT_HI_DIS_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_VOUT_HI_DIS_MASK              0x1
+#define MT6315_PMIC_RG_VBUCK4_VOUT_HI_DIS_SHIFT             5
+#define MT6315_PMIC_RG_VBUCK4_FUGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_FUGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK4_FUGON_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK4_FLGON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON31
+#define MT6315_PMIC_RG_VBUCK4_FLGON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK4_FLGON_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK4_RAMP_AC_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON32
+#define MT6315_PMIC_RG_VBUCK4_RAMP_AC_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK4_RAMP_AC_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK4_URT_EN_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON32
+#define MT6315_PMIC_RG_VBUCK4_URT_EN_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK4_URT_EN_SHIFT                  2
+#define MT6315_PMIC_RG_VBUCK4_RETENTION_EN_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON32
+#define MT6315_PMIC_RG_VBUCK4_RETENTION_EN_MASK             0x1
+#define MT6315_PMIC_RG_VBUCK4_RETENTION_EN_SHIFT            3
+#define MT6315_PMIC_RG_VBUCK4_SONIC_EN_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON32
+#define MT6315_PMIC_RG_VBUCK4_SONIC_EN_MASK                 0x1
+#define MT6315_PMIC_RG_VBUCK4_SONIC_EN_SHIFT                4
+#define MT6315_PMIC_RG_VBUCK4_GROUNDSEL_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON32
+#define MT6315_PMIC_RG_VBUCK4_GROUNDSEL_MASK                0x1
+#define MT6315_PMIC_RG_VBUCK4_GROUNDSEL_SHIFT               5
+#define MT6315_PMIC_RG_VBUCK4_DLC_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON32
+#define MT6315_PMIC_RG_VBUCK4_DLC_MASK                      0x3
+#define MT6315_PMIC_RG_VBUCK4_DLC_SHIFT                     6
+#define MT6315_PMIC_RG_VBUCK4_RCB_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON33
+#define MT6315_PMIC_RG_VBUCK4_RCB_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK4_RCB_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK4_UG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON33
+#define MT6315_PMIC_RG_VBUCK4_UG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK4_UG_SR_SHIFT                   3
+#define MT6315_PMIC_RG_VBUCK4_LG_SR_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON33
+#define MT6315_PMIC_RG_VBUCK4_LG_SR_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK4_LG_SR_SHIFT                   5
+#define MT6315_PMIC_RG_VBUCK4_ECOT_EN_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON33
+#define MT6315_PMIC_RG_VBUCK4_ECOT_EN_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK4_ECOT_EN_SHIFT                 7
+#define MT6315_PMIC_RG_VBUCK4_OCP_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON34
+#define MT6315_PMIC_RG_VBUCK4_OCP_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK4_OCP_SHIFT                     0
+#define MT6315_PMIC_RG_VBUCK4_OCN_ADDR                      \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON34
+#define MT6315_PMIC_RG_VBUCK4_OCN_MASK                      0x7
+#define MT6315_PMIC_RG_VBUCK4_OCN_SHIFT                     3
+#define MT6315_PMIC_RG_VBUCK4_DUMMY_LOAD_EN_ADDR            \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON34
+#define MT6315_PMIC_RG_VBUCK4_DUMMY_LOAD_EN_MASK            0x1
+#define MT6315_PMIC_RG_VBUCK4_DUMMY_LOAD_EN_SHIFT           6
+#define MT6315_PMIC_RG_VBUCK4_RON_TM_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON34
+#define MT6315_PMIC_RG_VBUCK4_RON_TM_MASK                   0x1
+#define MT6315_PMIC_RG_VBUCK4_RON_TM_SHIFT                  7
+#define MT6315_PMIC_RG_VBUCK4_DIGMON_SEL_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON35
+#define MT6315_PMIC_RG_VBUCK4_DIGMON_SEL_MASK               0x3F
+#define MT6315_PMIC_RG_VBUCK4_DIGMON_SEL_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK4_OC_STATUS_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON36
+#define MT6315_PMIC_RGS_VBUCK4_OC_STATUS_MASK               0x1
+#define MT6315_PMIC_RGS_VBUCK4_OC_STATUS_SHIFT              0
+#define MT6315_PMIC_RGS_VBUCK4_DIG_MON_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON36
+#define MT6315_PMIC_RGS_VBUCK4_DIG_MON_MASK                 0x1
+#define MT6315_PMIC_RGS_VBUCK4_DIG_MON_SHIFT                1
+#define MT6315_PMIC_RG_VBUCK4_UG_ONSR_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON36
+#define MT6315_PMIC_RG_VBUCK4_UG_ONSR_MASK                  0x3
+#define MT6315_PMIC_RG_VBUCK4_UG_ONSR_SHIFT                 2
+#define MT6315_PMIC_RG_VBUCK4_LXRON_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON36
+#define MT6315_PMIC_RG_VBUCK4_LXRON_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK4_LXRON_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK4_RSVH_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON37
+#define MT6315_PMIC_RG_VBUCK4_RSVH_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK4_RSVH_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK4_RSVL_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON38
+#define MT6315_PMIC_RG_VBUCK4_RSVL_MASK                     0xFF
+#define MT6315_PMIC_RG_VBUCK4_RSVL_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK4_TM_ADDR                       \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON39
+#define MT6315_PMIC_RG_VBUCK4_TM_MASK                       0xF
+#define MT6315_PMIC_RG_VBUCK4_TM_SHIFT                      0
+#define MT6315_PMIC_RG_VBUCK4_TM_KEY_ADDR                   \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON39
+#define MT6315_PMIC_RG_VBUCK4_TM_KEY_MASK                   0x3
+#define MT6315_PMIC_RG_VBUCK4_TM_KEY_SHIFT                  4
+#define MT6315_PMIC_RG_VBUCK1234_TMDL_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RG_VBUCK1234_TMDL_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK1234_TMDL_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK1234_SR_VBAT_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RG_VBUCK1234_SR_VBAT_MASK               0x1
+#define MT6315_PMIC_RG_VBUCK1234_SR_VBAT_SHIFT              1
+#define MT6315_PMIC_RG_4PH_CONFIG_LAT_RSVH_ADDR             \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RG_4PH_CONFIG_LAT_RSVH_MASK             0x1
+#define MT6315_PMIC_RG_4PH_CONFIG_LAT_RSVH_SHIFT            2
+#define MT6315_PMIC_RG_4PH_RECONFIG_RSVH_ADDR               \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RG_4PH_RECONFIG_RSVH_MASK               0x1
+#define MT6315_PMIC_RG_4PH_RECONFIG_RSVH_SHIFT              3
+#define MT6315_PMIC_RG_4PH_RECONFIG_EN_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RG_4PH_RECONFIG_EN_MASK                 0x1
+#define MT6315_PMIC_RG_4PH_RECONFIG_EN_SHIFT                4
+#define MT6315_PMIC_RGS_4PH1_VBUCK1_DIGCFG_EN_ADDR          \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RGS_4PH1_VBUCK1_DIGCFG_EN_MASK          0x1
+#define MT6315_PMIC_RGS_4PH1_VBUCK1_DIGCFG_EN_SHIFT         5
+#define MT6315_PMIC_RGS_4PH2_VBUCK2_DIGCFG_EN_ADDR          \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RGS_4PH2_VBUCK2_DIGCFG_EN_MASK          0x1
+#define MT6315_PMIC_RGS_4PH2_VBUCK2_DIGCFG_EN_SHIFT         6
+#define MT6315_PMIC_RGS_4PH3_VBUCK3_DIGCFG_EN_ADDR          \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON40
+#define MT6315_PMIC_RGS_4PH3_VBUCK3_DIGCFG_EN_MASK          0x1
+#define MT6315_PMIC_RGS_4PH3_VBUCK3_DIGCFG_EN_SHIFT         7
+#define MT6315_PMIC_RGS_4PH4_VBUCK4_DIGCFG_EN_ADDR          \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON41
+#define MT6315_PMIC_RGS_4PH4_VBUCK4_DIGCFG_EN_MASK          0x1
+#define MT6315_PMIC_RGS_4PH4_VBUCK4_DIGCFG_EN_SHIFT         0
+#define MT6315_PMIC_RG_VBUCK1_FCCM_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON42
+#define MT6315_PMIC_RG_VBUCK1_FCCM_MASK                     0x1
+#define MT6315_PMIC_RG_VBUCK1_FCCM_SHIFT                    0
+#define MT6315_PMIC_RG_VBUCK2_FCCM_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON42
+#define MT6315_PMIC_RG_VBUCK2_FCCM_MASK                     0x1
+#define MT6315_PMIC_RG_VBUCK2_FCCM_SHIFT                    1
+#define MT6315_PMIC_RG_VBUCK3_FCCM_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON42
+#define MT6315_PMIC_RG_VBUCK3_FCCM_MASK                     0x1
+#define MT6315_PMIC_RG_VBUCK3_FCCM_SHIFT                    2
+#define MT6315_PMIC_RG_VBUCK4_FCCM_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ANA_CON42
+#define MT6315_PMIC_RG_VBUCK4_FCCM_MASK                     0x1
+#define MT6315_PMIC_RG_VBUCK4_FCCM_SHIFT                    3
+#define MT6315_PMIC_BUCK_ANA0_ELR_LEN_ADDR                  \
+	MT6315_BUCK_ANA0_ELR_NUM
+#define MT6315_PMIC_BUCK_ANA0_ELR_LEN_MASK                  0xFF
+#define MT6315_PMIC_BUCK_ANA0_ELR_LEN_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK1_ZC_TRIM_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_0
+#define MT6315_PMIC_RG_VBUCK1_ZC_TRIM_MASK                  0x3F
+#define MT6315_PMIC_RG_VBUCK1_ZC_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK1_CCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_0
+#define MT6315_PMIC_RG_VBUCK1_CCOMP_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK1_CCOMP_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK1_NLIM_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_1
+#define MT6315_PMIC_RG_VBUCK1_NLIM_TRIM_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK1_NLIM_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK1_RCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_1
+#define MT6315_PMIC_RG_VBUCK1_RCOMP_MASK                    0xF
+#define MT6315_PMIC_RG_VBUCK1_RCOMP_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK1_TON_TRIM_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_2
+#define MT6315_PMIC_RG_VBUCK1_TON_TRIM_MASK                 0x7F
+#define MT6315_PMIC_RG_VBUCK1_TON_TRIM_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK1_FB_D2_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_2
+#define MT6315_PMIC_RG_VBUCK1_FB_D2_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK1_FB_D2_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK1_PFM_PEAK_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_3
+#define MT6315_PMIC_RG_VBUCK1_PFM_PEAK_MASK                 0xF
+#define MT6315_PMIC_RG_VBUCK1_PFM_PEAK_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK1_SONIC_PFM_PEAK_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_3
+#define MT6315_PMIC_RG_VBUCK1_SONIC_PFM_PEAK_MASK           0xF
+#define MT6315_PMIC_RG_VBUCK1_SONIC_PFM_PEAK_SHIFT          4
+#define MT6315_PMIC_RG_VBUCK1_ECOT_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_4
+#define MT6315_PMIC_RG_VBUCK1_ECOT_TRIM_MASK                0x7
+#define MT6315_PMIC_RG_VBUCK1_ECOT_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK1_CSNSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_4
+#define MT6315_PMIC_RG_VBUCK1_CSNSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK1_CSNSLP_TRIM_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK1_CSPSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_5
+#define MT6315_PMIC_RG_VBUCK1_CSPSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK1_CSPSLP_TRIM_SHIFT             0
+#define MT6315_PMIC_RG_VBUCK1_RAMP_SLP_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_5
+#define MT6315_PMIC_RG_VBUCK1_RAMP_SLP_MASK                 0x7
+#define MT6315_PMIC_RG_VBUCK1_RAMP_SLP_SHIFT                5
+#define MT6315_PMIC_RG_VBUCK1_DRIVER_SR_TRIM_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_6
+#define MT6315_PMIC_RG_VBUCK1_DRIVER_SR_TRIM_MASK           0x7
+#define MT6315_PMIC_RG_VBUCK1_DRIVER_SR_TRIM_SHIFT          0
+#define MT6315_PMIC_RG_VBUCK1_OC_D2P5_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_6
+#define MT6315_PMIC_RG_VBUCK1_OC_D2P5_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK1_OC_D2P5_SHIFT                 3
+#define MT6315_PMIC_RG_VBUCK1_RSV_EFUSE_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_6
+#define MT6315_PMIC_RG_VBUCK1_RSV_EFUSE_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK1_RSV_EFUSE_SHIFT               4
+#define MT6315_PMIC_RG_VBUCK2_ZC_TRIM_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_7
+#define MT6315_PMIC_RG_VBUCK2_ZC_TRIM_MASK                  0x3F
+#define MT6315_PMIC_RG_VBUCK2_ZC_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK2_CCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_7
+#define MT6315_PMIC_RG_VBUCK2_CCOMP_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK2_CCOMP_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK2_NLIM_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_8
+#define MT6315_PMIC_RG_VBUCK2_NLIM_TRIM_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK2_NLIM_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK2_RCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_8
+#define MT6315_PMIC_RG_VBUCK2_RCOMP_MASK                    0xF
+#define MT6315_PMIC_RG_VBUCK2_RCOMP_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK2_TON_TRIM_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_9
+#define MT6315_PMIC_RG_VBUCK2_TON_TRIM_MASK                 0x7F
+#define MT6315_PMIC_RG_VBUCK2_TON_TRIM_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK2_FB_D2_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_9
+#define MT6315_PMIC_RG_VBUCK2_FB_D2_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK2_FB_D2_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK2_PFM_PEAK_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_10
+#define MT6315_PMIC_RG_VBUCK2_PFM_PEAK_MASK                 0xF
+#define MT6315_PMIC_RG_VBUCK2_PFM_PEAK_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK2_SONIC_PFM_PEAK_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_10
+#define MT6315_PMIC_RG_VBUCK2_SONIC_PFM_PEAK_MASK           0xF
+#define MT6315_PMIC_RG_VBUCK2_SONIC_PFM_PEAK_SHIFT          4
+#define MT6315_PMIC_RG_VBUCK2_ECOT_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_11
+#define MT6315_PMIC_RG_VBUCK2_ECOT_TRIM_MASK                0x7
+#define MT6315_PMIC_RG_VBUCK2_ECOT_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK2_CSNSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_11
+#define MT6315_PMIC_RG_VBUCK2_CSNSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK2_CSNSLP_TRIM_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK2_CSPSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_12
+#define MT6315_PMIC_RG_VBUCK2_CSPSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK2_CSPSLP_TRIM_SHIFT             0
+#define MT6315_PMIC_RG_VBUCK2_RAMP_SLP_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_12
+#define MT6315_PMIC_RG_VBUCK2_RAMP_SLP_MASK                 0x7
+#define MT6315_PMIC_RG_VBUCK2_RAMP_SLP_SHIFT                5
+#define MT6315_PMIC_RG_VBUCK2_DRIVER_SR_TRIM_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_13
+#define MT6315_PMIC_RG_VBUCK2_DRIVER_SR_TRIM_MASK           0x7
+#define MT6315_PMIC_RG_VBUCK2_DRIVER_SR_TRIM_SHIFT          0
+#define MT6315_PMIC_RG_VBUCK2_OC_D2P5_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_13
+#define MT6315_PMIC_RG_VBUCK2_OC_D2P5_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK2_OC_D2P5_SHIFT                 3
+#define MT6315_PMIC_RG_VBUCK2_RSV_EFUSE_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_13
+#define MT6315_PMIC_RG_VBUCK2_RSV_EFUSE_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK2_RSV_EFUSE_SHIFT               4
+#define MT6315_PMIC_RG_VBUCK3_ZC_TRIM_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_14
+#define MT6315_PMIC_RG_VBUCK3_ZC_TRIM_MASK                  0x3F
+#define MT6315_PMIC_RG_VBUCK3_ZC_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK3_CCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_14
+#define MT6315_PMIC_RG_VBUCK3_CCOMP_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK3_CCOMP_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK3_NLIM_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_15
+#define MT6315_PMIC_RG_VBUCK3_NLIM_TRIM_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK3_NLIM_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK3_RCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_15
+#define MT6315_PMIC_RG_VBUCK3_RCOMP_MASK                    0xF
+#define MT6315_PMIC_RG_VBUCK3_RCOMP_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK3_TON_TRIM_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_16
+#define MT6315_PMIC_RG_VBUCK3_TON_TRIM_MASK                 0x7F
+#define MT6315_PMIC_RG_VBUCK3_TON_TRIM_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK3_FB_D2_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_16
+#define MT6315_PMIC_RG_VBUCK3_FB_D2_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK3_FB_D2_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK3_PFM_PEAK_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_17
+#define MT6315_PMIC_RG_VBUCK3_PFM_PEAK_MASK                 0xF
+#define MT6315_PMIC_RG_VBUCK3_PFM_PEAK_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK3_SONIC_PFM_PEAK_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_17
+#define MT6315_PMIC_RG_VBUCK3_SONIC_PFM_PEAK_MASK           0xF
+#define MT6315_PMIC_RG_VBUCK3_SONIC_PFM_PEAK_SHIFT          4
+#define MT6315_PMIC_RG_VBUCK3_ECOT_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_18
+#define MT6315_PMIC_RG_VBUCK3_ECOT_TRIM_MASK                0x7
+#define MT6315_PMIC_RG_VBUCK3_ECOT_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK3_CSNSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_18
+#define MT6315_PMIC_RG_VBUCK3_CSNSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK3_CSNSLP_TRIM_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK3_CSPSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_19
+#define MT6315_PMIC_RG_VBUCK3_CSPSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK3_CSPSLP_TRIM_SHIFT             0
+#define MT6315_PMIC_RG_VBUCK3_RAMP_SLP_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_19
+#define MT6315_PMIC_RG_VBUCK3_RAMP_SLP_MASK                 0x7
+#define MT6315_PMIC_RG_VBUCK3_RAMP_SLP_SHIFT                5
+#define MT6315_PMIC_RG_VBUCK3_DRIVER_SR_TRIM_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_20
+#define MT6315_PMIC_RG_VBUCK3_DRIVER_SR_TRIM_MASK           0x7
+#define MT6315_PMIC_RG_VBUCK3_DRIVER_SR_TRIM_SHIFT          0
+#define MT6315_PMIC_RG_VBUCK3_OC_D2P5_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_20
+#define MT6315_PMIC_RG_VBUCK3_OC_D2P5_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK3_OC_D2P5_SHIFT                 3
+#define MT6315_PMIC_RG_VBUCK3_RSV_EFUSE_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_20
+#define MT6315_PMIC_RG_VBUCK3_RSV_EFUSE_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK3_RSV_EFUSE_SHIFT               4
+#define MT6315_PMIC_RG_VBUCK4_ZC_TRIM_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_21
+#define MT6315_PMIC_RG_VBUCK4_ZC_TRIM_MASK                  0x3F
+#define MT6315_PMIC_RG_VBUCK4_ZC_TRIM_SHIFT                 0
+#define MT6315_PMIC_RG_VBUCK4_CCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_21
+#define MT6315_PMIC_RG_VBUCK4_CCOMP_MASK                    0x3
+#define MT6315_PMIC_RG_VBUCK4_CCOMP_SHIFT                   6
+#define MT6315_PMIC_RG_VBUCK4_NLIM_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_22
+#define MT6315_PMIC_RG_VBUCK4_NLIM_TRIM_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK4_NLIM_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK4_RCOMP_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_22
+#define MT6315_PMIC_RG_VBUCK4_RCOMP_MASK                    0xF
+#define MT6315_PMIC_RG_VBUCK4_RCOMP_SHIFT                   4
+#define MT6315_PMIC_RG_VBUCK4_TON_TRIM_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_23
+#define MT6315_PMIC_RG_VBUCK4_TON_TRIM_MASK                 0x7F
+#define MT6315_PMIC_RG_VBUCK4_TON_TRIM_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK4_FB_D2_ADDR                    \
+	MT6315_BUCK_TOP_4PHASE_ELR_23
+#define MT6315_PMIC_RG_VBUCK4_FB_D2_MASK                    0x1
+#define MT6315_PMIC_RG_VBUCK4_FB_D2_SHIFT                   7
+#define MT6315_PMIC_RG_VBUCK4_PFM_PEAK_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_24
+#define MT6315_PMIC_RG_VBUCK4_PFM_PEAK_MASK                 0xF
+#define MT6315_PMIC_RG_VBUCK4_PFM_PEAK_SHIFT                0
+#define MT6315_PMIC_RG_VBUCK4_SONIC_PFM_PEAK_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_24
+#define MT6315_PMIC_RG_VBUCK4_SONIC_PFM_PEAK_MASK           0xF
+#define MT6315_PMIC_RG_VBUCK4_SONIC_PFM_PEAK_SHIFT          4
+#define MT6315_PMIC_RG_VBUCK4_ECOT_TRIM_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_25
+#define MT6315_PMIC_RG_VBUCK4_ECOT_TRIM_MASK                0x7
+#define MT6315_PMIC_RG_VBUCK4_ECOT_TRIM_SHIFT               0
+#define MT6315_PMIC_RG_VBUCK4_CSNSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_25
+#define MT6315_PMIC_RG_VBUCK4_CSNSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK4_CSNSLP_TRIM_SHIFT             3
+#define MT6315_PMIC_RG_VBUCK4_CSPSLP_TRIM_ADDR              \
+	MT6315_BUCK_TOP_4PHASE_ELR_26
+#define MT6315_PMIC_RG_VBUCK4_CSPSLP_TRIM_MASK              0x1F
+#define MT6315_PMIC_RG_VBUCK4_CSPSLP_TRIM_SHIFT             0
+#define MT6315_PMIC_RG_VBUCK4_RAMP_SLP_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_26
+#define MT6315_PMIC_RG_VBUCK4_RAMP_SLP_MASK                 0x7
+#define MT6315_PMIC_RG_VBUCK4_RAMP_SLP_SHIFT                5
+#define MT6315_PMIC_RG_VBUCK4_DRIVER_SR_TRIM_ADDR           \
+	MT6315_BUCK_TOP_4PHASE_ELR_27
+#define MT6315_PMIC_RG_VBUCK4_DRIVER_SR_TRIM_MASK           0x7
+#define MT6315_PMIC_RG_VBUCK4_DRIVER_SR_TRIM_SHIFT          0
+#define MT6315_PMIC_RG_VBUCK4_OC_D2P5_ADDR                  \
+	MT6315_BUCK_TOP_4PHASE_ELR_27
+#define MT6315_PMIC_RG_VBUCK4_OC_D2P5_MASK                  0x1
+#define MT6315_PMIC_RG_VBUCK4_OC_D2P5_SHIFT                 3
+#define MT6315_PMIC_RG_VBUCK4_RSV_EFUSE_ADDR                \
+	MT6315_BUCK_TOP_4PHASE_ELR_27
+#define MT6315_PMIC_RG_VBUCK4_RSV_EFUSE_MASK                0xF
+#define MT6315_PMIC_RG_VBUCK4_RSV_EFUSE_SHIFT               4
+#define MT6315_PMIC_RG_4PH_CONFIG1_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ELR_28
+#define MT6315_PMIC_RG_4PH_CONFIG1_MASK                     0x1
+#define MT6315_PMIC_RG_4PH_CONFIG1_SHIFT                    0
+#define MT6315_PMIC_RG_4PH_CONFIG2_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ELR_28
+#define MT6315_PMIC_RG_4PH_CONFIG2_MASK                     0x1
+#define MT6315_PMIC_RG_4PH_CONFIG2_SHIFT                    1
+#define MT6315_PMIC_RG_4PH_CONFIG3_ADDR                     \
+	MT6315_BUCK_TOP_4PHASE_ELR_28
+#define MT6315_PMIC_RG_4PH_CONFIG3_MASK                     0x1
+#define MT6315_PMIC_RG_4PH_CONFIG3_SHIFT                    2
+#define MT6315_PMIC_RG_4PH_23PHIN_TRIM_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_28
+#define MT6315_PMIC_RG_4PH_23PHIN_TRIM_MASK                 0xF
+#define MT6315_PMIC_RG_4PH_23PHIN_TRIM_SHIFT                3
+#define MT6315_PMIC_RG_4PH_34PHIN_TRIM_ADDR                 \
+	MT6315_BUCK_TOP_4PHASE_ELR_29
+#define MT6315_PMIC_RG_4PH_34PHIN_TRIM_MASK                 0xF
+#define MT6315_PMIC_RG_4PH_34PHIN_TRIM_SHIFT                0
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
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+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#endif		/* _MT_PMIC_UPMU_HW_MT6315_H_ */

diff --git a/mcu/driver/devdrv/spmi/inc/pmif_sw.h b/mcu/driver/devdrv/spmi/inc/pmif_sw.h
new file mode 100644
index 0000000..033e3c0
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/inc/pmif_sw.h

@@ -0,0 +1,321 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __PMIF_SW_H__
+#define __PMIF_SW_H__
+
+#define PMIF_PRELOADER		0
+#define PMIF_LK			0
+#define PMIF_KERNEL		0
+#define PMIF_CTP		0
+#define PMIF_MD			1
+
+/* SW ENV define */
+#define PMIF_DEBUG		1
+#define PMIF_MATCH_SUPPORT	0
+
+/* Read/write byte limitation, by project */
+#define PMIF_BYTECNT_MAX	1
+
+/* For BringUp. if BringUp doesn't had PMIC, need open this */
+#if (PMIF_PRELOADER)
+	#if CFG_FPGA_PLATFORM
+		#define PMIF_NO_PMIC	1
+	#else
+		#define PMIF_NO_PMIC	0
+		#define PMIF_TIMEOUT	0
+	#endif
+	#define PMIF_NORMAL_BOOT        1
+#elif (PMIF_LK)
+	#if defined(MACH_FPGA)
+		#define PMIF_NO_PMIC	1
+	#else
+		#define PMIF_NO_PMIC	0
+		#define PMIF_TIMEOUT	0
+	#endif
+	#define PMIF_NORMAL_BOOT        1
+#elif (PMIF_CTP)
+	#if defined(CONFIG_MTK_FPGA)
+		#define PMIF_NO_PMIC	1
+	#else
+		#define PMIF_NO_PMIC	0
+		#define PMIF_TIMEOUT	0
+	#endif
+	#define PMIF_NORMAL_BOOT        0
+#elif (PMIF_MD)
+	#ifdef __FPGA__
+		#define PMIF_NO_PMIC	1
+	#else
+		#define PMIF_NO_PMIC	0
+		#define PMIF_TIMEOUT	0
+	#endif
+	#define PMIF_NORMAL_BOOT        1
+#else
+	#define PMIF_NO_PMIC		1
+	#define PMIF_TIMEOUT		0
+#endif
+
+/* SW ENV header define */
+#if (PMIF_PRELOADER)
+	#include <sync_write.h>
+	#include <typedefs.h>
+	#include <gpio.h>
+	#include <mt6885.h>
+	#include <pll.h>
+	#include <pal_log.h>
+	#define INIT_CRITICAL()
+	#define ENTER_CRITICAL()
+	#define EXIT_CRITICAL()
+#elif (PMIF_LK)
+	#include <debug.h>
+	#include <platform/mt_typedefs.h>
+	#include <platform/mt_reg_base.h>
+	#include <platform/mt_gpt.h>
+	#include <platform/mt_irq.h>
+	#include <sys/types.h>
+	#include <platform/sync_write.h>
+	#include <platform/upmu_hw.h>
+	#include <pal_log.h>
+	#include <kernel/thread.h>
+	#define INIT_CRITICAL()
+	#define ENTER_CRITICAL() enter_critical_section();
+	#define EXIT_CRITICAL() exit_critical_section();
+#elif (PMIF_KERNEL)
+#elif (PMIF_CTP)
+	#include <sync_write.h>
+	#include <typedefs.h>
+	#include <reg_base.H>
+	#include <driver_api.h>
+	#define INIT_CRITICAL()
+	#define ENTER_CRITICAL()
+	#define EXIT_CRITICAL()
+#elif (PMIF_MD)
+	#include "reg_base.h"
+	#include "drv_comm.h"
+	#include "init.h"
+	#include "dcl.h"
+	#include "kal_public_api.h"
+	#include "kal_public_defs.h"
+	#include "kal_hrt_api.h"
+	#include "us_timer.h"
+	#include "event_info_utility.h" // for MODEM_WARNING_MESSAGE
+	#define INIT_CRITICAL()
+	#define ENTER_CRITICAL()
+	#define EXIT_CRITICAL()
+#else
+	### Compile error, check SW ENV define
+#endif
+
+/* DEBUG MARCO */
+#define PMIFTAG		"[PMIF] "
+#if (PMIF_PRELOADER)
+	#if PMIF_DEBUG
+		#define PMIF_CRI(fmt, arg...) pal_log_err(PMIFTAG fmt, ##arg)
+		#define PMIF_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define PMIF_ERR(fmt, arg...) \
+			pal_log_err(PMIFTAG "%d: "fmt, __LINE__, ##arg)
+		#define PMIF_WARN(fmt, arg...) pal_log_warn(PMIFTAG fmt, ##arg)
+		#define PMIF_INFO(fmt, arg...) pal_log_info(PMIFTAG fmt, ##arg)
+		#define PMIF_DBG(fmt, arg...) pal_log_debug(PMIFTAG fmt, ##arg)
+	#else
+		#define PMIF_CRI(fmt, arg...) pal_log_err(PMIFTAG fmt, ##arg)
+		#define PMIF_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define PMIF_ERR(fmt, arg...) pal_log_err(PMIFTAG fmt, ##arg)
+		#define PMIF_WARN(fmt, arg...) pal_log_info(PMIFTAG fmt, ##arg)
+		#define PMIF_INFO(fmt, arg...) do { } while(0)
+		#define PMIF_DBG(fmt, arg...) do { } while(0)
+	#endif
+#elif (PMIF_LK)
+	#if PMIF_DEBUG
+		#define PMIF_CRI(fmt, arg...) pal_log_err(PMIFTAG fmt, ##arg)
+		#define PMIF_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define PMIF_ERR(fmt, arg...) \
+			pal_log_err(PMIFTAG "%d: "fmt, __LINE__, ##arg)
+		#define PMIF_WARN(fmt, arg...) pal_log_warn(PMIFTAG fmt, ##arg)
+		#define PMIF_INFO(fmt, arg...) pal_log_info(PMIFTAG fmt, ##arg)
+		#define PMIF_DBG(fmt, arg...) pal_log_debug(PMIFTAG fmt, ##arg)
+	#else
+		#define PMIF_CRI(fmt, arg...) pal_log_err(PMIFTAG fmt, ##arg)
+		#define PMIF_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define PMIF_ERR(fmt, arg...) pal_log_err(PMIFTAG fmt, ##arg)
+		#define PMIF_WARN(fmt, arg...) pal_log_info(PMIFTAG fmt, ##arg)
+		#define PMIF_INFO(fmt, arg...) do { } while(0)
+		#define PMIF_DBG(fmt, arg...) do { } while(0)
+	#endif
+#elif (PMIF_KERNEL)
+#elif (PMIF_CTP)
+	#ifdef PMIF_DEBUG
+		#define PMIF_CRI(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#define PMIF_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+		#define PMIF_ERR(fmt, arg...) \
+			dbg_print(PMIFTAG "%d: "fmt, __LINE__, ##arg)
+		#define PMIF_WARN(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#define PMIF_INFO(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#define PMIF_DBG(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+	#else
+		#define PMIF_CRI(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#define PMIF_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+		#define PMIF_ERR(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#define PMIF_WARN(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#define PMIF_INFO(fmt, arg...) do { } while(0)
+		#define PMIF_DBG(fmt, arg...) do { } while(0)
+	#endif /* end of #ifdef PMIF_DEBUG */
+#elif (PMIF_MD)
+	#if defined(DRV_DEBUG) || defined(ATEST_DRV_ENABLE)
+		#ifdef PMIF_DEBUG
+			#define PMIF_CRI(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+			#define PMIF_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+			#define PMIF_ERR(fmt, arg...) \
+				dbg_print(PMIFTAG "%d: "fmt, __LINE__, ##arg)
+			#define PMIF_WARN(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+			#define PMIF_INFO(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+			#define PMIF_DBG(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+		#else
+			#define PMIF_CRI(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+			#define PMIF_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+			#define PMIF_ERR(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+			#define PMIF_WARN(fmt, arg...) dbg_print(PMIFTAG fmt, ##arg)
+			#define PMIF_INFO(fmt, arg...) do { } while(0)
+			#define PMIF_DBG(fmt, arg...) do { } while(0)
+		#endif /* end of #ifdef PMIF_DEBUG */
+	#else
+		#define PMIF_CRI(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define PMIF_CRIL(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define PMIF_ERR(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define PMIF_WARN(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define PMIF_INFO(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define PMIF_DBG(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+	#endif
+#else
+	### Compile error, check SW ENV define
+#endif
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE		(0x00)
+#define SWINF_FSM_REQ		(0x02)
+#define SWINF_FSM_WFDLE		(0x04)
+#define SWINF_FSM_WFVLDCLR	(0x06)
+#define SWINF_INIT_DONE		(0x01)
+/* indicate which number SW channel start, by project */
+#if  defined(CHIP10992)
+#define PMIF_SWINF_0_CHAN_NO	6
+#define PMIF_SWINF_0_CHAN_NO_P	6
+#else
+#define PMIF_SWINF_0_CHAN_NO	4
+#define PMIF_SWINF_0_CHAN_NO_P	1
+#endif
+/* MD: 0, security domain: 1, AP: 2 */
+#if  defined(CHIP10992)
+#define PMIF_AP_SWINF_NO	0
+#define PMIF_AP_SWINF_NO_P	0
+#else
+#define PMIF_AP_SWINF_NO	0
+#define PMIF_AP_SWINF_NO_P	3
+#endif
+/* 0: SPI, 1: SPMI */
+#define PMIF_PMIFID		1
+#define PMIF_PMIFID_2		2
+
+#ifndef EIO
+#define	EIO 5		/* I/O error */
+#endif
+#ifndef EBUSY
+#define EBUSY	16  /* Device or resource busy */
+#endif
+#ifndef ENODEV
+#define	ENODEV	19	/* No such device */
+#endif
+#ifndef EINVAL
+#define EINVAL	22  /* Invalid argument */
+#endif
+#ifndef EOPNOTSUPP
+#define EOPNOTSUPP	95  /* Operation not supported on transport endpoint */
+#endif
+#ifndef ETIMEDOUT
+#define ETIMEDOUT	110 /* Connection timed out */
+#endif
+
+#ifndef BASE_INFRA_AO_CONFIG
+#define BASE_INFRA_AO_CONFIG		(0xC0001000)
+#endif
+#ifndef INFRACFG_AO_BASE
+#define INFRACFG_AO_BASE		BASE_INFRA_AO_CONFIG
+#endif
+#ifndef BASE_INFRA_AO_TOPCKGEN
+#define BASE_INFRA_AO_TOPCKGEN		(0xC0000000)
+#endif
+#ifndef TOPCKGEN_BASE
+#define TOPCKGEN_BASE			BASE_INFRA_AO_TOPCKGEN
+#endif
+#ifndef TOPRGU_BASE
+#define TOPRGU_BASE			(0xC0007000)
+#endif
+/* macro for spmi clock config */
+#ifndef CLK_CFG_UPDATE1
+#define CLK_CFG_UPDATE1			(TOPCKGEN_BASE+0x008)
+#endif
+#ifndef CLK_CFG_UPDATE2
+#define CLK_CFG_UPDATE2			(TOPCKGEN_BASE+0x00c)
+#endif
+#ifndef CLK_CFG_8_SET
+#define CLK_CFG_8_SET			(TOPCKGEN_BASE+0x094)
+#endif
+#ifndef CLK_CFG_8_CLR
+#define CLK_CFG_8_CLR			(TOPCKGEN_BASE+0x098)
+#endif
+#ifndef CLK_CFG_16_CLR
+#define CLK_CFG_16_CLR			(TOPCKGEN_BASE+0x118)
+#endif
+#ifndef MODULE_SW_CG_0_SET
+#define MODULE_SW_CG_0_SET		(INFRACFG_AO_BASE+0x080)
+#endif
+#ifndef MODULE_SW_CG_0_CLR
+#define MODULE_SW_CG_0_CLR		(INFRACFG_AO_BASE+0x084)
+#endif
+#ifndef MODULE_CLK_SEL
+#define MODULE_CLK_SEL			(INFRACFG_AO_BASE+0x098)
+#endif
+#ifndef MODULE_SW_CG_2_SET
+#define MODULE_SW_CG_2_SET		(INFRACFG_AO_BASE+0x0A4)
+#endif
+#ifndef MODULE_SW_CG_2_CLR
+#define MODULE_SW_CG_2_CLR		(INFRACFG_AO_BASE+0x0A8)
+#endif
+#define INFRA_GLOBALCON_RST2_SET	(INFRACFG_AO_BASE+0x140)
+#define INFRA_GLOBALCON_RST2_CLR	(INFRACFG_AO_BASE+0x144)
+
+extern int spmi_pmif_dbg_init(struct pmif *arb);
+#endif /*__PMIF_SW_H__*/

diff --git a/mcu/driver/devdrv/spmi/inc/spmi_sw.h b/mcu/driver/devdrv/spmi/inc/spmi_sw.h
new file mode 100644
index 0000000..a8cce0a
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/inc/spmi_sw.h

@@ -0,0 +1,316 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __SPMI_SW_H__
+#define __SPMI_SW_H__
+
+#define SPMI_PRELOADER		0
+#define SPMI_LK			0
+#define SPMI_KERNEL		0
+#define SPMI_CTP		0
+#define SPMI_MD			1
+
+/* SW ENV define */
+#define SPMI_DEBUG		0
+#define SPMI_EXTADDR_SUPPORT	0
+#define SPMI_MONITOR_SUPPORT	0
+#define SPMI_RCS_SUPPORT	0
+/* for evb or fpga used */
+#define MT63xx_EVB		1
+
+/* For BringUp. if BringUp doesn't had PMIC, need open this */
+#if (SPMI_PRELOADER)
+	#if CFG_FPGA_PLATFORM
+		#define SPMI_NO_PMIC	1
+	#else
+		#define SPMI_NO_PMIC	0
+		#define SPMI_TIMEOUT	0
+	#endif
+#elif (SPMI_LK)
+	#if defined(MACH_FPGA)
+		#define SPMI_NO_PMIC	1
+	#else
+		#define SPMI_NO_PMIC	0
+		#define SPMI_TIMEOUT	0
+	#endif
+#elif (SPMI_CTP)
+	#if defined(CONFIG_MTK_FPGA)
+		#define SPMI_NO_PMIC	1
+	#else
+		#define SPMI_NO_PMIC	0
+		#define SPMI_TIMEOUT	0
+	#endif
+#elif (SPMI_MD)
+	#ifdef __FPGA__
+		#define SPMI_NO_PMIC	1
+	#else
+		#define SPMI_NO_PMIC	0
+		#define SPMI_TIMEOUT	0
+	#endif
+#else
+	#define SPMI_NO_PMIC		1
+	#define SPMI_TIMEOUT		0
+#endif
+
+/* SW ENV header define */
+#if (SPMI_PRELOADER)
+	#include <sync_write.h>
+	#include <typedefs.h>
+	#include <gpio.h>
+	#include <mt6885.h>
+	#include <pll.h>
+	#include <pal_log.h>
+#elif (SPMI_LK)
+	#include <debug.h>
+	#include <platform/mt_typedefs.h>
+	#include <platform/mt_reg_base.h>
+	#include <platform/mt_gpt.h>
+	#include <platform/mt_irq.h>
+	#include <sys/types.h>
+	#include <platform/sync_write.h>
+	#include <platform/upmu_hw.h>
+	#include <pal_log.h>
+#elif (SPMI_KERNEL)
+#elif (SPMI_CTP)
+	#include <sync_write.h>
+	#include <typedefs.h>
+	#include <reg_base.H>
+	#include <driver_api.h>
+	#include <common.h>
+	#include <kallsyms.h>
+#elif (SPMI_MD)
+	#include "reg_base.h"
+	#include "drv_comm.h"
+	#include "init.h"
+	#include "dcl.h"
+	#include "kal_public_api.h"
+	#include "kal_public_defs.h"
+	#include "us_timer.h"
+	#include "event_info_utility.h" // for MODEM_WARNING_MESSAGE
+#else
+	### Compile error, check SW ENV define
+#endif
+
+/* DEBUG MARCO */
+#define SPMITAG		"[SPMI] "
+#if (SPMI_PRELOADER)
+	#if SPMI_DEBUG
+		#define SPMI_CRI(fmt, arg...) pal_log_err(SPMITAG fmt, ##arg)
+		#define SPMI_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define SPMI_ERR(fmt, arg...) \
+			pal_log_err(SPMITAG "%d: "fmt, __LINE__, ##arg)
+		#define SPMI_WARN(fmt, arg...) pal_log_warn(SPMITAG fmt, ##arg)
+		#define SPMI_INFO(fmt, arg...) pal_log_info(SPMITAG fmt, ##arg)
+		#define SPMI_DBG(fmt, arg...) pal_log_debug(SPMITAG fmt, ##arg)
+	#else
+		#define SPMI_CRI(fmt, arg...) pal_log_err(SPMITAG fmt, ##arg)
+		#define SPMI_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define SPMI_ERR(fmt, arg...) \
+			pal_log_err(SPMITAG "%d: "fmt, __LINE__, ##arg)
+		#define SPMI_WARN(fmt, arg...) pal_log_info(SPMITAG fmt, ##arg)
+		#define SPMI_INFO(fmt, arg...) do { } while(0)
+		#define SPMI_DBG(fmt, arg...) do { } while(0)
+	#endif
+#elif (SPMI_LK)
+	#if SPMI_DEBUG
+		#define SPMI_CRI(fmt, arg...) pal_log_err(SPMITAG fmt, ##arg)
+		#define SPMI_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define SPMI_ERR(fmt, arg...) \
+			pal_log_err(SPMITAG "%d: "fmt, __LINE__, ##arg)
+		#define SPMI_WARN(fmt, arg...) pal_log_warn(SPMITAG fmt, ##arg)
+		#define SPMI_INFO(fmt, arg...) pal_log_info(SPMITAG fmt, ##arg)
+		#define SPMI_DBG(fmt, arg...) pal_log_debug(SPMITAG fmt, ##arg)
+	#else
+		#define SPMI_CRI(fmt, arg...) pal_log_err(SPMITAG fmt, ##arg)
+		#define SPMI_CRIL(fmt, arg...) pal_log_err(fmt, ##arg)
+		#define SPMI_ERR(fmt, arg...) \
+			pal_log_err(SPMITAG "%d: "fmt, __LINE__, ##arg)
+		#define SPMI_WARN(fmt, arg...) pal_log_info(SPMITAG fmt, ##arg)
+		#define SPMI_INFO(fmt, arg...) do { } while(0)
+		#define SPMI_DBG(fmt, arg...) do { } while(0)
+	#endif
+#elif (SPMI_KERNEL)
+#elif (SPMI_CTP)
+	#ifdef SPMI_DEBUG
+		#define SPMI_CRI(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#define SPMI_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+		#define SPMI_ERR(fmt, arg...) \
+			dbg_print(SPMITAG "%d: "fmt, __LINE__, ##arg)
+		#define SPMI_WARN(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#define SPMI_INFO(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#define SPMI_DBG(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+	#else
+		#define SPMI_CRI(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#define SPMI_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+		#define SPMI_ERR(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#define SPMI_WARN(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#define SPMI_INFO(fmt, arg...) do { } while(0)
+		#define SPMI_DBG(fmt, arg...) do { } while(0)
+	#endif /* end of #ifdef SPMI_DEBUG */
+#elif (SPMI_MD)
+	#if defined(DRV_DEBUG) || defined(ATEST_DRV_ENABLE)
+		#ifdef SPMI_DEBUG
+			#define SPMI_CRI(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+			#define SPMI_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+			#define SPMI_ERR(fmt, arg...) \
+				dbg_print(SPMITAG "%d: "fmt, __LINE__, ##arg)
+			#define SPMI_WARN(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+			#define SPMI_INFO(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+			#define SPMI_DBG(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+		#else
+			#define SPMI_CRI(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+			#define SPMI_CRIL(fmt, arg...) dbg_print(fmt, ##arg)
+			#define SPMI_ERR(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+			#define SPMI_WARN(fmt, arg...) dbg_print(SPMITAG fmt, ##arg)
+			#define SPMI_INFO(fmt, arg...) do { } while(0)
+			#define SPMI_DBG(fmt, arg...) do { } while(0)
+		#endif /* end of #ifdef SPMI_DEBUG */
+	#else
+		#define SPMI_CRI(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define SPMI_CRIL(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define SPMI_ERR(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define SPMI_WARN(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define SPMI_INFO(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+		#define SPMI_DBG(string, ...) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_DHL_READER, (char*)string, ##__VA_ARGS__)
+	#endif
+#else
+	### Compile error, check SW ENV define
+#endif
+
+#define DEFAULT_VALUE_READ_TEST		(0x5a)
+#define DEFAULT_VALUE_WRITE_TEST	(0xa5)
+
+#define GET_REC_CMD(x)				(x & 0x00000003)
+#define GET_REC_W(x)				((x>>2) & 0x00000001)
+#define GET_REC_OP_ST_NACK(x)			((x>>3) & 0x00000001)
+#define GET_REC_PMIF_NACK(x)			((x>>4) & 0x00000001)
+#define GET_REC_PMIF_PARITY_ERR(x)		((x>>5) & 0x00000001)
+#define GET_REC_PMIF_BYTE_ERR(x)		((x>>6) & 0x00000001)
+#define GET_REC_PMIF_GRP_RD_ERR(x)		((x>>7) & 0x00000001)
+#define GET_REC_SLVID(x)			((x>>8) & 0x0000000f)
+#define GET_REC_BYTECNT(x)			((x>>12) & 0x0000000f)
+#define GET_REC_ADDR(x)				((x>>16) & 0x0000ffff)
+
+/* macro for spmi clock config */
+#define WDT_SWSYSRST2			(TOPRGU_BASE+0x090)
+#define CLK_CFG_UPDATE2			(TOPCKGEN_BASE+0x00c)
+#define CLK_CFG_16_CLR			(TOPCKGEN_BASE+0x118)
+
+struct cali {
+	unsigned int dly;
+	unsigned int pol;
+};
+
+enum
+{
+	SPMI_CK_NO_DLY = 0,
+	SPMI_CK_DLY_1T
+};
+
+enum
+{
+	SPMI_CK_POL_NEG = 0,
+	SPMI_CK_POL_POS
+};
+
+enum
+{
+	SPMI_OP_ST_BUSY = 1,
+	SPMI_OP_ST_ACK = 0,
+	SPMI_OP_ST_NACK = 1
+};
+
+enum
+{
+	SPMI_RCS_SR_BIT,
+	SPMI_RCS_A_BIT
+};
+
+enum
+{
+	SPMI_RCS_MST_W = 1,
+	SPMI_RCS_SLV_W = 3
+};
+
+enum
+{
+	SPMI_RESET = 0,
+	SPMI_SLEEP,
+	SPMI_SHUTDOWN,
+	SPMI_WAKEUP
+};
+
+enum spmi_regs {
+	SPMI_OP_ST_CTRL,
+	SPMI_GRP_ID_EN,
+	SPMI_OP_ST_STA,
+	SPMI_MST_SAMPL,
+	SPMI_MST_REQ_EN,
+	/* RCS support */
+#if SPMI_RCS_SUPPORT
+	SPMI_RCS_CTRL,
+	SPMI_SLV_3_0_EINT,
+	SPMI_SLV_7_4_EINT,
+	SPMI_SLV_B_8_EINT,
+	SPMI_SLV_F_C_EINT,
+#endif
+	SPMI_REC_CTRL,
+	SPMI_REC0,
+	SPMI_REC1,
+	SPMI_REC2,
+	SPMI_REC3,
+	SPMI_REC4,
+#if SPMI_RCS_SUPPORT
+	SPMI_REC_CMD_DEC,
+	SPMI_DEC_DBG,
+#endif
+	SPMI_MST_DBG
+};
+
+extern struct spmi_device *get_spmi_device(int mstid, unsigned int slv_type);
+extern int spmi_init(struct pmif *pmif_arb);
+
+/* pmif debug API declaration */
+extern void spmi_dump_pmif_reg(int mstid);
+extern void spmi_dump_pmif_record_reg(int mstid);
+extern void spmi_dump_pmif_swinf_reg(int mstid);
+extern void spmi_dump_pmif_busy_reg(int mstid);
+/* spmi debug API declaration */
+extern void spmi_dump_spmimst_reg(int mstid);
+/* pmic debug API declaration */
+extern void spmi_dump_slv_record_reg(struct spmi_device *dev);
+
+#endif /*__SPMI_SW_H__*/

diff --git a/mcu/driver/devdrv/spmi/src/dcl_spmi.c b/mcu/driver/devdrv/spmi/src/dcl_spmi.c
new file mode 100644
index 0000000..e0a2cfe
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/src/dcl_spmi.c

@@ -0,0 +1,480 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *    dcl_pmu.c
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   This Module defines DCL (Driver Common Layer) of the PMIC driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "kal_debug.h"
+#include "kal_public_api.h"
+#include "kal_hrt_api.h"
+#include "intrCtrl.h"
+#include "dcl.h"
+#include "pmif.h"
+#include "spmi.h"
+#include "pmif_sw.h"
+#include "spmi_sw.h"
+#include "us_timer.h"
+#include "drv_features.h"
+
+#if defined (DRV_SPMI_OFF) || DRV_SPMI_NOT_SUPPORT
+
+DCL_STATUS DclSPMI_Initialize(void)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_HANDLE DclSPMI_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSPMI_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSPMI_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSPMI_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSPMI_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSPMI_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSPMI_Close(DCL_HANDLE handle)
+{
+    return STATUS_UNSUPPORTED;
+}
+
+#else /* DRV_SPMI_OFF */
+SPMI_CONTROL_HANDLER spmi_control_handler = 0;
+static DCL_UINT32 dcl_spmi_handle_count = 0;
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_Initialize
+*
+* DESCRIPTION
+*  This function is to initialize SPMI module
+*
+* PARAMETERS
+*  None
+*
+* RETURNS
+*  STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_Initialize(void)
+{
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+	pmif_spmi_init(SPMI_MASTER_0);
+#elif defined(MT6853)
+#if defined(MT6315)
+	pmif_spmi_init(SPMI_MASTER_1);
+#else
+	pmif_spmi_init(SPMI_MASTER_1);
+	pmif_spmi_init(SPMI_MASTER_P_1);
+#endif
+#else
+	pmif_spmi_init(SPMI_MASTER_1);
+	pmif_spmi_init(SPMI_MASTER_P_1);
+#endif
+
+	return STATUS_OK;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_Open
+*
+* DESCRIPTION
+*  This function is to open the SPMI module and return a handle
+*
+* PARAMETERS
+*  dev: only valid for DCL_SPMI
+*  flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+*  DCL_HANDLE_INVALID: Open failed.
+*  other value: a valid handle
+*
+*************************************************************************/
+DCL_HANDLE DclSPMI_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+	kal_uint32 handle;
+
+	if (dev != DCL_SPMI) {
+		/* Incorrecr device ID */
+		return DCL_HANDLE_INVALID;
+	}
+	kal_hrt_take_itc_lock(KAL_ITC_SPMI_LOCK, KAL_INFINITE_WAIT);
+	dcl_spmi_handle_count++;
+	handle = dcl_spmi_handle_count;
+	kal_hrt_give_itc_lock(KAL_ITC_SPMI_LOCK);
+
+	/* Register DCL default lisr */
+	return handle;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_ReadData
+*
+* DESCRIPTION
+*  This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_WriteData
+*
+* DESCRIPTION
+*  This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_Configure
+*
+* DESCRIPTION
+*  This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+*	N/A
+*
+* RETURNS
+*	STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_RegisterCallback
+*
+* DESCRIPTION
+*   This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+*  	N/A
+*
+* RETURNS
+*  STATUS_UNSUPPORTED
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+	return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_Control
+*
+* DESCRIPTION
+*  This function is to send command to control the SPMI module.
+*
+* PARAMETERS
+*  handle: The handle value returned from DclSPMI_Open
+*  cmd: a control command for SPMI module
+* RETURNS
+*  STATUS_OK: command is executed successfully.
+*  STATUS_FAIL: command is failed.
+*  STATUS_INVALID_CMD: It's a invalid command.
+*     STATUS_UNSUPPORTED: It's a unsupported command.
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_Control_Priv(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+	struct spmi_device *md_dev;
+	DCL_INT32 ret = STATUS_OK, cmd_ret = 0;
+
+	switch(cmd) {
+		case EXT_REGISTER_READL:
+		{
+			SPMI_CTRL_EXT_REGISTER_READL *cmd = &(data->rSPMIExtRegisterReadL);
+			unsigned char rdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			//TBD md_dev = get_spmi_device(SPMI_MASTER_0, slaveid);
+			cmd_ret = spmi_ext_register_readl(md_dev, cmd->addr,
+					&rdata, cmd->len);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+			cmd->value = rdata;
+		}
+		break;
+
+		case EXT_REGISTER_WRITEL:
+		{
+			SPMI_CTRL_EXT_REGISTER_WRITEL *cmd = &(data->rSPMIExtRegisterWriteL);
+			unsigned char wdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			wdata = (unsigned char)cmd->value;
+			cmd_ret = spmi_ext_register_writel(md_dev, cmd->addr,
+					&wdata, cmd->len);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+		}
+		break;
+
+		case EXT_REGISTER_READL_FIELD:
+		{
+			SPMI_CTRL_EXT_REGISTER_READL_FIELD *cmd = &(data->rSPMIExtRegisterReadLField);
+			unsigned char rdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			cmd_ret = spmi_ext_register_readl_field(md_dev, cmd->addr,
+					&rdata, cmd->len, cmd->mask, cmd->shift);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+			cmd->value = rdata;
+		}
+		break;
+
+		case EXT_REGISTER_WRITEL_FIELD:
+		{
+			SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD *cmd = &(data->rSPMIExtRegisterWriteLField);
+			unsigned char wdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			wdata = (unsigned char)cmd->value;
+			cmd_ret = spmi_ext_register_writel_field(md_dev, cmd->addr,
+					&wdata, cmd->len, cmd->mask, cmd->shift);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+		}
+		break;
+
+		case REGISTER_READ:
+		{
+			SPMI_CTRL_EXT_REGISTER_READL *cmd = &(data->rSPMIExtRegisterReadL);
+			unsigned char rdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			cmd_ret = spmi_register_read(md_dev, cmd->addr,	&rdata);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+			cmd->value = rdata;
+		}
+		break;
+
+		case REGISTER_WRITE:
+		{
+			SPMI_CTRL_EXT_REGISTER_WRITEL *cmd = &(data->rSPMIExtRegisterWriteL);
+			unsigned char wdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			wdata = (unsigned char)cmd->value;
+			cmd_ret = spmi_register_write(md_dev, cmd->addr, wdata);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+		}
+		break;
+
+		case EXT_REGISTER_READ:
+		{
+			SPMI_CTRL_EXT_REGISTER_READL *cmd = &(data->rSPMIExtRegisterReadL);
+			unsigned char rdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			cmd_ret = spmi_ext_register_read(md_dev, cmd->addr,
+					&rdata, cmd->len);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+			cmd->value = rdata;
+		}
+		break;
+
+		case EXT_REGISTER_WRITE:
+		{
+			SPMI_CTRL_EXT_REGISTER_WRITEL *cmd = &(data->rSPMIExtRegisterWriteL);
+			unsigned char wdata = 0;
+
+			md_dev = get_spmi_device(SPMI_MASTER_0, (unsigned int)cmd->type);
+			wdata = (unsigned char)cmd->value;
+			cmd_ret = spmi_ext_register_write(md_dev, cmd->addr,
+					&wdata, cmd->len);
+			if (cmd_ret)
+				ret = STATUS_FAIL;
+		}
+		break;
+	}
+
+	return ret;
+}
+
+DCL_STATUS DclSPMI_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+	return DclSPMI_Control_Priv(handle, cmd, data);
+}
+/*************************************************************************
+* FUNCTION
+*  DclSPMI_Close
+*
+* DESCRIPTION
+*  This function is to close the SPMI module.
+*
+* PARAMETERS
+*  handle: the returned handle value of DclSPMI_Close
+*
+* RETURNS
+*  STATUS_OK
+*
+*************************************************************************/
+DCL_STATUS DclSPMI_Close(DCL_HANDLE handle)
+{
+	return STATUS_OK;
+}
+
+#endif /* endif DRV_SPMI_OFF */
+

diff --git a/mcu/driver/devdrv/spmi/src/pmif.c b/mcu/driver/devdrv/spmi/src/pmif.c
new file mode 100644
index 0000000..7ef3e76
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/src/pmif.c

@@ -0,0 +1,753 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+/*
+ * MTK PMIF Driver
+ *
+ * Copyright 2019 MediaTek Co.,Ltd.
+ *
+ * DESCRIPTION:
+ *     This file provides API for other drivers to access PMIC registers
+ *
+ */
+
+#include <pmif.h>
+#include <spmi.h>
+#include <pmif_sw.h>
+#include <spmi_sw.h>
+
+#define GET_SWINF_0_FSM(x)	((x>>1)  & 0x00000007)
+#define GET_PMIF_INIT_DONE(x)	((x>>15) & 0x00000001)
+#define TIMEOUT_WAIT_IDLE	(1000000) /* ap latency concern 1ms */
+
+#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG)
+#define PMIF_CMD_PER_1_3 \
+	((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG))
+#define PMIF_CMD_PER_2_3 \
+	((0x1 << PMIF_CMD_EXT_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG))
+
+static int pmif_spmi_read_cmd(struct pmif *arb, unsigned char opc,
+		unsigned char sid, unsigned short addr, unsigned char *buf,
+		unsigned short len);
+static int pmif_spmi_write_cmd(struct pmif *arb, unsigned char opc,
+	unsigned char sid, unsigned short addr, const unsigned char *buf,
+	unsigned short len);
+#if PMIF_NO_PMIC
+static int pmif_spmi_read_cmd(struct pmif *arb, unsigned char opc,
+		unsigned char sid, unsigned short addr, unsigned char *buf,
+		unsigned short len)
+{
+	PMIF_INFO("do Nothing.\n");
+	return 0;
+}
+
+static int pmif_spmi_write_cmd(struct pmif *arb, unsigned char opc,
+	unsigned char sid, unsigned short addr, const unsigned char *buf,
+	unsigned short len)
+{
+	PMIF_INFO("do Nothing.\n");
+	return 0;
+}
+
+/* init interface */
+int pmif_spmi_init(int mstid)
+{
+	PMIF_INFO("do Nothing.\n");
+	return 0;
+}
+#else /* #if PMIF_NO_PMIC */
+/* pmif internal API declaration */
+#if PMIF_TIMEOUT
+static unsigned long long pmif_get_current_time(void);
+static int pmif_timeout_ns(unsigned long long start_time_ns,
+	unsigned long long timeout_time_ns);
+static unsigned long long pmif_time2ns(unsigned long long time_us);
+#endif
+static void pmif_enable_soft_reset(int mstid);
+static void pmif_spmi_enable_clk_set(int mstid);
+static void pmif_spmi_force_normal_mode(int mstid);
+static void pmif_spmi_enable_swinf(int mstid, unsigned int chan_no,
+	unsigned int swinf_no);
+static void pmif_spmi_enable_cmdIssue(int mstid, kal_bool en);
+static void pmif_spmi_enable(int mstid);
+
+
+enum pmif_regs {
+	PMIF_INIT_DONE,
+	PMIF_INF_EN,
+	PMIF_INF_CMD_PER_0,
+	PMIF_INF_CMD_PER_1,
+	PMIF_INF_CMD_PER_2,
+	PMIF_INF_CMD_PER_3,
+	PMIF_INF_MAX_BYTECNT_PER_0,
+	PMIF_INF_MAX_BYTECNT_PER_1,
+	PMIF_INF_MAX_BYTECNT_PER_2,
+	PMIF_INF_MAX_BYTECNT_PER_3,
+	PMIF_ARB_EN,
+	PMIF_CMDISSUE_EN,
+	PMIF_TIMER_CTRL,
+	PMIF_SPI_MODE_CTRL,
+	PMIF_IRQ_EVENT_EN_0,
+	PMIF_IRQ_FLAG_0,
+	PMIF_IRQ_CLR_0,
+	PMIF_SWINF_0_ACC,
+	PMIF_SWINF_0_WDATA_31_0,
+	PMIF_SWINF_0_WDATA_63_32,
+	PMIF_SWINF_0_RDATA_31_0,
+	PMIF_SWINF_0_RDATA_63_32,
+	PMIF_SWINF_0_VLD_CLR,
+	PMIF_SWINF_0_STA,
+	PMIF_SWINF_1_ACC,
+	PMIF_SWINF_1_WDATA_31_0,
+	PMIF_SWINF_1_WDATA_63_32,
+	PMIF_SWINF_1_RDATA_31_0,
+	PMIF_SWINF_1_RDATA_63_32,
+	PMIF_SWINF_1_VLD_CLR,
+	PMIF_SWINF_1_STA,
+	PMIF_SWINF_2_ACC,
+	PMIF_SWINF_2_WDATA_31_0,
+	PMIF_SWINF_2_WDATA_63_32,
+	PMIF_SWINF_2_RDATA_31_0,
+	PMIF_SWINF_2_RDATA_63_32,
+	PMIF_SWINF_2_VLD_CLR,
+	PMIF_SWINF_2_STA,
+	PMIF_SWINF_3_ACC,
+	PMIF_SWINF_3_WDATA_31_0,
+	PMIF_SWINF_3_WDATA_63_32,
+	PMIF_SWINF_3_RDATA_31_0,
+	PMIF_SWINF_3_RDATA_63_32,
+	PMIF_SWINF_3_VLD_CLR,
+	PMIF_SWINF_3_STA,
+};
+
+static int mt6885_regs[] = {
+	[PMIF_INIT_DONE] =			0x0000,
+	[PMIF_INF_EN] =				0x0024,
+	[PMIF_INF_CMD_PER_0] =			0x002c,
+	[PMIF_INF_CMD_PER_1] =			0x0030,
+	[PMIF_INF_CMD_PER_2] =			0x0034,
+	[PMIF_INF_CMD_PER_3] =			0x0038,
+	[PMIF_INF_MAX_BYTECNT_PER_0] =		0x003c,
+	[PMIF_INF_MAX_BYTECNT_PER_1] =		0x0040,
+	[PMIF_INF_MAX_BYTECNT_PER_2] =		0x0044,
+	[PMIF_INF_MAX_BYTECNT_PER_3] =		0x0048,
+	[PMIF_ARB_EN] =				0x0150,
+	[PMIF_CMDISSUE_EN] =			0x03B4,
+	[PMIF_TIMER_CTRL] =			0x03E0,
+	[PMIF_SPI_MODE_CTRL] =			0x0400,
+	[PMIF_IRQ_EVENT_EN_0] =                 0x0418,
+	[PMIF_IRQ_FLAG_0] =                     0x0420,
+	[PMIF_IRQ_CLR_0] =                      0x0424,
+	[PMIF_SWINF_0_ACC] =			0x0C00,
+	[PMIF_SWINF_0_WDATA_31_0] =		0x0C04,
+	[PMIF_SWINF_0_WDATA_63_32] =		0x0C08,
+	[PMIF_SWINF_0_RDATA_31_0] =		0x0C14,
+	[PMIF_SWINF_0_RDATA_63_32] =		0x0C18,
+	[PMIF_SWINF_0_VLD_CLR] =		0x0C24,
+	[PMIF_SWINF_0_STA] =			0x0C28,
+	[PMIF_SWINF_1_ACC] =			0x0C40,
+	[PMIF_SWINF_1_WDATA_31_0] =		0x0C44,
+	[PMIF_SWINF_1_WDATA_63_32] =		0x0C48,
+	[PMIF_SWINF_1_RDATA_31_0] =		0x0C54,
+	[PMIF_SWINF_1_RDATA_63_32] =		0x0C58,
+	[PMIF_SWINF_1_VLD_CLR] =		0x0C64,
+	[PMIF_SWINF_1_STA] =			0x0C68,
+	[PMIF_SWINF_2_ACC] =			0x0C80,
+	[PMIF_SWINF_2_WDATA_31_0] =		0x0C84,
+	[PMIF_SWINF_2_WDATA_63_32] =		0x0C88,
+	[PMIF_SWINF_2_RDATA_31_0] =		0x0C94,
+	[PMIF_SWINF_2_RDATA_63_32] =		0x0C98,
+	[PMIF_SWINF_2_VLD_CLR] =		0x0CA4,
+	[PMIF_SWINF_2_STA] =			0x0CA8,
+	[PMIF_SWINF_3_ACC] =			0x0CC0,
+	[PMIF_SWINF_3_WDATA_31_0] =		0x0CC4,
+	[PMIF_SWINF_3_WDATA_63_32] =		0x0CC8,
+	[PMIF_SWINF_3_RDATA_31_0] =		0x0CD4,
+	[PMIF_SWINF_3_RDATA_63_32] =		0x0CD8,
+	[PMIF_SWINF_3_VLD_CLR] =		0x0CE4,
+	[PMIF_SWINF_3_STA] =			0x0CE8,
+};
+
+#if defined(CHIP10992)
+static int mt6880_regs[] = {
+	[PMIF_INIT_DONE] =			0x0000,
+	[PMIF_INF_EN] =				0x0024,
+	[PMIF_INF_CMD_PER_0] =			0x002c,
+	[PMIF_INF_CMD_PER_1] =			0x0030,
+	[PMIF_INF_CMD_PER_2] =			0x0034,
+	[PMIF_INF_CMD_PER_3] =			0x0038,
+	[PMIF_INF_MAX_BYTECNT_PER_0] =		0x003c,
+	[PMIF_INF_MAX_BYTECNT_PER_1] =		0x0040,
+	[PMIF_INF_MAX_BYTECNT_PER_2] =		0x0044,
+	[PMIF_INF_MAX_BYTECNT_PER_3] =		0x0048,
+	[PMIF_ARB_EN] =				0x0150,
+	[PMIF_CMDISSUE_EN] =			0x03B8,
+	[PMIF_TIMER_CTRL] =			0x03E4,
+	[PMIF_SPI_MODE_CTRL] =			0x0408,
+	[PMIF_IRQ_EVENT_EN_0] =			0x0420,
+	[PMIF_IRQ_FLAG_0] =			0x0428,
+	[PMIF_IRQ_CLR_0] =			0x042C,
+	[PMIF_SWINF_0_ACC] =			0x0800,
+	[PMIF_SWINF_0_WDATA_31_0] =		0x0804,
+	[PMIF_SWINF_0_RDATA_31_0] =		0x0814,
+	[PMIF_SWINF_0_VLD_CLR] =		0x0824,
+	[PMIF_SWINF_0_STA] =			0x0828,
+	[PMIF_SWINF_1_ACC] =			0x0840,
+	[PMIF_SWINF_1_WDATA_31_0] =		0x0844,
+	[PMIF_SWINF_1_RDATA_31_0] =		0x0854,
+	[PMIF_SWINF_1_VLD_CLR] =		0x0864,
+	[PMIF_SWINF_1_STA] =			0x0868,
+	[PMIF_SWINF_2_ACC] =			0x0880,
+	[PMIF_SWINF_2_WDATA_31_0] =		0x0884,
+	[PMIF_SWINF_2_RDATA_31_0] =		0x0894,
+	[PMIF_SWINF_2_VLD_CLR] =		0x08A4,
+	[PMIF_SWINF_2_STA] =			0x08A8,
+	[PMIF_SWINF_3_ACC] =			0x08C0,
+	[PMIF_SWINF_3_WDATA_31_0] =		0x08C4,
+	[PMIF_SWINF_3_RDATA_31_0] =		0x08D4,
+	[PMIF_SWINF_3_VLD_CLR] =		0x08E4,
+	[PMIF_SWINF_3_STA] =			0x08E8,
+};
+#else
+static int mt6853_regs[] = {
+	[PMIF_INIT_DONE] =			0x0000,
+	[PMIF_INF_EN] =				0x0024,
+	[PMIF_INF_CMD_PER_0] =			0x002c,
+	[PMIF_INF_CMD_PER_1] =			0x0030,
+	[PMIF_INF_CMD_PER_2] =			0x0034,
+	[PMIF_INF_CMD_PER_3] =			0x0038,
+	[PMIF_INF_MAX_BYTECNT_PER_0] =		0x003c,
+	[PMIF_INF_MAX_BYTECNT_PER_1] =		0x0040,
+	[PMIF_INF_MAX_BYTECNT_PER_2] =		0x0044,
+	[PMIF_INF_MAX_BYTECNT_PER_3] =		0x0048,
+	[PMIF_ARB_EN] =				0x0150,
+	[PMIF_CMDISSUE_EN] =			0x03B8,
+	[PMIF_TIMER_CTRL] =			0x03E4,
+	[PMIF_SPI_MODE_CTRL] =			0x0408,
+	[PMIF_IRQ_EVENT_EN_0] =                 0x0420,
+	[PMIF_IRQ_FLAG_0] =                     0x0428,
+	[PMIF_IRQ_CLR_0] =                      0x042C,
+	[PMIF_SWINF_0_ACC] =			0x0C00,
+	[PMIF_SWINF_0_WDATA_31_0] =		0x0C04,
+	[PMIF_SWINF_0_WDATA_63_32] =		0x0C08,
+	[PMIF_SWINF_0_RDATA_31_0] =		0x0C14,
+	[PMIF_SWINF_0_RDATA_63_32] =		0x0C18,
+	[PMIF_SWINF_0_VLD_CLR] =		0x0C24,
+	[PMIF_SWINF_0_STA] =			0x0C28,
+	[PMIF_SWINF_1_ACC] =			0x0C40,
+	[PMIF_SWINF_1_WDATA_31_0] =		0x0C44,
+	[PMIF_SWINF_1_WDATA_63_32] =		0x0C48,
+	[PMIF_SWINF_1_RDATA_31_0] =		0x0C54,
+	[PMIF_SWINF_1_RDATA_63_32] =		0x0C58,
+	[PMIF_SWINF_1_VLD_CLR] =		0x0C64,
+	[PMIF_SWINF_1_STA] =			0x0C68,
+	[PMIF_SWINF_2_ACC] =			0x0C80,
+	[PMIF_SWINF_2_WDATA_31_0] =		0x0C84,
+	[PMIF_SWINF_2_WDATA_63_32] =		0x0C88,
+	[PMIF_SWINF_2_RDATA_31_0] =		0x0C94,
+	[PMIF_SWINF_2_RDATA_63_32] =		0x0C98,
+	[PMIF_SWINF_2_VLD_CLR] =		0x0CA4,
+	[PMIF_SWINF_2_STA] =			0x0CA8,
+	[PMIF_SWINF_3_ACC] =			0x0CC0,
+	[PMIF_SWINF_3_WDATA_31_0] =		0x0CC4,
+	[PMIF_SWINF_3_WDATA_63_32] =		0x0CC8,
+	[PMIF_SWINF_3_RDATA_31_0] =		0x0CD4,
+	[PMIF_SWINF_3_RDATA_63_32] =		0x0CD8,
+	[PMIF_SWINF_3_VLD_CLR] =		0x0CE4,
+	[PMIF_SWINF_3_STA] =			0x0CE8,
+};
+#endif
+
+static struct pmif pmif_spmi_arb[] = {
+	{
+		.base = (unsigned int *)PMIF_SPMI_BASE,
+		.regs = mt6885_regs,
+		.spmimst_base = (unsigned int *)SPMI_MST_BASE,
+		.swinf_ch_start = PMIF_SWINF_0_CHAN_NO,
+		.swinf_no = PMIF_AP_SWINF_NO,
+		.write = 0x0,
+		.mstid = SPMI_MASTER_0,
+		.pmifid = PMIF_PMIFID,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+		.pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+		.pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+		.pmif_enable_swinf = pmif_spmi_enable_swinf,
+		.pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+		.pmif_enable = pmif_spmi_enable,
+		.is_pmif_init_done = is_pmif_spmi_init_done,
+	},
+	{
+		.base = (unsigned int *)PMIF_SPMI_BASE,
+#if defined(CHIP10992)
+		.regs = mt6880_regs,
+#else
+		.regs = mt6853_regs,
+#endif
+		.spmimst_base = (unsigned int *)SPMI_MST_BASE,
+		.swinf_ch_start = PMIF_SWINF_0_CHAN_NO,
+		.swinf_no = PMIF_AP_SWINF_NO,
+		.write = 0x0,
+		.mstid = SPMI_MASTER_1,
+		.pmifid = PMIF_PMIFID,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+		.pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+		.pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+		.pmif_enable_swinf = pmif_spmi_enable_swinf,
+		.pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+		.pmif_enable = pmif_spmi_enable,
+		.is_pmif_init_done = is_pmif_spmi_init_done,
+	},
+#if !defined(MT6885) && !defined(MT6873)
+	{
+		.base = (unsigned int *)PMIF_SPMI_P_BASE,
+#if defined(CHIP10992)
+		.regs = mt6880_regs,
+#else
+		.regs = mt6853_regs,
+#endif
+		.spmimst_base = (unsigned int *)SPMI_MST_P_BASE,
+		.swinf_ch_start = PMIF_SWINF_0_CHAN_NO_P,
+		.swinf_no = PMIF_AP_SWINF_NO_P,
+		.write = 0x0,
+		.mstid = SPMI_MASTER_P_1,
+		.pmifid = PMIF_PMIFID_2,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+		.pmif_enable_clk_set = pmif_spmi_enable_clk_set,
+		.pmif_force_normal_mode = pmif_spmi_force_normal_mode,
+		.pmif_enable_swinf = pmif_spmi_enable_swinf,
+		.pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
+		.pmif_enable = pmif_spmi_enable,
+		.is_pmif_init_done = is_pmif_spmi_init_done,
+	},
+#endif
+};
+/* static struct pmif pmif_spi_arb[0]; */
+
+/* pmif timeout */
+#if PMIF_TIMEOUT
+static unsigned long long pmif_get_current_time(void)
+{
+	return gpt4_get_current_tick();
+}
+
+static int pmif_timeout_ns(unsigned long long start_time_ns,
+	unsigned long long timeout_time_ns)
+{
+	return gpt4_timeout_tick(start_time_ns, timeout_time_ns);
+}
+
+static unsigned long long pmif_time2ns(unsigned long long time_us)
+{
+	return gpt4_time2tick_us(time_us);
+}
+#endif
+static inline unsigned int pmif_check_idle(int mstid) {
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int reg_rdata, offset = 0;
+#if PMIF_TIMEOUT
+	unsigned long long start_time_ns = 0, end_time_ns = 0, timeout_ns = 0;
+	unsigned long time_cnt = 100000;
+
+	start_time_ns = pmif_get_current_time();
+	timeout_ns = pmif_time2ns(TIMEOUT_WAIT_IDLE);
+#endif
+
+	do {
+#if PMIF_TIMEOUT
+		if (pmif_timeout_ns(start_time_ns, timeout_ns)) {
+			end_time_ns = pmif_get_current_time();
+			PMIF_ERR("%s timeout %d %d\n", __func__, start_time_ns,
+					end_time_ns - start_time_ns);
+			return -ETIMEDOUT;
+		}
+		if ((time_cnt--) == 0) {
+			PMIF_ERR("%s timeout %d %d\n", __func__, start_time_ns,
+					end_time_ns - start_time_ns);
+			return -ETIMEDOUT;
+		}
+#endif
+		offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->swinf_no);
+		reg_rdata = DRV_Reg32(arb->base + offset);
+	} while(GET_SWINF_0_FSM(reg_rdata) != SWINF_FSM_IDLE);
+
+    return 0;
+}
+
+static inline unsigned int pmif_check_vldclr(int mstid) {
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int reg_rdata, offset = 0;
+#if PMIF_TIMEOUT
+	unsigned long long start_time_ns = 0, end_time_ns = 0, timeout_ns = 0;
+	unsigned long time_cnt = 100000;
+
+	start_time_ns = pmif_get_current_time();
+	timeout_ns = pmif_time2ns(TIMEOUT_WAIT_IDLE);
+#endif
+
+	do {
+#if PMIF_TIMEOUT
+		if (pmif_timeout_ns(start_time_ns, timeout_ns)) {
+			end_time_ns = pmif_get_current_time();
+			PMIF_ERR("%s timeout %d %d\n", __func__, start_time_ns,
+					end_time_ns - start_time_ns);
+			return -ETIMEDOUT;
+		}
+		if ((time_cnt--) == 0) {
+			PMIF_ERR("%s timeout %d %d\n", __func__, start_time_ns,
+					end_time_ns - start_time_ns);
+			return -ETIMEDOUT;
+		}
+#endif
+		offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->swinf_no);
+		reg_rdata = DRV_Reg32(arb->base + offset);
+	} while(GET_SWINF_0_FSM(reg_rdata) != SWINF_FSM_WFVLDCLR);
+
+    return 0;
+}
+static void pmif_enable_soft_reset(int mstid)
+{
+	DRV_WriteReg32(INFRA_GLOBALCON_RST2_SET, 0x1 << 14);
+	DRV_WriteReg32(INFRA_GLOBALCON_RST2_CLR, 0x1 << 14);
+
+	PMIF_INFO("%s done\n", __func__);
+}
+
+static void pmif_spmi_enable_clk_set(int mstid)
+{
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+	/* TBD */
+	DRV_WriteReg32(CLK_CFG_8_CLR, (0x1 << 15) | (0x1 << 12) | (0x7 << 8));
+	DRV_WriteReg32(CLK_CFG_UPDATE1, 0x1 << 2);
+#endif
+
+	/* sys_ck cg enable, turn off clock */
+	DRV_WriteReg32(MODULE_SW_CG_0_SET, 0x0000000f);
+	/* turn off clock */
+	DRV_WriteReg32(MODULE_SW_CG_2_SET, 0x00000100);
+
+	/* toggle SPMI sw reset */
+	pmif_enable_soft_reset(mstid);
+
+	/* sys_ck cg enable, turn on clock */
+	DRV_WriteReg32(MODULE_SW_CG_0_CLR, 0x0000000f);
+	/* turn on clock */
+	DRV_WriteReg32(MODULE_SW_CG_2_CLR, 0x00000100);
+
+	PMIF_INFO("%s done\n", __func__);
+}
+
+static void pmif_spmi_force_normal_mode(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0);
+	unsigned int offset = 0;
+
+	/* Force SPMI in normal mode. */
+	offset = arb->regs[PMIF_SPI_MODE_CTRL];
+	DRV_WriteReg32(arb->base + offset,
+		DRV_Reg32(arb->base + offset) & (~(0x3 << 9)));
+	DRV_WriteReg32(arb->base + offset,
+		DRV_Reg32(arb->base + offset) | (0x1 << 9));
+
+	PMIF_INFO("%s done\n", __func__);
+}
+
+static void pmif_spmi_enable_swinf(int mstid, unsigned int chan_no,
+	unsigned int swinf_no)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int offset = 0;
+
+	/* Enable swinf */
+	offset = arb->regs[PMIF_INF_EN];
+	DRV_WriteReg32(arb->base + offset,
+			0x1 << (arb->swinf_ch_start + arb->swinf_no));
+
+	/* Enable arbitration */
+	offset = arb->regs[PMIF_ARB_EN];
+	DRV_WriteReg32(arb->base + offset,
+			0x1 << (arb->swinf_ch_start + arb->swinf_no));
+
+	PMIF_INFO("%s done\n", __func__);
+}
+
+static void pmif_spmi_enable_cmdIssue(int mstid, kal_bool en)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+
+	/* Enable cmdIssue */
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_CMDISSUE_EN], en);
+
+	PMIF_INFO("%s done\n", __func__);
+}
+
+static void pmif_spmi_enable(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+#if PMIF_NORMAL_BOOT
+	unsigned int bytecnt_per = 0, hw_bytecnt = 0;
+	unsigned int cmd_per = 0;
+
+	/* clear all cmd permission for per channel */
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_CMD_PER_0], 0);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_CMD_PER_1], 0);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_CMD_PER_2], 0);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_CMD_PER_3], 0);
+	/* enable if we need cmd 0~3 permission for per channel */
+	cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
+		PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_1_3 << 16 |
+		PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_1_3 << 0;
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_CMD_PER_0], cmd_per);
+	cmd_per = PMIF_CMD_PER_3 << 4;
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_CMD_PER_1], cmd_per);
+
+	/* set bytecnt max limitation*/
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_0], 0);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_1], 0);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_2], 0);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_3], 0);
+	/* hw bytecnt indicate when we set 0, it can send 1 byte;
+	 * set 1, it can send 2 byte.
+	 */
+	hw_bytecnt = PMIF_BYTECNT_MAX -1;
+	if (hw_bytecnt > 0) {
+		bytecnt_per = hw_bytecnt << 28 | hw_bytecnt << 24 |
+			hw_bytecnt << 20 | hw_bytecnt << 16 |
+			hw_bytecnt << 12 | hw_bytecnt << 8 |
+			hw_bytecnt << 4 | hw_bytecnt << 0;
+	}
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_0],
+			bytecnt_per);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_1],
+			bytecnt_per);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_2],
+			bytecnt_per);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_MAX_BYTECNT_PER_3],
+			bytecnt_per);
+#endif /* end of #if PMIF_NORMAL_BOOT */
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INF_EN], 0x2F5);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_ARB_EN], 0x2F5);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_TIMER_CTRL], 0x3);
+	DRV_WriteReg32(arb->base + arb->regs[PMIF_INIT_DONE], 0x1);
+
+	PMIF_INFO("%s done\n", __func__);
+}
+
+static int pmif_spmi_read_cmd(struct pmif *arb, unsigned char opc,
+		unsigned char sid, unsigned short addr, unsigned char *buf,
+		unsigned short len)
+{
+	int write = 0x0;
+	unsigned int ret = 0, offset = 0, data = 0;
+	unsigned char bc = len - 1;
+
+	if ((sid & ~(0xf)) != 0x0)
+		return -EINVAL;
+
+	if (len > PMIF_BYTECNT_MAX)
+		return -EINVAL;
+
+	/* Check the opcode */
+	if (opc >= 0x60 && opc <= 0x7F)
+		opc = PMIF_CMD_REG;
+	else if (opc >= 0x20 && opc <= 0x2F)
+		opc = PMIF_CMD_EXT_REG;
+	else if (opc >= 0x38 && opc <= 0x3F)
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else
+		return -EINVAL;
+
+	/* ENTER_CRITICAL(); */
+	kal_hrt_take_itc_lock(KAL_ITC_SPMI_LOCK, KAL_INFINITE_WAIT);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	ret = pmif_check_idle(arb->mstid);
+	if(ret)
+		return ret;
+
+	/* Send the command. */
+	offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->swinf_no);
+	DRV_WriteReg32(arb->base + offset,
+		(opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr);
+
+	/* Wait for Software Interface FSM state to be WFVLDCLR,
+	 *
+	 * read the data and clear the valid flag.
+	 */
+	if(write == 0)
+	{
+		ret = pmif_check_vldclr(arb->mstid);
+		if(ret)
+			return ret;
+
+		offset =
+		arb->regs[PMIF_SWINF_0_RDATA_31_0] + (0x40 * arb->swinf_no);
+		data = DRV_Reg32(arb->base + offset);
+		memcpy(buf, &data, (bc & 3) + 1);
+		offset =
+		arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->swinf_no);
+		DRV_WriteReg32(arb->base + offset, 0x1);
+	}
+	kal_hrt_give_itc_lock(KAL_ITC_SPMI_LOCK);
+	/* EXIT_CRITICAL(); */
+
+	return 0x0;
+}
+
+static int pmif_spmi_write_cmd(struct pmif *arb, unsigned char opc,
+	unsigned char sid, unsigned short addr, const unsigned char *buf,
+	unsigned short len)
+{
+	int write = 0x1;
+	unsigned int ret = 0, offset = 0, data = 0;
+	unsigned char bc = len - 1;
+
+	if ((sid & ~(0xf)) != 0x0)
+		return -EINVAL;
+
+	if (len > PMIF_BYTECNT_MAX)
+		return -EINVAL;
+
+	/* Check the opcode */
+	if (opc >= 0x40 && opc <= 0x5F)
+		opc = PMIF_CMD_REG;
+	else if (opc <= 0x0F)
+		opc = PMIF_CMD_EXT_REG;
+	else if (opc >= 0x30 && opc <= 0x37)
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else if (opc >= 0x80)
+		opc = PMIF_CMD_REG_0;
+	else
+		return -EINVAL;
+
+	/* ENTER_CRITICAL(); */
+	kal_hrt_take_itc_lock(KAL_ITC_SPMI_LOCK, KAL_INFINITE_WAIT);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	ret = pmif_check_idle(arb->mstid);
+	if(ret)
+		return ret;
+
+	/* Set the write data. */
+	if (write == 1)
+	{
+		offset =
+		arb->regs[PMIF_SWINF_0_WDATA_31_0] + (0x40 * arb->swinf_no);
+		memcpy(&data, buf, (bc & 3) + 1);
+		DRV_WriteReg32(arb->base + offset, data);
+	}
+	/* Send the command. */
+	offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->swinf_no);
+	DRV_WriteReg32(arb->base + offset,
+		(opc << 30) | (write << 29) | (sid << 24) |
+		(bc << 16) | addr);
+
+	kal_hrt_give_itc_lock(KAL_ITC_SPMI_LOCK);
+	/* EXIT_CRITICAL(); */
+
+	return 0x0;
+}
+
+struct pmif *get_pmif_controller(int inf, int mstid)
+{
+	if (inf == PMIF_SPMI) {
+		return &pmif_spmi_arb[mstid];
+	} else if (inf == PMIF_SPI) {
+		/* TBD
+		 *pmif_spi_arb[mstid].base = (unsigned int *)PMIF_SPI_BASE;
+		 *pmif_spi_arb[mstid].swinf_no = 0x0;
+		 *pmif_spi_arb[mstid].write = 0x0;
+		 *pmif_spi_arb[mstid].pmifid = 0x0;
+		 *pmif_spi_arb[mstid].read_cmd = pmif_spi_read_cmd;
+		 *pmif_spi_arb[mstid].write_cmd = pmif_spi_write_cmd;
+		 *pmif_spi_arb[mstid].read_cmd_nochk = pmif_spi_read_cmd_nochk;
+		 *pmif_spi_arb[mstid].write_cmd_nochk =
+		 *		pmif_spi_write_cmd_nochk;
+		 *return &pmif_spi_arb[mstid];
+		 */
+	}
+
+	return 0;
+}
+int is_pmif_spmi_init_done(int mstid)
+{
+	int ret = 0;
+
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+
+	ret = DRV_Reg32(arb->base + arb->regs[PMIF_INIT_DONE]);
+	PMIF_INFO("%s ret = %d\n", __func__, ret);
+	if ((ret & 0x1) == 1)
+		return 0;
+
+	return -ENODEV;
+}
+
+int pmif_spmi_init(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	int ret = 0;
+
+	INIT_CRITICAL();
+
+	if (is_pmif_spmi_init_done(mstid) != 0) {
+		arb->pmif_enable_clk_set(mstid);
+		arb->pmif_force_normal_mode(mstid);
+		/* Enable SWINF and arbitration for AP. */
+		arb->pmif_enable_swinf(mstid, PMIF_SWINF_0_CHAN_NO,
+			PMIF_AP_SWINF_NO);
+		arb->pmif_enable_cmdIssue(mstid,KAL_TRUE);
+
+		arb->pmif_enable(mstid);
+		ret = arb->is_pmif_init_done(mstid);
+		if(ret) {
+			PMIF_ERR("init done check fail\n");
+			return -ENODEV;
+		}
+	}
+
+	ret = spmi_init(arb);
+	if(ret) {
+		PMIF_ERR("init fail\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+#endif /* endif PMIF_NO_PMIC */

diff --git a/mcu/driver/devdrv/spmi/src/spmi.c b/mcu/driver/devdrv/spmi/src/spmi.c
new file mode 100644
index 0000000..f982a47
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/src/spmi.c

@@ -0,0 +1,992 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+/*
+ * MTK SPMI Driver
+ *
+ * Copyright 2018 MediaTek Co.,Ltd.
+ *
+ * DESCRIPTION:
+ *     This file provides API for other drivers to access PMIC registers
+ *
+ */
+
+#include <spmi.h>
+#include <pmif.h>
+#include <pmif_sw.h>
+#include <spmi_sw.h>
+#include <mt6315_upmu_hw.h>
+
+static int mt6885_spmi_regs[] = {
+	[SPMI_OP_ST_CTRL] =		0x0000,
+	[SPMI_GRP_ID_EN] =		0x0004,
+	[SPMI_OP_ST_STA] =		0x0008,
+	[SPMI_MST_SAMPL] =		0x000c,
+	[SPMI_MST_REQ_EN] =		0x0010,
+#if SPMI_RCS_SUPPORT
+	[SPMI_RCS_CTRL] =		0x0014,
+	[SPMI_SLV_3_0_EINT] =		0x0020,
+	[SPMI_SLV_7_4_EINT] =		0x0024,
+	[SPMI_SLV_B_8_EINT] =		0x0028,
+	[SPMI_SLV_F_C_EINT] =		0x002c,
+#endif /* #if SPMI_RCS_SUPPORT */
+	[SPMI_REC_CTRL] =		0x0040,
+	[SPMI_REC0] =			0x0044,
+	[SPMI_REC1] =			0x0048,
+	[SPMI_REC2] =			0x004c,
+	[SPMI_REC3] =			0x0050,
+	[SPMI_REC4] =			0x0054,
+#if SPMI_RCS_SUPPORT
+	[SPMI_REC_CMD_DEC] =		0x005c,
+	[SPMI_DEC_DBG] =		0x00f8,
+#endif
+	[SPMI_MST_DBG] =		0x00fc,
+};
+
+static struct pmif *pmif_spmi_arb_ctrl[SPMI_MASTER_MAX];
+#if MT63xx_EVB
+#if defined(MT6885) || defined(MT6873)
+struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_3,
+		.grpiden = 0x800,
+		.type = BUCK_MD,
+		.type_id = BUCK_MD_ID,
+		.mstid = SPMI_MASTER_0,/* spmi-m */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0b,
+		.swcid_val = 0x15,
+		.pmif_arb = NULL,
+	},	{
+		.slvid = SPMI_SLAVE_6,
+		.grpiden = 0x800,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+		.mstid = SPMI_MASTER_0,/* spmi-m */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0b,
+		.swcid_val = 0x15,
+		.pmif_arb = NULL,
+	},	{
+		.slvid = SPMI_SLAVE_7,
+		.grpiden = 0x800,
+		.type = BUCK_GPU,
+		.type_id = BUCK_GPU_ID,
+		.mstid = SPMI_MASTER_0,/* spmi-m */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0b,
+		.swcid_val = 0x15,
+		.pmif_arb = NULL,
+	},
+};
+#elif  defined(MT6853)
+#if defined(MT6315)
+struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_3,
+		.grpiden = 0x800,
+		.type = BUCK_MD,
+		.type_id = BUCK_MD_ID,
+		.mstid = SPMI_MASTER_1,/* spmi-m */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0b,
+		.swcid_val = 0x15,
+		.pmif_arb = NULL,
+	},
+};
+#else
+struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_9,
+		.grpiden = 0x0,
+		.type = SUB_PMIC,
+		.type_id = SUB_PMIC_ID,
+		.mstid = SPMI_MASTER_1,/* spmi-m */
+		.hwcid_addr = 0x0000,
+		.hwcid_val = 0x70,/* check [7:4] */
+		.swcid_addr = 0x0001,
+		.swcid_val = 0x08,/* check [3:0] */
+		.pmif_arb = NULL,
+	},	{
+		.slvid = SPMI_SLAVE_8,
+		.grpiden = 0x0,
+		.type = BUCK_MD,
+		.type_id = BUCK_MD_ID,
+		.mstid = SPMI_MASTER_P_1, /* spmi-p */
+		.hwcid_addr = 0x0706,
+		.hwcid_val = 0x00,
+		.swcid_addr = 0x0706,
+		.swcid_val = 0x00,
+		.pmif_arb = NULL,
+	},
+};
+#endif
+#elif  defined(CHIP10992)
+struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_4,
+		.grpiden = 0x1 << 0xB,
+		.type = MAIN_PMIC,
+		.type_id = MAIN_PMIC_ID,
+		.mstid = SPMI_MASTER_1,/* spmi-m */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x30,
+		.swcid_addr = 0x0b,
+		.swcid_val = 0x30,
+		.pmif_arb = NULL,
+	}, {
+		.slvid = SPMI_SLAVE_4,
+		.grpiden = 0x1 << 0xB,
+		.type = BUCK_MD,
+		.type_id = BUCK_MD_ID,
+		.mstid = SPMI_MASTER_P_1,/* spmi-p */
+		.hwcid_addr = 0x01A0, /* TOP_VRCTL_VR0_EN */
+		.hwcid_val = 0xFF, /* All BUCK EN = 0xFF */
+		.pmif_arb = NULL,
+	},
+};
+#endif /* end of #if defined(MT6885) || defined(MT6873) */
+#else
+struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_12,
+		.grpiden = 0x100,
+		.type = BUCK_MD,
+		.type_id = BUCK_MD_ID,
+		.pmif_arb = NULL,
+	},	{
+		.slvid = SPMI_SLAVE_10,
+		.grpiden = 0x100,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+		.pmif_arb = NULL,
+	},	{
+		.slvid = SPMI_SLAVE_11,
+		.grpiden = 0x100,
+		.type = BUCK_GPU,
+		.type_id = BUCK_GPU_ID,
+		.pmif_arb = NULL,
+	},
+};
+#endif
+unsigned char spmi_device_cnt;
+
+/* spmi internal API declaration */
+static int spmi_config_master(unsigned int mstid, kal_bool en);
+static int spmi_config_slave(struct spmi_device *dev);
+static int spmi_cali_rd_clock_polarity(struct spmi_device *dev,
+		unsigned int mstid);
+static int spmi_ctrl_op_st(int mstid, unsigned int grpiden,
+	unsigned int sid, unsigned int cmd);
+#if SPMI_RCS_SUPPORT
+static int spmi_enable_rcs(struct spmi_device *dev, unsigned int mstid);
+int spmi_read_eint_sta(unsigned char *slv_eint_sta);
+#endif
+#if SPMI_DEBUG
+static int spmi_rw_test(struct spmi_device *dev);
+static int spmi_read_check(struct spmi_device *dev);
+static int spmi_drv_ut(struct spmi_device *dev, unsigned int ut);
+#endif
+int spmi_enable_group_id(int mstid, unsigned int grpiden);
+int spmi_lock_slave_reg(struct spmi_device *dev);
+int spmi_unlock_slave_reg(struct spmi_device *dev);
+
+#if SPMI_NO_PMIC
+int spmi_init(struct pmif *pmif_arb)
+{
+	SPMI_INFO("do Nothing.\n");
+	return 0;
+}
+
+#else /* #ifdef SPMI_NO_PMIC */
+/*
+ * Function : mtk_spmi_readl()
+ * Description : mtk spmi controller read api
+ * Parameter :
+ * Return :
+ */
+unsigned int spmi_readl(int mstid, enum spmi_regs reg)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+
+	return DRV_Reg32(arb->spmimst_base + arb->spmimst_regs[reg]);
+}
+
+/*
+ * Function : mtk_spmi_writel()
+ * Description : mtk spmi controller write api
+ * Parameter :
+ * Return :
+ */
+void spmi_writel(int mstid, enum spmi_regs reg, unsigned int val)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+
+	DRV_WriteReg32(arb->spmimst_base + arb->spmimst_regs[reg], val);
+}
+
+/*
+ * Function : spmi_lock_slave_reg()
+ * Description : protect spmi slv register to be write
+ * Parameter :
+ * Return :
+ */
+int spmi_lock_slave_reg(struct spmi_device *dev)
+{
+	const unsigned char wpk_key = 0x0;
+	const unsigned char wpk_key_h = 0x0;
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* enable dig_wpk key, write 0x0*/
+		spmi_ext_register_writel(dev, MT6315_PMIC_DIG_WPK_KEY_ADDR,
+				&wpk_key, 1);
+		spmi_ext_register_writel(dev, MT6315_PMIC_DIG_WPK_KEY_H_ADDR,
+				&wpk_key_h, 1);
+	}
+
+	return 0;
+}
+
+/*
+ * Function : spmi_unlock_slave_reg()
+ * Description : unlock spmi slv register to write
+ * Parameter :
+ * Return :
+ */
+int spmi_unlock_slave_reg(struct spmi_device *dev)
+{
+	const unsigned char wpk_key = 0x15;
+	const unsigned char wpk_key_h = 0x63;
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* disable dig_wpk key, write 0x6315*/
+		spmi_ext_register_writel(dev, MT6315_PMIC_DIG_WPK_KEY_ADDR,
+				&wpk_key, 1);
+		spmi_ext_register_writel(dev, MT6315_PMIC_DIG_WPK_KEY_H_ADDR,
+				&wpk_key_h, 1);
+	}
+
+	return 0;
+}
+
+static int spmi_config_master(unsigned int mstid, kal_bool en)
+{
+	/* Software reset */
+	DRV_WriteReg32(WDT_SWSYSRST2, 0x85 << 24 | 0x1 << 4);
+
+#if !defined(CONFIG_FPGA_EARLY_PORTING)
+	/* TBD */
+	DRV_WriteReg32(CLK_CFG_16_CLR, 0x7 | (0x1 << 4) | (0x1 << 7));
+	DRV_WriteReg32(CLK_CFG_UPDATE2, 0x1 << 2);
+#endif
+
+	/* Software reset */
+	DRV_WriteReg32(WDT_SWSYSRST2, 0x85 << 24);
+
+	/* Enable SPMI */
+	spmi_writel(mstid, SPMI_MST_REQ_EN, en);
+
+	SPMI_INFO("%s done\n", __func__);
+
+	return 0;
+}
+
+static int spmi_config_slave(struct spmi_device *dev)
+{
+	return 0;
+}
+
+static int spmi_cali_rd_clock_polarity(struct spmi_device *dev,
+		unsigned int mstid)
+{
+	unsigned int i = 0;
+#if 0 //TBD
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+	struct cali cali_data[] = {
+			{SPMI_CK_DLY_1T, SPMI_CK_POL_POS},
+			{SPMI_CK_NO_DLY, SPMI_CK_POL_POS},
+			{SPMI_CK_NO_DLY, SPMI_CK_POL_NEG}
+	};
+
+	/* Indicate sampling clock polarity, 1: Positive 0: Negative  */
+	for (i = 0;i < 3; i++) {
+		spmi_writel(mstid, SPMI_MST_SAMPL,
+			(cali_data[i].dly << 0x1) | cali_data[i].pol);
+		/* for exception reboot, we only call UT/spmi_read_check w/o
+		 * write test. It avoid to affect exception record.
+		 */
+#if SPMI_DEBUG
+		if (spmi_read_check(dev) == 0) {
+			SPMI_DBG("dly:%d, pol:%d\n", cali_data[i].dly,
+					cali_data[i].pol);
+			break;
+		}
+#endif
+	}
+	if (i == 3) {
+		SPMI_ERR("FATAL ERROR");
+		ASSERT(0);
+	}
+
+#if 0 //TBD
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+	return 0;
+}
+
+#if SPMI_RCS_SUPPORT
+static int spmi_enable_rcs(struct spmi_device *dev, unsigned int mstid)
+{
+	unsigned char wdata = 0, rdata = 0, i = 0;
+
+	/* clear int status */
+	wdata = 0xc0;
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_INT_STATUS_RCS0_ADDR,
+		&wdata, 1);
+
+	/* config match mode */
+	wdata = 0x2;
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_INT_RCS1_ADDR, &wdata, 1);
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_INT_RCS1_ADDR, &rdata, 1);
+	SPMI_DBG("slvid:%x After set RG_INT_RCS1[0x%x]=0x%x\n", dev->slvid,
+			MT6315_PMIC_RG_INT_RCS1_ADDR, rdata);
+
+	/* set
+	 * RG_RCS_ABIT[1] = 1
+	 * RG_RCS_CMD[3:2] = 1
+	 * RG_RCS_ID[7:4] = 0
+	 */
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_RCS_ABIT_ADDR, &rdata, 1);
+	wdata = rdata |
+			(0x1 << MT6315_PMIC_RG_RCS_ABIT_SHIFT) |
+			(0x1 << MT6315_PMIC_RG_RCS_CMD_SHIFT);
+	wdata &= ~(0xf << MT6315_PMIC_RG_RCS_ID_SHIFT);
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_RCS_ABIT_ADDR, &wdata, 1);
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_RCS_ABIT_ADDR, &rdata, 1);
+	SPMI_DBG("slvid:%x After set SPMI_RCS_FUN0[0x%x]=0x%x\n", dev->slvid,
+			MT6315_PMIC_RG_RCS_ABIT_ADDR, rdata);
+
+	/* set rcs_addr = slvid */
+	wdata = dev->slvid;
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_RCS_ADDR_ADDR, &wdata, 1);
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_RCS_ADDR_ADDR, &rdata, 1);
+	SPMI_DBG("slvid:%x After set RCS_ADDR[0x%x]=0x%x\n", dev->slvid,
+			MT6315_PMIC_RG_RCS_ADDR_ADDR, rdata);
+
+	/* set mask */
+	wdata = 0x0;
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_INT_MASK_RCS0_ADDR,
+			&wdata, 1);
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_INT_MASK_RCS0_ADDR,
+			&rdata, 1);
+	SPMI_DBG("slvid:%x After set RG_INT_MASK[0x%x]=0x%x\n", dev->slvid,
+			MT6315_PMIC_RG_INT_MASK_RCS0_ADDR, rdata);
+
+	/* set top rcs0/rcs1 interrupt enable */
+	wdata = (0x1 << MT6315_PMIC_RG_INT_EN_RCS0_SHIFT) |
+		(0x1 << MT6315_PMIC_RG_INT_EN_RCS1_SHIFT);
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_INT_EN_RCS0_ADDR,
+			&wdata, 1);
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_INT_EN_RCS0_ADDR,
+			&rdata, 1);
+	SPMI_DBG("slvid:%x After set RG_INT_EN[0x%x]=0x%x\n", dev->slvid,
+			MT6315_PMIC_RG_INT_EN_RCS0_ADDR, rdata);
+
+	/* enable rcs function */
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_RCS_ENABLE_ADDR,
+			&rdata, 1);
+	wdata = rdata | (0x1 << MT6315_PMIC_RG_RCS_ENABLE_SHIFT);
+	spmi_ext_register_writel(dev, MT6315_PMIC_RG_RCS_ENABLE_ADDR,
+			&wdata, 1);
+	spmi_ext_register_readl(dev, MT6315_PMIC_RG_RCS_ENABLE_ADDR,
+			&rdata, 1);
+	SPMI_DBG("slvid:%x After set Enable[0x%x]=0x%x\n", dev->slvid,
+			MT6315_PMIC_RG_RCS_ENABLE_ADDR, rdata);
+
+}
+
+int spmi_read_eint_sta(unsigned char *slv_eint_sta)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0);
+	unsigned char offset = 0, j = 0, rdata = 0;
+	unsigned int regs = 0;
+
+	for (offset = 0; offset < 4; offset++) {
+		regs = arb->spmimst_regs[SPMI_SLV_3_0_EINT] + (offset*4);
+		rdata = DRV_Reg32(arb->spmimst_base + regs);
+		*(slv_eint_sta + j) = rdata & 0xff;
+		*(slv_eint_sta + j+1) = (rdata >> 8) & 0xff;
+		*(slv_eint_sta + j+2) = (rdata >> 16) & 0xff;
+		*(slv_eint_sta + j+3) = (rdata >> 24) & 0xff;
+		j += 4;
+	}
+
+	for (offset = 0; offset < 16; offset++) {
+		SPMI_INFO("%d, slv_eint_sta[0x%x]\n", offset,
+				*(slv_eint_sta + offset));
+	}
+	spmi_writel(mstid, SPMI_SLV_3_0_EINT, 0xffffffff);
+	spmi_writel(mstid, SPMI_SLV_7_4_EINT, 0xffffffff);
+	spmi_writel(mstid, SPMI_SLV_B_8_EINT, 0xffffffff);
+	spmi_writel(mstid, SPMI_SLV_F_C_EINT, 0xffffffff);
+
+	SPMI_INFO("%s, [0x%x]=0x%x\n", __func__,
+		arb->spmimst_base + arb->spmimst_regs[SPMI_DEC_DBG],
+		spmi_readl(mstid, SPMI_DEC_DBG));
+}
+#endif
+
+#if SPMI_EXTADDR_SUPPORT
+int spmi_register_zero_write_extaddr(struct spmi_device *dev,
+		unsigned int addr, unsigned char data)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* assign specific addr */
+		wdata = (addr&0xff);
+		spmi_ext_register_writel(dev,
+			MT6315_PMIC_RG_EXTADR_REG0_W_ADDR, &wdata, 1);
+		wdata = (addr>>8)&0xff;
+		spmi_ext_register_writel(dev,
+			MT6315_PMIC_RG_EXTADR_REG0_W_H_ADDR, &wdata, 1);
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_ZERO_WRITE,
+					dev->slvid, addr, &data, 1);
+}
+
+int spmi_register_zero_write_set_extaddr(struct spmi_device *dev,
+		unsigned int addr, kal_bool en)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		if (en == KAL_TRUE) {
+			/* assign specific addr */
+			wdata = (addr&0xff);
+			spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_REG0_W_ADDR, &wdata, 1);
+			wdata = (addr>>8)&0xff;
+			spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_REG0_W_H_ADDR,
+				&wdata, 1);
+		} else {
+			/* assign specific addr */
+			wdata = 0;
+			spmi_ext_register_writel(dev,
+					MT6315_PMIC_RG_EXTADR_REG0_W_ADDR,
+					&wdata, 1);
+			spmi_ext_register_writel(dev,
+					MT6315_PMIC_RG_EXTADR_REG0_W_H_ADDR,
+					&wdata, 1);
+		}
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return 0;
+}
+
+int spmi_register_read_extaddr(struct spmi_device *dev, unsigned int addr,
+		unsigned char *buf)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* assign specific addr */
+		wdata = ((addr >> 5) & 0xff);
+		spmi_ext_register_writel(dev,
+			MT6315_PMIC_RG_EXTADR_REG_RW_ADDR, &wdata, 1);
+		wdata = ((addr >> 5) & 0xff00);
+		spmi_ext_register_writel(dev,
+			MT6315_PMIC_RG_EXTADR_REG_RW_H_ADDR, &wdata, 1);
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return dev->pmif_arb->read_cmd(dev->pmif_arb, SPMI_CMD_READ,
+					dev->slvid, addr, buf, 1);
+}
+
+int spmi_register_write_extaddr(struct spmi_device *dev, unsigned int addr,
+		unsigned char data)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* assign specific addr */
+		wdata = ((addr >> 5) & 0xff);
+		spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_REG_RW_ADDR, &wdata, 1);
+		wdata = ((addr >> 5) & 0xff00);
+		spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_REG_RW_H_ADDR,
+				&wdata, 1);
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_WRITE,
+					dev->slvid, addr, &data, 1);
+}
+
+int spmi_register_rw_set_extaddr(struct spmi_device *dev, unsigned int addr,
+		kal_bool en)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		if (en == KAL_TRUE) {
+			/* assign specific addr */
+			wdata = ((addr >> 5) & 0xff);
+			spmi_ext_register_writel(dev,
+					MT6315_PMIC_RG_EXTADR_REG_RW_ADDR,
+					&wdata, 1);
+			wdata = ((addr >> 5) & 0xff00);
+			spmi_ext_register_writel(dev,
+					MT6315_PMIC_RG_EXTADR_REG_RW_H_ADDR,
+					&wdata, 1);
+		} else {
+			/* assign specific addr */
+			wdata = 0;
+			spmi_ext_register_writel(dev,
+					MT6315_PMIC_RG_EXTADR_REG_RW_ADDR,
+					&wdata, 1);
+			spmi_ext_register_writel(dev,
+					MT6315_PMIC_RG_EXTADR_REG_RW_H_ADDR,
+					&wdata, 1);
+		}
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return 0;
+}
+
+int spmi_ext_register_read_extaddr(struct spmi_device *dev, unsigned int addr,
+		unsigned char *buf, unsigned short len)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* assign specific addr */
+		wdata = ((addr >> 8) & 0xff);
+		spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_EXT_REG_RW_ADDR,
+				&wdata, 1);
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return dev->pmif_arb->read_cmd(dev->pmif_arb, SPMI_CMD_EXT_READ,
+					dev->slvid, addr, buf, len);
+}
+
+int spmi_ext_register_write_extaddr(struct spmi_device *dev, unsigned int addr,
+		const unsigned char *buf, unsigned short len)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* assign specific addr */
+		wdata = ((addr >> 8) & 0xff);
+		spmi_ext_register_writel(dev,
+			MT6315_PMIC_RG_EXTADR_EXT_REG_RW_ADDR, &wdata, 1);
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_EXT_WRITE,
+					dev->slvid, addr, buf, len);
+}
+
+int spmi_ext_register_rw_set_extaddr(struct spmi_device *dev,
+		unsigned int addr, kal_bool en)
+{
+	unsigned char wdata = 0;
+
+	spmi_unlock_slave_reg(dev);
+
+	if ((dev->slvid == SPMI_SLAVE_6) ||
+		(dev->slvid == SPMI_SLAVE_7) ||
+		(dev->slvid == SPMI_SLAVE_3)) {
+		/* assign specific addr */
+		if (en == KAL_TRUE) {
+			wdata = ((addr >> 8) & 0xff);
+			spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_EXT_REG_RW_ADDR,
+				&wdata, 1);
+		} else {
+			wdata = 0;
+			spmi_ext_register_writel(dev,
+				MT6315_PMIC_RG_EXTADR_EXT_REG_RW_ADDR,
+				&wdata, 1);
+		}
+	}
+
+	spmi_lock_slave_reg(dev);
+
+	return 0;
+}
+#endif /* end of SPMI_EXTADDR_SUPPORT */
+
+static int spmi_ctrl_op_st(int mstid, unsigned int grpiden, unsigned int sid,
+		unsigned int cmd)
+{
+	unsigned int rdata = 0x0;
+
+	/* gid is 0x800 */
+	spmi_writel(mstid, SPMI_GRP_ID_EN, grpiden);
+#if MT63xx_EVB
+	if (grpiden == (1 << SPMI_GROUP_ID))
+		spmi_writel(mstid, SPMI_OP_ST_CTRL,
+			(cmd << 0x4) | SPMI_GROUP_ID);
+#else
+	if (grpiden == 0x100)
+		spmi_writel(mstid, SPMI_OP_ST_CTRL, (cmd << 0x4) | 0x8);
+#endif
+	else
+		spmi_writel(mstid, SPMI_OP_ST_CTRL, (cmd << 0x4) | sid);
+
+	SPMI_WARN("spmi_ctrl_op_st 0x%x\n", spmi_readl(mstid, SPMI_OP_ST_CTRL));
+
+	do
+	{
+		rdata = spmi_readl(mstid, SPMI_OP_ST_STA);
+		SPMI_DBG("spmi_ctrl_op_st 0x%x\n", rdata);
+
+		if (((rdata >> 0x1) & SPMI_OP_ST_NACK) == SPMI_OP_ST_NACK) {
+			break;
+		}
+		}while((rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY);
+
+	return 0;
+}
+
+int spmi_command_reset(int mstid, struct spmi_device *dev, unsigned int grpiden)
+{
+#if MT63xx_EVB
+	if (grpiden != (1 << SPMI_GROUP_ID))
+		dev->slvid = grpiden;
+#else
+	if (grpiden != 0x100)
+		dev->slvid = grpiden;
+#endif
+	return spmi_ctrl_op_st(mstid, grpiden, dev->slvid, SPMI_RESET);
+}
+int spmi_command_sleep(int mstid, struct spmi_device *dev, unsigned int grpiden)
+{
+#if MT63xx_EVB
+	if (grpiden != (1 << SPMI_GROUP_ID))
+		dev->slvid = grpiden;
+#else
+	if (grpiden != 0x100)
+		dev->slvid = grpiden;
+#endif
+	return spmi_ctrl_op_st(mstid, grpiden, dev->slvid, SPMI_SLEEP);
+}
+int spmi_command_wakeup(int mstid, struct spmi_device *dev, unsigned int grpiden)
+{
+#if MT63xx_EVB
+	if (grpiden != (1 << SPMI_GROUP_ID))
+		dev->slvid = grpiden;
+#else
+	if (grpiden != 0x100)
+		dev->slvid = grpiden;
+#endif
+	return spmi_ctrl_op_st(mstid, grpiden, dev->slvid, SPMI_WAKEUP);
+}
+int spmi_command_shutdown(int mstid, struct spmi_device *dev, unsigned int grpiden)
+{
+#if MT63xx_EVB
+	if (grpiden != (1 << SPMI_GROUP_ID))
+		dev->slvid = grpiden;
+#else
+	if (grpiden != 0x100)
+		dev->slvid = grpiden;
+#endif
+	return spmi_ctrl_op_st(mstid, grpiden, dev->slvid, SPMI_SHUTDOWN);
+}
+
+int spmi_enable_group_id(int mstid, unsigned int grpiden)
+{
+	spmi_writel(mstid, SPMI_GRP_ID_EN, grpiden);
+
+	return 0;
+}
+
+#if SPMI_DEBUG
+static int spmi_rw_test(struct spmi_device *dev)
+{
+	unsigned char wdata = 0, rdata = 0;
+
+	if (dev->mstid == SPMI_MASTER_P_1) {
+		SPMI_INFO("SPMI-P doesn't do %s\n", __func__);
+		return 0;
+	}
+	switch (dev->slvid) {
+	case SPMI_SLAVE_3:
+	case SPMI_SLAVE_6:
+	case SPMI_SLAVE_7:
+		wdata = DEFAULT_VALUE_READ_TEST;
+		spmi_ext_register_writel(dev, MT6315_PMIC_TOP_MDB_RSV1_ADDR,
+				&wdata, 1);
+		spmi_ext_register_readl(dev, MT6315_PMIC_TOP_MDB_RSV1_ADDR,
+				&rdata, 1);
+		if (rdata != DEFAULT_VALUE_READ_TEST) {
+			SPMI_ERR("%s fail_r, slvid:%d rdata = 0x%x.\n",
+				__func__, dev->slvid, rdata);
+			return -EIO;
+		} else
+			SPMI_DBG("%s pass_r, slvid:%d\n", __func__, dev->slvid);
+
+		wdata = DEFAULT_VALUE_WRITE_TEST;
+		spmi_ext_register_writel(dev, MT6315_PMIC_TOP_MDB_RSV1_H_ADDR,
+				&wdata, 1);
+
+		spmi_ext_register_readl(dev, MT6315_PMIC_TOP_MDB_RSV1_H_ADDR,
+				&rdata, 1);
+		if (rdata != DEFAULT_VALUE_WRITE_TEST) {
+			SPMI_ERR("%s fail_w, slvid:%d rdata = 0x%x.\n",
+				__func__, dev->slvid, rdata);
+			return -EIO;
+		} else
+			SPMI_DBG("%s pass_w, slvid:%d\n", __func__, dev->slvid);
+
+		break;
+	case SPMI_SLAVE_9:
+		spmi_read_check(dev);
+		break;
+	case SPMI_SLAVE_8:
+	default:
+		SPMI_ERR("%s not be here, slvid:%d\n", __func__, dev->slvid);
+		break;
+	}
+	return 0;
+}
+
+static int spmi_read_check(struct spmi_device *dev)
+{
+	unsigned char rdata = 0;
+
+	spmi_ext_register_readl(dev, dev->hwcid_addr, &rdata, 1);
+	/* mt6362 can only check 0x00[7:4], other mt63xx can align the rule */
+	if ((rdata & 0xF0) != (dev->hwcid_val & 0xF0)) {
+		SPMI_ERR("%s next, slvid:%d rdata = 0x%x.\n",
+			__func__, dev->slvid, rdata);
+		return -EIO;
+	} else
+		SPMI_DBG("%s done, slvid:%d\n", __func__, dev->slvid);
+
+	return 0;
+}
+
+static int spmi_drv_ut(struct spmi_device *dev, unsigned int ut)
+{
+	int ret = 0;
+
+	switch (ut) {
+		case 1:
+			ret = spmi_rw_test(dev);
+			break;
+		case 2:
+			ret = spmi_read_check(dev);
+			break;
+		case 3:
+			break;
+		default:
+			break;
+	}
+
+	return ret;
+}
+#endif /* end of #if SPMI_DEBUG */
+
+struct spmi_device *get_spmi_device(int mstid, unsigned int slv_type)
+{
+	unsigned int i;
+
+	for (i = 0; i < spmi_device_cnt; i++) {
+		if (slv_type == spmi_dev[i].type) {
+			return &spmi_dev[i];
+		}
+	}
+
+	return NULL;
+}
+
+int spmi_init(struct pmif *pmif_arb)
+{
+	int i = 0;
+#if SPMI_DEBUG
+	int ret = 0;
+#endif
+
+	if (pmif_arb == NULL) /* null check */ {
+		SPMI_ERR("arguments err\n");
+		return -EINVAL;
+	}
+
+	pmif_arb->spmimst_regs = mt6885_spmi_regs;
+	pmif_spmi_arb_ctrl[pmif_arb->mstid] = pmif_arb;
+	spmi_device_cnt = sizeof(spmi_dev)/sizeof(spmi_dev[0]);
+
+	if (is_pmif_spmi_init_done(pmif_arb->mstid) != 0)
+		spmi_config_master(pmif_arb->mstid, KAL_TRUE);
+
+	for (i = 0; i < spmi_device_cnt; i++) {
+		if (pmif_arb->mstid == spmi_dev[i].mstid) {
+			spmi_dev[i].pmif_arb = pmif_spmi_arb_ctrl[pmif_arb->mstid];
+			if (is_pmif_spmi_init_done(pmif_arb->mstid) != 0) {
+				spmi_config_slave(&spmi_dev[i]);
+				spmi_cali_rd_clock_polarity(&spmi_dev[i],
+						pmif_arb->mstid);
+			}
+#if SPMI_MONITOR_SUPPORT
+			/* dump 1st time slave debug register when booting */
+			spmi_dump_slv_record_reg(&spmi_dev[i]);
+#endif
+#if SPMI_RCS_SUPPORT
+			if (is_pmif_spmi_init_done() != 0) {
+				/* enable master rcs support */
+				spmi_writel(pmif_arb->mstid, SPMI_MST_RCS_CTRL, 0x15);
+				spmi_enable_rcs(&spmi_dev[i], pmif_arb->mstid);
+			}
+#endif
+
+#if SPMI_DEBUG
+			/* shouldn't enable at here*/
+			ret = spmi_drv_ut(&spmi_dev[i], 1);
+			if(ret) {
+				SPMI_ERR("EIO err\n");
+				return ret;
+			}
+#endif
+			/*TBD spmi_lock_slave_reg(&spmi_dev[i]); */
+		}
+	}
+	SPMI_INFO("%s done\n", __func__);
+
+	return 0;
+}
+
+#endif /* #ifdef SPMI_NO_PMIC */

diff --git a/mcu/driver/devdrv/spmi/src/spmi_common.c b/mcu/driver/devdrv/spmi/src/spmi_common.c
new file mode 100644
index 0000000..e7fb4e1
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/src/spmi_common.c

@@ -0,0 +1,154 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+/*
+ * MTK SPMI Common Driver
+ *
+ * Copyright 2018 MediaTek Co.,Ltd.
+ *
+ * DESCRIPTION:
+ *     This file provides API for other drivers to access PMIC registers
+ *
+ */
+
+#include <pmif.h>
+#include <spmi.h>
+#include <pmif_sw.h>
+#include <spmi_sw.h>
+
+#if SPMI_NO_PMIC
+int spmi_ext_register_readl(struct spmi_device *dev, unsigned int addr,
+		unsigned char *buf, unsigned short len)
+{
+	SPMI_INFO("%s do Nothing.\n", __func__);
+	return 0;
+}
+int spmi_ext_register_writel(struct spmi_device *dev, unsigned int addr,
+		const unsigned char *buf, unsigned short len)
+{
+	SPMI_INFO("%s do Nothing.\n", __func__);
+	return 0;
+}
+#else /* #ifdef SPMI_NO_PMIC */
+int spmi_register_zero_write(struct spmi_device *dev, unsigned int addr,
+		unsigned char data)
+{
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_ZERO_WRITE,
+					dev->slvid, addr, &data, 1);
+}
+
+int spmi_register_read(struct spmi_device *dev, unsigned int addr,
+		unsigned char *buf)
+{
+	return dev->pmif_arb->read_cmd(dev->pmif_arb, SPMI_CMD_READ,
+					dev->slvid, addr, buf, 1);
+}
+
+int spmi_register_write(struct spmi_device *dev, unsigned int addr,
+		unsigned char data)
+{
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_WRITE,
+					dev->slvid, addr, &data, 1);
+}
+
+int spmi_ext_register_read(struct spmi_device *dev, unsigned int addr,
+		unsigned char *buf, unsigned short len)
+{
+	return dev->pmif_arb->read_cmd(dev->pmif_arb, SPMI_CMD_EXT_READ,
+					dev->slvid, addr, buf, len);
+}
+
+int spmi_ext_register_write(struct spmi_device *dev, unsigned int addr,
+		const unsigned char *buf, unsigned short len)
+{
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_EXT_WRITE,
+					dev->slvid, addr, buf, len);
+}
+
+int spmi_ext_register_readl(struct spmi_device *dev, unsigned int addr,
+		unsigned char *buf, unsigned short len)
+{
+	return dev->pmif_arb->read_cmd(dev->pmif_arb, SPMI_CMD_EXT_READL,
+					dev->slvid, addr, buf, len);
+}
+
+int spmi_ext_register_writel(struct spmi_device *dev, unsigned int addr,
+		const unsigned char *buf, unsigned short len)
+{
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_EXT_WRITEL,
+					dev->slvid, addr, buf, len);
+}
+
+int spmi_ext_register_readl_field(struct spmi_device *dev, unsigned int addr,
+	unsigned char *buf, unsigned short len,
+	unsigned short mask, unsigned short shift)
+{
+	unsigned int ret = 0;
+	unsigned char rdata = 0;
+
+	if (len > 1)
+		return -2;
+
+	ret = dev->pmif_arb->read_cmd(dev->pmif_arb, SPMI_CMD_EXT_READL,
+					dev->slvid, addr, &rdata, len);
+	if (ret != 0)
+		return ret;
+
+	*buf = (rdata >> shift) & mask;
+
+	return 0;
+}
+
+int spmi_ext_register_writel_field(struct spmi_device *dev, unsigned int addr,
+	const unsigned char *buf, unsigned short len,
+	unsigned short mask, unsigned short shift)
+{
+	unsigned char data = 0x0;
+	unsigned int ret = 0;
+
+	if (len > 1)
+		return -2;
+
+	ret = spmi_ext_register_readl(dev, addr, &data, 1);
+	if (ret != 0)
+		return ret;
+
+	data = data & ~(mask << shift);
+	data |= (*buf << shift);
+	return dev->pmif_arb->write_cmd(dev->pmif_arb, SPMI_CMD_EXT_WRITEL,
+					dev->slvid, addr, &data, len);
+}
+#endif /* endif SPMI_NO_PMIC */

diff --git a/mcu/driver/devdrv/spmi/src/spmi_dbg.c b/mcu/driver/devdrv/spmi/src/spmi_dbg.c
new file mode 100644
index 0000000..2924204
--- /dev/null
+++ b/mcu/driver/devdrv/spmi/src/spmi_dbg.c

@@ -0,0 +1,918 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+/*
+ * MTK SPMI Driver
+ *
+ * Copyright 2018 MediaTek Co.,Ltd.
+ *
+ * DESCRIPTION:
+ *     This file provides API for other drivers to access PMIC registers
+ *
+ */
+#include <pmif.h>
+#include <spmi.h>
+#include <spmi_sw.h>
+#include <pmif_sw.h>
+#include <mt6315_upmu_hw.h>
+
+#if !SPMI_NO_PMIC
+
+#if (SPMI_CTP)
+#define sprintf FormatString
+#endif
+
+enum pmif_dbg_regs {
+	PMIF_INIT_DONE,
+	PMIF_INF_BUSY_STA,
+	PMIF_OTHER_BUSY_STA_0,
+	PMIF_OTHER_BUSY_STA_1,
+	PMIF_IRQ_EVENT_EN_0,
+	PMIF_IRQ_FLAG_0,
+	PMIF_IRQ_CLR_0,
+	PMIF_IRQ_EVENT_EN_1,
+	PMIF_IRQ_FLAG_1,
+	PMIF_IRQ_CLR_1,
+	PMIF_IRQ_EVENT_EN_2,
+	PMIF_IRQ_FLAG_2,
+	PMIF_IRQ_CLR_2,
+	PMIF_IRQ_EVENT_EN_3,
+	PMIF_IRQ_FLAG_3,
+	PMIF_IRQ_CLR_3,
+	PMIF_IRQ_EVENT_EN_4,
+	PMIF_IRQ_FLAG_4,
+	PMIF_IRQ_CLR_4,
+	PMIF_WDT_EVENT_EN_0,
+	PMIF_WDT_FLAG_0,
+	PMIF_WDT_EVENT_EN_1,
+	PMIF_WDT_FLAG_1,
+	PMIF_MONITOR_CTRL,
+	PMIF_MONITOR_TARGET_CHAN_0,
+	PMIF_MONITOR_TARGET_CHAN_1,
+	PMIF_MONITOR_TARGET_CHAN_2,
+	PMIF_MONITOR_TARGET_CHAN_3,
+	PMIF_MONITOR_TARGET_CHAN_4,
+	PMIF_MONITOR_TARGET_CHAN_5,
+	PMIF_MONITOR_TARGET_CHAN_6,
+	PMIF_MONITOR_TARGET_CHAN_7,
+	PMIF_MONITOR_TARGET_WRITE,
+	PMIF_MONITOR_TARGET_ADDR_0,
+	PMIF_MONITOR_TARGET_ADDR_1,
+	PMIF_MONITOR_TARGET_ADDR_2,
+	PMIF_MONITOR_TARGET_ADDR_3,
+	PMIF_MONITOR_TARGET_ADDR_4,
+	PMIF_MONITOR_TARGET_ADDR_5,
+	PMIF_MONITOR_TARGET_ADDR_6,
+	PMIF_MONITOR_TARGET_ADDR_7,
+	PMIF_MONITOR_TARGET_WDATA_0,
+	PMIF_MONITOR_TARGET_WDATA_1,
+	PMIF_MONITOR_TARGET_WDATA_2,
+	PMIF_MONITOR_TARGET_WDATA_3,
+	PMIF_MONITOR_TARGET_WDATA_4,
+	PMIF_MONITOR_TARGET_WDATA_5,
+	PMIF_MONITOR_TARGET_WDATA_6,
+	PMIF_MONITOR_TARGET_WDATA_7,
+	PMIF_MONITOR_STA,
+	PMIF_MONITOR_RECORD_0_0,
+	PMIF_MONITOR_RECORD_0_1,
+	PMIF_MONITOR_RECORD_0_2,
+	PMIF_MONITOR_RECORD_0_3,
+	PMIF_MONITOR_RECORD_0_4,
+	PMIF_MONITOR_RECORD_1_0,
+	PMIF_MONITOR_RECORD_1_1,
+	PMIF_MONITOR_RECORD_1_2,
+	PMIF_MONITOR_RECORD_1_3,
+	PMIF_MONITOR_RECORD_1_4,
+	PMIF_MONITOR_RECORD_2_0,
+	PMIF_MONITOR_RECORD_2_1,
+	PMIF_MONITOR_RECORD_2_2,
+	PMIF_MONITOR_RECORD_2_3,
+	PMIF_MONITOR_RECORD_2_4,
+	PMIF_MONITOR_RECORD_3_0,
+	PMIF_MONITOR_RECORD_3_1,
+	PMIF_MONITOR_RECORD_3_2,
+	PMIF_MONITOR_RECORD_3_3,
+	PMIF_MONITOR_RECORD_3_4,
+	PMIF_MONITOR_RECORD_4_0,
+	PMIF_MONITOR_RECORD_4_1,
+	PMIF_MONITOR_RECORD_4_2,
+	PMIF_MONITOR_RECORD_4_3,
+	PMIF_MONITOR_RECORD_4_4,
+	PMIF_MONITOR_RECORD_5_0,
+	PMIF_MONITOR_RECORD_5_1,
+	PMIF_MONITOR_RECORD_5_2,
+	PMIF_MONITOR_RECORD_5_3,
+	PMIF_MONITOR_RECORD_5_4,
+	PMIF_MONITOR_RECORD_6_0,
+	PMIF_MONITOR_RECORD_6_1,
+	PMIF_MONITOR_RECORD_6_2,
+	PMIF_MONITOR_RECORD_6_3,
+	PMIF_MONITOR_RECORD_6_4,
+	PMIF_MONITOR_RECORD_7_0,
+	PMIF_MONITOR_RECORD_7_1,
+	PMIF_MONITOR_RECORD_7_2,
+	PMIF_MONITOR_RECORD_7_3,
+	PMIF_MONITOR_RECORD_7_4,
+	PMIF_MONITOR_RECORD_8_0,
+	PMIF_MONITOR_RECORD_8_1,
+	PMIF_MONITOR_RECORD_8_2,
+	PMIF_MONITOR_RECORD_8_3,
+	PMIF_MONITOR_RECORD_8_4,
+	PMIF_MONITOR_RECORD_9_0,
+	PMIF_MONITOR_RECORD_9_1,
+	PMIF_MONITOR_RECORD_9_2,
+	PMIF_MONITOR_RECORD_9_3,
+	PMIF_MONITOR_RECORD_9_4,
+	PMIF_MONITOR_RECORD_10_0,
+	PMIF_MONITOR_RECORD_10_1,
+	PMIF_MONITOR_RECORD_10_2,
+	PMIF_MONITOR_RECORD_10_3,
+	PMIF_MONITOR_RECORD_10_4,
+	PMIF_MONITOR_RECORD_11_0,
+	PMIF_MONITOR_RECORD_11_1,
+	PMIF_MONITOR_RECORD_11_2,
+	PMIF_MONITOR_RECORD_11_3,
+	PMIF_MONITOR_RECORD_11_4,
+	PMIF_MONITOR_RECORD_12_0,
+	PMIF_MONITOR_RECORD_12_1,
+	PMIF_MONITOR_RECORD_12_2,
+	PMIF_MONITOR_RECORD_12_3,
+	PMIF_MONITOR_RECORD_12_4,
+	PMIF_MONITOR_RECORD_13_0,
+	PMIF_MONITOR_RECORD_13_1,
+	PMIF_MONITOR_RECORD_13_2,
+	PMIF_MONITOR_RECORD_13_3,
+	PMIF_MONITOR_RECORD_13_4,
+	PMIF_MONITOR_RECORD_14_0,
+	PMIF_MONITOR_RECORD_14_1,
+	PMIF_MONITOR_RECORD_14_2,
+	PMIF_MONITOR_RECORD_14_3,
+	PMIF_MONITOR_RECORD_14_4,
+	PMIF_MONITOR_RECORD_15_0,
+	PMIF_MONITOR_RECORD_15_1,
+	PMIF_MONITOR_RECORD_15_2,
+	PMIF_MONITOR_RECORD_15_3,
+	PMIF_MONITOR_RECORD_15_4,
+	PMIF_MONITOR_RECORD_16_0,
+	PMIF_MONITOR_RECORD_16_1,
+	PMIF_MONITOR_RECORD_16_2,
+	PMIF_MONITOR_RECORD_16_3,
+	PMIF_MONITOR_RECORD_16_4,
+	PMIF_MONITOR_RECORD_17_0,
+	PMIF_MONITOR_RECORD_17_1,
+	PMIF_MONITOR_RECORD_17_2,
+	PMIF_MONITOR_RECORD_17_3,
+	PMIF_MONITOR_RECORD_17_4,
+	PMIF_MONITOR_RECORD_18_0,
+	PMIF_MONITOR_RECORD_18_1,
+	PMIF_MONITOR_RECORD_18_2,
+	PMIF_MONITOR_RECORD_18_3,
+	PMIF_MONITOR_RECORD_18_4,
+	PMIF_MONITOR_RECORD_19_0,
+	PMIF_MONITOR_RECORD_19_1,
+	PMIF_MONITOR_RECORD_19_2,
+	PMIF_MONITOR_RECORD_19_3,
+	PMIF_MONITOR_RECORD_19_4,
+	PMIF_MONITOR_RECORD_20_0,
+	PMIF_MONITOR_RECORD_20_1,
+	PMIF_MONITOR_RECORD_20_2,
+	PMIF_MONITOR_RECORD_20_3,
+	PMIF_MONITOR_RECORD_20_4,
+	PMIF_MONITOR_RECORD_21_0,
+	PMIF_MONITOR_RECORD_21_1,
+	PMIF_MONITOR_RECORD_21_2,
+	PMIF_MONITOR_RECORD_21_3,
+	PMIF_MONITOR_RECORD_21_4,
+	PMIF_MONITOR_RECORD_22_0,
+	PMIF_MONITOR_RECORD_22_1,
+	PMIF_MONITOR_RECORD_22_2,
+	PMIF_MONITOR_RECORD_22_3,
+	PMIF_MONITOR_RECORD_22_4,
+	PMIF_MONITOR_RECORD_23_0,
+	PMIF_MONITOR_RECORD_23_1,
+	PMIF_MONITOR_RECORD_23_2,
+	PMIF_MONITOR_RECORD_23_3,
+	PMIF_MONITOR_RECORD_23_4,
+	PMIF_MONITOR_RECORD_24_0,
+	PMIF_MONITOR_RECORD_24_1,
+	PMIF_MONITOR_RECORD_24_2,
+	PMIF_MONITOR_RECORD_24_3,
+	PMIF_MONITOR_RECORD_24_4,
+	PMIF_MONITOR_RECORD_25_0,
+	PMIF_MONITOR_RECORD_25_1,
+	PMIF_MONITOR_RECORD_25_2,
+	PMIF_MONITOR_RECORD_25_3,
+	PMIF_MONITOR_RECORD_25_4,
+	PMIF_MONITOR_RECORD_26_0,
+	PMIF_MONITOR_RECORD_26_1,
+	PMIF_MONITOR_RECORD_26_2,
+	PMIF_MONITOR_RECORD_26_3,
+	PMIF_MONITOR_RECORD_26_4,
+	PMIF_MONITOR_RECORD_27_0,
+	PMIF_MONITOR_RECORD_27_1,
+	PMIF_MONITOR_RECORD_27_2,
+	PMIF_MONITOR_RECORD_27_3,
+	PMIF_MONITOR_RECORD_27_4,
+	PMIF_MONITOR_RECORD_28_0,
+	PMIF_MONITOR_RECORD_28_1,
+	PMIF_MONITOR_RECORD_28_2,
+	PMIF_MONITOR_RECORD_28_3,
+	PMIF_MONITOR_RECORD_28_4,
+	PMIF_MONITOR_RECORD_29_0,
+	PMIF_MONITOR_RECORD_29_1,
+	PMIF_MONITOR_RECORD_29_2,
+	PMIF_MONITOR_RECORD_29_3,
+	PMIF_MONITOR_RECORD_29_4,
+	PMIF_MONITOR_RECORD_30_0,
+	PMIF_MONITOR_RECORD_30_1,
+	PMIF_MONITOR_RECORD_30_2,
+	PMIF_MONITOR_RECORD_30_3,
+	PMIF_MONITOR_RECORD_30_4,
+	PMIF_MONITOR_RECORD_31_0,
+	PMIF_MONITOR_RECORD_31_1,
+	PMIF_MONITOR_RECORD_31_2,
+	PMIF_MONITOR_RECORD_31_3,
+	PMIF_MONITOR_RECORD_31_4,
+	PMIF_DEBUG_CTRL,
+	PMIF_RESERVED_0,
+	PMIF_SWINF_0_ACC,
+	PMIF_SWINF_0_WDATA_31_0,
+	PMIF_SWINF_0_WDATA_63_32,
+	PMIF_SWINF_0_RDATA_31_0,
+	PMIF_SWINF_0_RDATA_63_32,
+	PMIF_SWINF_0_VLD_CLR,
+	PMIF_SWINF_0_STA,
+	PMIF_SWINF_1_ACC,
+	PMIF_SWINF_1_WDATA_31_0,
+	PMIF_SWINF_1_WDATA_63_32,
+	PMIF_SWINF_1_RDATA_31_0,
+	PMIF_SWINF_1_RDATA_63_32,
+	PMIF_SWINF_1_VLD_CLR,
+	PMIF_SWINF_1_STA,
+	PMIF_SWINF_2_ACC,
+	PMIF_SWINF_2_WDATA_31_0,
+	PMIF_SWINF_2_WDATA_63_32,
+	PMIF_SWINF_2_RDATA_31_0,
+	PMIF_SWINF_2_RDATA_63_32,
+	PMIF_SWINF_2_VLD_CLR,
+	PMIF_SWINF_2_STA,
+	PMIF_SWINF_3_ACC,
+	PMIF_SWINF_3_WDATA_31_0,
+	PMIF_SWINF_3_WDATA_63_32,
+	PMIF_SWINF_3_RDATA_31_0,
+	PMIF_SWINF_3_RDATA_63_32,
+	PMIF_SWINF_3_VLD_CLR,
+	PMIF_SWINF_3_STA,
+};
+
+static int mt6xxx_pmif_dbg_regs[] = {
+	[PMIF_INIT_DONE] =			0x0000,
+	[PMIF_INF_BUSY_STA] =			0x0018,
+	[PMIF_OTHER_BUSY_STA_0] =		0x001C,
+	[PMIF_OTHER_BUSY_STA_1] =		0x0020,
+	[PMIF_IRQ_EVENT_EN_0] =                 0x0418,
+	[PMIF_IRQ_FLAG_0] =                     0x0420,
+	[PMIF_IRQ_CLR_0] =                      0x0424,
+	[PMIF_IRQ_EVENT_EN_1] =                 0x0428,
+	[PMIF_IRQ_FLAG_1] =                     0x0430,
+	[PMIF_IRQ_CLR_1] =                      0x0434,
+	[PMIF_IRQ_EVENT_EN_2] =                 0x0438,
+	[PMIF_IRQ_FLAG_2] =                     0x0440,
+	[PMIF_IRQ_CLR_2] =                      0x0444,
+	[PMIF_IRQ_EVENT_EN_3] =                 0x0448,
+	[PMIF_IRQ_FLAG_3] =                     0x0450,
+	[PMIF_IRQ_CLR_3] =                      0x0454,
+	[PMIF_IRQ_EVENT_EN_4] =                 0x0458,
+	[PMIF_IRQ_FLAG_4] =                     0x0460,
+	[PMIF_IRQ_CLR_4] =                      0x0464,
+	[PMIF_WDT_EVENT_EN_0] =			0x046C,
+	[PMIF_WDT_FLAG_0] =			0x0470,
+	[PMIF_WDT_EVENT_EN_1] =         	0x0474,
+	[PMIF_WDT_FLAG_1] =			0x0478,
+	[PMIF_MONITOR_CTRL] =           	0x047C,
+	[PMIF_MONITOR_TARGET_CHAN_0] =  	0x0480,
+	[PMIF_MONITOR_TARGET_CHAN_1] =  	0x0484,
+	[PMIF_MONITOR_TARGET_CHAN_2] =  	0x0488,
+	[PMIF_MONITOR_TARGET_CHAN_3] =  	0x048C,
+	[PMIF_MONITOR_TARGET_CHAN_4] =  	0x0490,
+	[PMIF_MONITOR_TARGET_CHAN_5] =  	0x0494,
+	[PMIF_MONITOR_TARGET_CHAN_6] =  	0x0498,
+	[PMIF_MONITOR_TARGET_CHAN_7] =  	0x049C,
+	[PMIF_MONITOR_TARGET_WRITE] =   	0x04A0,
+	[PMIF_MONITOR_TARGET_ADDR_0] =  	0x04A4,
+	[PMIF_MONITOR_TARGET_ADDR_1] =  	0x04A8,
+	[PMIF_MONITOR_TARGET_ADDR_2] =  	0x04AC,
+	[PMIF_MONITOR_TARGET_ADDR_3] =  	0x04B0,
+	[PMIF_MONITOR_TARGET_ADDR_4] =  	0x04B4,
+	[PMIF_MONITOR_TARGET_ADDR_5] =  	0x04B8,
+	[PMIF_MONITOR_TARGET_ADDR_6] =  	0x04BC,
+	[PMIF_MONITOR_TARGET_ADDR_7] =  	0x04C0,
+	[PMIF_MONITOR_TARGET_WDATA_0] = 	0x04C4,
+	[PMIF_MONITOR_TARGET_WDATA_1] = 	0x04C8,
+	[PMIF_MONITOR_TARGET_WDATA_2] = 	0x04CC,
+	[PMIF_MONITOR_TARGET_WDATA_3] = 	0x04D0,
+	[PMIF_MONITOR_TARGET_WDATA_4] = 	0x04D4,
+	[PMIF_MONITOR_TARGET_WDATA_5] = 	0x04D8,
+	[PMIF_MONITOR_TARGET_WDATA_6] = 	0x04DC,
+	[PMIF_MONITOR_TARGET_WDATA_7] = 	0x04E0,
+	[PMIF_MONITOR_STA] =            	0x04E4,
+	[PMIF_MONITOR_RECORD_0_0] =     	0x04E8,
+	[PMIF_MONITOR_RECORD_0_1] =     	0x04EC,
+	[PMIF_MONITOR_RECORD_0_2] =     	0x04F0,
+	[PMIF_MONITOR_RECORD_0_3] =     	0x04F4,
+	[PMIF_MONITOR_RECORD_0_4] =     	0x04F8,
+	[PMIF_MONITOR_RECORD_1_0] =     	0x04FC,
+	[PMIF_MONITOR_RECORD_1_1] =     	0x0500,
+	[PMIF_MONITOR_RECORD_1_2] =     	0x0504,
+	[PMIF_MONITOR_RECORD_1_3] =     	0x0508,
+	[PMIF_MONITOR_RECORD_1_4] =     	0x050C,
+	[PMIF_MONITOR_RECORD_2_0] =     	0x0510,
+	[PMIF_MONITOR_RECORD_2_1] =     	0x0514,
+	[PMIF_MONITOR_RECORD_2_2] =     	0x0518,
+	[PMIF_MONITOR_RECORD_2_3] =     	0x051C,
+	[PMIF_MONITOR_RECORD_2_4] =     	0x0520,
+	[PMIF_MONITOR_RECORD_3_0] =     	0x0524,
+	[PMIF_MONITOR_RECORD_3_1] =     	0x0528,
+	[PMIF_MONITOR_RECORD_3_2] =     	0x052C,
+	[PMIF_MONITOR_RECORD_3_3] =     	0x0530,
+	[PMIF_MONITOR_RECORD_3_4] =     	0x0534,
+	[PMIF_MONITOR_RECORD_4_0] =     	0x0538,
+	[PMIF_MONITOR_RECORD_4_1] =     	0x053C,
+	[PMIF_MONITOR_RECORD_4_2] =     	0x0540,
+	[PMIF_MONITOR_RECORD_4_3] =     	0x0544,
+	[PMIF_MONITOR_RECORD_4_4] =     	0x0548,
+	[PMIF_MONITOR_RECORD_5_0] =     	0x054C,
+	[PMIF_MONITOR_RECORD_5_1] =     	0x0550,
+	[PMIF_MONITOR_RECORD_5_2] =     	0x0554,
+	[PMIF_MONITOR_RECORD_5_3] =     	0x0558,
+	[PMIF_MONITOR_RECORD_5_4] =     	0x055C,
+	[PMIF_MONITOR_RECORD_6_0] =     	0x0560,
+	[PMIF_MONITOR_RECORD_6_1] =     	0x0564,
+	[PMIF_MONITOR_RECORD_6_2] =     	0x0568,
+	[PMIF_MONITOR_RECORD_6_3] =     	0x056C,
+	[PMIF_MONITOR_RECORD_6_4] =     	0x0570,
+	[PMIF_MONITOR_RECORD_7_0] =     	0x0574,
+	[PMIF_MONITOR_RECORD_7_1] =     	0x0578,
+	[PMIF_MONITOR_RECORD_7_2] =     	0x057C,
+	[PMIF_MONITOR_RECORD_7_3] =     	0x0580,
+	[PMIF_MONITOR_RECORD_7_4] =		0x0584,
+	[PMIF_MONITOR_RECORD_8_0] =	     	0x0588,
+	[PMIF_MONITOR_RECORD_8_1] =     	0x058C,
+	[PMIF_MONITOR_RECORD_8_2] =     	0x0590,
+	[PMIF_MONITOR_RECORD_8_3] =     	0x0594,
+	[PMIF_MONITOR_RECORD_8_4] =     	0x0598,
+	[PMIF_MONITOR_RECORD_9_0] =     	0x059C,
+	[PMIF_MONITOR_RECORD_9_1] =     	0x05A0,
+	[PMIF_MONITOR_RECORD_9_2] =     	0x05A4,
+	[PMIF_MONITOR_RECORD_9_3] =     	0x05A8,
+	[PMIF_MONITOR_RECORD_9_4] =     	0x05AC,
+	[PMIF_MONITOR_RECORD_10_0] =    	0x05B0,
+	[PMIF_MONITOR_RECORD_10_1] =    	0x05B4,
+	[PMIF_MONITOR_RECORD_10_2] =    	0x05B8,
+	[PMIF_MONITOR_RECORD_10_3] =    	0x05BC,
+	[PMIF_MONITOR_RECORD_10_4] =    	0x05C0,
+	[PMIF_MONITOR_RECORD_11_0] =    	0x05C4,
+	[PMIF_MONITOR_RECORD_11_1] =    	0x05C8,
+	[PMIF_MONITOR_RECORD_11_2] =    	0x05CC,
+	[PMIF_MONITOR_RECORD_11_3] =    	0x05D0,
+	[PMIF_MONITOR_RECORD_11_4] =    	0x05D4,
+	[PMIF_MONITOR_RECORD_12_0] =    	0x05D8,
+	[PMIF_MONITOR_RECORD_12_1] =    	0x05DC,
+	[PMIF_MONITOR_RECORD_12_2] =    	0x05E0,
+	[PMIF_MONITOR_RECORD_12_3] =    	0x05E4,
+	[PMIF_MONITOR_RECORD_12_4] =    	0x05E8,
+	[PMIF_MONITOR_RECORD_13_0] =    	0x05EC,
+	[PMIF_MONITOR_RECORD_13_1] =    	0x05F0,
+	[PMIF_MONITOR_RECORD_13_2] =    	0x05F4,
+	[PMIF_MONITOR_RECORD_13_3] =    	0x05F8,
+	[PMIF_MONITOR_RECORD_13_4] =    	0x05FC,
+	[PMIF_MONITOR_RECORD_14_0] =    	0x0600,
+	[PMIF_MONITOR_RECORD_14_1] =    	0x0604,
+	[PMIF_MONITOR_RECORD_14_2] =    	0x0608,
+	[PMIF_MONITOR_RECORD_14_3] =    	0x060C,
+	[PMIF_MONITOR_RECORD_14_4] =    	0x0610,
+	[PMIF_MONITOR_RECORD_15_0] =    	0x0614,
+	[PMIF_MONITOR_RECORD_15_1] =    	0x0618,
+	[PMIF_MONITOR_RECORD_15_2] =    	0x061C,
+	[PMIF_MONITOR_RECORD_15_3] =    	0x0620,
+	[PMIF_MONITOR_RECORD_15_4] =    	0x0624,
+	[PMIF_MONITOR_RECORD_16_0] =    	0x0628,
+	[PMIF_MONITOR_RECORD_16_1] =    	0x062C,
+	[PMIF_MONITOR_RECORD_16_2] =    	0x0630,
+	[PMIF_MONITOR_RECORD_16_3] =    	0x0634,
+	[PMIF_MONITOR_RECORD_16_4] =    	0x0638,
+	[PMIF_MONITOR_RECORD_17_0] =    	0x063C,
+	[PMIF_MONITOR_RECORD_17_1] =    	0x0640,
+	[PMIF_MONITOR_RECORD_17_2] =    	0x0644,
+	[PMIF_MONITOR_RECORD_17_3] =    	0x0648,
+	[PMIF_MONITOR_RECORD_17_4] =    	0x064C,
+	[PMIF_MONITOR_RECORD_18_0] =    	0x0650,
+	[PMIF_MONITOR_RECORD_18_1] =    	0x0654,
+	[PMIF_MONITOR_RECORD_18_2] =    	0x0658,
+	[PMIF_MONITOR_RECORD_18_3] =    	0x065C,
+	[PMIF_MONITOR_RECORD_18_4] =    	0x0660,
+	[PMIF_MONITOR_RECORD_19_0] =    	0x0664,
+	[PMIF_MONITOR_RECORD_19_1] =    	0x0668,
+	[PMIF_MONITOR_RECORD_19_2] =    	0x066C,
+	[PMIF_MONITOR_RECORD_19_3] =    	0x0670,
+	[PMIF_MONITOR_RECORD_19_4] =    	0x0674,
+	[PMIF_MONITOR_RECORD_20_0] =    	0x0678,
+	[PMIF_MONITOR_RECORD_20_1] =    	0x067C,
+	[PMIF_MONITOR_RECORD_20_2] =    	0x0680,
+	[PMIF_MONITOR_RECORD_20_3] =    	0x0684,
+	[PMIF_MONITOR_RECORD_20_4] =    	0x0688,
+	[PMIF_MONITOR_RECORD_21_0] =    	0x068C,
+	[PMIF_MONITOR_RECORD_21_1] =    	0x0690,
+	[PMIF_MONITOR_RECORD_21_2] =    	0x0694,
+	[PMIF_MONITOR_RECORD_21_3] =    	0x0698,
+	[PMIF_MONITOR_RECORD_21_4] =    	0x069C,
+	[PMIF_MONITOR_RECORD_22_0] =    	0x06A0,
+	[PMIF_MONITOR_RECORD_22_1] =    	0x06A4,
+	[PMIF_MONITOR_RECORD_22_2] =    	0x06A8,
+	[PMIF_MONITOR_RECORD_22_3] =    	0x06AC,
+	[PMIF_MONITOR_RECORD_22_4] =    	0x06B0,
+	[PMIF_MONITOR_RECORD_23_0] =    	0x06B4,
+	[PMIF_MONITOR_RECORD_23_1] =    	0x06B8,
+	[PMIF_MONITOR_RECORD_23_2] =    	0x06BC,
+	[PMIF_MONITOR_RECORD_23_3] =    	0x06C0,
+	[PMIF_MONITOR_RECORD_23_4] =    	0x06C4,
+	[PMIF_MONITOR_RECORD_24_0] =    	0x06C8,
+	[PMIF_MONITOR_RECORD_24_1] =    	0x06CC,
+	[PMIF_MONITOR_RECORD_24_2] =    	0x06D0,
+	[PMIF_MONITOR_RECORD_24_3] =    	0x06D4,
+	[PMIF_MONITOR_RECORD_24_4] =    	0x06D8,
+	[PMIF_MONITOR_RECORD_25_0] =    	0x06DC,
+	[PMIF_MONITOR_RECORD_25_1] =    	0x06E0,
+	[PMIF_MONITOR_RECORD_25_2] =    	0x06E4,
+	[PMIF_MONITOR_RECORD_25_3] =    	0x06E8,
+	[PMIF_MONITOR_RECORD_25_4] =    	0x06EC,
+	[PMIF_MONITOR_RECORD_26_0] =    	0x06F0,
+	[PMIF_MONITOR_RECORD_26_1] =    	0x06F4,
+	[PMIF_MONITOR_RECORD_26_2] =    	0x06F8,
+	[PMIF_MONITOR_RECORD_26_3] =    	0x06FC,
+	[PMIF_MONITOR_RECORD_26_4] =    	0x0700,
+	[PMIF_MONITOR_RECORD_27_0] =    	0x0704,
+	[PMIF_MONITOR_RECORD_27_1] =    	0x0708,
+	[PMIF_MONITOR_RECORD_27_2] =    	0x070C,
+	[PMIF_MONITOR_RECORD_27_3] =    	0x0710,
+	[PMIF_MONITOR_RECORD_27_4] =    	0x0714,
+	[PMIF_MONITOR_RECORD_28_0] =    	0x0718,
+	[PMIF_MONITOR_RECORD_28_1] =    	0x071C,
+	[PMIF_MONITOR_RECORD_28_2] =    	0x0720,
+	[PMIF_MONITOR_RECORD_28_3] =    	0x0724,
+	[PMIF_MONITOR_RECORD_28_4] =    	0x0728,
+	[PMIF_MONITOR_RECORD_29_0] =    	0x072C,
+	[PMIF_MONITOR_RECORD_29_1] =    	0x0730,
+	[PMIF_MONITOR_RECORD_29_2] =    	0x0734,
+	[PMIF_MONITOR_RECORD_29_3] =    	0x0738,
+	[PMIF_MONITOR_RECORD_29_4] =    	0x073C,
+	[PMIF_MONITOR_RECORD_30_0] =    	0x0740,
+	[PMIF_MONITOR_RECORD_30_1] =    	0x0744,
+	[PMIF_MONITOR_RECORD_30_2] =    	0x0748,
+	[PMIF_MONITOR_RECORD_30_3] =    	0x074C,
+	[PMIF_MONITOR_RECORD_30_4] =    	0x0750,
+	[PMIF_MONITOR_RECORD_31_0] =    	0x0754,
+	[PMIF_MONITOR_RECORD_31_1] =    	0x0758,
+	[PMIF_MONITOR_RECORD_31_2] =    	0x075C,
+	[PMIF_MONITOR_RECORD_31_3] =    	0x0760,
+	[PMIF_MONITOR_RECORD_31_4] =    	0x0764,
+	[PMIF_DEBUG_CTRL] =			0x0768,
+	[PMIF_RESERVED_0] =			0x0770,
+	[PMIF_SWINF_0_ACC] =			0x0C00,
+	[PMIF_SWINF_0_WDATA_31_0] =		0x0C04,
+	[PMIF_SWINF_0_WDATA_63_32] =		0x0C08,
+	[PMIF_SWINF_0_RDATA_31_0] =		0x0C14,
+	[PMIF_SWINF_0_RDATA_63_32] =		0x0C18,
+	[PMIF_SWINF_0_VLD_CLR] =		0x0C24,
+	[PMIF_SWINF_0_STA] =			0x0C28,
+	[PMIF_SWINF_1_ACC] =			0x0C40,
+	[PMIF_SWINF_1_WDATA_31_0] =		0x0C44,
+	[PMIF_SWINF_1_WDATA_63_32] =		0x0C48,
+	[PMIF_SWINF_1_RDATA_31_0] =		0x0C54,
+	[PMIF_SWINF_1_RDATA_63_32] =		0x0C58,
+	[PMIF_SWINF_1_VLD_CLR] =		0x0C64,
+	[PMIF_SWINF_1_STA] =			0x0C68,
+	[PMIF_SWINF_2_ACC] =			0x0C80,
+	[PMIF_SWINF_2_WDATA_31_0] =		0x0C84,
+	[PMIF_SWINF_2_WDATA_63_32] =		0x0C88,
+	[PMIF_SWINF_2_RDATA_31_0] =		0x0C94,
+	[PMIF_SWINF_2_RDATA_63_32] =		0x0C98,
+	[PMIF_SWINF_2_VLD_CLR] =		0x0CA4,
+	[PMIF_SWINF_2_STA] =			0x0CA8,
+	[PMIF_SWINF_3_ACC] =			0x0CC0,
+	[PMIF_SWINF_3_WDATA_31_0] =		0x0CC4,
+	[PMIF_SWINF_3_WDATA_63_32] =		0x0CC8,
+	[PMIF_SWINF_3_RDATA_31_0] =		0x0CD4,
+	[PMIF_SWINF_3_RDATA_63_32] =		0x0CD8,
+	[PMIF_SWINF_3_VLD_CLR] =		0x0CE4,
+	[PMIF_SWINF_3_STA] =			0x0CE8,
+};
+#if SPMI_KERNEL
+static unsigned char spmi_pmif_log_buf[1280];
+#endif
+
+/* spmi & pmif debug mechanism */
+void spmi_dump_pmif_busy_reg(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int i = 0, offset = 0, tmp_dat = 0;
+	unsigned int start = 0, end = 0;
+
+	start = arb->dbgregs[PMIF_INF_BUSY_STA]/4;
+	end = arb->dbgregs[PMIF_OTHER_BUSY_STA_1]/4;
+
+	PMIF_CRI("");
+	for (i = start; i <= end; i++) {
+		offset = arb->dbgregs[PMIF_INF_BUSY_STA] + (i * 4);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		PMIF_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
+
+		if (i == 0)
+			continue;
+	}
+	PMIF_CRIL("\r\n");
+	spmi_dump_pmif_swinf_reg(mstid);
+
+}
+void spmi_dump_pmif_swinf_reg(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int i = 0, offset = 0, j = 0, tmp_dat = 0;
+	unsigned int swinf[4] = {0}, cmd[4] = {0}, rw[4] = {0};
+	unsigned int slvid[4] = {0}, bytecnt[4] = {0}, adr[4] = {0};
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+	unsigned int wd_31_0[4] = {0}, rd_31_0[4] = {0};
+	unsigned int err[4] = {0}, sbusy[4] = {0}, done[4] = {0};
+	unsigned int qfillcnt[4] = {0}, qfreecnt[4] = {0}, qempty[4] = {0};
+	unsigned int qfull[4] = {0}, req[4] = {0}, fsm[4] = {0}, en[4] = {0};
+
+	for (i = 0; i < 4; i++) {
+		offset = arb->dbgregs[PMIF_SWINF_0_ACC] + (i * 0x40);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		swinf[j] = i;
+		cmd[j] = (tmp_dat & (0x3 << 30)) >> 30;
+		rw[j] = (tmp_dat & (0x1 << 29)) >> 29;
+		slvid[j] = (tmp_dat & (0xf << 24)) >> 24;
+		bytecnt[j] = (tmp_dat & (0xf << 16)) >> 16;
+		adr[j] = (tmp_dat & (0xffff << 0)) >> 0;
+		j += 1;
+	}
+	j = 0;
+	for (i = 0; i < 4; i++) {
+		offset = arb->dbgregs[PMIF_SWINF_0_WDATA_31_0] + (i * 0x40);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		wd_31_0[j] = tmp_dat;
+		j += 1;
+	}
+	j = 0;
+	for (i = 0; i < 4; i++) {
+		offset = arb->dbgregs[PMIF_SWINF_0_RDATA_31_0] + (i * 0x40);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		rd_31_0[j] = tmp_dat;
+		j += 1;
+	}
+	j = 0;
+	for (i = 0; i < 4; i++) {
+		offset = arb->dbgregs[PMIF_SWINF_0_STA] + (i * 0x40);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		err[j] = (tmp_dat & (0x1 << 18)) >> 18;
+		sbusy[j] = (tmp_dat & (0x1 << 17)) >> 17;
+		done[j] = (tmp_dat & (0x1 << 15)) >> 15;
+		qfillcnt[j] = (tmp_dat & (0xf << 11)) >> 11;
+		qfreecnt[j] = (tmp_dat & (0xf << 7)) >> 7;
+		qempty[j] = (tmp_dat & (0x1 << 6)) >> 6;
+		qfull[j] = (tmp_dat & (0x1 << 5)) >> 5;
+		req[j] = (tmp_dat & (0x1 << 4)) >> 4;
+		fsm[j] = (tmp_dat & (0x7 << 1)) >> 1;
+		en[j] = (tmp_dat & (0x1 << 0)) >> 0;
+		j += 1;
+	}
+	for (i = 0; i < 4; i++) {
+		if (rw[i] == 0) {
+			PMIF_CRI("[swinf:%d, cmd:0x%x, rw:0x%x, slvid:%d ",
+				swinf[i], cmd[i], rw[i], slvid[i]);
+			PMIF_CRIL("bytecnt:%d (read adr 0x%04x=0x%x)]\r\n",
+				bytecnt[i], adr[i], rd_31_0[i]);
+			PMIF_CRI("[err:%d, sbusy:%d, done:%d, qfillcnt:%d ",
+				err[i], sbusy[i], done[i], qfillcnt[i]);
+			PMIF_CRIL("qfreecnt:%d, qempty:%d, qfull:%d, req:%d ",
+				qfreecnt[i], qempty[i], qfull[i], req[i]);
+			PMIF_CRIL("fsm:%d, en:%d]\r\n", fsm[i], en[i]);
+		} else {
+			PMIF_CRI("[swinf:%d, cmd:0x%x, rw:0x%x, slvid:%d ",
+				swinf[i], cmd[i], rw[i], slvid[i]);
+			PMIF_CRIL("bytecnt:%d (write adr 0x%04x=0x%x)]\r\n",
+				bytecnt[i], adr[i], wd_31_0[i]);
+			PMIF_CRI("[err:%d, sbusy:%d, done:%d, qfillcnt:%d ",
+				err[i], sbusy[i], done[i], qfillcnt[i]);
+			PMIF_CRIL("qfreecnt:%d, qempty:%d, qfull:%d, req:%d ",
+				qfreecnt[i], qempty[i], qfull[i], req[i]);
+			PMIF_CRIL("fsm:%d, en:%d]\r\n", fsm[i], en[i]);
+		}
+	}
+}
+
+void spmi_dump_pmif_reg(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int i = 0, offset = 0, tmp_dat = 0;
+	unsigned int start = 0, end = 0;
+
+	start = arb->dbgregs[PMIF_INIT_DONE]/4;
+	end = arb->dbgregs[PMIF_RESERVED_0]/4;
+
+	PMIF_CRI("");
+	for (i = start; i <= end; i++) {
+		offset = arb->dbgregs[PMIF_INIT_DONE] + (i * 4);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		PMIF_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
+
+		if (i == 0)
+			continue;
+		if (i % 8 == 0) {
+			PMIF_CRIL("\r\n[PMIF] ");
+		}
+	}
+	PMIF_CRIL("\r\n");
+	spmi_dump_pmif_swinf_reg(mstid);
+}
+
+void spmi_dump_pmif_record_reg(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int i = 0, offset = 0, j = 0, tmp_dat = 0;
+	unsigned int chan[32] = {0}, cmd[32] = {0}, rw[32] = {0};
+	unsigned int slvid[32] = {0}, bytecnt[32] = {0}, adr[32] = {0};
+#if 0
+/* under construction !*/
+#endif
+	unsigned int wd_31_0[32] = {0};
+
+	for (i = 0; i < 32; i++) {
+		offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_0] + (i * 0x14);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		chan[j] = (tmp_dat & (0xf8000000)) >> 27;
+		cmd[j] = (tmp_dat & (0x3 << 25)) >> 25;
+		rw[j] = (tmp_dat & (0x1 << 24)) >> 24;
+		slvid[j] = (tmp_dat & (0xf << 20)) >> 20;
+		bytecnt[j] = (tmp_dat & (0xf << 16)) >> 16;
+		adr[j] = (tmp_dat & (0xffff << 0)) >> 0;
+		j += 1;
+	}
+	j = 0;
+	for (i = 0; i < 32; i++) {
+		offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_1] + (i * 0x14);
+		tmp_dat = DRV_Reg32(arb->base + offset);
+		wd_31_0[j] = tmp_dat;
+		j += 1;
+	}
+
+	for (i = 0; i < 32; i++) {
+		SPMI_CRI("[swinf:%d, cmd:0x%x, rw:0x%x, slvid:%d ",
+			chan[i], cmd[i], rw[i], slvid[i]);
+		SPMI_CRIL("bytecnt:%d (adr 0x%04x=0x%x)]\r\n",
+			bytecnt[i], adr[i], wd_31_0[i]);
+	}
+	spmi_dump_pmif_swinf_reg(mstid);
+
+	/* clear record data and re-enable */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x800);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x5);
+}
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif
+void spmi_dump_spmimst_reg(int mstid)
+{
+	struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
+	unsigned int i = 0, offset = 0, tmp_dat = 0;
+	unsigned int start = 0, end = 0;
+
+	start = arb->spmimst_regs[SPMI_OP_ST_CTRL]/4;
+	end = arb->spmimst_regs[SPMI_REC4]/4;
+
+	SPMI_CRI("");
+	for (i = start; i <= end; i++) {
+		offset = arb->spmimst_regs[SPMI_OP_ST_CTRL] + (i * 4);
+		tmp_dat = DRV_Reg32(arb->spmimst_base + offset);
+		SPMI_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
+
+		if (i == 0)
+			continue;
+		if (i % 8 == 0) {
+			SPMI_CRIL("\r\n[SPMI] ");
+		}
+	}
+#if SPMI_RCS_SUPPORT
+	offset = arb->spmimst_regs[SPMI_DEC_DBG];
+	tmp_dat = DRV_Reg32(arb->spmimst_base + offset);
+	SPMI_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
+#endif
+	offset = arb->spmimst_regs[SPMI_MST_DBG];
+	tmp_dat = DRV_Reg32(arb->spmimst_base + offset);
+	SPMI_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
+	SPMI_CRIL("\r\n");
+}
+
+void spmi_dump_slv_record_reg(struct spmi_device *dev)
+{
+	unsigned char rdata1 = 0, rdata2 = 0, rdata3 = 0, rdata4 = 0;
+	unsigned int offset, i, j = 0;
+
+	/* log sequence, idx 0->1->2->3->0 */
+	for (offset = 0x34; offset < 0x50; offset += 4)
+	{
+		spmi_ext_register_readl(dev,
+			(MT6315_PLT0_ID_ANA_ID + offset), &rdata1, 1);
+		spmi_ext_register_readl(dev,
+			(MT6315_PLT0_ID_ANA_ID + offset + 1), &rdata2, 1);
+		spmi_ext_register_readl(dev,
+			(MT6315_PLT0_ID_ANA_ID + offset + 2), &rdata3, 1);
+		spmi_ext_register_readl(dev,
+			(MT6315_PLT0_ID_ANA_ID + offset + 3), &rdata4, 1);
+		if ((offset + 3) == 0x37) {
+			i = (rdata4 & 0xc) >> 2;
+			if (i == 0)
+				SPMI_CRI("slvid:%d DBG. Last cmd idx:0x3\r\n",
+					dev->slvid);
+			else {
+				SPMI_CRI("slvid:%d DBG. Last cmd idx:0x%x\r\n",
+					dev->slvid, ((rdata4 & 0xc) >> 2) - 1);
+			}
+
+		}
+		/*
+		 *SPMI_CRI("[0x%x]=0x%x [0x%x]=0x%x [0x%x]=0x%x [0x%x]=0x%x ",
+		 *	offset, rdata1, (offset + 1), rdata2,
+		 *	(offset + 2), rdata3, (offset + 3), rdata4);
+		 */
+
+		SPMI_CRI("Idx:%d slvid:%d Type:0x%x, [0x%x]=0x%x\r\n", j,
+			dev->slvid, (rdata4 & 0x3),
+			(rdata2 << 0x8) | rdata1, rdata3);
+		if (j <= 3)
+			j++;
+
+	}
+}
+
+int spmi_pmif_dbg_init(struct pmif *arb)
+{
+#if PMIF_MATCH_SUPPORT
+	unsigned int int_en = 0;
+#endif
+	arb->dbgregs = mt6xxx_pmif_dbg_regs;
+#if PMIF_MATCH_SUPPORT
+	/* enable matching mode */
+	PMIF_CRI("PMIF Matching Mode\n");
+
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_0], 0xffffffff);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_1], 0xffffffff);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_2], 0xffffffff);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_3], 0xffffffff);
+
+	int_en = DRV_Reg32(arb->base + arb->dbgregs[PMIF_IRQ_EVENT_EN_3]);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_EVENT_EN_3],
+		int_en | (0x1 << 7));
+
+	/* set monitor channel, should same as ARB_EN */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_CHAN_0],
+			0x2f5);
+	/* [31:16] addr mask, ffff mean all bit check
+	 * [15:0] addr, which addr been checked
+	 */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_ADDR_0],
+			0xffff03a5);
+	/* [31:16] wdata mask, ffff mean all bit check
+	 * [15:0] data, which data been checked
+	 */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WDATA_0],
+			0xffff005a);
+	/*
+	 * BIT[0] MONITOR_TARGET_WRITE_0
+	 * BIT[1] MONITOR_TARGET_WRITE_0_MASK: 0, rw all check, 1, check
+	 * BIT[0] if BIT[0] = 0, only check read;otherwise only check write.
+	 */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WRITE],
+			0x3);
+	/* reset then enable */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x800);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x405);
+#else
+	/* init pmif debug mechanism, hw matching mode or sw logging mode */
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_CHAN_0],
+			0x2f5);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_ADDR_0],
+			0x0);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WDATA_0],
+			0x0);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WRITE],
+			0x001);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x800);
+	DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x5);
+#endif /* end of PMIF_MATCH_SUPPORT */
+	return 0;
+}
+#endif /* endif SPMI_NO_PMIC */