[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/tia/inc/tia_reg.h b/mcu/driver/devdrv/tia/inc/tia_reg.h
new file mode 100644
index 0000000..f70caab
--- /dev/null
+++ b/mcu/driver/devdrv/tia/inc/tia_reg.h
@@ -0,0 +1,368 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2017
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tia_reg.h
+ *
+ * Project:
+ * --------
+ * VMOLY
+ *
+ * Description:
+ * ------------
+ * TIA (Thermal Information Acquisition) hardware register header
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __TIA_REG_H__
+#define __TIA_REG_H__
+
+#include "reg_base.h"
+//^^ move to reg_base_MTxxxx_username.h
+#ifndef BASE_INFRA_AO_TOPRGU
+#define BASE_INFRA_AO_TOPRGU (0xC0007000)
+#endif
+#ifndef BASE_MADDR_TIA
+#define BASE_MADDR_TIA (0xC001C000)
+#endif
+//&&
+
+#define TIA_M2N(adr) (((adr) & ~0xF0000000) | 0xD0000000)
+
+#define TIA_BASE (BASE_MADDR_TIA)
+#define TIA_AUXADC_CMD_ADDR (TIA_BASE + 0x0000)
+ #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR0_MSK (0xFFFF << 0)
+ #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR0(n) (((n) << 0) & TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR0_MSK)
+ #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR1_MSK (0xFFFF << 16)
+ #define TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR1(n) (((n) << 16) & TIA_AUXADC_CMD_ADDR_AUXADC_CMD_ADDR1_MSK)
+#define TIA_AUXADC_CMD (TIA_BASE + 0x0004)
+ #define TIA_AUXADC_CMD_AUXADC_CMD0_MSK (0xFFFF << 0)
+ #define TIA_AUXADC_CMD_AUXADC_CMD0(n) (((n) << 0) & TIA_AUXADC_CMD_AUXADC_CMD0_MSK)
+ #define TIA_AUXADC_CMD_AUXADC_CMD1_MSK (0xFFFF << 16)
+ #define TIA_AUXADC_CMD_AUXADC_CMD1(n) (((n) << 16) & TIA_AUXADC_CMD_AUXADC_CMD1_MSK)
+#define TIA_AUXADC_TEMP_ADDR (TIA_BASE + 0x0008)
+ #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR0_MSK (0xFFFF << 0)
+ #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR0(n) (((n) << 0) & TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR0_MSK)
+ #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR1_MSK (0xFFFF << 16)
+ #define TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR1(n) (((n) << 16) & TIA_AUXADC_TEMP_ADDR_AUXADC_RDATA_ADDR1_MSK)
+#define TIA_AUXADC_DLY (TIA_BASE + 0x000C)
+ #define TIA_AUXADC_DLY_AUXADC_INIT_DLY_MSK (0xFF << 0)
+ #define TIA_AUXADC_DLY_AUXADC_INIT_DLY(n) (((n) << 0) & TIA_AUXADC_DLY_AUXADC_INIT_DLY_MSK)
+ #define TIA_AUXADC_DLY_AUXADC_MEASURE_DLY_MSK (0xFF << 8)
+ #define TIA_AUXADC_DLY_AUXADC_MEASURE_DLY(n) (((n) << 8) & TIA_AUXADC_DLY_AUXADC_MEASURE_DLY_MSK)
+#define TIA_MD_ON (TIA_BASE + 0x0010)
+ #define TIA_MD_ON_MD_ON (1 << 0)
+#define TIA_MD_CTRL (TIA_BASE + 0x0014)
+ #define TIA_MD_CTRL_MD_PERIOD_MSK (0xFFF << 0)
+ #define TIA_MD_CTRL_MD_PERIOD(n) (((n) << 0) & TIA_MD_CTRL_MD_PERIOD_MSK)
+ #define TIA_MD_CTRL_MD_TEMP0_EN (1 << 12)
+ #define TIA_MD_CTRL_MD_TEMP1_EN (1 << 13)
+ #define TIA_MD_CTRL_MD_CLR_LATEST (1 << 14)
+#define TIA_GPS_ON (TIA_BASE + 0x0018)
+ #define TIA_GPS_ON_GPS_ON (1 << 0)
+#define TIA_GPS_CTRL (TIA_BASE + 0x001C)
+ #define TIA_GPS_CTRL_GPS_PERIOD_MSK (0xFFF << 0)
+ #define TIA_GPS_CTRL_GPS_PERIOD(n) (((n) << 0) & TIA_GPS_CTRL_GPS_PERIOD_MSK)
+ #define TIA_GPS_CTRL_GPS_TEMP0_EN (1 << 12)
+ #define TIA_GPS_CTRL_GPS_TEMP1_EN (1 << 13)
+ #define TIA_GPS_CTRL_GPS_CLR_LATEST (1 << 14)
+#define TIA_TEMP (TIA_BASE + 0x0020)
+ #define TIA_TEMP_TEMP0_MSK (0xFFFF << 0)
+ #define TIA_TEMP_TEMP0(v) (((v) >> 0) & 0xFFFF)
+ #define TIA_TEMP_TEMP1_MSK (0xFFFF << 16)
+ #define TIA_TEMP_TEMP1(v) (((v) >> 16) & 0xFFFF)
+#define TIA_SECUR (TIA_BASE + 0x0024)
+ #define TIA_SECUR_SEN (1 << 0)
+ #define TIA_SECUR_SEN_LOCK (1 << 1)
+#define TIA_DEBUG (TIA_BASE + 0x00FC)
+ #define TIA_DEBUG_CNT_T_MSK (0xFFF << 0)
+ #define TIA_DEBUG_CNT_T(v) (((v) >> 0) & 0xFFF)
+ #define TIA_DEBUG_MD_LATEST0 (1 << 12)
+ #define TIA_DEBUG_MD_LATEST1 (1 << 13)
+ #define TIA_DEBUG_GPS_LATEST0 (1 << 14)
+ #define TIA_DEBUG_GPS_LATEST1 (1 << 15)
+ #define TIA_DEBUG_FSM_MSK (0x7 << 16)
+ #define TIA_DEBUG_FSM(v) (((v) >> 16) & 0x7)
+#define TIA_TIA2_MODE_CTRL (TIA_BASE + 0x0028)
+ #define TIA_TIA2_MODE_CTRL_TIA_SEL (1 << 0)
+ #define TIA_TIA2_MODE_CTRL_TIA2_ON (1 << 1)
+ #define TIA_TIA2_MODE_CTRL_TIA2_MD_ON (1 << 4)
+ #define TIA_TIA2_MODE_CTRL_TIA2_GPS_ON (1 << 5)
+ #define TIA_TIA2_MODE_CTRL_TIA2_AP_ON (1 << 6)
+ #define TIA_TIA2_MODE_CTRL_TIA2_ADC_BIT_SEL (1 << 7)
+#define TIA_TIA2_MD_RC_CTRL (TIA_BASE + 0x002C)
+ #define TIA_TIA2_MD_RC_CTRL_TSX_RC_SEL_MD_MSK (0x3 << 0)
+ #define TIA_TIA2_MD_RC_CTRL_TSX_RC_SEL_MD(n) (((n) << 0) & TIA_TIA2_MD_RC_CTRL_TSX_RC_SEL_MD_MSK)
+ #define TIA_TIA2_MD_RC_CTRL_T0_RC_SEL_MD_MSK (0x3 << 4)
+ #define TIA_TIA2_MD_RC_CTRL_T0_RC_SEL_MD(n) (((n) << 4) & TIA_TIA2_MD_RC_CTRL_T0_RC_SEL_MD_MSK)
+ #define TIA_TIA2_MD_RC_CTRL_T1_RC_SEL_MD_MSK (0x3 << 8)
+ #define TIA_TIA2_MD_RC_CTRL_T1_RC_SEL_MD(n) (((n) << 8) & TIA_TIA2_MD_RC_CTRL_T1_RC_SEL_MD_MSK)
+ #define TIA_TIA2_MD_RC_CTRL_T2_RC_SEL_MD_MSK (0x3 << 12)
+ #define TIA_TIA2_MD_RC_CTRL_T2_RC_SEL_MD(n) (((n) << 12) & TIA_TIA2_MD_RC_CTRL_T2_RC_SEL_MD_MSK)
+ #define TIA_TIA2_MD_RC_CTRL_T3_RC_SEL_MD_MSK (0x3 << 16)
+ #define TIA_TIA2_MD_RC_CTRL_T3_RC_SEL_MD(n) (((n) << 16) & TIA_TIA2_MD_RC_CTRL_T3_RC_SEL_MD_MSK)
+#define TIA_TIA2_GPS_RC_CTRL (TIA_BASE + 0x0030)
+ #define TIA_TIA2_GPS_RC_CTRL_TSX_RC_SEL_GPS_MSK (0x3 << 0)
+ #define TIA_TIA2_GPS_RC_CTRL_TSX_RC_SEL_GPS(n) (((n) << 0) & TIA_TIA2_GPS_RC_CTRL_TSX_RC_SEL_GPS_MSK)
+ #define TIA_TIA2_GPS_RC_CTRL_T0_RC_SEL_GPS_MSK (0x3 << 4)
+ #define TIA_TIA2_GPS_RC_CTRL_T0_RC_SEL_GPS(n) (((n) << 4) & TIA_TIA2_GPS_RC_CTRL_T0_RC_SEL_GPS_MSK)
+ #define TIA_TIA2_GPS_RC_CTRL_T1_RC_SEL_GPS_MSK (0x3 << 8)
+ #define TIA_TIA2_GPS_RC_CTRL_T1_RC_SEL_GPS(n) (((n) << 8) & TIA_TIA2_GPS_RC_CTRL_T1_RC_SEL_GPS_MSK)
+ #define TIA_TIA2_GPS_RC_CTRL_T2_RC_SEL_GPS_MSK (0x3 << 12)
+ #define TIA_TIA2_GPS_RC_CTRL_T2_RC_SEL_GPS(n) (((n) << 12) & TIA_TIA2_GPS_RC_CTRL_T2_RC_SEL_GPS_MSK)
+ #define TIA_TIA2_GPS_RC_CTRL_T3_RC_SEL_GPS_MSK (0x3 << 16)
+ #define TIA_TIA2_GPS_RC_CTRL_T3_RC_SEL_GPS(n) (((n) << 16) & TIA_TIA2_GPS_RC_CTRL_T3_RC_SEL_GPS_MSK)
+#define TIA_TIA2_AP_RC_CTRL (TIA_BASE + 0x0034)
+ #define TIA_TIA2_AP_RC_CTRL_TSX_RC_SEL_AP_MSK (0x3 << 0)
+ #define TIA_TIA2_AP_RC_CTRL_TSX_RC_SEL_AP(n) (((n) << 0) & TIA_TIA2_AP_RC_CTRL_TSX_RC_SEL_AP_MSK)
+ #define TIA_TIA2_AP_RC_CTRL_T0_RC_SEL_AP_MSK (0x3 << 4)
+ #define TIA_TIA2_AP_RC_CTRL_T0_RC_SEL_AP(n) (((n) << 4) & TIA_TIA2_AP_RC_CTRL_T0_RC_SEL_AP_MSK)
+ #define TIA_TIA2_AP_RC_CTRL_T1_RC_SEL_AP_MSK (0x3 << 8)
+ #define TIA_TIA2_AP_RC_CTRL_T1_RC_SEL_AP(n) (((n) << 8) & TIA_TIA2_AP_RC_CTRL_T1_RC_SEL_AP_MSK)
+ #define TIA_TIA2_AP_RC_CTRL_T2_RC_SEL_AP_MSK (0x3 << 12)
+ #define TIA_TIA2_AP_RC_CTRL_T2_RC_SEL_AP(n) (((n) << 12) & TIA_TIA2_AP_RC_CTRL_T2_RC_SEL_AP_MSK)
+ #define TIA_TIA2_AP_RC_CTRL_T3_RC_SEL_AP_MSK (0x3 << 16)
+ #define TIA_TIA2_AP_RC_CTRL_T3_RC_SEL_AP(n) (((n) << 16) & TIA_TIA2_AP_RC_CTRL_T3_RC_SEL_AP_MSK)
+#define TIA_TIA2_ADC_INI_DLY (TIA_BASE + 0x0038)
+#define TIA_TIA2_RC_30K_DLY (TIA_BASE + 0x003C)
+#define TIA_TIA2_RC_100K_DLY (TIA_BASE + 0x0040)
+#define TIA_TIA2_RC_400K_DLY (TIA_BASE + 0x0044)
+#define TIA_TIA2_ADC15_CON_DLY (TIA_BASE + 0x0048)
+#define TIA_TIA2_ADC12_30K_CON_DLY (TIA_BASE + 0x004C)
+#define TIA_TIA2_ADC12_100K_CON_DLY (TIA_BASE + 0x0050)
+#define TIA_TIA2_ADC12_400K_CON_DLY0 (TIA_BASE + 0x0054)
+#define TIA_TIA2_ADC12_400K_CON_DLY1 (TIA_BASE + 0x0058)
+#define TIA_TIA2_ADC12_CON_SRCLK (TIA_BASE + 0x005C)
+#define TIA_TIA2_ADC_SET_ADDR (TIA_BASE + 0x0060)
+ #define TIA_TIA2_ADC_SET_ADDR_TIA2_ADC_SET_ADDR_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC_SET_ADDR_TIA2_ADC_SET_ADDR(n) (((n) << 0) & TIA_TIA2_ADC_SET_ADDR_TIA2_ADC_SET_ADDR_MSK)
+#define TIA_TIA2_TSX_30K_CMD (TIA_BASE + 0x0064)
+ #define TIA_TIA2_TSX_30K_CMD_TIA2_TSX_30K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_TSX_30K_CMD_TIA2_TSX_30K_CMD(n) (((n) << 0) & TIA_TIA2_TSX_30K_CMD_TIA2_TSX_30K_CMD_MSK)
+#define TIA_TIA2_TSX_100K_CMD (TIA_BASE + 0x0068)
+ #define TIA_TIA2_TSX_100K_CMD_TIA2_TSX_100K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_TSX_100K_CMD_TIA2_TSX_100K_CMD(n) (((n) << 0) & TIA_TIA2_TSX_100K_CMD_TIA2_TSX_100K_CMD_MSK)
+#define TIA_TIA2_TSX_400K_CMD (TIA_BASE + 0x006C)
+ #define TIA_TIA2_TSX_400K_CMD_TIA2_TSX_400K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_TSX_400K_CMD_TIA2_TSX_400K_CMD(n) (((n) << 0) & TIA_TIA2_TSX_400K_CMD_TIA2_TSX_400K_CMD_MSK)
+#define TIA_TIA2_ADC15_DCXO_CMD (TIA_BASE + 0x0070)
+ #define TIA_TIA2_ADC15_DCXO_CMD_TIA2_ADC15_DCXO_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC15_DCXO_CMD_TIA2_ADC15_DCXO_CMD(n) (((n) << 0) & TIA_TIA2_ADC15_DCXO_CMD_TIA2_ADC15_DCXO_CMD_MSK)
+#define TIA_TIA2_ADC12_DCXO_CMD (TIA_BASE + 0x0074)
+ #define TIA_TIA2_ADC12_DCXO_CMD_TIA2_ADC12_DCXO_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC12_DCXO_CMD_TIA2_ADC12_DCXO_CMD(n) (((n) << 0) & TIA_TIA2_ADC12_DCXO_CMD_TIA2_ADC12_DCXO_CMD_MSK)
+#define TIA_TIA2_T0_30K_CMD (TIA_BASE + 0x0078)
+ #define TIA_TIA2_T0_30K_CMD_TIA2_T0_30K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T0_30K_CMD_TIA2_T0_30K_CMD(n) (((n) << 0) & TIA_TIA2_T0_30K_CMD_TIA2_T0_30K_CMD_MSK)
+#define TIA_TIA2_T1_30K_CMD (TIA_BASE + 0x007C)
+ #define TIA_TIA2_T1_30K_CMD_TIA2_T1_30K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T1_30K_CMD_TIA2_T1_30K_CMD(n) (((n) << 0) & TIA_TIA2_T1_30K_CMD_TIA2_T1_30K_CMD_MSK)
+#define TIA_TIA2_T2_30K_CMD (TIA_BASE + 0x0080)
+ #define TIA_TIA2_T2_30K_CMD_TIA2_T2_30K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T2_30K_CMD_TIA2_T2_30K_CMD(n) (((n) << 0) & TIA_TIA2_T2_30K_CMD_TIA2_T2_30K_CMD_MSK)
+#define TIA_TIA2_T3_30K_CMD (TIA_BASE + 0x0084)
+ #define TIA_TIA2_T3_30K_CMD_TIA2_T3_30K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T3_30K_CMD_TIA2_T3_30K_CMD(n) (((n) << 0) & TIA_TIA2_T3_30K_CMD_TIA2_T3_30K_CMD_MSK)
+#define TIA_TIA2_T0_100K_CMD (TIA_BASE + 0x0088)
+ #define TIA_TIA2_T0_100K_CMD_TIA2_T0_100K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T0_100K_CMD_TIA2_T0_100K_CMD(n) (((n) << 0) & TIA_TIA2_T0_100K_CMD_TIA2_T0_100K_CMD_MSK)
+#define TIA_TIA2_T1_100K_CMD (TIA_BASE + 0x008C)
+ #define TIA_TIA2_T1_100K_CMD_TIA2_T1_100K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T1_100K_CMD_TIA2_T1_100K_CMD(n) (((n) << 0) & TIA_TIA2_T1_100K_CMD_TIA2_T1_100K_CMD_MSK)
+#define TIA_TIA2_T2_100K_CMD (TIA_BASE + 0x0090)
+ #define TIA_TIA2_T2_100K_CMD_TIA2_T2_100K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T2_100K_CMD_TIA2_T2_100K_CMD(n) (((n) << 0) & TIA_TIA2_T2_100K_CMD_TIA2_T2_100K_CMD_MSK)
+#define TIA_TIA2_T3_100K_CMD (TIA_BASE + 0x0094)
+ #define TIA_TIA2_T3_100K_CMD_TIA2_T3_100K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T3_100K_CMD_TIA2_T3_100K_CMD(n) (((n) << 0) & TIA_TIA2_T3_100K_CMD_TIA2_T3_100K_CMD_MSK)
+#define TIA_TIA2_T0_400K_CMD (TIA_BASE + 0x0098)
+ #define TIA_TIA2_T0_400K_CMD_TIA2_T0_400K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T0_400K_CMD_TIA2_T0_400K_CMD(n) (((n) << 0) & TIA_TIA2_T0_400K_CMD_TIA2_T0_400K_CMD_MSK)
+#define TIA_TIA2_T1_400K_CMD (TIA_BASE + 0x009C)
+ #define TIA_TIA2_T1_400K_CMD_TIA2_T1_400K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T1_400K_CMD_TIA2_T1_400K_CMD(n) (((n) << 0) & TIA_TIA2_T1_400K_CMD_TIA2_T1_400K_CMD_MSK)
+#define TIA_TIA2_T2_400K_CMD (TIA_BASE + 0x00A0)
+ #define TIA_TIA2_T2_400K_CMD_TIA2_T2_400K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T2_400K_CMD_TIA2_T2_400K_CMD(n) (((n) << 0) & TIA_TIA2_T2_400K_CMD_TIA2_T2_400K_CMD_MSK)
+#define TIA_TIA2_T3_400K_CMD (TIA_BASE + 0x00A4)
+ #define TIA_TIA2_T3_400K_CMD_TIA2_T3_400K_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T3_400K_CMD_TIA2_T3_400K_CMD(n) (((n) << 0) & TIA_TIA2_T3_400K_CMD_TIA2_T3_400K_CMD_MSK)
+#define TIA_TIA2_ADC15_TRIG_ADDR (TIA_BASE + 0x00A8)
+ #define TIA_TIA2_ADC15_TRIG_ADDR_TIA2_15ADC_TRIG_ADDR_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC15_TRIG_ADDR_TIA2_15ADC_TRIG_ADDR(n) (((n) << 0) & TIA_TIA2_ADC15_TRIG_ADDR_TIA2_15ADC_TRIG_ADDR_MSK)
+#define TIA_TIA2_ADC12_TRIG_ADDR (TIA_BASE + 0x00AC)
+ #define TIA_TIA2_ADC12_TRIG_ADDR_TIA2_12ADC_TRIG_ADDR_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC12_TRIG_ADDR_TIA2_12ADC_TRIG_ADDR(n) (((n) << 0) & TIA_TIA2_ADC12_TRIG_ADDR_TIA2_12ADC_TRIG_ADDR_MSK)
+#define TIA_TIA2_ADC15_TRIG_CMD (TIA_BASE + 0x00B0)
+ #define TIA_TIA2_ADC15_TRIG_CMD_TIA2_15ADC_TRIG_CMD_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC15_TRIG_CMD_TIA2_15ADC_TRIG_CMD(n) (((n) << 0) & TIA_TIA2_ADC15_TRIG_CMD_TIA2_15ADC_TRIG_CMD_MSK)
+#define TIA_TIA2_ADC12_TRIG_CMD0 (TIA_BASE + 0x00B4)
+ #define TIA_TIA2_ADC12_TRIG_CMD0_TIA2_12ADC_TRIG_CMD0_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC12_TRIG_CMD0_TIA2_12ADC_TRIG_CMD0(n) (((n) << 0) & TIA_TIA2_ADC12_TRIG_CMD0_TIA2_12ADC_TRIG_CMD0_MSK)
+#define TIA_TIA2_ADC12_TRIG_CMD1 (TIA_BASE + 0x00B8)
+ #define TIA_TIA2_ADC12_TRIG_CMD1_TIA2_12ADC_TRIG_CMD1_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC12_TRIG_CMD1_TIA2_12ADC_TRIG_CMD1(n) (((n) << 0) & TIA_TIA2_ADC12_TRIG_CMD1_TIA2_12ADC_TRIG_CMD1_MSK)
+#define TIA_TIA2_ADC15_READ_ADDR (TIA_BASE + 0x00BC)
+ #define TIA_TIA2_ADC15_READ_ADDR_TIA2_15ADC_READ_ADDR_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC15_READ_ADDR_TIA2_15ADC_READ_ADDR(n) (((n) << 0) & TIA_TIA2_ADC15_READ_ADDR_TIA2_15ADC_READ_ADDR_MSK)
+#define TIA_TIA2_ADC12_READ_ADDR0 (TIA_BASE + 0x00C0)
+ #define TIA_TIA2_ADC12_READ_ADDR0_TIA2_12ADC_READ_ADDR0_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC12_READ_ADDR0_TIA2_12ADC_READ_ADDR0(n) (((n) << 0) & TIA_TIA2_ADC12_READ_ADDR0_TIA2_12ADC_READ_ADDR0_MSK)
+#define TIA_TIA2_ADC12_READ_ADDR1 (TIA_BASE + 0x00C4)
+ #define TIA_TIA2_ADC12_READ_ADDR1_TIA2_12ADC_READ_ADDR1_MSK (0xFFFF << 0)
+ #define TIA_TIA2_ADC12_READ_ADDR1_TIA2_12ADC_READ_ADDR1(n) (((n) << 0) & TIA_TIA2_ADC12_READ_ADDR1_TIA2_12ADC_READ_ADDR1_MSK)
+#define TIA_TIA2_READY_CLR (TIA_BASE + 0x00C8)
+ #define TIA_TIA2_READY_CLR_MD_MD_TSX_READY_CLR (1 << 0)
+ #define TIA_TIA2_READY_CLR_MD_T0_READY_CLR (1 << 1)
+ #define TIA_TIA2_READY_CLR_MD_T1_READY_CLR (1 << 2)
+ #define TIA_TIA2_READY_CLR_MD_T2_READY_CLR (1 << 3)
+ #define TIA_TIA2_READY_CLR_MD_T3_READY_CLR (1 << 4)
+ #define TIA_TIA2_READY_CLR_MD_GPS_TSX_READY_CLR (1 << 5)
+ #define TIA_TIA2_READY_CLR_MD_DCXO_READY_CLR (1 << 6)
+ #define TIA_TIA2_READY_CLR_GPS_MD_TSX_READY_CLR (1 << 7)
+ #define TIA_TIA2_READY_CLR_GPS_T0_READY_CLR (1 << 8)
+ #define TIA_TIA2_READY_CLR_GPS_T1_READY_CLR (1 << 9)
+ #define TIA_TIA2_READY_CLR_GPS_T2_READY_CLR (1 << 10)
+ #define TIA_TIA2_READY_CLR_GPS_T3_READY_CLR (1 << 11)
+ #define TIA_TIA2_READY_CLR_GPS_GPS_TSX_READY_CLR (1 << 12)
+ #define TIA_TIA2_READY_CLR_GPS_DCXO_READY_CLR (1 << 13)
+ #define TIA_TIA2_READY_CLR_AP_MD_TSX_READY_CLR (1 << 14)
+ #define TIA_TIA2_READY_CLR_AP_T0_READY_CLR (1 << 15)
+ #define TIA_TIA2_READY_CLR_AP_T1_READY_CLR (1 << 16)
+ #define TIA_TIA2_READY_CLR_AP_T2_READY_CLR (1 << 17)
+ #define TIA_TIA2_READY_CLR_AP_T3_READY_CLR (1 << 18)
+ #define TIA_TIA2_READY_CLR_AP_GPS_TSX_READY_CLR (1 << 19)
+ #define TIA_TIA2_READY_CLR_AP_DCXO_READY_CLR (1 << 20)
+#define TIA_TIA2_MD_TSX_DATA (TIA_BASE + 0x00CC)
+ #define TIA_TIA2_MD_TSX_DATA_MD_MD_TSX_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_MD_TSX_DATA_MD_MD_TSX_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_GPS_TSX_DATA (TIA_BASE + 0x00D0)
+ #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_RC_MSK (0x3 << 16)
+ #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_RC(v) (((v) >> 16) & 0x3)
+ #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_GPS_TSX_DATA_GPS_TSX_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_T0_DATA (TIA_BASE + 0x00D4)
+ #define TIA_TIA2_T0_DATA_T0_RC_MSK (0x3 << 16)
+ #define TIA_TIA2_T0_DATA_T0_RC(v) (((v) >> 16) & 0x3)
+ #define TIA_TIA2_T0_DATA_T0_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T0_DATA_T0_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_T1_DATA (TIA_BASE + 0x00D8)
+ #define TIA_TIA2_T1_DATA_T1_RC_MSK (0x3 << 16)
+ #define TIA_TIA2_T1_DATA_T1_RC(v) (((v) >> 16) & 0x3)
+ #define TIA_TIA2_T1_DATA_T1_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T1_DATA_T1_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_T2_DATA (TIA_BASE + 0x00DC)
+ #define TIA_TIA2_T2_DATA_T2_RC_MSK (0x3 << 16)
+ #define TIA_TIA2_T2_DATA_T2_RC(v) (((v) >> 16) & 0x3)
+ #define TIA_TIA2_T2_DATA_T2_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T2_DATA_T2_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_T3_DATA (TIA_BASE + 0x00E0)
+ #define TIA_TIA2_T3_DATA_T3_RC_MSK (0x3 << 16)
+ #define TIA_TIA2_T3_DATA_T3_RC(v) (((v) >> 16) & 0x3)
+ #define TIA_TIA2_T3_DATA_T3_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_T3_DATA_T3_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_DCXO_DATA (TIA_BASE + 0x00E4)
+ #define TIA_TIA2_DCXO_DATA_DCXO_DATA_MSK (0xFFFF << 0)
+ #define TIA_TIA2_DCXO_DATA_DCXO_DATA(v) (((v) >> 0) & 0xFFFF)
+#define TIA_TIA2_SPMI_CMD (TIA_BASE + 0x00E8)
+ #define TIA_TIA2_SPMI_CMD_SPMI_CMD_MSK (0x3 << 0)
+ #define TIA_TIA2_SPMI_CMD_SPMI_CMD(n) (((n) << 0) & TIA_TIA2_SPMI_CMD_SPMI_CMD_MSK)
+ #define TIA_TIA2_SPMI_CMD_SPMI_PMIFID (1 << 2)
+ #define TIA_TIA2_SPMI_CMD_SPMI_BYTECNT (1 << 3)
+ #define TIA_TIA2_SPMI_CMD_SPMI_SLVID_MSK (0xF << 4)
+ #define TIA_TIA2_SPMI_CMD_SPMI_SLVID(n) (((n) << 4) & TIA_TIA2_SPMI_CMD_SPMI_SLVID_MSK)
+#define TIA_TIA2_DEBUG (TIA_BASE + 0x00F0)
+ #define TIA_TIA2_DEBUG_MD_MD_TSX_DATA_READY (1 << 0)
+ #define TIA_TIA2_DEBUG_MD_T0_DATA_READY (1 << 1)
+ #define TIA_TIA2_DEBUG_MD_T1_DATA_READY (1 << 2)
+ #define TIA_TIA2_DEBUG_MD_T2_DATA_READY (1 << 3)
+ #define TIA_TIA2_DEBUG_MD_T3_DATA_READY (1 << 4)
+ #define TIA_TIA2_DEBUG_MD_GPS_TSX_DATA_READY (1 << 5)
+ #define TIA_TIA2_DEBUG_MD_DCXO_DATA_READY (1 << 6)
+ #define TIA_TIA2_DEBUG_GPS_MD_TSX_DATA_READY (1 << 7)
+ #define TIA_TIA2_DEBUG_GPS_T0_DATA_READY (1 << 8)
+ #define TIA_TIA2_DEBUG_GPS_T1_DATA_READY (1 << 9)
+ #define TIA_TIA2_DEBUG_GPS_T2_DATA_READY (1 << 10)
+ #define TIA_TIA2_DEBUG_GPS_T3_DATA_READY (1 << 11)
+ #define TIA_TIA2_DEBUG_GPS_GPS_TSX_DATA_READY (1 << 12)
+ #define TIA_TIA2_DEBUG_GPS_DCXO_DATA_READY (1 << 13)
+ #define TIA_TIA2_DEBUG_AP_MD_TSX_DATA_READY (1 << 14)
+ #define TIA_TIA2_DEBUG_AP_T0_DATA_READY (1 << 15)
+ #define TIA_TIA2_DEBUG_AP_T1_DATA_READY (1 << 16)
+ #define TIA_TIA2_DEBUG_AP_T2_DATA_READY (1 << 17)
+ #define TIA_TIA2_DEBUG_AP_T3_DATA_READY (1 << 18)
+ #define TIA_TIA2_DEBUG_AP_DCXO_DATA_READY (1 << 19)
+ #define TIA_TIA2_DEBUG_AP_GPS_TSX_DATA_READY (1 << 20)
+ #define TIA_TIA2_DEBUG_ST_FSM_MSK (0xF << 21)
+ #define TIA_TIA2_DEBUG_ST_FSM(v) (((v) >> 21) & 0xF)
+ #define TIA_TIA2_DEBUG_TR_FSM_MSK (0x7 << 25)
+ #define TIA_TIA2_DEBUG_TR_FSM(v) (((v) >> 25) & 0x7)
+
+//******************************************************************************
+// useful macro
+//******************************************************************************
+// TIA ADC value, n = 0 ~ 3
+#define TIA_HW_RC_ADC(n) (TIA_M2N(TIA_TIA2_T0_DATA) + ((n) << 2))
+#define TIA_HW_RC_VAL(v) (((v) >> 16) & 0x3)
+#define TIA_HW_ADC_VLD(v) (((v) >> 15) & 0x1)
+#define TIA_HW_ADC_VAL(v) (((v) >> 0) & 0x7fff)
+
+// TOPRGU WDT_NONRST_REG2 for hw reset state record
+// 4BIT[20:17]: MD TIA SW Thermal Reset Used
+// https://wiki.mediatek.inc/display/ALPSStorage/Colgin+RGU+Usage
+#define TOPRGU_WDT_NONRST_REG2 (BASE_INFRA_AO_TOPRGU + 0x24)
+ #define TOPRGU_TIA_STATUS_MSK (0xF << 17)
+ #define TOPRGU_TIA_STATUS(n) (((v) << 17) & TOPRGU_TIA_STATUS_MSK)
+ #define TOPRGU_TID_STATUS(tid) (0x1 << (17 + (tid)))
+
+#endif