[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/uart/src/uart_handler.c b/mcu/driver/devdrv/uart/src/uart_handler.c
new file mode 100644
index 0000000..7614234
--- /dev/null
+++ b/mcu/driver/devdrv/uart/src/uart_handler.c
@@ -0,0 +1,610 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * uart_handler.c
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Handler for UART
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 29 2019 yao.xue
+ * [MOLY00425268] [SMO][VMOLY]Remove unnecessary Assert in user load
+ * Modify Assert to DEBUG ASSERT in UART driver
+ *
+ * 02 15 2019 panu.peisa
+ * [MOLY00384803] [Gen97][SystemService][Change Request] KAL Refactoring Phase-in
+ *
+ * Added changes to swrd part.
+ *
+ * 04 10 2018 yuke.ren
+ * [MOLY00318981] Merge SLT Code
+ * .
+ *
+ * 03 13 2018 shenghui.shi
+ * [MOLY00309657] UMOLYE driver warning fix
+ * update UART driver
+ *
+ * 09 07 2017 yao.xue
+ * [MOLY00275927] update uart dbg_print init
+ * update dbgprint init
+ *
+ * 04 24 2017 shenghui.shi
+ * [MOLY00243727] update UART PDN feature
+ * update UART pdn feature,to void system could not entry DCM issue.
+ *
+ * 03 15 2016 shenghui.shi
+ * [MOLY00081492] [UART] update uart driver
+ * update dbgprint driver for SMP
+ *
+ * 02 11 2015 shenghui.shi
+ * [MOLY00081492] [UART] update uart driver
+ * 1. add sw escape feature to UMOLY
+ * 2. phase out VFIFO hw code in devdrv_common.c
+ *
+ * 12 18 2014 shenghui.shi
+ * [MOLY00081492] [UART] update uart driver
+ * .
+ *
+ * 11 14 2014 shenghui.shi
+ * [MOLY00081492] [UART] update uart driver
+ * add UART eception check timeout status feature
+ *
+ * 12 30 2013 shenghui.shi
+ * [MOLY00051976] Update UART driver to separate UARTcore and DRV_DEBUG
+ * update uart driver to sperate uartcore and DRV_DEBUG
+ *
+ * 12 25 2013 shenghui.shi
+ * [MOLY00051587] [MT6290 MOLY] uart driver update for TTY_CMD_EXCEPTION_HIF_POLL
+ * uart driver update for TTY_CMD_EXCEPTION_HIF_POL
+ *
+ * 12 04 2013 shenghui.shi
+ * [MOLY00048917] [MT6290E2] uart driver update
+ * .
+ *
+ * 11 07 2013 shenghui.shi
+ * [MOLY00045403] update UARTcore task
+ * .
+ *
+ * 08 27 2013 shenghui.shi
+ * [MOLY00035212] fix uart build modis error
+ * update UART exception driver for following the HMU standard mode.
+ *
+ * 02 04 2013 ansel.liao
+ * [MOLY00006575] Add UART/HDMA Driver
+ * rename: 7208 -> 6290
+ *
+ * 12 12 2012 ansel.liao
+ * [MOLY00006575] Add UART/HDMA Driver
+ * Integration change.
+ *
+ * 11 23 2012 ansel.liao
+ * [MOLY00006575] Add UART/HDMA Driver
+ * Add UART/HDMA driver
+ ****************************************************************************/
+#include "dcl.h"
+#include "uart_internal.h"
+#include "uart_sw.h"
+#include "kal_general_types.h"
+#include "drv_comm.h"
+#include "kal_public_api.h"
+#include "kal_ex_api.h"
+
+
+#if defined(__HMU_ENABLE__)
+#include "hmu.h"
+#include "hmu_conf_data.h"
+#endif
+
+#define UART_CHUNK_SIZE 512
+
+UartDriver_strcut* pUart_CMD_FUNC[MAX_UART_PORT_NUM];
+kal_uint32 uart_open_event = 0;
+extern UARTStruct UARTPort[];
+extern kal_uint32 uart_ecpt_get_tx_state(UART_PORT port);
+extern void UART_PDN_Disable(UART_PORT port);
+extern void UART_PDN_Enable(UART_PORT port);
+extern void dbg_uart_init(void);
+#ifndef KTEST_UART_TRACES
+extern void dbg_uart_create_spinlock(void);
+#endif
+static DCL_STATUS UART_Handler(DCL_DEV dev,DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+Seriport_HANDLER_T Uart_Drv_Handler = {DCL_UART_TYPE, UART_Handler};
+//extern UART_flowCtrlMode UART_GetFlowCtrl(UART_PORT uart_port);
+
+DCL_STATUS UART_Handler(DCL_DEV dev,DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ kal_bool return_flag = KAL_FALSE;
+ DCL_STATUS return_status = STATUS_OK;
+ if(dev >= MAX_UART_PORT_NUM)
+ return STATUS_INVALID_DEVICE;
+
+ switch (cmd)
+ {
+ // Class Driver must implement
+ case SIO_CMD_INIT:
+ {
+ #if defined(DRV_DEBUG)||defined(__IC_SLT__)
+ UART_DriverInit(dev);
+ #ifndef KTEST_UART_TRACES
+ dbg_uart_create_spinlock();
+ #endif
+ //dbg_uart_init();
+ #elif defined(__HIF_UART_SUPPORT__)
+ UART_DriverInit(dev);
+ #else
+ /* disable uart clock in drv_init_phase1() if not used */
+ UART_PDN_Enable(dev);
+ #endif
+ }
+ break;
+
+ case SIO_CMD_OPEN:
+ {
+ UART_CTRL_OPEN_T* prCtrlOpen;
+#if defined(__UARTCORE_SUPPORT__) && !defined(UARTCORE_NOT_PRESENT) && !defined(__UARTCORE_TASK_DISABLE__)&&!defined(DRV_DEBUG)
+ uart_open_event ++;
+ hmu_hifeg_set(HIF_DRV_EG_UART_IND_EVENT);
+#endif
+ prCtrlOpen = &(data->rUARTCtrlOPEN);
+ return_flag = pUart_CMD_FUNC[dev]->Open(dev,(module_type)(prCtrlOpen->u4OwenrId));
+ if(return_flag == KAL_FALSE){
+ UART_DriverInit(dev);
+ return_status = STATUS_FAIL;
+ }
+ }
+ break;
+
+ case SIO_CMD_CLOSE:
+ {
+ UART_CTRL_CLOSE_T* prCtrlClose;
+ prCtrlClose = &(data->rUARTCtrlCLOSE);
+ pUart_CMD_FUNC[dev]->Close(dev,(module_type)(prCtrlClose->u4OwenrId));
+#if defined(__UARTCORE_SUPPORT__) && !defined(UARTCORE_NOT_PRESENT) && !defined(__UARTCORE_TASK_DISABLE__)&&!defined(DRV_DEBUG)
+ if(uart_open_event>0){
+ uart_open_event--;
+ }
+#endif
+ }
+ break;
+
+ case SIO_CMD_PURGE:
+ {
+ UART_CTRL_PURGE_T* prCtrlPurge;
+ prCtrlPurge = &(data->rUARTCtrlPURGE);
+ pUart_CMD_FUNC[dev]->Purge(dev,(UART_buffer)(prCtrlPurge->dir),(module_type)(prCtrlPurge->u4OwenrId) );
+ }
+ break;
+
+ case SIO_CMD_SET_OWNER:
+ {
+ UART_CTRL_OWNER_T* prCtrlOwner;
+ prCtrlOwner = &(data->rUARTCtrlOWNER);
+ pUart_CMD_FUNC[dev]->SetOwner(dev, (module_type) (prCtrlOwner->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_CLR_RX_BUF:
+ {
+ UART_CTRL_CLR_BUFFER_T* prCtrlClrBuffer;
+ prCtrlClrBuffer = &(data->rUARTCtrlCLRBUFFER);
+ pUart_CMD_FUNC[dev]->ClrRxBuffer(dev, (module_type) (prCtrlClrBuffer->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_CLR_TX_BUF:
+ {
+ UART_CTRL_CLR_BUFFER_T* prCtrlClrBuffer;
+ prCtrlClrBuffer = &(data->rUARTCtrlCLRBUFFER);
+ pUart_CMD_FUNC[dev]->ClrTxBuffer(dev, (module_type) (prCtrlClrBuffer->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_GET_OWNER_ID:
+ {
+ UART_CTRL_OWNER_T* prCtrlOwner;
+ prCtrlOwner = &(data->rUARTCtrlOWNER);
+ prCtrlOwner->u4OwenrId = pUart_CMD_FUNC[dev]->GetOwnerID(dev);
+ }
+ break;
+
+ // Other SIO configuration related commands
+ case SIO_CMD_SET_FLOW_CTRL:
+ {
+ UART_CTRL_FLOW_CTRL_T* prCtrlFlowCtrl;
+ prCtrlFlowCtrl = &(data->rUARTCtrlFLOWCTRL);
+ pUart_CMD_FUNC[dev]->SetFlowCtrl(dev,(kal_bool)(prCtrlFlowCtrl->bXON),(module_type)(prCtrlFlowCtrl->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_CONFIG_ESCAPE:
+ {
+ UART_CTRL_CONFIG_ESP_T* prCtrlConfigEsp;
+ prCtrlConfigEsp = &(data->rUARTCtrlCONFIGESP);
+ pUart_CMD_FUNC[dev]->ConfigEscape(dev, prCtrlConfigEsp->uEscChar, prCtrlConfigEsp->u2ESCGuardtime, (module_type) (prCtrlConfigEsp->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_SET_DCB_CONFIG:
+ {
+ UARTDCBStruct *prDCB;
+ UART_CTRL_DCB_T* prCtrlDCB;
+ prCtrlDCB = &(data->rUARTCtrlDCB);
+ prDCB = (UARTDCBStruct*)(&(prCtrlDCB->rUARTConfig));
+ pUart_CMD_FUNC[dev]->SetDCBConfig(dev,prDCB,(module_type)(prCtrlDCB->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_CTRL_DCD: // Not used in MT6290 UART
+ DEBUG_ASSERT(0);
+ break;
+
+ case SIO_CMD_CTRL_BREAK:
+ {
+ UART_CTRL_BREAK_T* prCtrlBreak;
+ prCtrlBreak = &(data->rUARTCtrlBREAK);
+ pUart_CMD_FUNC[dev]->CtrlBreak(dev, (IO_level) (prCtrlBreak->rIOLevelBRK), (module_type) (prCtrlBreak->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_SET_BAUDRATE:
+ {
+ UART_CTRL_BAUDRATE_T* prCtrlBaudrate;
+ prCtrlBaudrate = &(data->rUARTCtrlBAUDRATE);
+ pUart_CMD_FUNC[dev]->SetBaudRate(dev, prCtrlBaudrate->baudrate, (module_type)(prCtrlBaudrate->u4OwenrId));
+ }
+ break;
+
+ case SIO_CMD_SET_AUTOBAUD_DIV: // LTE TBC
+ DEBUG_ASSERT(0);
+ break;
+
+ case SIO_CMD_READ_DCB_CONFIG:
+ {
+ UARTDCBStruct *prDCB;
+ UART_CTRL_DCB_T* prCtrlDCB;
+ prCtrlDCB = &(data->rUARTCtrlDCB);
+ prDCB = (UARTDCBStruct*) &(prCtrlDCB->rUARTConfig);
+ pUart_CMD_FUNC[dev]->ReadDCBConfig(dev, prDCB);
+ }
+ break;
+
+ case SIO_CMD_CTRL_RI: // Not used in MT6290 UART
+ DEBUG_ASSERT(0);
+ break;
+
+ case SIO_CMD_GET_ESCAPE_INFO:
+ {
+ UART_CTRL_CONFIG_ESP_T* prCtrlConfigEsp;
+ prCtrlConfigEsp = &(data->rUARTCtrlCONFIGESP);
+ prCtrlConfigEsp->u2ESCGuardtime = UARTPort[dev].ESCDet.GuardTime;
+ prCtrlConfigEsp->uEscChar = UARTPort[dev].ESCDet.EscChar;
+ }
+ break;
+
+ case SIO_CMD_CTRL_DTR: // Not used in MT6290 UART
+ case SIO_CMD_READ_HW_STATUS: // Not used in MT6290 UART (assert temporary)
+
+ // Not used commands in driver level (TTY would handle/wrap these commands from conventional upper layer module)
+ case SIO_CMD_GET_BYTES:
+ case SIO_CMD_PUT_BYTES:
+ case SIO_CMD_GET_RX_AVAIL:
+ case SIO_CMD_GET_TX_AVAIL:
+ case SIO_CMD_PUT_ISR_BYTES:
+ case SIO_CMD_GET_ISR_TX_AVAIL:
+ case SIO_CMD_SEND_ISR_DATA:
+ case SIO_CMD_SEND_DATA:
+ case SIO_CMD_REG_TX_CB:
+ case SIO_CMD_REG_RX_CB:
+ case SIO_CMD_PUT_UART_BYTE:
+ case SIO_CMD_GET_UART_BYTE:
+ case SIO_CMD_PUT_UART_BYTES:
+ DEBUG_ASSERT(0);
+ break;
+
+ // ???
+ case SIO_CMD_GET_UART_BYTE_WITH_TIMEOUT:
+ // temporary
+ DEBUG_ASSERT(0);
+ {
+ UART_CTRL_GET_UART_BYTE_WITH_TIMEOUT_T* prCtrlGetUartByte;
+ prCtrlGetUartByte = &(data->rUARTCtrlGETUARTBYTEWithTimeOut);
+ prCtrlGetUartByte->u1retByte = pUart_CMD_FUNC[dev]->GetUARTByte_WithTimeOut(dev, &(prCtrlGetUartByte->uByte), prCtrlGetUartByte->u4timeout_value);
+ }
+ break;
+
+ // Only UART driver need to take care
+ case UART_CMD_SET_FIFO_TRIGGER:
+ {
+ UART_CTRL_SFT_T* prCtrlSFT;
+ prCtrlSFT = &(data->rUARTCtrlSFT);
+ UART_set_FIFO_trigger(dev, prCtrlSFT->tx_level, prCtrlSFT->rx_level);
+ }
+ break;
+
+ case UART_CMD_POWER_ON:
+ break;
+
+ case UART_CMD_CHECK_TX_BUF_EMPTY:
+ {
+ UART_CTRL_CHECK_TBE_T* prCtrlTBE;
+ prCtrlTBE = &(data->rUARTCtrlCheckBUFEMP);
+ prCtrlTBE->bFlag = UART_CheckTxBufferEmpty(dev);
+ }
+ break;
+
+ case UART_CMD_CHECK_TX_SEND_OUT:
+ {
+ UART_CTRL_CHECK_TSO_T* prCtrlTSO;
+ prCtrlTSO = &(data->rUARTCtrlCheckTXSendOut);
+ prCtrlTSO->bFlag = UART_CheckTxAllSentOut(dev);
+ }
+ break;
+
+ case UART_CMD_GET_TX_BUF_SIZE:
+ DEBUG_ASSERT(0);
+ {
+ UART_CTRL_GET_TBS_T* prCtrlGetTBS;
+ prCtrlGetTBS = &(data->rUARTCtrlGetTxBufSize);
+ UART_GetTxBufferSize(dev, (kal_uint32 *)(prCtrlGetTBS->ptotal_size), (kal_uint32 *)(prCtrlGetTBS->preturn_size));
+ }
+ break;
+
+ case UART_CMD_SLEEP_TX_ENABLE:
+ return STATUS_UNSUPPORTED;
+
+ case UART_CMD_CTRL_SLEEP_MODE:
+ {
+ UART_CTRL_SLEEP_ENABLE_T* prCtrlSleepEnable;
+ prCtrlSleepEnable = &(data->rUARTCtrlSleepEnable);
+ UART_SetSleepEnable(dev, (kal_bool) prCtrlSleepEnable->bFlag);
+ }
+ break;
+ case UART_CMD_SWITCH_PORT:
+ return STATUS_UNSUPPORTED;
+
+ case UART_CMD_BOOTUP_INIT:
+ {
+ UART_Bootup_Init();
+ }
+ break;
+
+ case UART_CMD_BOOT_PUTBYTES:
+ {
+ UART_CTRL_BOOT_PUTBYTES_T* prCtrlPutBytes;
+ prCtrlPutBytes = &(data->rUARTCtrlBootPutBytes);
+ UART_Boot_PutUARTBytes(dev,prCtrlPutBytes->puBuffaddr, prCtrlPutBytes->u2Length);
+ }
+ break;
+
+ case UART_CMD_LOOPBACK:
+ {
+ UART_loopback(dev);
+ }
+ break;
+
+ case UART_CMD_ASSERT_WAIT_SEND_OUT:
+ {
+ UART_AssertWaitPrevDataSentOut(dev);
+ }
+ break;
+
+ case UART_CMD_CTRL_USE_VFIFO:
+ return STATUS_UNSUPPORTED;
+ DEBUG_ASSERT(0);
+ {
+// UART_CTRL_USE_VFIFO_T* prCtrlUseVfifo;
+// prCtrlUseVfifo = &(data->rUARTCtrlUseVFifo);
+// UART_UseVFIFO(dev,prCtrlUseVfifo->bUseVFifo);
+ }
+ break;
+
+ case UART_CMD_GET_FLOW_CONTROL:
+ {
+ UART_CTRL_GET_FC_T* prCtrlFlowControl;
+ prCtrlFlowControl = &(data->rUARTCtrlGetFC);
+ prCtrlFlowControl->FlowCtrlMode = (UART_FLOW_CTRL_MODE_T) U_GetFlowCtrl(dev, prCtrlFlowControl->u4OwenrId);
+ }
+ break;
+
+ case UART_CMD_REG_DEF_CB:
+ DEBUG_ASSERT(0);
+ break;
+
+ case UART_CMD_BMT_PUT_BYTES:
+ {
+ #ifdef DRV_DEBUG
+ UART_CTRL_PUT_BYTES_T* prCtrlBMTPutBytes;
+ prCtrlBMTPutBytes = &(data->rUARTCtrlPUTBYTES);
+ BMT_PutBytes(dev, prCtrlBMTPutBytes->puBuffaddr, prCtrlBMTPutBytes->u2Length);
+ #endif
+ }
+ break;
+
+ case UART_CMD_GET_MAX_BAUDRATE:
+ {
+ UART_CTRL_GET_MAXBAUDRATE_T* prCtrlGetMaxBaudrate;
+ prCtrlGetMaxBaudrate = &(data->rUARTCtrlGetMaxBaudrate);
+ prCtrlGetMaxBaudrate->max_baudrate = UART_Get_Maxbaudrate(dev);
+ }
+ break;
+
+ case UART_CMD_RECHANDLER_VFIFO:
+ case UART_CMD_TRXHANDLER_VFIFO:
+ case UART_CMD_RECTIMEOUTHANDLE:
+ case UART_CMD_CTRL_TX_DMA:
+ DEBUG_ASSERT(0);
+ {
+ UART_CTRL_USE_VFIFO_T* prCtrlTxDMA;
+ prCtrlTxDMA = &(data->rUARTCtrlUseVFifo);
+ UART_VFIFO_TX_DMA_Enable(dev,(kal_bool)(prCtrlTxDMA->bUseVFifo));
+ }
+ break;
+
+ // TTY commands
+ case TTY_CMD_GET_CHUNK_SIZE:
+ {
+ UART_CTRL_GET_CHUNK_SIZE_T *prCtrlGetChunkSize;
+ prCtrlGetChunkSize = &(data->rUARTCtrlGETCHUNKSIZE);
+ prCtrlGetChunkSize->chunkSize = UART_CHUNK_SIZE;
+ }
+ break;
+
+ case TTY_CMD_ASSIGN_RX_IOR:
+ {
+ UART_CTRL_ASSIGN_RX_IOR_T *prCtrlAssignRxIor;
+ prCtrlAssignRxIor = &(data->rUARTCtrlAssignRxIor);
+ UART_GetBytesIor(dev, prCtrlAssignRxIor->ior);
+ }
+ break;
+
+ case TTY_CMD_NEED_TX_DONE_CB:
+ {
+ UART_CTRL_NEED_TX_DONE_CB_T *prNeedTxDoneCb;
+ prNeedTxDoneCb = &(data->rUARTCtrlNeedTxDoneCb);
+ UART_SetNeedTxDoneCb(dev, prNeedTxDoneCb->needTxDoneCb, prNeedTxDoneCb->u4OwnerId);
+ }
+ break;
+
+ case TTY_CMD_GET_DRV_STATE:
+ {
+ UART_CTRL_GET_DRV_STATE_T *prGetDrvState;
+ prGetDrvState = &(data->rUARTCtrlGetDrvState);
+ prGetDrvState->drv_state = DRV_ST_ATTACHED;
+ }
+ break;
+
+ case TTY_CMD_PUT_BYTES_IOR:
+ {
+ UART_CTRL_PUT_BYTES_IOR_T *prCtrlPutBytesIor;
+ prCtrlPutBytesIor = &(data->rUARTCtrlPUTBYTESIOR);
+ UART_PutBytesIor(dev, prCtrlPutBytesIor->putIor);
+ }
+ break;
+
+ case TTY_CMD_PUT_BYTES_IOR_LIGHT:
+ {
+ UART_CTRL_PUT_BYTES_IOR_T *prCtrlPutBytesIor;
+ prCtrlPutBytesIor = &(data->rUARTCtrlPUTBYTESIOR);
+ UART_PutBytesIor_LIGHT(dev, prCtrlPutBytesIor->putIor);
+ }
+ break;
+
+ // TTY commands for exception
+ case TTY_CMD_EXCEPTION_RESET:
+ break;
+
+ case TTY_CMD_EXCEPTION_HIF_INIT:
+ {
+ return_status = uart_ecpt_init_hif(dev);
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_CLEAR_CHANNEL:
+ {
+ return_status = uart_ecpt_clear_ch(dev);
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_TX_GPD:
+ {
+ TTY_CTRL_EXCP_TX_GPD_T* prCtrlExptTxGpd;
+ prCtrlExptTxGpd = &(data->rTTYCtrlExcpTxGPD);
+ return_status = uart_ecpt_tx_gpd(dev, prCtrlExptTxGpd->first_gpd, prCtrlExptTxGpd->last_gpd);
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_TX_DONE_INFO:
+ {
+ TTY_CTRL_EXCP_TX_DONE_INFO_T* prCtrlExptTxDoneInfo;
+ prCtrlExptTxDoneInfo = &(data->rTTYCtrlExcpTxDoneInfo);
+ return_status = uart_ecpt_tx_done_info(dev, &(prCtrlExptTxDoneInfo->first_gpd), &(prCtrlExptTxDoneInfo->last_gpd), (kal_uint32 *) &(prCtrlExptTxDoneInfo->num));
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_HIF_STATE:
+ {
+ TTY_CTRL_EXCP_HIF_STATE_T* prCtrlExptHifState;
+ prCtrlExptHifState = &(data->rTTYCtrlExcpHifState);
+ prCtrlExptHifState->hif_state = uart_ecpt_get_tx_state(dev); //HIF_STATE_NORMAL
+
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_ASSIGN_RX_GPD:
+ {
+ TTY_CTRL_EXCP_ASSIGN_RX_GPD_T* prCtrlExptAssignRxGpd;
+ prCtrlExptAssignRxGpd = &(data->rTTYCtrlExcpAssignRxGPD);
+ return_status = uart_ecpt_assign_rx_gpd(dev, prCtrlExptAssignRxGpd->first_gpd, prCtrlExptAssignRxGpd->last_gpd);
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_GET_RX_GPD:
+ {
+ TTY_CTRL_EXCP_GET_RX_GPD_T* prCtrlExptGetRxGpd;
+ prCtrlExptGetRxGpd = &(data->rTTYCtrlExcpGetRxGPD);
+ return_status = uart_ecpt_get_rx_gpd(dev, &(prCtrlExptGetRxGpd->first_gpd), &(prCtrlExptGetRxGpd->last_gpd), (kal_uint32 *) &(prCtrlExptGetRxGpd->num));
+ }
+ break;
+
+ case TTY_CMD_EXCEPTION_HIF_POLL:
+ {
+ TTY_CTRL_EXCP_HIF_POLL_T* pCtrlHifPoll;
+ pCtrlHifPoll = &(data->rTTYCtrlExcpHifPoll);
+ pCtrlHifPoll->reset_event = DCL_FALSE;
+ }
+ break;
+
+ default:
+ return STATUS_INVALID_CMD;
+ }
+
+ return return_status;
+}