[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/usim/inc/sim_al.h b/mcu/driver/devdrv/usim/inc/sim_al.h
new file mode 100644
index 0000000..c7c6f06
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_al.h
@@ -0,0 +1,209 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_al.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is used for including files for AL_SIM
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef SIM_AL_H
+#define SIM_AL_H
+
+//#define TEST /* test option for win32 simulation */
+/*Besnon 20040407 add for Jensen's request*/
+#define RESET_18V 0 /* Driver reset result = 1.8V */
+#define RESET_30V 1 /* Driver reset result = 3V */
+/*End Benson 20040407*/
+
+#define SIM_NO_ERROR 0 /* return value for SIM no error found */
+#define SIM_NO_INSERT 1 /* return value for no SIM insert */
+#define SIM_CARD_ERROR 3 /* return value for SIM error found */
+
+#define CLOCK_STOP_AT_HIGH 0x00 /* config SIM colck stop at high */
+#define CLOCK_STOP_AT_LOW 0x01 /* config SIM clock stop at low */
+#define CLOCK_STOP_NOT_ALLOW 0x02 /* config SIM clock stop not allowed */
+
+/* Define SIM command instruction ID */
+#define GSM_CLS 0xA0
+#define CMD_SELECT 0xA4
+#define CMD_GETRES 0xC0
+#define CMD_STATUS 0xF2
+#define CMD_READB 0xB0
+#define CMD_UPDATEB 0xD6
+#define CMD_READR 0xB2
+#define CMD_UPDATER 0xDC
+#define CMD_INCREASE 0x32
+#define CMD_VERIFYCHV 0x20
+#define CMD_CHANGECHV 0x24
+#define CMD_DISABLECHV 0x26
+#define CMD_ENABLECHV 0x28
+#define CMD_UNBLOCKCHV 0x2C
+#define CMD_INVALIDATE 0x04
+#define CMD_REHABILITATE 0x44
+#define CMD_RUNGSMALGO 0x88
+#define CMD_TERMINALPRO 0x10
+#define CMD_TERMINALRES 0x14
+#define CMD_ENVELOPE 0xC2
+#define CMD_FETCH 0x12
+
+/* define SIM file ID */
+#define SIM_DF_GSM 0x7F20
+#define SIM_DF_1800 0x7F21
+
+typedef enum
+{
+ ME_UNKNOW = 0,
+ ME_18V_30V,
+ ME_30V_ONLY,
+ ME_18V_ONLY
+} sim_env;
+
+typedef enum
+{
+ sim_card_normal_speed = 0,
+ sim_card_enhance_speed_64,
+ sim_card_enhance_speed_32,
+ sim_card_enhance_speed_16,
+ sim_card_enhance_speed_8
+} sim_card_speed_type;
+
+/* define ATR data Structure */
+typedef struct
+{
+ kal_uint8 info [40];
+} AtrStruct;
+
+#if !defined(DRV_MULTIPLE_SIM) && !defined(__SIM_DRV_MULTI_DRV_ARCH__)
+ /*this definition is only used when build old single SIM driver, the latest definitions are moved to sim_drv_sw_api.h*/
+ extern kal_uint8 L1sim_Reset(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info);
+ extern void L1sim_Configure(kal_uint8 clockMode);
+ extern kal_uint16 L1sim_Cmd(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error);
+ extern void L1sim_PowerOff(void);
+ extern void L1sim_Init(void);
+ extern sim_env SIM_GetCurrentEnv(void);
+#endif
+
+#endif /*SIM_AL_H*/
+
+
diff --git a/mcu/driver/devdrv/usim/inc/sim_ctrl_al.h b/mcu/driver/devdrv/usim/inc/sim_ctrl_al.h
new file mode 100644
index 0000000..ef5cf79
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_ctrl_al.h
@@ -0,0 +1,139 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_ctrl_al.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for common header files for different SIM controller drivers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if defined( DRV_MULTIPLE_SIM) && !defined(__SIM_DRV_MULTI_DRV_ARCH__)
+
+/*RHR*/
+#include "sim_sw_comm.h"
+#include "usim_MT6302.h"
+/*RHR*/
+
+#define SIM_MAX_INTERFACE 2 //maybe this should be defined in makefile
+typedef struct
+{
+ usim_status_enum(*reset)(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, kal_uint32 simInterface);
+ sim_status(*command)(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, kal_uint32 simInterface);
+ void (*powerOff)(kal_uint32 simInterface);
+ void (*getCardInfo)(sim_info_struct *info, kal_uint32 simInterface);
+ void (*enableEnhancedSpeed)(kal_bool enable, kal_uint32 simInterface);
+ void (*selectPreferPhyLayer)(sim_protocol_phy_enum T, kal_uint32 simInterface);
+ kal_bool(*setClockStopMode)(sim_clock_stop_enum mode, kal_uint32 simInterface);
+ void (*EOC)(kal_uint32 simInterface); /*use this to hook necessary action before return to SIM task, this is called by adaption layer, not SIM task*/
+ void (*addMessage)(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+} sim_ctrlDriver;
+
+#endif//DRV_MULTIPLE_SIM
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_HW_def_MTK.h b/mcu/driver/devdrv/usim/inc/sim_drv_HW_def_MTK.h
new file mode 100644
index 0000000..1c1abaf
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_HW_def_MTK.h
@@ -0,0 +1,658 @@
+#ifndef __SIM_DRV_HW_DEF_MTK_H__
+#define __SIM_DRV_HW_DEF_MTK_H__
+
+
+/* SIM_ADDDMA & NoT0CTRL can't active concurrently */
+#define SIM_ADDDMA
+
+/* SIM Format */
+#define SIM_direct 0
+#define SIM_indirect 1
+
+/* SIM Power */
+#define SIM_30V RESET_30V
+#define SIM_18V RESET_18V
+
+#define CMD_RECBUFSIZE 13
+/*DMA setting, such usb*/
+/* Size = 8bit, sinc en, dinc disable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimTxNormal 0x0074
+/* Size = 8bit, sinc disable, dinc enable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimRxNormal 0x0078
+
+/* SIM State */
+#define SIM_WAIT_FOR_ATR 0 /* reset SIM card and wait ATR */
+#define SIM_PROCESS_ATR 1 /* receiving ATR data */
+#define SIM_PROCESS_PTS 2 /* receiving PTS response data */
+#define SIM_PROCESSCMD 3
+#define SIM_SERIOUSERR 4 /* serous error due to txerr*/
+#define SIM_PWROFF 5
+#define SIM_WaitRejectDone 6
+
+
+/* SIM Miner State */
+#ifdef NoT0CTRL
+ #define SIMD_CmdIdle 0
+ #define SIM_WaitProcByte 1
+ #define SIM_AckDataState 2
+ #define SIM_NAckDataState 3
+ #define SIM_WaitSWByte 4
+#endif /*NoT0CTRL*/
+/*just for clock stop mode*/
+#define SIM_ProcessClk 5
+#define SIM_StopClk 6
+#define SIM_WaitCmdEnd 7
+
+
+/* Event */
+#define ATR_END 0x0100
+#define PTS_END 0x0008
+//#ifdef DCL_SIM_INTERFACE
+#define SIM_EVT_CMD_END 0x0004
+//#else
+//#define CMD_END 0x0004
+//#endif
+#define RST_READY 0x0002
+#define CLK_PROC 0x0020
+#define ACTIVATE_DONE 0x0040
+#define DEACTIVATE_DONE 0x0080
+#define SWRST_INT_END 0x0100
+
+
+/*#define INIRET 0x0001*/
+
+/*ATR data define*/
+#define TAMask 0x0010
+#define TBMask 0x0020
+#define TCMask 0x0040
+#define TDMask 0x0080
+
+/* Result */
+#define SIM_SUCCESS SIM_NO_ERROR
+#define SIM_NOREADY SIM_NO_INSERT
+#define SIM_CARDERR SIM_CARD_ERROR
+#define SIM_INITXERR 5
+#define SIM_INIPTSERR 6
+#define SIM_CMDTXERR 7 /* parity error */
+#define SIM_CMDRECERR 8
+#define SIM_CMDTOUT 9
+#define SIM_CLKPROC 10
+#define SIM_NULLTIMEOUT 11
+#define SIM_TS_INVALID 12
+#define SIM_NO_ATR 13
+#define SIM_RX_INVALID 14
+#define SIM_SWRST 15
+#define SIM_CLKSTOP 16
+#define SIM_GPT_TIMEOUT 17
+#define SIM_PTS_RX_INVALID 18
+#define SIM_OVERRUN 19
+
+#define SW1_GET_RESP_SIM 0x9f
+#define SW1_GET_RESP_USIM 0x61
+#define SW1_RESEND_USIM 0x6c
+#define LEN_INDEX 4 // index to the P3 of command header
+#define LEN_OF_CMD 5
+#define GET_RESP_CLA_SIM 0xa0
+#define GET_RESP_CLA_USIM 0x00
+#define SW1_WARN1 0x62
+#define SW1_WARN2 0x63
+//#ifdef DCL_SIM_INTERFACE
+#define SIM_SW_STATUS_OK 0x9000
+#define SIM_SW_STATUS_FAIL 0x00
+//#else
+//#define STATUS_OK 0x9000
+//#define STATUS_FAIL 0x00
+//#endif
+
+#define Speed372 0
+#define Speed64 1
+#define Speed32 2
+#define Speed16 3
+#define Speed8 4
+
+typedef kal_uint16 sim_status;
+
+#define SW1_GET_RESP_SIM 0x9f
+#define SW1_SIM_WARN1 0x9e
+#define SW1_GET_RESP_USIM 0x61
+#define SW1_RESEND_USIM 0x6c
+#define LEN_INDEX 4 // index to the P3 of command header
+#define LEN_OF_CMD 5
+#define GET_RESP_CLA_SIM 0xa0
+#define GET_RESP_CLA_USIM 0x00
+#define SW1_WARN1 0x62
+#define SW1_WARN2 0x63
+//#ifdef DCL_SIM_INTERFACE
+#define SIM_SW_STATUS_OK 0x9000
+#define SIM_SW_STATUS_FAIL 0x00
+
+#define MAX_SIM_ERROR_LINE 4
+
+
+
+typedef enum
+{
+ SIM_PROTOCOL,
+ USIM_PROTOCOL
+} sim_protocol_app_enum;
+
+typedef enum
+{
+ T0_PROTOCOL,
+ T1_PROTOCOL,
+ UNKNOWN_PROTOCOL
+} sim_protocol_phy_enum;
+
+typedef enum
+{
+ UNKNOWN_POWER_CLASS = 0,
+ CLASS_A_50V = 1,
+ CLASS_B_30V = 2,
+ CLASS_AB = 3,
+ CLASS_C_18V = 4,
+ ClASS_BC = 6,
+ CLASS_ABC = 7,
+ CLASS_ALLSUPPORT = 0xff
+} sim_power_enum;
+
+typedef enum
+{
+ CLOCK_STOP_NOT_SUPPORT = 0x0,
+ CLOCK_STOP_LOW = 0x40,
+ CLOCK_STOP_HIGH = 0x80,
+ CLOCK_STOP_ANY = 0xc0,
+ CLOCK_STOP_MSK = 0xc0,
+ CLOCK_STOP_UNKONW = 0x0f
+} sim_clock_stop_enum;
+
+typedef enum
+{
+ SPEED_372,
+ SPEED_64,
+ SPEED_32,
+ SPEED_16,
+ SPEED_8,
+ SPEED_RFU,
+ SPEED_MAX
+} sim_speed_enum;
+
+typedef enum
+{
+ SIM_DIRECT,
+ SIM_INVERSE
+} sim_dir_enum;
+
+typedef enum
+{
+ usim_case_1 = 1,
+ usim_case_2,
+ usim_case_3,
+ usim_case_4,
+ usim_case_2E,
+ usim_case_3E,
+ usim_case_4E
+} usim_cmd_case_enum;
+
+typedef enum
+{
+ USIM_DIRECT,
+ USIM_INVERSE
+} usim_dir_enum;
+
+typedef enum
+{
+ PPSS = 0, // initial character 0xFF
+ PPS0 = 1, // format character 0x1x
+ PPS1 = 2, // indicate the baudrate F, D
+ PCK = 3, // exclusive-or PPSS to PCK should be null
+ PPS_LEN = 4
+} usim_pts_enum;
+
+#define usim_protocol_enum sim_protocol_phy_enum
+#define usim_speed_enum sim_speed_enum
+#define usim_clock_stop_enum sim_clock_stop_enum
+#define usim_power_enum sim_power_enum
+
+typedef enum
+{
+ ERR_INVALID_BLOCK,
+ ERR_TIMEOUT
+} usim_err_enum;
+
+typedef enum
+{
+ USIM_RESET_NEGOTIABLE, // type 1
+ USIM_RESET_SPECIFIC // type 2
+} usim_reset_type_enum;
+
+typedef enum
+{
+ IDLE_STATE,
+ ACTIVATION_STATE,
+ ATR_STATE,
+ PTS_STATE,
+ MAIN_CMD_READY_STATE,
+ CMD_TX_STATE,
+ //CMD_RX_HEADER_STATE,
+ CMD_RX_BLOCK_REC_STATE,
+ //CMD_RX_S_BLOCK_STATE,
+ CMD_RX_STATE,
+ CLK_STOPPING_STATE,
+ CLK_STOPPED_STATE,
+ DEACTIVATION_STATE
+} usim_main_state_enum;
+
+typedef enum
+{
+ EVENT_TX = 0x1,
+ EVENT_RX = 0x2,
+ EVENT_OV = 0x4,
+ EVENT_TOUT = 0x8,
+ EVENT_TXERR = 0x10,
+ EVENT_NATR = 0x20,
+ EVENT_OFF = 0x40,
+ EVENT_T0END = 0x80,
+ EVENT_RXERR = 0x100,
+ EVENT_T1END = 0x200,
+ EVENT_EDCERR = 0x400
+} usim_event_type_enum;
+
+typedef enum
+{
+ USIM_NO_ERROR = 0,
+
+ // expected status
+ USIM_WAITING_EVENT = 1, // initial wait event status
+ USIM_BLOCK_REC = 2, // successfully received a complete block
+ USIM_POWER_OFF = 3, // successfully powered off
+ USIM_ATR_REC = 4, // successfully reveived all ATR
+ USIM_S_BLOCK_REC = 5, // successfully reveived S RESP
+
+ // error status
+ USIM_NO_INSERT = -1,
+ USIM_VOLT_NOT_SUPPORT = -2,
+ USIM_NO_ATR = -3,
+ USIM_TS_INVALID = -4,
+ USIM_ATR_ERR = -5,
+ USIM_INVALID_ATR = -6,
+ USIM_PTS_FAIL = -7,
+ USIM_RX_INVALID = -8, // EDC error or parity error
+ USIM_BWT_TIMEOUT = -9,
+ USIM_DATA_ABORT = -10,
+ USIM_DEACTIVATED = -11,
+ USIM_S_BLOCK_FAIL = -12,
+ USIM_INVALID_WRST = -13,
+ USIM_GPT_TIMEOUT = -14,
+ USIM_PTS_TIMEOUT = -15,
+ USIM_PTS_RX_INVALID = -16
+} usim_status_enum;
+
+typedef enum
+{
+ USIM_CMD_READY,
+ I_BLOCK_RX,
+ I_BLOCK_TX,
+ I_BLOCK_M0_RX,
+ I_BLOCK_M0_TX,
+ I_BLOCK_M1_RX,
+ I_BLOCK_M1_TX,
+ R_BLOCK_RX,
+ R_BLOCK_TX,
+ S_BlOCK_REQ_RX,
+ S_BlOCK_REQ_TX,
+ S_BlOCK_RESP_RX,
+ S_BlOCK_RESP_TX
+} usim_cmd_state_enum;
+
+typedef enum
+{
+ T1_NAD_INDEX = 0,
+ T1_PCB_INDEX = 1,
+ T1_LEN_INDEX = 2,
+ T1_INF_INDEX = 3,
+ T1_EDC_INDEX = 4
+} usim_t1_header_index_enum;
+
+typedef enum
+{
+ SIM_NORMAL = 0,
+ SIM_SLOW_CLOCK,
+ SIM_FORCE_3V,
+ SIM_CLOCK_FETCH__TERMINAL_RESPONSE,
+ SIM_3_25MHZ_ONLY
+} usim_process_hitorical_enum;
+
+typedef enum
+{
+ SIM_ASSERT_REASON_WRONG_OWNERTASK = 0x00,
+} usim_assert_reason;
+
+typedef enum
+{
+ SIM_ASSERT_OWNER_SIMTASK = 0x00,
+} usim_assert_owner;
+
+#if defined(SIM_DRV_IC_USB)
+typedef enum
+{
+ SIM_ICUSB_INIT,
+ SIM_ICUSB_SETVOLT,
+ SIM_ICUSB_ENABLESESSION,
+ SIM_ICUSB_POWERON,
+ SIM_ICUSB_CMD,
+ SIM_ICUSB_POWEROFF,
+ SIM_ICUSB_DISABLESESSION,
+ SIM_ICUSB_DEINIT,
+ SIM_ICUSB_ERRORHANDLING,
+} usim_icusb_state_enum;
+
+typedef enum
+{
+ SIM_ICUSB_ACK_OK = 0x00,
+ SIM_ICUSB_ACK_PREFER_3V = 0x10,
+ SIM_ICUSB_ACK_CMD_EN_SESSION_ERROR = 0xEA,
+ SIM_ICUSB_ACK_SET_VOLTAGE_ERROR = 0xEB,
+ SIM_ICUSB_ACK_CMD_TYPE_ERROR = 0xEC,
+ SIM_ICUSB_ACK_NEED_RX_TO_ACK = 0xEE,
+ SIM_ICUSB_ACK_CMD_ERROR = 0xFD,
+ SIM_ICUSB_ACK_TIMEOUT = 0xFE,
+ SIM_ICUSB_ACK_NO_CARD = 0xFF,
+
+ // error status
+ SIM_ICUSB_CCCI_CMD_EN_SESSION_ERROR = 0x1000,
+ SIM_ICUSB_CCCI_SET_VOLTAGE_ERROR,
+ SIM_ICUSB_CCCI_CMD_TYPE_ERROR,
+ SIM_ICUSB_CCCI_NEED_RX_TO_ACK,
+ SIM_ICUSB_CCCI_CMD_ERROR,
+ SIM_ICUSB_CCCI_TIMEOUT,
+ SIM_ICUSB_CCCI_NO_CARD,
+} usim_icusb_ackStatus;
+
+#define SIM_ICUSB_CONTROL_MESSAGE_LEN 0x9
+#define SIM_ICUSB_MESSAGE_HEADER_LEN 0x6
+#define TB15_ICUSB_MASK 0xC0
+#define SIM_ICUSB_CONTROL_MESSAGE_TYPE 0x80
+#define SIM_ICUSB_DATA_MESSAGE_TYPE 0x80
+
+#endif
+
+
+// definitions
+#define SELECT_PW_RETRY 3
+#define SELECT_DIR_RETRY 2
+#define ATR_RETRY 3
+#define INVALID_RETRY 3
+#define RESYNC_RETRY 3
+#define IFS_RETRY 2
+#define USIM_IFSD_MAX 0xFE
+
+#define FI_DEFAULT 372
+#define DI_DEFAULT 1
+#define INIT_WWT_T0 (9600+400) // etu (initial work waiting time) +400 to cover some slow card
+
+#define TOUT_OFFSET 0x04 // apply a offset to all timeout settings (4*16 = 64 etu), the unit of mt6290 is 16
+#define BGT_T1 22 // etu (block guard time)
+#define NAD 0 // node address byte
+
+#define SIM_DEFAULT_TOUT_VALUE 0x260
+//#define SIM_DEFAULT_TOUT_VALUE 0x983
+#define SIM_CMD_TOUT_VALUE 0x1400 //mtk04122: not used....
+
+// coding of PCB for I-block (0xxxxxxx)
+#define PCB_I_BIT8 0x80 // I-block must be 0, others(R,S) are 1
+#define PCB_I_SEQ 0x40 // sequence number
+#define PCB_I_M 0x20 // chaining more data bit(M)
+#define PCB_I_RFU 0x1F // RFU should be zero
+
+// coding of PCB for R-block (100xxxxx)
+#define PCB_R_N1 0x90
+#define PCB_R_N0 0x80
+#define PCB_R_BIT7 0x40 // R: 0, S:1, use to distinguish R-block with S-block
+#define PCB_R_SEQ 0x10 // sequence number
+#define PCB_R_STATUS 0x0f // 0: error free, 1:EDC or parity error, 2: other errors
+#define PCB_R_STATUS_EDC_ERR 0x1
+#define PCB_R_STATUS_OTHER_ERR 0x2
+#define PCB_R_STATUS_OK 0x0
+#define PCB_R_DEFAULT 0xe0
+
+// coding of PCB for S-block (11xxxxxx)
+#define PCB_S_DEFAULT 0xc0
+#define PCB_S_RESP 0x20 // 1: a response, 0: a request
+#define PCB_S_ID 0x1f
+
+
+#define LEN_MIN_T1 0
+#define LEN_MAX_T1 254
+#define USIM_IFSC_DEFAULT 32
+#define USIM_IFSD_DEFAULT 32
+#define USIM_CWT_DEFAULT 8203 // (11 + 1>>13) etu
+#define USIM_BWT_DEFAULT 15360 // (1<<4)*960
+#define USIM_POW_CLASS_MSK 0x3f // TAi bit 1~6
+#define USIM_PTS_PS1_MSK 0x10
+#define USIM_PTS_PS0_T1 0x1 // select T1 protocol
+#define USIM_NAD_DEFAULT 0x0
+
+#define USIM_EVENT 0x1
+
+#define ATR_TA1_372_5 0x11
+#define ATR_TA1_372_4 0x01
+#define ATR_TA1_64 0x94
+#define ATR_TA1_32 0x95
+#define ATR_TA1_16 0x96 //speed 16
+#define ATR_TA1_8 0x97 //speed 8
+
+
+#define USIM_RETRY 3
+#define INDEX_COUNT 4 // the count of the wline and sline
+#define MAX_BWI 9
+#define MAX_CWI 16
+#define SIM_TOTAL_FIFO_LEN 16 // excep 6208
+#define HIST_FIRST_USIM 0x80 // the first of the historical character of USIM
+#define HIST_SEC_USIM 0x31 // the second of the historical character of USIM
+#define HIST_FOUR_USIM 0x73 // the fourth of the historical character of USIM
+#define USIM_DMA_MAX_SIZE 260
+#define USIM_GPT_TIMEOUT_PERIOD 500 // x 10ms
+
+typedef enum
+{
+ RESYNC_REQ = PCB_S_DEFAULT,
+ IFS_REQ = (PCB_S_DEFAULT | 1),
+ ABORT_REQ = (PCB_S_DEFAULT | 2),
+ WTX_REQ = (PCB_S_DEFAULT | 3),
+ RESYNC_RESP = RESYNC_REQ | PCB_S_RESP,
+ IFS_RESP = IFS_REQ | PCB_S_RESP,
+ ABORT_RESP = ABORT_REQ | PCB_S_RESP,
+ WTX_RESP = WTX_REQ | PCB_S_RESP
+} usim_s_block_id_enum;
+
+typedef enum
+{
+ SIM_DRIVER_ACT = 0x00000001,
+ SIM_DRIVER_DEACT = 0x00000002,
+ SIM_PDNDIS = 0x00000003,
+ SIM_PDNEN = 0x00000004,
+ SIM_INT_SIM = 0x00000005,
+ SIM_INT_USIM = 0x00000006,
+ SIM_DRIVER_ACT_SIMD = 0x00000007,
+ SIM_DRIVER_DEACT_SIMD = 0x00000008,
+ SIM_CMD_TX_LOG = 0x00010001,
+ SIM_CMD_INS_LOG = 0x00010002,
+ SIM_CMD_TXDELAY = 0x00010003,
+ SIM_INIT_USIM = 0x00020001,
+ SIM_DEACTIVATE_1 = 0x00030001,
+ SIM_DEACTIVATE_2 = 0x00030002,
+ SIM_ACTION_RESET = 0x000F0001,
+ SIM_ACTION_POWOFF = 0x000F0002,
+ SIM_ACTION_COMMAND = 0x000F0003,
+ SIM_ACTION_EOC = 0x000F0004
+} sim_msgTag;
+
+
+typedef enum
+{
+ /*following is error*/
+ SIM_PRINT_DUMP_ERROR_LINE,
+ SIM_PRINT_RESET_NOATR_FAIL,
+ SIM_PRINT_RESET_FAIL_WITH_TS_HSK_ENABLE,
+ SIM_PRINT_RESET_FAIL_RESULT,
+ SIM_PRINT_SIM_CMD_FAIL_STATUS,
+ SIM_PRINT_CMD_FAIL_RESULT_STATUS,
+ SIM_PRINT_RECEIVE_ERR_1,
+ SIM_PRINT_RECEIVE_ERR_2,
+ SIM_PRINT_TCK_CHECKSUM_ERR,
+ SIM_PRINT_HISTORICAL_BYTE_ERR,
+ SIM_PRINT_L1USIM_RESET_FAIL,
+
+ /*following is information*/
+ SIM_PRINT_INFO_BASE = 1000,
+ SIM_PRINT_RESET_OK_POWER_SPEED,
+ SIM_PRINT_NULL_TIME_OUT,
+ SIM_PRINT_NULL_BYTE,
+ SIM_PRINT_NON_NULL_BYTE,
+ SIM_PRINT_9000_ON_SELECT,
+ SIM_PRINT_6100_FROM_CARD,
+ SIM_PRINT_CHECK_TCK,
+ SIM_PRINT_TCK_NOT_PRESENT,
+ SIM_PRINT_TCK_CHECKSUM_OK,
+ SIM_PRINT_IR_CARD,
+ SIM_PRINT_INDIRECT_CARD,
+ SIM_PRINT_L1USIM_RST_OK,
+
+ SIM_PRINT_L1SIM_CMD_TRC1 = 1101,
+ SIM_PRINT_L1SIM_CMD_TRC2,
+ SIM_PRINT_L1SIM_CMD_TRC3,
+ SIM_PRINT_L1SIM_CMD_TRC4,
+ SIM_PRINT_L1SIM_CMD_TRC5,
+ SIM_PRINT_L1SIM_CMD_TRC6,
+ SIM_PRINT_L1SIM_CMD_TRC7,
+ SIM_PRINT_L1SIM_CMD_TRC8,
+ SIM_PRINT_L1SIM_CMD_TRC9,
+
+ SIM_PRINT_L1SIM_CMD_TRC10 = 1110,
+ SIM_PRINT_L1SIM_CMD_TRC11,
+ SIM_PRINT_L1SIM_CMD_TRC12,
+ SIM_PRINT_L1SIM_CMD_TRC13,
+ SIM_PRINT_L1SIM_CMD_TRC14,
+ SIM_PRINT_L1SIM_CMD_TRC15,
+ SIM_PRINT_L1SIM_CMD_TRC16,
+ SIM_PRINT_L1SIM_CMD_TRC17,
+ SIM_PRINT_L1SIM_CMD_TRC18,
+ SIM_PRINT_L1SIM_CMD_TRC19,
+
+ SIM_PRINT_L1SIM_CMD_TRC20 = 1120,
+ SIM_PRINT_L1SIM_CMD_TRC21,
+ SIM_PRINT_L1SIM_CMD_TRC22,
+ SIM_PRINT_L1SIM_CMD_TRC23,
+ SIM_PRINT_L1SIM_CMD_TRC24,
+ SIM_PRINT_L1SIM_CMD_TRC25,
+ SIM_PRINT_L1SIM_CMD_TRC26,
+ SIM_PRINT_L1SIM_CMD_TRC27,
+ SIM_PRINT_L1SIM_CMD_TRC28,
+ SIM_PRINT_L1SIM_CMD_TRC29,
+
+ SIM_PRINT_L1SIM_CMD_TRC30 = 1130,
+ SIM_PRINT_L1SIM_CMD_TRC31,
+ SIM_PRINT_L1SIM_CMD_TRC32,
+ SIM_PRINT_L1SIM_CMD_TRC33,
+ SIM_PRINT_L1SIM_CMD_TRC34,
+ SIM_PRINT_L1SIM_CMD_TRC35,
+ SIM_PRINT_L1SIM_CMD_TRC36,
+ SIM_PRINT_L1SIM_CMD_TRC37,
+ SIM_PRINT_L1SIM_CMD_TRC38,
+ SIM_PRINT_L1SIM_CMD_TRC39,
+
+ SIM_PRINT_L1SIM_CMD_TRC40 = 1140,
+ SIM_PRINT_L1SIM_CMD_TRC41,
+ SIM_PRINT_L1SIM_CMD_TRC42,
+ SIM_PRINT_L1SIM_CMD_TRC43,
+ SIM_PRINT_L1SIM_CMD_TRC44,
+ SIM_PRINT_L1SIM_CMD_TRC45,
+ SIM_PRINT_L1SIM_CMD_TRC46,
+ SIM_PRINT_L1SIM_CMD_TRC47,
+ SIM_PRINT_L1SIM_CMD_TRC48,
+ SIM_PRINT_L1SIM_CMD_TRC49,
+
+ SIM_PRINT_L1SIM_CMD_TRC50 = 1150,
+ SIM_PRINT_L1SIM_CMD_TRC51,
+ SIM_PRINT_L1SIM_CMD_TRC52,
+ SIM_PRINT_L1SIM_CMD_TRC53,
+ SIM_PRINT_L1SIM_CMD_TRC54,
+ SIM_PRINT_L1SIM_CMD_TRC55,
+ SIM_PRINT_L1SIM_CMD_TRC56,
+ SIM_PRINT_L1SIM_CMD_TRC57,
+ SIM_PRINT_L1SIM_CMD_TRC58,
+ SIM_PRINT_L1SIM_CMD_TRC59,
+
+ SIM_PRINT_L1SIM_CMD_TRC60 = 1160,
+ SIM_PRINT_L1SIM_CMD_TRC61,
+ SIM_PRINT_L1SIM_CMD_TRC62,
+ SIM_PRINT_L1SIM_CMD_TRC63,
+ SIM_PRINT_L1SIM_CMD_TRC64,
+ SIM_PRINT_L1SIM_CMD_TRC65, //last
+ SIM_PRINT_L1SIM_CMD_TRC66,
+ SIM_PRINT_L1SIM_CMD_TRC67,
+ SIM_PRINT_L1SIM_CMD_TRC68,
+ SIM_PRINT_L1SIM_CMD_TRC69,
+ SIM_PRINT_L1SIM_CMD_TRC70,
+ SIM_PRINT_L1SIM_CMD_TRC71,
+ SIM_PRINT_L1SIM_CMD_TRC72,
+ SIM_PRINT_L1SIM_CMD_TRC73,
+ SIM_PRINT_L1SIM_CMD_TRC74,
+ SIM_PRINT_L1SIM_CMD_TRC75,
+ SIM_PRINT_L1SIM_CMD_TRC76,
+ SIM_PRINT_L1SIM_CMD_TRC77,
+ SIM_PRINT_L1SIM_CMD_TRC78,
+ SIM_PRINT_L1SIM_CMD_TRC79,
+ SIM_PRINT_L1SIM_CMD_TRC80,
+ SIM_PRINT_L1SIM_CMD_TRC81,
+ SIM_PRINT_L1SIM_CMD_TRC82,
+ SIM_PRINT_L1SIM_CMD_TRC83,
+ SIM_PRINT_L1SIM_CMD_TRC84,
+ SIM_PRINT_L1SIM_CMD_TRC85,
+ SIM_PRINT_L1SIM_CMD_TRC86,
+ SIM_PRINT_L1SIM_CMD_TRC87,
+ SIM_PRINT_L1SIM_CMD_TRC88,
+ SIM_PRINT_L1SIM_CMD_TRC89,
+ SIM_PRINT_L1SIM_CMD_TRC90,
+ SIM_PRINT_L1SIM_CMD_TRC91,
+ SIM_PRINT_L1SIM_CMD_TRC92,
+ SIM_PRINT_L1SIM_CMD_TRC93,
+ SIM_PRINT_L1SIM_CMD_TRC94,
+ SIM_PRINT_L1SIM_CMD_TRC95,
+ SIM_PRINT_L1SIM_CMD_TRC96,
+ SIM_PRINT_L1SIM_CMD_TRC97,
+ SIM_PRINT_L1SIM_CMD_TRC98,
+ SIM_PRINT_L1SIM_CMD_TRC99,
+ SIM_PRINT_L1SIM_CMD_TRC100,
+ SIM_PRINT_L1SIM_CMD_TRC101,
+ SIM_PRINT_L1SIM_CMD_TRC102,
+ SIM_PRINT_L1SIM_CMD_TRC103,
+ SIM_PRINT_L1SIM_CMD_TRC104,
+ SIM_PRINT_L1SIM_CMD_TRC105,
+ SIM_PRINT_L1SIM_CMD_TRC106,
+ SIM_PRINT_L1SIM_CMD_TRC107,
+ SIM_PRINT_L1SIM_CMD_TRC108,
+ SIM_PRINT_L1SIM_CMD_TRC109,
+ SIM_PRINT_L1SIM_CMD_TRC110,
+ SIM_PRINT_L1SIM_CMD_TRC111,
+ SIM_PRINT_L1SIM_CMD_TRC112,
+ SIM_PRINT_L1SIM_CMD_TRC113,
+ SIM_PRINT_L1SIM_CMD_TRC114,
+ SIM_PRINT_L1SIM_CMD_TRC115,
+ SIM_PRINT_L1SIM_CMD_TRC116,
+ SIM_PRINT_L1SIM_CMD_TRC117,
+ SIM_PRINT_L1SIM_CMD_TRC118,
+ SIM_PRINT_L1SIM_CMD_TRC119,
+ SIM_PRINT_L1SIM_CMD_TRC120,
+ SIM_PRINT_L1SIM_CMD_TRC121,
+ SIM_PRINT_L1SIM_CMD_TRC122,
+ SIM_PRINT_L1SIM_CMD_TRC123,
+ SIM_PRINT_L1SIM_CMD_TRC124,
+ SIM_PRINT_L1SIM_CMD_TRC125,
+ SIM_PRINT_L1SIM_CMD_TRC126,
+ SIM_PRINT_L1SIM_CMD_TRC127,
+ SIM_PRINT_L1SIM_CMD_TRC128,
+ SIM_PRINT_L1SIM_CMD_TRC129,
+ SIM_PRINT_L1SIM_CMD_TRC130,
+} sim_printEnum;
+#endif /*__SIM_DRV_HW_DEF_MTK_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_HW_reg_MTK.h b/mcu/driver/devdrv/usim/inc/sim_drv_HW_reg_MTK.h
new file mode 100644
index 0000000..0405876
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_HW_reg_MTK.h
@@ -0,0 +1,1165 @@
+#ifndef __SIM_DRV_HW_REG_MTK_H__
+#define __SIM_DRV_HW_REG_MTK_H__
+
+
+
+#ifdef SIM_base
+ #undef SIM_base
+#endif
+#define SIM_base SIM0_base
+
+#ifdef SIM2_base
+ #undef SIM2_base
+#endif
+#define SIM2_base SIM1_base
+
+
+
+
+#define ACK_NULL_CHAR 0x60
+
+#define SIM_CTRL (SIM_base+0x0)
+#define SIM_CONF (SIM_base+0x4)
+#define SIM_BRR (SIM_base+0x8)
+#define SIM_IRQEN (SIM_base+0x10)
+#define SIM_STS (SIM_base+0x14)
+
+#define SIM_RETRY (SIM_base+0x20)
+#define SIM_TIDE (SIM_base+0x24)
+
+#define SIM_DATA (SIM_base+0x30)
+#define SIM_COUNT (SIM_base+0x34)
+
+#define SIM_ATIME (SIM_base+0x40)
+#define SIM_DTIME (SIM_base+0x44)
+#define SIM_TOUT (SIM_base+0x48)
+
+#define SIM_INS (SIM_base+0x60)
+#define SIM_IMP3 (SIM_base+0x64)
+#define SIM_SW1 (SIM_base+0x68)
+#define SIM_SW2 (SIM_base+0x6c)
+#define SIM_REG_STATUS (SIM_base+0x74)
+
+
+/*
+ This is the most important define to combine single SIM and multiple SIM macro.
+ In DRV_SIM_ALL_SOLUTION_BUILT, single SIM driver's macro will use this variable, too.
+ DRV_SIM_BUILD_SINGLE_SIM is only defined in simd.c and usim_drv.c before including this header file.
+*/
+extern kal_uint32 simBaseAddr, simBaseAddrSpace;
+#ifdef DRV_SIM_BUILD_SINGLE_SIM
+ #define SIM0_BASE_ADDR_MTK (simBaseAddr )
+#else
+ /*in DRV_SIM_ALL_SOLUTION_BUILT, we use two variables, starting address and adress space, to calculate the actual address*/
+ //#define SIM0_BASE_ADDR_MTK (simBaseAddr + (simBaseAddrSpace * simInterface))
+ #define SIM0_BASE_ADDR_MTK (hw_cb->mtk_baseAddr)
+#endif
+
+// MTK04122: updated for MT6290
+#define SIM_VERSION_MTK 0x0
+#define SIM_CTRL_MTK 0x10
+#define SIM_CONF_MTK 0x14
+#define SIM_CONFSTA_MTK 0x18
+#define SIM_BRR_MTK 0x1C
+#define SIM_IRQEN_MTK 0x20
+#define SIM_STS_MTK 0x24
+
+#define SIM_RETRY_MTK 0x30
+#define SIM_TIDE_MTK 0x34
+
+#define SIM_DATA_MTK 0x40
+#define SIM_COUNT_MTK 0x44
+
+#if !defined(DRV_SIM_6293_SERIES) && !defined(DRV_SIM_6295_SERIES) && !defined(DRV_SIM_6297_SERIES)
+ #define SIM_ATIME_MTK 0x50
+#endif
+#define SIM_DTIME_MTK 0x54
+#define SIM_TOUT_MTK 0x58
+
+#define SIM_GTIME_MTK 0x5C
+#define SIM_ETIME_MTK 0x60
+#define SIM_EXT_TIME_MTK 0x64
+#define SIM_CGTIME_MTK 0x68
+
+
+/********************/
+//MTK04122: be removed in mt6290
+#define SIM_INS_MTK 0x60
+#define SIM_IMP3_MTK 0x64
+/********************/
+
+#define SIM_COMDCTRL_MTK 0x70
+#define SIM_COMDLEN_MTK 0x74
+#define SIM_LEFTLEN_MTK 0x78
+
+#define SIM_SW1_MTK 0x7C
+#define SIM_SW2_MTK 0x80
+
+#define SIM_ATRSTA_MTK 0x90
+#define SIM_STATUS_MTK 0x94
+#define SIM_DBG_MTK 0x98
+#define SIM_DBGDATA_MTK 0x9C
+
+/*************** since Gen93 ***************/
+#if defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES)|| defined(DRV_SIM_6297_SERIES)
+ #define SIM_ATIME1_MTK 0xB0
+ #define SIM_ATIME2_MTK 0xB4
+ #define SIM_ATIME3_MTK 0xB8
+ #define SIM_ATIME4_MTK 0xBC
+ #define SIM_ATIME_MTK SIM_ATIME1_MTK
+
+ #define SIM_SIMOE_MODE_MTK 0xC0
+ #define SIM_MANUAL_CTRL_MTK 0xA4
+#endif
+/*******************************************/
+/*************** since Gen95 ***************/
+#if defined(SIM_DRV_PRINT_DEBUG1_2)
+#define SIM_DEBUG1_MTK 0xD0
+#define SIM_DEBUG2_MTK 0xD4
+#endif
+/*******************************************/
+
+//SIM_CTRL
+#define SIM_CTRL_SIMON 0x0001
+#define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+#define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+#define SIM_CTRL_RSTLV 0x0008
+#define SIM_CTRL_RSTCTRL 0x0010
+#define SIM_CTRL_IFCLR 0x0020
+
+//SIM_CONF
+#define SIM_CONF_RXHSK 0x0001
+#define SIM_CONF_TXHSK 0x0002
+#define SIM_CONF_CLKPO 0x0004
+
+/********************/
+//MTK04122: be removed in mt6290
+#define SIM_CONF_SINV 0x0008
+#define SIM_CONF_SDIR 0x0010
+#define SIM_CONF_ODDPARITY 0x0020
+
+#define SIM_CONF_Direct 0x0000
+#define SIM_CONF_InDirect 0x0038
+/********************/
+#define SIM_CONF_CONV 0x0008
+
+#define SIM_CONF_SIMSEL 0x0010
+#define SIM_CONF_TOUTEN 0x0020
+#define SIM_CONF_T1EN 0x0040
+#define SIM_CONF_T0EN 0x0080
+#define SIM_CONF_HFEN 0x0100
+#define SIM_CONF_RXRDIS 0x0200
+#define SIM_CONF_TXRDIS 0x0400
+#define SIM_CONF_T1TX2RXEN 0x0800
+
+//SIM_CONFSTA
+#define SIM_CONFSTA_IFCLR_ON 0x0001
+#define SIM_CONFSTA_TXRDIS_S 0x0400
+
+//SIM_BRR
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+#define SIM_BRR_CLKMSK 0x3803
+#else
+#define SIM_BRR_CLKMSK 0x0003
+#endif
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ #define SIM_BRR_CLK_Div6 0x0000
+ #define SIM_BRR_CLK_Div8 0x0001
+ #define SIM_BRR_CLK_Div16 0x0002
+ #define SIM_BRR_CLK_Div32 0x0003
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+ #define SIM_BRR_CLK_Div7 0x0800
+#endif
+#else
+ /********************/
+ //MTK04122: be removed in mt6290
+ #define SIM_BRR_CLK_Div2 0x0000
+ /********************/
+
+ #define SIM_BRR_CLK_Div4 0x0001
+ #define SIM_BRR_CLK_Div8 0x0002
+ #define SIM_BRR_CLK_Div12 0x0003
+#endif
+
+#define SIM_BRR_ETUMSK 0x07FC
+
+//MTK04122:need to clarify
+#define SIM_BRR_BAUDMSK 0x000C
+
+
+#define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1
+#define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8
+#define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16
+#define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32
+#define SIM_BRR_BAUD_Div8 (8<<2) //F=512,D=64
+
+//SIM_IRQEN
+#define SIM_IRQEN_TX 0x0001
+#define SIM_IRQEN_RX 0x0002
+#define SIM_IRQEN_OV 0x0004
+#define SIM_IRQEN_TOUT 0x0008
+#define SIM_IRQEN_TXERR 0x0010
+#define SIM_IRQEN_NATR 0x0020
+#define SIM_IRQEN_SIMOFF 0x0040
+#define SIM_IRQEN_T0END 0x0080
+#define SIM_IRQEN_RXERR 0x0100
+#define SIM_IRQEN_T1END 0x0200
+#define SIM_IRQEN_EDCERR 0x0400
+#define SIM_IRQEN_UDRUN 0x0800
+
+/*TX, RX ,OV, TOUT, TXER, NATR, SIMOFF, RXER*/
+#define SIM_IRQEN_ALL 0x01bf
+#define SIM_IRQEN_ALLOFF 0x0000
+
+/* SIM_IRQEN_RXErr, SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT, SIM_IRQEN_OV, SIM_IRQEN_RX*/
+#define SIM_IRQEN_Normal 0x013e
+
+/*SIM_IRQEN_RXERR, SIM_IRQEN_T0END,SIM_IRQEN_TXErr, SIM_IRQEN_TOUT, SIM_IRQEN_OV, SIM_IRQEN_RX*/
+#define SIM_IRQEN_CMDNormal 0x019e
+/*#define SIM_IRQEN_CMDNormal 0x019c*/
+
+/*SIM_IRQEN_RXERR, SIM_IRQEN_T0END,SIM_IRQEN_TXErr, SIM_IRQEN_TOUT, SIM_IRQEN_OV*/
+#define SIM_IRQEN_CMDDMANormal 0x019c
+
+#define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR)
+#define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR)
+#define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \
+ SIM_STS_OV|SIM_STS_TOUT)
+#define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX)
+#define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END)
+
+//SIM_STS
+#define SIM_STS_TX 0x0001
+#define SIM_STS_RX 0x0002
+#define SIM_STS_OV 0x0004
+#define SIM_STS_TOUT 0x0008
+#define SIM_STS_TXERR 0x0010
+#define SIM_STS_NATR 0x0020
+#define SIM_STS_SIMOFF 0x0040
+#define SIM_STS_T0END 0x0080
+#define SIM_STS_RXERR 0x0100
+#define SIM_STS_T1END 0x0200
+#define SIM_STS_EDCERR 0x0400
+#define SIM_STS_UDRUN 0x0800
+
+//SIM_TOUT
+#define SIM_TOUT_MSK 0x3fff //??
+
+//SIM_RETRY
+#define SIM_RETRY_RXMASK 0x0007
+#define SIM_RETRY_TXMASK 0x0700
+
+//SIM_TIDE
+#define SIM_TIDE_RXMASK 0x000f
+#define SIM_TIDE_TXMASK 0x0f00
+
+//SIM_COUNT
+#define SIM_COUNT_MASK 0x001f
+
+//SIM_COMDCTRL: shall be re-named
+#define SIM_INS_MASK 0x00ff
+#define SIM_INS_INSD 0x0100
+#define SIM_INS_START 0x8000
+
+//SIM_COMDLEN
+#define SIM_IMP3_MASK 0x00ff
+
+//SIM_ATRSTA
+#define SIM_ATRSTA_OFF 0x0001
+#define SIM_ATRSTA_IR 0x0080
+#define SIM_ATRSTA_AL 0x0100
+
+/*MTK04122: to be update for mt6290 (TBC)*/
+// SIM_STATUS
+#define SIM_STATUS_EDC 0x40
+#define SIM_STATUS_ACK 0x20
+#define SIM_STATUS_NACK 0x10
+#define SIM_STATUS_IDLE 0x01
+#define SIM_STATUS_INS 0x02
+#define SIM_STATUS_SW1 0x04
+#define SIM_STATUS_SW2 0x08
+
+#define SIM_TX_DELAY_LEN 0x4
+#define SIM_TX_DELAY_LOOP 4000
+
+#define SIM_SIMOE_ENABLE 0x1
+/*
+ * HDMA Register Definitions
+ */
+#define BASE_HDMA BASE_ADDR_MDGDMA
+#define REG_HDMA_HDCSR0 (BASE_HDMA + 0x0100)
+#define HDMA_MODE_0 (1 << 9) //channel 0
+#define HDMA_MODE_1 (1 << 25) //channel 1
+#define REG_HDMA_HDSR (BASE_HDMA + 0x0120) // shared
+#define HDMA_STAT0_0 (1 << 0) // buffer 0, channel 0
+#define HDMA_STAT0_1 (1 << 1) // buffer 0, channel 1
+#define HDMA_STAT1_0 (1 << 16) // buffer 1, channel 0
+#define HDMA_STAT1_1 (1 << 17) // buffer 1, channel 1
+#define REG_HDMA_HDCPR (BASE_HDMA + 0x0124) // shared
+#define HDMA_HCURR_PTR_0 (1 << 0) // channel 0
+#define HDMA_HCURR_PTR_1 (1 << 1) // channel 1
+#define REG_HDMA_HDCTRR0 (BASE_HDMA + 0x0140) // channel 0
+#define REG_HDMA_HDCTRR1 (BASE_HDMA + 0x0160) // channel 1
+#define HDCTRR_STOP (1 << 2)
+#define HDCTRR_MEM_BUS_WIDTH(n) ((n) << 4)
+#define HDCTRR_DEV_BUS_WIDTH(n) ((n) << 6)
+#define HDCTRR_BUS_WIDTH_8 0
+#define HDCTRR_BUS_WIDTH_16 1
+#define HDCTRR_BUS_WIDTH_32 2
+#if defined(DRV_SIM_6290_SERIES) || defined(DRV_SIM_6291_SERIES) || defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES)
+#define HDCTRR_BST_SIZE(n) ((n) << 13)
+#else
+#define HDCTRR_BST_SIZE(n) ((n) << 12)
+#endif
+#define HDCTRR_BST_SIZE_4 2
+#define HDCTRR_BST_SIZE_8 3
+#define HDCTRR_BST_SIZE_16 4
+#define HDCTRR_BST_SIZE_32 5 // reserved
+#define HDCTRR_BST_SIZE_64 6 // reserved
+#define HDCTRR_BST_SIZE_128 7 // reserved
+#define HDCTRR_RX_SEL0(n) ((n) << 30)
+#define HDCTRR_RX_SEL1(n) ((n) << 31)
+#define REG_HDMA_HDC0R0 (BASE_HDMA + 0x0144) // channel 0
+#define REG_HDMA_HDC0R1 (BASE_HDMA + 0x0164) // channel 1
+#define HDCR_XFER_SIZE0(n) ((n) << 16)
+#define HDCR_START0 (1 << 0)
+#define REG_HDMA_HDC1R0 (BASE_HDMA + 0x0148) // channel 0
+#define REG_HDMA_HDC1R1 (BASE_HDMA + 0x0168) // channel 1
+#define HDCR_XFER_SIZE1(n) ((n) << 16)
+#define HDCR_START1 (1 << 0)
+#define REG_HDMA_HPRGA0R0 (BASE_HDMA + 0x014C) // channel 0
+#define REG_HDMA_HPRGA0R1 (BASE_HDMA + 0x016C) // channel 1
+#define REG_HDMA_HPRGA1R0 (BASE_HDMA + 0x0150) // channel 0
+#define REG_HDMA_HPRGA1R1 (BASE_HDMA + 0x0170) // channel 1
+#define REG_HDMA_HCCR0 (BASE_HDMA + 0x0154) // channel 0
+#define REG_HDMA_HCCR1 (BASE_HDMA + 0x0174) // channel 1
+#define HDMA_HCURR_CNT0 0x0000FFFF
+#define HDMA_HCURR_CNT1 0xFFFF0000
+#define REG_HDMA_HDCPR0 (BASE_HDMA + 0x0158) // channel 0
+#define REG_HDMA_HDCPR1 (BASE_HDMA + 0x0178) // channel 1
+#define REG_GDMA_GPMTR5 (BASE_HDMA + 0x0424) // HDMA channel promotion
+
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ #define MD_AP_DUMMY_I2C (BASE_MADDR_MDPERIMISC+0x100) //0xA0060000
+ #define AP_MD_DUMMY_I2C (BASE_MADDR_MDPERIMISC+0x300)
+ #define MD_AP_SCL (1<<15)
+ #define MD_AP_SDA (1<<14)
+ #define MD_AP_SDA_OE (1<<13)
+#endif
+
+
+#if defined(MT6763) // shall use this format afterall
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x350)
+#define IO_CFG_LB_BASE 0xC1E70000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_LB_BASE + 0x010)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LB_BASE + 0x010)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x020)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x020)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x040)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x040)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_LB_BASE + 0x0A0)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LB_BASE + 0x0A0)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_LB_BASE + 0x0C0)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LB_BASE + 0x0C0)
+#define SIM1_INS 0x00888000
+#define SIM2_INS 0x00000888
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x04); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) | SIM2_INS)); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x40); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM1_INS)); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x02); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) & ~(SIM2_INS))); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x20); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM1_INS))); \
+ }
+
+
+
+ #if defined(__SIM_SAME_GPIO_MODE__)
+ #define GPIO_SIM2_SIMIO 35
+ #define GPIO_SIM2_SIMRST 36
+ #define GPIO_SIM2_SIMCLK 37
+ #define GPIO_SIM1_SIMCLK 38
+ #define GPIO_SIM1_SIMRST 39
+ #define GPIO_SIM1_SIMIO 40
+ #else
+ #define GPIO_SIM1_SIMIO 35
+ #define GPIO_SIM1_SIMRST 36
+ #define GPIO_SIM1_SIMCLK 37
+ #define GPIO_SIM2_SIMCLK 38
+ #define GPIO_SIM2_SIMRST 39
+ #define GPIO_SIM2_SIMIO 40
+ #endif
+
+#elif defined(MT6739)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x390)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3A0)
+#define IOCFG_LB_BASE 0xC0002400
+#define REG_GPIO_IES_0_FOR_SIM (IOCFG_LB_BASE + 0x020)
+#define REG_GPIO_IES_1_FOR_SIM (IOCFG_LB_BASE + 0x020)
+#define REG_GPIO_SMT_0_FOR_SIM (IOCFG_LB_BASE + 0x090)
+#define REG_GPIO_SMT_1_FOR_SIM (IOCFG_LB_BASE + 0x090)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x070)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x080)
+#define REG_GPIO_DRV_0_FOR_SIM (IOCFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IOCFG_LB_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IOCFG_LB_BASE + 0x030)
+#define REG_GPIO_PUPD_1_FOR_SIM (IOCFG_LB_BASE + 0x040) // for abnormal SIM
+#define SIM1_INS 0x00000007
+#define SIM2_INS 0x00000038
+#define REG_GPIO_R0_CFG0_CLR_FOR_SIM (IOCFG_LB_BASE + 0x058)
+#define REG_GPIO_R1_CFG0_SET_FOR_SIM (IOCFG_LB_BASE + 0x064)
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF0000)) | 0x50000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM2_INS)); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF000)) | 0x5000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM1_INS)); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF0000)) | 0x50000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM2_INS))); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF000)) | 0x5000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM1_INS))); \
+ }
+
+ #if defined(__SIM_SAME_GPIO_MODE__)
+ #define GPIO_SIM2_SIMCLK 80
+ #define GPIO_SIM2_SIMRST 81
+ #define GPIO_SIM2_SIMIO 82
+ #define GPIO_SIM1_SIMCLK 77
+ #define GPIO_SIM1_SIMRST 78
+ #define GPIO_SIM1_SIMIO 79
+ #else
+ #define GPIO_SIM1_SIMCLK 80
+ #define GPIO_SIM1_SIMRST 81
+ #define GPIO_SIM1_SIMIO 82
+ #define GPIO_SIM2_SIMCLK 77
+ #define GPIO_SIM2_SIMRST 78
+ #define GPIO_SIM2_SIMIO 79
+ #endif
+#elif defined(MT6765)
+#define IOCFG_LB_BASE 0xC0002400
+
+#define REG_GPIO_INS_CFG0 (IOCFG_LB_BASE + 0x030)
+#define REG_GPIO_INS_CFG0_SET (IOCFG_LB_BASE + 0x034)
+#define REG_GPIO_INS_CFG0_CLR (IOCFG_LB_BASE + 0x038)
+
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+
+#define REG_GPIO_IES_0_FOR_SIM (IOCFG_LB_BASE + 0x020)
+#define REG_GPIO_IES_1_FOR_SIM (IOCFG_LB_BASE + 0x020)
+
+#define REG_GPIO_SMT_0_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+#define REG_GPIO_SMT_1_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x0D0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x0D0)
+
+#define REG_GPIO_RDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x090)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x0A0)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IOCFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IOCFG_LB_BASE + 0x000)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IOCFG_LB_BASE + 0x070) // R0_CFG0
+#define REG_GPIO_PUPD_1_FOR_SIM (IOCFG_LB_BASE + 0x080) // R1_CFG0
+
+#define SIM1_INS 0x00000007
+#define SIM2_INS 0x00000038
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_SET, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_SET, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_CLR, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_CLR, SIM1_INS); \
+ }
+
+#if defined(__SIM_SAME_GPIO_MODE__)
+ #define GPIO_SIM2_SIMCLK 37
+ #define GPIO_SIM2_SIMRST 36
+ #define GPIO_SIM2_SIMIO 35
+ #define GPIO_SIM1_SIMCLK 38
+ #define GPIO_SIM1_SIMRST 39
+ #define GPIO_SIM1_SIMIO 40
+#else
+ #define GPIO_SIM1_SIMCLK 37
+ #define GPIO_SIM1_SIMRST 36
+ #define GPIO_SIM1_SIMIO 35
+ #define GPIO_SIM2_SIMCLK 38
+ #define GPIO_SIM2_SIMRST 39
+ #define GPIO_SIM2_SIMIO 40
+#endif
+
+#elif defined(MT6295M) || defined(MT3967)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x370)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x380)
+#define IO_CFG_BL_BASE 0xC1D10000
+#define IO_CFG_LB_BASE 0xC1E70000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x050)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LB_BASE + 0x060)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x0F0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LB_BASE + 0x120)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x130)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x160)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x0D0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x0F0)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x020)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LB_BASE + 0x020)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LB_BASE + 0x0A0)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x060)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_LB_BASE + 0x080)
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000002
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x0A8)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0B4)
+#define REG_GPIO_R0_CFG0_CLR_1_FOR_SIM (IO_CFG_LB_BASE + 0x0C8)
+#define REG_GPIO_R1_CFG0_SET_1_FOR_SIM (IO_CFG_LB_BASE + 0x0D4)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x104)
+#define REG_GPIO_SR_CFG0_SET_1_FOR_SIM (IO_CFG_LB_BASE + 0x134)
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x1400); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x1400); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x0A00); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM, 0); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x0A00); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM, 0); \
+ }
+#elif defined(MT6779)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x400)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x400)
+#define IOCFG_RM_BASE 0xC1C20000
+#define REG_GPIO_IES_0_FOR_SIM (IOCFG_RM_BASE + 0x030)
+#define REG_GPIO_IES_1_FOR_SIM (IOCFG_RM_BASE + 0x030)
+#define REG_GPIO_SMT_0_FOR_SIM (IOCFG_RM_BASE + 0x0C0)
+#define REG_GPIO_SMT_1_FOR_SIM (IOCFG_RM_BASE + 0x0C0)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IOCFG_RM_BASE + 0x0F0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IOCFG_RM_BASE + 0x0F0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IOCFG_RM_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IOCFG_RM_BASE + 0x0B0)
+#define REG_GPIO_DRV_0_FOR_SIM (IOCFG_RM_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IOCFG_RM_BASE + 0x010)
+#define REG_GPIO_PUPD_0_FOR_SIM (IOCFG_RM_BASE + 0x060)
+#define REG_GPIO_PUPD_1_FOR_SIM (IOCFG_RM_BASE + 0x060)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IOCFG_RM_BASE + 0x040)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IOCFG_RM_BASE + 0x040)
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IOCFG_RM_BASE + 0x0D0)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IOCFG_RM_BASE + 0x088)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IOCFG_RM_BASE + 0x094)
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x000000FC); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x000000A8); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, 0x78000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x00000003); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x50000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000002); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x000000FC); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000054); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, 0x78000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x00000003); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x28000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000001); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MT6297)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x330)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+#define IO_CFG_BL_BASE 0xC1D00000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x010)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BL_BASE + 0x010)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x0A0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x0A0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x060)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x070)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x030)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BL_BASE + 0x030)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x020)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BL_BASE + 0x020 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x048)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x058)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x044)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x054)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x090)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x94)
+#define SIM1_DRIVING_MASK 0x1FF
+#define SIM2_DRIVING_MASK 0x3FE00
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x9200); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x049); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x0); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x0); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MT6885)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x350)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x360)
+#define IO_CFG_LT_BASE 0xC1F20000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_LT_BASE + 0x040)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LT_BASE + 0x014)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_LT_BASE + 0x0E0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LT_BASE + 0x0E0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_LT_BASE + 0x110)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LT_BASE + 0x110)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_LT_BASE + 0x090)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LT_BASE + 0x090)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_LT_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LT_BASE + 0x010)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_LT_BASE + 0x070)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LT_BASE + 0x070)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_LT_BASE + 0x050)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_LT_BASE + 0x050 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_LT_BASE + 0x098)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_LT_BASE + 0x0A8)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_LT_BASE + 0x094)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_LT_BASE + 0x0A4)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_LT_BASE + 0x0F0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_LT_BASE + 0xF4)
+#define SIM1_DRIVING_MASK 0x3F000000
+#define SIM2_DRIVING_MASK_1 0xC0000000
+#define SIM2_DRIVING_MASK_2 0x0000000F
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK_1); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK_2); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x80000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0xA); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x2A000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK_1); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK_2); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x40000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x5); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x15000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MT6873)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x350)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x360)
+#define IO_CFG_RM_BASE 0xC1C20000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_RM_BASE + 0x030)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_RM_BASE + 0x030)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_RM_BASE + 0x0C0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_RM_BASE + 0x0C0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x0F0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x0F0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_RM_BASE + 0x010)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_RM_BASE + 0x010)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_RM_BASE + 0x060)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_RM_BASE + 0x060)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x040)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_RM_BASE + 0x040 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x088)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x098)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x084)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x0D0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x0D4)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IO_CFG_RM_BASE + 0x088)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+#define SIM1_DRIVING_MASK 0x00000300
+#define SIM2_DRIVING_MASK 0x000000C0
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00000080); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00000200); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000040); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00000100); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MERCURY)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define IO_CFG_BL_BASE 0xC1D00000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BL_BASE + 0x000 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x00)
+#define SIM1_DRIVING_MASK 0x1FF
+#define SIM2_DRIVING_MASK 0x3FE00
+
+#define ENABLE_ABNORMAL_SIM(_n) ;
+
+#define DISABLE_ABNORMAL_SIM(_n) ;
+#elif defined(MT6853)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3E0)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3F0)
+#define IO_CFG_RM_BASE 0xC1C20000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_RM_BASE + 0x020)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_RM_BASE + 0x020)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x080)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x080)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_RM_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_RM_BASE + 0x010)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_RM_BASE + 0x040)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_RM_BASE + 0x040)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x030)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_RM_BASE + 0x030 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x058)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x068)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x054)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x064)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x0A0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x0A4)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IO_CFG_RM_BASE + 0x058)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IO_CFG_RM_BASE + 0x064)
+#define SIM1_DRIVING_MASK 0x00300000
+#define SIM2_DRIVING_MASK 0x000C0000
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00080000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00200000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00040000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00100000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+
+#elif defined(CHIP10992)
+#define IO_CFG_BL_BASE 0xC1D00000
+
+// only for reg dump
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3A0)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3B0)
+
+// only for reg dump
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x040)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BL_BASE + 0x050)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x0e0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BL_BASE + 0x0e0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x100)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x100)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x0c0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x0c0)
+
+// for both dump and config !!!
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x0a8)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x0b8)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0a4)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0b4)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x060)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BL_BASE + 0x060 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x0f0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0f4)
+
+#define SIM1_DRIVING_MASK 0x00003000
+#define SIM2_DRIVING_MASK 0x00003000
+
+// When abnormal mode enabled, driving @ 3rd gear
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00002000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00002000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+// When abnormal mode disabled, driving @ 2nd gear
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00001000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00001000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+
+#elif defined(MT6833)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3E0)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3F0)
+#define IO_CFG_BR_BASE 0xC1D40000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BR_BASE + 0x040)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BR_BASE + 0x040)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BR_BASE + 0x0C0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BR_BASE + 0x0C0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BR_BASE + 0x0E0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BR_BASE + 0x0F0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BR_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BR_BASE + 0x0B0)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BR_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BR_BASE + 0x000)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BR_BASE + 0x070)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BR_BASE + 0x070)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BR_BASE + 0x050)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BR_BASE + 0x050)
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BR_BASE + 0x098)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BR_BASE + 0x0A8)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BR_BASE + 0x094)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BR_BASE + 0x0A4)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BR_BASE + 0x0D0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BR_BASE + 0x0D4)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IO_CFG_BR_BASE + 0x098)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IO_CFG_BR_BASE + 0x0A4)
+#define SIM1_DRIVING_MASK 0x18000000
+#define SIM2_DRIVING_MASK 0x60000000
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x40000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x10000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x20000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x08000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+
+#else
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define IO_CFG_LB_BASE BASE_MADDR_AP_GPIOMUX
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define SIM1_INS 0x00000000
+#define SIM2_INS 0x00000000
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x02); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) | SIM2_INS)); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x20); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM1_INS)); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x01); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) & ~(SIM2_INS))); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x10); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM1_INS))); \
+ }
+#define SET_SIM1_SR(_n)
+#define SET_SIM2_SR(_n)
+
+#endif
+
+
+#if defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+#if defined(MT6330)
+/* writel_field to config vsim en and lp; only valid when SW_OP_EN=1 (default 1) */
+#define RG_LDO_VSIM1_CON0 0x1c07
+#define RG_LDO_VSIM1_EN_MASK 0x1
+#define RG_LDO_VSIM1_EN_SHIFT 0x0
+#define RG_LDO_VSIM1_LP_MASK 0x1
+#define RG_LDO_VSIM1_LP_SHIFT 0x1
+
+#define RG_LDO_VSIM1_OP_EN1 0x1c0e
+#define RG_LDO_VSIM1_OP_EN1_SET 0x1c0f
+#define RG_LDO_VSIM1_OP_EN1_CLR 0x1c10
+#define RG_LDO_VSIM1_SW_OP_EN (0x1<<7)
+
+#define RG_LDO_VSIM2_CON0 0x1c18
+#define RG_LDO_VSIM2_EN_MASK 0x1
+#define RG_LDO_VSIM2_EN_SHIFT 0x0
+#define RG_LDO_VSIM2_LP_MASK 0x1
+#define RG_LDO_VSIM2_LP_SHIFT 0x1
+
+#define RG_LDO_VSIM2_OP_EN1 0x1c1f
+#define RG_LDO_VSIM2_OP_EN1_SET 0x1c20
+#define RG_LDO_VSIM2_OP_EN1_CLR 0x1c20
+#define RG_LDO_VSIM2_SW_OP_EN (0x1<<7)
+
+/* writel to config vsim voltage */
+#define RG_VSIM1_ANA_CON1 0x1e93
+// #define RG_VSIM1_VOSEL_MASK 0xF
+// #define RG_VSIM1_VOSEL_SHIFT 0
+
+#define RG_VSIM2_ANA_CON1 0x1e96
+// #define RG_VSIM2_VOSEL_MASK 0xF
+// #define RG_VSIM2_VOSEL_SHIFT 0
+
+#define LDO_VSIM_1P7V 0x3 //4'b0011: 1.7V
+#define LDO_VSIM_1P8V 0x4 //4'b0100: 1.8V
+#define LDO_VSIM_2P9V 0xA //4'b1010: 2.9V
+#define LDO_VSIM_3P0V 0xB //4b'1011: 3.0V
+
+
+#define RG_LDO_VSIM1_EINT 0x1c17
+#define RG_LDO_VSIM2_EINT 0x1c28
+
+#define RG_LDO_VSIMx_EINT_EN (0x1<<0) // 0: disable, 1:enable
+#define RG_LDO_VSIMx_EINT_POL (0x1<<2) // 0: Low active, 1: High active
+#define RG_LDO_VSIMx_EINT_DB_SEL (0x1<<4) // 0: 5us, 1: 10us
+
+#else
+#if defined(__MTK_TARGET__)
+#error "Please add VSIM related PMIC register defination for New PMIC"
+#endif
+#endif
+#endif /* SIM_DRV_CTRL_VSIM_BY_SPMI */
+
+#endif /*__SIM_DRV_HW_REG_MTK_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_SW_API.h b/mcu/driver/devdrv/usim/inc/sim_drv_SW_API.h
new file mode 100644
index 0000000..ae5b3f0
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_SW_API.h
@@ -0,0 +1,98 @@
+#ifndef __SIM_DRV_SW_API_H__
+#define __SIM_DRV_SW_API_H__
+#include "multi_icc_custom.h"
+
+#ifdef DRV_SIM_BUILD_SINGLE_SIM
+ //extern kal_uint16 SIM_CMD(kal_uint8 *txData,kal_uint16 txSize,kal_uint8 *result,kal_uint16 *rcvSize, kal_uint8 *Error);
+ extern void L1sim_ChangeBaud(void);
+ extern void L1sim_NormalBaud(void);
+ extern sim_card_speed_type L1sim_Get_CardSpeedType(void);
+ extern void L1sim_Enable_Enhanced_Speed(kal_bool enable);
+ extern kal_uint16 L1sim_Cmd_Layer(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize);
+
+ extern void SIM1_LDO_enable(kal_bool enable);
+ extern void SIM2_LDO_enable(kal_bool enable);
+
+ usim_status_enum L1sim_Reset_All(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm);
+ void L1sim_Enable_Enhanced_Speed_All(kal_bool enable);
+ kal_bool L1sim_Set_ClockStopMode_All(sim_clock_stop_enum mode);
+ void L1sim_PowerOff_All(void);
+ void L1sim_Get_Card_Info_All(sim_info_struct *info);
+ sim_status L1sim_Cmd_All(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize);
+ void L1sim_Select_SIM_PLUS(kal_bool isSIMPLUS);
+ void L1sim_Select_Prefer_PhyLayer_All(sim_protocol_phy_enum T);
+#endif
+
+sim_HW_cb *sim_get_hwCb(kal_uint32 simInterface);
+kal_uint32 sim_get_logical_from_SIMIF(kal_uint32 HWIf);
+void SIM_StartFaltalReport(sim_HW_cb *hw_cb);
+kal_uint8 DRV_ICC_GPTI_GetHandle(kal_uint32 *handle);
+void DRV_ICC_GPTI_StopItem(kal_uint32 handle);
+kal_bool DRV_ICC_GPTI_StartItem(kal_uint32 handle, kal_uint16 tick, void (*gptimer_func)(void *), void *parameter);
+kal_uint8 DRV_ICC_makeCLA(kal_uint8 CLAHighBits, kal_uint8 CLAFromApdu);
+extern void sim_MT6302_init(void);
+extern sim_status L1sim_Cmd_Layer_MT6302(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb, kal_bool *isSW6263);
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+extern void sim_set_logical_to_SIMIF(kal_uint32 HWIf, kal_uint32 logical);
+/* custom setting */
+extern kal_uint32 sim_get_logicalNum_from_app(SIM_ICC_APPLICATION application);
+extern kal_uint32 sim_get_MT6302_from_logicalNum(kal_uint32 logicalNum);
+extern kal_uint32 sim_get_hwCtrl_from_logicalNum(kal_uint32 logicalNum);
+extern kal_uint32 sim_get_MT6302PeerInterface(kal_uint8 chipNum, kal_uint32 portNum);
+extern kal_uint32 sim_custom_task_2_driver(kal_uint32 taskInterface);
+extern void *kal_get_current_thread_ID(void);
+extern void L1sim_Set_Slt_Rlt(kal_bool rlt, SIM_ICC_APPLICATION application);
+extern void sim_custom_setting_before_turning_on_vsim(kal_uint32 hwInterfaceNo);
+extern void sim_custom_setting_after_turning_off_vsim(kal_uint32 hwInterfaceNo);
+extern void sim_custom_setting_before_resetting_sim(kal_uint32 hwInterfaceNo);
+
+#ifndef __TBD__
+ extern kal_uint32 SIM_GetCurrentTime(void);
+ extern kal_uint32 SIM_GetDurationTick(kal_uint32 previous_time, kal_uint32 current_time);
+#endif
+
+#ifndef __FPGA__
+ void DRV_ICC_PMU_setVolt(kal_uint32 hwInterfaceNo, usim_power_enum volt);
+ void DRV_ICC_PMU_switch(kal_uint32 hwInterfaceNo, kal_bool enable);
+ #if defined(__DRV_SIM_LP_MODE__)
+ void DRV_ICC_SetLp(kal_uint32 hwInterfaceNo, kal_bool isOn);
+ #endif
+#endif
+#if defined(LPWR_SLIM)
+ extern void DRV_ICC_CLKSRC_Lock(kal_uint32 hwInterfaceNo, kal_bool fLock);
+#endif
+extern void USIM_low_power_related_setting(sim_HW_cb *hw_cb, kal_uint8 option);
+
+extern void SIM_SetRXTIDE(kal_uint16 RXTIDE, sim_HW_cb *hw_cb);
+extern void SIM_SetTXTIDE(kal_uint16 _TXTIDE, sim_HW_cb *hw_cb);
+extern void L1sim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb);
+extern void USIM_SET_EVENT_Multiple(usim_dcb_struct *usim_dcb);
+extern void SIM_SetTOUT(kal_uint32 TOUT, sim_HW_cb *hw_cb);
+extern void DRV_ICC_print(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5);
+extern void DRV_ICC_print_dec(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5);
+extern void DRV_ICC_print_str(kal_char sim_dbg_str[]);
+extern void DRV_ICC_print_err_msg(sim_HW_cb *hw_cb, kal_char sim_dbg_str[]);
+extern void sim_dump_fifo(sim_HW_cb *hw_cb);
+extern void sim_MT6306_clkStopper(sim_HW_cb *hw_cb);
+extern void SIM_RegHotPlugCb(SIM_ICC_APPLICATION application, DCL_SIM_PLUG_IN_CALLBACK hotPlugInCb, DCL_SIM_PLUG_OUT_CALLBACK hotPlugOutCb);
+extern void DRV_ICC_Calc_WWT(kal_uint16 Fi, kal_uint8 Di, kal_uint8 Wi, kal_uint32 *WWT);
+extern void SIM_EINT_Mask(sim_HW_cb *hw_cb, kal_bool enable, kal_uint32 line_num);
+#if defined(SIM_DRV_IC_USB)
+ extern kal_uint32 SIM_icusb_init(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_setVolt(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_enableSession(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_powerOn(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_cmd(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_disableSession(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_disconnectDone(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_deinit(sim_HW_cb *hw_cb);
+#endif
+#if defined(__ABNORMAL_CARD__)
+ extern void usim_set_sim_io_special_mode(kal_int32 simIF, kal_bool enable);
+#endif // #if defined(__ABNORMAL_CARD__)
+
+extern void sim_releaseOwner(SIM_ICC_APPLICATION application);
+#if defined(__SIM_ACTIVATION_V2__)
+ extern void usim_gpt_timeout_handler_for_SIM_activation(void *parameter);
+#endif
+#endif /*__SIM_DRV_SW_API_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_SW_function.h b/mcu/driver/devdrv/usim/inc/sim_drv_SW_function.h
new file mode 100644
index 0000000..c9ec04e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_SW_function.h
@@ -0,0 +1,585 @@
+#ifndef __SIM_DRV_SW_FUNCTION_H__
+#define __SIM_DRV_SW_FUNCTION_H__
+
+#include "us_timer.h"
+
+
+
+#if defined(ATEST_DRV_ENABLE) || defined (__IC_SLT__)
+ #define SIM_DEBUG_ASSERT(_condition) ASSERT(_condition)
+#else //#ifdef defined(ATEST_DRV_ENABLE)|| defined (__IC_SLT__)
+#ifndef __DEBUG_ASSERT_SUPPORT__
+extern kal_char SIM_DEBUG_ASSERT_STR[512];
+ #define SIM_DEBUG_ASSERT(_condition)\
+ { \
+ if (!(_condition))\
+ {\
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(SIM_DEBUG_ASSERT_STR, "[SIM_DRV][ERR][%s:%d][%s] SIM_DEBUG_ASSERT !!!!!\r\n", __FILE__, __LINE__,__FUNCTION__); \
+ if (log_size > 0) DRV_ICC_print_str(SIM_DEBUG_ASSERT_STR); \
+ DEBUG_ASSERT(_condition); \
+ }\
+ }
+#else //#ifndef __DEBUG_ASSERT_SUPPORT__
+ #define SIM_DEBUG_ASSERT(_condition) DEBUG_ASSERT(_condition)
+#endif
+#endif
+
+
+#ifdef SIM_DBG_OPTION_ENABLE
+#define SIM_ASSERT(_condition) \
+ { \
+ ASSERT(_condition); \
+ }
+#else /*!SIM_DBG_OPTION_ENABLE*/
+#if defined(SIM_DEBUG_INFO)
+#define SIM_ASSERT(_condition) \
+ { \
+ if (!(_condition)) \
+ { \
+ sim_assert(__LINE__); \
+ } \
+ }
+#else
+#define SIM_ASSERT(_condition)
+#endif /*#if defined(SIM_DEBUG_INFO)*/
+#endif /*SIM_DBG_OPTION_ENABLE*/
+
+
+#define SIM_SetRXRetry(_RXRetry)\
+ {\
+ kal_uint16 _Retry;\
+ Data_Sync_Barrier(); \
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_RXMASK;\
+ _Retry |= _RXRetry;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_SetTXRetry(_TXRetry) \
+ {\
+ kal_uint16 _Retry;\
+ Data_Sync_Barrier(); \
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_TXMASK;\
+ _Retry |= (_TXRetry<<8);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_ObtainSW(_SW) \
+ {\
+ kal_uint16 _SW1;\
+ kal_uint16 _SW2;\
+ Data_Sync_Barrier(); \
+ _SW1 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK);\
+ _SW2 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW2_MTK);\
+ _SW = (_SW2 | (_SW1 << 8));\
+ }
+
+#define SIM_DMA_STOP(_channel) \
+ {\
+ kal_uint32 cnt = 0, ori_REG_HDMA_HDCTRR;\
+ if(_channel)\
+ {\
+ ori_REG_HDMA_HDCTRR = DRV_Reg32(REG_HDMA_HDCTRR1);\
+ SIM_SetBits32(REG_HDMA_HDCTRR1, HDCTRR_STOP);\
+ while((SIM_Reg32(REG_HDMA_HDCTRR1) & HDCTRR_STOP))\
+ {\
+ cnt++;\
+ if(cnt % 1000 == 0)\
+ {\
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC127, cnt, ori_REG_HDMA_HDCTRR, 0, 0, 0);\
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC127, hw_cb);\
+ }\
+ if(cnt % 10000 == 0) SIM_DEBUG_ASSERT(0);\
+ ust_us_busyloop(100); \
+ }\
+ } else\
+ {\
+ ori_REG_HDMA_HDCTRR = DRV_Reg32(REG_HDMA_HDCTRR0);\
+ SIM_SetBits32(REG_HDMA_HDCTRR0, HDCTRR_STOP);\
+ while((SIM_Reg32(REG_HDMA_HDCTRR0) & HDCTRR_STOP))\
+ {\
+ cnt++;\
+ if(cnt % 1000 == 0)\
+ {\
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC127, cnt, ori_REG_HDMA_HDCTRR, 0, 0, 0);\
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC127, hw_cb);\
+ }\
+ if(cnt % 10000 == 0) SIM_DEBUG_ASSERT(0);\
+ ust_us_busyloop(100); \
+ }\
+ }\
+ }
+
+//#define SIM_SetIMP3(_IMP3) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), _IMP3)
+#define SIM_SetCOMDLEN(_COMDLEN) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COMDLEN_MTK), _COMDLEN)
+
+//#define SIM_SetCmdINS(_INS) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_INS_MTK), _INS)
+#define SIM_SetCmdCTRL(_INS) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK), _INS)
+#define SIM_CMDSTART() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK),SIM_INS_START)
+
+#define SIM_SetAtime(_ATIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), _ATIME)
+#define SIM_SetDtime(_DTIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DTIME_MTK), _DTIME)
+
+//#define SIM_FIFO_Flush() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), 0x01)
+//mt6290
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES)|| defined(DRV_SIM_6297_SERIES)
+#define SIM_FIFO_Flush() \
+ {\
+ SIM_PRINT_DEBUG1_2; \
+ DRV_WriteReg32_NPW((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ Data_Sync_Barrier(); \
+ while(DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON); \
+ }
+#elif (defined(DRV_SIM_6290_SERIES) || defined(DRV_SIM_6291_SERIES)) && !defined(ATEST_ENABLE)
+#define SIM_FIFO_Flush() \
+ do {\
+ DRV_WriteReg32_NPW((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ ust_us_busyloop(2); \
+ } while(0)
+#else
+#define SIM_FIFO_Flush() \
+ { \
+ kal_uint32 t1 = 0; \
+ DRV_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ t1 = drv_get_current_time(); \
+ while(drv_get_duration_tick(t1, drv_get_current_time()) < 2); \
+ }
+#endif
+
+#if defined(SIM_DRV_PRINT_DEBUG1_2)
+#define SIM_PRINT_DEBUG1_2 \
+ { \
+ kal_uint32 dbg[2] = {0}; \
+ dbg[0] = DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DEBUG1_MTK); \
+ dbg[1] = DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DEBUG2_MTK); \
+ if(dbg[0] != 0 || dbg[1] != 0) \
+ { \
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC123, dbg[0], dbg[1], 0, 0, 0); \
+ } \
+ } while (0)
+#else
+#define SIM_PRINT_DEBUG1_2
+#endif
+
+#ifdef NO_SLIM_DEF
+#define SIM_Reject_Single() \
+ {\
+ SIM_DisAllIntr();\
+ SimCard.State = SIM_PWROFF;\
+ *(volatile kal_uint16 *)SIM_IRQEN = SIM_IRQEN_SIMOFF;\
+ *(volatile kal_uint16 *)SIM_CTRL &= ~SIM_CTRL_SIMON;\
+ SIM_FIFO_Flush();\
+ }
+
+#define SIM_Reject_MT6302(hw_cb) \
+ {\
+ SIM_DisAllIntr();\
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_MT6302_addMsg(SIM_MT6302_DRIVER_DEACT, hw_cb->simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ if(KAL_FALSE == sim_MT6302_QueryNeedManualControl(hw_cb)){\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);\
+ sim_MT6302_VCCCtrl(hw_cb, 0);\
+ }\
+ else{\
+ sim_MT6302_manualDeactive(hw_cb);\
+ }\
+ }\
+ else\
+ {\
+ sim_PDNEnable_MT6302(hw_cb);\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent_MT6302(SimCard,SIM_NOREADY);\
+ }\
+ }
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+/*SIM_WaitEvent_MTK(SimCard,SIM_NOREADY,KAL_FALSE)*/
+#define SIM_Reject_MTK(hw_cb) \
+ {\
+ dbg_print("\r\n++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r\n");\
+ SIM_DisAllIntr();\
+ if(SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_addMsg(SIM_DRIVER_DEACT_SIMD, hw_cb->simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ SIM_ClearBits(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK, SIM_CTRL_SIMON);\
+ SIM_WaitEvent_MTK(SimCard,SIM_NOREADY,KAL_FALSE); \
+ } else\
+ {\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent_MTK(SimCard,SIM_NOREADY);\
+ }\
+ }
+#endif
+//#define SIM_Active() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0x0001)
+#define SIM_Active() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON)
+
+#define SIM_Deactive() do {\
+ SIM_SET_OE_BIT();\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);\
+ }while(0)
+
+#ifdef NO_SLIM_DEF
+#define SIM_WaitEvent_Single(_SIMCARD,_flag) \
+ {\
+ kal_uint32 _event_group;\
+ kal_status returnValueOfSIMWaitEvent;\
+ extern void sim_dump_error_line(void);\
+ returnValueOfSIMWaitEvent = returnValueOfSIMWaitEvent;\
+ _SIMCARD.event_state = KAL_TRUE;\
+ _SIMCARD.EvtFlag = _flag;\
+ returnValueOfSIMWaitEvent = kal_retrieve_eg_events(_SIMCARD.event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_dump_error_line();\
+ }
+
+#define SIM_SetEvent_Single(_SIMCARD,_result) \
+ {\
+ kal_status returnValueOfSIMSetEvent;\
+ returnValueOfSIMSetEvent = returnValueOfSIMSetEvent;\
+ _SIMCARD.result = _result;\
+ _SIMCARD.event_state = KAL_FALSE;\
+ returnValueOfSIMSetEvent = kal_set_eg_events(_SIMCARD.event,_SIMCARD.EvtFlag,KAL_OR);\
+ *(volatile kal_uint16 *)SIM_IRQEN = SIM_IRQEN_ALLOFF;\
+ }
+
+#define SIM_WaitEvent_MT6302(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ kal_status returnValue;\
+ extern void sim_dump_error_line(void);\
+ returnValue = returnValue;\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ switch_CB->sim_workingTaskWaiting = KAL_TRUE;\
+ if(KAL_TRUE == _unmaskSIMIntr)\
+ IRQUnmask(hw_cb->mtk_lisrCode);\
+ returnValue= kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ switch_CB->sim_workingTaskWaiting = KAL_FALSE;\
+ sim_dump_error_line();\
+ }
+
+#define SIM_SetEvent_MT6302(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,SIM_EVT_CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_MT6302_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+
+/*********************************************************************************************
+*we move this macro from sim_sw_comm.h to here, since we need a distinguish from dual controllers or MT6302.
+*In dual controllers solution, we need to enable interrupt according to simInterface, but in MT6302 solution, we only need to enable SIM's.
+**********************************************************************************************/
+#define SIM_WaitEvent_MTK(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ extern void sim_dump_error_line(void);\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ if(KAL_TRUE == _unmaskSIMIntr){\
+ IRQUnmask(hw_cb->mtk_lisrCode);\
+ }\
+ kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_dump_error_line();\
+ }
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+#define SIM_SetEvent_MTK(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,SIM_EVT_CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+#endif
+#define SIM_NotifyCARDisHALTEN() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN)
+#define SIM_T0CtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_T0CtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_FlowCtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+#define SIM_FlowCtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+
+#define SIM_DisIntr(_Intr) SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), _Intr)
+
+
+
+#define sim_PDNEnable_Single() DRVPDN_Enable(PDN_SIM)
+#define sim_PDNDisable_Single() DRVPDN_Disable(PDN_SIM)
+
+
+
+
+
+#define SIM_ActiveClk_Single() \
+ {\
+ sim_PDNDisable_Single();\
+ *(volatile kal_uint16 *)SIM_CTRL &= ~SIM_CTRL_HALT;\
+ }
+
+#define SIM_ActiveClk_MT6302(hw_cb) \
+ {\
+ sim_PDNDisable_MT6302(hw_cb);\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_ActiveClk_MT6306(hw_cb) \
+ {\
+ sim_PDNDisable_MT6306(hw_cb);\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_ActiveClk_MTK(hw_cb) \
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_Idle_Single(_level) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable_Single();\
+ }
+
+#define SIM_Idle_MT6302(_level, hw_cb) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable_MT6302(hw_cb);\
+ }
+
+#define SIM_Idle_MT6306(_level, hw_cb) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable_MT6306(hw_cb);\
+ }
+
+#define SIM_Idle_MTK(_level, hw_cb) \
+ {\
+ if(_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ } else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ }
+
+#define SIM_FIFO_GetLev() (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK) & SIM_COUNT_MASK)
+#define SIM_DisTOUTIntr() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_OpenTOUTIntr() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_DisAllIntr() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF)
+
+#ifdef NO_SLIM_DEF
+
+#endif /* End of #ifdef NO_SLIM_DEF */
+#ifdef NoT0CTRL
+#define SIMCmdInit()
+#else /*NoT0CTRL*/
+#define SIMCmdInit() \
+ {\
+ SIM_T0CtrlEnable(); /*SIM_FlowCtrlEnable()*/ \
+ }
+#endif /*NoT0CTRL*/
+
+// macros
+#define SIM_WARM_RST() SIM_SetBits((SIM0_BASE_ADDR_MTK +SIM_CTRL_MTK), SIM_CTRL_WRST)
+
+/*
+ normally, wait event will before set event, but sometimes set event will before wait event.
+ for instance, during wait event, an interrupt is generated and trigger another interrupt before
+ the corresponding wait event.
+*/
+
+#define USIM_CLR_EVENT_Single()\
+ kal_set_eg_events(usim_dcb.event,0,KAL_AND)
+
+#define USIM_CLR_EVENT_Multiple()\
+ kal_set_eg_events(usim_dcb->event,0,KAL_AND)
+
+#define USIM_POW_ON() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON)
+#define USIM_WRST() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), (SIM_CTRL_WRST|SIM_CTRL_SIMON))
+#define USIM_ENABLE_T0() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define USIM_ENABLE_T1() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T1EN)
+#define USIM_DISABLE_T0() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define USIM_DISABLE_T1() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T1EN)
+#define USIM_ENABLE_TXRX_HANSHAKE() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK|SIM_CONF_RXHSK))
+#define USIM_DISABLE_TXRX_HANSHAKE() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK|SIM_CONF_RXHSK))
+
+//#define USIM_TX_START_T1() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_INS_MTK), 1)
+#define USIM_TX_START_T1() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK), SIM_INS_START)
+
+
+#define USIM_IS_IBLOCK(pcb) ((pcb&PCB_I_BIT8)==0)
+#define USIM_IS_RBLOCK(pcb) ((pcb&PCB_R_DEFAULT) == 0x80)
+#define USIM_IS_SBLOCK(pcb) ((pcb&PCB_S_DEFAULT) == PCB_S_DEFAULT)
+#define USIM_IS_RESP(pcb) (pcb&PCB_S_RESP)
+#define USIM_INV_N(n) (n = (n)?0:PCB_I_SEQ)
+
+#define USIM_CLR_FIFO() SIM_FIFO_Flush()
+
+#define USIM_RESET_T1() USIM_DISABLE_T1();USIM_ENABLE_T1();
+#define USIM_ENABLE_TOUT() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN)
+#define USIM_DISABLE_TOUT() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TOUTEN))
+//#define USIM_CLR_TX_TIDE() SIM_Reg(SIM_TIDE)&=(~SIM_TIDE_TXMASK)
+#define USIM_DMA_RX_TIDE() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK), 0);
+
+#define SIM_SET_OE_BIT() do {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK +SIM_SIMOE_MODE_MTK), SIM_SIMOE_ENABLE);\
+ MO_Sync();\
+}while(0)
+
+#define SIM_CLR_OE_BIT() do {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK +SIM_SIMOE_MODE_MTK), SIM_SIMOE_ENABLE);\
+ MO_Sync();\
+}while(0)
+
+#define USIM_CAL_TD_COUNT(a,b) \
+ {\
+ if(a & TAMask) b++;\
+ if(a & TBMask) b++;\
+ if(a & TCMask) b++;\
+ }
+
+// generate R-block header
+#define USIM_MAKE_R_BLOCK_Single(e) \
+ {\
+ kal_uint8 pcbInMacroMakeRBlock;\
+ \
+ if(usim_dcb.nr)\
+ pcbInMacroMakeRBlock = (PCB_R_N1|e);\
+ else\
+ pcbInMacroMakeRBlock = (PCB_R_N0|e);\
+ usim_dcb.header_tx[T1_PCB_INDEX] = pcbInMacroMakeRBlock;\
+ usim_dcb.header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb.cmd_state = R_BLOCK_TX;\
+ }
+
+#define USIM_MAKE_S_RESYNC_Single()\
+ {\
+ usim_dcb.header_tx[T1_PCB_INDEX] = PCB_S_DEFAULT;\
+ usim_dcb.header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb.cmd_state = S_BlOCK_REQ_TX;\
+ }
+
+#define USIM_MAKE_R_BLOCK_Multiple(e) \
+ {\
+ kal_uint8 pcb;\
+ \
+ if(usim_dcb->nr)\
+ pcb = (PCB_R_N1|e);\
+ else\
+ pcb = (PCB_R_N0|e);\
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;\
+ usim_dcb->header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb->cmd_state = R_BLOCK_TX;\
+ }
+
+#define USIM_MAKE_S_RESYNC_Multiple()\
+ {\
+ usim_dcb->header_tx[T1_PCB_INDEX] = PCB_S_DEFAULT;\
+ usim_dcb->header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb->cmd_state = S_BlOCK_REQ_TX;\
+ }
+
+
+////////////// temp definitions///////////////
+#define error()
+//////////////////////////////////////////////
+
+/*following is to move control block resource control code to custom files*/
+extern void *sim_get_sim_cb(kal_uint32 tasakInterface);
+extern void *sim_get_usim_cb(kal_uint32 tasakInterface);
+#define GET_USIM_CB(a) sim_get_usim_cb(a)
+#define GET_SIM_CB(a) sim_get_sim_cb(a)
+
+#define IMPLEMENTING_ASSERT ASSERT(0)
+
+#define sim_print(a,b) dbg_print(a,b)
+//#define sim_print(a,b) kal_prompt_trace(MOD_SIM,a,b)
+
+#if defined(LPWR_SLIM)
+#define usim_waitISR_with_spinlock(_spinlockid) \
+ { \
+ while(1) \
+ { \
+ kal_take_spinlock(_spinlockid, KAL_INFINITE_WAIT); \
+ Data_Sync_Barrier(); \
+ if(hw_cb->waitISR == KAL_FALSE) break; \
+ kal_give_spinlock(_spinlockid); \
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for ISR:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, (kal_uint32) hw_cb->waitISR, drv_get_current_time()); \
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr); \
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group); \
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL); \
+ } \
+ }
+#else
+#define usim_waitISR_with_spinlock(_spinlockid) \
+ { \
+ while(1) \
+ { \
+ kal_take_spinlock(_spinlockid, KAL_INFINITE_WAIT); \
+ Data_Sync_Barrier(); \
+ if(hw_cb->waitISR == KAL_FALSE) break; \
+ kal_give_spinlock(_spinlockid); \
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for ISR:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, (kal_uint32) hw_cb->waitISR, drv_get_current_time()); \
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr); \
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL); \
+ } \
+ }
+#endif
+
+
+
+void sim_dump_fifo(sim_HW_cb *hw_cb);
+void sim_storeFifo(sim_HW_cb *hw_cb);
+void sim_printFifo(sim_HW_cb *hw_cb);
+void sim_dump_sim_pins(sim_HW_cb *hw_cb);
+void sim_dump_reg(kal_uint32 trc_num, sim_HW_cb *hw_cb);
+void sim_dump_gpio(sim_HW_cb *hw_cb);
+void sim_dump_eint(sim_HW_cb *hw_cb);
+
+#endif /*__SIM_DRV_SW_FUNCTION_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_SW_struct.h b/mcu/driver/devdrv/usim/inc/sim_drv_SW_struct.h
new file mode 100644
index 0000000..83d9ba4
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_SW_struct.h
@@ -0,0 +1,465 @@
+#ifndef __SIM_DRV_SW_STRUCT_H__
+#define __SIM_DRV_SW_STRUCT_H__
+
+#define SIM_HW_CB_HEAD 0x5A5A5A5A
+#define SIM_HW_CB_TAIL 0xA5A5A5A5
+
+/* For sim hot plug callback function */
+#include "dcl.h"
+//typedef void (*DCL_SIM_PLUG_OUT_CALLBACK)(kal_uint32 simIf);
+//typedef void (*DCL_SIM_PLUG_IN_CALLBACK)(kal_uint32 simIf);
+
+
+
+typedef struct
+{
+ kal_uint32 BURST_SIZE;
+ kal_uint32 MEM_BUS_WIDTH;
+ kal_uint32 DEV_BUS_WIDTH;
+ kal_uint32 channel; // two channels(0 or 1) are avaliable in MT6290
+ //DMA config register address
+ kal_uint32 ADDR_HDMA_HPRGA0Rx; //buf 0 : used for TX or RX
+ kal_uint32 ADDR_HDMA_HPRGA1Rx; //buf 1: used for RX in auto-switch
+ kal_uint32 ADDR_HDMA_HDCTRRx; //config for buf direction, burst size, dev bus width, and mem bus width
+ kal_uint32 ADDR_HDMA_HDC0Rx; //buf 0 config for transfer size and start
+ kal_uint32 ADDR_HDMA_HDC1Rx; //buf 1 config for transfer size and start
+} Sim_HDMA_struct;
+
+
+typedef struct
+{
+ kal_uint32 head;
+ /*
+ Here defines MTK related HW information of this logical interface, these values are defined as constant in old driver.
+ Now we make it variable.
+ */
+ kal_uint32 mtk_baseAddr;
+ kal_uint32 mtk_lisrCode;
+ /*
+ in multiple SIM drivers, simInterface is used in all most all functions, we need record this information.
+ */
+ kal_uint32 simInterface; // The logical number. This value now can be 0~n, not limted as 0~1 before. We can assume it less than 2 now
+ kal_uint32 MT6302ChipNo; // record which MT6302 switch used for this card
+ kal_uint32 MT6302PortNo; // record which port of MT6302 is used for this card
+ void *MT6302PeerInterfaceCb; // MT6302 need peer's information, so we have to maintain a way to find its peer
+ kal_uint32 simSwitchChipNo;
+ kal_uint32 simSwitchPortNo;
+ void *simSwitchPeerInterfaceCb;
+ void *simSwitchPeerInterfaceCb1;
+ void *simSwitchPeerInterfaceCb2;
+ DCL_SIM_PLUG_IN_CALLBACK simHotPlugIn;
+ DCL_SIM_PLUG_OUT_CALLBACK simHotPlugOut;
+ kal_uint32 debounceTime; // hot swap EINT debounce time
+ kal_uint32 tail;
+ kal_bool polarity; // hot swap EINT poarity
+ kal_bool IsCardRemove;
+ kal_uint8 smHandler;
+ kal_bool forceOn26M;
+ kal_char dbgStr[256];
+ kal_char hisrDbgStr[256];
+ volatile kal_bool waitISR;
+ volatile kal_bool must_not_enable_sleep;
+ volatile kal_spinlockid spinlockid;
+ volatile kal_spinlockid spinlockid_sim_hot_swap;
+ volatile kal_uint8 waitGptISR_MT6306;
+ volatile kal_bool needStopGptISR;
+ kal_bool SlowClock;
+ kal_bool doNotStopSimClock;
+ kal_uint32 issueCardStatus;
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ kal_bool canUse_4_33_SCLK;
+#endif
+ kal_bool PollTimerStart;
+ kal_bool PollTimerEnd;
+ kal_bool PollTimerPluggedOut;
+ kal_affinity_group sim_task_group;
+ kal_char l4cDbgStr[256];
+ kal_uint32 sim_detect_pin_num;
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+ kal_uint32 gpioCardDetPin;
+#endif
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_bool no_md_eint_settings;
+#endif
+} sim_HW_cb;
+
+typedef struct
+{
+ kal_uint32* ptr;
+ kal_uint32 size;
+} sim_nvram_param_struct;
+
+typedef struct
+{
+ sim_power_enum power;
+ sim_speed_enum speed;
+ sim_clock_stop_enum clock_stop;
+ sim_protocol_app_enum app_proto;
+ sim_protocol_phy_enum phy_proto;
+ kal_bool T0_support; // if T0 is supported
+ kal_bool T1_support; // if T1 is supported
+ kal_uint8 hist_index; // index to the historical char of ATR
+ kal_uint8 *ATR;
+ /*following information is necessary for SIM task for UICC identification*/
+ kal_bool TAiExist; //if the first TA for T=15 is existed
+ kal_uint8 ATR_length; // length to the ATR_data
+ kal_bool isSW6263; // query if status word 0x62xx 0x63xx happen
+ kal_uint8 TB15; // query if support ic usb
+ kal_bool hasPowerClass;
+ kal_uint8 PowerClass;
+ kal_bool SupportExtendedLength;
+ kal_uint8 sim_tray_status;
+ kal_uint8 sim_result;
+} sim_info_struct;
+
+#if defined SIM_DRV_IC_USB
+typedef struct
+{
+ kal_uint8 *txData;
+ kal_uint16 txSize;
+ kal_uint8 *result;
+ kal_uint16 *rcvSize;
+ kal_uint16 *sw;
+} sim_icusb_T0cmd;
+
+typedef struct
+{
+ kal_uint8 sif;
+ kal_uint8 pcb;
+ kal_uint16 cp;
+ kal_uint16 len;
+ kal_uint8 *apdubuf;
+} sim_icusb_message;
+#endif
+
+
+typedef struct
+{
+ kal_uint8 State;
+ kal_uint8 Data_format; /*SIM_direct,SIM_indirect*/
+ kal_uint8 Power; /*SIM_3V,SIM_5V*/
+ kal_uint8 recData[40]; /*PTS or ATR data*/
+ kal_bool recDataErr;
+ kal_uint8 result; /* for ATR, command, RST */
+ sim_env SIM_ENV;
+#ifndef SIM_ADDDMA
+ kal_uint8 *txbuffer; /* only used for no DMA */
+ kal_uint16 txsize; /* only used for no DMA */
+ kal_uint16 txindex; /* only used for no DMA */
+ kal_uint8 *rxbuffer; /* only used for no DMA */
+#ifdef NoT0CTRL
+ kal_uint8 INS;
+ kal_uint8 SW1;
+ kal_uint8 SW2;
+ kal_uint16 recsize;
+#endif /*NoT0CTRL*/
+#endif /*SIM_ADDDMA*/
+ /*add for clock stop mode*/
+ kal_uint8 cmdState; /* only used for no T0CTRL, and for clock stop */
+ kal_uint8 Speed; /*Speed372,Speed64,Speed32*/
+ kal_bool clkStop; /*Clok Stop Enable*/
+ kal_bool clkStopLevel; /*Clok Stop level*/
+ kal_bool reject_set_event;
+ kal_bool event_state;
+ kal_uint8 initialPower;
+ sim_card_speed_type sim_card_speed;
+ kal_hisrid hisr; /*SIM HISR*/
+ kal_eventgrpid event; /*SIM Event*/
+
+ sim_protocol_app_enum app_proto;
+ kal_bool timeout;
+ usim_cmd_case_enum cmd_case;
+ kal_bool is_err; // sim command has error once.
+ kal_bool get9000WhenSelect;
+ /*
+ following variables are get from global variables for 2 SIM projects.
+ We won't use these in single SIM driver, but we need to define the power set.
+ */
+ kal_uint8 TOUT_Factor;
+ kal_uint16 Fi;
+ kal_uint16 etu_of_1860;
+ kal_uint16 etu_of_700;
+ kal_uint8 reset_index;
+#ifdef SIM_ADDDMA
+ Sim_HDMA_struct dma_config;
+#endif
+ kal_bool TS_HSK_ENABLE;
+ kal_bool sim_ATR_fail;
+ kal_bool PTS_check; /*if false use default value: F=372, D=1*/
+ kal_uint8 PTS_data[4];
+ kal_uint8 sim_nullByteIssueNullCount;
+ kal_uint32 sim_nullByteIssuenonNullCount;
+ kal_bool keepAtrFatal;
+ kal_uint16 recDataLen; /* for command, ATR process */
+ kal_uint32 EvtFlag;
+ kal_uint32 TOUTValue;
+ kal_uint32 sim_nullByteIssueGPT;
+ /*
+ magic1 is an increasing counter, increases when 1) start new command, 2)get SIM timeout, 3)get T0 end
+ for case 2 and 3, it means that one of the ends of SIM commands has appeared.
+ */
+ volatile kal_uint32 simMagic1;
+ /*
+ magic2 is used to compared with magic1 every time GPT expires. It is set to magic1 in the start of a new command,
+ if they were compared equally in GPT timer, we know that we are still waiting for SIM controller's event.
+ */
+ volatile kal_uint32 simMagic2;
+ kal_uint32 gpt_handle;
+ kal_bool clkstoping;
+ sim_power_enum power_class; // supported power class indicated at ATR [patch from 6280 sim driver]
+ kal_bool TC2Present;
+ kal_uint32 previous_state;
+ kal_uint32 atr_count;
+#if defined(SIM_DRV_IC_USB)
+ kal_bool isIcUsb; // query if support ic usb
+ kal_bool isIcUsbRecPPS; // query if support ic usb PPS resp received
+ kal_uint32 uart_sim_ccci_handle;
+ usim_icusb_state_enum icusb_state;
+ sim_icusb_T0cmd sim_icusb_T0cmd;
+ kal_uint8 icusb_recData[40]; /*PTS or ATR data*/
+ kal_uint32 waitingTime; // waitingTime
+ kal_bool forceISO;
+#endif
+ kal_bool isPrefer3V; // prefer3v
+ kal_uint8 TB15; // query if support ic usb
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_bool poll_sim_2s;
+#endif
+ kal_uint32 t_debug[6];
+#if defined(__SIM_ACTIVATION_V2__)
+ kal_uint32 gpt_handle_for_SIM_activation;
+ kal_uint32 gpio_handle_for_SIO;
+ kal_bool activation_v2;
+#endif
+ kal_uint32 mod_id;
+ kal_uint32 mod_extq_cap;
+ kal_uint32 cmd_duration_sum;
+ kal_uint32 cmd_duration_count;
+ kal_uint32 status_duration_sum;
+ kal_uint32 status_duration_count;
+ kal_uint8 bypass6263;
+ kal_bool EF_ICCID_Selected;
+} Sim_Card;
+
+
+
+typedef struct
+{
+ usim_dir_enum dir;
+
+} ATR_struct;
+
+// specify the supported attributes of the UICC
+typedef struct
+{
+ usim_power_enum power;
+ usim_protocol_enum protocol;
+ usim_clock_stop_enum clock_stop;
+ usim_speed_enum speed;
+} usim_info_struct;
+
+typedef struct
+{
+ // before reset
+ kal_bool high_speed_en; // control if high speed is enalbed
+ usim_power_enum power_in; // expected power class input form application layer
+ // after reset
+ usim_clock_stop_enum clock_stop_type;
+} usim_config_struct;
+
+typedef struct
+{
+ kal_eventgrpid event;
+ usim_power_enum power; // power class used
+ usim_status_enum status;
+ usim_speed_enum speed; // speed selected
+ // state control
+ volatile usim_main_state_enum main_state;
+ volatile usim_status_enum ev_status;
+ // informations
+ usim_dir_enum dir; // convention of character frame
+ sim_protocol_app_enum app_proto; // application protocol (USIM, SIM)
+ sim_protocol_phy_enum phy_proto; // protocol type selected (physical layer)
+
+ // ATR info
+ kal_uint8 ATR_data[36]; // used to store all ATR data string
+ kal_uint8 ATR_index; // index to the ATR_data
+ kal_uint8 header_tx[4], header_tx_bak[4]; // header_tx_bak used to backup the previous command
+ kal_uint8 header_rx[4];
+ kal_uint8 dma_buffer[USIM_DMA_MAX_SIZE];
+ kal_uint8 retry;
+
+ sim_env sim_env; // the voltage which MS can supply
+ usim_power_enum power_in; // expected power class input form application layer
+ usim_power_enum power_class; // supported power class indicated at ATR
+ kal_bool clock_stop_en; // clock_stop is enabled or not
+ // usim_protocol_enum T;
+ usim_speed_enum card_speed; // TA1, max speed card can support
+ kal_bool high_speed_en; // control if high speed is enalbed
+ usim_clock_stop_enum clock_stop_type;
+ kal_bool present;
+ usim_reset_type_enum reset_mode; // specific or negotiable mode
+ kal_bool warm_rst; // KAL_TRUE: it's a warm reset, KAL_FALSE: a cold reset
+ kal_bool T0_support; // if T0 is supported
+ kal_bool T1_support; // if T1 is supported
+ kal_uint8 Di;
+
+ // T=1
+ kal_uint8 ns; // sequence # of sending
+ kal_uint8 nr; // sequence # of receiving
+ kal_uint8 ifsd; // information size of interface device
+ kal_uint8 ifsc; // information size of card
+ usim_cmd_state_enum cmd_state;
+ usim_cmd_state_enum cmd_state_bak;
+ kal_bool abort;
+ kal_bool wtx; // waiting time extension
+ kal_bool resync;
+ kal_bool send_prev; // send the previous block
+ kal_bool tx_chain;
+ kal_bool rx_chain;
+ kal_uint8 *tx_buf;
+ kal_uint8 *rx_buf;
+ kal_uint8 sw[2]; // used to contain SW1 and SW2
+ kal_uint8 wtx_m; // multiplier of BWT
+
+ // others
+ kal_bool ts_hsk_en; // enable handshake at TS byte (error signal and char repetition)
+
+#ifdef SIM_ADDDMA
+ Sim_HDMA_struct dma_config;
+#endif
+ kal_uint8 hist_index; // index to the historical characters
+ usim_cmd_case_enum cmd_case;
+ sim_protocol_phy_enum perfer_phy_proto; // protocol type selected (physical layer)
+ /*SIM task need following information for UICC identification*/
+ kal_bool TAiExist; //if the first TA for T=15 is existed
+#if defined(USIM_DEBUG)
+ kal_int32 sline[INDEX_COUNT]; // set event at the which line in usim_drv.c
+ kal_uint32 sindex; // index to the sline[4]
+ kal_int32 wline[INDEX_COUNT]; // wait event at the which line in usim_drv.c
+ kal_uint32 windex; // index to the wline
+#endif
+ kal_uint16 tx_size;
+ kal_uint16 rx_size;
+ kal_uint16 tx_index;
+ kal_uint16 rx_index;
+
+ kal_uint16 Fi;
+ kal_uint16 etu_of_1860;
+ kal_uint16 etu_of_700;
+ kal_uint32 gpt_handle;
+
+ // time out control
+ kal_uint32 WWT; // work waiting time (T0)
+ kal_uint32 CWT; // character waiting time in etu(T1)
+ kal_uint32 BWT; // blcok waiting time in etu(T1)
+ kal_uint32 timeout; // etu
+ kal_uint32 ev_flag;
+ kal_hisrid hisr;
+ kal_uint32 int_status;
+
+ /*
+ following variables are get from global variables for 2 SIM projects.
+ We won't use these in single SIM driver, but we need to define the power set.
+ */
+ kal_taskid ownerTask; // the task that own this control block
+
+ kal_uint32 processingState; //to to reentry check
+ kal_bool isSW6263; // query if status word 0x62xx 0x63xx happen
+ kal_uint32 previous_state;
+ kal_uint32 atr_count;
+#if defined (SIM_AUTO_TEST)
+ kal_bool auto_test; // auto test for MTK internal
+#endif
+ kal_uint32 intsta[10];
+ kal_uint32 intcnt;
+#if defined(SIM_DRV_IC_USB)
+ kal_bool isIcUsb; // query if support ic usb
+ kal_bool isIcUsbRecPPS; // query if support ic usb PPS resp received
+ kal_uint32 uart_sim_ccci_handle;
+ usim_icusb_state_enum icusb_state;
+ kal_uint8 icusb_ATR_data[36]; // used to store all ATR data string
+ kal_uint8 icusb_ATR_index; // index to the ATR_data
+ kal_uint32 waitingTime; // waitingTime
+ kal_bool forceISO;
+#endif
+ kal_bool isPrefer3V; // prefer3v
+ kal_uint8 TB15; // query if support ic usb
+ kal_uint8 TA2;
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_bool poll_sim_2s;
+#endif
+#if defined(__SIM_ACTIVATION_V2__)
+ kal_uint32 gpt_handle_for_SIM_activation;
+ kal_uint32 gpio_handle_for_SIO;
+ kal_bool activation_v2;
+#endif
+#if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ kal_bool retry_3v_prefer;
+#endif
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ kal_bool retry_special_mode_prefer;
+#endif
+ kal_bool hasPowerClass;
+ kal_uint8 PowerClass;
+ kal_bool stopSimClkInEndOfAction;
+ kal_bool Support_Extended_Length;
+ kal_bool simInitialized;
+ volatile usim_status_enum error_status;
+} usim_dcb_struct;
+
+extern usim_dcb_struct usim_dcb;
+
+
+typedef struct
+{
+ sim_msgTag tag;
+ kal_uint32 event;
+ kal_uint32 data1;
+ kal_uint32 data2;
+ kal_uint32 time;
+} sim_msg;
+
+typedef usim_status_enum(*SIM_API_RESET)(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, sim_HW_cb *hw_cb);
+typedef sim_status(*SIM_API_CMD)(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_PWROFF)(sim_HW_cb *hw_cb);
+typedef void (*SIM_API_CARDINFO)(sim_info_struct *info, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_ENHANCED_SPEED)(kal_bool enable, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_ENHANCED_SELECT_PHY)(sim_protocol_phy_enum T, sim_HW_cb *hw_cb);
+typedef kal_bool(*SIM_API_SET_CLKSTOP)(sim_clock_stop_enum mode, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_EOC)(sim_HW_cb *hw_cb);
+typedef void (*SIM_API_MSG)(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+typedef void (*SIM_API_TOUT_TEST)(kal_uint32 toutValue, sim_HW_cb *hw_cb);
+
+
+typedef struct
+{
+ SIM_API_RESET reset;
+ SIM_API_CMD command;
+ SIM_API_PWROFF powerOff;
+ SIM_API_CARDINFO getCardInfo;
+ SIM_API_ENHANCED_SPEED enableEnhancedSpeed;
+ SIM_API_ENHANCED_SELECT_PHY selectPreferPhyLayer;
+ SIM_API_SET_CLKSTOP setClockStopMode;
+ SIM_API_EOC EOC;/*use this to hook necessary action before return to SIM task, this is called by adaption layer, not SIM task*/
+ SIM_API_MSG addMessage;
+ SIM_API_TOUT_TEST toutTest;
+} sim_ctrlDriver;
+
+#define USIM_LP_DISABLE 0x40
+#define USIM_LP_ENABLE 0x80
+#define USIM_LP_MASK_NORMAL_VSIM_CURRENT 0x01
+#define USIM_LP_MASK_REDUCE_VSIM_CURRENT 0x02
+#define USIM_LP_MASK_NORMAL_26M 0x04
+#define USIM_LP_MASK_FORCE_ON_26M 0x08
+#define USIM_LP_MASK_START_SCLK 0x10
+#define USIM_LP_MASK_STOP_SCLK 0x20
+
+#if defined(__LOCK_VSIM__)
+typedef struct
+{
+ kal_uint8 lock_vsim;
+} sim_nfc_communication;
+#endif // #if defined(__LOCK_VSIM__)
+
+#endif /*__SIM_DRV_SW_STRUCT_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_hw.h b/mcu/driver/devdrv/usim/inc/sim_hw.h
new file mode 100644
index 0000000..930554f
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_hw.h
@@ -0,0 +1,556 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for SIM driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+/*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/
+#include "sim_drv_HW_reg_MTK.h"
+#else
+
+/*RHR*/
+#include "reg_base.h"
+/*RHR*/
+
+#ifndef _SIM_HW_H
+#define _SIM_HW_H
+
+
+//#if ( (!defined(MT6208)) && (!defined(FPGA)) && (!defined(MT6205)) && (!defined(MT6205B)) && (!defined(MT6218)) )
+#if !defined(DRV_SIM_REG_6208_SERIES) && !defined(DRV_SIM_REG_6205B_SERIES)
+/*MT6218B || MT6219 || MT6217 || MT6226 || MT6227 || MT6228 || MT6229*/
+
+#ifdef SIM_NAMING_FROM_0_ADDRESS
+
+ #ifdef SIM_base
+ #undef SIM_base
+ #endif
+ #define SIM_base SIM0_base
+
+ #ifdef SIM2_base
+ #undef SIM2_base
+ #endif
+ #define SIM2_base SIM1_base
+
+#endif //SIM_NAMING_FROM_0_ADDRESS
+
+#ifdef SIM_DVT_ON_SIM2
+ #undef SIM_base
+ #define SIM_base SIM2_base
+#endif
+
+#define ACK_NULL_CHAR 0x60
+
+#define SIM_CTRL (SIM_base+0x0)
+#define SIM_CONF (SIM_base+0x4)
+#define SIM_BRR (SIM_base+0x8)
+#define SIM_IRQEN (SIM_base+0x10)
+#define SIM_STS (SIM_base+0x14)
+
+#define SIM_RETRY (SIM_base+0x20)
+#define SIM_TIDE (SIM_base+0x24)
+
+#define SIM_DATA (SIM_base+0x30)
+#define SIM_COUNT (SIM_base+0x34)
+
+#define SIM_ATIME (SIM_base+0x40)
+#define SIM_DTIME (SIM_base+0x44)
+#define SIM_TOUT (SIM_base+0x48)
+
+#define SIM_INS (SIM_base+0x60)
+#define SIM_IMP3 (SIM_base+0x64)
+#define SIM_SW1 (SIM_base+0x68)
+#define SIM_SW2 (SIM_base+0x6c)
+#define SIM_REG_STATUS (SIM_base+0x74)
+
+//SIM_CTRL
+#define SIM_CTRL_SIMON 0x0001
+#define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+#define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+
+//SIM_CONF
+#define SIM_CONF_RXHSK 0x0001
+#define SIM_CONF_TXHSK 0x0002
+#define SIM_CONF_CLKPO 0x0004
+#define SIM_CONF_SINV 0x0008
+#define SIM_CONF_SDIR 0x0010
+#define SIM_CONF_ODDPARITY 0x0020
+#define SIM_CONF_SIMSEL 0x0040
+#define SIM_CONF_TOUTEN 0x0080
+#define SIM_CONF_T0EN 0x0200
+#define SIM_CONF_HFEN 0x0400
+#define SIM_CONF_T1EN 0x0100
+
+#define SIM_CONF_Direct 0x0000
+#define SIM_CONF_InDirect 0x0038
+
+//SIM_BRR
+#define SIM_BRR_CLKMSK 0x0003
+#define SIM_BRR_CLK_Div2 0x0000
+#define SIM_BRR_CLK_Div4 0x0001
+#define SIM_BRR_CLK_Div8 0x0002
+#define SIM_BRR_CLK_Div12 0x0003
+
+#define SIM_BRR_ETUMSK 0x07FC
+#define SIM_BRR_BAUDMSK 0x000C
+//#if ( (defined(MT6218B)) || (defined(MT6219)))
+#if defined(DRV_SIM_REG_BAUD_6218B_SERIES)
+ #define SIM_BRR_BAUD_Div372 (0x16<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (0x03<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (0x01<<2) //F=512, D=16
+#else /*!Mt6218B,MT6219*/
+ #define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16
+ #define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32
+#endif /*MT6218B,MT6219*/
+
+//SIM_IRQEN
+#define SIM_IRQEN_TX 0x0001
+#define SIM_IRQEN_RX 0x0002
+#define SIM_IRQEN_OV 0x0004
+#define SIM_IRQEN_TOUT 0x0008
+#define SIM_IRQEN_TXERR 0x0010
+#define SIM_IRQEN_NATR 0x0020
+#define SIM_IRQEN_SIMOFF 0x0040
+#define SIM_IRQEN_T0END 0x0080
+#define SIM_IRQEN_RXERR 0x0100
+
+#define SIM_IRQEN_ALL 0x01bf
+#define SIM_IRQEN_ALLOFF 0x0000
+/* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+#define SIM_IRQEN_Normal 0x013e
+/*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/
+#define SIM_IRQEN_CMDNormal 0x019e
+/*#define SIM_IRQEN_CMDNormal 0x019c*/
+#define SIM_IRQEN_CMDDMANormal 0x019c
+#define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR)
+#define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR)
+#define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \
+ SIM_STS_OV|SIM_STS_TOUT)
+#define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX)
+#define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END)
+
+//SIM_STS
+#define SIM_STS_TX 0x0001
+#define SIM_STS_RX 0x0002
+#define SIM_STS_OV 0x0004
+#define SIM_STS_TOUT 0x0008
+#define SIM_STS_TXERR 0x0010
+#define SIM_STS_NATR 0x0020
+#define SIM_STS_SIMOFF 0x0040
+#define SIM_STS_T0END 0x0080
+#define SIM_STS_RXERR 0x0100
+#define SIM_STS_T1END 0x0200
+#define SIM_STS_EDCERR 0x0400
+
+//SIM_TOUT
+#define SIM_TOUT_MSK 0x3fff
+
+//SIM_RETRY
+#define SIM_RETRY_RXMASK 0x0007
+#define SIM_RETRY_TXMASK 0x0700
+
+//SIM_TIDE
+#define SIM_TIDE_RXMASK 0x000f
+#define SIM_TIDE_TXMASK 0x0f00
+
+//SIM_COUNT
+#define SIM_COUNT_MASK 0x000f
+
+//SIM_INS
+#define SIM_INS_MASK 0x00ff
+#define SIM_INS_INSD 0x0100
+
+//SIM_IMP3
+#define SIM_IMP3_MASK 0x01ff
+
+// SIM_STATUS
+#define SIM_STATUS_EDC 0x40
+#define SIM_STATUS_ACK 0x20
+#define SIM_STATUS_NACK 0x10
+#define SIM_STATUS_IDLE 0x01
+#define SIM_STATUS_INS 0x02
+#define SIM_STATUS_SW1 0x04
+#define SIM_STATUS_SW2 0x08
+
+#define SIM_TX_DELAY_LEN 0x4
+#define SIM_TX_DELAY_LOOP 4000
+#endif /*MT6218B*/
+
+//#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_REG_6205B_SERIES)
+ #define ACK_NULL_CHAR 0x60
+
+ #define SIM_CTRL (SIM_base+0x0)
+ #define SIM_CONF (SIM_base+0x4)
+ #define SIM_BRR (SIM_base+0x8)
+ #define SIM_IRQEN (SIM_base+0xc)
+ #define SIM_STS (SIM_base+0x10)
+ #define SIM_DATA (SIM_base+0x14)
+ #define SIM_TOUT (SIM_base+0x18)
+ #define SIM_RETRY (SIM_base+0x1c)
+ #define SIM_TIDE (SIM_base+0x20)
+ #define SIM_COUNT (SIM_base+0x24)
+ #define SIM_ATIME (SIM_base+0x28)
+ #define SIM_DTIME (SIM_base+0x2C)
+ #define SIM_INS (SIM_base+0x30)
+ #define SIM_IMP3 (SIM_base+0x34)
+ #define SIM_SW1 (SIM_base+0x38)
+ #define SIM_SW2 (SIM_base+0x3c)
+
+
+ //SIM_CTRL
+ #define SIM_CTRL_SIMON 0x0001
+ #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+ #define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+
+ //SIM_CONF
+ #define SIM_CONF_RXHSK 0x0001
+ #define SIM_CONF_TXHSK 0x0002
+ #define SIM_CONF_CLKPO 0x0004
+ #define SIM_CONF_SINV 0x0008
+ #define SIM_CONF_SDIR 0x0010
+ #define SIM_CONF_ODDPARITY 0x0020
+ #define SIM_CONF_SIMSEL 0x0040
+ #define SIM_CONF_TOUTEN 0x0080
+ #define SIM_CONF_HALTEN 0x0100
+ #define SIM_CONF_T0EN 0x0200
+ #define SIM_CONF_HFEN 0x0400
+
+ #define SIM_CONF_Direct 0x0000
+ #define SIM_CONF_InDirect 0x0038
+
+ //SIM_BRR
+ #define SIM_BRR_CLKMSK 0x0003
+ #define SIM_BRR_CLK_Div2 0x0000
+ #define SIM_BRR_CLK_Div4 0x0001
+ #define SIM_BRR_CLK_Div8 0x0002
+ #define SIM_BRR_CLK_Div12 0x0003
+
+ #define SIM_BRR_ETUMSK 0x07FC
+ #define SIM_BRR_BAUDMSK 0x000C
+ //#ifdef MT6205B
+ #if defined(DRV_SIM_REG_BAUD_6205B)
+ #define SIM_BRR_BAUD_Div372 0x000c //F=372, D=1
+ #define SIM_BRR_BAUD_Div368 0x0000 //F=368, D=1
+ #else /*!MT6205B*/
+ #define SIM_BRR_BAUD_Div372 0x0000 //F=372, D=1
+ #endif /*MT6205B*/
+ #define SIM_BRR_BAUD_Div64 0x0004 //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 0x0008 //F=512, D=16
+
+ //SIM_IRQEN
+ #define SIM_IRQEN_TX 0x0001
+ #define SIM_IRQEN_RX 0x0002
+ #define SIM_IRQEN_OV 0x0004
+ #define SIM_IRQEN_TOUT 0x0008
+ #define SIM_IRQEN_TXERR 0x0010
+ #define SIM_IRQEN_NATR 0x0020
+ #define SIM_IRQEN_SIMOFF 0x0040
+ #define SIM_IRQEN_T0END 0x0080
+ #define SIM_IRQEN_RXERR 0x0100
+
+ #define SIM_IRQEN_ALL 0x01bf
+ #define SIM_IRQEN_ALLOFF 0x0000
+ /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+ #define SIM_IRQEN_Normal 0x013e
+ /*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/
+ #define SIM_IRQEN_CMDNormal 0x019e
+ /*#define SIM_IRQEN_CMDNormal 0x019c*/
+ #define SIM_IRQEN_CMDDMANormal 0x019c
+
+ //SIM_STS
+ #define SIM_STS_TX 0x0001
+ #define SIM_STS_RX 0x0002
+ #define SIM_STS_OV 0x0004
+ #define SIM_STS_TOUT 0x0008
+ #define SIM_STS_TXERR 0x0010
+ #define SIM_STS_NATR 0x0020
+ #define SIM_STS_SIMOFF 0x0040
+ #define SIM_STS_T0END 0x0080
+ #define SIM_STS_RXERR 0x0100
+
+ //SIM_TOUT
+ #define SIM_TOUT_MSK 0x3fff
+
+ //SIM_RETRY
+ #define SIM_RETRY_RXMASK 0x0007
+ #define SIM_RETRY_TXMASK 0x0700
+
+ //SIM_TIDE
+ #define SIM_TIDE_RXMASK 0x000f
+ #define SIM_TIDE_TXMASK 0x0f00
+
+ //SIM_COUNT
+ #define SIM_COUNT_MASK 0x000f
+
+ //SIM_INS
+ #define SIM_INS_MASK 0x00ff
+ #define SIM_INS_INSD 0x0100
+
+ //SIM_IMP3
+ #define SIM_IMP3_MASK 0x01ff
+#endif /*(MT6205,MT6205B,MT6218)*/
+
+//#if ( (defined(MT6208)) || (defined(FPGA)) )
+#if defined(DRV_SIM_MT6208_SERIES)
+ #define MAX_FIFO_SIZE 31
+ #define ACK_NULL_CHAR 0x60
+
+ #define LISR_COMPLETE 0x80
+
+ #define SIM_CTRL (SIM_base+0x0)
+ #define SIM_CONF (SIM_base+0x4)
+ #define SIM_BRR (SIM_base+0x8)
+ #define SIM_IRQEN (SIM_base+0xc)
+ #define SIM_STS (SIM_base+0x10)
+ #define SIM_DATA (SIM_base+0x14)
+ #define SIM_TOUT (SIM_base+0x18)
+ #define SIM_RETRY (SIM_base+0x1c)
+ #define SIM_TIDE (SIM_base+0x20)
+ #define SIM_COUNT (SIM_base+0x24)
+ #define SIM_ATIME (SIM_base+0x28)
+ #define SIM_DTIME (SIM_base+0x2C)
+
+
+ //SIM_CTRL
+ #define SIM_CTRL_SIMON 0x0001
+ #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+
+ //SIM_CONF
+ #define SIM_CONF_RXHSK 0x0001
+ #define SIM_CONF_TXHSK 0x0002
+ #define SIM_CONF_CLKPO 0x0004
+ #define SIM_CONF_SINV 0x0008
+ #define SIM_CONF_SDIR 0x0010
+ #define SIM_CONF_ODDPARITY 0x0020
+ #define SIM_CONF_SIMSEL 0x0040
+ #define SIM_CONF_TOUTEN 0x0080
+
+ #define SIM_CONF_Direct 0x0000
+ #define SIM_CONF_InDirect 0x0038
+
+ //SIM_BRR
+ #define SIM_BRR_CLKMSK 0x0003
+ #define SIM_BRR_CLK_Div2 0x0000
+ #define SIM_BRR_CLK_Div4 0x0001
+ #define SIM_BRR_CLK_Div8 0x0002
+ #define SIM_BRR_CLK_Div12 0x0003
+
+ #define SIM_BRR_ETUMSK 0x07FC
+ #define SIM_BRR_BAUDMSK 0x000C
+ #define SIM_BRR_BAUD_Div372 0x0000 //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 0x0004 //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 0x0008 //F=512, D=16
+
+ //SIM_IRQEN
+ #define SIM_IRQEN_TX 0x0001
+ #define SIM_IRQEN_RX 0x0002
+ #define SIM_IRQEN_OV 0x0004
+ #define SIM_IRQEN_TOUT 0x0008
+ #define SIM_IRQEN_TXERR 0x0010
+ #define SIM_IRQEN_NATR 0x0020
+ #define SIM_IRQEN_SIMOFF 0x0040
+
+ #define SIM_IRQEN_ALL 0x01bf
+ #define SIM_IRQEN_ALLOFF 0x0000
+ /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+ #define SIM_IRQEN_Normal 0x03e
+
+ //SIM_STS
+
+ #define SIM_STS_TX 0x0001
+ #define SIM_STS_RX 0x0002
+ #define SIM_STS_OV 0x0004
+ #define SIM_STS_TOUT 0x0008
+ #define SIM_STS_TXERR 0x0010
+ #define SIM_STS_NATR 0x0020
+ #define SIM_STS_SIMOFF 0x0040
+
+ //SIM_DATA
+ #define SIM_DATA_DATAMSK 0x00ff
+ #define SIM_DATA_PARITY 0x0100
+
+ //SIM_TOUT
+ #define SIM_TOUT_MSK 0x3fff
+
+ //SIM_RETRY
+ #define SIM_RETRY_RXMASK 0x0007
+ #define SIM_RETRY_TXMASK 0x0700
+
+ //SIM_TIDE
+ #define SIM_TIDE_RXMASK 0x001f
+ #define SIM_TIDE_TXMASK 0x1f00
+
+ //SIM_TXCNT
+ #define SIM_COUNT_MASK 0x001f
+#endif /*(MT6208,FPGA)*/
+
+#endif /*_SIM_HW_H*/
+
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_hw_mtk.h b/mcu/driver/devdrv/usim/inc/sim_hw_mtk.h
new file mode 100644
index 0000000..7ed70f2
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_hw_mtk.h
@@ -0,0 +1,320 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_hw_mtk.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for MTK SIM driver in multiple sim interface solution code.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "drv_features.h"
+#include "reg_base.h"
+/*RHR*/
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+/*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/
+#include "sim_drv_HW_reg_MTK.h"
+#else
+#ifndef _SIM_HW_H
+#define _SIM_HW_H
+
+//#if ( (!defined(MT6208)) && (!defined(FPGA)) && (!defined(MT6205)) && (!defined(MT6205B)) && (!defined(MT6218)) )
+#if !defined(DRV_SIM_REG_6208_SERIES) && !defined(DRV_SIM_REG_6205B_SERIES)
+/*MT6218B || MT6219 || MT6217 || MT6226 || MT6227 || MT6228 || MT6229*/
+
+#ifdef SIM_NAMING_FROM_0_ADDRESS
+
+ #ifdef SIM_base
+ #undef SIM_base
+ #endif
+ #define SIM_base SIM0_base
+
+ #ifdef SIM2_base
+ #undef SIM2_base
+ #endif
+ #define SIM2_base SIM1_base
+
+#endif //SIM_NAMING_FROM_0_ADDRESS
+
+#define ACK_NULL_CHAR 0x60
+
+#define SIM_CTRL (SIM_base+0x0)
+#define SIM_CONF (SIM_base+0x4)
+#define SIM_BRR (SIM_base+0x8)
+#define SIM_IRQEN (SIM_base+0x10)
+#define SIM_STS (SIM_base+0x14)
+
+#define SIM_RETRY (SIM_base+0x20)
+#define SIM_TIDE (SIM_base+0x24)
+
+#define SIM_DATA (SIM_base+0x30)
+#define SIM_COUNT (SIM_base+0x34)
+
+#define SIM_ATIME (SIM_base+0x40)
+#define SIM_DTIME (SIM_base+0x44)
+#define SIM_TOUT (SIM_base+0x48)
+
+#define SIM_INS (SIM_base+0x60)
+#define SIM_IMP3 (SIM_base+0x64)
+#define SIM_SW1 (SIM_base+0x68)
+#define SIM_SW2 (SIM_base+0x6c)
+#define SIM_REG_STATUS (SIM_base+0x74)
+
+#define SIM_ADDR_OFFSET 0x90000
+
+#ifndef DRV_2_SIM_CONTROLLER
+ #define SIM0_BASE_ADDR_MTK SIM_base
+#else //DRV_2_SIM_CONTROLLER is defined
+ //SIM0_BASE_ADDR_MTK is used in Gemini project, to make code integrity, we use this in dual controller solution, too
+ //simInterface should be local variable when this MACRO called, this won't make race condition
+ #define SIM0_BASE_ADDR_MTK (SIM_base + ((SIM2_base-SIM_base)*simInterface))
+#endif
+#define SIM_CTRL_MTK 0x0
+#define SIM_CONF_MTK 0x4
+#define SIM_BRR_MTK 0x8
+#define SIM_IRQEN_MTK 0x10
+#define SIM_STS_MTK 0x14
+
+#define SIM_RETRY_MTK 0x20
+#define SIM_TIDE_MTK 0x24
+
+#define SIM_DATA_MTK 0x30
+#define SIM_COUNT_MTK 0x34
+
+#define SIM_ATIME_MTK 0x40
+#define SIM_DTIME_MTK 0x44
+#define SIM_TOUT_MTK 0x48
+
+#define SIM_INS_MTK 0x60
+#define SIM_IMP3_MTK 0x64
+#define SIM_SW1_MTK 0x68
+#define SIM_SW2_MTK 0x6c
+#define SIM_STATUS_MTK 0x74
+
+
+//SIM_CTRL
+#define SIM_CTRL_SIMON 0x0001
+#define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+#define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+
+//SIM_CONF
+#define SIM_CONF_RXHSK 0x0001
+#define SIM_CONF_TXHSK 0x0002
+#define SIM_CONF_CLKPO 0x0004
+#define SIM_CONF_SINV 0x0008
+#define SIM_CONF_SDIR 0x0010
+#define SIM_CONF_ODDPARITY 0x0020
+#define SIM_CONF_SIMSEL 0x0040
+#define SIM_CONF_TOUTEN 0x0080
+#define SIM_CONF_T0EN 0x0200
+#define SIM_CONF_HFEN 0x0400
+#define SIM_CONF_T1EN 0x0100
+
+#define SIM_CONF_Direct 0x0000
+#define SIM_CONF_InDirect 0x0038
+
+//SIM_BRR
+#define SIM_BRR_CLKMSK 0x0003
+#define SIM_BRR_CLK_Div2 0x0000
+#define SIM_BRR_CLK_Div4 0x0001
+#define SIM_BRR_CLK_Div8 0x0002
+#define SIM_BRR_CLK_Div12 0x0003
+
+#define SIM_BRR_ETUMSK 0x07FC
+#define SIM_BRR_BAUDMSK 0x000C
+//#if ( (defined(MT6218B)) || (defined(MT6219)))
+#if defined(DRV_SIM_REG_BAUD_6218B_SERIES)
+ #define SIM_BRR_BAUD_Div372 (0x16<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (0x03<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (0x01<<2) //F=512, D=16
+#else /*!Mt6218B,MT6219*/
+ #define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16
+ #define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32
+#endif /*MT6218B,MT6219*/
+
+//SIM_IRQEN
+#define SIM_IRQEN_TX 0x0001
+#define SIM_IRQEN_RX 0x0002
+#define SIM_IRQEN_OV 0x0004
+#define SIM_IRQEN_TOUT 0x0008
+#define SIM_IRQEN_TXERR 0x0010
+#define SIM_IRQEN_NATR 0x0020
+#define SIM_IRQEN_SIMOFF 0x0040
+#define SIM_IRQEN_T0END 0x0080
+#define SIM_IRQEN_RXERR 0x0100
+
+#define SIM_IRQEN_ALL 0x01bf
+#define SIM_IRQEN_ALLOFF 0x0000
+/* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+#define SIM_IRQEN_Normal 0x013e
+/*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/
+#define SIM_IRQEN_CMDNormal 0x019e
+/*#define SIM_IRQEN_CMDNormal 0x019c*/
+#define SIM_IRQEN_CMDDMANormal 0x019c
+#define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR)
+#define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR)
+#define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \
+ SIM_STS_OV|SIM_STS_TOUT)
+#define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX)
+#define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END)
+
+//SIM_STS
+#define SIM_STS_TX 0x0001
+#define SIM_STS_RX 0x0002
+#define SIM_STS_OV 0x0004
+#define SIM_STS_TOUT 0x0008
+#define SIM_STS_TXERR 0x0010
+#define SIM_STS_NATR 0x0020
+#define SIM_STS_SIMOFF 0x0040
+#define SIM_STS_T0END 0x0080
+#define SIM_STS_RXERR 0x0100
+#define SIM_STS_T1END 0x0200
+#define SIM_STS_EDCERR 0x0400
+
+//SIM_TOUT
+#define SIM_TOUT_MSK 0x3fff
+
+//SIM_RETRY
+#define SIM_RETRY_RXMASK 0x0007
+#define SIM_RETRY_TXMASK 0x0700
+
+//SIM_TIDE
+#define SIM_TIDE_RXMASK 0x000f
+#define SIM_TIDE_TXMASK 0x0f00
+
+//SIM_COUNT
+#define SIM_COUNT_MASK 0x000f
+
+//SIM_INS
+#define SIM_INS_MASK 0x00ff
+#define SIM_INS_INSD 0x0100
+
+//SIM_IMP3
+#define SIM_IMP3_MASK 0x01ff
+
+// SIM_STATUS
+#define SIM_STATUS_EDC 0x40
+#define SIM_STATUS_ACK 0x20
+#define SIM_STATUS_NACK 0x10
+#define SIM_STATUS_IDLE 0x01
+#define SIM_STATUS_INS 0x02
+#define SIM_STATUS_SW1 0x04
+#define SIM_STATUS_SW2 0x08
+
+#define SIM_TX_DELAY_LEN 0x4
+#define SIM_TX_DELAY_LOOP 4000
+#endif /*MT6218B*/
+
+#endif /*_SIM_HW_H*/
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_mtk.h b/mcu/driver/devdrv/usim/inc/sim_mtk.h
new file mode 100644
index 0000000..e29771c
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_mtk.h
@@ -0,0 +1,221 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_mtk.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is the header file for MTK dual SIM controllers.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ *
+ * removed!
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+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "drv_features.h"
+#include "sim_sw_comm.h"
+#include "sim_hw_mtk.h"
+#include "sim_reg_adp.h"
+#include "intrCtrl.h"
+/*RHR*/
+
+#ifndef __SIM_DRV_MULTI_DRV_ARCH__
+#ifdef DRV_2_SIM_CONTROLLER
+typedef enum
+{
+ SIM_DRIVER_ACT = 0x00000001,
+ SIM_DRIVER_DEACT = 0x00000002,
+ SIM_PDNDIS = 0x00000003,
+ SIM_PDNEN = 0x00000004,
+ SIM_INT_SIM = 0x00000005,
+ SIM_INT_USIM = 0x00000006,
+ SIM_DRIVER_ACT_SIMD = 0x00000007,
+ SIM_DRIVER_DEACT_SIMD = 0x00000008,
+ SIM_CMD_TX_LOG = 0x00010001,
+ SIM_CMD_INS_LOG = 0x00010002,
+ SIM_CMD_TXDELAY = 0x00010003,
+ SIM_INIT_USIM = 0x00020001,
+ SIM_DEACTIVATE_1 = 0x00030001,
+ SIM_DEACTIVATE_2 = 0x00030002,
+ SIM_ACTION_RESET = 0x000F0001,
+ SIM_ACTION_POWOFF = 0x000F0002,
+ SIM_ACTION_COMMAND = 0x000F0003,
+ SIM_ACTION_EOC = 0x000F0004
+} sim_msgTag;
+
+typedef struct
+{
+ sim_msgTag tag;
+ kal_uint32 event;
+ kal_uint32 data1;
+ kal_uint32 data2;
+ kal_uint32 time;
+} sim_msg;
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+#define SIM_Reject_MTK(simInterface) \
+ {\
+ SIM_DisAllIntr(simInterface);\
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_addMsg(SIM_DRIVER_DEACT_SIMD, simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ SIM_ClearBits(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK, SIM_CTRL_SIMON);\
+ }\
+ else\
+ {\
+ sim_PDNEnable(simInterface);\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent_MTK(SimCard,SIM_NOREADY);\
+ }\
+ }
+#ifdef NO_SLIM_DEF
+/*********************************************************************************************
+*we move this macro from sim_sw_comm.h to here, since we need a distinguish from dual controllers or MT6302.
+*In dual controllers solution, we need to enable interrupt according to simInterface, but in MT6302 solution, we only need to enable SIM's.
+**********************************************************************************************/
+#define SIM_WaitEvent_MTK(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ extern void sim_dump_error_line(void);\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ sim_workingTaskWaiting = KAL_TRUE;\
+ if(KAL_TRUE == _unmaskSIMIntr){\
+ if(0 == simInterface)\
+ IRQUnmask(IRQ_USIM0_CODE);\
+ else\
+ IRQUnmask(IRQ_USIM1_CODE);\
+ }\
+ kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_workingTaskWaiting = KAL_FALSE;\
+ sim_dump_error_line();\
+ }
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+#define SIM_SetEvent_MTK(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+#endif /*#ifdef NO_SLIM_DEF*/
+#endif /*DRV_2_SIM_CONTROLLER*/
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_reg_adp.h b/mcu/driver/devdrv/usim/inc/sim_reg_adp.h
new file mode 100644
index 0000000..3a80938
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_reg_adp.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_reg_adp.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is to be an adaptation layer for all SIM related register functions.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "drv_comm.h"
+/*RHR*/
+#ifndef __SIM_REG_ADP_H__
+#define __SIM_REG_ADP_H__
+
+
+
+
+
+#ifdef __DRV_SIM_RW_DBG__
+ #define SIM_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+ #define SIM_Reg(addr) DRV_DBG_Reg(addr)
+ #define SIM_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+ #define SIM_Reg32(addr) DRV_DBG_Reg32(addr)
+ #define SIM_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+ #define SIM_Reg8(addr) DRV_DBG_Reg8(addr)
+ #define SIM_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+ #define SIM_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+ #define SIM_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+ #define SIM_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+ #define SIM_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+ #define SIM_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+ #define SIM_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+ #define SIM_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+ #define SIM_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+ #define SIM_WriteReg(addr,data) DRV_WriteReg(addr,data)
+ #define SIM_Reg(addr) DRV_Reg(addr)
+ #define SIM_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+ #define SIM_Reg32(addr) DRV_Reg32(addr)
+ #define SIM_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+ #define SIM_Reg8(addr) DRV_Reg8(addr)
+ #if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ #define SIM_ClearBits(addr,data) {MO_Sync();DRV_ClearBits(addr,data);}
+ #define SIM_SetBits(addr,data) {MO_Sync();DRV_SetBits(addr,data);}
+ #define SIM_SetData(addr, bitmask, value) {MO_Sync();DRV_SetData(addr, bitmask, value);}
+ #define SIM_ClearBits32(addr,data) {MO_Sync();DRV_ClearBits32(addr,data);}
+ #define SIM_SetBits32(addr,data) {MO_Sync();DRV_SetBits32(addr,data);}
+ #define SIM_SetData32(addr, bitmask, value) {MO_Sync();DRV_SetData32(addr, bitmask, value);}
+ #define SIM_ClearBits8(addr,data) {MO_Sync();DRV_ClearBits8(addr,data);}
+ #define SIM_SetBits8(addr,data) {MO_Sync();DRV_SetBits8(addr,data);}
+ #define SIM_SetData8(addr, bitmask, value) {MO_Sync();DRV_SetData8(addr, bitmask, value);}
+ #else
+ #define SIM_ClearBits(addr,data) DRV_ClearBits(addr,data)
+ #define SIM_SetBits(addr,data) DRV_SetBits(addr,data)
+ #define SIM_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+ #define SIM_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+ #define SIM_SetBits32(addr,data) DRV_SetBits32(addr,data)
+ #define SIM_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+ #define SIM_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+ #define SIM_SetBits8(addr,data) DRV_SetBits8(addr,data)
+ #define SIM_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+ #endif
+#endif
+
+
+
+
+
+#endif //__SIM_REG_ADP_H__
diff --git a/mcu/driver/devdrv/usim/inc/sim_sw_comm.h b/mcu/driver/devdrv/usim/inc/sim_sw_comm.h
new file mode 100644
index 0000000..893450e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_sw_comm.h
@@ -0,0 +1,634 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_sw_comm.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for different SIM drivers on multiple SIM solution.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "sim_al.h"
+#include "kal_public_api.h"
+#include "sim_hw_mtk.h"
+#include "sim_reg_adp.h"
+#include "drv_features.h"
+/*RHR*/
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+/*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/
+#include "sim_drv_HW_def_MTK.h"
+#include "sim_drv_SW_struct.h"
+#include "sim_drv_SW_function.h"
+#include "sim_drv_SW_API.h"
+#include "multi_icc_custom.h"
+#else /*__SIM_DRV_MULTI_DRV_ARCH__*/
+#ifndef _SIM_SW_H
+#define _SIM_SW_H
+
+
+
+//#define __30V_ONLY_ME__
+//#define __18V_ONLY_ME__
+//#define __18V_30V_ME__
+
+//#if ( (!defined(MT6208)) && (!defined(FPGA)) )
+#if ((!defined(DRV_SIM_MT6208_SERIES)) && (!defined(DRV_SIM_MT6205B_SERIES)))
+/* SIM_ADDDMA & NoT0CTRL can't active concurrently */
+#define SIM_ADDDMA
+//#define NoT0CTRL
+
+/* SIM Format */
+#define SIM_direct 0
+#define SIM_indirect 1
+
+/* SIM Power */
+#define SIM_30V RESET_30V
+#define SIM_18V RESET_18V
+
+#define CMD_RECBUFSIZE 13
+/*DMA setting, such usb*/
+/* Size = 8bit, sinc en, dinc disable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimTxNormal 0x0074
+/* Size = 8bit, sinc disable, dinc enable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimRxNormal 0x0078
+
+/* SIM State */
+#define SIM_WAIT_FOR_ATR 0 /* reset SIM card and wait ATR */
+#define SIM_PROCESS_ATR 1 /* receiving ATR data */
+#define SIM_PROCESS_PTS 2 /* receiving PTS response data */
+#define SIM_PROCESSCMD 3
+#define SIM_SERIOUSERR 4 /* serous error due to txerr*/
+#define SIM_PWROFF 5
+#define SIM_WaitRejectDone 6
+
+
+/* SIM Miner State */
+#ifdef NoT0CTRL
+ #define SIMD_CmdIdle 0
+ #define SIM_WaitProcByte 1
+ #define SIM_AckDataState 2
+ #define SIM_NAckDataState 3
+ #define SIM_WaitSWByte 4
+#endif /*NoT0CTRL*/
+/*just for clock stop mode*/
+#define SIM_ProcessClk 5
+#define SIM_StopClk 6
+#define SIM_WaitCmdEnd 7
+
+
+/* Event */
+#define ATR_END 0x0010
+#define PTS_END 0x0008
+#define SIM_EVT_CMD_END 0x0004
+#define RST_READY 0x0002
+#define CLK_PROC 0x0020
+#define ACTIVATE_DONE 0x0040
+/*#define INIRET 0x0001*/
+
+/*ATR data define*/
+#define TAMask 0x0010
+#define TBMask 0x0020
+#define TCMask 0x0040
+#define TDMask 0x0080
+
+/* Result */
+#define SIM_SUCCESS SIM_NO_ERROR
+#define SIM_NOREADY SIM_NO_INSERT
+#define SIM_CARDERR SIM_CARD_ERROR
+#define SIM_INITXERR 5
+#define SIM_INIPTSERR 6
+#define SIM_CMDTXERR 7 /* parity error */
+#define SIM_CMDRECERR 8
+#define SIM_CMDTOUT 9
+#define SIM_CLKPROC 10
+#define SIM_NULLTIMEOUT 11
+
+#define SW1_GET_RESP_SIM 0x9f
+#define SW1_GET_RESP_USIM 0x61
+#define SW1_RESEND_USIM 0x6c
+#define LEN_INDEX 4 // index to the P3 of command header
+#define LEN_OF_CMD 5
+#define GET_RESP_CLA_SIM 0xa0
+#define GET_RESP_CLA_USIM 0x00
+#define SW1_WARN1 0x62
+#define SW1_WARN2 0x63
+#define SIM_SW_STATUS_OK 0x9000
+#define SIM_SW_STATUS_FAIL 0x00
+
+#define Speed372 0
+#define Speed64 1
+#define Speed32 2
+#define Speed16 3
+
+typedef kal_uint16 sim_status;
+
+#define MAX_SIM_ERROR_LINE 4
+
+#ifdef SIM_DBG_OPTION_ENABLE
+#define SIM_ASSERT(_condition) \
+ { \
+ ASSERT(_condition); \
+ }
+#else /*!SIM_DBG_OPTION_ENABLE*/
+#if defined(SIM_DEBUG_INFO)
+#define SIM_ASSERT(_condition) \
+ { \
+ if (!(_condition)) \
+ { \
+ sim_assert(__LINE__); \
+ } \
+ }
+#else
+#define SIM_ASSERT(_condition)
+#endif /*#if defined(SIM_DEBUG_INFO)*/
+#endif /*SIM_DBG_OPTION_ENABLE*/
+
+typedef enum
+{
+ SIM_PROTOCOL,
+ USIM_PROTOCOL
+} sim_protocol_app_enum;
+
+typedef enum
+{
+ T0_PROTOCOL,
+ T1_PROTOCOL,
+ UNKNOWN_PROTOCOL
+} sim_protocol_phy_enum;
+
+typedef enum
+{
+ UNKNOWN_POWER_CLASS = 0,
+ CLASS_A_50V = 1,
+ CLASS_B_30V = 2,
+ CLASS_AB = 3,
+ CLASS_C_18V = 4,
+ ClASS_BC = 6,
+ CLASS_ABC = 7,
+ CLASS_ALLSUPPORT = 0xff
+} sim_power_enum;
+
+typedef enum
+{
+ CLOCK_STOP_NOT_SUPPORT = 0x0,
+ CLOCK_STOP_LOW = 0x40,
+ CLOCK_STOP_HIGH = 0x80,
+ CLOCK_STOP_ANY = 0xc0,
+ CLOCK_STOP_MSK = 0xc0,
+ CLOCK_STOP_UNKONW = 0x0f
+} sim_clock_stop_enum;
+
+typedef enum
+{
+ SPEED_372,
+ SPEED_64,
+ SPEED_32,
+ SPEED_16
+} sim_speed_enum;
+
+typedef enum
+{
+ SIM_DIRECT,
+ SIM_INVERSE
+} sim_dir_enum;
+
+typedef enum
+{
+ usim_case_1 = 1,
+ usim_case_2,
+ usim_case_3,
+ usim_case_4
+} usim_cmd_case_enum;
+
+typedef struct
+{
+ kal_uint32* ptr;
+ kal_uint32 size;
+} sim_nvram_param_struct;
+
+typedef struct
+{
+ sim_power_enum power;
+ sim_speed_enum speed;
+ sim_clock_stop_enum clock_stop;
+ sim_protocol_app_enum app_proto;
+ sim_protocol_phy_enum phy_proto;
+ kal_bool T0_support; // if T0 is supported
+ kal_bool T1_support; // if T1 is supported
+ kal_uint8 hist_index; // index to the historical char of ATR
+ kal_uint8 *ATR;
+ /*following information is necessary for SIM task for UICC identification*/
+ kal_bool TAiExist; //if the first TA for T=15 is existed
+} sim_info_struct;
+
+typedef struct
+{
+ kal_uint8 State;
+ kal_uint8 Data_format; /*SIM_direct,SIM_indirect*/
+ kal_uint8 Power; /*SIM_3V,SIM_5V*/
+ kal_uint8 recData[40]; /*PTS or ATR data*/
+ kal_bool recDataErr;
+ kal_uint16 recDataLen; /* for command, ATR process */
+ kal_uint8 result; /* for ATR, command, RST */
+ kal_uint32 EvtFlag;
+ sim_env SIM_ENV;
+#ifndef SIM_ADDDMA
+ kal_uint8 *txbuffer; /* only used for no DMA */
+ kal_uint16 txsize; /* only used for no DMA */
+ kal_uint16 txindex; /* only used for no DMA */
+ kal_uint8 *rxbuffer; /* only used for no DMA */
+#ifdef NoT0CTRL
+ kal_uint16 recsize;
+ kal_uint8 INS;
+ kal_uint8 SW1;
+ kal_uint8 SW2;
+#endif /*NoT0CTRL*/
+#endif /*SIM_ADDDMA*/
+ /*add for clock stop mode*/
+ kal_uint8 cmdState; /* only used for no T0CTRL, and for clock stop */
+ kal_uint8 Speed; /*Speed372,Speed64,Speed32*/
+ kal_bool clkStop; /*Clok Stop Enable*/
+ kal_bool clkStopLevel; /*Clok Stop level*/
+ kal_bool reject_set_event;
+ kal_bool event_state;
+ kal_uint8 initialPower;
+ sim_card_speed_type sim_card_speed;
+ kal_hisrid hisr; /*SIM HISR*/
+ kal_eventgrpid event; /*SIM Event*/
+
+ sim_protocol_app_enum app_proto;
+ kal_bool timeout;
+ usim_cmd_case_enum cmd_case;
+ kal_bool is_err; // sim command has error once.
+ kal_bool get9000WhenSelect;
+
+ /*following variables are get from global variables for 2 SIM projects*/
+ kal_uint32 TOUTValue;
+ kal_uint8 TOUT_Factor;
+ kal_uint8 sim_dmaport;
+ kal_uint8 reset_index;
+ DMA_HWMENU sim_menu;
+ DMA_INPUT sim_input;
+ kal_bool TS_HSK_ENABLE;
+ kal_bool sim_ATR_fail;
+ kal_bool PTS_check;
+ kal_uint8 PTS_data[4];
+
+} Sim_Card;
+
+
+#define GET_SIM_CB(a) &SimCard_cb[a]
+
+#define SIM_SetRXRetry(_RXRetry)\
+ {\
+ kal_uint16 _Retry;\
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_RXMASK;\
+ _Retry |= _RXRetry;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_SetTXRetry(_TXRetry) \
+ {\
+ kal_uint16 _Retry;\
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_TXMASK;\
+ _Retry |= (_TXRetry<<8);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_ObtainSW(_SW) \
+ {\
+ kal_uint16 _SW1;\
+ kal_uint16 _SW2;\
+ _SW1 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK);\
+ _SW2 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW2_MTK);\
+ _SW = (_SW2 | (_SW1 << 8));\
+ }
+
+#define SIM_SetIMP3(_IMP3) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), _IMP3)
+
+#define SIM_SetCmdINS(_INS) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_INS_MTK), _INS)
+
+#define SIM_SetAtime(_ATIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), _ATIME)
+
+#define SIM_SetDtime(_DTIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DTIME_MTK), _DTIME)
+
+#define SIM_FIFO_Flush() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), 0x01)
+
+#define SIM_Reject(simInterface) \
+ {\
+ SIM_DisAllIntr(simInterface);\
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_MT6302_addMsg(SIM_MT6302_DRIVER_DEACT, simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ if(KAL_FALSE == sim_MT6302_QueryNeedManualControl()){\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);\
+ sim_MT6302_VCCCtrl(simInterface, 0);\
+ }\
+ else{\
+ sim_MT6302_manualDeactive(simInterface);\
+ }\
+ }\
+ else\
+ {\
+ sim_PDNEnable(simInterface);\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent(SimCard,SIM_NOREADY);\
+ }\
+ }
+
+
+#define SIM_Active() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0x0001)
+
+
+#define SIM_WaitEvent(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ extern void sim_dump_error_line(void);\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ sim_workingTaskWaiting = KAL_TRUE;\
+ if(KAL_TRUE == _unmaskSIMIntr)\
+ IRQUnmask(IRQ_USIM0_CODE);\
+ kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_workingTaskWaiting = KAL_FALSE;\
+ sim_dump_error_line();\
+ }
+
+#define SIM_SetEvent(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,SIM_EVT_CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_MT6302_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+
+
+#define SIM_NotifyCARDisHALTEN() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN)
+#define SIM_T0CtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_T0CtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_FlowCtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+#define SIM_FlowCtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+
+#define SIM_DisIntr(_Intr) SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), _Intr)
+#define SIM_ActiveClk(simInterface) \
+ {\
+ sim_PDNDisable(simInterface);\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_Idle(_level, simInterface) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable(simInterface);\
+ }
+
+
+#define SIM_FIFO_GetLev(a) (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK) & SIM_COUNT_MASK)
+#define SIM_DisTOUTIntr(a) SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_OpenTOUTIntr(a) SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_DisAllIntr(a) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF)
+#ifdef SIM_TOUT_REG_V2
+#define SIM_SetTOUT(_TOUT) \
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ if (_TOUT < 0xffffff)\
+ SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), _TOUT);\
+ else\
+ SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffffff);\
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ }
+#else
+#define SIM_SetTOUT(_TOUT) \
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ if (_TOUT < 0xffff)\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), _TOUT);\
+ else\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffff);\
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ }
+#endif
+
+#ifdef NoT0CTRL
+#define SIMCmdInit()
+#else /*NoT0CTRL*/
+#define SIMCmdInit() \
+ {\
+ SIM_T0CtrlEnable(); /*SIM_FlowCtrlEnable()*/ \
+ }
+#endif /*NoT0CTRL*/
+
+extern void sim_assert(kal_uint32 line);
+extern kal_uint16 SIM_CMD(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error, kal_uint32 simInterface);
+extern void L1sim_ChangeBaud(void);
+extern void L1sim_NormalBaud(void);
+extern sim_card_speed_type L1sim_Get_CardSpeedType(kal_uint32 simInterface);
+extern void L1sim_Enable_Enhanced_Speed(kal_bool enable, kal_uint32 simInterface);
+extern kal_uint16 L1sim_Cmd_Layer(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, kal_uint32 simInterface);
+
+extern void SIM1_LDO_enable(kal_bool enable);
+extern void SIM2_LDO_enable(kal_bool enable);
+
+#endif /*(MT6208,FPGA)*/
+
+#endif /*_SIM_SW_H*/
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/mt6306/inc/mt63062.h b/mcu/driver/devdrv/usim/mt6306/inc/mt63062.h
new file mode 100644
index 0000000..047abf3
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/inc/mt63062.h
@@ -0,0 +1,120 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MT63062.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is the header file of MT6306 security
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MT63062_H__
+#define __MT63062_H__
+#include "sim_sw_comm.h"
+extern void sim_MT63062_Init(kal_uint32 chipNo);
+extern kal_uint8 sim_MT63062_Cmd(sim_HW_cb *hw_cb);
+extern void sim_MT63062_TakeI2Csem(void);
+extern void sim_MT63062_GiveI2Csem(void);
+#endif /*__MT63062_H__*/
+
diff --git a/mcu/driver/devdrv/usim/mt6306/inc/sim_mt6306.h b/mcu/driver/devdrv/usim/mt6306/inc/sim_mt6306.h
new file mode 100644
index 0000000..4205cd5
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/inc/sim_mt6306.h
@@ -0,0 +1,647 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_MT6302.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for header files for MT6302 related control code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
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+ * removed!
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+ *
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+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
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+ *
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+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __SIM_MT6306_H__
+#define __SIM_MT6306_H__
+
+#include "mt6306_i2c.h"
+
+#define __DRV_2_SIM_USING_MT6306__
+#define SIM_MT6306_MAX_INTERFACES 2
+#define SIM_MT6306_REG_NUMBER 9
+#define SIM_MT6306_REG_CARDSS 8
+#define SIM_MT6306_REG_RST 0
+#define SIM_MT6306_REG_CLK 1
+#define SIM_MT6306_REG_DAT 2
+#define SIM_MT6306_REG_VCC 3
+
+#define SIM_MT6306_CONFMSK 0x33B
+#define SIM_MT6306_SERVING_INTERFACE_NONE 0xff
+
+#if defined(DRV_SIM_DBG_LOW_COST_ULC)
+ #define SIM_MT6306_MSG_NUM 256
+#elif defined(DRV_SIM_DBG_LOW_COST_COMMON)
+ #define SIM_MT6306_MSG_NUM 512
+#else
+ #define SIM_MT6306_MSG_NUM 1024
+#endif
+
+#ifdef DRV_2_SIM_USING_LTC4558
+ #define SIM_MT6306_GPIO_LTC4558_CLKRUNA 4
+ #define SIM_MT6306_GPIO_LTC4558_CLKRUNB 7
+ #define SIM_MT6306_GPIO_LTC4558_ENABLEA 8
+ #define SIM_MT6306_GPIO_LTC4558_ENABLEB 9
+ #define SIM_MT6306_GPIO_LTC4558_CSEL 11
+ #define SIM_MT6306_GPIO_LTC4558_VSELA 12
+ #define SIM_MT6306_GPIO_LTC4558_VSELB 13
+#endif
+
+#ifndef __SIM_DRV_MULTI_DRV_ARCH__
+
+#define MT6306_RACE_PROTECT(a) \
+ { \
+ if(0 < MT6306_raceConditionProtect[a]) \
+ SIM_DEBUG_ASSERT(0); \
+ MT6306_raceConditionProtect[a] ++; \
+ }
+
+#define MT6306_RACE_RELEASE(a) \
+ {MT6306_raceConditionProtect[a] -- ;}
+
+#else
+#define MT6306_RP_TAKE_SEM(a)\
+ { \
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit()){ \
+ kal_take_sem(wait_sim_MT6306_RACE_PROTECT[a], KAL_INFINITE_WAIT);} \
+ }
+
+#define MT6306_RP_GIVE_SEM(a) \
+ { \
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit()){ \
+ kal_give_sem(wait_sim_MT6306_RACE_PROTECT[a]);} \
+ }
+
+#define MT6306_RACE_PROTECT(a) \
+ { \
+ MT6306_RP_TAKE_SEM(a); \
+ if(0 < switch_CB->MT6306_raceConditionProtect[a]) \
+ SIM_DEBUG_ASSERT(0); \
+ switch_CB->MT6306_raceConditionProtect[a] ++; \
+ }
+
+#define MT6306_RACE_RELEASE(a) \
+ { \
+ switch_CB->MT6306_raceConditionProtect[a] -- ; \
+ MT6306_RP_GIVE_SEM(a); \
+ Data_Sync_Barrier(); \
+ }
+#endif
+
+
+
+typedef enum
+{
+ SIM_MT6306_SELECT_LTC4558 = 0x00030001,
+ SIM_MT6306_RETREIVE_BAUD = 0x00030002,
+ SIM_MT6306_CLOCK_CTRL = 0x00030003,
+ SIM_MT6306_VCC_CTRL = 0x00030004,
+ SIM_MT6306_VCC_LVL_CTRL = 0x00030005,
+ SIM_MT6306_ACT_SIM_CTRL = 0x00030006,
+ SIM_MT6306_DEACT_SIM_CTRL = 0x00030007,
+ SIM_MT6306_RST_CTRL = 0x00030008,
+ SIM_MT6306_DAT_CTRL = 0x00030009,
+
+ SIM_MT6306_BLOCK_DAT = 0x00040001,
+ SIM_MT6306_BLOCK_RST = 0x00040002,
+ SIM_MT6306_PASS_DAT = 0x00040003,
+ SIM_MT6306_PASS_RST = 0x00040004,
+ SIM_MT6306_PASS_CLK = 0x00040005,
+ SIM_MT6306_BLOCK_CLK = 0x00040006,
+ SIM_MT6306_BLOCK_CLK_BEGIN = 0x00040007,
+ SIM_MT6306_NO_NEED_CLK_BEGIN = 0x00040008,
+
+ SIM_MT6306_D2D = 0x00050001,
+ SIM_MT6306_D2S = 0x00050002,
+ SIM_MT6306_R2D = 0x00050003,
+ SIM_MT6306_R2R = 0x00050004,
+ SIM_MT6306_R2S = 0x00050005,
+ SIM_MT6306_S2D = 0x00050006,
+ SIM_MT6306_S2R = 0x00050007,
+ SIM_MT6306_S2S = 0x00050008,
+ SIM_MT6306_D2R = 0x00050009, /*this is only valid in MT6306*/
+
+ SIM_MT6306_CHANGE_LISR = 0x00060001,
+ SIM_MT6306_CHANGE_CARD_STATE = 0x00060002,
+ SIM_MT6306_CHANGE_CURRENT_LISR = 0x00060003,
+ SIM_MT6306_CHANGE_CARD_TYPE = 0x00060004,
+
+ SIM_MT6306_DRIVER_ACT = 0x00070001,
+ SIM_MT6306_DRIVER_DEACT = 0x00070002,
+ SIM_MT6306_DRIVER_STOPCLK = 0x00070003,
+ SIM_MT6306_DRIVER_STARTCLK = 0x00070004,
+ SIM_MT6306_DRIVER_PDNEN = 0x00070005,
+ SIM_MT6306_DRIVER_PDNDIS = 0x00070006,
+ SIM_MT6306_DRIVER_STOPCLK_BEGIN = 0x00070007,
+
+ SIM_MT6306_ACTION_RESET = 0x00080001,
+ SIM_MT6306_ACTION_COMMAND = 0x00080002,
+ SIM_MT6306_ACTION_POWOFF = 0x00080003,
+ SIM_MT6306_ACTION_EOC = 0x00080004,
+
+ SIM_MT6306_TEST_1 = 0x00090001,
+ SIM_MT6306_TEST_2 = 0x00090002,
+ SIM_MT6306_TEST_3 = 0x00090003,
+ SIM_MT6306_TEST_4 = 0x00090004,
+ SIM_MT6306_TEST_5 = 0x00090005,
+ SIM_MT6306_TEST_6 = 0x00090006,
+ SIM_MT6306_TEST_7 = 0x00090007,
+ SIM_MT6306_TEST_0 = 0x00090008,
+ SIM_MT6306_TEST2_1 = 0x00090021,
+ SIM_MT6306_TEST2_2 = 0x00090022,
+ SIM_MT6306_TEST2_3 = 0x00090023,
+ SIM_MT6306_TEST2_4 = 0x00090024,
+ SIM_MT6306_TEST2_5 = 0x00090025,
+ SIM_MT6306_TEST2_6 = 0x00090026,
+ SIM_MT6306_TEST2_7 = 0x00090027,
+ SIM_MT6306_TEST2_0 = 0x00090028,
+
+ SIM_MT6306_CLKSTOP_TIMEOUT = 0x000a0001,
+ SIM_MT6306_CLKSTOP_START = 0x000a0002,
+ SIM_MT6306_CLKSTOP_ABORT = 0x000a0003,
+ SIM_MT6306_CLKSTOP_DEQUE = 0x000a0004,
+ SIM_MT6306_CLKSTOP_STOP = 0x000a0005,
+
+ SIM_MT6306_CLKSTART_START = 0x000b0001,
+ SIM_MT6306_CLKSTART_END = 0x000b0002,
+ SIM_MT6306_CLKSTART_HISR = 0x000b0003,
+ SIM_MT6306_CLKSTART_NEW_TRUE = 0x000b0004,
+ SIM_MT6306_CLKSTART_NEW_FALSE = 0x000b0005,
+ SIM_MT6306_CLKSTART_HISR2 = 0x000b0006,
+
+ SIM_MT6306_SPI_WRITE = 0x000c0001,
+ SIM_MT6306_SPI_WRITE_DBG = 0x000c0002
+} sim_MT6306_msgTag;
+
+#if defined(__DRV_2_SIM_USING_MT6306__)
+
+#define MT6306_CLK_CFG_BLOCKED(simInterface) ((sim_MT6306_card[simInterface].pins.CLK & (0x5<<hw_cb->simSwitchPortNo)) != (0x1<<hw_cb->simSwitchPortNo))
+
+/*MT6306 's pin state is more complicated, if I don't describe it precisely, I may encounter struggle in the future*/
+typedef enum
+{
+ sim_MT6306_VCC18VDisable = 0,
+ sim_MT6306_VCC3VDisable = 1,
+ sim_MT6306_VCC18V = 4, // I plan to use ((reg_value >> simInterface) & 0x5) to assign the pin state value, thus the enum should be the same as reg value
+ sim_MT6306_VCC3V = 5
+} sim_MT6306_stateVCC;
+
+typedef enum
+{
+ sim_MT6306_DATBlockedHigh = 0,
+ sim_MT6306_DATPass_High = 1, //Data is now pass and controlled by the side that driving, but DATA_L is 0, that is, when we block it will become high
+ sim_MT6306_DATBlockedLow = 5,
+ sim_MT6306_DATBlockedHigh_Low = 4, //Data is now block high but DATA_L is 1, that is, when we set DATAEN, it will become block low
+
+ /*in following state, pin is stay in low lv because no ldo supply*/
+ sim_MT6306_NoLDO_DATBlockedHigh = 0x10,
+ sim_MT6306_NoLDO_DATPass_High = 0x11,
+ sim_MT6306_NoLDO_DATBlockedLow = 0x15,
+ sim_MT6306_NoLDO_DATBlockedHigh_Low = 0x14
+
+} sim_MT6306_stateDAT;
+
+typedef enum
+{
+ sim_MT6306_CLKBlockedLow = 0,
+ sim_MT6306_CLKPass = 1,
+ sim_MT6306_CLKBlockedHigh = 5,
+ sim_MT6306_CLKInvalidState = 4,
+
+ /*in following state, pin is stay in low lv because no ldo supply*/
+ sim_MT6306_NoLDO_CLKBlockedLow = 0x10,
+ sim_MT6306_NoLDO_CLKPass = 0x11,
+ sim_MT6306_NoLDO_CLKBlockedHigh = 0x15,
+ sim_MT6306_NoLDO_CLKInvalidState = 0x14
+} sim_MT6306_stateCLK;
+
+typedef enum
+{
+ sim_MT6306_RSTPass_Low = 0, //RSTVAL is low, that is, when we block RST, it will becomes block low
+ sim_MT6306_RSTBlockedLow = 1,
+ sim_MT6306_RSTBlockedHigh = 5,
+ sim_MT6306_RSTPass_High = 4,//RSTVAL is high, that is, when we block RST, it will becomes block high
+
+ /*in following state, pin is stay in low lv because no ldo supply*/
+ sim_MT6306_NoLDO_RSTPass_Low = 0x10,
+ sim_MT6306_NoLDO_RSTBlockedLow = 0x11,
+ sim_MT6306_NoLDO_RSTBlockedHigh = 0x15,
+ sim_MT6306_NoLDO_RSTPass_High = 0x14
+} sim_MT6306_stateRST;
+
+#elif defined (DRV_2_SIM_USING_LTC4558)
+
+typedef enum
+{
+ sim_MT6306_VCCDisable = 0,
+ sim_MT6306_VCC18V = 1,
+ sim_MT6306_VCC3V = 2,
+ sim_MT6306_VCCMaxValue
+} sim_MT6306_stateVCC;
+
+typedef enum
+{
+ sim_MT6306_DATBlockedHigh = 0,
+ sim_MT6306_DATPass = 1,
+ sim_MT6306_DATBlockedLow = 2,
+ sim_MT6306_DATMaxValue
+} sim_MT6306_stateDAT;
+
+typedef enum
+{
+ sim_MT6306_CLKBlockedLow = 0,
+ sim_MT6306_CLKPass = 1,
+ sim_MT6306_CLKBlockedHigh = 2,
+ sim_MT6306_CLKMaxValue
+} sim_MT6306_stateCLK;
+
+typedef enum
+{
+ sim_MT6306_RSTBlockedLow = 0,
+ sim_MT6306_RSTPass = 1,
+ sim_MT6306_RSTBlockedHigh = 2,
+ sim_MT6306_RSTMaxValue
+} sim_MT6306_stateRST;
+
+#endif
+
+typedef enum
+{
+ sim_MT6306_statusNoError = 0
+} sim_MT6306_status;
+
+typedef enum
+{
+ sim_MT6306_eventReset = 0,
+ sim_MT6306_eventCommand,
+ sim_MT6306_eventPowerOff
+} sim_MT6306_changeEvent;
+
+typedef enum
+{
+ sim_MT6306_stateDeactiavate = 0,
+ sim_MT6306_stateClkRunning = 1,
+ sim_MT6306_stateClkStopped = 2
+} sim_MT6306_cardState;
+
+typedef enum
+{
+ sim_MT6306_cardTypeAL = 0,
+ sim_MT6306_cardTypeIR = 1,
+ sim_MT6306_cardTypeMaxValue
+} sim_MT6306_cardType;
+
+typedef enum
+{
+ sim_MT6306_LISRnotRegistered = 0,
+ sim_MT6306_LISRUsim = 1,
+ sim_MT6306_LISRSim
+} sim_MT6306_LISRState;
+
+enum
+{
+ sim_MT6306_protectionChange = 0,
+ sim_MT6306_protectionSpi,
+ sim_MT6306_protectionCmd,
+ sim_MT6306_protectionRst,
+ sim_MT6306_protectionPwf,
+ sim_MT6306_protectionPdn,
+ sim_MT6306_protectionState,
+ sim_MT6306_protectionStopper,
+ SIM_MT6306_MAX_PROTECTION_NUM
+};
+
+
+/*this is the prototype in MT6302 driver*/
+typedef void (*sim_MT6306_SPIWriter)(kal_uint32 chipNo, kal_uint16 data);
+
+/*this is the reader/writer prototype among different I2C solution*/
+typedef void (*sim_MT6306_I2CWriter_implementation)(kal_uint8 addr, kal_uint8 data_addr, kal_uint8 data_value);
+typedef kal_uint8(*sim_MT6306_I2CReader_implementation)(kal_uint8 device_addr, kal_uint8 data_addr);
+
+
+typedef struct
+{
+ sim_MT6306_msgTag tag;
+ kal_uint32 event;
+ kal_uint32 data1;
+ kal_uint32 data2;
+} sim_MT6306_msg;
+
+typedef struct
+{
+ sim_MT6306_stateCLK CLK;
+ sim_MT6306_stateDAT DAT;
+ sim_MT6306_stateRST RST;
+ sim_MT6306_stateVCC VCC;
+} sim_MT6306_pinStatus;
+
+typedef struct
+{
+ sim_MT6306_pinStatus pins;
+ sim_MT6306_cardState state;
+ sim_MT6306_cardType type;
+ sim_MT6306_LISRState lisrState;
+ kal_uint16 baud;
+ kal_uint16 config;
+ kal_uint32 sim_MT6306_gptHandle;
+ volatile kal_bool sim_MT6306_clkStopQueued;
+} sim_MT6306_cardInfo;
+
+typedef struct
+{
+ kal_uint32 MT6306ChipNo; //for which MT6306 chip does this control block stand
+ sim_MT6306_SPIWriter sim_MT6320_writer;
+ kal_uint32 sim_MT6306_servingInterface;// the latest interface that controller is serving
+ kal_semid sim_MT6306_arb;
+ volatile kal_bool sim_MT6306_taskAccessing;
+ kal_bool sim_MT6306_needCLKStartTimeout;
+ kal_uint8 sim_MT6306_regValue[SIM_MT6306_REG_NUMBER];
+ sim_MT6306_LISRState sim_MT6306_registeredLISR;
+ kal_bool sim_MT6306_needManualControl; /*this flag will only be set true in MT6306*/
+ volatile kal_uint8 MT6306_raceConditionProtect[SIM_MT6306_MAX_PROTECTION_NUM];
+ kal_bool sim_workingTaskWaiting; //this is used to know whether serving task is waiting for event
+ kal_bool sim_MT6306_initialized;
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+ sim_HW_cb *usim_waitHisrCb_MT6306; //record the hw_cb pointer to whom is using this switch's hisr
+ sim_HW_cb *sim_waitHisrCb_MT6306; //record the hw_cb pointer to whom is using this switch's hisr
+ kal_uint32 nullByteGPTServingInterface;
+ /*following is for LCD SPI*/
+ kal_uint32 MT6306_SPI_LCDSerialData;
+ kal_uint8 MT6306_LCD_pdnHandle; /*lcd_get_power_handle will return value less than 32, set this as RW 0xff*/
+#endif
+ kal_semid sim_MT6306_Check_arb;
+ volatile kal_bool sim_MT6306_CLKStopping;
+ kal_uint8 sim_MT6306_LPDisabled;
+ void* peerSwitch;
+} sim_MT6306_switchInfo;
+
+typedef struct
+{
+ kal_bool isHandleCmd;
+} sim_clockStopMap;
+
+typedef struct
+{
+ sim_HW_cb *hw_cb;
+ kal_bool queued;
+} sim_MT6306_clockStopQueueEvent;
+extern sim_clockStopMap clockStopMap[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+#ifndef __SIM_DRV_MULTI_DRV_ARCH__
+ typedef sim_MT6306_status(*sim_MT6306_eventHandler)(kal_uint32, sim_MT6306_changeEvent);
+#else
+ typedef sim_MT6306_status(*sim_MT6306_eventHandler)(sim_HW_cb *, sim_MT6306_changeEvent);
+ sim_MT6306_switchInfo *sim_MT6306_get_MT6306switchCB(sim_HW_cb *hw_cb);
+ sim_MT6306_cardInfo *sim_MT6306_get_MT6306CardCB(sim_HW_cb *hw_cb);
+#endif
+
+
+extern sim_status L1sim_Cmd_Layer_MT6306(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb, kal_bool *isSW6263);
+extern kal_uint32 MT6306_getGPIOCLK(void);
+extern kal_uint32 MT6306_getGPIODAT(void);
+extern void MT6306_Writer_AL(kal_uint8 chipno, kal_uint16 data);
+extern void MT6306_i2cInit(sim_MT6306_SPIWriter *spiWritePtr, kal_uint32 chipNo);
+extern void sim_PDNDisable_MT6302(sim_HW_cb *hw_cb);
+extern void sim_PDNEnable_MT6302(sim_HW_cb *hw_cb);
+extern void MT6306_HW_I2C_init(kal_uint8 deviceAddress);
+extern void SIM_WaitEvent_MT6306(Sim_Card *SIMCARD, kal_uint32 flag, kal_bool unmaskSIMIntr, sim_HW_cb *hw_cb);
+extern void sim_MT6306_manualReset(sim_HW_cb *hw_cb);
+extern void SIM_SetEvent_MT6306(Sim_Card *SIMCARD, kal_uint8 result, sim_HW_cb *hw_cb);
+extern void MT6306_Get_GPIO_Mode(kal_uint8* mode);
+#endif //__SIM_MT6306_H__
diff --git a/mcu/driver/devdrv/usim/mt6306/mt6256/mt63062.lib b/mcu/driver/devdrv/usim/mt6306/mt6256/mt63062.lib
new file mode 100755
index 0000000..5d977c3
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/mt6256/mt63062.lib
Binary files differ
diff --git a/mcu/driver/devdrv/usim/mt6306/src/MT6306_HW_I2C.c b/mcu/driver/devdrv/usim/mt6306/src/MT6306_HW_I2C.c
new file mode 100644
index 0000000..2d6f319
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/src/MT6306_HW_I2C.c
@@ -0,0 +1,245 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MT6306_HW_I2C.C
+ *
+ * Project:
+ * --------
+ * Gemini
+ *
+ * Description:
+ * ------------
+ * this file implement MT6306 writer on HW I2C
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************///******************************************************************//
+// //
+// Implement through hardware I2C //
+//******************************************************************//
+#include "drv_comm.h"
+//#include "MT6306_i2c.h"
+//#include "MT63062.h"
+//#include "sim_trc.h"
+//#include "sim_sw_comm.h"
+//#include "sim_mt6306.h"
+#include "dcl.h"
+#include "kal_public_api.h"
+#include "dcl_i2c.h"
+#include "sim_drv_trc.h"
+#include "sim_sw_comm.h"
+kal_char SIM_HW_I2C_DBG_STR[512];
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+
+DCL_HANDLE MT6306I2CHandle;
+
+void MT6306_HW_I2C_writer(kal_uint8 addr, kal_uint8 data_addr, kal_uint8 data_value)
+{
+ DCL_STATUS status;
+ kal_uint8 WriteBuff[2];
+ DCL_CTRL_DATA_T I2cData;
+
+ I2cData.rSingleWrite.u4DataLen = 2;
+
+ WriteBuff[0] = data_addr;
+ WriteBuff[1] = data_value;
+ I2cData.rSingleWrite.pu1Data = WriteBuff;
+
+
+
+ status = DclSI2C_Control(MT6306I2CHandle, I2C_CMD_SINGLE_WRITE, (DCL_CTRL_DATA_T *)&I2cData);
+ if (STATUS_OK != status)
+ {
+ sim_addMsg(0x12070601, status, 0, 0);
+#ifdef ATEST_DRV_ENABLE
+ dbg_print("[SIM_DRV:%d][ERR]%s\n\r", 0, __FUNCTION__);
+#else
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(SIM_HW_I2C_DBG_STR, "[%s]Addr:%x,data_addr:%x,data_value:%x",__FUNCTION__,addr,data_addr,data_value);
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ERR,0,SIM_HW_I2C_DBG_STR);
+#endif
+ //SIM_DEBUG_ASSERT(0);
+ }
+}
+
+
+kal_uint8 MT6306_HW_I2C_reader(kal_uint8 device_addr, kal_uint8 data_addr)
+{
+ DCL_STATUS status;
+ kal_uint8 ReadBuff[1] = {0};
+ kal_uint8 WriteBuff[1];
+ DCL_CTRL_DATA_T I2cData;
+
+
+ WriteBuff[0] = data_addr;
+ I2cData.rWriteAndRead.pu1OutData = WriteBuff;
+ I2cData.rWriteAndRead.u4OutDataLen = 1;
+ I2cData.rWriteAndRead.pu1InData = ReadBuff;
+ I2cData.rWriteAndRead.u4InDataLen = 1;
+
+ status = DclSI2C_Control(MT6306I2CHandle, I2C_CMD_WRITE_AND_READ, (DCL_CTRL_DATA_T *) &I2cData);
+ if (STATUS_OK != status)
+ {
+ sim_addMsg(0x12070602, status, 0, 0);
+#ifdef ATEST_DRV_ENABLE
+ dbg_print("[SIM_DRV:%d][ERR]%s\n\r", 0, __FUNCTION__);
+#else
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(SIM_HW_I2C_DBG_STR, "[%s]Addr:%x,data_addr:%x",__FUNCTION__,device_addr,data_addr);
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ERR,0,SIM_HW_I2C_DBG_STR);
+#endif
+ //SIM_DEBUG_ASSERT(0);
+ }
+
+ return (ReadBuff[0]);
+}
+
+void MT6306_HW_I2C_init(kal_uint8 deviceAddress)
+{
+ I2C_CONFIG_T HWI2CPara;
+
+ /*not allow to call this after system init*/
+ if (KAL_FALSE == kal_query_systemInit())
+ SIM_DEBUG_ASSERT(0);
+
+ if (127 < deviceAddress)
+ SIM_DEBUG_ASSERT(0);
+
+ if (0 == MT6306I2CHandle)
+ {
+
+ DclSI2C_Initialize();
+ MT6306I2CHandle = DclSI2C_Open(DCL_I2C, DCL_I2C_OWNER_MT6306);
+
+ HWI2CPara.eOwner = DCL_I2C_OWNER_MT6306;
+ HWI2CPara.fgGetHandleWait = KAL_TRUE;
+ HWI2CPara.u1SlaveAddress = (deviceAddress * 2);
+ HWI2CPara.u1DelayLen = 0;
+ HWI2CPara.eTransactionMode = DCL_I2C_TRANSACTION_FAST_MODE;
+ HWI2CPara.u4FastModeSpeed = HWI2CPara.u4HSModeSpeed = 400;
+ HWI2CPara.fgEnableDMA = KAL_FALSE;
+ DclSI2C_Configure(MT6306I2CHandle, (DCL_CONFIGURE_T *)&HWI2CPara);
+ }
+}
+
diff --git a/mcu/driver/devdrv/usim/mt6306/src/MT6306_I2C.c b/mcu/driver/devdrv/usim/mt6306/src/MT6306_I2C.c
new file mode 100644
index 0000000..898535e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/src/MT6306_I2C.c
@@ -0,0 +1,1804 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MT6302_interface.C
+ *
+ * Project:
+ * --------
+ * Gemini
+ *
+ * Description:
+ * ------------
+ * this file is to be adaption layer for different SPI implementation
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "drv_comm.h"
+#include "reg_base.h"
+//#include "gpio_sw.h"
+#include "sim_reg_adp.h"
+#include "mt6306_i2c.h"
+//#include "mt63062.h"
+#include "sim_sw_comm.h"
+#include "sim_mt6306.h"
+#include "dcl.h"
+#include "dcl_sim_gpio.h"
+#include "drv_features.h"
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+kal_uint32 MT6306_initDelayTime;
+kal_uint32 gpio_write_cnt=0;
+kal_uint32 get_current_time_cnt = 0;
+extern kal_bool spiWriterFlag;
+extern kal_uint32 MT6306_getGPIODAT(void);
+extern kal_uint32 MT6306_getGPIOCLK(void);
+extern kal_char sim_dbg_str[];
+
+/*MT6306_I2C.c and MT6306_HW_I2C.c are too couple, I don't want to use header file to define the prototype*/
+extern void MT6306_HW_I2C_writer(kal_uint8 addr, kal_uint8 data_addr, kal_uint8 data_value);
+extern kal_uint8 MT6306_HW_I2C_reader(kal_uint8 device_addr, kal_uint8 data_addr);
+
+//extern void sim_MT63062_CacheRegVal(kal_uint32 chipNo, kal_uint8 addr, kal_uint8 value);
+extern kal_uint32 MT6306_geti2cInterface(kal_uint32 MT6306Interface);
+extern sim_HW_cb *retreiveQueuedCb(kal_uint32 i);
+extern kal_uint8 MT6306_getDeviceAddr(void);
+extern kal_uint32 MT6306_getVIOLevel();
+extern void sim_MT63062_TakeI2Csem(void);
+extern void sim_MT63062_GiveI2Csem(void) ;
+extern void sim_MT6306_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+#define MT6306_SIM_GPIO_VCC_DELAY 500
+#define MT6306_SIM_GPIO_PIN_GROUP_REG 0x1A
+
+extern kal_bool spiWriterGptTimeoutFlag;
+typedef struct
+{
+ kal_uint16 drive_high;
+ kal_uint32 drive_low;
+ kal_uint16 dir;
+ kal_uint16 gpi_val;
+ kal_uint8 pin_group;
+ kal_uint16 vcc;
+ kal_uint16 voltH;
+ kal_uint16 voltL;
+} mt6306_simgpio_reg_table;
+mt6306_simgpio_reg_table regTable[] =
+{
+ {0x015, 0x010, 0x012, 0x0A0, 0x0, 0x032, 0x030, 0x022},
+ {0x005, 0x000, 0x002, 0x0B0, 0x0, 0x032, 0x030, 0x022},
+ {0x021, 0x020, 0x080, 0x0C0, 0x0, 0x032, 0x030, 0x022},
+
+ {0x01A, 0x011, 0x013, 0x0A1, 0x1, 0x033, 0x031, 0x023},
+ {0x00A, 0x001, 0x003, 0x0B1, 0x1, 0x033, 0x031, 0x023},
+ {0x022, 0x021, 0x081, 0x0C1, 0x1, 0x033, 0x031, 0x023},
+
+ {0x055, 0x050, 0x052, 0x0A2, 0x2, 0x072, 0x070, 0x062},
+ {0x045, 0x040, 0x042, 0x0B2, 0x2, 0x072, 0x070, 0x062},
+ {0x061, 0x060, 0x082, 0x0C2, 0x2, 0x072, 0x070, 0x062},
+
+ {0x05A, 0x051, 0x053, 0x0A3, 0x3, 0x073, 0x071, 0x063},
+ {0x04A, 0x041, 0x043, 0x0B3, 0x3, 0x073, 0x071, 0x063},
+ {0x062, 0x061, 0x083, 0x0C3, 0x3, 0x073, 0x071, 0x063},
+
+ {0x0, 0x0, 0x0, 0x0D2, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 0x0, 0x0, 0x0D3, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 0x0, 0x0, 0x0D0, 0x0, 0x0, 0x0, 0x0},
+
+ {0x0, 0x0, 0x0, 0x0D1, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 0x0, 0x0, 0x0E0, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 0x0, 0x0, 0x0E1, 0x0, 0x0, 0x0, 0x0},
+};
+
+sim_MT6306_I2CWriter_implementation I2CWriterPtr;
+sim_MT6306_I2CReader_implementation I2CReaderPtr;
+DCL_HANDLE clkHandle, datHandle;
+kal_uint32 GPIO_Orig_Mode[2]={1,1};
+//******************************************************************//
+// //
+// adaptation layer //
+//******************************************************************//
+
+/*This is an adaptation layer of all kinds of MT6306 writer, all of MT6306 related driver should call this writer.*/
+void MT6306_Writer_AL(kal_uint8 chipno, kal_uint16 data)
+{
+ kal_uint16 tmpaddr = 0;
+ kal_uint8 addr, value;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+ DRV_GET_RET_ADDR(retAddr);
+ sim_addMsg(0x11042001, chipno, data, (kal_uint32)retAddr);
+
+ /*
+ data is a 12 bit value, use uint16 to store its value, its format is :
+ | 11:8 | 7:4 | 3:0 |
+ addr_high addr_low data
+
+ and we want to send data to MT6306 as following format:
+ |S |7:1 |W |A |11:8 |7:4 |A |all zero,7:4|3:0 |A |S
+ start device addr R/W ack addr_high addr_low ack stuff 0 data ack stop
+ */
+
+ /*handling address swap*/
+
+ /*handling address swap*/
+ tmpaddr = (data & 0xFF0);
+ addr = (kal_uint8)(tmpaddr >> 4); //MT6306 I2C Spec.
+ value = (kal_uint8)(data & 0x0F);
+
+ if (addr <= 3)
+ {
+ if (chipno == 1)
+ {
+ addr = addr + 4;
+ }
+ }
+
+ I2CWriterPtr(MT6306_getDeviceAddr(), addr, value);// MT6306_Writer_GPIO
+}
+
+/*This is an adaptation layer of all kinds of MT6306 writer, all of MT6306 related driver should call this writer.*/
+kal_uint8 MT6306_Reader_AL(kal_uint8 chipno, kal_uint16 addr)
+{
+ kal_uint8 readValue;
+ if (addr <= 3)
+ {
+ if (chipno == 1)
+ {
+ addr = addr + 4;
+ }
+ }
+
+ readValue = I2CReaderPtr(chipno, addr);
+ return readValue;
+}
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+kal_uint32 MD_AP_DUMMY_I2C_REG = MD_AP_SCL | MD_AP_SDA | MD_AP_SDA_OE;
+#endif
+kal_uint32 AP_MD_DUMMY_I2C_REG = 0;
+
+//******************************************************************//
+// //
+// Implement software I2C //
+//******************************************************************//
+void MT6306_GPIO_init(kal_uint8 deviceAddress)
+{
+ /* in order to confirm GPIO had been configre correctly.
+ we set mode and direction at each Writer_GPIO/Read_GPIO
+ operation. It will avoid share pin issue */
+ GPIO_CTRL_RETURN_MODE_T mode;
+
+
+ datHandle = DclGPIO_Open(DCL_GPIO, MT6306_getGPIODAT());
+ clkHandle = DclGPIO_Open(DCL_GPIO, MT6306_getGPIOCLK());
+
+ DclGPIO_Control(clkHandle, GPIO_CMD_RETURN_MODE, (DCL_CTRL_DATA_T *) &mode);
+ GPIO_Orig_Mode[0] = mode.u1RetMode & 0x07;
+
+ DclGPIO_Control(datHandle, GPIO_CMD_RETURN_MODE, (DCL_CTRL_DATA_T *) &mode);
+ GPIO_Orig_Mode[1] = mode.u1RetMode & 0x07;
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ MD_AP_DUMMY_I2C_REG |= MD_AP_SCL | MD_AP_SDA | MD_AP_SDA_OE;
+ DRV_WriteReg32(MD_AP_DUMMY_I2C, MD_AP_DUMMY_I2C_REG);
+#if defined(MT6763)
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_MODE_2, 0);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_MODE_2, 0);
+#elif defined(MT6739)
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_MODE_5, 0);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_MODE_5, 0);
+#endif
+#elif defined(MT3967) || defined(MT6779)
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_MODE_4, 0);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_MODE_4, 0);
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853)
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_MODE_3, 0);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_MODE_3, 0);
+#else
+
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_MODE_0, 0);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_MODE_0, 0);
+
+ DclGPIO_Control(datHandle, GPIO_CMD_ENABLE_PULL, NULL);
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_PULL_HIGH, NULL);
+ DclGPIO_Control(datHandle, GPIO_CMD_WRITE_HIGH, NULL);
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_DIR_OUT, NULL);
+ DclGPIO_Control(clkHandle, GPIO_CMD_ENABLE_PULL, NULL);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_PULL_HIGH, NULL);
+ DclGPIO_Control(clkHandle, GPIO_CMD_WRITE_HIGH, NULL);
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_DIR_OUT, NULL);
+
+#endif
+
+// kal_sprintf(sim_dbg_str,"MT6306_Writer_GPIO(%x, %x)",clkHandle, datHandle);
+// kal_print(sim_dbg_str);
+}
+void MT6306_Get_GPIO_Mode(kal_uint8* gpio_mode)
+{
+ GPIO_CTRL_RETURN_MODE_T mode;
+ GPIO_CTRL_RETURN_DIR_T dir;
+ clkHandle = DclGPIO_Open(DCL_GPIO, MT6306_getGPIOCLK());
+ datHandle = DclGPIO_Open(DCL_GPIO, MT6306_getGPIODAT());
+
+ DclGPIO_Control(clkHandle, GPIO_CMD_RETURN_MODE, (DCL_CTRL_DATA_T *)&mode);
+ *(gpio_mode)=mode.u1RetMode&0x07;
+ DclGPIO_Control(datHandle, GPIO_CMD_RETURN_MODE, (DCL_CTRL_DATA_T *)&mode);
+ *(gpio_mode+1)=mode.u1RetMode&0x07;
+
+ DclGPIO_Control(clkHandle, GPIO_CMD_RETURN_DIR, (DCL_CTRL_DATA_T *)&dir);
+ *(gpio_mode+2)=dir.u1RetDirData&0x07;
+ DclGPIO_Control(datHandle, GPIO_CMD_RETURN_DIR, (DCL_CTRL_DATA_T *)&dir);
+ *(gpio_mode+3)=dir.u1RetDirData&0x07;
+
+}
+void MT6306_Restore_GPIO_Mode(void)
+{
+ clkHandle = DclGPIO_Open(DCL_GPIO, MT6306_getGPIOCLK());
+ datHandle = DclGPIO_Open(DCL_GPIO, MT6306_getGPIODAT());
+
+ DclGPIO_Control(clkHandle, GPIO_CMD_SET_MODE_0+GPIO_Orig_Mode[0],0);
+ DclGPIO_Control(datHandle, GPIO_CMD_SET_MODE_0+GPIO_Orig_Mode[1],0);
+
+}
+void Delay(kal_uint16 index)
+{
+ kal_uint16 counter;
+ for (counter = 0; counter <= index; counter++)
+ {
+ counter = counter;
+ }
+}
+#if defined(DRV_SIM_6292_SERIES)
+#define I2C_DELAY_US_PER_GPIO 2
+#else
+#define I2C_DELAY_US_PER_GPIO 0
+#endif
+static kal_uint32 prev_level=0xFFFFFFFF;
+void Delay_for_each_gpio_write(kal_uint8 delay_count)
+{
+
+ kal_uint32 t1 = ust_get_current_time_source(); //Keep
+ kal_uint32 t2 = t1;
+ volatile kal_uint32 counter = 0;
+
+ if(delay_count == 0) return;
+
+ do
+ {
+ counter = 0;
+ while (counter++ < 90)__asm__(""); // in ELBRUS EVB, 1us = 90 asm instructions (28 busy loops)
+ t2 = ust_get_current_time_source();
+ get_current_time_cnt++;
+ }
+ while (ust_us_duration(t1, t2) < delay_count);
+ get_current_time_cnt++;
+
+ return;
+}
+
+
+
+void GPIO_WRITE_IF_CHANGED(kal_uint32 handle, kal_uint32 level)
+{
+ if (handle == datHandle)
+ {
+ if (prev_level != level)
+ {
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ if (level == GPIO_CMD_WRITE_LOW)
+ MD_AP_DUMMY_I2C_REG &= ~MD_AP_SDA;
+ else
+ MD_AP_DUMMY_I2C_REG |= MD_AP_SDA;
+ DRV_WriteReg32(MD_AP_DUMMY_I2C, MD_AP_DUMMY_I2C_REG);
+#else
+ DclGPIO_Control(handle, level, NULL);
+#endif
+ Delay_for_each_gpio_write(I2C_DELAY_US_PER_GPIO);
+ gpio_write_cnt++;
+ }
+
+ prev_level = level;
+ }
+ else
+ {
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ if (level == GPIO_CMD_WRITE_LOW)
+ MD_AP_DUMMY_I2C_REG &= ~MD_AP_SCL;
+ else
+ MD_AP_DUMMY_I2C_REG |= MD_AP_SCL;
+ DRV_WriteReg32(MD_AP_DUMMY_I2C, MD_AP_DUMMY_I2C_REG);
+#else
+ DclGPIO_Control(handle, level, NULL);
+#endif
+ Delay_for_each_gpio_write(I2C_DELAY_US_PER_GPIO);
+ gpio_write_cnt++;
+ }
+}
+
+/*
+* MT6306_Writer_GPIO
+*
+* DESCRIPTION
+* The function is used to write MT6306 register by GPIO
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+
+void MT6306_Writer_GPIO(kal_uint8 device_addr, kal_uint8 data_addr, kal_uint8 data_value)
+{
+ kal_uint32 j = 3;
+ /* not to open datHandle and clkHandle at here because it cause (414)DRVHISR
+ assertion */
+ //i = SaveAndSetIRQMask();
+ //I2C start
+ /*send start bit*/
+
+//dbg_print("\r\n[%s]Addr:%x,value:%x\r\n ", __func__,data_addr,data_value);
+ //extern kal_char sim_shared_dbgstr[];
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ MD_AP_DUMMY_I2C_REG = DRV_Reg32(MD_AP_DUMMY_I2C);
+ AP_MD_DUMMY_I2C_REG = DRV_Reg32(AP_MD_DUMMY_I2C);
+#endif
+ kal_uint32 t_debug = ust_get_current_time(),t_debug2,duration;
+ prev_level=0xFFFFFFFF; //Fisrt bit always write
+ gpio_write_cnt=0;
+ get_current_time_cnt = 0;
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+
+ //SlaveAddr 0x64 = 1100100'b
+ /*send dat 1*/
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ /*send dat 1*/
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ /*send dat 0*/
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ //R/W
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ //ACK, in I2C protocol, the sender should wait for ACK here, but not send the ACK bit
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ /*send data*/
+ //Address
+ if (data_addr & 0x80)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit7
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+ if (data_addr & 0x40)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit6
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_addr & 0x20)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit5
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_addr & 0x10)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit4
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_addr & 0x08)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit3
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_addr & 0x04)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit2
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_addr & 0x02)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit1
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_addr & 0x01)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit0
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ //ACK
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ //data
+ if (data_value & 0x80)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit7
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x40)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit6
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x20)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit5
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x10)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit4
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x08)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit3
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x04)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit2
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x02)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit1
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ if (data_value & 0x01)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ //bit0
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+
+ //ACK
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ //STOP
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+
+ MO_Sync();
+ t_debug2=ust_get_current_time();
+ duration=ust_us_duration(t_debug, t_debug2);
+ //kal_sprintf(sim_shared_dbgstr, "[%s] %d us, %d, %d, %d\n\r", __FUNCTION__, duration, gpio_write_cnt, (duration*1000)/gpio_write_cnt, get_current_time_cnt);
+ //dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, sim_shared_dbgstr);
+ sim_MT6306_addMsg(SIM_MT6306_SPI_WRITE_DBG, duration, gpio_write_cnt, get_current_time_cnt);
+
+// DclGPIO_Close(datHandle);
+// DclGPIO_Close(clkHandle);
+ //RestoreIRQMask(i);
+}
+
+
+/*
+* FUNCTION
+* MT6306_Read_GPIO
+*
+* DESCRIPTION
+* The function is used to read MT6306 register by GPIO
+*
+* CALLS
+* readValue = MT6306_Reader_AL(0,0x10); read register 0x10h
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+
+void MT6306_Set_Dir(kal_uint32 dir)
+{
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ if (dir == GPIO_CMD_SET_DIR_IN)
+ MD_AP_DUMMY_I2C_REG &= ~MD_AP_SDA_OE; //Disable output mode
+ else
+ MD_AP_DUMMY_I2C_REG |= MD_AP_SDA_OE;
+
+ DRV_WriteReg32(MD_AP_DUMMY_I2C, MD_AP_DUMMY_I2C_REG);
+#else
+
+ DclGPIO_Control(datHandle, dir, 0);
+
+#endif
+
+}
+kal_uint8 MT6306_Read_GPIO(kal_uint8 device_addr, kal_uint8 data_addr)
+{
+ kal_uint32 j = 3;
+ kal_uint8 value = 0, bTmp = 0;
+#if !defined(SIM_DRV_USE_MDGPIO_I2C)
+ DCL_CTRL_DATA_T i2cDat;
+ GPIO_CTRL_READ_T *prRead;
+#endif
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ MD_AP_DUMMY_I2C_REG = DRV_Reg32(MD_AP_DUMMY_I2C);
+ AP_MD_DUMMY_I2C_REG = DRV_Reg32(AP_MD_DUMMY_I2C);
+#endif
+
+ /* not to open datHandle and clkHandle at here because it cause (414)DRVHISR
+ assertion */
+ value = value;
+ //i = SaveAndSetIRQMask();
+
+ //I2C start
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //SlaveAddr 0x64
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //R/W
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //ACK
+ MT6306_Set_Dir(GPIO_CMD_SET_DIR_IN);
+
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+
+ MT6306_Set_Dir(GPIO_CMD_SET_DIR_OUT);
+
+ Delay(j);
+
+ //Address
+ if (data_addr & 0x80)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x40)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x20)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x10)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x08)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x04)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x02)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ }
+
+ if (data_addr & 0x01)
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+ else
+ {
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ }
+
+ //ACK
+ MT6306_Set_Dir(GPIO_CMD_SET_DIR_IN);
+
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+
+ MT6306_Set_Dir(GPIO_CMD_SET_DIR_OUT);
+
+ Delay(j);
+
+ //I2C start
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //SlaveAddr 0x64
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //R/W
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //ACK
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+
+ MT6306_Set_Dir(GPIO_CMD_SET_DIR_IN);
+ MO_Sync();
+ //Read word data
+ for (bTmp = 0; bTmp < 8; bTmp++)
+ {
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ MD_AP_DUMMY_I2C_REG |= MD_AP_SCL;
+ DRV_WriteReg32(MD_AP_DUMMY_I2C, MD_AP_DUMMY_I2C_REG);
+#else
+ DclGPIO_Control(clkHandle, GPIO_CMD_WRITE_HIGH, NULL);
+ /* reset SDA data */
+ i2cDat.rRead.u1IOData = 0;
+#endif
+
+ Delay_for_each_gpio_write(I2C_DELAY_US_PER_GPIO);
+
+ MO_Sync();
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ AP_MD_DUMMY_I2C_REG = DRV_Reg32(AP_MD_DUMMY_I2C);
+ AP_MD_DUMMY_I2C_REG = (AP_MD_DUMMY_I2C_REG >> 13) & 0x01;
+ value |= (AP_MD_DUMMY_I2C_REG << (7 - bTmp));
+#else
+ DclGPIO_Control(datHandle, GPIO_CMD_READ, &i2cDat);
+
+
+ Delay(j);
+ prRead = &(i2cDat.rRead);
+
+ if (prRead->u1IOData)
+ {
+ value |= (1 << (7 - bTmp));
+ }
+ else
+ {
+ value |= (0 << (7 - bTmp));
+ }
+#endif
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ MD_AP_DUMMY_I2C_REG &= ~MD_AP_SCL;
+ DRV_WriteReg32(MD_AP_DUMMY_I2C, MD_AP_DUMMY_I2C_REG);
+#else
+ DclGPIO_Control(clkHandle, GPIO_CMD_WRITE_LOW, NULL);
+#endif
+
+ Delay_for_each_gpio_write(I2C_DELAY_US_PER_GPIO);
+ }
+
+
+ prev_level=0xFFFFFFFF;
+ //noACK
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+
+ MT6306_Set_Dir(GPIO_CMD_SET_DIR_OUT);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+
+ //STOP
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_LOW);
+ Delay(j);
+ GPIO_WRITE_IF_CHANGED(clkHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+#if !defined(SIM_DRV_USE_MDGPIO_I2C)
+ i2cDat.rWriteSpi.data = 1;
+#endif
+ GPIO_WRITE_IF_CHANGED(datHandle, GPIO_CMD_WRITE_HIGH);
+ Delay(j);
+
+ MO_Sync();
+ //RestoreIRQMask(i);
+
+ return (value);
+}
+
+void MT6306_i2cInit(sim_MT6306_SPIWriter *spiWritePtr, kal_uint32 chipNo)
+{
+ kal_uint32 i, j;
+ kal_uint8 readValue = 0;
+ j = drv_get_current_time();
+ for (i = 3000; i > 0; i--);
+ readValue = readValue;
+
+ MT6306_initDelayTime = drv_get_duration_tick(j, drv_get_current_time());
+
+ /*no matter which I2C solution we used, the writer pointer of MT6302 driver should point to writer adaptation*/
+ *spiWritePtr = (sim_MT6306_SPIWriter)MT6306_Writer_AL;
+
+ if (MT6306_I2C_USE_DEDICATED_GPIO == MT6306_geti2cInterface(chipNo)) //MT6306_I2C_USE_DEDICATED_GPIO
+ {
+ MT6306_GPIO_init(MT6306_getDeviceAddr());
+ I2CWriterPtr = MT6306_Writer_GPIO;
+ I2CReaderPtr = MT6306_Read_GPIO;
+ }
+ else if (MT6306_I2C_USE_HW_I2C == MT6306_geti2cInterface(chipNo))
+ {
+ MT6306_HW_I2C_init(MT6306_getDeviceAddr());
+ I2CWriterPtr = MT6306_HW_I2C_writer;
+ I2CReaderPtr = MT6306_HW_I2C_reader;
+ }
+
+ if (MT6306_VIO_1V8 == MT6306_getVIOLevel())
+ {
+ MT6306_Writer_AL(0, 0x108); // set VIOLVL = 1.8V
+ //readValue = MT6306_Reader_AL(0,0x10);
+ }
+}
+
+/*************************************************************************
+* FUNCTION
+* MT6306_GPIO_checkClkStopQueue
+*
+* DESCRIPTION
+* This function implements check clock stop queue when SIMGPIO access done.
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void MT6306_GPIO_checkClkStopQueue(void)
+{
+ /*borrow the task context to stop the queued Clk stop event*/
+ int i;
+ sim_HW_cb *queuedCb;
+
+ for (i = 0; 4 > i; i++)
+ {
+ queuedCb = retreiveQueuedCb(i);
+ if (queuedCb != NULL)
+ {
+ sim_MT6306_clkStopper(queuedCb);
+ }
+ }
+ spiWriterGptTimeoutFlag = KAL_FALSE;
+}
+
+/*************************************************************************
+* FUNCTION
+* MT6306_GPIO_InitIO
+*
+* DESCRIPTION
+* This function implements SIMGPIO direction output/input mode.
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void MT6306_GPIO_InitIO(kal_uint16 dir, kal_uint16 port)
+{
+ kal_uint8 Reg = 0, chipno = 1, addr = 0, offset = 0;
+ kal_uint16 tmpaddr = 0, dir_val = 0;
+
+ dir_val = regTable[port].dir;
+ tmpaddr = (dir_val & 0xFF0);
+ addr = (kal_uint8)(tmpaddr >> 4); //MT6306 I2C Spec.
+ offset = dir & 0xF;
+ if (addr <= 3)
+ {
+ chipno = 0;
+ }
+
+ sim_MT63062_TakeI2Csem();
+ /* used to check if any context access Writer interface */
+ if (spiWriterFlag == KAL_TRUE)
+ SIM_DEBUG_ASSERT(0);
+ spiWriterFlag = KAL_TRUE;
+
+ if (dir == KAL_TRUE)
+ {
+ Reg = MT6306_Reader_AL(chipno, addr);
+ Reg |= 1 << offset;
+
+ MT6306_Writer_AL(chipno, ((addr << 4) | Reg));
+ }
+ else
+ {
+ Reg = MT6306_Reader_AL(chipno, addr);
+ Reg &= ~(1 << offset);
+
+ MT6306_Writer_AL(chipno, ((addr << 4) | Reg));
+ }
+ if (spiWriterGptTimeoutFlag == KAL_TRUE)
+ {
+ MT6306_GPIO_checkClkStopQueue();
+ }
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+
+}
+
+/*************************************************************************
+* FUNCTION
+* MT6306_GPIO_SelPinGroup
+*
+* DESCRIPTION
+* This function implements SIMGPIO ping group selection(only GPIO1~12).
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void MT6306_GPIO_SelPinGroup(kal_uint8 pg)
+{
+ kal_uint8 Reg = 0;
+ Reg = MT6306_Reader_AL(1, MT6306_SIM_GPIO_PIN_GROUP_REG);
+ Reg |= 1 << pg;
+ MT6306_Writer_AL(1, ((MT6306_SIM_GPIO_PIN_GROUP_REG << 4) | Reg)); //chipno don't care
+}
+
+/*************************************************************************
+* FUNCTION
+* MT6306_GPIO_TurnOnVcc
+*
+* DESCRIPTION
+* This function implements SIMGPIO turn on/off VCC(VCC1~4).
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void MT6306_GPIO_TurnOnVcc(kal_bool on, kal_uint8 volt, kal_uint8 port)
+{
+ kal_uint8 Reg = 0, chipno = 1, addr = 0, offset = 0, voltH = 0, voltL = 0;
+ kal_uint8 voltHaddr = 0, VoltHoffset = 0, voltLaddr = 0, VoltLoffset = 0;
+ kal_uint16 tmpaddr = 0, tmpvoltHAddr = 0, tmpvoltLAddr = 0, pg = 0, vcc_val = 0;
+
+ pg = regTable[port].pin_group;
+ vcc_val = regTable[port].vcc;
+ voltH = regTable[port].voltH;
+ voltL = regTable[port].voltL;
+
+ tmpaddr = (vcc_val & 0xFF0);
+ addr = (kal_uint8)(tmpaddr >> 4); //MT6306 I2C Spec.
+ offset = vcc_val & 0xF;
+ if (addr <= 3)
+ {
+ chipno = 0;
+ }
+
+
+
+ sim_MT63062_TakeI2Csem();
+ /* used to check if any context access Writer interface */
+ if (spiWriterFlag == KAL_TRUE)
+ SIM_DEBUG_ASSERT(0);
+ spiWriterFlag = KAL_TRUE;
+ if (on == KAL_TRUE)
+ {
+ /* select pin group */
+ MT6306_GPIO_SelPinGroup(pg);
+
+ tmpvoltHAddr = (voltH & 0xFF0);
+ voltHaddr = (kal_uint8)(tmpvoltHAddr >> 4); //MT6306 I2C Spec.
+ VoltHoffset = voltH & 0xF;
+
+ tmpvoltLAddr = (voltL & 0xFF0);
+ voltLaddr = (kal_uint8)(tmpvoltLAddr >> 4); //MT6306 I2C Spec.
+ VoltLoffset = voltL & 0xF;
+
+ switch (volt)
+ {
+ case SIMGPIO_VOLT_18V:
+ /* write VSELx[1] */
+ Reg = MT6306_Reader_AL(chipno, voltHaddr);
+ Reg &= ~(1 << VoltHoffset);
+
+ MT6306_Writer_AL(chipno, ((voltHaddr << 4) | Reg));
+
+ /* write VSELx[0] */
+ Reg = MT6306_Reader_AL(chipno, voltLaddr);
+ Reg &= ~(1 << VoltLoffset);
+
+ MT6306_Writer_AL(chipno, ((voltLaddr << 4) | Reg));
+ break;
+ case SIMGPIO_VOLT_28V:
+ /* write VSELx[1] */
+ Reg = MT6306_Reader_AL(chipno, voltHaddr);
+ Reg &= ~(1 << VoltHoffset);
+
+ MT6306_Writer_AL(chipno, ((voltHaddr << 4) | Reg));
+
+ /* write VSELx[0] */
+ Reg = MT6306_Reader_AL(chipno, voltLaddr);
+ Reg |= 1 << VoltLoffset;
+
+ MT6306_Writer_AL(chipno, ((voltLaddr << 4) | Reg));
+ break;
+ case SIMGPIO_VOLT_30V:
+ /* write VSELx[1] */
+ Reg = MT6306_Reader_AL(chipno, voltHaddr);
+ Reg |= 1 << VoltHoffset;
+
+ MT6306_Writer_AL(chipno, ((voltHaddr << 4) | Reg));
+
+ /* write VSELx[0] */
+ Reg = MT6306_Reader_AL(chipno, voltLaddr);
+ Reg &= ~(1 << VoltLoffset);
+
+ MT6306_Writer_AL(chipno, ((voltLaddr << 4) | Reg));
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ Reg = MT6306_Reader_AL(chipno, addr);
+ Reg |= 1 << offset;
+
+ MT6306_Writer_AL(chipno, ((addr << 4) | Reg));
+ Delay(MT6306_SIM_GPIO_VCC_DELAY);
+ }
+ else
+ {
+ Reg = MT6306_Reader_AL(chipno, addr);
+ Reg &= ~(1 << offset);
+
+ MT6306_Writer_AL(chipno, ((addr << 4) | Reg));
+ Delay(MT6306_SIM_GPIO_VCC_DELAY);
+ }
+ if (spiWriterGptTimeoutFlag == KAL_TRUE)
+ {
+ MT6306_GPIO_checkClkStopQueue();
+ }
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+}
+
+/*************************************************************************
+* FUNCTION
+* MT6306_GPIO_ReadIO
+*
+* DESCRIPTION
+* This function implements read SIMGPIO value.
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_uint8 MT6306_GPIO_ReadIO(kal_uint8 port)
+{
+ kal_uint8 Reg = 0, chipno = 1, addr = 0, offset = 0;
+ kal_uint16 tmpaddr = 0, gpi_val = 0;
+
+ gpi_val = regTable[port].gpi_val;
+
+ tmpaddr = (gpi_val & 0xFF0);
+ addr = (kal_uint8)(tmpaddr >> 4); //MT6306 I2C Spec.
+ offset = gpi_val & 0xF;
+ if (addr <= 3)
+ {
+ chipno = 0;
+ }
+
+ sim_MT63062_TakeI2Csem();
+ /* used to check if any context access Writer interface */
+ if (spiWriterFlag == KAL_TRUE)
+ SIM_DEBUG_ASSERT(0);
+ spiWriterFlag = KAL_TRUE;
+ Reg = MT6306_Reader_AL(chipno, addr);
+ if (spiWriterGptTimeoutFlag == KAL_TRUE)
+ {
+ MT6306_GPIO_checkClkStopQueue();
+ }
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+ return Reg >> offset;
+}
+
+/*************************************************************************
+* FUNCTION
+* MT6306_GPIO_WriteIO
+*
+* DESCRIPTION
+* This function implements write SIMGPIO drive high/low.
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_uint8 MT6306_GPIO_WriteIO(kal_uint8 data, kal_uint8 port)
+{
+ kal_uint8 Reg = 0, chipno = 1, addr = 0, offset = 0;
+ kal_uint16 tmpaddr = 0, drive = 0;
+
+ drive = regTable[port].drive_high;
+ tmpaddr = (drive & 0xFF0);
+ addr = (kal_uint8)(tmpaddr >> 4); //MT6306 I2C Spec.
+
+ if (addr <= 3)
+ {
+ chipno = 0;
+ }
+ sim_MT63062_TakeI2Csem();
+ /* used to check if any context access Writer interface */
+ if (spiWriterFlag == KAL_TRUE)
+ SIM_DEBUG_ASSERT(0);
+ spiWriterFlag = KAL_TRUE;
+
+ if (data == 1)
+ {
+ Reg = MT6306_Reader_AL(chipno, addr);
+ drive |= Reg;
+ }
+ else
+ {
+ offset = regTable[port].drive_low & 0xF;
+ Reg = MT6306_Reader_AL(chipno, addr);
+ Reg &= ~(1 << offset);
+ drive = (addr << 4) | Reg;
+ }
+ MT6306_Writer_AL(chipno, drive);
+ if (spiWriterGptTimeoutFlag == KAL_TRUE)
+ {
+ MT6306_GPIO_checkClkStopQueue();
+ }
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+ return 1; //success return
+}
+#endif
+#endif //DRV_SIM_OFF
+
+
diff --git a/mcu/driver/devdrv/usim/mt6306/src/dcl_sim_gpio.c b/mcu/driver/devdrv/usim/mt6306/src/dcl_sim_gpio.c
new file mode 100644
index 0000000..613fbef
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/src/dcl_sim_gpio.c
@@ -0,0 +1,424 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_sim_gpio.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines DCL (Driver Common Layer) of the SIM GPIO card driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#include "drv_features.h"
+#include "drv_comm.h"
+#include "dcl.h"
+#include "init.h"
+#include "kal_public_api.h"
+#ifdef DCL_SIM_INTERFACE
+
+#if !defined(DRV_SIM_OFF)
+/**************************************************************************
+following defines static global variables used in this file
+***************************************************************************/
+
+/******************************************************************************************
+*following are extern variables from other file
+******************************************************************************************/
+#define DCL_SIMGPIO_MAGIC_NUM 0x20000000
+#define DCL_SIMGPI_MAGIC_NUM 0x10000000
+
+#define DCL_SIMGPIO_IS_HANDLE_MAGIC(handle_) ((handle_)& DCL_SIMGPIO_MAGIC_NUM)
+#define DCL_SIMGPIO_GET_DEV(handle_) ((handle_)& (~DCL_SIMGPIO_MAGIC_NUM))
+
+#define DCL_SIMGPI_IS_HANDLE_MAGIC(handle_) ((handle_) & DCL_SIMGPI_MAGIC_NUM)
+#define DCL_SIMGPI_GET_DEV(handle_) ((handle_) & (~DCL_SIMGPI_MAGIC_NUM))
+
+/***************************************************************************************
+followings are DCL SIM GPIO API exported
+*****************************************************************************************/
+DCL_STATUS DclSIMGPIO_Initialize(void)
+{
+ return STATUS_OK;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+* DclSIMGPIO_Open
+* DESCRIPTION
+* This function is to open the GPIO module and get a handle. Note that multiple opens are allowed.
+*
+* PARAMETERS
+* eDev: - only valid for DCL_GPIO,DCL_GPO,DCL_GPIO_CLK.
+* flags: - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID: - Open failed.
+* other value: - a valid handle
+*
+*-----------------------------------------------------------------------*/
+
+DCL_HANDLE DclSIMGPIO_Open(DCL_DEV eDev, DCL_FLAGS flags)
+{
+ if (flags > 0xFF)
+ {
+ SIM_DEBUG_ASSERT(0);
+ return DCL_HANDLE_INVALID;
+ }
+ if (eDev == DCL_SIM_GPIO)
+ return (DCL_SIMGPIO_MAGIC_NUM | flags);
+ else if (eDev == DCL_SIM_GPI)
+ return (DCL_SIMGPI_MAGIC_NUM | flags);
+ else
+ {
+ EXT_ASSERT(0, eDev, flags, 0);
+ return DCL_HANDLE_INVALID;
+ }
+ return DCL_HANDLE_NONE;
+}
+
+DCL_STATUS DclSIMGPIO_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIMGPIO_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIMGPIO_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIMGPIO_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+* DclSIMGPIO_Control
+*
+* DESCRIPTION
+* This function is to send command to control the GPIO module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclGPIO_Open()
+* cmd - a control command for GPIO module
+* 1. SIMGPIO_CMD_READ: to read the input value from the GPIO port contain in handle.
+* 2. SIMGPIO_CMD_WRITE: to write low to the output of GPIO port contain in handle.
+* 3. SIMGPIO_CMD_SET_DIR: to set direction of GPIO port contain in handle.
+* 4. SIMGPIO_CMD_TRUN_ON_VCC: to turn vcc and select voltage domain.
+* 5. SIMGPI_CMD_READ: to read GPI value.
+* RETURNS
+* STATUS_OK - command is executed successfully.
+* STATUS_FAIL - command is failed.
+* STATUS_INVALID_CMD - The command is invalid.
+* STATUS_INVALID_DCL_HANDLE - The handle is invalid.
+* STATUS_INVALID_CTRL_DATA - The ctrl data is not valid.
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclSIMGPIO_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ kal_char port;
+ port = 0x000000FF & handle;
+
+ if (DCL_SIMGPIO_IS_HANDLE_MAGIC(handle))
+ {
+
+ switch (cmd)
+ {
+ case SIMGPIO_CMD_READ:
+ {
+ SIMGPIO_CTRL_READ_T *prRead;
+
+ prRead = &(data->rSGRead);
+ prRead->u1IOData = MT6306_GPIO_ReadIO(port);
+ break;
+ }
+ case SIMGPIO_CMD_WRITE:
+ {
+ SIMGPIO_CTRL_WRITE_T *prWrite;
+
+ prWrite = &(data->rSGWrite);
+ MT6306_GPIO_WriteIO(prWrite->u1IOData, port);
+ break;
+ }
+ case SIMGPIO_CMD_SET_DIR:
+ {
+ SIMGPIO_CTRL_SET_DIR_T *prSetDir;
+
+ prSetDir = &(data->rSGSetDir);
+ MT6306_GPIO_InitIO(prSetDir->u2Dir, port);
+ break;
+ }
+ case SIMGPIO_CMD_TRUN_ON_VCC:
+ {
+ SIMGPIO_CTRL_TRUN_ON_POWER *prTurnOnPower;
+
+ prTurnOnPower = &(data->rSGTurnOnPower);
+ MT6306_GPIO_TurnOnVcc(prTurnOnPower->on, prTurnOnPower->volt, port);
+ break;
+ }
+ default:
+ EXT_ASSERT(0, handle, cmd, 0);
+ return STATUS_INVALID_DCL_HANDLE;
+
+ }
+ }
+ else if (DCL_SIMGPI_IS_HANDLE_MAGIC(handle))
+ {
+ switch (cmd)
+ {
+ case SIMGPI_CMD_READ:
+ {
+ SIMGPIO_CTRL_READ_T *prIRead;
+
+ prIRead = &(data->rSGIRead);
+ prIRead->u1IOData = MT6306_GPIO_ReadIO(port);
+ break;
+ }
+ default:
+ EXT_ASSERT(0, handle, cmd, 0);
+ return STATUS_INVALID_DCL_HANDLE;
+ }
+ }
+ else
+ {
+ EXT_ASSERT(0, handle, cmd, 0);
+ return STATUS_INVALID_DCL_HANDLE;
+ }
+ return STATUS_OK;
+}
+
+/*-----------------------------------------------------------------------*
+* FUNCTION
+* DclSIMGPIO_Close
+*
+* DESCRIPTION
+* This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*-----------------------------------------------------------------------*/
+DCL_STATUS DclSIMGPIO_Close(DCL_HANDLE handle)
+{
+ return STATUS_OK;
+}
+
+#else /*!defined(DRV_SIM_OFF)*/
+
+
+DCL_STATUS DclSIMGPIO_Initialize(void)
+{
+ return STATUS_FAIL;
+}
+
+DCL_HANDLE DclSIMGPIO_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+ return DCL_HANDLE_INVALID;
+}
+
+DCL_STATUS DclSIMGPIO_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIMGPIO_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIMGPIO_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIMGPIO_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ return STATUS_FAIL;
+}
+
+DCL_STATUS DclSIMGPIO_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ return STATUS_FAIL;
+}
+
+DCL_STATUS DclSIMGPIO_Close(DCL_HANDLE handle)
+{
+ return STATUS_FAIL;
+}
+
+#endif /*!defined(DRV_SIM_OFF)*/
+
+#endif /*DCL_SIM_INTERFACE*/
diff --git a/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl0_mt6306.c b/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl0_mt6306.c
new file mode 100644
index 0000000..103052c
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl0_mt6306.c
@@ -0,0 +1,5375 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * switchControl0.c (originally named simd_MT6306.c)
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the SIM driver in MT6306 switch solution.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "kal_public_api.h"
+//#include "stack_common.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_msgs.h"
+//RHR#include "syscomp_config.h"
+//RHR#include "task_config.h"
+//RHR#include "stacklib.h"
+#include "drv_comm.h"
+#include "md_drv_sap.h"
+#include "nvram_msgid.h"
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#include "reg_base.h"
+#include "intrCtrl.h"
+#include "sim_reg_adp.h"
+
+#include "sim_hw_mtk.h"
+#include "sim_al.h"
+//#include "dma_sw.h"
+#include "sim_sw_comm.h"
+#include "drvpdn.h"
+#include "drv_hisr.h"
+
+#ifdef __MTK_TARGET__
+#if (defined(DRV_SIM_ALL_SOLUTION_BUILT) || (defined(DRV_MULTIPLE_SIM) && defined(DRV_2_SIM_CONTROLLER)))
+#if !defined(DRV_SIM_MT6208_SERIES)
+//#ifdef MT6318
+//#include "pmic6318_sw.h"
+//#endif /*MT6318*/
+//RHR#include "init.h"
+
+#ifndef __MAUI_BASIC__
+//RHR#include "nvram_user_defs.h"
+#include "nvram_struct.h"
+#endif
+
+#include "sim_mtk.h"
+
+//#include "pwic.h"
+
+//#if defined(MT6223PMU)
+//#include "pmu_sw.h"
+//#endif
+
+#include "sim_mt6306.h"
+#include "sim_ctrl_al.h"
+#include "sim_drv_trc.h"
+
+#ifdef SIM_CACHED_SUPPORT
+#include "cache_sw.h"
+#endif
+//#include "pmic6326_ccci_sw.h"
+//#endif
+
+/*RHR*/
+#include "drv_features.h"
+//#include "kal_non_specific_general_types.h"
+#include "string.h"
+#include "sim_nvram_def.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#include "stdio.h"
+//#include "pmic_features.h"
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if !defined( __MAUI_BASIC__)
+#include "kal_trace.h"
+#else
+extern void dbg_print(char *fmt, ...);
+#endif
+#include "kal_debug.h"
+/*RHR*/
+//#include "mt63062.h"
+
+#define SIM_NULLBYTE_ISSUE
+#ifdef SIM_NULLBYTE_ISSUE
+/*
+magic1 is an increasing counter, increases when 1) start new command, 2)get SIM timeout, 3)get T0 end
+for case 2 and 3, it means that one of the ends of SIM commands has appeared.
+*/
+//kal_uint32 simMagic1;
+/*
+magic2 is used to compared with magic1 every time GPT expires. It is set to magic1 in the start of a new command,
+if they were compared equally in GPT timer, we know that we are still waiting for SIM controller's event.
+*/
+//kal_uint32 SimCard->simMagic2;
+//kal_uint32 GPTServingInterface;
+//kal_uint8 SimCard->sim_nullByteIssueGPT, SimCard->sim_nullByteIssueNullCount;
+//extern kal_bool GPTI_StartItem(kal_uint8 module,kal_uint16 tick,void (*gptimer_func)(void *),void *parameter);
+//extern void GPTI_StopItem(kal_uint8 module);
+//extern kal_uint8 GPTI_GetHandle(kal_uint8 *handle);
+#endif
+extern sim_MT6306_status sim_MT6306_passRST(sim_HW_cb *hw_cb);
+extern kal_int32 invalidate_wt_cache(kal_uint32 addr, kal_uint32 len);
+
+
+//#define SIM_DEFAULT_TOUT_VALUE 0x983
+//#define SIM_CMD_TOUT_VALUE 0x1400
+
+#define FILE_SWITCHCONTROL0 1
+
+extern kal_uint32 hwCbArray[];
+
+//kal_uint32 TOUTValue = SIM_DEFAULT_TOUT_VALUE;
+//static kal_uint8 TOUT_Factor=1;
+/*Maybe changed when the unit of the HW TOUT counter is changed!!*/
+
+static const kal_uint8 ClkStopTimeTable[5][2] = { {0, 5},
+ {3, 11},
+ {6, 19},
+ {12, 40},
+ {24, 78}
+};
+
+//I set the number of element to a fixed value, since this code is for analog-switch solution, I have no power to support more than 2 interface
+//static Sim_Card SimCard_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+
+extern usim_dcb_struct usim_cb[];
+//extern kal_bool sim_physicalSlotChanged;
+//Sim_Card *SimCard = &SimCard_cb[0];
+//kal_uint8 reset_index;
+//kal_uint8 PTS_data[4];
+
+#if defined(__USIM_DRV__)
+//kal_bool sim_ATR_fail;
+#endif
+
+//static kal_bool PTS_check = KAL_TRUE;
+//extern kal_uint8 sim_MT6306_regValue[];
+//extern kal_bool sim_workingTaskWaiting;
+
+
+static kal_uint32 SIM_ERROR_LINE[MAX_SIM_ERROR_LINE];
+static kal_uint8 SIM_ERROR_LINE_INDEX;
+static kal_bool sim_error_tag;
+
+#if defined(__ARMCC_VERSION)
+#pragma arm section zidata = "NONCACHEDZI", rwdata = "NONCACHEDRW"
+#endif
+#ifdef SIM_CACHED_SUPPORT
+/*declare 2 pairs of uncache buffer for 2 SIM interfaces*/
+extern kal_uint32 sim_uncachedTxBuffer0[], sim_uncachedRxBuffer0[], sim_uncachedTxBuffer1[], sim_uncachedRxBuffer1[];
+#define GET_NCACHEDTX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedTxBuffer0; else p=(kal_uint8 *)sim_uncachedTxBuffer1;}
+#define GET_NCACHEDRX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedRxBuffer0; else p=(kal_uint8 *)sim_uncachedRxBuffer1;}
+extern kal_uint8 uncachedDmaBuffer0[], uncachedDmaBuffer1[];//the instance is declared in icc_sim_common_mtk.c
+#define GET_NCACHED_USIM_DMA_BUF_P(p, a) {if(0==a) p=(kal_uint8 *)uncachedDmaBuffer0; else p=(kal_uint8 *)uncachedDmaBuffer1;}
+#define GET_NCACHED_USIM_DMA_BUF_INT(p, a) {if(0==a) p=(kal_uint32)uncachedDmaBuffer0; else p=(kal_uint32)uncachedDmaBuffer1;}
+#endif
+#if defined(__ARMCC_VERSION)
+#pragma arm section zidata, rwdata
+#endif
+
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+#include "hisr_config.h"
+#else
+static kal_hisrid sim_hisrid = NULL;
+static kal_hisrid sim2_hisrid = NULL;
+#endif
+
+void sim_PDNDisable_MT6306(sim_HW_cb *hw_cb);
+void sim_PDNEnable_MT6306(sim_HW_cb *hw_cb);
+extern int sprintf(char *, const char *, ...);
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+extern void sim_MT6306_VCCCtrl(sim_HW_cb *hw_cb, kal_uint32 on);
+extern void sim_MT6306_VCCLvlCtrl(sim_HW_cb *hw_cb, kal_uint32 level);
+extern kal_bool sim_MT6306_QueryNeedManualControl(sim_HW_cb *hw_cb);
+extern void sim_MT6306_manualDeactive(sim_HW_cb *hw_cb);
+extern sim_MT6306_status sim_MT6306_blockCLK(sim_HW_cb *hw_cb);
+extern void sim_MT6306_setCardState(sim_HW_cb *hw_cb, sim_MT6306_cardState cardState);
+extern kal_bool sim_MT6306_allCLKStopped(sim_HW_cb *hw_cb);
+extern void sim_MT6306_SPIWrite(sim_MT6306_switchInfo *switch_CB, kal_uint16 data);
+extern kal_uint8 sim_MT6306_SPIRead(sim_MT6306_switchInfo *switch_CB, kal_uint16 addr);
+extern void sim_MT6306_clkStopTimer(sim_HW_cb *hw_cb);
+extern sim_env SIM_GetCurrentEnv(kal_uint32 simInterface);
+extern void sim_MT6306_LISRStateChange(sim_HW_cb *hw_cb, sim_MT6306_LISRState lisrState);
+extern kal_uint32 SIM_GetCurrentTime(void);
+extern void SIM_SetRXTIDE(kal_uint16 RXTIDE, sim_HW_cb *hw_cb);
+extern void SIM_SetTXTIDE(kal_uint16 TXTIDE, sim_HW_cb *hw_cb);
+extern kal_uint32 SIM_GetDurationTick(kal_uint32 previous_time, kal_uint32 current_time);
+extern void sim_WWTTest(sim_HW_cb *hw_cb);
+extern kal_bool MT6306_ShowReg(int chip);
+extern kal_bool OSTD_Infinite_Sleep_Query(void);
+static void sim_assert_update_nvram(void)
+{
+#if SPICIAL_SIM
+#ifndef __MAUI_BASIC__
+ ilm_struct *ilm_ptr;
+ peer_buff_struct *peer_buffer_ptr;
+ sim_nvram_param_struct* data_stream;
+ nvram_write_req_struct* parm_stream;
+ kal_uint16 data_len;
+
+ parm_stream = (nvram_write_req_struct *)construct_local_para(sizeof(nvram_write_req_struct), TD_CTRL);
+ peer_buffer_ptr = construct_peer_buff(sizeof(SIM_ERROR_LINE), 0, 0, TD_CTRL);
+
+ data_stream = (sim_nvram_param_struct *)get_pdu_ptr(peer_buffer_ptr, &data_len);
+
+ memcpy(data_stream, SIM_ERROR_LINE, sizeof(SIM_ERROR_LINE));
+
+ //data_stream->ptr = SIM_ERROR_LINE;
+ //data_stream->size = sizeof(SIM_ERROR_LINE);
+
+ ((nvram_write_req_struct*) parm_stream)->file_idx = NVRAM_EF_SIM_ASSERT_LID;
+ ((nvram_write_req_struct*) parm_stream)->para = 1;
+
+ ilm_ptr = allocate_ilm(MOD_SIM);
+ ilm_ptr->src_mod_id = MOD_SIM;
+ ilm_ptr->msg_id = MSG_ID_NVRAM_WRITE_REQ;
+ ilm_ptr->sap_id = DRIVER_PS_SAP;
+ ilm_ptr->local_para_ptr = (local_para_struct *)parm_stream;
+ ilm_ptr->peer_buff_ptr = (peer_buff_struct *)peer_buffer_ptr;
+ ilm_ptr->dest_mod_id = MOD_NVRAM;
+ msg_send_ext_queue(ilm_ptr);
+#endif
+#endif
+}
+
+static void sim_dump_error_line(sim_HW_cb *hw_cb)
+{
+ if (sim_error_tag != KAL_FALSE)
+ {
+ //kal_sprintf(hw_cb->dbgStr,"[SIM_DRV]:I=%d,L=%d,%d,%d,%d", SIM_ERROR_LINE_INDEX, SIM_ERROR_LINE[0], SIM_ERROR_LINE[1], SIM_ERROR_LINE[2], SIM_ERROR_LINE[3]);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_DUMP_ERROR_LINE, SIM_ERROR_LINE_INDEX, SIM_ERROR_LINE[0], SIM_ERROR_LINE[1], SIM_ERROR_LINE[2], SIM_ERROR_LINE[3]);
+ sim_error_tag = KAL_FALSE;
+ sim_assert_update_nvram();
+ }
+}
+
+static void SIM_Initialize(kal_uint8 format, kal_uint8 power, sim_HW_cb *hw_cb);
+
+
+extern sim_MT6306_status sim_MT6306_passCLK(sim_HW_cb *hw_cb);
+static void SIM_L1Reset(sim_HW_cb *hw_cb, kal_bool maskSIMIntr)
+{
+ Sim_Card *SimCard;
+ sim_MT6306_switchInfo *switch_CB;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ SimCard = SimCard;
+ switch_CB = switch_CB;
+ SIM_DisAllIntr();
+
+#ifdef SIM_ADDDMA
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+#endif // SIM_ADDDMA
+
+ SIM_FIFO_Flush();
+ //De-activate SIM card
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)&SIM_CTRL_SIMON)
+ {
+ sim_addMsg(SIM_MT6306_DRIVER_DEACT, hw_cb->simInterface, 1, 0);
+ kal_set_eg_events(SimCard->event, 0, KAL_AND);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_SIMOFF | SIM_IRQEN_NATR));
+ /* [MAUI_03053369][1] Assert Fail: icc_switchControl2_mt6306.c 1502 -SIM*/
+ sim_MT6306_cardInfo *card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ DRV_ICC_GPTI_StopItem(card_cb->sim_MT6306_gptHandle);
+ if (sim_MT6306_CLKPass != card_cb->pins.CLK)
+ {
+ sim_MT6306_passCLK(hw_cb);
+ kal_sleep_task(1);
+ }
+ if (KAL_FALSE == sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+#if defined(__SIM_DRV_ENABLE_SWRST__)
+ // 1. pull low SIMRST
+ sim_MT6306_setRST(hw_cb, KAL_FALSE);
+ kal_sleep_task(16);
+ // 2. set SIM_CTRL register SWRST bit to enable ATR TOUT
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SWRST);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC35, SimCard->reject_set_event, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->State, 0);
+#endif
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);
+
+ SIM_Deactive();
+ //must wait for LDO falling time
+ if (KAL_FALSE == kal_query_systemInit())
+ {
+ kal_sleep_task(10);
+ }
+ /* we should wait SIMOFF interrupt */
+ SIM_WaitEvent_MT6306(SimCard, DEACTIVATE_DONE, KAL_FALSE, hw_cb);
+ while (!(DRV_Reg32(hw_cb->mtk_baseAddr + SIM_ATRSTA_MTK) & 0x0001));
+ /*since we have do lots actions, if its context is task, there maybe chance that hisr occur before we wait event*/
+ /*to prevent this race condition, if maskSIMIntr is true, we have to disable SIM's interrupt*/
+ if (KAL_TRUE == maskSIMIntr)
+ IRQMask(hw_cb->mtk_lisrCode);
+ sim_MT6306_VCCCtrl(hw_cb, 0);
+ if (KAL_FALSE == kal_query_systemInit())
+ {
+ kal_sleep_task(16);
+ }
+ /*turn off LDO*/
+#if !defined(__DRV_SIM_SIMIF_CONTROL_VSIM__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_FALSE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_FALSE);
+ }
+#endif
+ kal_sleep_task(16);
+ }
+ else
+ {
+ sim_MT6306_manualDeactive(hw_cb);
+ /*since we don't use HISR and event, we have to set ev_status manually*/
+ SimCard->EvtFlag = DEACTIVATE_DONE;
+ }
+ }
+ else
+ {
+ /*since we have do lots actions, if its context is task, there maybe chance that hisr occur before we wait event*/
+ /*to prevent this race condition, if maskSIMIntr is true, we have to disable SIM's interrupt*/
+ if (KAL_TRUE == maskSIMIntr)
+ {
+ IRQMask(hw_cb->mtk_lisrCode);
+ }
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC46, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ }
+}
+
+
+
+#ifdef NoT0CTRL
+kal_uint8 SIM_CheckSW(kal_uint16 ACK)
+{
+ if ((ACK & 0x00f0) == 0x0060)
+ return KAL_TRUE;
+ if ((ACK & 0x00f0) == 0x0090)
+ return KAL_TRUE;
+
+ return KAL_FALSE;
+}
+#endif /*NoT0CTRL*/
+static kal_bool SIM_ResetNoATR(kal_uint8 pow, sim_HW_cb *hw_cb) //For normal case reset
+{
+ //Only enable SIM interrupt
+
+ Sim_Card *SimCard;
+ sim_MT6306_switchInfo *switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ switch_CB = switch_CB;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->State = SIM_WAIT_FOR_ATR;
+ SimCard->reset_index = 0;
+ SimCard->Power = pow;
+
+ //Deactivate the SIM card
+ SIM_L1Reset(hw_cb, KAL_FALSE);
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (usim_dcb->present == KAL_FALSE)
+ return KAL_FALSE;
+#endif
+
+ SIM_WaitEvent_MT6306(SimCard, RST_READY, KAL_TRUE, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC47, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ if (SimCard->result == SIM_SUCCESS)
+ {
+ return KAL_TRUE;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+
+}
+
+static void SIM_Initialize(kal_uint8 format, kal_uint8 power, sim_HW_cb *hw_cb)
+{
+ kal_uint16 Conf = 0;
+ Sim_Card *SimCard;
+ const kal_uint8 *tmpPtr = ClkStopTimeTable[0];
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div7;
+#elif defined(SIM_DRV_4_33MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div8;
+#else
+ kal_uint32 clk_div = SIM_BRR_CLK_Div4;
+#endif
+
+ tmpPtr = tmpPtr;
+ //sim_input = sim_input;
+ //sim_menu = sim_menu;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->Data_format = format;
+ SimCard->Power = power;
+#if defined(SIM_DEBUG_INFO)
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "SIM_Initialize power: %d, format: %d, TS_HSK_ENABLE: %d\n\r", power, format, SimCard->TS_HSK_ENABLE);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ //Setup the SIM control module, SIM_BRR, SIM_CONF
+ //Set SIMCLK = 13M/4, and BAUD RATE = default value(F=372,D=1);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div372));
+
+ if (format != SIM_direct)
+ {
+ Conf |= SIM_CONF_CONV;
+ }
+ else
+ {
+ Conf &= ~(SIM_CONF_CONV);
+ }
+
+#if !defined(__DRV_SIM_SIMIF_CONTROL_VSIM__)
+ /*use PMU API to enalbe MT632x PMIC LDO output to 1.8V
+ it will pull up SIMIO/SIMCLK/SIMIO.
+ BB SIMIO/SIMCLK/SIMIO is powered by AVDD30_VSIMn by PMIC feedback
+ logical circuit */
+ /* fix PMIC output to 1.8V */
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(0, CLASS_C_18V);
+ }
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(1, CLASS_C_18V);
+ }
+
+ Conf |= SIM_CONF_SIMSEL;
+ if (SIM_30V == power)
+ {
+ sim_MT6306_VCCLvlCtrl(hw_cb, 1);
+ }
+ else
+ {
+ sim_MT6306_VCCLvlCtrl(hw_cb, 0);
+ }
+#else /*Phone setting*/
+ SIM_DEBUG_ASSERT(0);
+#endif /*Phone setting*/
+
+ if (SimCard->TS_HSK_ENABLE == KAL_TRUE)
+ Conf |= (SIM_CONF_TXHSK | SIM_CONF_RXHSK);
+
+#if defined (__SIM_ATRSTA_BIT_SHIFT__)
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, Conf | SIM_CONF_RSTCTL);
+#else
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, Conf);
+#endif
+ if (SimCard->TS_HSK_ENABLE == KAL_TRUE)
+ {
+ SIM_SetRXRetry(1);
+ SIM_SetTXRetry(1);
+ }
+ else
+ {
+ SIM_SetRXRetry(0);
+ SIM_SetTXRetry(0);
+ }
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ //Set the ATRTout as 9600etu
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+
+ // reset interrupts, flush rx, tx fifo
+ SIM_FIFO_Flush();
+
+ //Set the txfifo and rxfifo tide mark
+ SIM_SetRXTIDE(1, hw_cb);
+
+ //Read Interrupt Status
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+
+ SimCard->State = SIM_WAIT_FOR_ATR;
+
+ //Enable Interrupt
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_Normal & ~SIM_IRQEN_RXERR));
+ SimCard->recDataErr = KAL_FALSE;
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ SIM_CLR_OE_BIT();
+ //activate the SIM card, and activate the SIMCLK
+ /* Enable PMIC VSIM LDO to fix 1.8V */
+#if !defined(__DRV_SIM_SIMIF_CONTROL_VSIM__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_TRUE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_TRUE);
+ }
+#endif
+ /* Enable MT6306 VSIM LDO */
+ sim_MT6306_VCCCtrl(hw_cb, 1);
+ sim_addMsg(SIM_MT6306_DRIVER_ACT, hw_cb->simInterface, 1, power);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC68, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), 0, 0);
+
+ if (sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+ sim_MT6306_manualReset(hw_cb);
+ }
+ else
+ {
+
+ SIM_Active();
+ ////dbg_print("SIM ACtive\r\n");
+#if defined(__SIM_DRV_ENABLE_SWRST__)
+ SIM_WaitEvent_MT6306(SimCard, SWRST_INT_END, KAL_FALSE, hw_cb);
+ if (SimCard->result == SIM_SWRST)
+ {
+ // 1. swrst interrupt received
+ // 2. pull high SIMRST
+ sim_MT6306_setRST(hw_cb, KAL_TRUE);
+ // 3. reenable WWT T0 and clear ev_status
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ SimCard->result = SIM_SUCCESS;
+ // 4. set SIM_CTRL register SWRST bit to enable ATR TOUT
+ SIM_SetData(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK, SIM_CTRL_SWRST, SIM_CTRL_SWRST);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC36, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0, 0);
+ //Enable Interrupt
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_Normal & ~SIM_IRQEN_RXERR));
+ }
+ else
+ {
+ kal_set_eg_events(SimCard->event, 0, KAL_AND);
+ // there should be not interrupt can earier than USIM_WAITING_SWRST
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC37, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ // SIM_DEBUG_ASSERT(0);
+ }
+#endif
+
+ }
+}
+
+extern kal_uint32 MT6306_initDelayTime;
+
+static kal_bool SIM_PTSProcess(kal_uint8 *TxBuffaddr, kal_uint8 Txlength, sim_HW_cb *hw_cb) //Bool lalasun
+{
+ kal_uint8 index;
+ kal_uint8 tmp;
+ Sim_Card *SimCard = NULL;
+ usim_dcb_struct *usim_dcb = NULL;
+ sim_MT6306_switchInfo *switch_CB = NULL;
+ switch_CB = switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+
+#if defined(__USIM_DRV__)
+#ifdef SIM_ACTIVATE_BY_PTS_ERROR
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON) == 0)
+ {
+ SimCard->sim_ATR_fail = KAL_TRUE;
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC49, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_WaitEvent_MT6306(SimCard, RST_READY, KAL_TRUE, hw_cb);
+
+ if (SimCard->result != SIM_SUCCESS)
+ {
+ return KAL_FALSE;
+ }
+ //Got TS, need to wait for all ATR received
+ kal_sleep_task(KAL_TICKS_500_MSEC_REAL);
+ }
+#endif
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK))
+ {
+ USIM_CLR_FIFO();
+ }
+ if (usim_dcb->reset_mode == USIM_RESET_SPECIFIC && (usim_dcb->TA2 & 0x10) == 0)
+ return KAL_TRUE;
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+#endif
+
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && SimCard->forceISO == KAL_FALSE)
+ {
+ Txlength = 4;
+ *(TxBuffaddr) = 0xFF;
+ *(TxBuffaddr + 1) = 0x2F;
+ *(TxBuffaddr + 2) = 0xC0;
+ *(TxBuffaddr + 3) = 0x10;
+ }
+#endif
+ /* fix plug out cause this flag set as true, but let next PPS response can't reveice data at Rxtide interrupt */
+ SimCard->timeout = KAL_FALSE;
+
+ for (index = 0; index < Txlength; index++)
+ {
+ SimCard->PTS_data[index] = 0;
+ tmp = * (TxBuffaddr + index);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, tmp);
+ }
+
+ SimCard->State = SIM_PROCESS_PTS;
+
+ SIM_SetRXTIDE(Txlength, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_Normal);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ SimCard->timeout = KAL_FALSE;
+ SIM_WaitEvent_MT6306(SimCard, PTS_END, KAL_FALSE, hw_cb);
+
+ if ((SimCard->recDataErr == KAL_TRUE)
+ || (SimCard->result == SIM_INIPTSERR))
+ {
+#ifndef __MAUI_BASIC__
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__, SimCard->recDataErr, drv_get_current_time(), *TxBuffaddr, *(TxBuffaddr + 1), *(TxBuffaddr + 2), *(TxBuffaddr + 3));
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+#endif
+ SimCard->recDataErr = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC50, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ DRV_ICC_print_err_msg(hw_cb, "SIM_INIPTSERR");
+ return KAL_FALSE;
+ }
+
+ for (index = 0; index < Txlength; index++)
+ {
+ if (SimCard->PTS_data[index] != * (TxBuffaddr + index))
+ {
+#ifndef __MAUI_BASIC__
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__, *TxBuffaddr, *(TxBuffaddr + 1), *(TxBuffaddr + 2), *(TxBuffaddr + 3), SimCard->PTS_data[index], index);
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC51, SimCard->PTS_data[0], SimCard->PTS_data[1], SimCard->PTS_data[2], SimCard->PTS_data[3], 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC51, *(TxBuffaddr + 0), *(TxBuffaddr + 1), *(TxBuffaddr + 2), *(TxBuffaddr + 3), 0);
+
+ return KAL_FALSE;
+ }
+ }
+ // Some high speed SIM card after clock rate change have to wait a while to
+ // to receive the first command.
+ if (SimCard->PTS_data[1] != 0x00)
+ kal_sleep_task(10);
+
+ return KAL_TRUE;
+}
+
+static kal_bool SIM_ProcessATRData(sim_HW_cb *hw_cb)
+{
+ kal_uint8 index = 0;
+ kal_uint16 tmp, tmp1, Fi = 372;
+ kal_uint8 ptsdata[4];
+ /*TOUT is an uint32 value*/
+ kal_uint32 TOUT = 0, WWT = 0;
+ kal_uint8 Dvalue = 1;
+ Sim_Card *SimCard = NULL;
+ usim_dcb_struct *usim_dcb = NULL;
+ sim_MT6306_switchInfo *switch_CB = NULL;
+ kal_char *p;
+ kal_uint32 i, log_size = 0;
+ /* fix build warning */
+ TOUT = TOUT;
+ WWT = WWT;
+ switch_CB = switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+#if defined(__USIM_DRV__)
+ if (SimCard->sim_ATR_fail)
+ {
+ SIM_WaitEvent_MT6306(SimCard, ATR_END, KAL_FALSE, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC52, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ SimCard->recDataErr = KAL_FALSE;
+ return KAL_FALSE;
+ }
+ DRV_ICC_print_str("[SIM_DRV]Bad Card Recovery Success.");
+ /* For DHL Limitation, Log length should <= 116bytes */
+ p = hw_cb->dbgStr;
+ log_size = kal_sprintf(p, "[SIM_DRV:%d]SIM ATR= ", hw_cb->simInterface);
+ p += strlen(p);
+ for (i = 0; i < SimCard->recDataLen; i++)
+ {
+ log_size += kal_sprintf(p, "%02X", SimCard->recData[i]);
+ p += 2;
+ }
+#ifdef ATEST_DRV_ENABLE
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ATR,hw_cb->dbgStr);
+#endif
+
+ }
+ else
+ {
+ kal_mem_cpy(SimCard->recData, usim_dcb->ATR_data, usim_dcb->ATR_index);
+ }
+#else
+ SIM_WaitEvent_MT6306(SimCard, ATR_END, KAL_FALSE, hw_cb);
+
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ SimCard->recDataErr = KAL_FALSE;
+ return KAL_FALSE;
+ }
+#endif
+
+ index = 2;
+ if (SimCard->recData[1] & 0x00f0)
+ {
+ if (SimCard->recData[1] & TAMask)
+ {
+ tmp = SimCard->recData[index]; //TA1
+ index++;
+ ////dbg_print("TA1=%x\r\n",tmp);
+ // default value of Fi, Di, or TA2 with bit5==1
+ if ((tmp == 0x0011) || (tmp == 0x0001) || (usim_dcb->reset_mode == USIM_RESET_SPECIFIC && (usim_dcb->TA2 & 0x10)))
+ {
+ //Don't process ATR data!!
+ SimCard->State = SIM_PROCESSCMD;
+ SIMCmdInit();
+#ifdef NoT0CTRL
+ SimCard->cmdState = SIMD_CmdIdle;
+#endif
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ return KAL_TRUE;
+ }
+ else
+ {
+ /* Set default Fi as 512 */
+ Fi = 512;
+ switch (tmp)
+ {
+ case 0x0094: //F = 512,D=8
+ SimCard->sim_card_speed = sim_card_enhance_speed_64;
+
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 8;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x94;
+ ptsdata[3] = 0x7b;
+ SimCard->Speed = Speed64;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div64);
+ SimCard->TOUT_Factor = 8; //hw-specific
+ /* calc 512/8 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 8, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+
+ case 0x0095: //F=512,D=16
+ SimCard->sim_card_speed = sim_card_enhance_speed_32;
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 16;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x95;
+ ptsdata[3] = 0x7a;
+ SimCard->Speed = Speed32;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div32);
+ SimCard->TOUT_Factor = 16;
+ /* calc 512/16 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 16, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+ case 0x0096: //F=512,D=32
+ SimCard->sim_card_speed = sim_card_enhance_speed_16;
+
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 32;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x96;
+ ptsdata[3] = 0x79;
+ SimCard->Speed = Speed16;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div16);
+ SimCard->TOUT_Factor = 32;
+ /* calc 512/32 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 32, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+ case 0x0097: //F=512,D=64
+ SimCard->sim_card_speed = sim_card_enhance_speed_8;
+
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 64;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x97;
+ ptsdata[3] = 0x78;
+ SimCard->Speed = Speed8;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div8);
+ SimCard->TOUT_Factor = 64;
+ /* calc 512/64 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 64, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+ default: //F=372,D=1
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ break;
+ }
+ }
+ } /*if (SimCard->recData[1] & TAMask)*/
+
+
+ SimCard->Fi = Fi;
+
+
+ if (SimCard->recData[1] & TBMask)
+ {
+ tmp = SimCard->recData[index];
+ ////dbg_print("TB1=%x\r\n",tmp);
+ index++;
+ }
+ if (SimCard->recData[1] & TCMask)
+ {
+ tmp = SimCard->recData[index];
+ ////dbg_print("TC1=%x\r\n",tmp);
+ if (tmp != 0xff && tmp != 0x00)
+ {
+ return KAL_FALSE;
+ }
+ index++;
+ }
+
+ if (SimCard->recData[1] & TDMask)
+ {
+ tmp = SimCard->recData[index]; // TD1
+ index++;
+ // dbg_print("TD1=%x\r\n",tmp);
+ if (tmp & TCMask) //TC2 is obtain
+ {
+ if (tmp & TAMask)
+ {
+ tmp1 = SimCard->recData[index];
+ // dbg_print("TA2=%x\r\n",tmp1);
+ index++;
+ }
+ if (tmp & TBMask)
+ {
+ tmp1 = SimCard->recData[index];
+ // dbg_print("TB2=%x\r\n",tmp1);
+ index++;
+ }
+ if (tmp & TCMask) //TC2
+ {
+ tmp1 = SimCard->recData[index];
+ // dbg_print("TC2=%x\r\n",tmp1);
+ // TOUT is an uint32 value
+ // TOUT = (960*Dvalue);
+ // TOUT = (TOUT*tmp1)/4; // (/4)is hw-specific
+ index++;
+// SimCard->TOUTValue = TOUT+8;
+ // dbg_print("TOUT=%x\r\n",TOUT);
+ SimCard->TC2Present = KAL_TRUE;
+ // Calc 512/Dvalue TOUT value
+ DRV_ICC_Calc_WWT(Fi, Dvalue, tmp1, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+
+// if (TOUT < 0xffff)
+// SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), TOUT);
+// else
+// SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffff);
+ }
+ }
+ } /*if (SimCard->recData[1] & TDMask)*/
+ }/*if (SimCard->recData[1] & 0x00f0)*/
+ SimCard->State = SIM_PROCESSCMD;
+ SIMCmdInit();
+#ifdef NoT0CTRL
+ SimCard->cmdState = SIMD_CmdIdle;
+#endif /*NoT0CTRL*/
+ return KAL_TRUE;
+}
+
+static void SIM_Cmdhandler(sim_HW_cb *hw_cb)
+{
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+#ifndef SIM_ADDDMA
+ while (SIM_FIFO_GetLev())
+ {
+ * (SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK));
+ SimCard->recDataLen++;
+ }
+#endif /*SIM_ADDDMA*/
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);
+ return;
+}
+
+#ifndef SIM_ADDDMA
+void SIM_Txhandler(sim_HW_cb *hw_cb)
+{
+#ifdef NoT0CTRL
+ kal_uint8 index;
+ kal_uint16 reslen;
+ reslen = SimCard->txsize - SimCard->txindex;
+ if (reslen <= 15)
+ {
+ for (index = 0; index < reslen; index++)
+ {
+ SIM_WriteReg(SIM_DATA, * (SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_SetRXTIDE(2);
+ SimCard->cmdState = SIM_WaitProcByte;
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ }
+ else
+ {
+ for (index = 0; index < 15; index++)
+ {
+ SIM_WriteReg(SIM_DATA, * (SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_SetTXTIDE(0, hw_cb);
+ SIM_WriteReg(SIM_IRQEN, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ }
+ return;
+#else /*NoT0CTRL*/
+ kal_uint8 index;
+ kal_uint16 reslen;
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+
+ reslen = SimCard->txsize - SimCard->txindex;
+ if (reslen <= 15)
+ {
+ for (index = 0; index < reslen; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, * (SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDNormal);
+ }
+ else
+ {
+ for (index = 0; index < 15; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, * (SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_SetTXTIDE(0, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ }
+#endif /*NoT0CTRL*/
+}
+#endif /*SIM_ADDDMA*/
+
+static void SIM_Rxhandler(kal_uint16 sim_int, sim_HW_cb *hw_cb)
+{
+ kal_uint16 TS;
+ kal_uint8 index;
+ Sim_Card *SimCard;
+ kal_uint32 log_size = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ if (SimCard->State == SIM_WAIT_FOR_ATR)
+ {
+ TS = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+
+ if ((TS == 0x003f) || (TS == 0x003b))
+ {
+ SimCard->State = SIM_PROCESS_ATR;
+
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) |=
+ // (SIM_CONF_TXHSK | SIM_CONF_RXHSK |SIM_CONF_TOUTEN);
+#if defined (__SIM_ATRSTA_BIT_SHIFT__)
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK | SIM_CONF_RXHSK | SIM_CONF_TOUTEN | SIM_CONF_RSTCTL));
+#else
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK | SIM_CONF_RXHSK | SIM_CONF_TOUTEN));
+#endif
+ /* *(volatile kal_uint16 *)SIM_CONF |= SIM_CONF_TOUTEN; */
+ SIM_SetRXTIDE(12, hw_cb);
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ SimCard->recData[0] = TS;
+ SimCard->recDataLen = 1;
+
+ //[Bernie][Logic Diff]: WR8 not send event?
+ //Begin Logic Diff
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);
+ SimCard->EvtFlag = ATR_END;
+ // End Logic Diff
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_Normal);
+ }
+ else
+ {
+ SimCard->EvtFlag = ATR_END;
+ SIM_SetEvent_MT6306(SimCard, SIM_TS_INVALID, hw_cb);
+ }
+ return;
+ }
+
+ if (SimCard->State == SIM_PROCESS_ATR)
+ {
+ while (1)
+ {
+ if (SIM_FIFO_GetLev())
+ {
+ if (40 <= SimCard->recDataLen)
+ {
+ sim_addMsg(0x20080213, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK));
+#ifdef SIM_REMOVE_ATR_ASSERT
+ SIM_StartFaltalReport(hw_cb);
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDRECERR, hw_cb);
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__, 0, SimCard->State, SimCard->result, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+
+ return;
+#else
+ SIM_DEBUG_ASSERT(0);
+#endif
+ }
+ SimCard->recData[SimCard->recDataLen] = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ SimCard->recDataLen++;
+ }
+ else
+ {
+ if (sim_int & SIM_STS_TOUT)
+ {
+ //[Bernie][Logic Diff]: mtk_0 send event only when tout
+ ////Begin Logic Diff
+ SimCard->EvtFlag = ATR_END;
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);
+ ////End Logic Diff
+ }
+ /* Following lines from WR8
+ SimCard->EvtFlag = ATR_END;
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);*/
+ break;
+ }
+ }
+ return;
+ }
+
+ if (SimCard->State == SIM_PROCESS_PTS)
+ {
+ index = 0;
+ while (KAL_TRUE)
+ {
+ kal_uint8 ch;
+
+ ch = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+
+ if (index < PPS_LEN)
+ {
+ /* to avoid overflow other members of SimCard_cb */
+ SimCard->PTS_data[index] = ch;
+ }
+
+ index++;
+
+ if (SIM_FIFO_GetLev() == 0)
+ {
+ if (index > PPS_LEN)
+ {
+ /* received too many data when processing PTS */
+ sim_addMsg(0x20140415, index, SimCard->recDataErr, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK));
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "Too many PTS:%d", index);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+ }
+ if (SimCard->recDataErr == KAL_FALSE)
+ {
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);
+ }
+ else
+ {
+ /* SetEvent should be called when handling TOUT */
+ }
+ break;
+ }
+ }
+ SIM_DisAllIntr();
+ return;
+ }
+
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+#ifdef SIM_ADDDMA
+ ////dbg_print("something error\r\n");
+#else /*SIM_ADDDMA*/
+#ifdef NoT0CTRL
+ {
+ kal_uint16 ACK;
+ while (SIM_FIFO_GetLev())
+ {
+ if (SimCard->cmdState == SIM_WaitProcByte)
+ {
+ ACK = SIM_Reg(SIM_DATA);
+ if ((ACK == SimCard->INS) || (ACK == (SimCard->INS + 1))) //ACK
+ {
+ if (SimCard->txsize != 5)
+ {
+ /*Trx command*/
+ SIM_WriteReg(SIM_DATA, * (SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ SIM_SetTXTIDE(0);
+ SIM_WriteReg(SIM_IRQEN, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ SimCard->cmdState = SIM_AckDataState;
+ return;
+ }
+ else
+ {
+ SIM_SetTXTIDE(0xffff);
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ SimCard->cmdState = SIM_AckDataState;
+ continue;
+ }
+ }
+
+ if ((ACK == (~SimCard->INS & 0x00ff)) || (ACK == (~(SimCard->INS + 1) & 0x00ff))) ///NACK
+ {
+ if (SimCard->txsize != 5)
+ {
+ SIM_WriteReg(SIM_DATA, * (SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ SIM_SetRXTIDE(1);
+ SimCard->cmdState = SIM_WaitProcByte;
+ /*Trx command*/
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ return;
+ }
+ else
+ {
+ SIM_SetTXTIDE(0xffff);
+ SimCard->cmdState = SIM_NAckDataState;
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ }
+ continue;
+ }
+
+ if (ACK == 0x60) //ACK
+ {
+ continue;
+ }
+ if (SIM_CheckSW(ACK)) //ACK
+ {
+ SimCard->SW1 = (kal_uint8)ACK;
+ SIM_SetRXTIDE(1);
+ SimCard->recDataLen++;
+ SimCard->cmdState = SIM_WaitSWByte;
+ continue;
+ }
+ }
+
+ if (SimCard->cmdState == SIM_WaitSWByte)
+ {
+ SimCard->SW2 = (kal_uint8)SIM_Reg(SIM_DATA);
+ /*SimCard->recDataLen++;*/
+ SimCard->recDataLen--;
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);
+ return;
+ }
+
+ if (SimCard->cmdState == SIM_AckDataState)
+ {
+ * (SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg(SIM_DATA);
+ SimCard->recDataLen++;
+ if (SimCard->recsize == SimCard->recDataLen)
+ {
+ SimCard->cmdState = SIM_WaitProcByte;
+ }
+ continue;
+ }
+
+ if (SimCard->cmdState == SIM_NAckDataState)
+ {
+ * (SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg(SIM_DATA);
+ SimCard->recDataLen++;
+ SimCard->cmdState = SIM_WaitProcByte;
+ continue;
+ }
+ } /*while(SIM_FIFO_GetLev())*/
+ if (SimCard->txsize == 5)
+ {
+ if ((SimCard->recsize + 2 - SimCard->recDataLen) > 15)
+ {
+ SIM_SetRXTIDE(CMD_RECBUFSIZE - 8);
+ }
+ else
+ {
+ SIM_SetRXTIDE(SimCard->recsize + 2 - SimCard->recDataLen);
+ }
+
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ }
+ }
+#else /*NoT0CTRL*/
+ while (SIM_FIFO_GetLev())
+ {
+ * (SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ SimCard->recDataLen++;
+ }
+#endif /*NoT0CTRL*/
+#endif /*SIM_ADDDMA*/
+ return;
+ }
+}
+
+static kal_bool recordHISR;
+static void sim_gpt_timeout_handler(void *parameter)
+{
+ sim_HW_cb *hw_cb;
+ Sim_Card * SimCard;
+
+ hw_cb = (sim_HW_cb *)parameter;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC45, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+
+ SIM_SetEvent_MT6306(SimCard, SIM_GPT_TIMEOUT, hw_cb);
+}
+
+void SIM_WaitEvent_MT6306(Sim_Card *SIMCARD, kal_uint32 flag, kal_bool unmaskSIMIntr, sim_HW_cb *hw_cb)
+{
+ kal_uint32 event_group = 0;
+ kal_status returnValue = 0;
+ sim_MT6306_switchInfo *switch_CB = NULL;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+// extern static void sim_dump_error_line(sim_HW_cb *hw_cb);
+ returnValue = returnValue;
+ DRV_GET_RET_ADDR(retAddr);
+ sim_addMsg(0x12345679, flag, SIMCARD->result, (kal_uint32)retAddr);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ SIMCARD->event_state = KAL_TRUE;
+ SIMCARD->EvtFlag = flag;
+ switch_CB->sim_workingTaskWaiting = KAL_TRUE;
+ if (KAL_TRUE == unmaskSIMIntr)
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ DRV_ICC_GPTI_StartItem(SIMCARD->gpt_handle,
+ USIM_GPT_TIMEOUT_PERIOD,
+ sim_gpt_timeout_handler,
+ hw_cb);
+
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ {
+ returnValue = kal_retrieve_eg_events(SIMCARD->event, flag, KAL_OR_CONSUME, &event_group, KAL_SUSPEND);
+ }
+ else
+ {
+ returnValue = kal_retrieve_eg_events(SIMCARD->event, flag, KAL_OR_CONSUME, &event_group, 0);
+ }
+ switch_CB->sim_workingTaskWaiting = KAL_FALSE;
+ sim_dump_error_line(hw_cb);
+ if (SIMCARD->result != SIM_GPT_TIMEOUT)
+ DRV_ICC_GPTI_StopItem(SIMCARD->gpt_handle);
+}
+
+void SIM_SetEvent_MT6306(Sim_Card *SIMCARD, kal_uint8 result, sim_HW_cb *hw_cb)
+{
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+ DRV_GET_RET_ADDR(retAddr);
+ sim_addMsg(0x12345678, SIMCARD->EvtFlag, drv_get_current_time(), (kal_uint32)retAddr);
+ DRV_ICC_GPTI_StopItem(SIMCARD->gpt_handle);
+ SIMCARD->result = result;
+ SIMCARD->event_state = KAL_FALSE;
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);
+ MO_Sync();
+
+ if (0 == SIMCARD->EvtFlag)
+ kal_set_eg_events(SIMCARD->event, SIM_EVT_CMD_END, KAL_OR);
+ else
+ kal_set_eg_events(SIMCARD->event, SIMCARD->EvtFlag, KAL_OR);
+
+}
+
+void SIM_Reject_MT6306(sim_HW_cb *hw_cb)
+{
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+ Sim_Card *SimCard;
+
+ DRV_GET_RET_ADDR(retAddr);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ sim_addMsg(0x1234567A, SimCard->EvtFlag, drv_get_current_time(), (kal_uint32)retAddr);
+
+ SIM_DisAllIntr();
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)
+ {
+ sim_addMsg(SIM_MT6306_DRIVER_DEACT, hw_cb->simInterface, 2, 0);
+ SimCard->State = SIM_PWROFF;
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);
+ SIM_FIFO_Flush();
+ /* [MAUI_03053369][1] Assert Fail: icc_switchControl2_mt6306.c 1502 -SIM*/
+ if (KAL_FALSE == sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);
+ sim_MT6306_VCCCtrl(hw_cb, 0);
+ }
+ else
+ {
+ sim_MT6306_manualDeactive(hw_cb);
+ }
+ }
+ else
+ {
+ //sim_PDNEnable_MT6306(hw_cb);
+ if (SimCard->reject_set_event)
+ SIM_SetEvent_MT6306(SimCard, SIM_NOREADY, hw_cb);
+ }
+ /* Do clean up */
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, 0x0);
+ SIM_FIFO_Flush();
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, 0xFFFF);
+}
+
+void SIM_HISR_MT6306_Common(sim_HW_cb *hw_cb, kal_uint32 sim_int)
+{
+ Sim_Card *SimCard;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ hw_cb->waitISR = 1;
+ Data_Sync_Barrier();
+
+#if defined(ATEST_DRV_ENABLE)
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%x]SIM_int:%x IRQEN:%x\n\r", hw_cb->simInterface, sim_int, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_HISR,hw_cb->simInterface, sim_int, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+#endif
+
+
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, sim_int);
+#if defined(__SIM_DRV_ENABLE_SWRST__)
+ if (sim_int & SIM_STS_SWRST)
+ {
+ SIM_SetEvent_MT6306(SimCard, SIM_SWRST, hw_cb);
+ }
+#endif
+
+ if (SimCard->previous_state == SIM_WAIT_FOR_ATR || SimCard->previous_state == SIM_PROCESS_ATR)
+ {
+ SimCard->previous_state = SimCard->State;
+ SimCard->atr_count++;
+ if (SimCard->atr_count > 40)
+ {
+ SIM_DisAllIntr();
+ SIM_Reject_MT6306(hw_cb);
+ SimCard->atr_count = 0;
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ DRV_ICC_print_str("[SIM DRV]SIM card send too many ATR data\n\r");
+ hw_cb->waitISR = 0;
+ Data_Sync_Barrier();
+ return;
+ }
+ }
+ else
+ {
+ SimCard->previous_state = SimCard->State;
+ SimCard->atr_count = 0;
+ }
+
+
+ if (sim_int & SIM_STS_TXERR)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "SIM_STS_TXERR");
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SimCard->State = SIM_SERIOUSERR;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x7, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_DisAllIntr();
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else
+ {
+ /* PTS TX err */
+ //SIM_Reject_MT6306(hw_cb);
+ SIM_SetEvent_MT6306(SimCard, SIM_INIPTSERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if (sim_int & SIM_STS_TX)
+ {
+ ////dbg_print("SIM_STS_TX\r\n");
+ //SIM_DisIntr(SIM_IRQEN_TX);
+#ifdef SIM_ADDDMA
+ ////dbg_print("something error\r\n");
+#else /*SIM_ADDDMA*/
+ SIM_Txhandler(hw_cb); /* Only used for no DMA */
+#endif /*SIM_ADDDMA*/
+ }
+
+ if (sim_int & SIM_STS_TOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x8, SimCard->State, drv_get_current_time(), SimCard->cmdState, hw_cb->simInterface);
+ ////dbg_print("703SIM_STS_TOUT\r\n");
+ if (SimCard->State == SIM_WAIT_FOR_ATR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC54, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SimCard->EvtFlag = ATR_END;
+ SIM_SetEvent_MT6306(SimCard, SIM_RX_INVALID, hw_cb);
+ SIM_ASSERT(0);
+ }
+
+ if (SimCard->State == SIM_PROCESS_ATR)
+ {
+ SIM_Rxhandler(sim_int, hw_cb);
+ }
+
+ if (SimCard->State == SIM_PROCESS_PTS)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC55, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MT6306(SimCard, SIM_INIPTSERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC56, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SimCard->EvtFlag, hw_cb->simInterface, SimCard->result, SimCard->recDataErr, __LINE__);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SIM_Reg(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDCTRRx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDC0Rx), 0, 0);
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else
+ {
+ switch (SimCard->cmdState)
+ {
+ case SIM_ProcessClk:
+ SimCard->EvtFlag = CLK_PROC;
+ SIM_SetEvent_MT6306(SimCard, SIM_CLKPROC, hw_cb);
+ break;
+
+ case SIM_StopClk:
+ /*in Gemini project, we can't use HISR to stop clk*/
+ SIM_DEBUG_ASSERT(0);
+ break;
+
+ default: /*normal command case*/
+#ifdef NoT0CTRL
+ if (SimCard->cmdState == SIM_WaitProcByte)
+ {
+ kal_uint8 ACK;
+ kal_uint8 Error;
+ Error = KAL_TRUE;
+ while (SIM_FIFO_GetLev())
+ {
+ ACK = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ if (ACK == 0x60) //NULL
+ {
+ continue;
+ }
+ if (SIM_CheckSW(ACK)) //ACK
+ {
+ SimCard->SW1 = ACK;
+ SimCard->SW2 = (kal_uint8)SIM_Reg(SIM_DATA);
+ SIM_SetEvent_MT6306(SimCard, SIM_SUCCESS, hw_cb);
+ Error = KAL_FALSE;
+ }
+ else
+ {
+ break;
+ }
+ }
+ if (Error)
+ {
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDTOUT, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x9, 1, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDTOUT, hw_cb);
+ SIM_ASSERT(0);
+ }
+#else /*NoT0CTRL*/
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->simMagic1 ++;
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x9, 0, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_ASSERT(0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDTOUT, hw_cb);
+#endif /*NoT0CTRL*/
+ break;
+ }/*endof switch*/
+ }
+ }/*if (SimCard->State == SIM_PROCESSCMD)*/
+
+ if (SimCard->State == SIM_SERIOUSERR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC57, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDTXERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ SIM_DisAllIntr();
+ }
+
+ if (sim_int & SIM_STS_RX)
+ {
+ ////dbg_print("SIM_STS_RX\r\n");
+ if (SimCard->timeout != KAL_TRUE)
+ SIM_Rxhandler(sim_int, hw_cb);
+ }
+
+ if (sim_int & SIM_STS_OV)
+ {
+ DRV_ICC_print_str("[DRV] SIM_STS_OV\r\n");
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC56, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SimCard->EvtFlag, hw_cb->simInterface, SimCard->result, SimCard->recDataErr, __LINE__);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SIM_Reg(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDCTRRx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDC0Rx), 0, 0);
+#endif
+ SimCard->recDataErr = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x4, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetTOUT(0x4, hw_cb); // set TOUT ASAP
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if (sim_int & SIM_STS_RXERR)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "SIM_STS_RXERR");
+ SimCard->recDataErr = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x6, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetTOUT(0x4, hw_cb); // set TOUT ASAP
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MT6306(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if ((sim_int & SIM_IRQEN_T0END)
+ && (SimCard->State == SIM_PROCESSCMD))
+ {
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->simMagic1 ++;
+#endif
+
+ ////dbg_print("SIM_IRQEN_T0END\r\n");
+ SIM_Cmdhandler(hw_cb);
+ SIM_DisAllIntr();
+ }
+
+ if (sim_int & SIM_STS_NATR && (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK) & SIM_IRQEN_NATR))
+ {
+
+ DRV_ICC_print_err_msg(hw_cb, "No ATR");
+ SIM_DisAllIntr();
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, SimCard->SIM_ENV, SimCard->Power, SimCard->Data_format, 0, 0x1014);
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+
+ SIM_SetEvent_MT6306(SimCard, SIM_NO_ATR, hw_cb);
+ }
+
+ if (sim_int & SIM_STS_SIMOFF)
+ {
+ SimCard->EvtFlag = DEACTIVATE_DONE;
+ /* [MAUI_03037644] FTA test fail because result should set as SIM_NOREADY */
+ SIM_SetEvent_MT6306(SimCard, SIM_NOREADY, hw_cb);
+ }
+ hw_cb->waitISR = 0;
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ Data_Sync_Barrier();
+
+}
+
+void SIM_HISR_MT6306(void)
+{
+ kal_uint16 sim_int;
+ //Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(0));
+ //SimCard = GET_SIM_CB(hw_cb->simInterface);
+ sim_int = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+
+
+#if defined(__SIM_DRV_TRACE__)
+#ifndef __MAUI_BASIC__
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL0, __LINE__,
+ sim_int, drv_get_current_time(), SimCard->State, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), 0);
+#endif
+#endif
+ if (recordHISR)
+ sim_addMsg(SIM_MT6306_CLKSTART_HISR, hw_cb->simInterface, sim_int, 0);
+ SIM_HISR_MT6306_Common(hw_cb, sim_int);
+}
+
+
+void SIM_HISR2_MT6306(void)
+{
+ kal_uint16 sim_int;
+ //Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(1));
+ //SimCard = GET_SIM_CB(hw_cb->simInterface);
+ sim_int = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+#if defined(__SIM_DRV_TRACE__)
+#ifndef __MAUI_BASIC__
+#if !defined(__L1_STANDALONE__)
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL0, __LINE__,
+ sim_int, drv_get_current_time(), SimCard->State, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), 0);
+#endif
+#endif
+#endif
+ if (recordHISR)
+ sim_addMsg(SIM_MT6306_CLKSTART_HISR2, hw_cb->simInterface, sim_int, 0);
+ SIM_HISR_MT6306_Common(hw_cb, sim_int);
+}
+
+void SIM_LISR_MT6306(kal_uint32 vector)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(0));
+ IRQMask(hw_cb->mtk_lisrCode);
+ //drv_active_hisr(DRV_SIM_HISR_ID);
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(SIM_HISR);
+#else
+ kal_activate_hisr(sim_hisrid);
+#endif
+}
+
+void SIM_LISR2_MT6306(kal_uint32 vector)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(1)]);
+ IRQMask(hw_cb->mtk_lisrCode);
+ //drv_active_hisr(DRV_SIM2_HISR_ID);
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(SIM2_HISR);
+#else
+ kal_activate_hisr(sim2_hisrid);
+#endif
+
+}
+
+#if 1
+//==========================SIM adaption=============================
+/*
+* FUNCTION
+* L1sim_PowerOff
+*
+* DESCRIPTION
+* The function requests the driver to deactivate SIM
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void sim_PowerOff_MT6306(sim_HW_cb *hw_cb) //Validate
+{
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, 0, 0, drv_get_current_time(), 0, hw_cb->simInterface);
+
+ SIM_DisAllIntr();
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ SIM_icusb_disableSession(hw_cb);
+ sim_addMsg(0xE014, hw_cb->simInterface, 0, 0);
+ }
+#endif
+
+ /*
+ sim_PDNDisable_MT6306(hw_cb);
+ if(SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_HALT)
+ {
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);
+ }*/
+ SimCard->reject_set_event = KAL_FALSE;
+
+ SIM_L1Reset(hw_cb, KAL_FALSE);
+ /* [MAUI_03053369][1] Assert Fail: icc_switchControl2_mt6306.c 1502 -SIM*/
+ /* check if pdn need to enable */
+
+
+ //sim_PDNEnable_MT6306(hw_cb);
+
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ //tell USB to reset MAC & PHY
+ SIM_icusb_disconnectDone(hw_cb);
+ sim_addMsg(0xE015, hw_cb->simInterface, 0, 0);
+ SIM_icusb_deinit(hw_cb);
+ }
+#endif
+
+}
+
+/*
+* FUNCTION
+* L1sim_Reset
+*
+* DESCRIPTION
+* The function L1sim_Reset is used to reset SIM by specific voltage
+*
+* CALLS
+*
+* PARAMETERS
+* resetVolt: Request the driver to reset SIM at voltage resetVolt
+* resultVolt: The pointer to the voltage after the driver reset SIM.
+* (RESET_3V,RESET_5V)
+* Info: The pointer to buffer of ATR data returned from SIM
+*
+* RETURNS
+* SIM_NO_ERROR No SIM error
+* SIM_NO_INSERT No SIM inserted
+* SIM_CARD_ERROR SIM fatal error
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+static kal_uint8 L1sim_Core_Reset(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info, sim_HW_cb *hw_cb) //Validate
+{
+ kal_uint8 index = 0;
+ Sim_Card *SimCard = NULL;
+ usim_dcb_struct *usim_dcb = NULL;
+ kal_bool returnBool = 0;
+ sim_MT6306_switchInfo *switch_CB = NULL;
+ switch_CB = switch_CB;
+ index = index;
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ kal_sleep_task(2);
+ SIM_DisAllIntr();
+ SimCard->sim_card_speed = sim_card_normal_speed;
+ SimCard->reject_set_event = KAL_TRUE;
+ //sim_PDNDisable_MT6306(hw_cb);
+
+
+ /*
+ SIM_DEFAULT_TOUT_VALUE is 0x260 in ../inc/sim_drv_HW_def_MTK.h
+ It has been divide by 16
+ */
+ SimCard->TOUTValue = SIM_DEFAULT_TOUT_VALUE << 2;
+
+
+ SimCard->TOUT_Factor = 1;
+ SimCard->clkStop = KAL_FALSE;
+ SimCard->Speed = Speed372;
+ SimCard->State = SIM_WAIT_FOR_ATR;
+ SimCard->Power = resetVolt;
+ SimCard->initialPower = resetVolt;
+ SimCard->power_class = UNKNOWN_POWER_CLASS;
+ SimCard->TC2Present = KAL_FALSE;
+ SimCard->timeout = KAL_FALSE;
+// SimCard->gpt_handle = usim_dcb->gpt_handle;
+ SimCard->previous_state = 0;
+ SimCard->atr_count = 0;
+#if defined(SIM_DRV_IC_USB)
+ SimCard->isIcUsb = usim_dcb->isIcUsb;
+ SimCard->TB15 = usim_dcb->TB15;
+ SimCard->isIcUsbRecPPS = usim_dcb->isIcUsbRecPPS;
+ SimCard->uart_sim_ccci_handle = usim_dcb->uart_sim_ccci_handle;
+#endif
+
+#if defined(__USIM_DRV__)
+ {
+ SimCard->Data_format = usim_dcb->dir;
+ SimCard->result = SIM_SUCCESS;
+ SimCard->sim_ATR_fail = KAL_FALSE;
+ SimCard->power_class = usim_dcb->power_class;
+
+ }
+#else
+ SimCard->Data_format = SIM_direct;
+ reset_index = 0;
+ SimCard->result = SIM_NOREADY;
+ SIM_L1Reset();
+
+ SIM_WaitEvent_MT6306(SimCard, RST_READY, KAL_FALSE, hw_cb);
+
+ if (SimCard->result == SIM_NOREADY)
+ {
+ //L1sim_PowerOff();
+ return SIM_NO_INSERT;
+ }
+
+ if (SimCard->result == SIM_CARDERR)
+ {
+ if (SimCard->Power == SIM_30V)
+ {
+ SimCard->Power = SIM_18V;
+ SIM_L1Reset();
+ }
+ else
+ {
+ SimCard->Power = SIM_30V;
+ SIM_L1Reset();
+ }
+ SIM_WaitEvent_MT6306(SimCard, RST_READY, KAL_FALSE, hw_cb);
+ }
+
+#endif
+
+ if (SimCard->result == SIM_SUCCESS)
+ {
+ index = 0;
+ while (1)
+ {
+ if (!SIM_ProcessATRData(hw_cb))
+ {
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+ DRV_ICC_print_err_msg(hw_cb, "Bad card/Hw contact issue, cause PTS error. Enter recovery process\n\r");
+ index++;
+ //if (index == 3)
+ if (index == 2)
+ {
+ SimCard->PTS_check = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC59, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ }
+ //else if (index > 3)
+ else if (index > 2 || KAL_TRUE == SimCard->keepAtrFatal)
+ {
+ SimCard->PTS_check = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC60, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ sim_PowerOff_MT6306(hw_cb);
+
+ return SIM_CARD_ERROR;
+ }
+#ifdef DRV_SIM_RETRY_18V_ONLY_USIM_ON_PTS_ERROR
+ else if ((SimCard->Power == SIM_18V) && SimCard->power_class == CLASS_C_18V)
+ {
+ DRV_ICC_print_str("RETRY_18V_ONLY_USIM\n\r");
+ SimCard->PTS_check = KAL_TRUE;
+ SimCard->SIM_ENV = ME_18V_ONLY;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC61, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ //index = 0;
+ }
+#endif
+#ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+ /* For [MAUI_01321659] begin, retry 3V when we fail in 1.8V */
+ else if ((SimCard->Power == SIM_18V) && (SIM_GetCurrentEnv(hw_cb->simInterface) == ME_18V_30V))
+ {
+ DRV_ICC_print_str("RETRY_3V_ON_PTS_ERROR\n\r");
+ SimCard->Power = SIM_30V;
+ SimCard->PTS_check = KAL_TRUE;
+ //index = 0;
+ }/* For [MAUI_01321659] end */
+#endif // #ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+
+#if defined(__USIM_DRV__)
+ SimCard->sim_ATR_fail = KAL_TRUE;
+#endif
+
+ /*since we may power off the card and set SIM pdn, we have to disable PDN here, or we may trapped in wait event*/
+ //sim_PDNDisable_MT6306(hw_cb);
+
+#ifdef DRV_SIM_RETRY_VOLTAGE_ON_PPS_TIMEOUT
+ if (index == 2)
+ {
+ if (SimCard->SIM_ENV == ME_18V_30V)
+ {
+ if (SimCard->Power == SIM_30V)
+ {
+ SimCard->Power = SIM_18V;
+ }
+ else
+ {
+ SimCard->Power = SIM_30V;
+ }
+ }
+ }
+#endif
+
+ returnBool = SIM_ResetNoATR(SimCard->Power, hw_cb);
+ if (KAL_TRUE != returnBool)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_NOATR_FAIL, SimCard->Power, index, 0, 0, 0);
+ return SIM_CARD_ERROR;
+ }
+ }
+ else
+ {
+ if (resultVolt != NULL)
+ {
+ *resultVolt = SimCard->Power;
+ }
+ if (Info != NULL)
+ {
+ for (index = 0; index < SimCard->recDataLen; index++)
+ {
+ Info->info[index] = SimCard->recData[index];
+ }
+ }
+ return SIM_NO_ERROR;
+ }
+ }
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC62, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ sim_PowerOff_MT6306(hw_cb);
+ return SIM_CARD_ERROR;
+ }
+}
+
+kal_uint8 sim_Reset_MT6306(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info, sim_HW_cb *hw_cb) //Validate
+{
+ kal_uint8 result;
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->TS_HSK_ENABLE = KAL_TRUE;
+ result = L1sim_Core_Reset(resetVolt, resultVolt, Info, hw_cb);
+ if (result != SIM_NO_ERROR && KAL_FALSE == SimCard->keepAtrFatal)
+ {
+ //dbg_print("[SIM]: SIM reset fail with TS_HSK_ENABLE");
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_FAIL_WITH_TS_HSK_ENABLE, 0, 0, 0, 0, 0);
+ SimCard->TS_HSK_ENABLE = KAL_FALSE;
+ ////[Bernie][Logic Diff]: mtk_0 doesn't call SIM_Initialize()
+ //no atr, give VSIM power again
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+ result = L1sim_Core_Reset(resetVolt, resultVolt, Info, hw_cb);
+ }
+ if (result == SIM_NO_ERROR)
+ {
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkRunning);
+ //kal_sprintf(hw_cb->dbgStr,"[SIM]:SIM RESET OK, power:%d ,speed:%d",SimCard->Power,SimCard->Speed);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_OK_POWER_SPEED, SimCard->Power, SimCard->Speed, 0, 0, 0);
+ }
+ else
+ {
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateDeactiavate);
+ //kal_sprintf(hw_cb->dbgStr,"[SIM]:SIM RESET FAIL, result:%d", result);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_FAIL_RESULT, result, 0, 0, 0, 0);
+ }
+ return result;
+}
+
+
+
+/*
+* FUNCTION
+* L1sim_Configure
+*
+* DESCRIPTION
+* The function indicates clock mode when idle.
+*
+* CALLS
+*
+* PARAMETERS
+* clockMode: The clockMode defines the clock mode when idle.
+* CLOCK_STOP_AT_HIGH,CLOCK_STOP_AT_LOW,CLOCK_STOP_NOT_ALLOW
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void L1sim_Configure_MT6306(kal_uint8 clockMode, sim_HW_cb *hw_cb) //Validate
+{
+ Sim_Card *SimCard;
+ kal_uint32 t1 = 0, log_size = 0;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "[%s], mode:%d, Interface:%d", __func__, clockMode, hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ switch (clockMode)
+ {
+ case CLOCK_STOP_AT_HIGH:
+ // #if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) |= SIM_CONF_HALTEN;
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN);
+#endif /*MT6205,MT6205B,MT6218*/
+ SimCard->clkStop = KAL_TRUE;
+ SimCard->clkStopLevel = KAL_TRUE;
+ break;
+
+ case CLOCK_STOP_AT_LOW:
+ //#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) |= SIM_CONF_HALTEN;
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN);
+#endif /*MT6205,MT6205B,MT6218*/
+ SimCard->clkStop = KAL_TRUE;
+ SimCard->clkStopLevel = KAL_FALSE;
+ break;
+
+ case CLOCK_STOP_NOT_ALLOW:
+ //#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) &= ~SIM_CONF_HALTEN;
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN);
+#endif /*MT6205,MT6205B,MT6218*/
+ SimCard->clkStop = KAL_FALSE;
+ break;
+ default:
+ break;
+ }
+ if (clockMode != CLOCK_STOP_NOT_ALLOW)
+ {
+ t1 = SIM_GetCurrentTime();
+ while ((SIM_GetCurrentTime() - t1) < 20); // delay 600 clock cycles (600us)
+ //sim_MT6306_clkStopper(hw_cb);
+ }
+}
+void sim_dump_MT6306(sim_HW_cb * hw_cb)
+{
+ sim_MT6306_switchInfo *switch_CB;
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ kal_uint8 index = 0;
+ kal_uint8 readVal[4] = {0};
+ kal_uint8 gpio_mode[4] = {0, 0, 0, 0};
+ kal_uint32 log_size = 0;
+
+ for (index = 0; index < 4; index++)
+ {
+ readVal[index] = sim_MT6306_SPIRead(switch_CB, index);
+ }
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] Interface:%d, %x, %x, %x, %x, %x", __func__, hw_cb->simInterface, readVal[0], readVal[1], readVal[2], readVal[3], sim_MT6306_SPIRead(switch_CB, 8));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ for (index = 0x08; index < 0x1E; index++)
+ {
+ kal_uint8 readValue = sim_MT6306_SPIRead(switch_CB, index);
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] Interface:%d, %x:%x", __func__, hw_cb->simInterface, index, readValue);
+ if (readValue != 0xFF && log_size > 0)
+ DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ MT6306_Get_GPIO_Mode(gpio_mode);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] Interface:%d, GPIOMODE:%x, %x, DIR:%x,%x", __func__, hw_cb->simInterface, gpio_mode[0], gpio_mode[1], gpio_mode[2], gpio_mode[3]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+}
+#ifdef SIM_NULLBYTE_ISSUE
+/*in MT6306 solution, there is only one task to access card in the same time, so we don't need the interface parameter*/
+void sim_nullByteIssueGptTimeoutMT6306(void *parameter)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+ sim_MT6306_switchInfo *switch_CB;
+ kal_uint32 log_size = 0;
+
+ hw_cb = (sim_HW_cb *)parameter;
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ if (switch_CB->nullByteGPTServingInterface != switch_CB->sim_waitHisrCb_MT6306->simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (switch_CB->sim_waitHisrCb_MT6306 != hw_cb)
+ SIM_DEBUG_ASSERT(0);
+
+ if (switch_CB->nullByteGPTServingInterface != hw_cb->simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ extern volatile kal_uint32 timeout_handler_start[];
+ timeout_handler_start[0] = 0;
+ timeout_handler_start[1] = 0;
+ timeout_handler_start[2] = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ /* [ALPS00600930]we should stop wait event gpt timer;otherwise it will cause null byte process fail */
+ DRV_ICC_GPTI_StopItem(SimCard->gpt_handle);
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+
+ /* [MAUI_03009364]If card is removed, we don't need to wait null bytes */
+ if (hw_cb->IsCardRemove == KAL_TRUE)
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+ /*must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger*/
+ SimCard->simMagic1 ++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ switch_CB->nullByteGPTServingInterface = hw_cb->simInterface;
+ return;
+ }
+#endif
+ if (SimCard->simMagic1 != SimCard->simMagic2) /*cmd finished before GPT timeout*/
+ {
+ DRV_ICC_print_str("sim_nullByteIssueGptTimeout_0:cmd finished before GPT timeout");
+ }
+ else /*the GPT timer is used to find out these cases, it means we still haven't complete the CMD for so long duration*/
+ {
+
+ /*it means the last byte received is null byte, we wait for 5 consecutive null byte noticed before ending the CMD*/
+ kal_uint8 SW1 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK);
+ if (0x60 == SW1)
+ {
+ SimCard->sim_nullByteIssueNullCount ++;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] : null timeout %d\n\r", hw_cb->simInterface, SimCard->sim_nullByteIssueNullCount);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_NULL_TOUT,hw_cb->simInterface, SimCard->sim_nullByteIssueNullCount);
+#endif
+
+ if (38 < SimCard->sim_nullByteIssueNullCount)
+ {
+ /*we have receive 5 null byte*/
+ SIM_DisAllIntr();
+ //DRV_ICC_print(hw_cb, SIM_PRINT_NULL_TIME_OUT, hw_cb->simInterface, 0, 0, 0, 0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MT6306(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else
+ {
+ /*polling status every 3 sec*/
+ if (msg_get_task_extq_messages(SimCard->mod_id) > SimCard->mod_extq_cap - 5)
+ {
+ SIM_DisAllIntr();
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM:%d] : extq num:%d\n\r", __LINE__, msg_get_task_extq_messages(SimCard->mod_id));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ //DRV_ICC_print(SIM_PRINT_NULL_TIME_OUT, hw_cb->simInterface, 0, 0, 0, 0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MT6306(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else if (OSTD_Infinite_Sleep_Query() == KAL_FALSE) //No EPOF
+ {
+ /*polling status every 1 sec*/
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 100, sim_nullByteIssueGptTimeoutMT6306, parameter);
+ }
+ else
+ {
+ SIM_DisAllIntr();
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] Quit waiting null byte\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MT6306(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ }
+ }
+ else /*received is not null*/
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount ++;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] : non-null timeout %d\n\r", hw_cb->simInterface, SimCard->sim_nullByteIssuenonNullCount);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_NON_NULL_TOUT,hw_cb->simInterface, SimCard->sim_nullByteIssuenonNullCount);
+#endif
+
+ if (48 < SimCard->sim_nullByteIssuenonNullCount)
+ {
+ /*we have receive 84 non null byte*/
+ SIM_DisAllIntr();
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MT6306(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC66, SimCard->TOUTValue, drv_get_current_time(), 0, 0, 0);
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC66, hw_cb);
+ sim_dump_fifo(hw_cb);
+ if (SimCard->sim_nullByteIssuenonNullCount % 10 == 0)
+ sim_dump_MT6306(hw_cb);
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 100, sim_nullByteIssueGptTimeoutMT6306, parameter);
+ }
+ }
+
+ }
+}
+#endif
+
+
+
+/*
+* FUNCTION
+* SIM_CMD
+*
+* DESCRIPTION
+* The function is used to transmit coded command and
+* its following data to the driver.
+*
+* CALLS
+*
+* PARAMETERS
+* txData: Pointer to the transmitted command and data.
+* txSize: The size of the transmitted command and data from AL to driver.
+* expSize: The size of expected data from SIM
+* result: Pointer to received data
+* rcvSize: Pointer to the size of data received
+* parityError: 1 (parity error) or 0(no parity error)
+*
+* RETURNS
+* status(high byte:sw1 low byte: sw2)
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+
+//#define GEMINI_ORIGINAL_CLKSTART
+//#define GEMINI_CLKSTART2
+#define GEMINI_CLKSTART3
+#define GEMINI_NEW_DELAY
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+static kal_uint16 SIM_CMD(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error, sim_HW_cb *hw_cb)
+//kal_uint16 L1sim_Cmd(kal_uint8 *txData,kal_uint16 txSize,kal_uint8 expSize, kal_uint8 *result,kal_uint8 *rcvSize, kal_uint8 *Error)
+{
+ kal_uint16 SW = 0;
+ kal_uint8 index = 0;
+ kal_uint16 INS = 0;
+ kal_uint16 temp = 0;
+ kal_uint16 expSize = *rcvSize;
+ kal_bool txDelay = KAL_FALSE;
+#ifdef SIM_ADDDMA
+
+ kal_uint32 txaddr = 0;
+ kal_uint32 rxaddr = 0;
+#endif/*SIM_ADDDMA*/
+ Sim_Card *SimCard = NULL;
+ kal_uint32 clkStartTime1;
+ kal_uint32 delayIndex = 0;
+ //kal_uint32 clkStartTime1 = 0;
+ kal_uint16 temp_reg = 0;
+ kal_uint32 savedMask = 0;
+ sim_MT6306_switchInfo *switch_CB = NULL;
+ sim_MT6306_cardInfo *card_cb;
+ kal_uint32 hwCtrl;
+ kal_uint8 tmpsts;
+ temp = temp;
+ delayIndex = delayIndex;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ kal_uint32 log_size = 0;
+
+ // Special Case: AP issued case2 command with le < Lr (Real response data length), Then expsize should equal txData[4]
+ if (5 == txSize && 0 != txData[4])
+ {
+ expSize = txData[4];
+ }
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ *Error = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ SimCard->t_debug[2] = ust_get_current_time();
+
+ if (result == NULL && *rcvSize != 0)
+ {
+ *Error = KAL_TRUE;
+ return 0;
+ }
+ if (SimCard->State != SIM_PROCESSCMD)
+ {
+ *Error = KAL_TRUE;
+ return 0;
+ }
+
+#ifdef NoT0CTRL
+ if ((SimCard->cmdState != SIMD_CmdIdle) && (SimCard->cmdState != SIM_StopClk))
+ {
+ *Error = KAL_TRUE;
+ return 0;
+ }
+#endif /*NoT0CTRL*/
+
+#if !defined(ATEST_DRV_ENABLE)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *txData, *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ if (result == NULL)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, 0, drv_get_current_time(), SimCard->timeout);
+ else
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, (kal_uint32) result, drv_get_current_time(), SimCard->timeout);
+#endif
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *result, *(result + 1), *(result + 2), *(result + 3), *(result + 4));
+#endif // #if defined(SIM_DEBUG_INFO)
+
+ SIM_DisAllIntr();
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && SimCard->forceISO == KAL_FALSE)
+ {
+#if defined(SIM_DRV_IC_USB_DBG_2)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *txData, *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *(txData + 5), *(txData + 6), *(txData + 7), *(txData + 8), *(txData + 9));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, index, drv_get_current_time(), 0xaaaa);
+#endif
+ kal_set_eg_events(SimCard->event, 0, KAL_AND); //2: NU_AND
+ *Error = KAL_FALSE;
+ SimCard->recDataErr = KAL_FALSE;
+ SimCard->sim_icusb_T0cmd.txData = txData;
+ SimCard->sim_icusb_T0cmd.txSize = txSize;
+ SimCard->sim_icusb_T0cmd.result = result;
+ SimCard->sim_icusb_T0cmd.rcvSize = rcvSize;
+ SW = SIM_icusb_cmd(hw_cb);
+ if (SW == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE023, hw_cb->simInterface, 0, 0);
+ SW = 0x0000;
+ }
+#if defined(SIM_DRV_IC_USB_DBG)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC83, SimCard->icusb_state, SW, hw_cb->simInterface, SimCard->TB15, SimCard->isIcUsbRecPPS);
+#endif
+#if defined(SIM_DRV_IC_USB_DBG_2)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, index, drv_get_current_time(), 0xaaab);
+#endif
+ return SW;
+ }
+#endif
+
+ SIM_DisAllIntr();
+
+ if (0x3 == SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))
+ SIM_DEBUG_ASSERT(0);
+
+
+ if (SimCard->clkStop == KAL_TRUE)
+ {
+ if (switch_CB->sim_MT6306_needCLKStartTimeout) //This flag is set because we jsut pass the clock of MT6306.
+ {
+ switch_CB->sim_MT6306_needCLKStartTimeout = KAL_FALSE;
+ clkStartTime1 = drv_get_current_time();
+ sim_addMsg(0x20080216, clkStartTime1, 0, 0);
+ if (SimCard->Speed != Speed372)
+ {
+ temp_reg = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK);
+ temp_reg &= ~SIM_CONF_TOUTEN;
+
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), temp_reg);
+
+ if (5 <= SimCard->Speed ||
+ 0 == SimCard->TOUT_Factor
+ )
+ SIM_DEBUG_ASSERT(0);
+
+ while (12 > (drv_get_current_time() - clkStartTime1));
+
+ sim_addMsg(0x20080216, drv_get_current_time(), 0, 0);
+ /*
+ SIM_SetTOUT(ClkStopTimeTable[SimCard->Speed][0]* SimCard->TOUT_Factor, hw_cb);
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) |= SIM_CONF_TOUTEN;
+ SimCard->cmdState = SIM_ProcessClk;
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK,SIM_IRQEN_TOUT);
+ SIM_WaitEvent_MT6306(SimCard,CLK_PROC, KAL_FALSE, hw_cb);
+ */
+ }
+ }
+ else
+ {
+ }
+ }
+ sim_addMsg(SIM_MT6306_CLKSTART_END, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkRunning);
+ if (sim_MT6306_CLKPass != card_cb->pins.CLK)
+ SIM_DEBUG_ASSERT(0);
+
+ SIM_DisAllIntr();
+
+ if (SimCard->is_err && SimCard->Speed == Speed32) // to solve ROSSINI SIM issue
+ {
+ kal_uint32 t1;
+
+ t1 = SIM_GetCurrentTime();
+ while ((SIM_GetCurrentTime() - t1) < 5); // delay 500 clock cycles (152us)
+
+ }
+
+ /*check pdn bit and clk*/
+
+#if defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ /* SWRST SIM_CTRL[7] is also been set */
+ if (0x1 != (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON))
+ SIM_DEBUG_ASSERT(0);
+#else
+ if (0x1 != SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))
+ SIM_DEBUG_ASSERT(0);
+#endif
+
+ if (KAL_FALSE == switch_CB->sim_MT6306_taskAccessing)
+ SIM_DEBUG_ASSERT(0);
+ /*check pin state*/
+ if (((0x1 << hw_cb->simSwitchPortNo) == (switch_CB->sim_MT6306_regValue[0] & (0x5 << hw_cb->simSwitchPortNo))) && (sim_MT6306_cardTypeAL == card_cb->type))
+ SIM_DEBUG_ASSERT(0);
+ if ((0x1 << hw_cb->simSwitchPortNo) != (switch_CB->sim_MT6306_regValue[1] & (0x5 << hw_cb->simSwitchPortNo)))
+ SIM_DEBUG_ASSERT(0);
+ if ((0x1 << hw_cb->simSwitchPortNo) != (switch_CB->sim_MT6306_regValue[2] & (0x5 << hw_cb->simSwitchPortNo)))
+ SIM_DEBUG_ASSERT(0);
+ if ((0x4 << hw_cb->simSwitchPortNo) != (switch_CB->sim_MT6306_regValue[3] & (0x4 << hw_cb->simSwitchPortNo)))
+ SIM_DEBUG_ASSERT(0);
+ if (0x23 == (switch_CB->sim_MT6306_regValue[2]))
+ SIM_DEBUG_ASSERT(0);
+
+ //sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[1]);
+ //sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[2]);
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#ifndef __MAUI_BASIC__
+ if (0 != SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK))
+ {
+ /*we print index, */
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK)
+);
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+ }
+#endif
+
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN)
+ kal_set_eg_events(SimCard->event, 0, KAL_AND); //2: NU_AND
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+
+
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ SIM_FIFO_Flush();
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ // delay 100 clock cycles (30us) [MAUI_03431888]/[MAUI_03433590]
+ {
+ kal_uint32 t1;
+ t1 = drv_get_current_time();
+ while ((drv_get_current_time() - t1) < 1);
+ }
+ *Error = KAL_FALSE;
+ SimCard->recDataErr = KAL_FALSE;
+
+#ifdef SIM_ADDDMA
+ txaddr = (kal_uint32)txData;
+ rxaddr = (kal_uint32)result;
+#else /*SIM_ADDDMA*/
+ SimCard->txbuffer = txData;
+ SimCard->txsize = txSize;
+ SimCard->rxbuffer = result;
+ SimCard->recDataLen = 0;
+#ifdef NoT0CTRL
+ SimCard->recsize = expSize;
+ SimCard->txindex = 0;
+ SimCard->INS = * (txData + 1);
+#endif /*NoT0CTRL*/
+#endif/*SIM_ADDDMA*/
+
+#ifndef NoT0CTRL
+
+
+ INS = (kal_uint16) txData[1];
+ SIM_SetCOMDLEN(txData[4]);
+ SimCard->cmdState = SIM_WaitCmdEnd;
+#endif /*NoT0CTRL*/
+///////////////////////////////////////////////////////////////////////////////////
+#ifdef SIM_ADDDMA
+
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), 0, 0
+);
+
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif
+
+ savedMask = SaveAndSetIRQMask();
+ for (index = 0; index < 5; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, * (txData + index));
+ }
+ sim_addMsg(SIM_CMD_TX_LOG, * (txData + 1), * (txData + 4), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+ RestoreIRQMask(savedMask);
+
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), 0, 0
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif
+
+ SIM_SetRXTIDE(1, hw_cb); //set rxtide 0
+
+ if (expSize == 0)
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("SIM TX\n\r");
+#endif
+
+ SIM_SetTXTIDE(0, hw_cb);
+ //#if ( defined(MT6205) || defined(MT6205B) )
+
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)(txaddr + 5));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(0) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(txSize - 5) | HDCR_START0);
+
+ INS |= SIM_INS_INSD;
+
+ }
+ else
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("SIM RX\n\r");
+#endif
+
+ SIM_SetTXTIDE(0xffff, hw_cb);
+
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)(rxaddr));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(expSize) | HDCR_START0);
+
+ }
+
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+
+ while (hw_cb->waitISR)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for ISR:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, (kal_uint32) hw_cb->waitISR, drv_get_current_time());
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL);
+ }
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDDMANormal);
+
+#else /*SIM_ADDDMA*/
+#ifdef NoT0CTRL
+ for (index = 0; index < 5; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, * (txData + index));
+ }
+ SimCard->txindex = 5;
+ SimCard->cmdState = SIM_WaitProcByte;
+
+ if (expSize == 0) //Transmit
+ {
+ if (txSize == 5)
+ {
+ SIM_SetRXTIDE(2, hw_cb);
+ }
+ else
+ {
+ SIM_SetRXTIDE(1, hw_cb);
+ }
+ }
+ else
+ {
+ if ((expSize + 3) > 15)
+ {
+ SIM_SetRXTIDE(CMD_RECBUFSIZE - 8, hw_cb);
+ }
+ else
+ {
+ SIM_SetRXTIDE(expSize + 3, hw_cb);
+ }
+ }
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDNormal);
+#else /*NoT0CTRL*/
+
+ if (txSize <= 15)
+ {
+ for (index = 0; index < txSize; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, * (txData + index));
+ }
+ SimCard->txindex = txSize;
+
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDNormal);
+ }
+ else
+ {
+ for (index = 0; index < 15; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, * (txData + index));
+ }
+ SimCard->txindex = 15;
+ SIM_SetTXTIDE(0, hw_cb);
+
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ }
+
+ if (expSize > 0)
+ {
+ if (expSize > 15)
+ {
+ SIM_SetRXTIDE(CMD_RECBUFSIZE, hw_cb);
+ }
+ else
+ {
+ SIM_SetRXTIDE(expSize, hw_cb);
+ }
+ /* maybe changed for 64k rate */
+ }
+ else
+ {
+ INS |= SIM_INS_INSD;
+ }
+#endif /*NoT0CTRL*/
+#endif/*SIM_ADDDMA*/
+
+#ifdef SIM_ADDDMA
+ /*start DMA*/
+ //mtk04122:we start the DMA after we finish the DMA configuration
+ //SIM_SetBits(SimCard->dma_config.ADDR_HDMA_HDC0Rx, HDCR_START0);
+
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC40, hw_cb);
+#endif
+
+
+#endif /*SIM_ADDDMA*/
+
+ {
+
+#ifndef NoT0CTRL
+#ifdef SIM_NULLBYTE_ISSUE
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+ if (MTK_SIMIF0 == hwCtrl)
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount = 0;
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+ /*must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger*/
+ SimCard->simMagic1 ++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ switch_CB->nullByteGPTServingInterface = hw_cb->simInterface;
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 300, sim_nullByteIssueGptTimeoutMT6306, hw_cb);
+ }
+ else if (MTK_SIMIF1 == hwCtrl)
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount = 0;
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+ /*must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger*/
+ SimCard->simMagic1 ++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ switch_CB->nullByteGPTServingInterface = hw_cb->simInterface;
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 300, sim_nullByteIssueGptTimeoutMT6306, hw_cb);
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+
+#endif
+#endif /*NoT0CTRL*/
+
+ /*use PDN_STATUS(dev, s, t) to fullfill my dbg usage, add the code later*/
+
+ /*in case */
+ SimCard->EvtFlag = 0x0;
+
+ if (SimCard->simMagic2 != SimCard->simMagic1)
+ SIM_DEBUG_ASSERT(0);
+ if (txDelay == KAL_FALSE)
+ savedMask = SaveAndSetIRQMask();
+#ifndef NoT0CTRL
+ {
+
+ /*we should not use the same variable to store the return value twice*/
+ kal_uint32 savedMask2;
+
+ savedMask2 = SaveAndSetIRQMask();
+ sim_addMsg(SIM_CMD_INS_LOG, hw_cb->simInterface, INS, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+
+ SIM_SetCmdCTRL(INS);
+
+ SIM_CMDSTART();
+
+ RestoreIRQMask(savedMask2);
+
+ }
+#endif /*NoT0CTRL*/
+
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif /* End of #if defined (__SIM_DVT__) */
+
+
+
+ if (txDelay == KAL_FALSE)
+ RestoreIRQMask(savedMask);
+
+ }
+#ifdef SIM_ADDDMA
+ sim_addMsg(0x2468024, hw_cb->simInterface, txDelay, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+#endif /*SIM_ADDDMA*/
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif /* End of #if defined (__SIM_DVT__) */
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC42, hw_cb);
+#endif
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ *Error = KAL_TRUE;
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ SIM_FIFO_Flush();
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return 0;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ SIM_WaitEvent_MT6306(SimCard, SIM_EVT_CMD_END, KAL_FALSE, hw_cb);
+ SimCard->t_debug[3] = ust_get_current_time();
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_DisAllIntr();
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ sim_storeFifo(hw_cb);
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC43, hw_cb);
+#endif
+#ifdef SIM_NULLBYTE_ISSUE
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+#endif
+
+
+#ifdef SIM_ADDDMA
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+#endif /*SIM_ADDDMA*/
+
+#ifdef NoT0CTRL
+ SimCard->initialPower = SimCard->cmdState;
+ SimCard->cmdState = SIMD_CmdIdle;
+#endif /*NoT0CTRL*/
+
+
+
+ if (0x3 == SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))
+ SIM_DEBUG_ASSERT(0);
+
+ if (SimCard->result == SIM_SUCCESS && SimCard->recDataErr == KAL_FALSE)
+ {
+#ifdef SIM_ADDDMA
+ if (expSize != 0)
+ {
+ kal_uint16 leftlen = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_LEFTLEN_MTK);
+ if (leftlen > expSize)
+ {
+ *rcvSize = expSize;
+ log_size = kal_sprintf(hw_cb->dbgStr, "SIM Error : in SIM_CMD Leftlen(%d) > expSize(%d)!!!\r\n", leftlen, expSize);
+ if (log_size > 0) tst_sys_trace(hw_cb->dbgStr);
+ }
+ else
+ {
+ *rcvSize = expSize - leftlen;
+ }
+ }
+#else /*SIM_ADDDMA*/
+ *rcvSize = SimCard->recDataLen;
+#endif /*SIM_ADDDMA*/
+
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("SIM_SUCCESS\n\r");
+#endif
+
+#ifdef NoT0CTRL
+ SW = (SimCard->SW2 | (SimCard->SW1 << 8));
+#else /*NoT0CTRL*/
+ SIM_ObtainSW(SW);
+#endif /*NoT0CTRL*/
+
+#if !defined(ATEST_DRV_ENABLE)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC16, hw_cb->simInterface/*SimCard->sim_menu.addr*/, /*SimCard->sim_input.type*/ ust_us_duration(SimCard->t_debug[2], SimCard->t_debug[3]), /*SimCard->sim_input.count*/ 0, SW, *rcvSize);
+ if (result == NULL)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC16, txSize, *Error, 0, 0, drv_get_current_time());
+ else
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC16, txSize, *Error, *result, *(result + 1), drv_get_current_time());
+#endif
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ *Error = KAL_TRUE;
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ SIM_FIFO_Flush();
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return 0;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+ return SW;
+ }
+ else
+ {
+ if (SimCard->result == SIM_CMDTOUT)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "CMD_TOUT");
+ }
+#ifdef NoT0CTRL
+ SW = (SimCard->SW2 | (SimCard->SW1 << 8));
+#else /*NoT0CTRL*/
+ SIM_ObtainSW(SW);
+ if (SW == 0x0000)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "SIM%d Get SW=0x0000 from SIM Controller!!!!", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+#endif /*NoT0CTRL*/
+
+ //kal_sprintf(hw_cb->dbgStr,"[SIM]:SIM_CMD fail status=%d,SW:%x", SimCard->result,SW);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SimCard->result, SW, drv_get_current_time(), *rcvSize, hw_cb->simInterface);
+ //DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SimCard->sim_menu.addr, SimCard->sim_input.type, SimCard->sim_input.count,*result,*(result+1));
+ if (result == NULL)
+ DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, 0, 0, 0, expSize, txSize);
+ else
+ DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, *(result + 2), *(result + 3), *(result + 4), expSize, txSize);
+ sim_dump_fifo(hw_cb);
+ sim_dump_reg(SIM_PRINT_SIM_CMD_FAIL_STATUS, hw_cb);
+
+ //DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SIM_Reg32(DMA_base + 0x0 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x4 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x8 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x10 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x18 + (0x80 * SimCard->sim_dmaport)));
+ //DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SIM_Reg32(DMA_base + 0x1c + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x20 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x24 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x28 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x38 + (0x80 * SimCard->sim_dmaport)));
+ //DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SIM_Reg32(DMA_base + 0x50 + (0x80 * SimCard->sim_dmaport)),SIM_Reg32(DMA_base + 0x8),SIM_Reg32(0x80000450),drv_get_current_time(),SIM_Reg(SIM0_BASE_ADDR_MTK + 0x64));
+#ifndef __MAUI_BASIC__
+ /*we print DMA lefting, SIM controller power, SW1, SW2, 0x70, 0x74*/
+ if (0 != expSize)
+ {
+ /*we print P3, rx buffer addr, ((EV_GCB *)SimCard->event)->ev_current_events, data count, rx 1st, 2nd byte*/
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), (kal_uint32)result, 0, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ *result, * (result + 1)
+);
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+ }
+#endif /*__MAUI_BASIC__*/
+
+ //SimCard->recDataErr = KAL_FALSE;
+ SimCard->is_err = KAL_TRUE;
+ *Error = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] Interface:%d, Error! SW=%x, result:%x", __func__, hw_cb->simInterface, SW, SimCard->result);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ sim_dump_MT6306(hw_cb);
+ return 0;
+ }
+}
+
+
+
+/*
+* FUNCTION
+* L1sim_Cmd
+*
+* DESCRIPTION
+* The function is used to implement re-try command mechanism.
+*
+* CALLS
+*
+* PARAMETERS
+* txData: Pointer to the transmitted command and data.
+* txSize: The size of the transmitted command and data from AL to driver.
+* expSize: The size of expected data from SIM
+* result: Pointer to received data
+* rcvSize: Pointer to the size of data received
+* parityError: 1 (parity error) or 0(no parity error)
+*
+* RETURNS
+* status(high byte:sw1 low byte: sw2)
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+static kal_uint16 L1sim_Cmd(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error, sim_HW_cb *hw_cb)
+{
+ kal_uint8 index;
+ kal_uint16 SW;
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+#ifdef SIM_CACHED_SUPPORT
+ kal_uint8 *pNoncachedTx, *pNoncachedRx;
+#endif
+ kal_uint32 log_size = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "L1sim_Cmd(1) txSize=%d, rcvSize=%d\n\r", txSize, *rcvSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+
+ if (SimCard->State != SIM_PROCESSCMD)
+ {
+ *Error = KAL_TRUE;
+ return 0;
+ }
+ SimCard->get9000WhenSelect = KAL_FALSE;
+
+ // while encounter physical errors, deactivate the SIM immediately
+ for (index = 0; index < 3; index++)
+ {
+ SimCard->timeout = KAL_FALSE;
+
+#ifdef SIM_CACHED_SUPPORT
+ if (INT_QueryIsCachedRAM(txData, txSize) || INT_QueryIsCachedRAM(result, 512))
+
+ {
+ GET_NCACHEDTX_P(pNoncachedTx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ GET_NCACHEDRX_P(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ kal_mem_cpy(pNoncachedTx, txData, txSize);
+ if (INT_QueryIsCachedRAM(result, 512))
+ {
+ SW = SIM_CMD((kal_uint8 *)pNoncachedTx, txSize, (kal_uint8 *)pNoncachedRx, rcvSize, Error, hw_cb);
+ if (0 != *rcvSize)
+ {
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef __MAUI_BASIC__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ if (result != NULL)
+ kal_mem_cpy(result, pNoncachedRx, *rcvSize);
+ }
+ }
+ else
+ {
+ SW = SIM_CMD((kal_uint8 *)pNoncachedTx, txSize, result, rcvSize, Error, hw_cb);
+ }
+ }
+ else
+#endif
+ {
+ SW = SIM_CMD(txData, txSize, result, rcvSize, Error, hw_cb);
+ }
+
+ if (0x9000 == SW && 0xA4 == txData[1])
+ {
+ //dbg_print("[SIM]:0x9000 on select");
+ DRV_ICC_print(hw_cb, SIM_PRINT_9000_ON_SELECT, 0, 0, 0, 0, 0);
+ SimCard->get9000WhenSelect = KAL_TRUE;
+ }
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "L1sim_Cmd(2) txSize=%d, rcvSize=%d, fifo: %d\n\r", txSize, *rcvSize, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+#ifdef SIM_HOT_SWAP_V2
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+
+ /* [MAUI_03009364]If card is removed, we don't need to wait status words */
+ if (hw_cb->IsCardRemove && *Error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x3, SW, drv_get_current_time(), *rcvSize, hw_cb->simInterface);
+ /* SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave */
+ SimCard->timeout = KAL_FALSE;
+ return SW;
+ }
+#endif
+#endif
+
+ if (SimCard->timeout && SimCard->app_proto == USIM_PROTOCOL)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC18, txSize, *rcvSize, index, SW, SimCard->timeout);
+ /*SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave*/
+ SimCard->timeout = KAL_FALSE;
+
+
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ /*20130926, argus
+ we should not pass rst because it will cause rst to low if we did not connect to SIMIF */
+ /*USIM FTA requires to deactivate the card after timeout in 100ms*/
+ /*if we will use manual deactivate, we don't need to pass RST*/
+ if (KAL_FALSE == sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+ sim_MT6306_passRST(hw_cb);
+ }
+#endif
+ sim_PowerOff_MT6306(hw_cb);
+ /*set card not present to prevent next SIM command rush in*/
+ usim_dcb->present = KAL_FALSE;
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateDeactiavate);
+
+ return SW;
+ }
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+
+ /* [MAUI_03009364]If card is removed, we don't need to wait status words */
+ if (hw_cb->IsCardRemove && *Error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x5, SW, drv_get_current_time(), *rcvSize, hw_cb->simInterface);
+ /*SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave*/
+ SimCard->timeout = KAL_FALSE;
+ /*set card not present to prevent next SIM command rush in*/
+ usim_dcb->present = KAL_FALSE;
+ return SW;
+ }
+#endif
+ if (*Error == 0)
+ break;
+ }
+
+ if (((SW & 0xf000) != 0x6000) && ((SW & 0xf000) != 0x9000))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Illegal SW:%x", SW);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+ sim_dump_reg(SIM_PRINT_SIM_CMD_FAIL_STATUS, hw_cb);
+ *Error = KAL_TRUE;
+ }
+
+ if ((SW == 0x9000 || (SW & 0xFF00) == 0x9100 || (SW & 0xFF00) == 0x9200) && 0xB0 == txData[1] && *rcvSize == 0)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "READ BINARY, SW:%x, rcvSize:%d", SW, *rcvSize);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+ //*Error = KAL_TRUE;
+ SW = 0x6281;
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "Convert SW to :%x", SW);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+ }
+
+
+ if (*Error)
+ {
+ //kal_sprintf(hw_cb->dbgStr,"[SIM]:SIM_CMD fail result=%d, status=%x", SimCard->result, SW);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_CMD_FAIL_RESULT_STATUS, SimCard->result, SW, drv_get_current_time(), 0, 0);
+ //kal_sprintf(hw_cb->dbgStr,"[SIM]: recDataErr=%d, timeout=%d, cmdState=%d, event_state=%d, EvtFlag=%d, clkStop=%d, app_proto=%d",
+ // SimCard->recDataErr, SimCard->timeout, SimCard->cmdState, SimCard->event_state,
+ // SimCard->EvtFlag, SimCard->clkStop, SimCard->app_proto);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_RECEIVE_ERR_1, SimCard->recDataErr, SimCard->timeout, SimCard->cmdState, SimCard->event_state, SimCard->EvtFlag);
+ DRV_ICC_print(hw_cb, SIM_PRINT_RECEIVE_ERR_2, SimCard->clkStop, SimCard->app_proto, 0, 0, 0);
+
+#ifndef __MAUI_BASIC__
+ if (0 != result)
+ {
+ /*we print P3, rx buffer addr, ((EV_GCB *)SimCard->event)->ev_current_events, data count, rx 1st, 2nd byte*/
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), (kal_uint32)result, 0, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ *result, * (result + 1)
+);
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+ }
+#endif
+ if (SimCard->clkStop == KAL_TRUE)
+ {
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkStopped);
+ }
+ }
+
+#ifdef SIM_CACHED_SUPPORT_WRITE_THROUGH_SERIES
+ invalidate_wt_cache((kal_uint32)result, *rcvSize);
+#endif
+
+ if (SW != 0 && *Error == KAL_FALSE)
+ {
+ SimCard->cmd_duration_count++;
+ SimCard->cmd_duration_sum += ust_us_duration(SimCard->t_debug[2], SimCard->t_debug[3]);
+ }
+
+ /*SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave*/
+ SimCard->timeout = KAL_FALSE;
+ if (SimCard->EF_ICCID_Selected == KAL_TRUE && *rcvSize == 10 && txData[1] == 0xB0 && result != NULL)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", result[0], result[1], result[2], result[3], result[4], result[5], result[6], result[7], result[8], result[9]);
+
+#ifdef ATEST_DRV_ENABLE
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ICCID,hw_cb->simInterface, hw_cb->dbgStr);
+#endif
+
+
+ SimCard->EF_ICCID_Selected = KAL_FALSE;
+ }
+ if (txData[1] == 0xA4)
+ {
+ if (txSize >= 7 && txData[5] == 0x2F && txData[6] == 0xE2)
+ SimCard->EF_ICCID_Selected = KAL_TRUE;
+ else
+ SimCard->EF_ICCID_Selected = KAL_FALSE;
+ }
+ return SW;
+}
+
+/*
+* FUNCTION
+* L1sim_Init
+*
+* DESCRIPTION
+* The function L1sim_Init initialize the SIM driver.
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void L1sim_Init_MT6306(sim_HW_cb *hw_cb) //Validate
+{
+ kal_uint16 tmp = 0;
+ Sim_Card *SimCard = NULL, *peer_SimCard = NULL;
+ sim_HW_cb *peerHWCb = NULL;
+ sim_MT6306_switchInfo *switch_cb = NULL;
+ kal_uint32 hwCtrl;
+#ifdef SIM_ADDDMA
+ kal_uint8 DMA_channel = 0;
+#endif
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ tmp = tmp;
+ switch_cb = sim_MT6306_get_MT6306switchCB(hw_cb);
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ peer_SimCard = GET_SIM_CB(peerHWCb->simInterface);
+
+ SimCard->SIM_ENV = SIM_GetCurrentEnv(hw_cb->simInterface);
+ if (SimCard->SIM_ENV == ME_30V_ONLY)
+ {
+ SimCard->Power = SIM_30V;
+ }
+ else
+ {
+ SimCard->Power = SIM_18V;
+ }
+ usim_dcb->simInitialized=KAL_TRUE;
+
+ SimCard->Data_format = SIM_direct;
+ SimCard->State = SIM_WAIT_FOR_ATR;
+ SimCard->clkStop = KAL_FALSE;
+ SimCard->Speed = Speed372;
+
+#ifdef SIM_ADDDMA
+ SimCard->dma_config.BURST_SIZE = HDCTRR_BST_SIZE_16;
+ SimCard->dma_config.DEV_BUS_WIDTH = HDCTRR_BUS_WIDTH_8;
+ SimCard->dma_config.MEM_BUS_WIDTH = HDCTRR_BUS_WIDTH_32;
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+ if (MTK_SIMIF0 == hwCtrl)
+ DMA_channel = 0;
+ else
+ DMA_channel = 1;
+
+ SimCard->dma_config.channel = DMA_channel;
+ SimCard->dma_config.ADDR_HDMA_HPRGA0Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA0R0 : REG_HDMA_HPRGA0R1;
+ SimCard->dma_config.ADDR_HDMA_HPRGA1Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA1R0 : REG_HDMA_HPRGA1R1;
+ SimCard->dma_config.ADDR_HDMA_HDCTRRx = (DMA_channel == 0) ? REG_HDMA_HDCTRR0 : REG_HDMA_HDCTRR1;
+ SimCard->dma_config.ADDR_HDMA_HDC0Rx = (DMA_channel == 0) ? REG_HDMA_HDC0R0 : REG_HDMA_HDC0R1;
+ SimCard->dma_config.ADDR_HDMA_HDC1Rx = (DMA_channel == 0) ? REG_HDMA_HDC1R0 : REG_HDMA_HDC1R1;
+
+#endif /*SIM_ADDDMA*/
+ SimCard->cmd_duration_sum = 0;
+ SimCard->cmd_duration_count = 0;
+ SimCard->status_duration_sum = 0;
+ SimCard->status_duration_count = 0;
+ /*following members are originally RW global variable, need additional initialize here*/
+
+ SimCard->TOUTValue = SIM_DEFAULT_TOUT_VALUE << 2;
+
+ SimCard->TOUT_Factor = 1;
+ SimCard->PTS_check = KAL_TRUE;
+ SimCard->Fi = 372;
+
+
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+ /*
+ if(KAL_FALSE == sim_physicalSlotChanged){
+ if(0 != simInterface && NULL != SimCard_cb[0].event)
+ SimCard->event = SimCard_cb[0].event;
+ else if(0 != simInterface);//this case is legal since there maybe no SIM1 and we didn't do SIM1's L1sim_init
+ //SIM_DEBUG_ASSERT(0);
+ }
+ else{
+ if(1 != simInterface && NULL != SimCard_cb[1].event)
+ SimCard->event = SimCard_cb[1].event;
+ else if(1 != simInterface);//this case is legal since there maybe no SIM1 and we didn't do SIM1's L1sim_init
+ //SIM_DEBUG_ASSERT(0);
+ }
+ */
+ if (NULL != peer_SimCard->event)
+ SimCard->event = peer_SimCard->event;
+
+ if (SimCard->event == NULL)
+ {
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+ if (MTK_SIMIF0 == hwCtrl)
+ {
+ SimCard->event = kal_create_event_group("SIMEVT");
+ }
+ else if (MTK_SIMIF1 == hwCtrl)
+ {
+ SimCard->event = kal_create_event_group("SIMEVT2");
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (sim_hisrid == NULL)
+ {
+ sim_hisrid = kal_init_hisr(SIM_HISR);
+ }
+#endif
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, SIM_LISR_MT6306, "SIM handler");
+
+#ifdef SIM_NULLBYTE_ISSUE
+ if (0 != peer_SimCard->sim_nullByteIssueGPT)
+ SimCard->sim_nullByteIssueGPT = peer_SimCard->sim_nullByteIssueGPT;
+ if (NULL == (void*)SimCard->sim_nullByteIssueGPT)
+ DRV_ICC_GPTI_GetHandle(&SimCard->sim_nullByteIssueGPT);
+#if 0
+#ifdef SIM_HOT_SWAP_V2
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#endif
+ if (SimCard->gpt_handle == (kal_uint32)NULL)
+ DRV_ICC_GPTI_GetHandle(&SimCard->gpt_handle);
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ }
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (sim2_hisrid == NULL)
+ {
+ sim2_hisrid = kal_init_hisr(SIM2_HISR);
+ }
+#endif
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, SIM_LISR2_MT6306, "SIM2 handler");
+
+#ifdef SIM_NULLBYTE_ISSUE
+ if (0 != peer_SimCard->sim_nullByteIssueGPT)
+ SimCard->sim_nullByteIssueGPT = peer_SimCard->sim_nullByteIssueGPT;
+ if (NULL == (void*)SimCard->sim_nullByteIssueGPT)
+ DRV_ICC_GPTI_GetHandle(&SimCard->sim_nullByteIssueGPT);
+
+#if 0
+#ifdef SIM_HOT_SWAP_V2
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#endif
+ if (SimCard->gpt_handle == (kal_uint32)NULL)
+ DRV_ICC_GPTI_GetHandle(&SimCard->gpt_handle);
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+
+ }
+#endif
+ else
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ switch_cb->sim_waitHisrCb_MT6306 = hw_cb;
+ sim_MT6306_LISRStateChange(hw_cb, sim_MT6306_LISRSim);
+}
+#endif
+//================================ Layer type SIM driver start ==================================
+/*************************************************************************
+* FUNCTION
+* L1sim_Cmd_Layer
+*
+* DESCRIPTION
+* Layer type sim driver (transport layer) which maps C-APDU into C-TPDU for T=0
+*
+* PARAMETERS
+* txData: address of the tx buffer including the command header and optional tx data
+* txSize: size of data to be transfer including command buffer(5 bytes):(Lc+5) and
+ will be updated by real transfered data count.
+* rxData: address of the rx buffer
+* rxSize: expect received data size not including the sw1 and sw2 and will be updataed
+ by the real received data coung
+*
+* RETURNS
+* kal_uint16: status bytes of (sw1<<8|sw2), and 0 to indicate a physical error detected
+ by the driver such as timeout.
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+sim_status L1sim_Cmd_Layer_MT6306(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb, kal_bool *isSW6263)
+{
+ kal_bool warn, case4, sim_card, isSw6310 = KAL_FALSE;
+ kal_uint8 sw1, sw2, error, gp, rs, *tx;
+ kal_uint8 sim_get_resp_sim[] = {0xa0, 0xc0, 0x00, 0x00, 0x00 }; // 0xa0: SIM, 0x00: USIM
+ sim_status status, status_w = 0;
+ kal_uint32 rx_len, rx_buf_len, log_size = 0;
+ // sim_protocol_app_enum p = SimCard->app_proto;
+ Sim_Card *SimCard;
+
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]%s P3=%d txSize=%d, rxData%s=NULL, *rxSize=%d\n\r",
+ hw_cb->simInterface, __FUNCTION__, txData[4], *txSize, (rxData == NULL) ? "=" : "!", (rxData != NULL) ? *rxSize : 0);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_CMD_LEN,hw_cb->simInterface, txData[4], *txSize, (rxData == NULL) ? '=' : '!', (rxData != NULL) ? *rxSize : 0);
+#endif
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ /* [MAUI_03035883]clear status word 0x62xx 0x63xx flag */
+ *isSW6263 = KAL_FALSE;
+
+ /////dbg_print("L1sim_Cmd_Layer\r\n");
+ if (rxData != NULL && *rxSize == 0)
+ rx_buf_len = 256;
+ else
+ rx_buf_len = *rxSize;
+
+ if (*rxSize > 256) *rxSize = 256;
+
+ if (SimCard->cmd_case == usim_case_4)
+ {
+ case4 = KAL_TRUE;
+ *txSize -= 1;
+ *rxSize = 0;
+ }
+ else
+ case4 = KAL_FALSE;
+
+ if (SimCard->cmd_case == usim_case_2 && txData[0] == 0xA0 && txData[4] != 0)
+ {
+ *rxSize = txData[4]; //Use Le for rxSize
+ }
+
+
+ tx = txData;
+ status = L1sim_Cmd(tx, (kal_uint16) * txSize, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ rx_len = *rxSize;
+ rxData += *rxSize;
+ rs = SW1_RESEND_USIM;
+ //if(SIM_PROTOCOL == p)
+ if (txData[0] == 0xA0) // some usim will compatiable with SIM after received 0xa0....
+ {
+ gp = SW1_GET_RESP_SIM;
+ sim_get_resp_sim[0] = GET_RESP_CLA_SIM;
+ sim_card = KAL_TRUE;
+ }
+ else
+ {
+ // USIM_PROTOCOL (0x61 and 0x6c are only for case2 and case4
+ gp = SW1_GET_RESP_USIM;
+ /*
+ 2009/3/28, from Nagra SMD, we should uses previouse CLA byte as the CLA of get response payload
+ Snce CLA in usim is a run time variable depends on the channl opened in card, only protocol layer knows what is correct CLA.
+ */
+ /*
+ 2011/2/11, CLA need to have a revise :
+ for version before R7, bit5 to bit8 of CLA is defined by spec; bit1 to bit 4 is from SIM task.
+ for version after R7, bit7 to bit8 of CLA is defined by spec; bit1 to bit 6 is from SIM task.
+ */
+ sim_get_resp_sim[0] = DRV_ICC_makeCLA(GET_RESP_CLA_USIM, tx[0]);
+ sim_card = KAL_FALSE;
+ }
+ warn = KAL_FALSE;
+ for (;;)
+ {
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000009, drv_get_current_time(), case4, status_w, status);
+ sim_printFifo(hw_cb);
+ status = SIM_SW_STATUS_FAIL;
+ //*rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+ }
+ sw1 = status >> 8;
+ sw2 = status & 0xff;
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, rs, gp, sw1, sw2, status);
+#endif
+
+
+ if (SimCard->bypass6263 && (sw1 == SW1_WARN1 || sw1 == SW1_WARN2))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]return warning status1:%x \r\n", hw_cb->simInterface, status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ *isSW6263 = KAL_TRUE; //set 0x62xx 0x63xx flag
+ return status;
+ }
+
+
+ if (txData[0] == 0x80 && sw1 == SW1_GET_RESP_SIM)
+ {
+ /* 0x80 is Only For UIM/CSIM CMD */
+ gp = SW1_GET_RESP_SIM;
+ sim_get_resp_sim[0] = 0xA0;
+ sim_card = KAL_TRUE; /* by default, 0x80 will be treated as UICC CMD */
+ }
+
+ if ((sw1 == gp) ||
+ (sim_card && (sw1 == SW1_SIM_WARN1))) //add 9exx judegement
+ {
+ // get response 0x61
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC4, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC4, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC4, rs, gp, sw1, sw2, status);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "get response %x \r\n", sw1);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (rxData == NULL)
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("!!! ERR NULL rx buffer\r\n");
+#endif
+ return status;
+ }
+ //add 9exx judegement
+ if (sw1 == SW1_SIM_WARN1)
+ {
+#if defined(SIM_DEBUG_INFO )
+ log_size = kal_sprintf(hw_cb->dbgStr, "warning status %x %x\r\n", sw1, sw2);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ *isSW6263 = KAL_TRUE; //set 0x9exx flag
+ warn = KAL_TRUE;
+ status_w = status;
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC5, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC5, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC5, rs, gp, sw1, sw2, status);
+#endif
+ }
+ tx = sim_get_resp_sim;
+ if (0 != sw2)
+ {
+ if (sw2 > (rx_buf_len - rx_len))
+ sw2 = (rx_buf_len - rx_len);
+ *rxSize = sw2;
+ tx[LEN_INDEX] = sw2;
+ }
+ else
+ {
+ if (256 > (rx_buf_len - rx_len))
+ {
+ *rxSize = (rx_buf_len - rx_len);
+ tx[LEN_INDEX] = (rx_buf_len - rx_len);
+ }
+ else
+ {
+ *rxSize = 256;
+ tx[LEN_INDEX] = 0;
+ }
+ }
+ if (0 == *rxSize) /*we have to take care one condition that SIM task gave not enough space for next action*/
+ {
+ *rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+ }
+
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000007, drv_get_current_time(), case4, status_w, status);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ if (sim_card)
+ break;
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC6, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC6, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC6, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else if (sim_card && sw1 == SW1_GET_RESP_USIM) /*this is a work around for that, a SIM card replies USIM procedure byte*/
+ {
+ // get response 0x61
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC7, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC7, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC7, rs, gp, sw1, sw2, status);
+
+ //dbg_print("0x6100 from SIM card");
+ DRV_ICC_print(hw_cb, SIM_PRINT_6100_FROM_CARD, 0, 0, 0, 0, 0);
+#endif
+
+ if (rxData == NULL)
+ {
+#if defined(SIM_DEBUG_INFO)
+ dbg_print("!!! ERR NULL rx buffer \r\n");
+#endif
+ return status;
+ }
+ tx = sim_get_resp_sim;
+ if (0 != sw2)
+ {
+ if (sw2 > (rx_buf_len - rx_len))
+ sw2 = (rx_buf_len - rx_len);
+ *rxSize = sw2;
+ tx[LEN_INDEX] = sw2;
+ }
+ else
+ {
+ if (256 > (rx_buf_len - rx_len))
+ {
+ *rxSize = (rx_buf_len - rx_len);
+ tx[LEN_INDEX] = (rx_buf_len - rx_len);
+ }
+ else
+ {
+ *rxSize = 256;
+ tx[LEN_INDEX] = 0;
+ }
+ }
+ if (0 == *rxSize) /*we have to take care one condition that SIM task gave not enough space for next action*/
+ return status;
+
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ if (error == KAL_TRUE)
+ {
+ status = SIM_SW_STATUS_FAIL;
+ //*rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+ }
+ if (sim_card)
+ break;
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC8, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC8, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC8, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else if (!sim_card && sw1 == rs)
+ {
+ // resend the previous cmd 0x6c
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC9, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC9, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC9, rs, gp, sw1, sw2, status);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "resend command %x \r\n", sw1);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (rxData == NULL)
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("!!! ERR NULL rx buffer\r\n");
+#endif
+ return status;
+ }
+ /*there is one card that keep asking host to do get response.
+ but in this case we did not prepare enough buffer, so we should check buffer size here.
+ */
+ if (sim_get_resp_sim == tx && (rx_buf_len - rx_len) < sw2)
+ {
+ break;
+ }
+
+ /*we should check the valid buffer size here*/
+ if ((NULL != rxData) && ((rx_buf_len - rx_len) < sw2))
+ {
+ break;
+ }
+
+ tx[LEN_INDEX] = sw2;
+ *rxSize = sw2;
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ /*
+ In FTA test, SIM may reply 0x62, 0x6c then we get status word 0x9000 while resend.
+ Since we have resend many CMD and got correct status word, if we return old warning status word,
+ we will make SIM task take wrong action. Here is we got success SW, we set warn as FALSE
+ */
+ if (0x9000 == status && KAL_TRUE == warn)
+ warn = KAL_FALSE;
+
+ /* [ALPS00315325]we should add rxSize to rx_len to record total received length */
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000010, drv_get_current_time(), case4, status_w, status);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC10, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC10, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC10, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else if (!sim_card && case4 &&
+ (sw1 == SW1_WARN1 || sw1 == SW1_WARN2 || ((status != SIM_SW_STATUS_OK) && ((sw1 & 0xf0) == 0x90) && (sw1 != 0x91) && (sw1 != 0x92))))
+ {
+ /*
+ 08/07/30, it is 102 221 didn't consider the case that recursive get response condition.
+ It is impossible for driver to tell whether it is 3.a or 3.b when we encounter 0x91 status word after receiving 0x61.
+ But 0x91 will always be handled in SIM task layer, we do a little modification that won't classify 0x91 status word to 3.b,
+ if card do goes to wrong state, this status word will be catched and handled by SIM task.
+ */
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC11, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC11, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC11, rs, gp, sw1, sw2, status);
+#endif
+
+ // warning status
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "warning status %x %x\r\n", sw1, sw2);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ /* [MAUI_03035883]set status word 0x62xx 0x63xx flag */
+ *isSW6263 = KAL_TRUE; //set 0x62xx 0x63xx flag
+#if defined (DTAG_WALLET_V1)
+ if (sw1 == SW1_WARN2 && sw2 == 0x10)
+ {
+ isSw6310 = KAL_TRUE;
+ // [ALPS00459948]Review DTAG requirement for multipart APDUs
+ // If we enconter status 0x6310, it is specific for DTAG wallet development
+ // we just return status to sim task and let ril drive to send get response
+ log_size = kal_sprintf(hw_cb->dbgStr, "sw1:%x, isSW6263:%d, warn:%d, isSW6310:%d, status:%x", sw1, *isSW6263, warn, isSw6310, status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ // *rxSize = rx_len; // *rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ // return status;
+ }
+#endif
+#if defined(SIM_BY_PASS_6310)
+ if (sw1 == SW1_WARN2 && sw2 == 0x10 && *rxSize != 0)
+ {
+ *rxSize = rx_len; // *rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ log_size = kal_sprintf(hw_cb->dbgStr, "1.CLA:%x, INS:%x, isSW6263:%d, warn:%d, rx_len:%d, *rxSize:%x", *txData, *(txData + 1), *isSW6263, warn, rx_len, *rxSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return 0x6310;
+ }
+ else
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "CLA:%x, INS:%x, isSW6263:%d, warn:%d, rx_len:%d, *rxSize:%x", *txData, *(txData + 1), sw1, sw2, rx_len, *rxSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (tx[1] == 0xC0 && (((*rxSize) == tx[LEN_INDEX] && tx[LEN_INDEX] != 0) || ((*rxSize) == 256 && tx[LEN_INDEX] == 0)))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Le(%d) == *rxSize(%d)\n\r", tx[LEN_INDEX], *rxSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return status;
+ }
+ else
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Le(%d), *rxSize(%d), tx[1](%d)\n\r", tx[LEN_INDEX], *rxSize, tx[1]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ }
+#endif
+ warn = KAL_TRUE;
+ status_w = status;
+ tx = sim_get_resp_sim;
+ if (sw1 == SW1_WARN2 && sw2 == 0x10)
+ {
+ status_w = 0x6310;
+ }
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "DBG sw1:%x, isSW6263:%d, warn:%d, isSW6310:%d, status:%x", sw1, *isSW6263, warn, isSw6310, status_w);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ tx[LEN_INDEX] = 0;
+ if (sw1 == SW1_WARN2 && sw2 == 0x10)
+ {
+ *rxSize = 256;
+ }
+ else
+ {
+ *rxSize = 0;
+ }
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000011, drv_get_current_time(), case4, status_w, status);
+ status = SIM_SW_STATUS_FAIL;
+ //*rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+ }
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC12, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC12, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC12, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else
+ {
+ // command complete
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "command complete %x \r\n", status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ *rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC13, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC13, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC13, rs, gp, sw1, sw2, status);
+#endif
+ if (warn == KAL_TRUE || isSw6310 == KAL_TRUE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "DBG2 sw1:%x, sw2:%x, isSW6263:%d, warn:%d, isSW6310:%d, status:%x", sw1, sw2, *isSW6263, warn, isSw6310, status_w);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000012, drv_get_current_time(), case4, status_w, status);
+ return status_w;
+ }
+ return status;
+ }
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, rs, gp, sw1, sw2, status);
+#endif
+ //*rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+}
+//================================ Layer type SIM driver end ==================================
+//================================SIM test code==================================
+#ifdef DEVDRV_TEST
+#undef DEVDRV_TEST
+#endif
+#ifdef DEVDRV_TEST
+kal_uint8 Volt;
+kal_uint8 resVolt;
+AtrStruct ATRInfo;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 1
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /*MT6205,MT6205B,MT6218*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 1
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+void Sim_test(void)
+{
+ kal_uint8 result;
+ result = sim_Reset_MT6306(SIM_30V, &resVolt, &ATRInfo);
+ if (result == SIM_NO_ERROR)
+ {
+ //dbg_print("SIM has no Error!\r\n");
+ }
+ if (result == SIM_CARD_ERROR)
+ {
+ //dbg_print("SIM CARD has something error!\r\n");
+ return;
+ }
+
+ if (result == SIM_NO_INSERT)
+ {
+ //dbg_print("SIM CARD no insert!\r\n");
+ return;
+ }
+ //dbg_print("the resVolt=%x\r\n",resVolt);
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 1
+ if (vcc_check())
+ {
+ //dbg_print("VCC check is ok\r\n");
+ // break;
+ }
+ else
+ {
+ //dbg_print("VCC check is Failed\r\n");
+ }
+#endif
+ //return;
+ CheckPinCMD();
+ //////dbg_print("=========================================\r\n");
+#if 1
+ //////dbg_print("Will be close the sim!!\r\n");
+ //delay1s(50);
+ closeSIMcmd();
+ //SIM_Reject();
+ //dbg_print("SIM is closed!!\r\n");
+#endif
+}
+#endif /* DEVDRV_TEST */
+
+#endif //#if defined(SIM_DRV_SWITCH_MT6306)
+#endif //#if !defined(DRV_SIM_MT6208_SERIES)
+#endif //DRV_MULTIPLE_SIM
+#endif //__MTK_TARGET__
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
+
+#endif //DRV_SIM_OFF
+
diff --git a/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl1_mt6306.c b/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl1_mt6306.c
new file mode 100644
index 0000000..598eef9
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl1_mt6306.c
@@ -0,0 +1,5226 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * switchControl1.c(originally named usim_MT6302.c)
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * USIM driver functions on MT6302 dual SIM solution.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *
+ * 05 11 2015 bernie.chang
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "drv_comm.h"
+
+
+
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#include "reg_base.h"
+#include "intrCtrl.h"
+#include "sim_reg_adp.h"
+#include "drv_gdma.h"
+#include "sim_al.h"
+#include "sim_hw_mtk.h"
+
+
+#include "sim_sw_comm.h"
+//RHR#include "dma_hw.h"
+//#include "dma_sw.h"
+//#include "gpt_sw.h"
+//RHR#include "gpio_sw.h"
+#include "drv_hisr.h"
+#include "sim_mtk.h"
+#include "multi_icc_custom.h"
+//#ifdef DRV_MULTIPLE_SIM
+#if (defined(DRV_SIM_ALL_SOLUTION_BUILT) || (defined(DRV_MULTIPLE_SIM) && defined(DRV_2_SIM_CONTROLLER)))
+//#ifdef MT6318
+//#include "pmic6318_sw.h"
+//#endif /*MT6318*/
+
+#if defined(__SIM_PLUS__)
+ #include "msdc_def.h"
+#endif
+
+#if defined(__USIM_DRV__)
+//#include "usim_MT6302.h"
+
+//#include "pwic.h"
+
+//#if defined(MT6223PMU)
+//#include "pmu_sw.h"
+//#endif
+//#ifdef DRV_2_SIM_CONTROLLER
+#include "sim_mt6306.h"
+#include "sim_ctrl_al.h"
+#include "sim_drv_trc.h"
+
+//#endif
+#if defined(LPWR_SLIM)
+ #include "sleepdrv_interface.h"
+#endif
+#ifdef SIM_CACHED_SUPPORT
+ //RHR#include "init.h"
+ #include "cache_sw.h"
+#endif
+
+//#include "pmic6326_ccci_sw.h"
+//#endif
+
+/*RHR*/
+#include "drv_features.h"
+#include "drvpdn.h"
+//#include "kal_non_specific_general_types.h"
+#include "kal_public_api.h"
+#if !defined( __MAUI_BASIC__)
+ #include "kal_trace.h"
+#else
+ extern void dbg_print(char *fmt, ...);
+#endif
+#include "kal_debug.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#include "stdio.h"
+#include "string.h"
+/*RHR*/
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+
+/*following decalration were moved from gpt_sw.h*, we should change them to dcl form eventually*/
+//extern kal_uint8 GPTI_GetHandle(kal_uint8 *handle);
+//extern kal_bool GPTI_StartItem(kal_uint8 module,kal_uint16 tick,void (*gptimer_func)(void *),void *parameter);
+//extern void GPTI_StopItem(kal_uint8 module);
+
+extern kal_uint32 SIM_GetCurrentTime(void);
+extern void pmic6326_ccci_lock(kal_bool lock);
+
+
+extern void SIM_SetRXTIDE(kal_uint16 RXTIDE, sim_HW_cb *hw_cb);
+extern void SIM_SetTXTIDE(kal_uint16 _TXTIDE, sim_HW_cb *hw_cb);
+extern void DRV_ICC_print(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5);
+extern void sim_MT6306_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+extern void sim_MT6306_VCCCtrl(sim_HW_cb *hw_cb, kal_uint32 on);
+extern void sim_MT6306_VCCLvlCtrl(sim_HW_cb *hw_cb, kal_uint32 level);
+extern kal_bool sim_MT6306_QueryNeedManualControl(sim_HW_cb *hw_cb);
+extern void sim_MT6306_manualDeactive(sim_HW_cb *hw_cb);
+extern void sim_MT6306_manualReset(sim_HW_cb *hw_cb);
+extern sim_MT6306_status sim_MT6306_blockCLK(sim_HW_cb *hw_cb);
+extern void sim_MT6306_setCardState(sim_HW_cb *hw_cb, sim_MT6306_cardState cardState);
+extern void sim_MT6306_SPIWrite(sim_MT6306_switchInfo *switch_CB, kal_uint16 data);
+extern sim_env SIM_GetCurrentEnv(kal_uint32 simInterface);
+extern void sim_MT6306_LISRStateChange(sim_HW_cb *hw_cb, sim_MT6306_LISRState lisrState);
+extern kal_bool sim_MT6306_allCLKStopped(sim_HW_cb *hw_cb);
+extern kal_bool sim_MT6306_noneNeedClk(sim_HW_cb *hw_cb);
+extern sim_MT6306_status sim_MT6306_change(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+extern void sim_MT6306_setCardType(sim_HW_cb *hw_cb, sim_MT6306_cardType cardType);
+extern void L1sim_Init_MT6306(sim_HW_cb *hw_cb);
+extern kal_uint8 sim_Reset_MT6306(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info, sim_HW_cb *hw_cb);
+extern sim_MT6306_status sim_MT6306_recordDirectionBaud(sim_HW_cb *hw_cb);
+extern void L1sim_Configure_MT6306(kal_uint8 clockMode, sim_HW_cb *hw_cb);
+extern kal_bool sim_MT6306_QuerySIMActive(sim_HW_cb *hw_cb);
+extern void sim_PowerOff_MT6306(sim_HW_cb *hw_cb);
+extern void sim_MT6306_endOfAction(sim_HW_cb *hw_cb);
+
+extern sim_MT6306_status sim_MT6306_blockRST(sim_HW_cb *hw_cb);
+extern kal_bool MT6306_ShowReg(int chip);
+extern void sim_dump_MT6306(sim_HW_cb * hw_cb);
+extern int sprintf(char *, const char *, ...);
+extern kal_uint8 sim_MT6306_SPIRead(sim_MT6306_switchInfo *switch_CB, kal_uint16 addr);
+extern void sim_MT6306_clkStopTimerStop(sim_HW_cb *hw_cb);
+
+extern sim_MT6306_status sim_MT6306_passDAT(sim_HW_cb *hw_cb);
+extern sim_MT6306_status sim_MT6306_passRST(sim_HW_cb *hw_cb);
+extern sim_MT6306_status sim_MT6306_passCLK(sim_HW_cb *hw_cb);
+
+/*defines here since these functions will be called in sim_drv_SW_function.h*/
+static void usim_gpt_timeout_handler(void *parameter);
+void usim_restore_protocol(usim_dcb_struct * usim_dcb, sim_HW_cb * hw_cb);
+extern kal_uint32 sim_get_app_from_logicalNum(kal_uint32 logicalNum);
+
+extern Sim_Card *SimCard;
+//extern kal_bool TS_HSK_ENABLE;
+
+#define FILE_SWITCHCONTROL1 2
+
+extern kal_uint32 hwCbArray[DRV_SIM_MAX_LOGICAL_INTERFACE];
+extern kal_uint8 MT6302_raceConditionProtect[];
+//extern kal_bool sim_workingTaskWaiting;
+kal_bool sim_MT6306_noNeedEoc[DRV_SIM_MAX_LOGICAL_INTERFACE];
+extern kal_bool sim_physicalSlotChanged;
+
+
+//I set the number of element to a fixed value, since this code is for analog-switch solution, I have no power to support more than 2 interface
+//static usim_dcb_struct usim_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+extern Sim_Card SimCard_cb[];
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+volatile kal_semid wait_sim_MT6306_RACE_PROTECT[SIM_MT6306_MAX_PROTECTION_NUM] = {0};
+#endif
+//usim_dcb_struct *usim_dcb = &usim_cb[0];
+
+static kal_uint8 BWT_Factor[5] = {1, 6, 12, 24, 48}; // 372/64 = 6, 372/32 = 12, 23< 372/16 < 24
+
+
+
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+#include "hisr_config.h"
+#else
+static kal_hisrid usim_hisrid = NULL;
+static kal_hisrid usim2_hisrid = NULL;
+#endif
+
+#if defined(USIM_DEBUG)
+#define BUF_COUNT 1024
+kal_uint16 int_buffer[BUF_COUNT];
+kal_uint32 buf_index;
+#define PUSH_INT(a) int_buffer[(buf_index&(BUF_COUNT-1))] = a;\
+ buf_index++;
+#else
+#define PUSH_INT(a)
+#endif
+
+
+
+sim_clockStopMap clockStopMap[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+#if defined(__ARMCC_VERSION)
+ #pragma arm section zidata = "NONCACHEDZI", rwdata = "NONCACHEDRW"
+#endif
+#ifdef SIM_CACHED_SUPPORT
+ extern kal_uint32 sim_uncachedTxBuffer0[], sim_uncachedRxBuffer0[], sim_uncachedTxBuffer1[], sim_uncachedRxBuffer1[];
+ #define GET_NCACHEDTX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedTxBuffer0; else p=(kal_uint8 *)sim_uncachedTxBuffer1;}
+ #define GET_NCACHEDRX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedRxBuffer0; else p=(kal_uint8 *)sim_uncachedRxBuffer1;}
+ extern kal_uint8 uncachedDmaBuffer0[], uncachedDmaBuffer1[];//the instance is declared in icc_sim_common_mtk.c
+ #define GET_NCACHED_USIM_DMA_BUF_P(p, a) {if(0==a) p=(kal_uint8 *)uncachedDmaBuffer0; else p=(kal_uint8 *)uncachedDmaBuffer1;}
+ #define GET_NCACHED_USIM_DMA_BUF_INT(p, a) {if(0==a) p=(kal_uint32)uncachedDmaBuffer0; else p=(kal_uint32)uncachedDmaBuffer1;}
+#endif
+#if defined(__ARMCC_VERSION)
+ #pragma arm section zidata, rwdata
+#endif
+
+#if defined(USIM_DEBUG)
+extern void dbg_print(char * fmt, ...);
+static kal_uint32 start, end;
+kal_uint32 get_current_time(void)
+{
+ return (SIM_Reg32(0x80200230));
+}
+kal_uint32 get_duration_tick(kal_uint32 previous_time)
+{
+ kal_uint32 result, current_time;
+
+ current_time = SIM_Reg32(0x80200230);
+ if (previous_time > current_time)
+ {
+ result = 0x80000 - previous_time + current_time;
+ }
+ else
+ {
+ result = current_time - previous_time;
+ }
+ return result;
+}
+#endif
+
+// proto type
+static kal_bool usim_check_input_volt(usim_power_enum volt, sim_HW_cb *hw_cb);
+static usim_status_enum usim_process_ATR(sim_HW_cb *hw_cb);
+static void usim_process_TA1(kal_uint8 TA1, sim_HW_cb *hw_cb);
+static kal_bool usim_process_PTS(sim_HW_cb *hw_cb);
+static void usim_set_speed(usim_speed_enum speed, sim_HW_cb *hw_cb);
+static void usim_set_protocol(usim_protocol_enum T, sim_HW_cb *hw_cb);
+static void usim_set_timeout(kal_uint32 timeout, sim_HW_cb *hw_cb);
+static kal_bool usim_select_power(usim_power_enum ExpectVolt, sim_HW_cb *hw_cb);
+static void usim_activation(sim_HW_cb *hw_cb);
+static void usim_deactivation(sim_HW_cb *hw_cb) ;
+static void usim_t1end_handler(sim_HW_cb *hw_cb);
+static void usim_rx_handler(kal_uint32 int_status, sim_HW_cb *hw_cb);
+static void usim_send_block(kal_uint8 *adrs, sim_HW_cb *hw_cb);
+static kal_bool usim_rx_block_handler(kal_uint32 *adrs, sim_HW_cb *hw_cb);
+static sim_status usim_send_i_block(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb);
+void sim_PDNDisable_MT6306(sim_HW_cb *hw_cb);
+void sim_PDNEnable_MT6306(sim_HW_cb *hw_cb);
+//kal_taskid kal_get_current_thread_ID(void);
+
+#if defined(__CHAINING_TEST__)
+ extern kal_bool Send_IFS_REQ(kal_uint8 ifs, kal_uint8 interface);
+ extern void Set_IFSC(kal_uint8 ifs, kal_uint8 interface);
+#endif
+
+#if defined(__SPEED_TEST__)
+ extern usim_speed_enum speed_test;
+ extern kal_bool speed_test_enable;
+ extern void Set_Speed(kal_uint8 select_speed);
+#endif
+
+void USIM_WAIT_EVENT_MT6306(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ sim_MT6306_switchInfo *switch_CB;
+ kal_uint32 log_size = 0;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ DRV_ICC_GPTI_StartItem(usim_dcb->gpt_handle,
+ USIM_GPT_TIMEOUT_PERIOD,
+ usim_gpt_timeout_handler,
+ usim_dcb);
+
+ switch_CB->sim_workingTaskWaiting = KAL_TRUE;
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ {
+ kal_retrieve_eg_events(usim_dcb->event, USIM_EVENT, KAL_AND_CONSUME, &usim_dcb->ev_flag, KAL_SUSPEND);
+ }
+ else
+ {
+ kal_retrieve_eg_events(usim_dcb->event, USIM_EVENT, KAL_AND_CONSUME, &usim_dcb->ev_flag, 0);
+ }
+ switch_CB->sim_workingTaskWaiting = KAL_FALSE;
+ if (usim_dcb->status != USIM_GPT_TIMEOUT)
+ {
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ }
+ else
+ {
+ // Abnormal case, should dump registers for further anaysis
+
+ if (hw_cb != NULL)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "GPT TIMEOUT !!!");
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] %x, %x, %x, %x, %x, %x\n\r", hw_cb->simInterface,
+ SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK),
+ SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_STS_MTK),
+ SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+
+ // clear usim_dcb->status
+ usim_dcb->status = USIM_NO_ERROR;
+ }
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_check_input_volt
+*
+* DESCRIPTION
+* check if the input volt is supported by the interface device
+*
+* PARAMETERS
+* volt: voltage used by SIM card
+*
+* RETURNS
+* KAL_TRUE: it is supported
+* KAL_FALSE: not supported
+*
+* GLOBALS AFFECTED
+*
+*
+*************************************************************************/
+static kal_bool usim_check_input_volt(usim_power_enum volt, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (usim_dcb->sim_env == ME_18V_30V)
+ return KAL_TRUE;
+ if (usim_dcb->sim_env == ME_30V_ONLY && volt == CLASS_B_30V)
+ return KAL_TRUE;
+ if (usim_dcb->sim_env == ME_18V_ONLY && volt == CLASS_C_18V)
+ return KAL_TRUE;
+
+ return KAL_FALSE;
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_check_TCK
+*
+* DESCRIPTION
+* check if TCK present and the checksum of ATR is correct
+*
+* PARAMETERS
+*
+* RETURNS
+* KAL_TRUE: TCK is not present or chekcsum is correct
+* KAL_FALSE: Chekcsum is incorrect
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static kal_bool usim_check_TCK(sim_HW_cb *hw_cb)
+{
+ kal_uint32 i = 0;
+ kal_uint8 ck = 0;
+ kal_uint8 *ptr;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ ptr = usim_dcb->ATR_data;
+
+
+ //dbg_print("usim_check_TCK");
+ //DRV_ICC_print(SIM_PRINT_CHECK_TCK, 0, 0, 0, 0, 0);
+
+ while (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK) == 0 && i++ <= 22)
+ {
+ kal_sleep_task(10);
+ }
+ if (i >= 23)
+ {
+ //dbg_print("TCK not present");
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_NOT_PRESENT, 0, 0, 0, 0, 0);
+ return KAL_TRUE;
+ }
+
+ if (usim_dcb->ATR_index >= 33)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_CHECKSUM_ERR, 0, 0, 0, 0, 0);
+ return KAL_FALSE;
+ }
+
+ ptr[usim_dcb->ATR_index++] = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ for (i = 1; i < usim_dcb->ATR_index; i++)
+ ck ^= ptr[i];
+ if (ck != 0)
+ {
+ //dbg_print("TCK checksum err");
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_CHECKSUM_ERR, 0, 0, 0, 0, 0);
+ return KAL_FALSE;
+ }
+
+ //dbg_print("TCK checksum ok");
+ //DRV_ICC_print(SIM_PRINT_TCK_CHECKSUM_OK, 0, 0, 0, 0, 0);
+ return KAL_TRUE;
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_process_ATR
+*
+* DESCRIPTION
+* 1. wait all ATR characters received at HISR and put into usim_dcb->ATR_data
+* 2. Get parameters from ATR, Fi, Di, T0_support, T1_support, reset mode, WWT(T0)
+* IFSC(T1), CWI, BWI, X, U
+*
+* PARAMETERS
+* None
+* RETURNS
+* KAL_TRUE: Valid TS is received
+* KAL_FALSE: Valid TS is not received, card is not present or not supported
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static usim_status_enum usim_process_ATR(sim_HW_cb *hw_cb)
+{
+ kal_uint8 data, TD;
+ kal_bool T15;
+ kal_uint8 *ptr;
+ kal_uint32 index = 1; // skip the first TS byte
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ ptr = usim_dcb->ATR_data;
+
+ // get the application protocol of the sim card
+ if ((ptr[index] & 0x0f) == 0)
+ usim_dcb->app_proto = SIM_PROTOCOL; // no historical char imply SIM_PROTOCOL
+ else
+ {
+ do
+ {
+ data = ptr[index++];
+ USIM_CAL_TD_COUNT(data, index);
+ }
+ while (data & TDMask);
+ usim_dcb->hist_index = index;
+
+ if (ptr[index] == HIST_FIRST_USIM && ptr[index + 1] == HIST_SEC_USIM && ptr[index + 3] == HIST_FOUR_USIM)
+ {
+ usim_dcb->app_proto = USIM_PROTOCOL;
+ }
+ else if (ptr[index] == HIST_FIRST_USIM && ptr[index + 1] == HIST_SEC_USIM && ptr[index + 3] == 0x51 && ptr[index + 5] == HIST_FOUR_USIM)
+ {
+ //dbg_print("historycal byte error");
+ DRV_ICC_print(hw_cb, SIM_PRINT_HISTORICAL_BYTE_ERR, 0, 0, 0, 0, 0);
+ usim_dcb->app_proto = USIM_PROTOCOL;
+ }
+ else
+ usim_dcb->app_proto = SIM_PROTOCOL;
+ }
+ // parse the content of ATR
+ T15 = KAL_FALSE;
+ index = 1;
+ TD = ptr[index++]; //T0
+ if (TD & TAMask)
+ {
+ // TA1 (FI, DI)
+ data = ptr[index++];
+ usim_process_TA1(data, hw_cb);
+ //usim_dcb->WWT = INIT_WWT_T0*usim_dcb->Di;
+ DRV_ICC_Calc_WWT(usim_dcb->Fi, usim_dcb->Di, 10, &usim_dcb->WWT);
+ }
+ if (TD & TBMask)
+ {
+ // TB1 (PI, II) (neglect it)
+ data = ptr[index++];
+ }
+ if (TD & TCMask)
+ {
+ // TC1 (N: extra guard time) (neglect it)
+ data = ptr[index++];
+ if (data != 0 && data != 255)
+ return USIM_INVALID_ATR;
+ }
+ if (!(TD & TDMask))
+ {
+ usim_dcb->T0_support = KAL_TRUE;
+ return USIM_NO_ERROR;
+ }
+
+ TD = ptr[index++]; // TD1
+ if ((TD & 0x0f) == 0)
+ usim_dcb->T0_support = KAL_TRUE;
+ else if ((TD & 0x0f) == 1)
+ usim_dcb->T1_support = KAL_TRUE;
+ else if ((TD & 0x0f) == 0x0f)
+ {
+ // T = 15 is forbidden in TD1
+ return USIM_INVALID_ATR;
+ }
+
+ if (TD & TAMask)
+ {
+ //TA2 (specific mode)
+ //dbg_print("TA2(specific mode) \r\n");
+ usim_dcb->TA2 = ptr[index++];
+ usim_dcb->reset_mode = USIM_RESET_SPECIFIC;
+ // chage the clock to the one before reset.
+ }
+ if (TD & TBMask)
+ {
+ // TB2 (PI2)(neglect it)
+ data = ptr[index++];
+ }
+ if (TD & TCMask)
+ {
+ // TC2 (work waiting time = 960xWIxDi etu)(T0)
+ data = ptr[index++];
+ //usim_dcb->WWT = 960*data*usim_dcb->Di;
+ DRV_ICC_Calc_WWT(usim_dcb->Fi, usim_dcb->Di, data, &usim_dcb->WWT);
+ }
+ if (!(TD & TDMask))
+ {
+ if (usim_dcb->T0_support && !usim_dcb->T1_support && !T15)
+ {
+ return USIM_NO_ERROR;
+ }
+ else
+ {
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ return USIM_INVALID_ATR;
+ else
+ return USIM_NO_ERROR;
+ }
+ }
+
+ TD = ptr[index++]; // TD2
+ if ((TD & 0x0f) == 1)
+ {
+ usim_dcb->T1_support = KAL_TRUE;
+ }
+ else if ((TD & 0x0f) == 0x0f)
+ {
+ T15 = KAL_TRUE;
+ goto global_interface;
+ }
+ if (TD & TAMask)
+ {
+ //TA3 (ISFC)
+ data = ptr[index++];
+ usim_dcb->ifsc = data;
+ }
+ if (TD & TBMask)
+ {
+ kal_uint8 cwi, bwi;
+
+ // TB3 (PI2)
+ data = ptr[index++];
+ cwi = data & 0xf; // range from 0~5
+ bwi = (data & 0xf0) >> 4;
+ if (cwi > MAX_CWI)
+ return USIM_INVALID_ATR;
+ if (bwi > MAX_BWI)
+ return USIM_INVALID_ATR;
+ usim_dcb->CWT = (1 << cwi) + 11;
+ usim_dcb->BWT = (1 << bwi) * 960;
+ }
+ else
+ {
+ usim_dcb->CWT = USIM_CWT_DEFAULT;
+ usim_dcb->BWT = USIM_BWT_DEFAULT;
+ }
+ if (TD & TCMask)
+ {
+ // TC3 (neglect)
+ // data = ptr[index++];
+ index++;
+ }
+ if (!(TD & TDMask))
+ {
+ if (usim_dcb->T0_support && !usim_dcb->T1_support && !T15)
+ return USIM_NO_ERROR;
+ else
+ {
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ return USIM_INVALID_ATR;
+ else
+ return USIM_NO_ERROR;
+ }
+ }
+ TD = ptr[index++]; // TD3
+ if ((TD & 0x0f) != 0x0f)
+ {
+ if (usim_dcb->T0_support && !usim_dcb->T1_support && !T15)
+ return USIM_NO_ERROR;
+ else
+ {
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ return USIM_INVALID_ATR;
+ else
+ return USIM_NO_ERROR;
+ }
+ }
+
+global_interface:
+
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ return USIM_INVALID_ATR;
+
+ if (TD & TAMask)
+ {
+ //TAi (clock stop(X) and power class(U))
+ data = ptr[index++];
+ usim_dcb->clock_stop_type = (usim_clock_stop_enum)(data & CLOCK_STOP_MSK);
+ usim_power_enum PowerClass = (usim_power_enum)(data & USIM_POW_CLASS_MSK);
+ usim_dcb->hasPowerClass = KAL_TRUE;
+ usim_dcb->PowerClass = PowerClass;
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ /*[ALPS00378979]
+ fix BJ TMC NFC fail 5_5_4_2 TC1 Power provided in full power mode (Class B)
+ */
+ {
+ if (PowerClass == CLASS_C_18V)
+ usim_dcb->power_class = CLASS_C_18V;
+ else if (PowerClass == CLASS_B_30V)
+ usim_dcb->power_class = CLASS_B_30V;
+ else
+ usim_dcb->power_class = CLASS_ALLSUPPORT;
+ }
+ else
+ usim_dcb->power_class = (usim_power_enum)(data & USIM_POW_CLASS_MSK);
+
+ /*SIM task need following information for UICC identification*/
+ usim_dcb->TAiExist = KAL_TRUE;
+#if defined(SIM_DRV_IC_USB)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC50, data, usim_dcb->clock_stop_type, usim_dcb->power_class, usim_dcb->TAiExist, 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC50, usim_dcb->app_proto, usim_dcb->sim_env, usim_dcb->power, usim_dcb->power_in, usim_dcb->power_class);
+#endif
+ }
+ else //from latest 7816-3, if ATR is valid without class indicator, host should continue normal operation
+ {
+ return USIM_NO_ERROR;
+ }
+ if (TD & TBMask)
+ {
+ data = ptr[index];
+ usim_dcb->TB15 = data;
+ }
+#if defined(SIM_DRV_IC_USB)
+ if (TD & TBMask && usim_dcb->forceISO == KAL_FALSE)
+ {
+ // TBi indicate supporting IC-USB interface
+ data = ptr[index++];
+ if ((data & TB15_ICUSB_MASK) == TB15_ICUSB_MASK)
+ {
+ usim_dcb->isIcUsb = KAL_TRUE;
+ usim_dcb->TB15 = data;
+ }
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC51, data, usim_dcb->clock_stop_type, usim_dcb->power_class, usim_dcb->TAiExist, usim_dcb->isIcUsb);
+ }
+ else
+ {
+ usim_dcb->isIcUsb = KAL_FALSE;
+ }
+#endif
+
+ // check if used power is supported by the UICC
+ if ((usim_dcb->power & usim_dcb->power_class) == 0)
+ {
+ if (usim_dcb->sim_env == ME_18V_30V)
+ {
+ if (usim_dcb->power == CLASS_C_18V)
+ usim_dcb->power = CLASS_B_30V;
+
+ return USIM_VOLT_NOT_SUPPORT;
+ }
+ }
+ else if (usim_dcb->app_proto == SIM_PROTOCOL)
+ return USIM_NO_ERROR;
+
+ return USIM_NO_ERROR;
+}
+/*************************************************************************
+* FUNCTION
+* usim_process_TA1
+*
+* DESCRIPTION
+ 1.
+Get Di and Fi from TA1
+*
+* PARAMETERS
+ TA1: first interface character used to indicate the Fi and Di
+
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* usim_dcb->Fi, usim_dcb->Di
+*
+*************************************************************************/
+static void usim_process_TA1(kal_uint8 TA1, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (TA1 == ATR_TA1_64)
+ {
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 8;
+ usim_dcb->card_speed = SPEED_64;
+ }
+ else if (TA1 == ATR_TA1_32)
+ {
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 16;
+ usim_dcb->card_speed = SPEED_32;
+ }
+ else if (TA1 == ATR_TA1_16)
+ {
+ // only support speed32 even encounter a speed16 card
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 32;
+ usim_dcb->card_speed = SPEED_16;
+ }
+ else if (TA1 == ATR_TA1_8)
+ {
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 64;
+ usim_dcb->card_speed = SPEED_8;
+ }
+ else if ((TA1 & 0xF0) == 0x70 || (TA1 & 0xF0) == 0x80 || (TA1 & 0xF0) == 0xE0 || (TA1 & 0xF0) == 0xF0
+ || (TA1 & 0x0F) == 0x00 || (TA1 & 0x0F) == 0x0A || (TA1 & 0x0F) == 0x0B || (TA1 & 0x0F) == 0x0C
+ || (TA1 & 0x0F) == 0x0D || (TA1 & 0x0F) == 0x0E || (TA1 & 0x0F) == 0x0F)
+ {
+ usim_dcb->Fi = 372;
+ usim_dcb->Di = 1;
+ usim_dcb->card_speed = SPEED_RFU;
+ }
+ else
+ {
+ usim_dcb->Fi = 372;
+ usim_dcb->Di = 1;
+ usim_dcb->card_speed = SPEED_372;
+ }
+
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_process_PTS
+*
+* DESCRIPTION
+* 1. Perform the PTS to select the protocol and enhanced speed parameter(Fn,Dn).
+ T1 has higher priority than T0
+* 2. Change the clock rate according to the PTS response
+* 3. Enable the T0 or T1 controller according to the PTS response
+*
+* PARAMETERS
+ None
+
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* usim_dcb->speed
+*
+*************************************************************************/
+static kal_bool usim_process_PTS(sim_HW_cb *hw_cb)
+{
+ kal_uint32 savedMask;
+ kal_uint32 i = 0;
+ kal_uint8 pts[PPS_LEN] = {0}, pts_r[PPS_LEN] = {0}, pck;
+ usim_speed_enum speed;
+ kal_bool echoed = KAL_TRUE;
+ usim_dcb_struct *usim_dcb = NULL;
+ kal_uint8 pps_length = PPS_LEN;
+// sim_MT6306_switchInfo *switch_CB = NULL;
+
+// switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+
+ /////dbg_print("usim_process_PTS \r\n");
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ //dbg_print("PTS not performed (SIM_PROTOCOL) \r\n");
+ echoed = KAL_FALSE;
+
+ // move codes from exit:
+ usim_dcb->phy_proto = T0_PROTOCOL;
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ return KAL_TRUE;
+ }
+ if (usim_dcb->reset_mode == USIM_RESET_SPECIFIC)
+ {
+ /////dbg_print("not performed (specific mode)");
+ echoed = KAL_TRUE;
+ if (usim_dcb->TA2 & 0x10)
+ {
+ goto exit;
+ }
+ }
+ if (usim_dcb->high_speed_en)
+ {
+ if (usim_dcb->Di == 1)
+ speed = SPEED_372;
+ else if (usim_dcb->Di == 8)
+ speed = SPEED_64;
+ else if (usim_dcb->Di == 16)
+ speed = SPEED_32;
+ else if (usim_dcb->Di == 32)
+ speed = SPEED_16;
+ else if (usim_dcb->Di == 64)
+ speed = SPEED_8;
+
+ else
+ speed = SPEED_372;
+ }
+ else
+ {
+ speed = SPEED_372;
+ }
+
+ if (usim_dcb->reset_mode == USIM_RESET_SPECIFIC)
+ {
+ usim_set_speed(speed, hw_cb);
+ goto exit;
+ }
+#if defined(__SPEED_TEST__)
+ if (KAL_TRUE == speed_test_enable)
+ {
+ speed = speed_test;
+ speed_test_enable = KAL_FALSE;
+ }
+#endif
+ //dbg_print("select speed %d(372:64:32, 0:1:2)\r\n", speed);
+
+ // generate PTS packet
+ pts[PPSS] = 0xff;
+ pck = 0xff;
+ pts[PPS0] = USIM_PTS_PS1_MSK;
+
+ /*******************************************************************************************/
+//mtk04122: due to the stability considerations, we use T1 physical protocol when card only supports T1
+// However, in test mode, we still need to verify T1 functionailiy. Hence, we add a compiler flag
+// only used in test mode for T1 testing.
+ /*******************************************************************************************/
+#if !defined(__T1_HIGT_PRIORITY__)
+ if (usim_dcb->T1_support && usim_dcb->app_proto == USIM_PROTOCOL && !usim_dcb->T0_support) // priority T1 > T0
+#else
+ if (usim_dcb->T1_support && usim_dcb->app_proto == USIM_PROTOCOL) //modified by MTK04122
+#endif
+ {
+ // T1 only usim card will go to here
+ pts[PPS0] |= USIM_PTS_PS0_T1;
+ }
+ else
+ {
+ //dbg_print("select T=0\r\n");
+ }
+
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && usim_dcb->forceISO == KAL_FALSE)
+ {
+ pts[PPS0] = 0x2F;
+ }
+#endif
+
+ pck ^= pts[PPS0];
+ if (speed == SPEED_372)
+ pts[PPS1] = ATR_TA1_372_5;
+ else if (speed == SPEED_64)
+ pts[PPS1] = ATR_TA1_64;
+ else if (speed == SPEED_32) // SPEED_32
+ pts[PPS1] = ATR_TA1_32;
+ else if (speed == SPEED_16) // SPEED_16
+ pts[PPS1] = ATR_TA1_16;
+ else if (speed == SPEED_8) // SPEED_8
+ pts[PPS1] = ATR_TA1_8;
+
+
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && usim_dcb->forceISO == KAL_FALSE)
+ {
+ pts[PPS1] = 0xC0;
+ }
+#endif
+
+ pck ^= pts[PPS1];
+
+ // send PTS packet
+ usim_dcb->main_state = PTS_STATE;
+ pts[PCK] = pck;
+ if(usim_dcb->card_speed == SPEED_RFU)
+ {
+ pts[PPSS] = 0xFF;
+ pts[PPS0] = 0x00;
+ pts[PPS1] = 0xFF;
+ pps_length = 3;
+ }
+ SIM_FIFO_Flush();
+
+
+ // make sure FIFO really cleared
+
+ SIM_SetRXTIDE(pps_length, hw_cb);
+ savedMask = SaveAndSetIRQMask();
+ for (i = 0; i < pps_length; i++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, pts[i]);
+ }
+ RestoreIRQMask(savedMask);
+
+
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ usim_set_timeout(0, hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ if (usim_dcb->ev_status != USIM_NO_ERROR)
+ echoed = KAL_FALSE;
+ // read the response
+ if (echoed)
+ {
+ for (i = 0; i < pps_length; i++)
+ {
+ pts_r[i] = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ if (pts[i] != pts_r[i])
+ echoed = KAL_FALSE;
+ }
+ }
+
+#if defined(SIM_DRV_IC_USB)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC71, usim_dcb->isIcUsbRecPPS, echoed, usim_dcb->ev_status, usim_dcb->isIcUsb, 0);
+#endif
+
+ if (echoed)
+ {
+ usim_set_speed(speed, hw_cb);
+ // Some high speed SIM card after clock rate change have to wait a while to
+ // to receive the first command.
+ if (pts[1] != 0x00)
+ kal_sleep_task(10);
+ }
+ else
+ {
+ DRV_ICC_print_err_msg(hw_cb, "PPS exchange fail");
+ usim_set_speed(SPEED_372, hw_cb);
+ DRV_ICC_print(hw_cb , SIM_PRINT_L1SIM_CMD_TRC71, pts[0], pts[1], pts[2], pts[3], 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC71, pts_r[0], pts_r[1], pts_r[2], pts_r[3], 0);
+ }
+
+exit:
+ // GSM will only use T=0, no matter t=1 is supported.
+#if !defined(__T1_HIGT_PRIORITY__)
+ if (usim_dcb->T1_support && !usim_dcb->T0_support &&
+ (usim_dcb->app_proto == USIM_PROTOCOL) && echoed)
+#else
+ if (usim_dcb->T1_support &&
+ (usim_dcb->app_proto == USIM_PROTOCOL) && echoed)
+#endif
+ {
+ // T1 only usim card will go to here
+ usim_dcb->phy_proto = T1_PROTOCOL;
+ usim_set_protocol(T1_PROTOCOL, hw_cb);
+ USIM_DISABLE_TXRX_HANSHAKE();
+ SIM_SetRXRetry(0);
+ SIM_SetTXRetry(0);
+ }
+ else
+ {
+ usim_dcb->phy_proto = T0_PROTOCOL;
+ if (usim_dcb->app_proto == USIM_PROTOCOL && echoed)
+ usim_set_protocol(T0_PROTOCOL, hw_cb); // SIM_PROTOCOL is enabled at simd.c
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ }
+
+ return echoed;
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_set_timeout
+*
+* DESCRIPTION
+* setup the timeout value in the unit of etu
+*
+* PARAMETERS
+* timeout: timeout value in the unit of etu , 0 means disabling timeout
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void usim_set_timeout(kal_uint32 timeout, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (timeout)
+ {
+ timeout >>= 2;
+ SIM_SetTOUT(timeout + TOUT_OFFSET, hw_cb);
+ usim_dcb->timeout = timeout + TOUT_OFFSET;
+ }
+ else
+ {
+ USIM_DISABLE_TOUT();
+ }
+}
+/*************************************************************************
+* FUNCTION
+* usim_set_speed
+*
+* DESCRIPTION
+* setup the baudrate of the SIM card, only support 372, 64 and 32.
+* speed 16 is not supported, use speed32 insteadly.
+*
+* PARAMETERS
+* timeout: timeout value in the unit of etu , 0 means disabling timeout
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void usim_set_speed(usim_speed_enum speed, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div7;
+#elif defined(SIM_DRV_4_33MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div8;
+#else
+ kal_uint32 clk_div = SIM_BRR_CLK_Div4;
+#endif
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ switch (speed)
+ {
+ case SPEED_372:
+ // clock: 13/4 = 3.25M, with default etu F/372
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div372));
+ break;
+ case SPEED_64:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div64));
+ break;
+ case SPEED_32:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div32));
+ break;
+ case SPEED_16:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div16));
+ break;
+ case SPEED_8:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div8));
+ break;
+
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+ usim_dcb->speed = speed;
+ usim_dcb->BWT = usim_dcb->BWT * BWT_Factor[speed] + 11;
+}
+/*************************************************************************
+* FUNCTION
+* usim_set_protocol
+*
+* DESCRIPTION
+* setup the physical protocol layer including T=0 and T=1.
+*
+* PARAMETERS
+* T: physical protocol layer including T=0 and T=1.
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void usim_set_protocol(usim_protocol_enum T, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (T == T1_PROTOCOL)
+ {
+ USIM_ENABLE_T1();
+ }
+ else
+ {
+ USIM_ENABLE_T0();
+ }
+ usim_dcb->phy_proto = T;
+}
+/*************************************************************************
+* FUNCTION
+* usim_select_power
+*
+* DESCRIPTION
+ 1. Try the input voltage from application layer if availabe.
+ 2. Try the possible voltage which the ME can support.
+ 3. Get the valid TS
+*
+* PARAMETERS
+ 1. ExpectVolt: application layer give a expected power class
+
+* RETURNS
+* KAL_TRUE: Valid TS is received
+* KAL_FALSE: Valid TS is not received, card is not present or not supported
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static kal_bool usim_select_power(usim_power_enum ExpectVolt, sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry = 0;
+ usim_dcb_struct *usim_dcb = NULL;
+// sim_MT6306_switchInfo *switch_CB = NULL;
+
+// switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /////dbg_print("usim_select_power with power: %d \r\n", ExpectVolt);
+
+ SIM_FIFO_Flush();
+#if defined (SIM_NFC_DELAY_VSIM_ON_OFF)
+ SIM_SetAtime(0xf000):
+#endif
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ {
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE004, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ usim_deactivation(hw_cb);
+ // decide the initial power class
+ usim_dcb->power_in = ExpectVolt;
+ if (ExpectVolt != UNKNOWN_POWER_CLASS)
+ {
+ usim_dcb->power = ExpectVolt;
+ }
+ else
+ {
+ if (usim_dcb->sim_env == ME_30V_ONLY)
+ {
+ usim_dcb->power = CLASS_B_30V;
+ }
+ else // ME_18_ONLY, ME_18V_30V
+ {
+ usim_dcb->power = CLASS_C_18V;
+ }
+ }
+ }
+ // start from low power class to high, if no ATR received, try another power class
+ // if the an invalid TS byte is received, change the convention with the same power class
+ retry = 0;
+ while (retry++ < 3)
+ {
+ //2007_04_12, some 3G card will give wrong ATR in the first time, and we should reset it twice
+ //If we don't reset these 2 variables, former wrong path will affect next time we process ATR
+ usim_dcb->abort = usim_dcb->resync = KAL_FALSE;
+ usim_activation(hw_cb);
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE009, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+#if !defined( __MAUI_BASIC__) || defined(MEUT_ON_FPGA)
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL1, __LINE__,
+ usim_dcb->ev_status, usim_dcb->power,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), drv_get_current_time()
+);
+#endif
+#endif
+#endif
+
+ if (usim_dcb->ev_status == USIM_NO_ERROR)
+ {
+ // a correct TS byte is received
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ }
+ if (usim_dcb->present == KAL_FALSE) return KAL_FALSE;
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+ // all ATR characters are received
+ if (usim_dcb->ev_status != USIM_ATR_REC)
+ {
+ return KAL_FALSE;
+ }
+ else
+ {
+ return KAL_TRUE;
+ }
+ }
+ else if (usim_dcb->ev_status == USIM_ATR_REC)
+ {
+ // all ATR characters are received
+ return KAL_TRUE;
+ }
+ else if (usim_dcb->warm_rst == KAL_TRUE)
+ {
+ usim_deactivation(hw_cb);
+ return KAL_FALSE;
+ }
+ else if ((usim_dcb->ev_status == USIM_TS_INVALID || usim_dcb->ev_status == USIM_RX_INVALID)
+ && (usim_dcb->dir == USIM_DIRECT))
+ {
+ // try another convention
+ usim_dcb->dir = (USIM_INVERSE == usim_dcb->dir) ? USIM_DIRECT : USIM_INVERSE;
+ dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, "[%s] interface:%d, dir:%d\n\r", __FUNCTION__, hw_cb->simInterface, usim_dcb->dir);
+ usim_deactivation(hw_cb);
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE00A, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ //dbg_print("change another convention %d !!\r\n", usim_dcb->dir);
+ }
+ else if (usim_dcb->ev_status == USIM_NO_ATR || usim_dcb->ev_status == USIM_BWT_TIMEOUT ||
+ (usim_dcb->ev_status == USIM_TS_INVALID || usim_dcb->ev_status == USIM_RX_INVALID))
+ {
+ retry = 0;
+ usim_dcb->dir = USIM_DIRECT;
+ // deactivate and delay
+ usim_deactivation(hw_cb);
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE00B, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ // change another power class if availabe, no retry with the same power class
+ if (usim_dcb->sim_env == ME_18V_30V)
+ {
+ if (usim_dcb->power_in == UNKNOWN_POWER_CLASS && usim_dcb->power == CLASS_C_18V)
+ {
+ usim_dcb->power = CLASS_B_30V;
+ }
+ else if (usim_dcb->power_in != UNKNOWN_POWER_CLASS && usim_dcb->power_in == usim_dcb->power)
+ {
+ if (usim_dcb->power_in == CLASS_C_18V)
+ usim_dcb->power = CLASS_B_30V;
+ else
+ usim_dcb->power = CLASS_C_18V;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+ dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, "[%s] interface:%d, power:%d\n\r", __FUNCTION__, hw_cb->simInterface, usim_dcb->power);
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+
+ }
+ else
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ }
+ return KAL_FALSE;
+}
+/*************************************************************************
+* FUNCTION
+* usim_activation
+*
+* DESCRIPTION
+* Perform the activation of USIM
+* It is a cold reset
+* select the power according to usim_dcb->power (input)
+* select the convention according to usim_dcb->dir (input)
+* the clock rate adopted is SPEED_372
+* set the default timeout value
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void usim_activation(sim_HW_cb *hw_cb)
+{
+ kal_uint16 reg = 0;
+ usim_dcb_struct *usim_dcb = NULL;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+ DRV_GET_RET_ADDR(retAddr);
+
+ sim_addMsg(0x11042007, 0, 0, (kal_uint32)retAddr);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ /*enanle VSIM to 3V so that we can drive IO low*/
+ /*enanle VSIM2 to 3V so that we can drive IO low*/
+
+
+ /////dbg_print("usim_activation, pow = %d, dir: %d \r\n",usim_dcb->power, usim_dcb->dir);
+
+ /*no matter which interface, in Gemini project, we only need to control one PMIC*/
+
+ reg = SIM_CONF_SIMSEL;
+ /*use PMU API to enalbe MT632x PMIC LDO output to 1.8V
+ it will pull up SIMIO/SIMCLK/SIMIO.
+ BB SIMIO/SIMCLK/SIMIO is powered by AVDD30_VSIMn by PMIC feedback
+ logical circuit */
+ /* fix PMIC output to 1.8V */
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(0, CLASS_C_18V);
+ }
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(1, CLASS_C_18V);
+ }
+
+ if (CLASS_B_30V == usim_dcb->power)
+ {
+ sim_MT6306_VCCLvlCtrl(hw_cb, 1);
+ }
+ else
+ {
+ sim_MT6306_VCCLvlCtrl(hw_cb, 0);
+ }
+
+
+ if (usim_dcb->dir == USIM_DIRECT)
+ reg &= ~(SIM_CONF_CONV);
+ else
+ reg |= SIM_CONF_CONV;
+
+ if (KAL_TRUE == usim_dcb->ts_hsk_en)
+ {
+ reg |= (SIM_CONF_TXHSK | SIM_CONF_RXHSK);
+ SIM_SetRXRetry(1);
+ SIM_SetTXRetry(1);
+ }
+ else
+ {
+ SIM_SetRXRetry(0);
+ SIM_SetTXRetry(0);
+ }
+#if defined (__SIM_ATRSTA_BIT_SHIFT__)
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, reg | SIM_CONF_RSTCTL);
+#else
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, reg);
+#endif
+ SIM_FIFO_Flush();
+ // delay 100 clock cycles (30us) [MAUI_03431888]/[MAUI_03433590]
+ {
+ kal_uint32 t1;
+ t1 = drv_get_current_time();
+ while ((drv_get_current_time() - t1) < 1);
+ }
+ SIM_SetRXTIDE(2, hw_cb); // generate a interrupt while TS byte and T0 is received
+
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, USIM_IRQEN_ATR | SIM_STS_RXERR);
+ reg = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, reg);
+ usim_dcb->main_state = ACTIVATION_STATE;
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ {
+ SIM_CLR_OE_BIT() ;
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ /* Enable PMIC VSIM LDO to fix 1.8V */
+#if !defined(__DRV_SIM_SIMIF_CONTROL_VSIM__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_TRUE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_TRUE);
+ }
+#endif
+ /* Enable MT6306 VSIM LDO */
+ sim_MT6306_VCCCtrl(hw_cb, 1);
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_ACT, hw_cb->simInterface, 0, usim_dcb->power);
+
+#if !defined(__SIM_DRV_ENABLE_SWRST__)
+ // if we don't need SW control SWRST, we should set this bit to 1 as HW controler SIMRST
+#if defined (__SIM_ATRSTA_BIT_SHIFT__)
+ SIM_SetData(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, SIM_CONF_RSTCTL, SIM_CONF_RSTCTL);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC63, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x04), 0xfefe);
+#endif
+#endif
+
+ if (sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+ sim_MT6306_manualReset(hw_cb);
+ }
+ else
+ {
+
+ USIM_POW_ON();
+
+// sim_MT6306_manualReset(hw_cb);
+#if defined(__SIM_DRV_ENABLE_SWRST__)
+ USIM_WAIT_EVENT_MT6306(usim_dcb);
+ if (usim_dcb->ev_status == USIM_WAITING_SWRST)
+ {
+ // 1. swrst interrupt received
+ // 2. pull high SIMRST
+ sim_MT6306_setRST(hw_cb, KAL_TRUE);
+ // 3. reenable WWT T0 and clear ev_status
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ // 4. set SIM_CTRL register SWRST bit to enable ATR TOUT
+ SIM_SetData(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK, SIM_CTRL_SWRST, SIM_CTRL_SWRST);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC31, usim_dcb->ev_status, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0, 0);
+ // add SIM_IRQEN_SWRST at USIM_IRQEN_ATR marco
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, USIM_IRQEN_ATR | SIM_STS_RXERR);
+ // if card send atr, we can enter select power process;otherwise, enter find card process
+ }
+ else
+ {
+ // there should be not interrupt can earier than USIM_WAITING_SWRST
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC32, usim_dcb->ev_status, hw_cb->simInterface, usim_dcb->status, SIM_Reg(SIM0_BASE_ADDR_MTK + 0x70), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x74));
+ //SIM_DEBUG_ASSERT(0); using original activation flow, to rery 3 times to find card
+ }
+#endif
+ }
+ }
+ else
+ {
+ // for r2R
+ sim_MT6306_passDAT(hw_cb);
+ sim_MT6306_passRST(hw_cb);
+ USIM_WRST();
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ kal_sleep_task(10);
+ }
+
+ // go to usim_hisr of case RXTIDE, ATRERR, RXERR(parity error)
+}
+
+void usim_lisr_MT6306(kal_uint32 v)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(0));
+ IRQMask(hw_cb->mtk_lisrCode);
+ //drv_active_hisr(DRV_USIM_HSIR_ID);
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(USIM_HISR);
+#else
+ kal_activate_hisr(usim_hisrid);
+#endif
+}
+
+void usim_lisr2_MT6306(kal_uint32 v)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(1));
+ IRQMask(hw_cb->mtk_lisrCode);
+ //drv_active_hisr(DRV_USIM2_HSIR_ID);
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(USIM2_HISR);
+#else
+ kal_activate_hisr(usim2_hisrid);
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_deactivation
+*
+* DESCRIPTION
+* 1. deactivate the UICC card
+* 2. wait util the the deactivation is complete
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb->main_state
+*
+*************************************************************************/
+static void usim_deactivation(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb = NULL;
+
+// sim_MT6306_switchInfo *switch_CB = NULL;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+ DRV_GET_RET_ADDR(retAddr);
+ sim_PDNDisable_MT6306(hw_cb);
+ sim_addMsg(0x11042008, 0, 0, (kal_uint32)retAddr);
+
+// switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /////dbg_print("usim_deactivation\r\n");
+
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)&SIM_CTRL_SIMON)
+ {
+
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_DEACT, hw_cb->simInterface, 0, 0);
+ // before deactivate the SIM interface, turn on the clock first.
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) &= ~SIM_CTRL_HALT;
+
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ sim_addMsg(SIM_DEACTIVATE_1, hw_cb->simInterface, usim_dcb->main_state, usim_dcb->ev_status);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ sim_MT6306_cardInfo *card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ DRV_ICC_GPTI_StopItem(card_cb->sim_MT6306_gptHandle);
+ if (sim_MT6306_CLKPass != card_cb->pins.CLK)
+ {
+ sim_MT6306_passCLK(hw_cb);
+ kal_sleep_task(1);
+ }
+
+ if (KAL_FALSE == sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+#if defined(__SIM_DRV_ENABLE_SWRST__)
+ // 1. pull low SIMRST
+ sim_MT6306_setRST(hw_cb, KAL_FALSE);
+ // 2. set SIM_CTRL register SWRST bit to enable ATR TOUT
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SWRST);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC33, usim_dcb->ev_status, hw_cb->simInterface, usim_dcb->status, SIM_Reg(SIM0_BASE_ADDR_MTK + 0x70), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x74));
+#endif
+ SIM_Deactive();
+ while (!(DRV_Reg32(hw_cb->mtk_baseAddr + SIM_ATRSTA_MTK) & 0x0001));
+ sim_MT6306_VCCCtrl(hw_cb, 0);
+ //must wait for LDO falling time
+
+ if (KAL_FALSE == kal_query_systemInit())
+ {
+ kal_sleep_task(10);
+ }
+
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ USIM_CLR_FIFO();
+ SIM_DisAllIntr(); // disable SIMOFF INT
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ // tell USB to reset MAC & PHY
+ SIM_icusb_disableSession(hw_cb);
+ sim_addMsg(0xE005, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ }
+#endif
+
+#if defined(__FPGA__)
+#else // #if defined(__FPGA__)
+ while (!(DRV_Reg32(hw_cb->mtk_baseAddr + SIM_ATRSTA_MTK) & 0x0001));
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_FALSE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_FALSE);
+ }
+#endif // #if defined(__FPGA__)
+ }
+ else
+ {
+ sim_MT6306_manualDeactive(hw_cb);
+ /*since we don't use HISR and event, we have to set ev_status manually*/
+ usim_dcb->ev_status = USIM_POWER_OFF;
+ }
+
+
+ if (KAL_FALSE == sim_MT6306_QuerySIMActive(hw_cb->simSwitchPeerInterfaceCb))
+ {
+ sim_MT6306_addMsg(0x11030801, hw_cb->simInterface, hw_cb->mtk_baseAddr, 0);
+ }
+ else
+ {
+ sim_MT6306_addMsg(0x11030802, hw_cb->simInterface, 0, 0);
+ }
+
+ // Need delay of at least 10ms before next activate operation
+ kal_sleep_task(KAL_TICKS_50_MSEC);
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ // tell USB to reset MAC & PHY
+ SIM_icusb_disconnectDone(hw_cb);
+ sim_addMsg(0xE007, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ }
+#endif
+
+ sim_addMsg(SIM_DEACTIVATE_2, hw_cb->simInterface, usim_dcb->main_state, usim_dcb->ev_status);
+ usim_dcb->main_state = DEACTIVATION_STATE;
+ if (usim_dcb->ev_status == USIM_POWER_OFF)
+ usim_dcb->main_state = DEACTIVATION_STATE;
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC20, hw_cb->mtk_baseAddr, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), 0, 0, 0x1116);
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC20, hw_cb);
+ }
+ }
+#if defined(SIM_DRV_IC_USB)
+ else
+ {
+ sim_addMsg(0xE008, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ }
+#endif
+
+}
+/*************************************************************************
+* FUNCTION
+* usim_t1end_handler
+*
+* DESCRIPTION
+* 1. it is called while t1end interrupt is generated.
+* 2. there are two different states in this function:
+ CMD_TX_STATE: a complete block is sent to UICC
+ CMD_RX_INF_STATE: a complete block is received from UICC
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb->main_state
+*
+*************************************************************************/
+static void usim_t1end_handler(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ switch (usim_dcb->main_state)
+ {
+ case (volatile usim_main_state_enum) CMD_TX_STATE:
+
+ USIM_DMA_RX_TIDE();
+
+ if (usim_dcb->wtx == KAL_TRUE)
+ {
+ usim_dcb->wtx = KAL_FALSE;
+ usim_set_timeout(usim_dcb->BWT * usim_dcb->wtx_m, hw_cb);
+ }
+ else
+ usim_set_timeout(usim_dcb->BWT, hw_cb);
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ usim_dcb->main_state = CMD_RX_STATE;
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_STS_EDCERR | SIM_STS_RXERR | SIM_STS_T1END | SIM_STS_OV | SIM_STS_TOUT));
+ break;
+ case (volatile usim_main_state_enum) CMD_RX_STATE:
+ {
+ kal_uint8 len, pcb;
+#ifdef SIM_CACHED_SUPPORT
+ kal_uint8 *dma_buffer;
+ GET_NCACHED_USIM_DMA_BUF_P(dma_buffer, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+#else
+ kal_uint8 *dma_buffer = usim_dcb->dma_buffer;
+#endif
+
+ usim_set_timeout(0, hw_cb);
+#ifdef SIM_ADDDMA
+ SIM_DMA_STOP(usim_dcb->dma_config.channel);
+#endif
+
+#ifdef SIM_CACHED_SUPPORT_WRITE_THROUGH_SERIES
+ /*in write through cache, we should invalidate the rxbuffer, once we want to read its data*/
+ invalidate_wt_cache((kal_uint32)usim_dcb->dma_menu.addr, usim_dcb->dma_input.count);
+#endif
+
+
+ if (usim_dcb->ev_status == USIM_RX_INVALID)
+ {
+ // comes from EDC or parity error
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ log_size = kal_sprintf(hw_cb->dbgStr, "usim_dcb->ev_status Status:%x\n\r", usim_dcb->ev_status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ return;
+ }
+ // receive a complete block, except a S-block received, there still is one
+ // parameter byte in the fifo
+ usim_dcb->header_rx[T1_NAD_INDEX] = dma_buffer[T1_NAD_INDEX]; // NAD
+ pcb = usim_dcb->header_rx[T1_PCB_INDEX] = dma_buffer[T1_PCB_INDEX]; // PCB
+ len = usim_dcb->header_rx[T1_LEN_INDEX] = dma_buffer[T1_LEN_INDEX]; // LEN
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "CMD_RX_STATE (reveive a block!! len: %d)\n\r", len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+
+#if defined (__SIM_DVT__)
+ log_size = kal_sprintf(hw_cb->dbgStr, "CMD_RX_STATE (reveive a block!! len: %d)\n\r", len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif /* End of #if defined (__SIM_DVT__) */
+
+ if (len)
+ {
+ if (len == 1 && USIM_IS_SBLOCK(pcb))
+ {
+ usim_dcb->header_rx[T1_INF_INDEX] = dma_buffer[T1_INF_INDEX];
+ }
+ else
+ {
+ kal_mem_cpy(usim_dcb->rx_buf + usim_dcb->rx_index, &dma_buffer[T1_INF_INDEX], len);
+ }
+ }
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ break;
+ default: // MTK04122: add default for handling error state
+ SIM_ASSERT(0);
+ break;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("\n\r");
+#endif
+}
+static void usim_timeout_handler(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+
+ switch (usim_dcb->main_state)
+ {
+ case ATR_STATE:
+ // may be optimized by parsing the content instead of using timeout.
+ // read the remaining bytes of ATR
+ {
+ kal_uint32 count;
+
+ count = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK);
+ while (count--)
+ {
+ if (usim_dcb->ATR_index >= 33)
+ {
+ USIM_CLR_FIFO();
+ /* maybe the atr is correct??? */
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ return;
+ }
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ }
+ usim_dcb->ev_status = USIM_ATR_REC;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "ATR TOUT, usim_dcb->ev_status:%x", usim_dcb->ev_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+ }
+ break;
+ case CLK_STOPPING_STATE:
+ /*in Gemini project, we can't use HISR to stop clk*/
+ SIM_DEBUG_ASSERT(0);
+ {
+ kal_bool level;
+
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->main_state = CLK_STOPPED_STATE;
+ if (usim_dcb->clock_stop_type == CLOCK_STOP_HIGH)
+ level = KAL_TRUE;
+ else
+ level = KAL_FALSE;
+ sim_MT6306_blockCLK(hw_cb);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkStopped);
+ if (sim_MT6306_allCLKStopped(hw_cb))
+ {
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_STOPCLK, hw_cb->simInterface, 0, 0);
+ SIM_Idle_MT6306(level, hw_cb);
+ /*controller's clock must now stopped, verify it*/
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & 0x2) != 0x2)
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ SIM_DisAllIntr();
+#if defined(USIM_DEBUG)
+ end = get_duration_tick(start);
+#endif
+ }
+ break;
+ case CLK_STOPPED_STATE:
+ {
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ break;
+ default:
+#ifdef SIM_ADDDMA
+ SIM_DMA_STOP(usim_dcb->dma_config.channel);
+#endif
+ usim_dcb->ev_status = USIM_BWT_TIMEOUT;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+
+}
+
+static void usim_hisr_common(sim_HW_cb *hw_cb, kal_uint32 int_status)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 log_size = 0;
+ //not like Gemini project, in dual controller solution, we need 2 individual HISR and thus every HISR mapping fixed interface
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+#if defined(ATEST_DRV_ENABLE)
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%x]int_status:%x IRQEN:%x, mian_state:%x\n\r", hw_cb->simInterface, int_status, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), usim_dcb->main_state);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_HISR_USIM,hw_cb->simInterface, int_status, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+#endif
+
+ /*In mt6290, INT status is write clear*/
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, int_status);
+
+ sim_addMsg(SIM_INT_USIM, 0, int_status, usim_dcb->ev_status);
+ usim_dcb->int_status = int_status;
+ PUSH_INT(int_status);
+
+#if defined(__SIM_DRV_ENABLE_SWRST__)
+ if (int_status & SIM_STS_SWRST)
+ {
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_WAITING_SWRST;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+#endif
+ if (usim_dcb->previous_state == ACTIVATION_STATE || usim_dcb->previous_state == ATR_STATE)
+ {
+ usim_dcb->previous_state = usim_dcb->main_state;
+ usim_dcb->atr_count++;
+ if (usim_dcb->atr_count > 40)
+ {
+ SIM_DisAllIntr(); // disable SIMOFF INT
+ usim_dcb->ev_status = USIM_NO_ATR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ usim_dcb->atr_count = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM DRV:%d]SIM1 card send too many ATR data\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto end_of_hisr;
+ }
+ }
+ else
+ {
+ usim_dcb->previous_state = usim_dcb->main_state;
+ usim_dcb->atr_count = 0;
+ }
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] usim_hisr int:%x, FIFO count = %d\r\n",int_status, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+#endif
+ if (int_status & SIM_STS_RXERR)
+ {
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "RXERR, usim_dcb->ev_status:%x, int_status:%x", usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+
+ if (usim_dcb->main_state == ACTIVATION_STATE)
+ {
+ SIM_DisAllIntr();
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ goto end_of_hisr;
+ }
+ // wait t1end interrupt
+ }
+
+ if (int_status & SIM_STS_EDCERR)
+ {
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ }
+ if (int_status & SIM_STS_TOUT)
+ {
+ if (KAL_FALSE == sim_MT6306_QueryNeedManualControl(hw_cb))
+ {
+ usim_timeout_handler(hw_cb);
+ }
+ else
+ {
+ /*it is manual control, and we receive timeout hisr, we should make driver feel NATR*/
+ usim_dcb->ev_status = USIM_NO_ATR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ goto end_of_hisr;
+ }
+ if (int_status & SIM_STS_T1END)
+ {
+ usim_t1end_handler(hw_cb);
+ }
+ if (int_status & SIM_STS_RX)
+ {
+ usim_rx_handler(int_status, hw_cb);
+ }
+ if (int_status & SIM_STS_SIMOFF)
+ {
+ usim_dcb->ev_status = USIM_POWER_OFF;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ goto end_of_hisr;
+ }
+ if (int_status & SIM_STS_TXERR || int_status & SIM_STS_OV)
+ {
+ // SIM_DEBUG_ASSERT(0); [ALPS00426103]not need assert
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "TXERR, usim_dcb->ev_status:%x, int_status:%x", usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+ }
+ if (int_status & SIM_STS_NATR)
+ {
+ usim_dcb->ev_status = USIM_NO_ATR;
+ DRV_ICC_print_err_msg(hw_cb, "No ATR");
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+
+end_of_hisr:
+
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+}
+/*we need usim_hisr and usim_hisr2, since there is no argument to tell additional information*/
+void usim_hisr_MT6306(void)
+{
+ kal_uint32 int_status;
+ sim_HW_cb *hw_cb;
+ //usim_dcb_struct *usim_dcb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(0));
+ //usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ int_status = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ /*
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL1, __LINE__,
+ usim_dcb->int_status, int_status, hw_cb->simInterface,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), usim_dcb->ev_status, usim_dcb->main_state
+ );*/
+ sim_MT6306_addMsg(0x01170002, hw_cb->simInterface, int_status, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK));
+ usim_hisr_common(hw_cb, int_status);
+
+}
+void usim_hisr2_MT6306(void)
+{
+ kal_uint32 int_status;
+ sim_HW_cb *hw_cb;
+ //usim_dcb_struct *usim_dcb;
+
+ hw_cb = sim_get_hwCb(sim_get_logical_from_SIMIF(1));
+ //usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ int_status = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+
+ /*drv_trace8(TRACE_GROUP_4, LOG_SIM_DRV_GEMINI_GEN1, FILE_SWITCHCONTROL1, __LINE__,
+ usim_dcb->int_status, int_status, hw_cb->simInterface,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), usim_dcb->ev_status, usim_dcb->main_state
+ );*/
+ sim_MT6306_addMsg(0x01170003, hw_cb->simInterface, int_status, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK));
+ usim_hisr_common(hw_cb, int_status);
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_rx_handler
+*
+* DESCRIPTION
+* 1. It is called byt usim_hisr
+* 2. It is called while RXTIDE interrupt is triggerred
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void usim_rx_handler(kal_uint32 int_status, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 log_size = 0 ;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /////dbg_print("usim_rx_handler ");
+
+ switch (usim_dcb->main_state)
+ {
+ case ACTIVATION_STATE:
+ /////dbg_print("ACTIVATION_STATE ");
+ {
+ kal_uint8 TS = 0, T0 = 0, count;
+
+ TS = SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK));
+ /////dbg_print("TS = %x ", TS);
+ if (TS == 0x3B || TS == 0x3F)
+ {
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ SIM_SetRXRetry(USIM_RETRY);
+ SIM_SetTXRetry(USIM_RETRY);
+ count = 0;
+ T0 = SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK));
+ usim_dcb->hist_index = T0 & 0xf; // use to contain the length of historical char (temperary)
+ USIM_CAL_TD_COUNT(T0, count);
+ //if((T0 & TDMask) == (kal_uint32)NULL)
+ if (!(T0 & TDMask))
+ {
+ count += usim_dcb->hist_index;
+ if (count >= SIM_TOTAL_FIFO_LEN)
+ {
+ usim_dcb->abort = KAL_TRUE; // for temp usage (separate two times)
+ count -= 6;
+ }
+ usim_dcb->resync = KAL_TRUE; // for temp usage (last time)
+ }
+ else
+ count++;
+ if (count == 0)
+ {
+ usim_dcb->ev_status = USIM_ATR_REC;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ else
+ {
+ usim_dcb->rx_size = count + 1; // for temp usage (index to TD byte)
+ SIM_SetRXTIDE(count, hw_cb);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), USIM_IRQEN_NORMAL);
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ }
+
+ usim_dcb->main_state = ATR_STATE;
+ usim_dcb->ATR_index = 0;
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = TS;
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = T0;
+ }
+ else
+ {
+ usim_dcb->ev_status = USIM_TS_INVALID;
+ SIM_DisAllIntr(); // prevent the following ATR bytes trigger RX interrupt
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+ DRV_ICC_print_str("[SIM_DRV]Card Error, Enter find Card Process.\n\r");
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "Check HW Waveform for HW issue. TS:%x T0:%x usim_dcb->ev_status:%x, int_status:%x", TS, T0, usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ }
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+
+ break;
+ case ATR_STATE:
+ {
+ // receive all ATR data without timeout to indicate
+ kal_uint32 count;
+ kal_uint8 TD;
+
+ count = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK);
+ /////dbg_print("ATR_STATE : %d ",count);
+ while (count--)
+ {
+ if (usim_dcb->ATR_index >= 33)
+ {
+ USIM_CLR_FIFO();
+ /* maybe the atr is correct??? */
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ return;
+ }
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ }
+ if (usim_dcb->abort == KAL_TRUE)
+ {
+ usim_dcb->abort = KAL_FALSE;
+ SIM_SetRXTIDE(6, hw_cb);
+ usim_dcb->resync = KAL_TRUE;
+ break;
+ }
+ if (usim_dcb->resync == KAL_FALSE)
+ {
+ TD = usim_dcb->ATR_data[usim_dcb->rx_size];
+ /////dbg_print(", TD = %x ,%d", TD,usim_dcb->rx_size);
+ count = 0;
+ USIM_CAL_TD_COUNT(TD, count);
+ //if((TD & TDMask) == (kal_uint32)NULL)
+ if (!(TD & TDMask))
+ {
+ count += usim_dcb->hist_index;
+ if (count >= SIM_TOTAL_FIFO_LEN)
+ {
+ // usim_dcb->rx_index = count; // for temp usage (total ATR len)
+ usim_dcb->abort = KAL_TRUE; // for temp usage (separate two times)
+ count -= 6;
+ }
+ usim_dcb->resync = KAL_TRUE; // for temp usage (last time)
+ }
+ else
+ count++;
+ usim_dcb->rx_size += (count); // for temp usage (index to TD byte)
+ SIM_SetRXTIDE(count, hw_cb);
+ }
+ else
+ {
+ usim_set_timeout(0, hw_cb);
+ /////dbg_print("\r\n!! all ATR received \r\n");
+ usim_dcb->hist_index = 0;
+ usim_dcb->rx_size = 0;
+ usim_dcb->resync = KAL_FALSE;
+ usim_dcb->abort = KAL_FALSE;
+ usim_dcb->ev_status = USIM_ATR_REC;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ }
+ break;
+ case PTS_STATE:
+ SIM_DisAllIntr();
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ break;
+
+ default:
+ //MTK04122: other states shall not invoke rx_handler
+ SIM_ASSERT(0);
+ break;
+ }
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_send_block
+*
+* DESCRIPTION
+* 1. sending a block to UICC, with header in usim_dcb->header_tx
+* 2. if len > 0 then using DMA to transfer data from tx buffer to the fifo of sim
+ interface.
+ 3. after a complete block is sent, T1END is generated
+ 4. after that, three bytes of received block header will come into rx fifo
+*
+* PARAMETERS
+ adrs: tx buffer address
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void usim_send_block(kal_uint8 *adrs, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 len, pcb;
+ kal_uint8 *header;
+ kal_uint32 pNoncachedRx;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ //usim_dcb_struct *dcb = usim_dcb;
+
+ header = usim_dcb->header_tx;
+ usim_dcb->main_state = CMD_TX_STATE;
+ USIM_CLR_FIFO();
+
+ kal_sleep_task(1);
+ // make sure FIFO really cleared
+
+ // write header into fifo
+ len = header[T1_LEN_INDEX];
+ pcb = header[T1_PCB_INDEX];
+
+#if defined(USIM_DEBUG)
+ {
+ kal_uint32 i;
+ dbg_print("tx:");
+ if (USIM_IS_SBLOCK(pcb) && len == 1)
+ {
+ dbg_print(" %x", header[T1_INF_INDEX]);
+ }
+ else
+ {
+ for (i = 0; i < len; i++)
+ {
+ dbg_print(" %x", adrs[i]);
+ }
+ }
+ dbg_print("\r\n");
+ }
+#endif
+
+ sim_MT6306_addMsg(0x01170001, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), header[T1_NAD_INDEX], pcb);
+ sim_MT6306_addMsg(len, adrs[0], adrs[1], SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK));
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), header[T1_NAD_INDEX]);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), pcb);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), len);
+
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COMDLEN_MTK), len);
+
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ // transfer by DMA if the count > 12, otherwise by MCU
+ SIM_SetTXTIDE(1, hw_cb);
+ if (len > 12)
+ {
+ //dbg_print("[DRV] LEN > 12, do dma autoTx2Rx...\r\n");
+ SIM_SetRXTIDE(1, hw_cb); //set rxtide = 0
+ //enable autoTX2RX
+ SIM_SetBits32((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T1TX2RXEN);
+ GET_NCACHED_USIM_DMA_BUF_INT(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)adrs); //TX buf 0
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA1Rx, pNoncachedRx); //RX buf 1
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(0) | HDCTRR_RX_SEL1(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(len) | HDCR_START1); //TX
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC1Rx, HDCR_XFER_SIZE0(USIM_DMA_MAX_SIZE) | HDCR_START1); //RX
+
+
+
+ USIM_TX_START_T1();
+
+ }
+ else if (USIM_IS_SBLOCK(pcb) && len == 1)
+ {
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), header[T1_INF_INDEX]);
+
+ /********************/
+ //dma config is moved from t1endhandler to here...
+ USIM_DMA_RX_TIDE();
+ GET_NCACHED_USIM_DMA_BUF_INT(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)pNoncachedRx);
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ //SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, (HDCR_XFER_SIZE0(4) | HDCR_START1));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(USIM_DMA_MAX_SIZE) | HDCR_START1);
+ /********************/
+ USIM_TX_START_T1();
+ }
+ else
+ {
+ kal_uint32 i;
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] LEN < 12, only do dma Rx...\r\n");
+#endif
+ for (i = 0; i < len; i++)
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), adrs[i]);
+
+ /********************/
+ //dma config is moved from t1endhandler to here...
+ USIM_DMA_RX_TIDE();
+ GET_NCACHED_USIM_DMA_BUF_INT(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx, pNoncachedRx);
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, (HDCR_XFER_SIZE0(USIM_DMA_MAX_SIZE) | HDCR_START1));
+
+ /*********************/
+ USIM_TX_START_T1();
+ }
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_STS_T1END);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+}
+/*
+1. send S blocks of request or response.
+2. if sending request, check if the response is correct.
+3. if sending response,
+4. EDC will be generated(tx) and removed(rx) by T1 controller
+
+id: PCB of the S block
+param: parameter of the S-block
+
+*/
+static usim_status_enum usim_send_s_block(usim_s_block_id_enum id, kal_uint8 param, sim_HW_cb *hw_cb)
+{
+ kal_uint8 *tx_buf, *rx_buf, len, t;
+ kal_bool is_resp;
+ kal_uint32 i;
+ //usim_dcb_struct *dcb = usim_dcb;
+ usim_dcb_struct *usim_dcb = NULL;
+// sim_MT6306_switchInfo *switch_CB = NULL;
+
+// switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ tx_buf = usim_dcb->header_tx;
+ rx_buf = usim_dcb->header_rx;
+ tx_buf[T1_NAD_INDEX] = USIM_NAD_DEFAULT;
+ tx_buf[T1_PCB_INDEX] = id;
+ is_resp = (((kal_uint32)id & PCB_S_RESP) != 0) ? KAL_TRUE : KAL_FALSE;
+ usim_dcb->cmd_state = (is_resp) ? (S_BlOCK_RESP_TX) : (S_BlOCK_REQ_TX);
+ if (id == IFS_REQ || id == WTX_REQ || id == IFS_RESP || id == WTX_RESP)
+ {
+ len = 4;
+ tx_buf[T1_LEN_INDEX] = 1;
+ }
+ else
+ {
+ len = 3;
+ tx_buf[T1_LEN_INDEX] = 0;
+ }
+ tx_buf[T1_INF_INDEX] = param;
+ usim_dcb->retry = 0;
+
+ while (usim_dcb->retry++ < 3)
+ {
+ usim_send_block(¶m, hw_cb);
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+ if (usim_dcb->ev_status == USIM_NO_ERROR)
+ {
+ if (!is_resp)
+ {
+ for (t = 0, i = 0; i < len; i++)
+ t += rx_buf[i] ^ tx_buf[i];
+ if (t != PCB_S_RESP)
+ continue;
+ }
+ break;
+ }
+ }
+ if (usim_dcb->retry == 4)
+ {
+ usim_deactivation(hw_cb);
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ return USIM_NO_ERROR;
+
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_rx_block_handler
+*
+* DESCRIPTION
+* 1. process the received block including I, R, and S blocks
+* 2. prepare the next sending block header in the usim_dcb->header_tx
+*
+* PARAMETERS
+ adrs: address of the data buffer
+
+* RETURNS
+ KAL_TRUE: a valid block is received
+ KAL_FALSE: an invalid block is received
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static kal_bool usim_rx_block_handler(kal_uint32 *adrs, sim_HW_cb *hw_cb)
+{
+ kal_uint8 pcb, len;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+
+ if (usim_dcb->header_rx[T1_NAD_INDEX] != 0)
+ {
+ return KAL_FALSE;
+ }
+ pcb = usim_dcb->header_rx[T1_PCB_INDEX];
+ len = usim_dcb->header_rx[T1_LEN_INDEX];
+ if (len > usim_dcb->ifsd) // 0 <= len <= IFSC (max 254)
+ return KAL_FALSE;
+#if defined(USIM_DEBUG)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "rx:%x %x %x", usim_dcb->header_rx[0], usim_dcb->header_rx[1], usim_dcb->header_rx[2]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (USIM_IS_SBLOCK(usim_dcb->header_rx[1]))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, " %x\r\n", usim_dcb->rx_buf[3]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+
+ }
+#endif
+ // USIM_INV_N(usim_dcb->ns);
+ if (USIM_IS_IBLOCK(pcb))
+ {
+ // I-block
+ if (pcb & PCB_I_RFU)
+ {
+ return KAL_FALSE;
+ }
+#if defined(USIM_DEBUG)
+ {
+ kal_uint32 i, log_size = 0;
+ for (i = 0; i < len; i++)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, " %x", usim_dcb->rx_buf[usim_dcb->rx_index + i]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ DRV_ICC_print_str("\r\n");
+ }
+#endif
+ if ((pcb & PCB_I_SEQ) != usim_dcb->nr)
+ {
+ return KAL_FALSE;
+ }
+ if (usim_dcb->header_rx[T1_LEN_INDEX] > usim_dcb->ifsd)
+ {
+ return KAL_FALSE;
+ }
+ if (usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ // must receive a S RESP not any other block
+ return KAL_FALSE;
+ }
+
+ usim_dcb->tx_chain = KAL_FALSE;
+ USIM_INV_N(usim_dcb->nr);
+ usim_dcb->retry = 0;
+ usim_dcb->tx_size -= usim_dcb->header_tx[T1_LEN_INDEX];
+ usim_dcb->tx_index += usim_dcb->header_tx[T1_LEN_INDEX];
+ usim_dcb->rx_size -= usim_dcb->header_rx[T1_LEN_INDEX];
+ usim_dcb->rx_index += usim_dcb->header_rx[T1_LEN_INDEX];
+ if (pcb & PCB_I_M)
+ {
+ // a chaining I-block received send a R-block
+ usim_dcb->rx_chain = KAL_TRUE;
+ USIM_MAKE_R_BLOCK_Multiple(PCB_R_STATUS_OK);
+ }
+ else
+ {
+ // command complete
+ usim_dcb->rx_chain = KAL_FALSE;
+ usim_dcb->retry = 0;
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ }
+ }
+ else if (USIM_IS_RBLOCK(pcb))
+ {
+ // R-block
+ if (usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ // must receive a S RESP not any other block
+ return KAL_FALSE;
+ }
+ if (len)
+ {
+ return KAL_FALSE;
+ }
+ if (usim_dcb->tx_chain && (pcb & PCB_R_STATUS) == 0)
+ {
+ // receive a err free R block
+ if (((pcb & PCB_R_SEQ) << 2) == usim_dcb->ns)
+ {
+ // send next chaining block
+ if (usim_dcb->abort == KAL_TRUE)
+ {
+ /* clear abort flag */
+ usim_dcb->abort = KAL_FALSE;
+
+ /* should re-send cmd */
+ usim_dcb->tx_size += usim_dcb->tx_index;
+ usim_dcb->tx_index = 0;
+ *adrs = (kal_uint32)(usim_dcb->tx_buf + usim_dcb->tx_index);
+
+ pcb = PCB_I_M;
+ len = usim_dcb->ifsc;
+ usim_dcb->cmd_state = I_BLOCK_M1_TX;
+
+ if (usim_dcb->ns)
+ pcb |= PCB_I_SEQ;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ usim_dcb->header_tx_bak[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx_bak[T1_LEN_INDEX] = len;
+ USIM_INV_N(usim_dcb->ns);
+
+ //usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ }
+ else if (usim_dcb->tx_size != 0)
+ {
+ // normal chaining case
+ usim_dcb->retry = 0;
+ usim_dcb->tx_size -= usim_dcb->ifsc;
+ usim_dcb->tx_index += usim_dcb->ifsc;
+ *adrs = (kal_uint32)(usim_dcb->tx_buf + usim_dcb->tx_index);
+ if (usim_dcb->tx_size <= usim_dcb->ifsc)
+ {
+ pcb = 0;
+ len = usim_dcb->tx_size;
+ usim_dcb->cmd_state = I_BLOCK_M0_TX;
+ }
+ else // txSize > IFSC
+ {
+ pcb = PCB_I_M;
+ len = usim_dcb->ifsc;
+ usim_dcb->cmd_state = I_BLOCK_M1_TX;
+ }
+ if (usim_dcb->ns)
+ pcb |= PCB_I_SEQ;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ usim_dcb->header_tx_bak[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx_bak[T1_LEN_INDEX] = len;
+ USIM_INV_N(usim_dcb->ns);
+ }
+ }
+ else
+ {
+ // sending the previous I block again
+ usim_dcb->retry++;
+ usim_dcb->cmd_state = usim_dcb->cmd_state_bak;
+ usim_dcb->header_tx[T1_PCB_INDEX] = usim_dcb->header_tx_bak[T1_PCB_INDEX];
+ usim_dcb->header_tx[T1_LEN_INDEX] = usim_dcb->header_tx_bak[T1_LEN_INDEX];
+ }
+ }
+ else
+ {
+ // error handling R-Block received
+ if ((pcb & PCB_R_SEQ) << 2 != (usim_dcb->ns))
+ {
+ // previous sending sequence
+ usim_dcb->retry++;
+ usim_dcb->cmd_state = usim_dcb->cmd_state_bak;
+ usim_dcb->header_tx[T1_PCB_INDEX] = usim_dcb->header_tx_bak[T1_PCB_INDEX];
+ usim_dcb->header_tx[T1_LEN_INDEX] = usim_dcb->header_tx_bak[T1_LEN_INDEX];
+ }
+ else
+ {
+ // next sending sequence
+ // send the previous R-block again
+ usim_dcb->retry = 0;
+ return KAL_FALSE;
+ }
+ }
+ }
+ else if (USIM_IS_SBLOCK(pcb))
+ {
+ // S-block(REQ)
+ if (USIM_IS_RESP(pcb))
+ {
+ // response (only resync response block will be received.)
+ if (pcb == RESYNC_RESP && usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ if (len != 0)
+ {
+ return KAL_FALSE;
+ }
+ // resync complete (the card is reset to the initial state)
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ usim_dcb->ns = 0;
+ usim_dcb->nr = 0;
+ usim_dcb->resync = KAL_TRUE;
+ usim_dcb->retry = 0;
+ // usim_dcb->ifsc = USIM_IFSC_DEFAULT;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+ }
+ else
+ {
+ // receiving a S-block of request
+ if (usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ // must receive a S RESP not any other block
+ return KAL_FALSE;
+ }
+
+ usim_dcb->cmd_state = S_BlOCK_RESP_TX;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb | PCB_S_RESP;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ if (len)
+ {
+ usim_dcb->header_tx[T1_INF_INDEX] = usim_dcb->header_rx[T1_INF_INDEX];
+ }
+ switch (pcb)
+ {
+ case RESYNC_REQ:
+ return KAL_FALSE;
+ //break; //remove for for RVCT warning
+ case IFS_REQ:
+ if (len != 1)
+ return KAL_FALSE;
+ usim_dcb->ifsc = usim_dcb->header_rx[T1_INF_INDEX];
+ break;
+ case ABORT_REQ:
+ if (len != 0)
+ return KAL_FALSE;
+ usim_dcb->retry = 0;
+ usim_dcb->abort = KAL_TRUE;
+ /*in the FTA test 7.3.11, after the abbort request, card will resend data, so we should reset rx_index to zero*/
+ usim_dcb->rx_index = 0;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC38, usim_dcb->tx_size, usim_dcb->tx_index, usim_dcb->rx_size, usim_dcb->rx_index, pcb);
+
+ break;
+ case WTX_REQ:
+ if (len != 1)
+ return KAL_FALSE;
+ usim_dcb->retry = 0;
+ // re-start the BWT( according to the spec, the timer should be restart after
+ // the WTX response has been sent.
+ usim_dcb->wtx = KAL_TRUE;
+ usim_dcb->wtx_m = usim_dcb->header_rx[T1_INF_INDEX];;
+ break;
+ default:
+ return KAL_FALSE;
+ }
+ }
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+
+ return KAL_TRUE;
+}
+/*************************************************************************
+* FUNCTION
+* usim_err_handler
+*
+* DESCRIPTION
+* 1. send R block to UICC to indicate the previous block is error at previous two retry.
+* 2. send S(RESYN) to UICC to recover the errors.
+* 3. deactivate the UICC
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+* usim_dcb->retry
+*
+*************************************************************************/
+static void usim_err_handler(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ // send R block
+ usim_dcb->retry++;
+ USIM_CLR_FIFO();
+ if (usim_dcb->retry < 3)
+ {
+ {
+ if (usim_dcb->ev_status == USIM_RX_INVALID)
+ {
+ USIM_MAKE_R_BLOCK_Multiple(PCB_R_STATUS_EDC_ERR);
+ }
+ else
+ {
+ USIM_MAKE_R_BLOCK_Multiple(PCB_R_STATUS_OTHER_ERR);
+ }
+ }
+ }
+ else if (usim_dcb->retry < 6)
+ {
+ // next level error handling => resync
+ USIM_MAKE_S_RESYNC_Multiple();
+ }
+ else
+ {
+ // deactivate
+ usim_deactivation(hw_cb);
+ }
+}
+
+void sim_PDNEnable_MT6306(sim_HW_cb *hw_cb)
+{
+ switch (hw_cb->mtk_baseAddr)
+ {
+ case SIM_base:
+ HDMA_PDN_SET(0); // channel 0
+ PDN_SET(PDN_USIM1);
+ break;
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ case SIM2_base:
+ HDMA_PDN_SET(1); // channel 1
+ PDN_SET(PDN_USIM2);
+ break;
+#endif
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+}
+
+void sim_PDNDisable_MT6306(sim_HW_cb *hw_cb)
+{
+ switch (hw_cb->mtk_baseAddr)
+ {
+ case SIM_base:
+ HDMA_PDN_CLR(0); // channel 0
+ PDN_CLR(PDN_USIM1);
+ break;
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ case SIM2_base:
+ HDMA_PDN_CLR(1); // channel 1
+ PDN_CLR(PDN_USIM2);
+ break;
+#endif
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+}
+/*************************************************************************
+* FUNCTION
+* usim_send_i_block
+*
+* DESCRIPTION
+* 1. send I block to UICC with length of ifsc including case 1~4.
+*
+* PARAMETERS
+* 1. txData: tx buffer containing command header optional with tx data.
+* 2. txSize: length of the tx data
+* 3. rxData: rx buffer (must inluding two extra one for sw1 and sw2)
+* 4. rxSize: length of the rx data except sw1|sw2
+*
+* RETURNS
+* status bytes(SW1|SW2), 0 means a physical error.
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static sim_status usim_send_i_block(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb)
+{
+ kal_uint8 pcb = 0, len = 0;
+ kal_uint32 count = 0, adrs = 0;
+ usim_status_enum status;
+ kal_uint16 sw = 0;
+ usim_dcb_struct *usim_dcb = NULL;
+// sim_MT6306_switchInfo *switch_CB = NULL;
+
+// switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ sim_PDNDisable_MT6306(hw_cb);
+ if (usim_dcb->clock_stop_en == KAL_TRUE)
+ {
+ if (usim_dcb->main_state == CLK_STOPPING_STATE)
+ {
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ }
+ else if (usim_dcb->main_state == CLK_STOPPED_STATE)
+ {
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) &= ~SIM_CTRL_HALT;
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);
+ usim_set_timeout(usim_dcb->etu_of_700, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ usim_set_timeout(0, hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+ }
+ }
+
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkRunning);
+
+ do
+ {
+ status = USIM_NO_ERROR;
+ usim_dcb->tx_index = 0;
+ usim_dcb->rx_index = 0;
+ usim_dcb->tx_buf = txData;
+ if (rxData == NULL)
+ usim_dcb->rx_buf = usim_dcb->sw;
+ else
+ usim_dcb->rx_buf = rxData;
+ usim_dcb->tx_size = *txSize;
+ usim_dcb->rx_size = *rxSize + 2; // include SW1, SW2
+ usim_dcb->retry = 0;
+ usim_dcb->abort = KAL_FALSE;
+ usim_dcb->resync = KAL_FALSE;
+ usim_dcb->rx_chain = KAL_FALSE;
+
+ count = *txSize;
+ adrs = (kal_uint32)usim_dcb->tx_buf;
+ if (count <= usim_dcb->ifsc)
+ {
+ pcb = 0;
+ len = count;
+ usim_dcb->tx_chain = KAL_FALSE;
+ usim_dcb->cmd_state = I_BLOCK_M0_TX;
+ }
+ else // txSize > IFSC
+ {
+ pcb = PCB_I_M;
+ len = usim_dcb->ifsc;
+ usim_dcb->tx_chain = KAL_TRUE;
+ usim_dcb->cmd_state = I_BLOCK_M1_TX;
+ }
+ if (usim_dcb->ns)
+ pcb |= PCB_I_SEQ;
+
+ usim_dcb->cmd_state_bak = usim_dcb->cmd_state;
+ usim_dcb->header_tx[T1_NAD_INDEX] = USIM_NAD_DEFAULT;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx_bak[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ usim_dcb->header_tx_bak[T1_LEN_INDEX] = len;
+ USIM_INV_N(usim_dcb->ns);
+
+ while (1)
+ {
+ usim_send_block((kal_uint8*)adrs, hw_cb);
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+ if (usim_dcb->ev_status == USIM_NO_ERROR)
+ {
+ // a complete block is received
+ if (usim_rx_block_handler(&adrs, hw_cb) == KAL_FALSE)
+ usim_err_handler(hw_cb);
+ }
+ else
+ {
+ usim_err_handler(hw_cb);
+ }
+ if (usim_dcb->main_state == MAIN_CMD_READY_STATE)
+ {
+ // command complete
+ *rxSize = usim_dcb->rx_index;
+ break;
+ }
+ if (DEACTIVATION_STATE == usim_dcb->main_state)
+ {
+ status = USIM_DEACTIVATED;
+ break;
+ }
+
+ }
+
+ /* [ALPS00411009][MT6589][in-house FTA][UICC] 7.3.11(UICC)
+ receive s-abort request and reply s-abort resp is defined by spec. it is not error
+ if(usim_dcb->abort == KAL_TRUE)
+ {
+ status = USIM_DATA_ABORT;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC42, sw, *txSize, *rxSize,status,usim_dcb->resync);
+ break;
+ }
+ */
+ if (usim_dcb->main_state == DEACTIVATION_STATE)
+ {
+ status = USIM_DEACTIVATED;
+ break;
+ }
+ }
+ while (usim_dcb->resync == KAL_TRUE);
+
+ usim_dcb->status = status;
+ if (status != USIM_NO_ERROR)
+ return SIM_SW_STATUS_FAIL;
+ // the *rxsize include the sw1 and sw1, the upper layer should prepare it.
+ *rxSize -= 2;
+ if (rxData == NULL)
+ {
+ sw = (kal_uint16)((usim_dcb->sw[0] << 8) | (usim_dcb->sw[1]));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC34, sw, *txSize, *rxSize, usim_dcb->sw[0], usim_dcb->sw[1]);
+
+ return sw;
+ }
+ sw = (rxData[*rxSize] << 8) | (rxData[*rxSize + 1]);
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC30, sw, *txSize, *rxSize, 0, 0);
+#endif
+ return sw;
+
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_InterfaceCheck
+*
+* DESCRIPTION
+* do platform sim interface support check, mainly on checking whether this platform support second sim interface
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+// Remove above temp code
+void static usim_InterfaceCheck(sim_HW_cb *hw_cb)
+{
+ //dbg_print("\r\n[%s] Interface:%d,GEMINI_PLUS:%d\r\n",__func__,hw_cb->simInterface,GEMINI_PLUS);
+#if defined(GEMINI_PLUS)
+ if (hw_cb->simInterface > GEMINI_PLUS - 1)
+ //if(hw_cb->simInterface > 3)
+#else
+ if (hw_cb->simInterface > 3)
+#endif
+ SIM_DEBUG_ASSERT(0);
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_update_sim_to_ready
+*
+* DESCRIPTION
+* 1. update the ATR informations from usim_dcb into SimCard
+* to make sim(t=0) driver work..
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+* SimCard
+* TOUTValue
+*
+*************************************************************************/
+void static usim_update_sim_to_ready(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ Sim_Card *SimCard;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->app_proto = usim_dcb->app_proto;
+ SimCard->State = SIM_PROCESSCMD;
+ SimCard->Data_format = usim_dcb->dir;
+ if (usim_dcb->power == CLASS_B_30V)
+ SimCard->Power = SIM_30V;
+ else if (usim_dcb->power == CLASS_C_18V)
+ SimCard->Power = SIM_18V;
+ SimCard->SIM_ENV = usim_dcb->sim_env;
+ SimCard->Speed = usim_dcb->speed;
+ SimCard->clkStop = usim_dcb->clock_stop_en;
+ if (usim_dcb->clock_stop_type == CLOCK_STOP_HIGH)
+ SimCard->clkStopLevel = KAL_TRUE;
+ else if (usim_dcb->clock_stop_type == CLOCK_STOP_LOW)
+ SimCard->clkStopLevel = KAL_FALSE;
+ SimCard->sim_card_speed = (sim_card_speed_type)usim_dcb->card_speed;
+ SimCard->TOUTValue = usim_dcb->WWT >> 2;
+ SimCard->TOUT_Factor = usim_dcb->Di;
+ SimCard->Fi = usim_dcb->Fi;
+
+ SimCard->power_class = usim_dcb->power_class;
+#if defined(SIM_DRV_IC_USB)
+ SimCard->isIcUsb = usim_dcb->isIcUsb;
+ SimCard->TB15 = usim_dcb->TB15;
+ SimCard->isIcUsbRecPPS = usim_dcb->isIcUsbRecPPS;
+ SimCard->uart_sim_ccci_handle = usim_dcb->uart_sim_ccci_handle;
+ SimCard->isPrefer3V = usim_dcb->isPrefer3V;
+ SimCard->forceISO = usim_dcb->forceISO;
+#endif
+ SimCard->previous_state = usim_dcb->previous_state;
+ SimCard->atr_count = usim_dcb->atr_count;
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ SimCard->poll_sim_2s = usim_dcb->poll_sim_2s;
+#endif
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Init
+*
+* DESCRIPTION
+* 1. It is the initialization function of usim driver
+* 2. It shall be called only once.
+* 3. It gets the customization data of borad-supported voltage.
+* 4. It initialize the structure of usim control block .
+* 5. It get a GPT handler, a dma port,and register lisr, hisr, a event groug
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void L1usim_Init(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb, *peer_usim_dcb;
+ kal_uint32 simInterface;
+ kal_uint32 hwCtrl;
+ sim_HW_cb *peerHWCb;
+ sim_MT6306_switchInfo *switch_CB;
+ kal_uint8 DMA_channel = 0;
+#if defined(SIM_DRV_IC_USB)
+ UART_CTRL_OPEN_T data;
+ kal_uint8 status;
+#endif
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+#if defined(SIM_DRV_GEMINI_WITH_MT6306)
+ SIM_DEBUG_ASSERT(0);
+#endif
+ simInterface = hw_cb->simInterface;
+ usim_dcb = GET_USIM_CB(simInterface);
+ peer_usim_dcb = GET_USIM_CB(peerHWCb->simInterface);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ sim_addMsg(SIM_INIT_USIM, hw_cb->simInterface, 0, 0);
+
+ hw_cb->forceOn26M = KAL_TRUE;
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ {
+ usim_dcb->sim_env = SIM_GetCurrentEnv(hw_cb->simInterface);
+ usim_dcb->dir = USIM_DIRECT;
+ usim_dcb->speed = SPEED_372;
+ usim_dcb->clock_stop_en = KAL_FALSE;
+ usim_dcb->clock_stop_type = CLOCK_STOP_UNKONW;
+ usim_dcb->phy_proto = T1_PROTOCOL;
+ usim_dcb->warm_rst = KAL_FALSE;
+ usim_dcb->rx_size = 0;
+ usim_dcb->rx_buf = NULL;
+ usim_dcb->tx_size = 0;
+ usim_dcb->tx_buf = NULL;
+ usim_dcb->Fi = FI_DEFAULT;
+ usim_dcb->Di = DI_DEFAULT;
+ usim_dcb->header_tx[0] = NAD;
+ usim_dcb->ts_hsk_en = KAL_TRUE;
+ usim_dcb->WWT = INIT_WWT_T0;
+ usim_dcb->etu_of_1860 = (1860 / 32);
+ usim_dcb->etu_of_700 = (700 / 32);
+ usim_dcb->present = KAL_TRUE;
+ usim_dcb->power_class = UNKNOWN_POWER_CLASS;
+ usim_dcb->T0_support = KAL_FALSE;
+ usim_dcb->T1_support = KAL_FALSE;
+ usim_dcb->reset_mode = USIM_RESET_NEGOTIABLE;
+ usim_dcb->TB15 = 0;
+ usim_dcb->hasPowerClass = KAL_FALSE;
+
+#if defined(SIM_DRV_IC_USB)
+ usim_dcb->icusb_state = SIM_ICUSB_INIT;
+ SIM_icusb_init(hw_cb);
+#endif
+ usim_dcb->previous_state = 0;
+ usim_dcb->atr_count = 0;
+ /*there will be no enable enhanced_speed function, we should set this myself*/
+ usim_dcb->high_speed_en = KAL_TRUE;
+ usim_dcb->stopSimClkInEndOfAction = KAL_FALSE;
+
+ // Set GDMA to MD Side. USIM0, USIM1 two bits
+ usim_dcb->dma_config.BURST_SIZE = HDCTRR_BST_SIZE_16;
+ usim_dcb->dma_config.DEV_BUS_WIDTH = HDCTRR_BUS_WIDTH_8;
+ usim_dcb->dma_config.MEM_BUS_WIDTH = HDCTRR_BUS_WIDTH_32;
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+ if (MTK_SIMIF0 == hwCtrl)
+ DMA_channel = 0;
+ else
+ DMA_channel = 1;
+ usim_dcb->dma_config.channel = DMA_channel;
+ usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA0R0 : REG_HDMA_HPRGA0R1;
+ usim_dcb->dma_config.ADDR_HDMA_HPRGA1Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA1R0 : REG_HDMA_HPRGA1R1;
+ usim_dcb->dma_config.ADDR_HDMA_HDCTRRx = (DMA_channel == 0) ? REG_HDMA_HDCTRR0 : REG_HDMA_HDCTRR1;
+ usim_dcb->dma_config.ADDR_HDMA_HDC0Rx = (DMA_channel == 0) ? REG_HDMA_HDC0R0 : REG_HDMA_HDC0R1;
+ usim_dcb->dma_config.ADDR_HDMA_HDC1Rx = (DMA_channel == 0) ? REG_HDMA_HDC1R0 : REG_HDMA_HDC1R1;
+
+
+ if (NULL != peer_usim_dcb->event)
+ usim_dcb->event = peer_usim_dcb->event;
+
+ if (usim_dcb->event == NULL)
+ {
+ //hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+ if (MTK_SIMIF0 == hwCtrl)
+ {
+ usim_dcb->event = kal_create_event_group("USIM_EV");
+ }
+ else if (MTK_SIMIF1 == hwCtrl)
+ {
+ usim_dcb->event = kal_create_event_group("USIM_EV2");
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ if ((kal_uint32)hw_cb != hwCbArray[hw_cb->simInterface])
+ SIM_DEBUG_ASSERT(0);
+ if (IRQ_USIM0_CODE != hw_cb->mtk_lisrCode)
+ SIM_DEBUG_ASSERT(0);
+
+ /*
+ #if defined(__UNIFIED_ISR_LEVEL__)
+ DRV_Register_HISR(DRV_USIM_HSIR_ID, usim_hisr);
+ #endif
+ */
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (usim_hisrid == NULL)
+ {
+ usim_hisrid = kal_init_hisr(USIM_HISR);
+ }
+#endif
+ if ((void *)usim_dcb->gpt_handle == NULL)
+ DRV_ICC_GPTI_GetHandle(&usim_dcb->gpt_handle);
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+#if defined(SIM_DRV_IC_USB)
+ //only SIM1 support ICUSB
+ if (usim_dcb->uart_sim_ccci_handle == (kal_uint32)NULL && sim_get_app_from_logicalNum(simInterface) == (kal_uint32) SIM_ICC_APPLICATION_PHONE1)
+ {
+ usim_dcb->forceISO = KAL_FALSE;
+ data.u4OwenrId = MOD_SIM;
+ usim_dcb->uart_sim_ccci_handle = DclSerialPort_Open(uart_port_sim_ccci, 0);
+ status = DclSerialPort_Control(usim_dcb->uart_sim_ccci_handle, SIO_CMD_OPEN, (DCL_CTRL_DATA_T*)&data);
+
+ if (status != STATUS_OK)
+ SIM_DEBUG_ASSERT(0);
+
+ kal_bool indication = KAL_FALSE;
+ DclSerialPort_Control(usim_dcb->uart_sim_ccci_handle, TTY_CMD_SET_INDICATION, (DCL_CTRL_DATA_T*) &indication);
+ }
+#endif
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ usim_dcb->poll_sim_2s = KAL_FALSE;
+#endif
+ }
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+ if ((kal_uint32)hw_cb != hwCbArray[hw_cb->simInterface])
+ SIM_DEBUG_ASSERT(0);
+ if (IRQ_USIM1_CODE != hw_cb->mtk_lisrCode)
+ SIM_DEBUG_ASSERT(0);
+ /*
+ #if defined(__UNIFIED_ISR_LEVEL__)
+ DRV_Register_HISR(DRV_USIM2_HSIR_ID, usim_hisr2);
+ #endif
+ */
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (usim2_hisrid == NULL)
+ {
+ usim2_hisrid = kal_init_hisr(USIM2_HISR);
+ }
+#endif
+ if ((void *)usim_dcb->gpt_handle == NULL)
+ DRV_ICC_GPTI_GetHandle(&usim_dcb->gpt_handle);
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+ }
+#endif
+ else
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (0 != peer_usim_dcb->gpt_handle)
+ usim_dcb->gpt_handle = peer_usim_dcb->gpt_handle;
+
+
+ /*IRQ related setting check */
+ if (IRQ_USIM0_CODE != hw_cb->mtk_lisrCode
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ && IRQ_USIM1_CODE != hw_cb->mtk_lisrCode
+#endif
+ )
+ SIM_DEBUG_ASSERT(0);
+ //IRQUnmask(IRQ_SIM_CODE);
+ }
+
+ // reset these value no matter cold or warm reset
+ usim_dcb->simInitialized=KAL_FALSE;
+ usim_dcb->main_state = ACTIVATION_STATE;
+ usim_dcb->ifsc = USIM_IFSC_DEFAULT;
+ usim_dcb->ifsd = USIM_IFSD_DEFAULT;
+ usim_dcb->ns = 0;
+ usim_dcb->nr = 0;
+
+
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, usim_lisr_MT6306,"USIM_Lisr");
+
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+
+ switch_CB->usim_waitHisrCb_MT6306 = hw_cb;
+ sim_MT6306_LISRStateChange(hw_cb, sim_MT6306_LISRUsim);
+
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ IRQUnmask(hw_cb->mtk_lisrCode);
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_PowerOff
+*
+* DESCRIPTION
+* 1. perform the deactivation to UICC
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_PowerOff(sim_HW_cb *hw_cb)
+{
+#if defined(SIM_DRV_IC_USB)
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ sim_addMsg(0xE012, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+
+ //sim_PDNDisable_MT6306(hw_cb);
+ usim_deactivation(hw_cb);
+
+ //sim_PDNEnable_MT6306(hw_cb);
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Reset
+*
+* DESCRIPTION
+* 1. Reset the sim card and parse the ATR and perform the PTS(optional) and
+ enter the command ready mode
+* 2. First time it is a cold reset, second it's a warm reset
+* 3. If the ExpectVolt equal to the current volt, perform a warm reset.
+ Otherwise perform a cold reset.
+* 4. Finally, S-block of IFS request is sent the UICC to configure the IFSD
+*
+* PARAMETERS
+ 1. ExpectVolt: application layer give a expected power class
+
+* RETURNS
+* USIM_VOLT_NOT_SUPPORT: Valid TS is received
+* KAL_FALSE: Valid TS is not received, card is not present or not supported
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static usim_status_enum L1usim_Reset(usim_power_enum ExpectVolt, usim_power_enum *ResultVolt, sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry = 0;
+ usim_dcb_struct *usim_dcb = NULL;
+ kal_uint32 ori_ExpectVolt = (kal_uint32) ExpectVolt, log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+#if defined(SIM_DRV_IC_USB)
+ usim_dcb->isPrefer3V = KAL_FALSE;
+PREFER_3V:
+ if (usim_dcb->isPrefer3V == KAL_TRUE)
+ {
+ sim_addMsg(0xE002, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ ExpectVolt = CLASS_B_30V;
+ }
+PREFER_ORI:
+#endif
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] Interface:%d:, ExpectVolt:%d\n\r", __func__, hw_cb->simInterface, ExpectVolt);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ IRQMask(hw_cb->mtk_lisrCode);
+ sim_PDNDisable_MT6306(hw_cb);
+ SIM_DisAllIntr();
+ usim_set_timeout(0, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, 0xFFFF);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+
+
+ if (usim_dcb->clock_stop_en == KAL_TRUE && usim_dcb->warm_rst == KAL_TRUE &&
+ usim_dcb->phy_proto == T1_PROTOCOL)
+ {
+ if (usim_dcb->main_state == CLK_STOPPING_STATE)
+ {
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ }
+ else if (usim_dcb->main_state == CLK_STOPPED_STATE)
+ {
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) &= ~SIM_CTRL_HALT;
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);
+ usim_set_timeout(usim_dcb->etu_of_700, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ USIM_WAIT_EVENT_MT6306(hw_cb);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkRunning);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ usim_set_timeout(0, hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+ }
+ }
+ L1usim_Init(hw_cb);
+ if (usim_check_input_volt(ExpectVolt, hw_cb) == KAL_FALSE)
+ return USIM_VOLT_NOT_SUPPORT;
+ // 1. Activate the USIM interface
+ SIM_DisAllIntr();
+ SIM_DMA_STOP(usim_dcb->dma_config.channel);
+
+ usim_set_speed(SPEED_372, hw_cb);
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+ /*
+ if(TS_HSK_ENABLE)
+ {
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ }
+ */
+ // if corrupted ATRs are received, retry 3 times
+ for (retry = 0; retry < ATR_RETRY; retry++)
+ {
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE003, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ if (usim_select_power(ExpectVolt, hw_cb) == KAL_FALSE)
+ {
+ dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, "[%s] interface:%d, retry %d\n\r", __FUNCTION__, hw_cb->simInterface, retry);
+ if (usim_dcb->warm_rst == KAL_TRUE)
+ {
+ return USIM_ATR_ERR;
+ }
+ if (usim_dcb->ts_hsk_en == KAL_TRUE)
+ {
+ usim_dcb->ts_hsk_en = KAL_FALSE;
+ }
+ else
+ {
+ dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, "[%s] interface:%d -> USIM_NO_INSERT\r", __FUNCTION__, hw_cb->simInterface);
+ sim_dump_reg(0x0, hw_cb);
+ sim_dump_MT6306(hw_cb);
+
+ return USIM_NO_INSERT;
+ }
+ //continue;
+ }
+ else if (usim_process_ATR(hw_cb) == USIM_NO_ERROR)
+ {
+ break;
+ }
+
+ ExpectVolt = usim_dcb->power;
+ }
+
+ if (retry == ATR_RETRY)
+ return USIM_ATR_ERR;
+ *ResultVolt = usim_dcb->power;
+ // 3. Process PTS
+ //if(usim_dcb->reset_mode == USIM_RESET_NEGOTIABLE)
+ {
+
+ if (usim_process_PTS(hw_cb) == KAL_FALSE)
+ {
+ for (retry = 0; retry < 3; retry++)
+ {
+#if !defined(ATEST_DRV_ENABLE)
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] retry PTS %d\n\r", hw_cb->simInterface, retry);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (usim_select_power(ori_ExpectVolt, hw_cb) == KAL_FALSE) continue;
+ if (usim_process_ATR(hw_cb) != USIM_NO_ERROR) continue;
+ if (usim_process_PTS(hw_cb) == KAL_TRUE)
+ {
+ break;
+ }
+ else if (retry == 2)
+ {
+ return USIM_PTS_FAIL;
+ }
+ }
+ }
+ if (retry == 3) return USIM_PTS_FAIL;
+ // 4. Configure the IFSD
+ if (usim_dcb->phy_proto == T1_PROTOCOL)
+ {
+ if (usim_send_s_block(IFS_REQ, USIM_IFSD_MAX, hw_cb) == USIM_NO_ERROR)
+ {
+ /*if we failed to send S block when negotiating IFSD and deactivate the card, we should report the reset status correctly*/
+ if (DEACTIVATION_STATE == usim_dcb->main_state)
+ return USIM_S_BLOCK_FAIL;
+
+ usim_dcb->ifsd = USIM_IFSD_MAX;
+ }
+ }
+ }
+ // NOTE: can't turn off the PDN bit of SIM interface over, it will cause
+ // the SIM behavior abnormal.
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ usim_dcb->cmd_state = USIM_CMD_READY;
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && usim_dcb->forceISO == KAL_FALSE)
+ {
+ kal_uint32 icusbStatus = 0;
+ sim_addMsg(0xE00C, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+
+ // power off ISO mode
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)&SIM_CTRL_SIMON)
+ {
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);
+ USIM_CLR_FIFO();
+
+ // tell USB to reset MAC & PHY
+ icusbStatus = SIM_icusb_disableSession(hw_cb);
+ if (icusbStatus == SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE005, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+
+ // Need delay of at least 10ms before next activate operation
+ kal_sleep_task(10);
+
+ // tell USB to reset MAC & PHY
+ icusbStatus = SIM_icusb_disconnectDone(hw_cb);
+ if (icusbStatus == SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE007, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+ }
+ usim_dcb->isPrefer3V = KAL_FALSE;
+ //notify AP libusb
+ if (SIM_icusb_setVolt(hw_cb) == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc0);
+ sim_addMsg(0xE024, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+
+ icusbStatus = SIM_icusb_enableSession(hw_cb);
+ if (icusbStatus == SIM_ICUSB_ACK_PREFER_3V)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc1);
+ L1usim_PowerOff(hw_cb);
+ usim_dcb->isPrefer3V = KAL_TRUE;
+ sim_addMsg(0xE00F, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto PREFER_3V;
+ }
+ else if (icusbStatus == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc2);
+ sim_addMsg(0xE025, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+ if (SIM_icusb_powerOn(hw_cb) == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc3);
+ sim_addMsg(0xE026, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC66, usim_dcb->isIcUsbRecPPS, usim_dcb->main_state, usim_dcb->isIcUsb, usim_dcb->icusb_state, 0);
+ }
+#if defined SIM_DRV_IC_USB_DBG_2
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xaaad);
+#endif
+#endif
+ return USIM_NO_ERROR;
+
+#if defined(SIM_DRV_IC_USB)
+LEAVE_ICUSB_INIT:
+ usim_dcb->forceISO = KAL_TRUE;
+ usim_dcb->isIcUsb = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xaaae);
+ if (usim_dcb->isPrefer3V == KAL_TRUE || usim_dcb->power == CLASS_B_30V) goto PREFER_3V;
+ else goto PREFER_ORI;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* L1usim_Get_Card_Info
+*
+* DESCRIPTION
+* get the card informations
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_Get_Card_Info(sim_info_struct *info, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ SIM_DEBUG_ASSERT(usim_dcb->main_state >= ATR_STATE);
+ info->power = usim_dcb->power;
+ info->speed = usim_dcb->speed;
+ info->clock_stop = usim_dcb->clock_stop_type;
+ info->app_proto = usim_dcb->app_proto;
+ info->phy_proto = usim_dcb->phy_proto;
+ info->T0_support = usim_dcb->T0_support;
+ info->T1_support = usim_dcb->T1_support;
+ info->hist_index = usim_dcb->hist_index;
+ info->ATR = usim_dcb->ATR_data;
+ info->TAiExist = usim_dcb->TAiExist;
+ info->ATR_length = usim_dcb->ATR_index;
+ info->isSW6263 = usim_dcb->isSW6263;
+ info->TB15 = usim_dcb->TB15;
+ info->hasPowerClass = usim_dcb->hasPowerClass;
+ info->PowerClass = usim_dcb->PowerClass;
+}
+
+/*************************************************************************
+* FUNCTION
+* L1usim_Enable_Enhanced_Speed
+*
+* DESCRIPTION
+* 1. enable the enhance speed mode if UICC supports
+* 2. shall be called before reset after init
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ //ASSERT(usim_dcb->main_state == IDLE_STATE);
+ usim_dcb->high_speed_en = enable;
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Set_ClockStopMode
+*
+* DESCRIPTION
+* setup the clock stop mode according to the ATR information.
+*
+* PARAMETERS
+* mode: clock stop mode
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_Set_ClockStopMode(usim_clock_stop_enum mode, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ Sim_Card *SimCard;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ kal_uint32 t1 = 0;
+
+ if (mode & CLOCK_STOP_MSK)
+ {
+ // calculate the clock to etu for 1860 and 700
+ usim_dcb->etu_of_1860 = (1860 / (usim_dcb->Fi / usim_dcb->Di)) + 10; // longer than spec.
+ usim_dcb->etu_of_700 = (700 / (usim_dcb->Fi / usim_dcb->Di)) + 5;
+ usim_dcb->clock_stop_en = KAL_TRUE;
+ if (mode == CLOCK_STOP_ANY)
+ usim_dcb->clock_stop_type = CLOCK_STOP_LOW;
+ else
+ usim_dcb->clock_stop_type = mode;
+ if (CLOCK_STOP_HIGH == mode)
+ SimCard->clkStopLevel = KAL_TRUE;
+ else
+ SimCard->clkStopLevel = KAL_FALSE;
+ SimCard->clkStop = KAL_TRUE;
+ t1 = SIM_GetCurrentTime();
+ while ((SIM_GetCurrentTime() - t1) < 20); // delay 600 clock cycles (600us)
+ //sim_MT6306_clkStopper(hw_cb);
+ }
+ else
+ {
+ usim_dcb->clock_stop_en = KAL_FALSE;
+ SimCard->clkStop = KAL_FALSE;
+
+ }
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Cmd
+*
+* DESCRIPTION
+* usim T=1 command
+*
+* PARAMETERS
+* 1. txData: tx buffer containing command header optional with tx data.
+* 2. txSize: length of the tx data
+* 3. rxData: rx buffer (must inluding two extra one for sw1 and sw2)
+* 4. rxSize: length of the rx data except sw1|sw2
+*
+* RETURNS
+* status bytes(SW1|SW2), 0 means a physical error.
+
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static sim_status L1usim_Cmd(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+#ifdef SIM_CACHED_SUPPORT
+ sim_status SW;
+ kal_uint8 *pNoncachedTx, *pNoncachedRx;
+#endif
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /*
+ if(usim_dcb->main_state != MAIN_CMD_READY_STATE && usim_dcb->main_state != CLK_STOPPED_STATE)
+ {
+ kal_prompt_trace(MOD_SIM,"[SIM_DRV]:L1usim_Cmd is called at err state");
+ return SIM_SW_STATUS_FAIL;
+ }
+ */
+ if (rxData == NULL && *rxSize != 0)
+ SIM_DEBUG_ASSERT(0);
+ if (usim_dcb->cmd_case == usim_case_1)
+ {
+ // for case1, only 4 bytes need to be transfer
+ *txSize = 4;
+ *rxSize = 0;
+ }
+ /*
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL1, __LINE__,
+ hw_cb->simInterface, txData[1], (kal_uint32)rxData, *txSize,
+ *rxSize, usim_dcb->cmd_case
+ );
+ */
+
+#ifdef SIM_CACHED_SUPPORT
+ if (INT_QueryIsCachedRAM(txData, *txSize))
+ {
+ GET_NCACHEDTX_P(pNoncachedTx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ kal_mem_cpy(pNoncachedTx, txData, *txSize);
+ }
+ else
+ {
+ pNoncachedTx = txData;
+ }
+
+ if (rxData != NULL && INT_QueryIsCachedRAM(rxData, 512))
+ {
+ GET_NCACHEDRX_P(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ }
+ else
+ {
+ pNoncachedRx = rxData;
+ }
+
+ SW = usim_send_i_block((kal_uint8 *)pNoncachedTx, txSize, (kal_uint8 *)pNoncachedRx, rxSize, hw_cb);
+
+ if (rxData != NULL && INT_QueryIsCachedRAM(rxData, 512))
+ {
+ if (0 != *rxSize)
+ {
+ if (512 < *rxSize)
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ kal_mem_cpy(rxData, pNoncachedRx, *rxSize);
+ }
+ }
+
+ return SW;
+#endif
+
+#ifdef SIM_CACHED_SUPPORT_WRITE_THROUGH_SERIES
+ invalidate_wt_cache((kal_uint32)rxData, *rxSize);
+#endif
+
+#ifndef SIM_CACHED_SUPPORT
+ return usim_send_i_block(txData, txSize, rxData, rxSize, hw_cb);
+#endif
+}
+/*************************************************************************
+* FUNCTION
+* usim_TimeOutHandler
+*
+* DESCRIPTION
+* Callback function of gpt timer, and launched while MSDC busy for a while
+
+*
+* PARAMETERS
+*
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*
+*************************************************************************/
+static void usim_gpt_timeout_handler(void *parameter)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = (usim_dcb_struct *)parameter;
+
+ /*
+ kal_prompt_trace(MOD_SIM,"[SIM_DRV]: usim gpt timeout !");
+ */
+ usim_dcb->status = USIM_GPT_TIMEOUT;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+}
+
+//------------------------------------------------------------------------//
+// General interfaces of sim driver
+//------------------------------------------------------------------------//
+/*************************************************************************
+* FUNCTION
+* L1sim_Reset_All
+*
+* DESCRIPTION
+* 1. general interface of sim reset for T=0 and T=1
+* 2. it support warm reset for UICC
+* 3. first enable error repeat handling process to cover parity error at ATR, if not
+* success, disable it.
+* 4. for SIM protocol with T=0, additional reset will be perfromed.
+*
+* PARAMETERS
+* ExpectVolt: expected input voltage for the SIM card.
+* ResultVolt: finally used power voltage.
+* warm: specify warm reset for UICC
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+usim_status_enum L1sim_Reset_MT6306(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, sim_HW_cb *hw_cb)
+{
+ usim_status_enum status;
+ usim_dcb_struct *usim_dcb;
+ Sim_Card *SimCard;
+ sim_MT6306_switchInfo *switch_CB;
+ kal_uint32 log_size = 0;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] interface:%d", __func__, hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ /*we should do platform check here, not allow to access interface 2 on one-SIM platform*/
+ usim_InterfaceCheck(hw_cb);
+
+ /*we should additionally check whether this interface has owner or not*/
+ if (0 != usim_dcb->ownerTask && kal_get_current_thread_ID() != usim_dcb->ownerTask)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC122, SIM_ASSERT_REASON_WRONG_OWNERTASK, SIM_ASSERT_OWNER_SIMTASK,
+ (kal_uint32) usim_dcb->ownerTask, (kal_uint32) kal_get_current_thread_ID(), 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ sim_MT6306_clkStopTimerStop(hw_cb);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->needStopGptISR = KAL_TRUE;
+ while (1)
+ {
+ Data_Sync_Barrier();
+ if (hw_cb->waitGptISR_MT6306 == 0) break;
+ kal_give_spinlock(hw_cb->spinlockid);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for GPT ISR:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, hw_cb->waitGptISR_MT6306, drv_get_current_time());
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ }
+#if defined(LPWR_SLIM)
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ sim_MT6306_change(hw_cb, sim_MT6306_eventReset);
+ MT6306_RACE_PROTECT(sim_MT6306_protectionRst);
+
+ if (warm == KAL_FALSE)
+ {
+ //TS_HSK_ENABLE = KAL_TRUE;
+ status = L1usim_Reset(ExpectVolt, ResultVolt, hw_cb);
+ usim_dcb->ownerTask = kal_get_current_thread_ID();
+ if (status < 0)
+ {
+ //kal_sprintf(hw_cb->dbgStr,"L1usim_Reset failed!(%d, %d)",status, hw_cb->simInterface);
+ //kal_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RESET_FAIL, status, hw_cb->simInterface, (kal_uint32)usim_dcb->ev_status, (kal_uint32)ExpectVolt, (kal_uint32)ResultVolt);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RESET_FAIL, SIM_Reg(SIM0_BASE_ADDR_MTK + 0x08), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x20), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x24), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x34), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x60));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RESET_FAIL, SIM_Reg(SIM0_BASE_ADDR_MTK + 0x74), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x70), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x00), 0);
+ //L1sim_PowerOff_All(simInterface);
+ L1usim_PowerOff(hw_cb);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateDeactiavate);
+ if (status == USIM_NO_INSERT)
+ usim_dcb->present = KAL_FALSE;
+ MT6306_RACE_RELEASE(sim_MT6306_protectionRst);
+ return status;
+ /*
+ TS_HSK_ENABLE = KAL_FALSE;
+ status = L1usim_Reset(ExpectVolt, ResultVolt);
+ if(status <0)
+ {
+ L1sim_PowerOff_All();
+ MT6306_RACE_RELEASE(sim_MT6306_protectionRst);
+ return status;
+ }
+ */
+ }
+ else
+ {
+ kal_uint32 i;
+ kal_char *p;
+
+
+ /*reset successfully, record its IR or AL state*/
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & SIM_ATRSTA_AL)
+ {
+ sim_MT6306_setCardType(hw_cb, sim_MT6306_cardTypeAL);
+ }
+ else if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & SIM_ATRSTA_IR)
+ {
+ //kal_print("IR card !!!!!\n\r");
+ DRV_ICC_print(hw_cb, SIM_PRINT_IR_CARD, 0, 0, 0, 0, 0);
+ sim_MT6306_setCardType(hw_cb, sim_MT6306_cardTypeIR);
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+
+ if (USIM_DIRECT != usim_dcb->dir)
+ {
+ }
+
+ p = hw_cb->dbgStr;
+ log_size = kal_sprintf(p, "[SIM_DRV:%d]:SIM ATR= ", hw_cb->simInterface);
+ p += strlen(p);
+ for (i = 0; i < usim_dcb->ATR_index; i++)
+ {
+ log_size += kal_sprintf(p, "%02X", usim_dcb->ATR_data[i]);
+ p += 2;
+ }
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkRunning);
+#ifdef ATEST_DRV_ENABLE
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ATR,hw_cb->dbgStr);
+#endif
+
+ //kal_sprintf(hw_cb->dbgStr,"[SIM_DRV]: L1usim_Reset OK v: %d, T: %d, app: %d, speed:%d",
+ // usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RST_OK, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed, 0);
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]L1usim_Reset OK voltage: %d, T: %d, app: %d, speed:%d\n\r", hw_cb->simInterface, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_BASIC_SIM_INFO,hw_cb->simInterface, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed);
+#endif
+
+
+ // reset successfully, record its IR or AL state
+ if (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & SIM_ATRSTA_AL)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "AL card, convention: %x\n\r", usim_dcb->ATR_data[0]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else if (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & SIM_ATRSTA_IR)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "IR card, convention: %x\n\r", usim_dcb->ATR_data[0]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+
+ kal_uint8 s;
+ kal_uint8 power;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ L1sim_Init_MT6306(hw_cb);
+ if (usim_dcb->power == CLASS_C_18V)
+ power = SIM_18V;
+ else
+ power = SIM_30V;
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ s = sim_Reset_MT6306(power, NULL, NULL, hw_cb);
+#ifdef SIM_REMOVE_ATR_ASSERT
+ if (SIM_NO_ERROR != s)
+ {
+ usim_dcb->present = KAL_FALSE;
+ status = USIM_NO_INSERT;
+ MT6306_RACE_RELEASE(sim_MT6306_protectionRst);
+ return status;
+ }
+#endif
+ SIM_DEBUG_ASSERT(s == SIM_NO_ERROR);
+#ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+ {
+ /* For [MAUI_01321659] begin */
+ if (SimCard->Power == SIM_18V)
+ *ResultVolt = CLASS_C_18V;
+ else if (SimCard->Power == SIM_30V)
+ *ResultVolt = CLASS_B_30V;
+ else
+ SIM_DEBUG_ASSERT(0);
+ } /* For [MAUI_01321659] end */
+#endif
+ }
+ else
+ usim_update_sim_to_ready(hw_cb);
+
+ sim_MT6306_recordDirectionBaud(hw_cb);
+ SimCard->mod_id = kal_get_active_module_id();
+ SimCard->mod_extq_cap = msg_get_task_extq_capacity(SimCard->mod_id);
+ }//usim_dcb->phy_proto == T0_PROTOCOL
+ else
+ {
+ sim_MT6306_recordDirectionBaud(hw_cb);
+ }
+ }
+ else
+ {
+ if (usim_dcb->app_proto == USIM_PROTOCOL)
+ {
+ usim_dcb->warm_rst = KAL_TRUE;
+ status = L1usim_Reset(usim_dcb->power, ResultVolt, hw_cb);
+ usim_dcb->warm_rst = KAL_FALSE;
+ if (status < 0)
+ {
+ //L1sim_PowerOff_All(simInterface);
+ L1usim_PowerOff(hw_cb);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateDeactiavate);
+ MT6306_RACE_RELEASE(sim_MT6306_protectionRst);
+ return status;
+ }
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkRunning);
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ kal_uint8 power = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ L1sim_Init_MT6306(hw_cb);
+ if (usim_dcb->power == CLASS_C_18V)
+ power = SIM_18V;
+ else
+ power = SIM_30V;
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ sim_Reset_MT6306(power, NULL, NULL, hw_cb);
+#ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+ {
+ /* For [MAUI_01321659] begin */
+ if (SimCard->Power == SIM_18V)
+ *ResultVolt = CLASS_C_18V;
+ else if (SimCard->Power == SIM_30V)
+ *ResultVolt = CLASS_B_30V;
+ else
+ SIM_DEBUG_ASSERT(0);
+ } /* For [MAUI_01321659] end */
+#endif
+ }
+ else
+ usim_update_sim_to_ready(hw_cb);
+
+ SimCard->mod_id = kal_get_active_module_id();
+ SimCard->mod_extq_cap = msg_get_task_extq_capacity(SimCard->mod_id);
+ }
+ sim_MT6306_recordDirectionBaud(hw_cb);
+ }
+ else
+ {
+ status = USIM_INVALID_WRST;
+ }
+ }
+
+ MT6306_RACE_RELEASE(sim_MT6306_protectionRst);
+ return status;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Enable_Enhanced_Speed_All
+*
+* DESCRIPTION
+* enable the enhance speed
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_Enable_Enhanced_Speed_MT6306(kal_bool enable, sim_HW_cb *hw_cb)
+{
+ //extern void L1sim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb);
+
+ L1sim_Enable_Enhanced_Speed(enable, hw_cb);
+ L1usim_Enable_Enhanced_Speed(enable, hw_cb);
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Select_Prefer_PhyLayer_All
+*
+* DESCRIPTION
+* select the prefer physical layer protocol, the selected one has higher priority
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_Select_Prefer_PhyLayer_MT6306(sim_protocol_phy_enum T, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ usim_dcb->perfer_phy_proto = T;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Set_ClockStopMode_All
+*
+* DESCRIPTION
+* configure the clock stop mode.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+kal_bool L1sim_Set_ClockStopMode_MT6306(sim_clock_stop_enum mode, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ if (mode == CLOCK_STOP_HIGH)
+ L1sim_Configure_MT6306(CLOCK_STOP_AT_HIGH, hw_cb);
+ else if (mode == CLOCK_STOP_LOW || mode == CLOCK_STOP_ANY)
+ L1sim_Configure_MT6306(CLOCK_STOP_AT_LOW, hw_cb);
+ else
+ L1sim_Configure_MT6306(CLOCK_STOP_NOT_ALLOW, hw_cb);
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ }
+ else
+ {
+ L1usim_Set_ClockStopMode(mode, hw_cb);
+ }
+ return KAL_TRUE;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_PowerOff_All
+*
+* DESCRIPTION
+* turn off the SIM card.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_PowerOff_MT6306(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_HW_cb *peerHWCb;
+ kal_uint32 log_size = 0;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ /*we should additionally check whether this interface has owner or not*/
+ if (0 != usim_dcb->ownerTask && kal_get_current_thread_ID() != usim_dcb->ownerTask)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC122, SIM_ASSERT_REASON_WRONG_OWNERTASK, SIM_ASSERT_OWNER_SIMTASK,
+ (kal_uint32) usim_dcb->ownerTask, (kal_uint32) kal_get_current_thread_ID(), 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (KAL_TRUE == sim_MT6306_noNeedEoc[hw_cb->simInterface])
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_FALSE == sim_MT6306_QuerySIMActive(hw_cb))
+ {
+ sim_MT6306_noNeedEoc[hw_cb->simInterface] = KAL_TRUE;
+ return;
+ }
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] Interface:%d\n\r", __func__, hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ sim_MT6306_clkStopTimerStop(hw_cb);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->needStopGptISR = KAL_TRUE;
+ while (1)
+ {
+ Data_Sync_Barrier();
+ if (hw_cb->waitGptISR_MT6306 == 0 && peerHWCb->waitGptISR_MT6306 == 0) break;
+ kal_give_spinlock(hw_cb->spinlockid);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for GPT ISR:%d, peer:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, hw_cb->waitGptISR_MT6306, peerHWCb->waitGptISR_MT6306, drv_get_current_time());
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ }
+#if defined(LPWR_SLIM)
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ sim_MT6306_change(hw_cb, sim_MT6306_eventPowerOff);
+ MT6306_RACE_PROTECT(sim_MT6306_protectionPwf);
+ /*
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL1, __LINE__,
+ hw_cb->simInterface, usim_dcb->ev_status, usim_dcb->main_state,
+ usim_dcb->present, usim_dcb->phy_proto, 0
+ );
+ */
+
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ sim_PowerOff_MT6306(hw_cb);
+ kal_sleep_task(2);
+ }
+ else
+ L1usim_PowerOff(hw_cb);
+
+ usim_dcb->present = KAL_FALSE;
+ /*
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL1, __LINE__,
+ hw_cb->simInterface, usim_dcb->ev_status, usim_dcb->main_state,
+ usim_dcb->present, usim_dcb->phy_proto, 0
+ );
+ */
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateDeactiavate);
+ MT6306_RACE_RELEASE(sim_MT6306_protectionPwf);
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Get_Card_Info_All
+*
+* DESCRIPTION
+* get the card information
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_Get_Card_Info_MT6306(sim_info_struct *info, sim_HW_cb *hw_cb)
+{
+ L1usim_Get_Card_Info(info, hw_cb);
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Cmd_All
+*
+* DESCRIPTION
+* 1. check which case the command belongs to.
+* 2. direct the command into T=0 or T=1 protocol layer.
+*
+* PARAMETERS
+* 1. txData: tx buffer containing command header optional with tx data.
+* 2. txSize: length of the tx data
+* 3. rxData: rx buffer (for T=1, must inluding two extra one for sw1 and sw2)
+* 4. rxSize: length of the rx data except sw1|sw2
+*
+* RETURNS
+* status bytes(SW1|SW2), 0 means a physical error.
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+sim_status L1sim_Cmd_MT6306(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb)
+{
+ kal_uint32 maskedValue, log_size = 0;
+ usim_dcb_struct *usim_dcb, *peer_usim_dcb;
+ sim_status result = 0x9000;
+ Sim_Card *SimCard;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_HW_cb *peerHWCb;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /*we should do platform check here, not allow to access interface 2 on one-SIM platform*/
+ usim_InterfaceCheck(hw_cb);
+
+ sim_MT6306_clkStopTimerStop(hw_cb);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->needStopGptISR = KAL_TRUE;
+ while (1)
+ {
+ Data_Sync_Barrier();
+ if (hw_cb->waitGptISR_MT6306 == 0 && peerHWCb->waitGptISR_MT6306 == 0) break;
+ kal_give_spinlock(hw_cb->spinlockid);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for GPT ISR:%d, peer:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, hw_cb->waitGptISR_MT6306, peerHWCb->waitGptISR_MT6306, drv_get_current_time());
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ }
+#if defined(LPWR_SLIM)
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ int i = 0;
+ kal_uint32 txBUFFER[10] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+ for (i = 0; i < *txSize && i < 10; i++)
+ {
+ txBUFFER[i] = *(txData + i);
+ }
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[%s] interface:%d, txSize:%d, rxSize:%d, %x %x %x %x %x %x %x %x %x %x\r\n", __func__, hw_cb->simInterface, *txSize, *rxSize, txBUFFER[0],
+ txBUFFER[1], txBUFFER[2], txBUFFER[3], txBUFFER[4], txBUFFER[5], txBUFFER[6], txBUFFER[7], txBUFFER[8], txBUFFER[9]);
+
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ peer_usim_dcb = GET_USIM_CB(peerHWCb->simInterface);
+ /*we should additionally check whether this interface has owner or not*/
+ if (0 != usim_dcb->ownerTask && kal_get_current_thread_ID() != usim_dcb->ownerTask)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC122, SIM_ASSERT_REASON_WRONG_OWNERTASK, SIM_ASSERT_OWNER_SIMTASK,
+ (kal_uint32) usim_dcb->ownerTask, (kal_uint32) kal_get_current_thread_ID(), 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+ if (KAL_TRUE == sim_MT6306_noNeedEoc[hw_cb->simInterface])
+ SIM_DEBUG_ASSERT(0);
+
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ sim_MT6306_noNeedEoc[hw_cb->simInterface] = KAL_TRUE;
+ return SIM_SW_STATUS_FAIL;
+ }
+
+ sim_MT6306_change(hw_cb, sim_MT6306_eventCommand);
+
+ MT6306_RACE_PROTECT(sim_MT6306_protectionCmd);
+
+ SIM_SetRXRetry(3);
+ SIM_SetTXRetry(3);
+
+
+ // check cmd cases
+ if (*txSize == 5 && rxData == NULL)
+ {
+ //SIM case1 txSize = 5 bytes, UICC case1 txSize = 4 bytes
+ usim_dcb->cmd_case = usim_case_1;
+ /////dbg_print("usim_case_1 \r\n");
+ }
+ else if (*txSize == 5 && rxData != NULL)
+ {
+ usim_dcb->cmd_case = usim_case_2;
+ if (((0 == txData[LEN_INDEX]) && (256 > *rxSize)) || (*rxSize < txData[LEN_INDEX]))
+ {
+ return 0x0000;
+ }
+ /////dbg_print("usim_case_2 \r\n");
+ }
+ else if (*txSize != 5 && rxData == NULL)
+ {
+ //SIM case3 txSize > 5 bytes, UICC case3 txSize > 5 bytes
+ usim_dcb->cmd_case = usim_case_3;
+ /////dbg_print("usim_case_3 \r\n");
+ }
+ else if (*txSize != 5 && rxData != NULL)
+ {
+ usim_dcb->cmd_case = usim_case_4;
+ /////dbg_print("usim_case_4 \r\n");
+ }
+ SimCard->cmd_case = usim_dcb->cmd_case;
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC1, *txData, *(txData + 1), *(txData + 2), *(txData + 3), drv_get_current_time());
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC1, *txSize, *rxSize, hw_cb->simInterface, *rxData, SimCard->cmd_case);
+#endif
+ maskedValue = SaveAndSetIRQMask();
+ clockStopMap[hw_cb->simInterface].isHandleCmd = KAL_TRUE;
+ RestoreIRQMask(maskedValue);
+
+ if (usim_dcb->phy_proto != peer_usim_dcb->phy_proto || ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) & (SIM_CONF_T0EN | SIM_CONF_T1EN)) == 0))
+ {
+ usim_restore_protocol(usim_dcb, hw_cb); //restore SIM_IF to current protocol if another card has different protocol
+ }
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+
+ result = L1sim_Cmd_Layer_MT6306(txData, txSize, rxData, rxSize, hw_cb, &usim_dcb->isSW6263);
+ MT6306_RACE_RELEASE(sim_MT6306_protectionCmd);
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC19, *txData, *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC19, *rxData, *(rxData + 1), *(rxData + 2), *(rxData + 3), *(rxData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC19, *txSize, *rxSize, result, usim_dcb->isSW6263, SimCard->cmd_case);
+#endif
+ if (SimCard->clkStop == KAL_TRUE && result != SIM_SW_STATUS_FAIL && usim_dcb->present)
+ {
+ usim_dcb->stopSimClkInEndOfAction = KAL_TRUE;
+ }
+ }
+ else
+ {
+ result = L1usim_Cmd(txData, txSize, rxData, rxSize, hw_cb);
+ MT6306_RACE_RELEASE(sim_MT6306_protectionCmd);
+ if (usim_dcb->clock_stop_en == KAL_TRUE && DEACTIVATION_STATE != usim_dcb->main_state && result != SIM_SW_STATUS_FAIL && usim_dcb->present)
+ {
+ usim_dcb->stopSimClkInEndOfAction = KAL_TRUE;
+ }
+ }
+ maskedValue = SaveAndSetIRQMask();
+ clockStopMap[hw_cb->simInterface].isHandleCmd = KAL_FALSE;
+ RestoreIRQMask(maskedValue);
+
+#if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ if (result == SIM_SW_STATUS_FAIL && usim_dcb->present)
+ {
+ if (usim_dcb->hasPowerClass && usim_dcb->PowerClass != CLASS_C_18V)
+ usim_dcb->retry_3v_prefer = KAL_TRUE;
+ }
+#endif
+
+ return result;
+
+}
+
+void L1sim_EOC_MT6306(sim_HW_cb *hw_cb)
+{
+ if (KAL_TRUE == sim_MT6306_noNeedEoc[hw_cb->simInterface])
+ {
+ sim_MT6306_noNeedEoc[hw_cb->simInterface] = KAL_FALSE;
+ return;
+ }
+
+ sim_MT6306_endOfAction(hw_cb);
+}
+
+sim_ctrlDriver sim_ctrlDriver_MT6306 =
+{
+ L1sim_Reset_MT6306,
+ L1sim_Cmd_MT6306,
+ L1sim_PowerOff_MT6306,
+ L1sim_Get_Card_Info_MT6306,
+ L1sim_Enable_Enhanced_Speed_MT6306,
+ L1sim_Select_Prefer_PhyLayer_MT6306,
+ L1sim_Set_ClockStopMode_MT6306,
+ L1sim_EOC_MT6306,
+ sim_MT6306_addMsg
+};
+// Revert protocol setting to either T=1 or T=0
+void usim_restore_protocol(usim_dcb_struct *usim_dcb, sim_HW_cb * hw_cb)
+{
+ if (usim_dcb->phy_proto == T1_PROTOCOL)
+ {
+ usim_set_protocol(T1_PROTOCOL, hw_cb);
+ USIM_DISABLE_TXRX_HANSHAKE();
+ USIM_DISABLE_T0();
+ }
+ else
+ {
+ usim_set_protocol(T0_PROTOCOL, hw_cb); //Must Set protocol after another SIM reset fail
+ USIM_DISABLE_T1();
+ USIM_ENABLE_TXRX_HANSHAKE();
+ }
+}
+#if defined(__CHAINING_TEST__)
+kal_bool Send_IFS_REQ_MT6306(kal_uint8 ifs, kal_uint8 simInterface)
+{
+ kal_bool result = KAL_TRUE;
+ sim_HW_cb *hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ sim_HW_cb *peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ usim_dcb_struct *usim_dcb = GET_USIM_CB(simInterface);
+ usim_dcb_struct *peer_usim_dcb = GET_USIM_CB(peerHWCb->simInterface);
+ sim_MT6306_switchInfo * switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ kal_uint32 log_size = 0;
+
+ dbg_print("\r\ninterface:%d\r\n", simInterface);
+
+ USIM_low_power_related_setting(hw_cb, USIM_LP_DISABLE | USIM_LP_MASK_NORMAL_VSIM_CURRENT | USIM_LP_MASK_START_SCLK);
+
+ /*we should do platform check here, not allow to access interface 2 on one-SIM platform*/
+ usim_InterfaceCheck(hw_cb);
+
+ sim_MT6306_clkStopTimerStop(hw_cb);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->needStopGptISR = KAL_TRUE;
+ while (1)
+ {
+ Data_Sync_Barrier();
+ if (hw_cb->waitGptISR_MT6306 == 0 && peerHWCb->waitGptISR_MT6306 == 0) break;
+ kal_give_spinlock(hw_cb->spinlockid);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for GPT ISR:%d, peer:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, hw_cb->waitGptISR_MT6306, peerHWCb->waitGptISR_MT6306, drv_get_current_time());
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ }
+#if defined(LPWR_SLIM)
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ sim_MT6306_change(hw_cb, sim_MT6306_eventCommand);
+ MT6306_RACE_PROTECT(sim_MT6306_protectionCmd);
+
+ if (usim_dcb->phy_proto != peer_usim_dcb->phy_proto || ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) & (SIM_CONF_T0EN | SIM_CONF_T1EN)) == 0))
+ {
+ usim_restore_protocol(usim_dcb, hw_cb); //restore SIM_IF to current protocol if another card has different protocol
+ }
+#if 1
+ if (usim_send_s_block(IFS_REQ, ifs, (sim_HW_cb *) hwCbArray[simInterface]) == USIM_NO_ERROR)
+ {
+ usim_dcb->ifsd = ifs;
+ }
+ else
+ result = KAL_FALSE;
+#endif
+ MT6306_RACE_RELEASE(sim_MT6306_protectionCmd);
+ L1sim_EOC_MT6306(hw_cb);
+
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+
+ return result;
+}
+
+#endif
+
+//--------------------------------------------------------------------------//
+// usim driver unit test code
+//--------------------------------------------------------------------------//
+/*
+The behavior of the T1 controller
+1. enable T1 controller
+2. write NAD, PCB, LEN into SIM_DATA
+3. write LEN into SIMP3
+4. configure the DMA for data transfer (INF field)
+5. write any value into SIM_INS (trigger to start)
+6. generate the T1END interrupt.
+7. if a response block is received, T1END is generated again
+8. The received block is in the data buffer, the EDC is checked and removed.
+9. Calc WWT value, we can run sim_WWTTest at sim_Reset_MT6306 before return result;
+*/
+#endif //#if defined(SIM_DRV_SWITCH_MT6306)
+#endif // __USIM_DRV__
+#endif //DRV_MULTIPLE_SIM
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
+
+#endif //DRV_SIM_OFF
+
diff --git a/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl2_mt6306.c b/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl2_mt6306.c
new file mode 100644
index 0000000..1077a27
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt6306/src/icc_switchControl2_mt6306.c
@@ -0,0 +1,3478 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * switchControl2.c(originally named sim_MT6302.C)
+ *
+ * Project:
+ * --------
+ * Gemini
+ *
+ * Description:
+ * ------------
+ * this file is to do MT6302 related operation
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "drv_comm.h"
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#include "reg_base.h"
+#include "intrCtrl.h"
+#include "sim_reg_adp.h"
+
+#include "sim_al.h"
+#include "sim_hw_mtk.h"
+//#include "dma_sw.h"
+#include "sim_sw_comm.h"
+//#include "sim_sw.h"
+//#include "dma_hw.h"
+//#include "gpt_sw.h"
+//#include "gpio_sw.h"
+#include "drv_hisr.h"
+//#include "usim_drv.h"
+#include "sim_mt6306.h"
+#include "mt6306_i2c.h"
+//#include "..\..\..\ps\sim\include\sim_trc.h"
+/*RHR*/
+#include "drv_features.h"
+//#include "kal_non_specific_general_types.h"
+#include "string.h"
+#include "nvram_data_items.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#include "stack_ltlcom.h"
+#include "stdio.h"
+//#include "pmic_features.h"
+#include "kal_trace.h"
+#include "kal_debug.h"
+/*RHR*/
+#include "sim_drv_trc.h"
+//#include "mt63062.h"
+#include "drv_hisr.h"
+#if (defined(DRV_SIM_ALL_SOLUTION_BUILT) || (defined(DRV_MULTIPLE_SIM) && !defined(DRV_2_SIM_CONTROLLER)))
+#if defined(SIM_DRV_SWITCH_MT6306)
+
+#if defined(LPWR_SLIM)
+ #include "sleepdrv_interface.h"
+#endif
+
+#define FILE_SWITCHCONTROL2 3
+
+#define VERIFY_MT6306_REG 0
+sim_MT6306_status sim_MT6306_blockCLK(sim_HW_cb *hw_cb);
+sim_MT6306_status sim_MT6306_blockDAT(sim_HW_cb *hw_cb);
+sim_MT6306_status sim_MT6306_passRST(sim_HW_cb *hw_cb);
+sim_MT6306_status sim_MT6306_passDAT(sim_HW_cb *hw_cb);
+sim_MT6306_status sim_MT6306_passCLK(sim_HW_cb *hw_cb);
+sim_MT6306_status sim_MT6306_d2D(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_d2R(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_d2S(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_r2D(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_r2R(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_r2S(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_s2D(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_s2R(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+sim_MT6306_status sim_MT6306_s2S(sim_HW_cb *hw_cb, sim_MT6306_changeEvent event);
+void sim_MT6306_clkStopper(sim_HW_cb *hw_cb);
+void sim_MT6306_clkStopTimerStop(sim_HW_cb *hw_cb);
+void sim_MT6306_setCardState(sim_HW_cb *hw_cb, sim_MT6306_cardState cardState);
+kal_bool sim_MT6306_noneNeedClk(sim_HW_cb *hw_cb);
+
+void sim_PDNDisable_MT6306(sim_HW_cb *hw_cb);
+void sim_PDNEnable_MT6306(sim_HW_cb *hw_cb);
+void sim_MT6306_deClkStopQueue(sim_HW_cb *hw_cb);
+void sim_MT6306_enClkStopQueue(sim_HW_cb *hw_cb);
+sim_HW_cb *retreiveQueuedCb(kal_uint32 i);
+extern void SIM_HISR_MT6306(void);
+extern void SIM_HISR2_MT6306(void);
+extern void usim_hisr_MT6306(void);
+extern void usim_hisr2_MT6306(void);
+extern kal_uint32 SIM_GetCurrentTime(void);
+volatile kal_uint32 timeout_handler_start[4]={0};
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ extern volatile kal_semid wait_sim_MT6306_RACE_PROTECT[];
+#endif
+kal_uint32 sim_MT6306_gptHandle_clkStopQueue = 0;
+volatile kal_bool sim_MT6306_gpt_clkStopQueue_start = KAL_FALSE;
+
+sim_MT6306_cardInfo sim_MT6306_card[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+//sim_MT6306_msg sim_MT6306_msgArray[SIM_MT6306_MSG_NUM];
+//kal_uint32 sim_MT6306_msgIndex;
+
+kal_bool spiWriterFlag;
+kal_bool spiWriterGptTimeoutFlag = KAL_FALSE;
+
+/*all global variables merge to following control blocks*/
+sim_MT6306_switchInfo switchCBMT6306[SIM_MT6302_MAX_MT6302];
+sim_MT6306_clockStopQueueEvent clockStopQueue[DRV_SIM_MAX_LOGICAL_INTERFACE];
+kal_char *mt6306StateStr[9] = {"D2D", "D2R", "D2S", "R2D", "R2R", "R2S", "S2D", "S2R", "S2S"};
+
+#ifdef ATEST_DRV_ENABLE
+#define MT6306_DBG( fmt, ...) // dbg_print(fmt, ##__VA_ARGS__)
+#else
+#if 0
+/* under construction !*/
+#else
+#define MT6306_DBG( fmt, ...) \
+ do{ \
+ if(kal_if_hisr()) \
+ { \
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, fmt,##__VA_ARGS__); \
+ if (log_size > 0) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, hw_cb->hisrDbgStr); \
+ } \
+ else \
+ { \
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(hw_cb->dbgStr, fmt,##__VA_ARGS__); \
+ if (log_size > 0) dhl_print(TRACE_INFO, DHL_USER_FLAG_NONE, MOD_SIM_DRV, hw_cb->dbgStr); \
+ } \
+ }while(0)
+#endif
+#endif
+
+sim_MT6306_eventHandler sim_MT6306_handlerTable[9] =
+{
+ sim_MT6306_d2D,
+ sim_MT6306_d2R,
+ sim_MT6306_d2S,
+ sim_MT6306_r2D,
+ sim_MT6306_r2R,
+ sim_MT6306_r2S,
+ sim_MT6306_s2D,
+ sim_MT6306_s2R,
+ sim_MT6306_s2S,
+};
+
+void usim_lisr_MT6306(kal_uint32 vector);
+void usim_lisr2_MT6306(kal_uint32 vector);
+void SIM_LISR_MT6306(kal_uint32 vector);
+void SIM_LISR2_MT6306(kal_uint32 vector);
+//extern kal_uint32 sim_waitHisrInterface, usim_waitHisrInterface;
+//extern sim_HW_cb *usim_waitHisrCb_MT6306, *sim_waitHisrCb_MT6306; have moved to sim_MT6306_switchInfo
+extern Sim_Card SimCard_cb[];
+extern usim_dcb_struct usim_cb[];
+extern void L1sim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb);
+
+typedef struct
+{
+ kal_uint32 MT6306ChipNo; //for which MT6306 chip does this control block stand
+ kal_semid sim_MT6306_arb;
+ kal_uint8 sim_MT6306_regValue[SIM_MT6306_REG_NUMBER];
+ kal_uint8 sim_MT6306_internal_bypass_sem; //WPLin 20110407 remove usage of MT6306_Writer_GPIO_Krl()
+#ifdef MT6306_SEC_AVERAGE //WPLin 20110505
+ kal_uint8 sim_MT6306_prev_check_result[MT6306_SEC_AVERAGE_CHECK_NUM]; // [0] means oldest result
+#else
+ kal_uint8 sim_MT6306_prev_check_result; //WPLin 20110407
+#endif
+} sim_MT63062_switchCB;
+sim_MT63062_switchCB switch_CB_63062;
+volatile kal_spinlockid switch_spinlock = 0;
+volatile kal_spinlockid spinlockid_simClkStop = 0;
+void sim_MT6306_SPIWrite(sim_MT6306_switchInfo *switch_CB, kal_uint16 data);
+kal_uint8 sim_MT6306_SPIRead(sim_MT6306_switchInfo *switch_CB, kal_uint16 addr);
+
+void sim_MT63062_TakeI2Csem(void) //WPLin 20110407 separate functions from MT6306_I2C.c --> MT6306_security.c
+{
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+
+ DRV_GET_RET_ADDR(retAddr);
+
+ sim_addMsg(0x11042002, 0, 0, (kal_uint32)retAddr);
+
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ kal_take_sem(switch_CB_63062.sim_MT6306_arb, KAL_INFINITE_WAIT);
+}
+
+void sim_MT63062_GiveI2Csem(void) //WPLin 20110407 separate functions from MT6306_I2C.c --> MT6306_security.c
+{
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+
+ DRV_GET_RET_ADDR(retAddr);
+ sim_addMsg(0x11042003, 0, 0, (kal_uint32)retAddr);
+
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ kal_give_sem(switch_CB_63062.sim_MT6306_arb);
+}
+
+void sim_MT6306_SPIWrite(sim_MT6306_switchInfo *switch_CB, kal_uint16 data);
+
+
+/*following is MT6306 specific funcion, not originated from MT6302*/
+/*since 4 card share the same register but MT6302 behave in two SIM cards, we have to globally record the value of this register*/
+kal_uint16 sim_MT6306_CSTOPRegValue = 0x9F;
+void sim_MT6306_SetCSTOP(sim_HW_cb *hw_cb)
+{
+ kal_uint32 chipNo, portNo;
+ sim_MT6306_switchInfo *switch_CB;
+
+ chipNo = hw_cb->simSwitchChipNo;
+ portNo = hw_cb->simSwitchPortNo;
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ if (1 < chipNo || 1 < portNo)
+ SIM_DEBUG_ASSERT(0);
+ sim_MT6306_CSTOPRegValue |= (0x1 << (chipNo * 2 + portNo));
+ sim_MT6306_SPIWrite(switch_CB, sim_MT6306_CSTOPRegValue);
+}
+
+void sim_MT6306_ClearCSTOP(sim_HW_cb *hw_cb)
+{
+ kal_uint32 chipNo, portNo;
+ sim_MT6306_switchInfo *switch_CB;
+
+ chipNo = hw_cb->simSwitchChipNo;
+ portNo = hw_cb->simSwitchPortNo;
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ if (1 < chipNo || 1 < portNo)
+ SIM_DEBUG_ASSERT(0);
+ sim_MT6306_CSTOPRegValue &= ~(0x1 << (chipNo * 2 + portNo));
+ sim_MT6306_SPIWrite(switch_CB, sim_MT6306_CSTOPRegValue);
+}
+
+
+
+void sim_MT6306_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2)
+{
+ /*share the same meg array, reduce the RAM size*/
+ sim_addMsg(tag, event, data1, data2);
+}
+
+void sim_MT6306_checkCtrlPDN(sim_HW_cb *hw_cb)
+{
+ /*MT6306 may not connect to SIM1, be careful on this*/
+ /* We should make sure we disable PDN before access SIMIF */
+ sim_PDNDisable_MT6306(hw_cb);
+}
+
+sim_MT6306_switchInfo *sim_MT6306_get_MT6306switchCB(sim_HW_cb *hw_cb)
+{
+ return &switchCBMT6306[hw_cb->simSwitchChipNo];
+}
+
+sim_MT6306_cardInfo *sim_MT6306_get_MT6306CardCB(sim_HW_cb *hw_cb)
+{
+ return &sim_MT6306_card[hw_cb->simInterface];
+}
+
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+
+extern kal_char sim_shared_dbgstr[];
+extern kal_uint8 MT6306_Reader_AL(kal_uint8 chipno, kal_uint16 addr);
+void sim_MT6306_SPIWrite(sim_MT6306_switchInfo *switch_CB, kal_uint16 data)
+{
+// if(KAL_TRUE == kal_if_hisr() && KAL_TRUE == switch_CB->sim_MT6306_taskAccessing && KAL_FALSE == switch_CB->sim_workingTaskWaiting)
+// SIM_DEBUG_ASSERT(0);
+ /*
+ kal_uint32 t1=SIM_GetCurrentTime();
+ kal_sprintf(sim_shared_dbgstr,"[Race Protect] Chip:%d, now:%x, thread:%x", switch_CB->MT6306ChipNo,t1,thread_id);
+ DRV_ICC_print_str(sim_shared_dbgstr);
+ */
+
+ kal_uint32 thread_id=(kal_uint32)kal_get_current_thread_ID(), log_size = 0;
+
+ MT6306_RACE_PROTECT(sim_MT6306_protectionSpi);
+
+ if (0x43 == data)
+ SIM_DEBUG_ASSERT(0);
+
+ // sim_MT63062_TakeI2Csem();
+ // used to check if any context access Writer interface
+ kal_take_spinlock(switch_spinlock, KAL_INFINITE_WAIT);
+ if (spiWriterFlag == KAL_TRUE)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[%s] SIM_DEBUG_ASSERT Chip:%d, %d %d %d,thread:%x\n\r", __func__, switch_CB->MT6306ChipNo, kal_if_hisr(), switch_CB->sim_MT6306_taskAccessing, switch_CB->sim_workingTaskWaiting,thread_id);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ SIM_DEBUG_ASSERT(0);
+ }
+ spiWriterFlag = KAL_TRUE;
+ log_size = kal_sprintf(sim_shared_dbgstr, "[%s] Chip:%d, %d %d %d,thread:%x\n\r", __func__, switch_CB->MT6306ChipNo, kal_if_hisr(), switch_CB->sim_MT6306_taskAccessing, switch_CB->sim_workingTaskWaiting,thread_id);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ switch_CB->sim_MT6320_writer(switch_CB->MT6306ChipNo, data); //MT6306_Writer_GPIO
+
+#if VERIFY_MT6306_REG //Enable this to check if 6306 is ok
+ kal_uint8 readValue = MT6306_Reader_AL(switch_CB->MT6306ChipNo, data >> 4);
+ if ((data & 0xF) != readValue)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[ERROR][%s] Chip:%d, Addr:%x, write:%x, readValue:%x", __func__, switch_CB->MT6306ChipNo, data >> 4, data & 0xF, readValue);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ int i = 0;
+ for (i = 0; i <= 0x13; i++)
+ {
+ kal_uint8 value = MT6306_Reader_AL(0, i);
+ log_size = kal_sprintf(sim_shared_dbgstr, "\r\nReg:%x:%x", i, value);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ }
+ SIM_DEBUG_ASSERT(0);
+ }
+#endif
+
+ spiWriterFlag = KAL_FALSE;
+ kal_give_spinlock(switch_spinlock);
+
+ //sim_MT63062_GiveI2Csem();
+
+ MT6306_RACE_RELEASE(sim_MT6306_protectionSpi);
+
+ /*
+ kal_uint32 t2=SIM_GetCurrentTime();
+ kal_sprintf(sim_shared_dbgstr,"[Race Release] Chip:%d, cost:%x, thread:%x", switch_CB->MT6306ChipNo,t2-t1,thread_id);
+ DRV_ICC_print_str(sim_shared_dbgstr);*/
+
+ sim_MT6306_addMsg(SIM_MT6306_SPI_WRITE, data, switch_CB->MT6306ChipNo, kal_if_hisr());
+}
+
+kal_uint8 sim_MT6306_SPIRead(sim_MT6306_switchInfo *switch_CB, kal_uint16 addr)
+{
+
+ kal_uint8 readValue;
+ kal_uint32 log_size = 0;
+// if(KAL_TRUE == kal_if_hisr() && KAL_TRUE == switch_CB->sim_MT6306_taskAccessing && KAL_FALSE == switch_CB->sim_workingTaskWaiting)
+// SIM_DEBUG_ASSERT(0);
+ MT6306_RACE_PROTECT(sim_MT6306_protectionSpi);
+ kal_take_spinlock(switch_spinlock, KAL_INFINITE_WAIT);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[%s] Chip:%d, %d %d %d\n\r", __func__, switch_CB->MT6306ChipNo, kal_if_hisr(), switch_CB->sim_MT6306_taskAccessing, switch_CB->sim_workingTaskWaiting);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ //sim_MT63062_TakeI2Csem();
+ /* used to check if any context access Writer interface */
+ if (spiWriterFlag == KAL_TRUE)
+ SIM_DEBUG_ASSERT(0);
+ spiWriterFlag = KAL_TRUE;
+ readValue = MT6306_Reader_AL(switch_CB->MT6306ChipNo, addr); //MT6306_Writer_GPIO
+ spiWriterFlag = KAL_FALSE;
+ //sim_MT63062_GiveI2Csem();
+ kal_give_spinlock(switch_spinlock);
+ MT6306_RACE_RELEASE(sim_MT6306_protectionSpi);
+ return readValue;
+}
+sim_MT6306_status sim_MT6306_setVCC(sim_HW_cb *hw_cb, kal_uint32 level)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d, level:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo, level);
+
+ if (KAL_FALSE == switch_CB->sim_MT6306_taskAccessing)
+ SIM_DEBUG_ASSERT(0);
+ if (1 < level)
+ SIM_DEBUG_ASSERT(0);
+ if (0 == level) /*1.8V*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC] &= ~(0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+ /*clear VSEL bit*/
+ card_cb->pins.VCC &= ~0x1;
+ }
+ else /*3V*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC] |= (0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+ /*set VSEL bit*/
+ card_cb->pins.VCC |= 0x1;
+ }
+ sim_MT6306_addMsg(SIM_MT6306_VCC_LVL_CTRL, MT6306PortNo, level, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_switchVCC(sim_HW_cb *hw_cb, kal_uint32 on)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d, onoff:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo, on);
+
+ if (KAL_FALSE == switch_CB->sim_MT6306_taskAccessing)
+ SIM_DEBUG_ASSERT(0);
+ if (1 < on)
+ SIM_DEBUG_ASSERT(0);
+ if (0 == on) /*turn off*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC] &= ~(0x4 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+
+ /*in MT6306, if VCC is down, pin state have to change*/
+ card_cb->pins.VCC &= ~0x4;
+ if (sim_MT6306_VCC18VDisable != card_cb->pins.VCC && sim_MT6306_VCC3VDisable != card_cb->pins.VCC)
+ SIM_DEBUG_ASSERT(0);
+ card_cb->pins.CLK |= 0x10;
+ card_cb->pins.DAT |= 0x10;
+ card_cb->pins.RST |= 0x10;
+
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateDeactiavate);
+
+ }
+ else /*turn on*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC] |= (0x4 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+
+ /*in MT6306, if VCC is down, pin state have to change*/
+ card_cb->pins.VCC |= 0x4;
+ if (sim_MT6306_VCC18V != card_cb->pins.VCC && sim_MT6306_VCC3V != card_cb->pins.VCC)
+ SIM_DEBUG_ASSERT(0);
+ card_cb->pins.CLK &= ~0x10;
+ card_cb->pins.DAT &= ~0x10;
+ card_cb->pins.RST &= ~0x10;
+
+ }
+ sim_MT6306_addMsg(SIM_MT6306_VCC_CTRL, MT6306PortNo, on, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+
+ return sim_MT6306_statusNoError;
+}
+
+/* this function pure set RSTVAL, that is, if we block RST, what level will RST stay
+* call this function doesn't change block or pass on RST
+*/
+sim_MT6306_status sim_MT6306_setRST(sim_HW_cb *hw_cb, kal_uint32 level)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ if (KAL_FALSE == switch_CB->sim_MT6306_taskAccessing)
+ SIM_DEBUG_ASSERT(0);
+
+ if (1 < level)
+ SIM_DEBUG_ASSERT(0);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d,level:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo, level);
+ if (0 == level) /*turn off*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] &= ~(0x4 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST]);
+ card_cb->pins.RST &= ~0x4;
+ }
+ else /*set to high*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] |= 0x4 << MT6306PortNo;
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST]);
+ card_cb->pins.RST |= 0x4;
+ }
+ sim_MT6306_addMsg(SIM_MT6306_RST_CTRL, MT6306PortNo, level, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST]);
+
+ return sim_MT6306_statusNoError;
+}
+
+/* this function pure set DATA_L, that is, if we block DAT, what level will DAT stay
+* call this function doesn't change block or pass on DAT
+*/
+sim_MT6306_status sim_MT6306_setDAT(sim_HW_cb *hw_cb, kal_uint32 level)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ if (KAL_FALSE == switch_CB->sim_MT6306_taskAccessing)
+ SIM_DEBUG_ASSERT(0);
+ if (1 < level)
+ SIM_DEBUG_ASSERT(0);
+ if (KAL_FALSE == switch_CB->sim_MT6306_needManualControl)
+ SIM_DEBUG_ASSERT(0);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d, level:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo, level);
+ if (0 == level) /*set to block low*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] |= (0x5 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+ card_cb->pins.DAT |= 0x5;
+ }
+ else /*set to block high*/
+ {
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] &= ~(0x5 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+ card_cb->pins.DAT &= ~0x5;
+ }
+ sim_MT6306_addMsg(SIM_MT6306_DAT_CTRL, MT6306PortNo, level, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+
+ return sim_MT6306_statusNoError;
+}
+
+void sim_MT6306_manualReset(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ /*
+ in design spec, we have to do following:
+ (1)raise B's VCC, (2)pass B's CLK, (3)pass B's DAT, (4)set timeout, (5)raise B's RST to replace SIM controller's activation
+ */
+ /*VCC has been raised in USIM/SIM driver, we don't need to control VCC here*/
+
+ /*controller's clk must now running, that is why we implement manual reset*/
+ if (DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & 0x2)
+ SIM_DEBUG_ASSERT(0);
+
+ /*after we pass B's clk, clk start running*/
+ sim_MT6306_passCLK(hw_cb);
+
+ sim_MT6306_passDAT(hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK) |= SIM_IRQEN_TOUT;
+ DRV_SetBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT);
+
+ /*enable timeout, must guarantee a 0->1 change*/
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) &= ~SIM_CONF_TOUTEN;
+ DRV_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) |= SIM_CONF_TOUTEN;
+ DRV_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ /*RX IRQ has been enabled*/
+
+ /*RST should be low now*/
+ //if(card_cb->pins.RST & 0x4)
+ // SIM_DEBUG_ASSERT(0);
+
+ /*RST should be block now*/
+ if ((card_cb->pins.RST & 0x1) == 0)
+ SIM_DEBUG_ASSERT(0);
+
+
+
+ /*manual raise B's RST, not by controller*/
+ sim_MT6306_setRST(hw_cb, 1);
+}
+
+void sim_MT6306_manualDeactive(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+
+ /*
+ (1)pull down B's RST, (2)stop clk low, (3)block DAT low (4)close the power
+ */
+
+ /*RST should be block now*/
+ if ((card_cb->pins.RST & 0x1) == 0)
+ SIM_DEBUG_ASSERT(0);
+
+ sim_MT6306_setRST(hw_cb, 0);
+ ust_us_busyloop(100);
+
+ sim_MT6306_blockCLK(hw_cb);
+ ust_us_busyloop(100);
+
+ sim_MT6306_setDAT(hw_cb, 0);
+ sim_MT6306_blockDAT(hw_cb);
+ ust_us_busyloop(100);
+
+ sim_MT6306_switchVCC(hw_cb, 0);
+}
+#endif
+
+//#ifdef DRV_2_SIM_USING_LTC4558
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+sim_MT6306_status sim_MT6306_retreiveDirectionBaud(sim_HW_cb *hw_cb)
+{
+ kal_uint16 temp_reg;
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+
+ sim_MT6306_checkCtrlPDN(hw_cb);
+
+ /*setting baud rate*/
+ temp_reg = DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK);
+ temp_reg &= SIM_BRR_CLKMSK;
+ temp_reg |= (card_cb->baud << 2);
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) = temp_reg;
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), temp_reg);
+
+ /*setting convention and T0, T1*/
+ temp_reg = DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK);
+ temp_reg &= ~SIM_MT6306_CONFMSK;
+ temp_reg |= (card_cb->config & SIM_MT6306_CONFMSK);
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK) = temp_reg;
+#if defined (__SIM_ATRSTA_BIT_SHIFT__)
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), temp_reg | SIM_CONF_RSTCTL);
+#else
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), temp_reg);
+#endif
+ sim_MT6306_addMsg(SIM_MT6306_RETREIVE_BAUD, hw_cb->simSwitchPortNo, DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK));
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_blockDAT(sim_HW_cb *hw_cb)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ switch (card_cb->pins.DAT)
+ {
+ case sim_MT6306_DATPass_High:
+ case sim_MT6306_NoLDO_DATPass_High:
+ {
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] & (0x1 << MT6306PortNo)) != (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] &= ~(0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+
+ card_cb->pins.DAT &= ~0x1;
+
+ break;
+ }
+ case sim_MT6306_DATBlockedLow:
+ case sim_MT6306_NoLDO_DATBlockedLow:
+ {
+ break;
+ }
+ case sim_MT6306_DATBlockedHigh_Low:
+ case sim_MT6306_NoLDO_DATBlockedHigh_Low:
+ {
+
+ break;
+ }
+ case sim_MT6306_DATBlockedHigh:
+ case sim_MT6306_NoLDO_DATBlockedHigh:
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+#elif defined (DRV_2_SIM_USING_LTC4558)
+
+ if (sim_MT6306_DATPass == card_cb->pins.DAT)
+ {
+ /*we do need to config the switch*/
+
+ /*in LTC4558, we can only select one channel, can't control DAT line separately*/
+ /*to block one channel's dat line, the only way is to select the other channel*/
+ sim_LTC4558_select(1 - MT6302InterfaceNo);
+ card_cb->pins.DAT = sim_MT6302_DATBlockedHigh;
+ card_cb->pins.RST = sim_MT6302_RSTBlockedHigh;
+
+ /*the other interface's state is also changed*/
+ card_cb->pins.DAT = sim_MT6302_DATPass;
+ card_cb->pins.RST = sim_MT6302_RSTPass;
+
+
+ }
+ else if (sim_MT6306_DATBlockedLow == card_cb->pins.DAT)
+ {
+ /*by "block DAT", we mean let switch pull high DAT line. If DAT is low currently, must change its value*/
+ IMPLEMENTING_ASSERT;
+ }
+#endif
+ sim_MT6306_addMsg(SIM_MT6306_BLOCK_DAT, MT6306PortNo, card_cb->pins.DAT, card_cb->pins.DAT);
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_blockRST(sim_HW_cb *hw_cb)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ switch (card_cb->pins.RST)
+ {
+ case sim_MT6306_RSTPass_High:
+ case sim_MT6306_RSTPass_Low:
+ case sim_MT6306_NoLDO_RSTPass_High:
+ case sim_MT6306_NoLDO_RSTPass_Low:
+ {
+ if (switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] & (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+ /*to block RST, we only need to set 1<<interface*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] |= (0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST]);
+
+ card_cb->pins.RST |= 0x1;
+ break;
+ }
+ case sim_MT6306_RSTBlockedHigh:
+ case sim_MT6306_RSTBlockedLow:
+ case sim_MT6306_NoLDO_RSTBlockedHigh:
+ case sim_MT6306_NoLDO_RSTBlockedLow:
+ break;
+ default :
+ SIM_DEBUG_ASSERT(0);
+ }
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ if (sim_MT6306_RSTPass == card_cb->pins.RST)
+ {
+ /*we do need to config the switch*/
+
+ /*in LTC4558, we can only select one channel, can't control RST line separately*/
+ /*to block one channel's RST line, the only way is to select the other channel*/
+ sim_LTC4558_select(1 - MT6302InterfaceNo);
+
+ /*state of this interface has been changed*/
+ card_cb->pins.DAT = sim_MT6302_DATBlockedHigh;
+ card_cb->pins.RST = sim_MT6302_RSTBlockedHigh;
+
+ /*the other interface's state is also changed*/
+ sim_MT6306_card[1 - MT6302Interface].pins.DAT = sim_MT6306_DATPass;
+ sim_MT6306_card[1 - MT6302Interface].pins.RST = sim_MT6306_RSTPass;
+ }
+#endif
+ sim_MT6306_addMsg(SIM_MT6306_BLOCK_RST, MT6306PortNo, sim_MT6306_card[hw_cb->simInterface].pins.RST, sim_MT6306_card[hw_cb->simInterface].pins.RST);
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_passDAT(sim_HW_cb *hw_cb)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ switch (card_cb->pins.DAT)
+ {
+ case sim_MT6306_DATBlockedHigh:/*b000*/
+ case sim_MT6306_NoLDO_DATBlockedHigh:/*b000*/
+ {
+ if (switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] & (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+
+ /*b00 -> b01*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] |= (0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+
+ card_cb->pins.DAT |= 0x1;
+ break;
+ }
+ case sim_MT6306_DATBlockedLow:/*b101*/
+ case sim_MT6306_NoLDO_DATBlockedLow:/*b101*/
+ {
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] & (0x5 << MT6306PortNo)) != (0x5 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+
+ /*b101->b001*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] &= ~(0x4 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+
+ card_cb->pins.DAT &= ~0x4;
+ break;
+ }
+ case sim_MT6306_DATBlockedHigh_Low:
+ case sim_MT6306_NoLDO_DATBlockedHigh_Low:
+ {
+ IMPLEMENTING_ASSERT;
+ }
+ case sim_MT6306_DATPass_High:
+ case sim_MT6306_NoLDO_DATPass_High:
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ if (sim_MT6306_DATBlockedHigh == card_cb->pins.DAT)
+ {
+ /*we do need to config the switch*/
+ /*in LTC4558, we can only select one channel, can't control DAT line separately*/
+ /*to pass one channel's dat line, the only way is to select this channel*/
+ sim_LTC4558_select(simInterface);
+ card_cb->pins.DAT = sim_MT6306_DATPass;
+ card_cb->pins.RST = sim_MT6306_RSTPass;
+
+ /*the other interface's state is also changed*/
+ sim_MT6306_card[1 - simInterface].pins.DAT = sim_MT6306_DATBlockedHigh;
+ sim_MT6306_card[1 - simInterface].pins.RST = sim_MT6306_RSTBlockedHigh;
+ }
+ else if (sim_MT6306_DATBlockedLow == card_cb->pins.DAT)
+ {
+ /*it's impossible for LTC4558 to be in this state*/
+ IMPLEMENTING_ASSERT;
+ }
+#endif
+ sim_MT6306_addMsg(SIM_MT6306_PASS_DAT, hw_cb->simInterface, sim_MT6306_card[hw_cb->simInterface].pins.DAT, sim_MT6306_card[hw_cb->simInterface].pins.DAT);
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_passRST(sim_HW_cb *hw_cb)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ switch (card_cb->pins.RST)
+ {
+ case sim_MT6306_RSTBlockedHigh:
+ case sim_MT6306_RSTBlockedLow:
+ case sim_MT6306_NoLDO_RSTBlockedHigh:
+ case sim_MT6306_NoLDO_RSTBlockedLow:
+ {
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] & (0x1 << MT6306PortNo)) != (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+
+ /*to pass RST, we only need to clear 1<<interface*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] &= ~(0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST]);
+
+ card_cb->pins.RST &= ~0x1;
+
+ break;
+ }
+ case sim_MT6306_RSTPass_High:
+ case sim_MT6306_RSTPass_Low:
+ case sim_MT6306_NoLDO_RSTPass_High:
+ case sim_MT6306_NoLDO_RSTPass_Low:
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ if (sim_MT6306_RSTBlockedHigh == card_cb->pins.RST || sim_MT6306_RSTBlockedLow == card_cb->pins.RST)
+ {
+ /*in LTC4558, we can only select one channel, can't control RST line separately*/
+ /*to pass one channel's RST line, the only way is to select this channel*/
+ sim_LTC4558_select(simInterface);
+ card_cb->pins.DAT = sim_MT6306_DATPass;
+ card_cb->pins.RST = sim_MT6306_RSTPass;
+
+ /*the other interface's state is also changed*/
+ sim_MT6306_card[1 - simInterface].pins.DAT = sim_MT6306_DATBlockedHigh;
+ sim_MT6306_card[1 - simInterface].pins.RST = sim_MT6306_RSTBlockedHigh;
+ }
+#endif
+ sim_MT6306_addMsg(SIM_MT6306_PASS_RST, MT6306PortNo, sim_MT6306_card[hw_cb->simInterface].pins.RST, sim_MT6306_card[hw_cb->simInterface].pins.RST);
+
+ return sim_MT6306_statusNoError;
+}
+
+
+sim_MT6306_status sim_MT6306_passCLK(sim_HW_cb *hw_cb)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ switch (card_cb->pins.CLK)
+ {
+ case sim_MT6306_CLKBlockedHigh:
+ case sim_MT6306_NoLDO_CLKBlockedHigh:
+ {
+ /*should be 0x5<<interface, others assert*/
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] & (0x5 << MT6306PortNo)) != (0x5 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+ /*original is 0x5<<interface, now change to 0x1<<interface, mask 0x4<<interface*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] &= ~(0x4 << MT6306PortNo);
+
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK]);
+ card_cb->pins.CLK &= 0xf0;// we must preserve the information of LDO state
+ card_cb->pins.CLK |= sim_MT6306_CLKPass;
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] & (0x5 << MT6306PortNo)) != (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ case sim_MT6306_CLKBlockedLow:
+ case sim_MT6306_NoLDO_CLKBlockedLow:
+ {
+ /*should be 0x0<<interface, others assert*/
+ if (switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] & (0x5 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+ /*original is 0x0<<interface, now change to 0x1<<interface, set 0x1<<interface*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] |= (0x1 << MT6306PortNo);
+
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK]);
+ card_cb->pins.CLK &= 0xf0;// we must preserve the information of LDO state
+ card_cb->pins.CLK |= sim_MT6306_CLKPass;
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] & (0x5 << MT6306PortNo)) != (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ case sim_MT6306_CLKPass:
+ case sim_MT6306_NoLDO_CLKPass:
+ break;
+ case sim_MT6306_CLKInvalidState:
+ case sim_MT6306_NoLDO_CLKInvalidState:
+ SIM_DEBUG_ASSERT(0);
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ if (sim_MT6306_CLKBlockedHigh == card_cb->pins.CLK)
+ {
+ /*it's impossible for LTC4558 to be in this state*/
+ IMPLEMENTING_ASSERT;
+ }
+ else if (sim_MT6306_CLKBlockedLow == card_cb->pins.CLK)
+ {
+ /*to pass CLK to interface not selected, must use CLKRUN to pass the Clk*/
+ /*we don't select interface here, since if we do need to select interface, it can be done when pass other signals*/
+
+ sim_LTC4558_CLKCtrl(MT6306Interface, 1);
+ /*state of this interface has been changed*/
+ card_cb->pins.CLK = sim_MT6306_CLKPass;
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+#endif
+
+ sim_MT6306_ClearCSTOP(hw_cb);
+
+ /*if SIM controller is now clk running, from card's viewpoint, its clk is now starting*/
+ if ((DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_HALT) == 0x0)
+ {
+ switch_CB->sim_MT6306_needCLKStartTimeout = KAL_TRUE;
+ }
+ sim_MT6306_addMsg(SIM_MT6306_PASS_CLK, hw_cb->simInterface, sim_MT6306_card[hw_cb->simInterface].pins.CLK, sim_MT6306_card[hw_cb->simInterface].pins.CLK);
+ return sim_MT6306_statusNoError;
+}
+kal_bool MT6306_ShowReg(int chip)
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ return KAL_TRUE;
+
+}
+sim_MT6306_status sim_MT6306_blockCLK(sim_HW_cb *hw_cb)
+{
+ Sim_Card *simCard;
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+ usim_dcb_struct *usim_dcb;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+ DRV_GET_RET_ADDR(retAddr);
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ simCard = GET_SIM_CB(hw_cb->simInterface);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+ sim_MT6306_addMsg(SIM_MT6306_BLOCK_CLK_BEGIN, hw_cb->simInterface, (kal_uint32)retAddr, sim_MT6306_card[1].pins.CLK);
+
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ switch (card_cb->pins.CLK)
+ {
+ case sim_MT6306_CLKPass:
+ case sim_MT6306_NoLDO_CLKPass:
+ {
+ /*should be 0x1<<interface, others assert*/
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] & (0x5 << MT6306PortNo)) != (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+
+ /*if clock stop is not enable and not manual control, there is something wrong*/
+ if (!simCard->clkStop && !usim_dcb->clock_stop_en) /*both states in sim and usim are not enabled*/
+ {
+ /*we must allow clkstop when we doing manual control, manul control is the back door to clk control*/
+ /*for case that SIM1 PTS failed and deactive, we wato block signal and do SIM2 command, this case should be allowed*/
+ if (KAL_FALSE == switch_CB->sim_MT6306_needManualControl && sim_MT6306_stateClkRunning == card_cb->state)
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ else
+ {
+ /*when we block clk in manual control, we just want to block it low*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] &= ~(0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK]);
+ card_cb->pins.CLK &= 0xf0;//preserve LDO state
+ card_cb->pins.CLK |= sim_MT6306_CLKBlockedLow;
+ }
+ }
+
+ if (simCard->clkStopLevel || CLOCK_STOP_HIGH == usim_dcb->clock_stop_type)
+ {
+ /*original is 0x1<<interface, now change to 0x5<<interface, set 0x5<<interface*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] |= (0x5 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK]);
+ card_cb->pins.CLK &= 0xf0;//preserve LDO state
+ card_cb->pins.CLK |= sim_MT6306_CLKBlockedHigh;
+ }
+ else
+ {
+ /*original is 0x1<<interface, now change to 0x0<<interface, mask 0x1<<interface*/
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] &= ~(0x1 << MT6306PortNo);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK]);
+ card_cb->pins.CLK &= 0xf0;//preserve LDO state
+ card_cb->pins.CLK |= sim_MT6306_CLKBlockedLow;
+ }
+ if ((switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] & (0x5 << MT6306PortNo)) == (0x1 << MT6306PortNo))
+ SIM_DEBUG_ASSERT(0);
+
+ break;
+ }
+ case sim_MT6306_CLKBlockedHigh:
+ case sim_MT6306_CLKBlockedLow:
+ case sim_MT6306_NoLDO_CLKBlockedHigh:
+ case sim_MT6306_NoLDO_CLKBlockedLow:
+ break;
+ case sim_MT6306_CLKInvalidState:
+ case sim_MT6306_NoLDO_CLKInvalidState:
+ SIM_DEBUG_ASSERT(0);
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ /*need to stop the clock according to its clk stop level*/
+ if (sim_MT6306_CLKPass == card_cb->pins.CLK)
+ {
+
+ /*in LTC4558, if we want to stop interface's clock, we must select other interface then block the clock*/
+ sim_LTC4558_select(1 - simInterface);
+
+ /*we don't de-select interface here, since if we do need to de-select interface, it can be done when block other signals*/
+ sim_LTC4558_CLKCtrl(simInterface, 0);
+ card_cb->pins.CLK = sim_MT6306_CLKBlockedLow;
+ }
+#endif
+
+ sim_MT6306_SetCSTOP(hw_cb);
+
+ sim_MT6306_addMsg(SIM_MT6306_BLOCK_CLK, hw_cb->simInterface, sim_MT6306_card[hw_cb->simInterface].pins.CLK, sim_MT6306_card[hw_cb->simInterface].pins.CLK);
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_blockAllSignal(sim_HW_cb *hw_cb)
+{
+ kal_uint32 MT6306PortNo;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ MT6306PortNo = hw_cb->simSwitchPortNo;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ /*handle DAT*/
+ sim_MT6306_blockDAT(hw_cb);
+
+
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Port:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, MT6306PortNo);
+
+ /*handle RST*/
+#ifdef __DRV_2_SIM_USING_MT6306__
+ /*set RST to suitable level if not yet config*/
+ if (sim_MT6306_cardTypeAL == card_cb->type && !(switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] & (0x4 << MT6306PortNo)))
+ {
+ sim_MT6306_setRST(hw_cb, 1);
+ }
+ else if (sim_MT6306_cardTypeIR == card_cb->type && (switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] & (0x4 << MT6306PortNo)))
+ {
+ sim_MT6306_setRST(hw_cb, 0);
+ }
+#endif
+
+ sim_MT6306_blockRST(hw_cb);
+
+ /*handle CLK*/
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if ((card_cb->pins.CLK & 0x10) != 0x10) /*in MT6306, if VCC ldo is not enable, the CLK is always down*/
+#endif
+ {
+ sim_MT6306_blockCLK(hw_cb);
+ if (card_cb->state == sim_MT6306_stateClkRunning)
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkStopped);
+ }
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_activateSIMCtrl(sim_HW_cb *hw_cb)
+{
+
+ sim_MT6306_checkCtrlPDN(hw_cb);
+
+ /*set controller to activate*/
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0x0001);
+
+ sim_MT6306_addMsg(SIM_MT6306_ACT_SIM_CTRL, 0, 0, 0);
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_deactivateSIMCtrl(sim_HW_cb *hw_cb)
+{
+
+ sim_MT6306_checkCtrlPDN(hw_cb);
+
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) = 0;
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0);
+
+ /*we must wait SIM controller deactive down*/
+#ifdef __MAUI_BASIC__
+ //GPTI_BusyWait(40);
+ SIM_DEBUG_ASSERT(0);
+#else
+ kal_sleep_task(10);
+#endif
+
+ sim_MT6306_addMsg(SIM_MT6306_DEACT_SIM_CTRL, 0, 0, DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK));
+
+ return sim_MT6306_statusNoError;
+}
+
+sim_MT6306_status sim_MT6306_recordDirectionBaud(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ /*record convention*/
+ card_cb->config = DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK);
+
+ /*record baud rare*/
+ card_cb->baud = (DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) & SIM_BRR_ETUMSK) >> 2;
+
+ return sim_MT6306_statusNoError;
+}
+
+
+sim_MT6306_status sim_MT6306_passAllSignal(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+
+ /*handle DAT*/
+ sim_MT6306_passDAT(hw_cb);
+
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ /*handle RST*/
+ sim_MT6306_passRST(hw_cb);
+#endif
+ /*handle CLK*/
+ if (sim_MT6306_CLKPass != card_cb->pins.CLK)
+ sim_MT6306_passCLK(hw_cb);
+
+ /*handle convention & baud rate*/
+ //sim_MT6306_retreiveDirectionBaud(simInterface);
+ return sim_MT6306_statusNoError;
+}
+
+
+
+/*
+* deactivated to deactivated handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_d2D(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ sim_MT6306_addMsg(SIM_MT6306_D2D, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ if (sim_MT6306_eventReset != event)
+ SIM_DEBUG_ASSERT(0);
+ if (0 == hw_cb->simSwitchPeerInterfaceCb)
+ SIM_DEBUG_ASSERT(0);
+ /*make sure block all signals*/
+ sim_MT6306_blockAllSignal(hw_cb->simSwitchPeerInterfaceCb);
+
+ sim_MT6306_passAllSignal(hw_cb);
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* deactivated to clock running handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_d2R(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ Sim_Card *SimCard;
+ sim_MT6306_switchInfo *switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ sim_MT6306_addMsg(SIM_MT6306_D2R, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ /*we can only accept this case if B can't stop clock, check it*/
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ /* MAUI_03018847
+ 1. sim card support clock stop, if clock stop successfully, it should not enter this state
+ 2. sim card start clock stop timer
+ 3. sim card has been reset, and clock stop timer is stopped
+ 4. enter this wrong state
+ 5. add SimCard->clkstoping for checking. It is impossible clock is stopping and entering d2R state */
+ if ((KAL_FALSE != SimCard->clkStop) &&
+ (SimCard->clkstoping == KAL_TRUE))
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ else /*now that B can't stop clok, we must check that SIM controller must clk running now*/
+ {
+ if (DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) != 0x1)
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ sim_MT6306_blockAllSignal(hw_cb->simSwitchPeerInterfaceCb);
+
+ /*not like D2S scenario, in D2R, controller is still clk running, we don't need to activate controller*/
+
+ /*no matter what event we want to do, DAT should pass*/
+ sim_MT6306_passDAT(hw_cb);
+
+ if (sim_MT6306_eventCommand != event)
+ {
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ sim_MT6306_passRST(hw_cb);
+#endif
+ }
+
+ switch_CB->sim_waitHisrCb_MT6306 = hw_cb;
+ switch_CB->usim_waitHisrCb_MT6306 = hw_cb;
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* deactivated to clock Stopped handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_d2S(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ sim_MT6306_cardInfo *card_cb;
+ sim_MT6306_switchInfo *switch_CB;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ Sim_Card *SimCard = GET_SIM_CB(hw_cb->simInterface);
+ sim_MT6306_addMsg(SIM_MT6306_D2S, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ /*make sure block all signals of both cards then activate sim controller*/
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ sim_MT6306_blockAllSignal(hw_cb->simSwitchPeerInterfaceCb);
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ /* in LTC4558, we can only make switch to stay in one interface, of course can't stay in the interface we want to keep alive
+ * We stay in original deactivate interface, and close its power, then activate SIM controller
+ */
+
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+ sim_MT6306_blockAllSignal(hw_cb);
+ kal_uint32 tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+
+
+ //Enable PMIC
+#if !defined(__DRV_SIM_SIMIF_CONTROL_VSIM__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_TRUE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_TRUE);
+ }
+#endif
+ /*activate SIM controller*/
+ sim_MT6306_activateSIMCtrl(hw_cb);
+
+ /*must polling until activation done before changing to another interface, this is a bad method, just for experiment.
+ maybe design a small HISR and hook dynamically then wait event is better*/
+ //if(((*(kal_uint16 *)0x80140070) & 0x180) == 0);
+ //kal_sleep_task(30000);
+
+ //SIM_DisAllIntr(simInterface);
+ //DRV_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_NATR);
+ //while(DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK) != SIM_STS_NATR);
+
+ /*polling until SIM controller stay in state 8*/
+#if defined (__SIM_ATRSTA_BIT_SHIFT__)
+ while (DRV_Reg(SIM0_BASE_ADDR_MTK + 0x0070) != 0x200)
+#else
+ while ((DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & (SIM_ATRSTA_IR | SIM_ATRSTA_AL)) == 0)
+ //while(1)
+#endif
+ {
+ kal_sleep_task(2);
+ }
+
+
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+
+ //SIM_WaitEvent(SimCard, ACTIVATE_DONE);
+
+ /*we will connect B's signals, must take care of which type card B is, IR or AL*/
+ if (sim_MT6306_cardTypeIR == card_cb->type)
+ {
+ /*since wr want to do reset or power off, it should not matter even RST park at high for a while, just record the event*/
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ sim_MT6306_passAllSignal(hw_cb);
+ if (sim_MT6306_eventCommand == event) SimCard->t_debug[1] = ust_get_current_time();
+
+ switch_CB->sim_waitHisrCb_MT6306 = hw_cb;
+ switch_CB->usim_waitHisrCb_MT6306 = hw_cb;
+
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* clock running to deactivated handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_r2D(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ Sim_Card *peerSimCard;
+ sim_HW_cb *peerHWCb;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb, *peerCard_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ card_cb = card_cb;
+ sim_MT6306_addMsg(SIM_MT6306_R2D, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ if (sim_MT6306_eventReset != event)
+ SIM_DEBUG_ASSERT(0);
+
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ peerSimCard = GET_SIM_CB(peerHWCb->simInterface);
+ peerCard_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+ if (KAL_FALSE == peerSimCard->clkStop)
+ {
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ /*non-clkStop card, need special action*/
+ /*block A's DAT*/
+ sim_MT6306_blockDAT(peerHWCb);
+
+ /*in most case, we block RST to high, pull it low now*/
+ sim_MT6306_setRST(hw_cb, 0);
+
+ /*
+ in design spec, we have to do following:
+ (1)raise B's VCC, (2)pass B's CLK, (3)pass B's DAT, (4)set timeout, (5)raise B's RST to replace SIM controller's activation
+ we do nothing but set a flag here, usim_activation and SIM_initialize will check this flag then call our API to activate.
+ */
+ switch_CB->sim_MT6306_needManualControl = KAL_TRUE;
+
+ return sim_MT6306_statusNoError;
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ IMPLEMENTING_ASSERT;
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+ }
+
+ /*since we will block A's siganl, this means to stop its clk, must take care whether A's clk-stop timer expire or not*/
+#ifdef __MAUI_BASIC__
+ //GPTI_BusyWait(20);
+ SIM_DEBUG_ASSERT(0);
+#else
+ sim_MT6306_clkStopTimerStop(peerHWCb);
+ kal_sleep_task(5);
+#endif
+
+ /*stop all signal of A*/
+ sim_MT6306_blockAllSignal(hw_cb->simSwitchPeerInterfaceCb);
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_stateClkRunning == peerCard_cb->state)
+ sim_MT6306_setCardState(peerHWCb, sim_MT6306_stateClkStopped);
+#endif
+
+#ifdef DRV_2_SIM_USING_LTC4558
+ /*following code should be wrong and should be the same as MT6306's case, but LTC4558 has finished its UT, I don't want to modify this part in case this was intended to do*/
+ if (sim_MT6306_stateClkRunning == peerCard_cb->state)
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkStopped);
+#endif
+
+ /*in design spec, we assume controller is in IR or LA state, make sure controller is not in deactivation state*/
+
+#ifdef __DRV_2_SIM_USING_MT6306__ /*in LTC4558, if we select B, then A's signal will connected*/
+ /*block B's signal*/
+ sim_MT6306_blockAllSignal(hw_cb);
+#endif
+
+ /*deactivate SIM controller to stand the same position with B*/
+ sim_MT6306_deactivateSIMCtrl(hw_cb);
+
+ /*connect all signal to B*/
+ sim_MT6306_passAllSignal(hw_cb);
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* clock running to clock running handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_r2R(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *peerHWCb;
+ sim_MT6306_cardInfo *card_cb, *peerCard_cb;
+ sim_MT6306_switchInfo *switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+
+ sim_MT6306_addMsg(SIM_MT6306_R2R, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ peerCard_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+ if (sim_MT6306_CLKPass != sim_MT6306_card[hw_cb->simInterface].pins.CLK || sim_MT6306_CLKPass != sim_MT6306_card[peerHWCb->simInterface].pins.CLK)
+ SIM_DEBUG_ASSERT(0);
+
+ if (sim_MT6306_eventCommand == event)
+ {
+ sim_MT6306_blockDAT(peerHWCb);
+ sim_MT6306_passDAT(hw_cb);
+
+#ifdef DRV_2_SIM_USING_LTC4558
+ card_cb->pins.CLK = sim_MT6306_CLKPass;
+#endif
+ /* [MAUI_03053369][1] Assert Fail: icc_switchControl2_mt6306.c 1502 -SIM*/
+ /*
+ we may encounter send command and cmd timeout. In this case, we should manual deactivate card
+ */
+ switch_CB->sim_MT6306_needManualControl = KAL_TRUE;
+
+ }
+ else/*reset or power off*/
+ {
+ SimCard = GET_SIM_CB(peerHWCb->simInterface);
+ if (KAL_FALSE == SimCard->clkStop)
+ {
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ /*non-clkStop card, need special action*/
+ /*block A's DAT*/
+ sim_MT6306_blockDAT(peerHWCb);
+
+ /*in most case, we block RST to high, pull it low now*/
+ sim_MT6306_setRST(hw_cb, 0);
+
+ /*
+ in design spec, we have to do following:
+ (1)raise B's VCC, (2)pass B's CLK, (3)pass B's DAT, (4)set timeout, (5)raise B's RST to replace SIM controller's activation
+ we do nothing but set a flag here, usim_activation and SIM_initialize will check this flag then call our API to activate.
+ */
+ switch_CB->sim_MT6306_needManualControl = KAL_TRUE;
+
+ return sim_MT6306_statusNoError;
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ IMPLEMENTING_ASSERT;
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+
+ }
+ else
+ {
+ /*since we will block A's siganl, this means to stop its clk, must take care whether A's clk-stop timer expire or not*/
+#ifdef __MAUI_BASIC__
+ //GPTI_BusyWait(20);
+ SIM_DEBUG_ASSERT(0);
+#else
+ sim_MT6306_clkStopTimerStop(peerHWCb);
+ kal_sleep_task(5);
+#endif
+
+ /*block all A's signal*/
+ sim_MT6306_blockAllSignal(peerHWCb);
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_stateClkRunning == peerCard_cb->state)
+ sim_MT6306_setCardState(peerHWCb, sim_MT6306_stateClkStopped);
+#endif
+
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_cardTypeIR == card_cb->type)
+ {
+ /*keep B's RST low, should to consider if we want to reset after deactivating, when to connect RST signal*/
+ /*if want to do power off, keep low is fine, if want to do reset, IR card need not RST to pull high*/
+ sim_MT6306_setRST(hw_cb, 0);
+ sim_MT6306_blockRST(hw_cb);
+ }
+ else
+ {
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ sim_MT6306_passRST(hw_cb);
+#endif
+ }
+#endif
+
+ /*CLK is connected, just need to pass DAT*/
+ sim_MT6306_passDAT(hw_cb);
+ }
+ }
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* clock running to clock stopped handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_r2S(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *peerHWCb;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb, *peerCard_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ sim_MT6306_addMsg(SIM_MT6306_R2S, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ peerCard_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+
+ if (sim_MT6306_eventCommand == event)
+ {
+ sim_MT6306_blockDAT(peerHWCb);
+ sim_MT6306_passCLK(hw_cb);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ SimCard->t_debug[1] = ust_get_current_time();
+ sim_MT6306_passDAT(hw_cb);
+ /* [MAUI_03053369][1] Assert Fail: icc_switchControl2_mt6306.c 1502 -SIM*/
+ /*
+ we may encounter send command and cmd timeout. In this case, we should manual deactivate card
+ */
+ switch_CB->sim_MT6306_needManualControl = KAL_TRUE;
+
+ }
+ else/*reset or power off*/
+ {
+ SimCard = GET_SIM_CB(peerHWCb->simInterface);
+ if (KAL_FALSE == SimCard->clkStop)
+ {
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ /*non-clkStop card, need special action*/
+ /*block A's DAT*/
+ sim_MT6306_blockDAT(peerHWCb);
+
+ /*in most case, we block RST to high, pull it low now*/
+ sim_MT6306_setRST(hw_cb, 0);
+
+ /*
+ in design spec, we have to do following:
+ (1)raise B's VCC, (2)pass B's CLK, (3)pass B's DAT, (4)set timeout, (5)raise B's RST to replace SIM controller's activation
+ we do nothing but set a flag here, usim_activation and SIM_initialize will check this flag then call our API to activate.
+ */
+ switch_CB->sim_MT6306_needManualControl = KAL_TRUE;
+
+ return sim_MT6306_statusNoError;
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ IMPLEMENTING_ASSERT;
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+
+ }
+ else
+ {
+ /*block all A's signal*/
+ /*Be careful!!!, if we block A's clock now, it means we stop A's clock, need to consider the 1860 clk, about 1ms*/
+ sim_MT6306_clkStopTimerStop(peerHWCb);
+ kal_sleep_task(2);
+ sim_MT6306_blockAllSignal(peerHWCb);
+ if (sim_MT6306_stateClkRunning == peerCard_cb->state)
+ sim_MT6306_setCardState(peerHWCb, sim_MT6306_stateClkStopped);
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_cardTypeIR == card_cb->type)
+ {
+ /*keep B's RST low, should to consider if we want to reset after deactivating, when to connect RST signal*/
+ /*if want to do power off, keep low is fine, if want to do reset, IR card need not RST to pull high*/
+ sim_MT6306_setRST(hw_cb, 0);
+ sim_MT6306_blockRST(hw_cb);
+ }
+ else
+ {
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ /*pass B's RST*/
+ sim_MT6306_passRST(hw_cb);
+#endif
+ }
+
+ /*pass B's clk*/
+ sim_MT6306_passCLK(hw_cb);
+#endif
+
+#ifdef DRV_2_SIM_USING_LTC4558
+ /*in LTC4558, when we block A's signal, we connect B's signal, though controller's CLK maybe stopped*/
+ card_cb->pins.CLK = sim_MT6306_CLKPass;
+#endif
+ /*CLK is connected, just need to pass DAT*/
+ sim_MT6306_passDAT(hw_cb);
+ }
+ }
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* clock stopped to deactivated handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_s2D(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *peerHWCb;
+
+ sim_MT6306_addMsg(SIM_MT6306_S2D, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+
+
+ if (sim_MT6306_eventReset != event)
+ SIM_DEBUG_ASSERT(0);
+
+ SimCard = GET_SIM_CB(peerHWCb->simInterface);
+
+ /*If A's clkstop is false, we can never stop A's clk*/
+ if (KAL_FALSE == SimCard->clkStop)
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ /*stop all signal of A*/
+ sim_MT6306_blockAllSignal(peerHWCb);
+
+ /*in design spec, we assume controller is in IR or LA state, make sure controller is not in deactivation state*/
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ /*block B's signal*/
+ sim_MT6306_blockAllSignal(hw_cb);
+#endif
+ /*deactivate SIM controller to stand the same position with B*/
+ sim_MT6306_deactivateSIMCtrl(hw_cb);
+
+ /*connect all signal to B*/
+ sim_MT6306_passAllSignal(hw_cb);
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* clock stopped to clock running handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_s2R(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ switch_CB = switch_CB;
+ sim_MT6306_addMsg(SIM_MT6306_S2R, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ if (sim_MT6306_eventCommand == event)
+ {
+ sim_MT6306_blockDAT(hw_cb->simSwitchPeerInterfaceCb);
+ sim_MT6306_passDAT(hw_cb);
+ }
+ else/*reset or power off*/
+ {
+
+ /*block all A's signal*/
+ sim_MT6306_blockAllSignal(hw_cb->simSwitchPeerInterfaceCb);
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_cardTypeIR == card_cb->type)
+ {
+ /*keep B's RST low, should to consider if we want to reset after deactivating, when to connect RST signal*/
+ sim_MT6306_setRST(hw_cb, 0);
+ sim_MT6306_blockRST(hw_cb);
+ }
+ else
+ {
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ sim_MT6306_passRST(hw_cb);
+#endif
+ }
+#endif
+
+ /*CLK is connected, just need to pass DAT*/
+ sim_MT6306_passDAT(hw_cb);
+ }
+
+ return sim_MT6306_statusNoError;
+}
+
+/*
+* clock stopped to clock stopped handler
+* simInterface: target interface that we want to switch to
+*/
+sim_MT6306_status sim_MT6306_s2S(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+ Sim_Card *SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ switch_CB = switch_CB;
+ sim_MT6306_addMsg(SIM_MT6306_S2S, hw_cb->simSwitchChipNo, event, hw_cb->simInterface);
+
+ if (sim_MT6306_eventCommand == event)
+ {
+ sim_MT6306_blockDAT(hw_cb->simSwitchPeerInterfaceCb);
+
+ /*controller's clk should be enabled in driver, we just connect CLK now*/
+ sim_MT6306_passCLK(hw_cb);
+ SimCard->t_debug[1] = ust_get_current_time();
+ sim_MT6306_passDAT(hw_cb);
+ }
+ else/*reset or power off*/
+ {
+ /*block all A's signal*/
+ sim_MT6306_blockAllSignal(hw_cb->simSwitchPeerInterfaceCb);
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_cardTypeIR == card_cb->type)
+ {
+ /*keep B's RST low, should to consider if we want to reset after deactivating, when to connect RST signal*/
+ sim_MT6306_setRST(hw_cb, 0);
+ sim_MT6306_blockRST(hw_cb);
+ }
+ else
+ {
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ sim_MT6306_passRST(hw_cb);
+#endif
+ }
+#endif
+
+#ifdef DRV_2_SIM_USING_LTC4558
+ /*in LTC4558, when we block A's signal, we connect B's signal, though controller's CLK maybe stopped*/
+ card_cb->pins.CLK = sim_MT6306_CLKPass;
+#endif
+ /*CLK is connected, just need to pass DAT*/
+ sim_MT6306_passCLK(hw_cb);
+
+ sim_MT6306_passDAT(hw_cb);
+
+ }
+
+ return sim_MT6306_statusNoError;
+}
+sim_MT6306_status sim_MT6306_change(
+ sim_HW_cb *hw_cb,
+ sim_MT6306_changeEvent event
+)
+{
+ kal_uint32 handlerIndex;
+ Sim_Card *SimCard;
+ sim_HW_cb *peerHWCb;
+
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb, *peerCard_cb;
+ kal_uint32 t2, t1;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ MT6306_DBG("[%s] interface:%d, thread:%x\n\r", __func__, hw_cb->simInterface, (kal_uint32)kal_get_current_thread_ID());
+ /*semaphore protect*/
+ if (timeout_handler_start[hw_cb->simInterface] != 0 &&
+ ust_us_duration(timeout_handler_start[hw_cb->simInterface], ust_get_current_time()) > 3000000)
+ SIM_DEBUG_ASSERT(0);
+ timeout_handler_start[hw_cb->simInterface] = 0;
+ kal_take_sem(switch_CB->sim_MT6306_arb, KAL_INFINITE_WAIT);
+
+ switch_CB->sim_MT6306_taskAccessing = KAL_TRUE;
+ Data_Sync_Barrier();
+
+ /*in MT6306 driver, one SIMIF may surve multiple cards, we need record the current master*/
+ sim_set_logical_to_SIMIF(sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface), hw_cb->simInterface);
+
+ MT6306_RACE_PROTECT(sim_MT6306_protectionChange);
+
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ peerCard_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+
+ /*we are ready to seving this interface, stop its clk-stop gpt timer now*/
+ sim_MT6306_clkStopTimerStop(hw_cb);
+ sim_MT6306_deClkStopQueue(hw_cb);
+ switch_CB->sim_MT6306_needCLKStartTimeout = KAL_FALSE;
+
+
+
+ if (switch_CB->sim_MT6306_CLKStopping == KAL_TRUE)
+ {
+ t1 = SIM_GetCurrentTime();
+ do
+ {
+ //Wait until clock stop done
+ kal_sleep_task(1);
+ t2 = SIM_GetCurrentTime();
+ }
+ while (switch_CB->sim_MT6306_CLKStopping == KAL_TRUE);// Clock is being stopped( I2C writting)
+ MT6306_DBG("[%s]: Interface:%d, Clock Stopping take:%d\r\n", __func__, hw_cb->simInterface, t2 - t1);
+ if (t2 - t1 > 10000)
+ SIM_DEBUG_ASSERT(0);
+ }
+ /*from 2/18 meeting minutes, SIM controller's clk must run before we pass MT6306's clk*/
+ if (sim_MT6306_eventCommand == event)
+ sim_PDNDisable_MT6306(hw_cb);
+
+ SimCard = GET_SIM_CB(peerHWCb->simInterface);
+ /*current connection check*/
+ if (switch_CB->sim_MT6306_servingInterface == hw_cb->simInterface)
+ {
+ /*we don't need to switch, must take care on reset, power off commands*/
+
+ /*in MT6306, we block DAT and RST in EOC to protect any signal error, we have to pass them now*/
+#ifdef __DRV_2_SIM_USING_MT6306__
+ /*pass DAT, maybe for some card, we can't pass DAT, need more revise*/
+ sim_MT6306_passDAT(hw_cb);
+
+ /*for reset and power off, we have to pass RST, but there maybe some card can't pass, have to revise*/
+ if (sim_MT6306_eventCommand != event)
+ {
+#if !defined (__SIM_DRV_ENABLE_MT6306_SAVE_RST_PIN__)
+ if (sim_MT6306_stateClkRunning != peerCard_cb->state)
+ sim_MT6306_passRST(hw_cb);
+#endif
+ }
+
+ /*we may have blocked CLK, no matter we will do command or reset, power off, we have to pass clk*/
+ if ((card_cb->pins.CLK & 0x07) != sim_MT6306_CLKPass)
+ {
+ sim_MT6306_passCLK(hw_cb);
+ SimCard->t_debug[1] = ust_get_current_time();
+
+ /*if SIM controller is now clk running, from card's viewpoint, its clk is now starting*/
+ if ((DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_HALT) == 0x0)
+ switch_CB->sim_MT6306_needCLKStartTimeout = KAL_TRUE;
+ }
+
+#endif
+
+ /*what if A's clock is running, which means its CLK is pass, and we want to do reset or power off now*/
+ if (sim_MT6306_stateClkRunning == peerCard_cb->state)
+ {
+ switch_CB->sim_MT6306_needManualControl = KAL_TRUE; //In case of command fail->powoff. Need to manul powoff if peer is clk running
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ if (sim_MT6306_eventCommand != event)
+ {
+ if (KAL_TRUE == SimCard->clkStop)
+ {
+ /*since we will block A's siganl, this means to stop its clk, must take care whether A's clk-stop timer expire or not*/
+// dbg_print("we use a bad delay to avoid blocking A's signal before clk-stop timer expire\n\r");
+#ifdef __MAUI_BASIC__
+ //GPTI_BusyWait(20);
+ SIM_DEBUG_ASSERT(0);
+#else
+ sim_MT6306_clkStopTimerStop(peerHWCb);
+ kal_sleep_task(5);
+#endif
+ sim_MT6306_blockAllSignal(peerHWCb);
+
+ sim_MT6306_setCardState(peerHWCb, sim_MT6306_stateClkStopped);
+ }
+ else
+ {
+
+ /*block A's DAT*/
+ sim_MT6306_blockDAT(peerHWCb);
+
+ sim_MT6306_blockRST(hw_cb);
+ /*in most case, we block RST to high, pull it low now*/
+ sim_MT6306_setRST(hw_cb, 0);
+
+
+ }
+ }
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ dbg_print("havn't implement case 1\n\r");
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+
+ }
+ }
+ else
+ {
+ /*record previous lisr state*/
+ peerCard_cb->lisrState = switch_CB->sim_MT6306_registeredLISR;
+
+ /*change LISR registration if need*/
+ if (switch_CB->sim_MT6306_registeredLISR != card_cb->lisrState)
+ {
+ sim_MT6306_addMsg(SIM_MT6306_CHANGE_LISR, switch_CB->sim_MT6306_registeredLISR, sim_MT6306_card[hw_cb->simInterface].lisrState, sim_MT6306_card[peerHWCb->simInterface].lisrState);
+ if (sim_MT6306_LISRSim == card_cb->lisrState)
+ {
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, SIM_LISR_MT6306, "SIM handler");
+ }
+ else
+ {
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, SIM_LISR2_MT6306, "SIM2 handler");
+ }
+ }
+ else if (sim_MT6306_LISRUsim == card_cb->lisrState)
+ {
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, usim_lisr_MT6306, "USIM_Lisr");
+ }
+ else
+ {
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, usim_lisr2_MT6306, "USIM2_Lisr");
+ }
+ }
+
+ switch_CB->sim_MT6306_registeredLISR = card_cb->lisrState;
+ }
+ else /*for the case that both cards are all activated, and we change from one interface to another*/
+ {
+ if (sim_MT6306_LISRSim == switch_CB->sim_MT6306_registeredLISR)
+ {
+ //sim_waitHisrInterface = hw_cb->MT6306Interface;
+ switch_CB->sim_waitHisrCb_MT6306 = hw_cb;
+ }
+ else if (sim_MT6306_LISRUsim == switch_CB->sim_MT6306_registeredLISR)
+ {
+ //usim_waitHisrInterface = hw_cb->MT6306Interface;
+ switch_CB->usim_waitHisrCb_MT6306 = hw_cb;
+ }
+ }
+
+ /*should not record baud here, should record only after PTS, which is only by the end of l1sim_reset_all*/
+ //sim_MT6306_recordDirectionBaud(1 - simInterface);
+
+ sim_MT6306_retreiveDirectionBaud(hw_cb);
+ /*decide which handler for this*/
+ handlerIndex = (peerCard_cb->state * 3) + card_cb->state;
+ MT6306_DBG("[%s] Hadler:%s(%d), peer state:%d, my state:%d, interface(%d->%d), event:%d\r\n", __func__, mt6306StateStr[handlerIndex], handlerIndex, peerCard_cb->state, card_cb->state, peerHWCb->simInterface, hw_cb->simInterface, event);
+
+ sim_MT6306_handlerTable[handlerIndex](hw_cb , event);
+ }
+
+ /*record the servingInterface, since we judge this by who is the latest interface that controller served*/
+ /*move from EOC to here on 1/22, since there is a case that we didn't do change in power off, since the card is already deactivate, but change this variable since we did EOC*/
+ switch_CB->sim_MT6306_servingInterface = hw_cb->simInterface;
+
+
+ MT6306_RACE_RELEASE(sim_MT6306_protectionChange);
+ return sim_MT6306_statusNoError;
+}
+
+void sim_MT6306_setCardState(sim_HW_cb *hw_cb, sim_MT6306_cardState cardState)
+{
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MT6306_RACE_PROTECT(sim_MT6306_protectionState);
+
+ /*doing state assert*/
+ if (sim_MT6306_stateDeactiavate == card_cb->state)
+ {
+ if (sim_MT6306_stateClkStopped == cardState)
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ sim_MT6306_addMsg(SIM_MT6306_CHANGE_CARD_STATE, hw_cb->simInterface, card_cb->state, cardState);
+ card_cb->state = cardState;
+
+ if (sim_MT6306_stateDeactiavate == cardState)
+ {
+ sim_MT6306_deClkStopQueue(hw_cb);
+ sim_MT6306_addMsg(SIM_MT6306_CLKSTOP_DEQUE, card_cb->state, hw_cb->simInterface, 0);
+
+
+ }
+
+ MT6306_RACE_RELEASE(sim_MT6306_protectionState);
+}
+
+void sim_MT6306_setCardType(sim_HW_cb *hw_cb, sim_MT6306_cardType cardType)
+{
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+
+ sim_MT6306_addMsg(SIM_MT6306_CHANGE_CARD_TYPE, hw_cb->simSwitchChipNo, card_cb->type, cardType);
+
+ card_cb->type = cardType;
+
+}
+
+void sim_MT6306_clkStopTimer(sim_HW_cb *hw_cb);
+void sim_MT6306_endOfAction(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb, *peer_card_cb;
+ sim_HW_cb *peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ Sim_Card *SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ peer_card_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MT6306_DBG("[%s] interface:%d\n\r", __func__, hw_cb->simInterface);
+
+#ifdef __DRV_2_SIM_USING_MT6306__
+ /*hold RST and DAT*/
+ sim_MT6306_blockDAT(hw_cb);
+ if (sim_MT6306_stateDeactiavate != card_cb->state) /*if card is currently active*/
+ {
+#ifdef __DRV_2_SIM_USING_MT6306__
+ if (sim_MT6306_cardTypeAL == card_cb->type)
+ {
+ /*if card is LA card, we should block its RST to high*/
+ sim_MT6306_setRST(hw_cb, 1);
+ }
+ else if (sim_MT6306_cardTypeIR == card_cb->type)
+ {
+ /*if card is IR card, we should block its RST to low*/
+ sim_MT6306_setRST(hw_cb, 0);
+ }
+#endif
+ }
+ sim_MT6306_blockRST(hw_cb);
+#endif
+
+ /*since clkStopper will stop clk depends on in SIM or USIM method, we have to record interface's using LISR now*/
+ card_cb->lisrState = switch_CB->sim_MT6306_registeredLISR;
+
+ if (clockStopQueue[peerHWCb->simInterface].hw_cb != NULL)
+ {
+ if (sim_MT6306_stateDeactiavate == peer_card_cb->state
+ || sim_MT6306_stateClkStopped == peer_card_cb->state
+ || ((peer_card_cb->pins.CLK & 0x07) != sim_MT6306_CLKPass)
+ )
+ {
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, cancel SCLK stop(%d)\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, peerHWCb->simInterface);
+ sim_MT6306_deClkStopQueue(peerHWCb);
+ timeout_handler_start[peerHWCb->simInterface] = 0;
+ }
+ else
+ {
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, stop SCLK(%d)\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo, peerHWCb->simInterface);
+ sim_MT6306_clkStopper(peerHWCb);
+ }
+ }
+ else
+ {
+ // sometimes, the current sim driver deClkStopQueue(peer) when it chanages event
+ timeout_handler_start[peerHWCb->simInterface] = 0;
+ if (sim_MT6306_noneNeedClk(peerHWCb) && (0x1 == DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)))
+ {
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_STOPCLK, peerHWCb->simInterface, 0, drv_get_current_time());
+ /*we don't set clk-stop bit of SIM controller, only power down SIM controller*/
+
+ if (switch_CB->sim_MT6306_LPDisabled == 0) //No other task enter
+ USIM_low_power_related_setting(peerHWCb, USIM_LP_ENABLE);
+#if defined(LPWR_SLIM)
+ if ((switch_CB->sim_MT6306_LPDisabled & (1 << peerHWCb->simSwitchPortNo)) == 0)
+ SleepDrv_UnlockSleep(peerHWCb->smHandler, peerHWCb->sim_task_group);
+#endif
+ }
+ }
+
+ switch_CB->sim_MT6306_needManualControl = KAL_FALSE;
+
+ switch_CB->sim_MT6306_taskAccessing = KAL_FALSE;
+
+ switch_CB->sim_MT6306_LPDisabled &= ~(1 << hw_cb->simSwitchPortNo);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->needStopGptISR = KAL_FALSE;
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ usim_dcb_struct *usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if ((usim_dcb->clock_stop_en == KAL_FALSE && usim_dcb->phy_proto == T1_PROTOCOL)
+ || (SimCard->clkStop == KAL_FALSE && usim_dcb->phy_proto == T0_PROTOCOL))
+ {
+#if defined(LPWR_SLIM)
+ SleepDrv_UnlockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ }
+
+ Data_Sync_Barrier();
+
+ /*handle the semaphore*/
+ kal_give_sem(switch_CB->sim_MT6306_arb);
+
+ if(usim_dcb->stopSimClkInEndOfAction == KAL_TRUE)
+ {
+ if (usim_dcb->phy_proto == T1_PROTOCOL)
+ {
+ usim_dcb->main_state = CLK_STOPPING_STATE;
+ }
+ sim_MT6306_clkStopTimer(hw_cb);
+ usim_dcb->stopSimClkInEndOfAction = KAL_FALSE;
+ }
+}
+
+/* this is to be called by simd, usim driver, to set the voltage level to the card
+* level 0 means 1.8V, 1 means 3V
+*/
+void sim_MT6306_VCCLvlCtrl(sim_HW_cb *hw_cb, kal_uint32 level)
+{
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ sim_MT6306_setVCC(hw_cb, level);
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ /*LTC4558 related init*/
+ sim_LTC4558_VCCLvlCtrl(hw_cb, level);
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+
+}
+
+void sim_MT6306_VCCCtrl(sim_HW_cb *hw_cb, kal_uint32 on)
+{
+#if defined(__DRV_2_SIM_USING_MT6306__)
+ sim_MT6306_switchVCC(hw_cb, on);
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ /*LTC4558 related init*/
+ sim_LTC4558_VCCCtrl(hw_cb, on);
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+
+}
+
+kal_bool sim_MT6306_QueryNeedManualControl(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_switchInfo *switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ return switch_CB->sim_MT6306_needManualControl;
+}
+
+kal_bool sim_MT6306_QuerySIMActive(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+
+ if (sim_MT6306_stateClkRunning == card_cb->state || sim_MT6306_stateClkStopped == card_cb->state)
+ return KAL_TRUE;
+ else
+ return KAL_FALSE;
+}
+
+void sim_MT6306_LISRStateChange(sim_HW_cb *hw_cb, sim_MT6306_LISRState lisrState)
+{
+ sim_MT6306_switchInfo *switch_CB;
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ sim_MT6306_addMsg(SIM_MT6306_CHANGE_CURRENT_LISR, switch_CB->sim_MT6306_registeredLISR, lisrState, 0);
+
+ switch_CB->sim_MT6306_registeredLISR = lisrState;
+}
+
+kal_bool sim_MT6306_allCLKStopped(sim_HW_cb *hw_cb)
+{
+ sim_HW_cb *peerHWCb;
+ sim_MT6306_cardInfo *card_cb, *peerCard_cb;
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ peerCard_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+
+ if (sim_MT6306_stateClkStopped == card_cb->state && sim_MT6306_stateClkStopped == peerCard_cb->state)
+ return KAL_TRUE;
+ else
+ return KAL_FALSE;
+}
+kal_bool sim_MT6306_noneNeedClk(sim_HW_cb *hw_cb)
+{
+ sim_HW_cb *peerHWCb;
+ sim_MT6306_cardInfo *card_cb, *peerCard_cb;
+ //sim_MT6306_switchInfo *switch_CB;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+
+ DRV_GET_RET_ADDR(retAddr);
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+ peerCard_cb = sim_MT6306_get_MT6306CardCB(peerHWCb);
+ sim_MT6306_addMsg(SIM_MT6306_NO_NEED_CLK_BEGIN, hw_cb->simInterface, 1, (kal_uint32)retAddr);
+#if defined(__SIM_DRV_TRACE__)
+
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+
+ MD_TRC_LOG_SIM_DRV_GEMINI_GEN1(FILE_SWITCHCONTROL2, __LINE__,
+ switch_CB->sim_MT6306_needCLKStartTimeout , hw_cb->simInterface, switch_CB->sim_MT6306_taskAccessing, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK),
+ switch_CB->sim_MT6306_needManualControl, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+#endif
+ if (sim_MT6306_stateClkRunning != card_cb->state && sim_MT6306_stateClkRunning != peerCard_cb->state)
+ return KAL_TRUE;
+ else
+ return KAL_FALSE;
+}
+
+
+/*this API may run in timer HISR or task */
+volatile kal_spinlockid spinlockid_clk;
+volatile kal_bool wait_sim_MT6306_clkStopper = KAL_FALSE;
+void sim_MT6306_clkStopper(sim_HW_cb *hw_cb)
+{
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+ DRV_GET_RET_ADDR(retAddr);
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ MT6306_RACE_PROTECT(sim_MT6306_protectionStopper);
+
+ switch_CB->sim_MT6306_CLKStopping = KAL_TRUE;
+
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_STOPCLK_BEGIN, hw_cb->simInterface, (kal_uint32)retAddr, drv_get_current_time());
+
+// if(KAL_TRUE == kal_if_hisr() && KAL_TRUE == switch_CB->sim_MT6306_taskAccessing)
+// SIM_DEBUG_ASSERT(0);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo);
+ if (sim_MT6306_stateClkRunning != card_cb->state)
+ SIM_DEBUG_ASSERT(0);
+ /*caution!!!!!, clk may not be stopped in this stopper, clk maybe stoped while changing interface*/
+ /*this stopper is to stop the clok, if it havn't been stopped*/
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ SimCard = SimCard;
+ /*check whether SIM or USIM state current interface is*/
+ if (sim_MT6306_LISRSim == card_cb->lisrState)
+ {
+
+ sim_MT6306_blockCLK(hw_cb);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkStopped);
+ sim_MT6306_deClkStopQueue(hw_cb);
+ //if(sim_MT6306_allCLKStopped())
+ if (sim_MT6306_noneNeedClk(hw_cb) && (0x1 == DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)))
+ {
+ //sim_MT6306_addMsg(SIM_MT6306_DRIVER_STOPCLK, simInterface, 1, drv_get_gpt_current_time());
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_STOPCLK, hw_cb->simInterface, 1, drv_get_current_time());
+ /*in Gemini we don't need to care what clkStopLevel we set on SIM controller since the level is controller by MT6306*/
+ /*we don't set clk-stop bit of SIM controller, only power down SIM controller*/
+
+ if (switch_CB->sim_MT6306_LPDisabled == 0) //No other task enter
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE);
+#if defined(LPWR_SLIM)
+ if ((switch_CB->sim_MT6306_LPDisabled & (1 << hw_cb->simSwitchPortNo)) == 0)
+ SleepDrv_UnlockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ }
+ }
+ else if (sim_MT6306_LISRUsim == card_cb->lisrState)
+ {
+
+ usim_dcb->main_state = CLK_STOPPED_STATE;
+ sim_MT6306_blockCLK(hw_cb);
+ sim_MT6306_setCardState(hw_cb, sim_MT6306_stateClkStopped);
+ sim_MT6306_deClkStopQueue(hw_cb);
+ //if(sim_MT6306_allCLKStopped())
+ if (sim_MT6306_noneNeedClk(hw_cb) && (0x1 == DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)))
+ {
+ sim_MT6306_addMsg(SIM_MT6306_DRIVER_STOPCLK, hw_cb->simInterface, 0, drv_get_current_time());
+ /*we don't set clk-stop bit of SIM controller, only power down SIM controller*/
+
+ if (switch_CB->sim_MT6306_LPDisabled == 0) //No other task enter
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE);
+#if defined(LPWR_SLIM)
+ if ((switch_CB->sim_MT6306_LPDisabled & (1 << hw_cb->simSwitchPortNo)) == 0)
+ SleepDrv_UnlockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif
+ }
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+
+ SimCard->t_debug[5] = ust_get_current_time();
+ switch_CB->sim_MT6306_CLKStopping = KAL_FALSE;
+ MT6306_RACE_RELEASE(sim_MT6306_protectionStopper);
+ timeout_handler_start[hw_cb->simInterface] = 0;
+}
+
+void sim_MT6306_clkStopQueueHandler(void *parameter)
+{
+ kal_uint32 i;
+ sim_HW_cb *queuedCb, *hw_cb = NULL;
+ sim_MT6306_switchInfo *queued_switch_CB;
+ sim_MT6306_cardInfo *queued_card_cb;
+
+ spiWriterGptTimeoutFlag = KAL_TRUE;
+
+ for (i = 0; 4 > i; i++)
+ {
+ queuedCb = clockStopQueue[i].hw_cb;
+ if (queuedCb != NULL)
+ {
+ kal_take_spinlock(queuedCb->spinlockid, KAL_INFINITE_WAIT);
+ queuedCb->waitGptISR_MT6306 += 1;
+ Data_Sync_Barrier();
+ kal_give_spinlock(queuedCb->spinlockid);
+ queued_switch_CB = sim_MT6306_get_MT6306switchCB(queuedCb);
+ queued_card_cb = sim_MT6306_get_MT6306CardCB(queuedCb);
+ hw_cb = queuedCb;
+
+ if (queuedCb->needStopGptISR
+ || sim_MT6306_stateDeactiavate == queued_card_cb->state
+ || sim_MT6306_stateClkStopped == queued_card_cb->state
+ || ((queued_card_cb->pins.CLK & 0x07) != sim_MT6306_CLKPass)
+ )
+ {
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, cancel\r\n", __func__, queuedCb->simInterface, queued_switch_CB->MT6306ChipNo);
+ sim_MT6306_deClkStopQueue(queuedCb);
+ timeout_handler_start[queuedCb->simInterface] = 0;
+ kal_take_spinlock(queuedCb->spinlockid, KAL_INFINITE_WAIT);
+ queuedCb->waitGptISR_MT6306 -= 1;
+ kal_give_spinlock(queuedCb->spinlockid);
+ continue;
+ }
+
+ // this runs in HISR, it's purpose is : 1. If no task is accessing SIM, stop clk immediately; 2. set flag only
+ if (KAL_FALSE == queued_switch_CB->sim_MT6306_taskAccessing && KAL_FALSE == queued_switch_CB->sim_MT6306_CLKStopping)
+ {
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, stop SCLK\r\n", __func__, queuedCb->simInterface, queued_switch_CB->MT6306ChipNo);
+ sim_MT6306_clkStopper(queuedCb);
+ }
+ else
+ {
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, can't stop SCLK, (%d, %d)\r\n",
+ __func__, queuedCb->simInterface, queued_switch_CB->MT6306ChipNo,
+ queued_switch_CB->sim_MT6306_taskAccessing, (kal_uint32) queued_switch_CB->sim_MT6306_CLKStopping);
+ }
+
+ kal_take_spinlock(queuedCb->spinlockid, KAL_INFINITE_WAIT);
+ queuedCb->waitGptISR_MT6306 -= 1;
+ kal_give_spinlock(queuedCb->spinlockid);
+ }
+ }
+
+ kal_take_spinlock(spinlockid_simClkStop, KAL_INFINITE_WAIT);
+ sim_MT6306_gpt_clkStopQueue_start = KAL_FALSE;
+ if (clockStopQueue[0].queued || clockStopQueue[1].queued || clockStopQueue[2].queued || clockStopQueue[3].queued)
+ {
+ if (sim_MT6306_gpt_clkStopQueue_start == KAL_FALSE)
+ {
+ sim_MT6306_gpt_clkStopQueue_start = KAL_TRUE;
+ DRV_ICC_GPTI_StartItem(sim_MT6306_gptHandle_clkStopQueue, 10, sim_MT6306_clkStopQueueHandler, NULL);
+ MT6306_DBG("[%s]: start gpt again (clkStopQueue) (%d, %d, %d, %d)\r\n", __func__,
+ (kal_uint32) clockStopQueue[0].queued, (kal_uint32) clockStopQueue[1].queued,
+ (kal_uint32 )clockStopQueue[2].queued, (kal_uint32) clockStopQueue[3].queued);
+ }
+ }
+ kal_give_spinlock(spinlockid_simClkStop);
+}
+
+void sim_MT6306_clkStopTimeoutHandler(void *parameter)
+{
+ sim_HW_cb *hw_cb;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+ Sim_Card *SimCard;
+
+ /* For mt6306 GPIO checking */
+ spiWriterGptTimeoutFlag = KAL_TRUE;
+
+ hw_cb = (sim_HW_cb *)parameter;
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ /*This flag is used to check is cmd clock stop timer is started. If cmd clock stop timer is
+ started and stoped again, we should allow this case for d2R */
+ SimCard->clkstoping = KAL_FALSE;
+ sim_MT6306_addMsg(SIM_MT6306_CLKSTOP_TIMEOUT, hw_cb->simInterface, drv_get_current_time(), switch_CB->sim_MT6306_taskAccessing);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitGptISR_MT6306 += 1;
+ Data_Sync_Barrier();
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ /*if we deactivate usim card in command error then the timer expired, we will not do anything about clock stop*/
+ if (hw_cb->needStopGptISR
+ || sim_MT6306_stateDeactiavate == card_cb->state
+ || sim_MT6306_stateClkStopped == card_cb->state
+ || (card_cb->pins.CLK & 0x07) != sim_MT6306_CLKPass)
+ {
+ sim_MT6306_addMsg(SIM_MT6306_CLKSTOP_ABORT, card_cb->state, 0, 0);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, cancel\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitGptISR_MT6306 -= 1;
+ kal_give_spinlock(hw_cb->spinlockid);
+ return;
+ }
+
+ timeout_handler_start[hw_cb->simInterface] = ust_get_current_time();
+
+ /*this runs in HISR, it's purpose is : 1. If no task is accessing SIM, stop clk immediately; 2. set flag only*/
+ if (KAL_FALSE == switch_CB->sim_MT6306_taskAccessing && KAL_FALSE == switch_CB->sim_MT6306_CLKStopping && hw_cb->waitGptISR_MT6306 == 1)
+ {
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, stop SCLK\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo);
+ sim_MT6306_clkStopper(hw_cb);
+ }
+ else
+ {
+ kal_take_spinlock(spinlockid_simClkStop, KAL_INFINITE_WAIT);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, Enqueued\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo);
+ sim_MT6306_enClkStopQueue(hw_cb);
+ if (sim_MT6306_gpt_clkStopQueue_start == KAL_FALSE)
+ {
+ sim_MT6306_gpt_clkStopQueue_start = KAL_TRUE;
+ DRV_ICC_GPTI_StartItem(sim_MT6306_gptHandle_clkStopQueue, 10, sim_MT6306_clkStopQueueHandler, NULL);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d, start gpt (clkStopQueue)\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo);
+ }
+ kal_give_spinlock(spinlockid_simClkStop);
+ }
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitGptISR_MT6306 -= 1;
+ kal_give_spinlock(hw_cb->spinlockid);
+}
+
+/*this is the API called by SIM driver, for clock stop*/
+void sim_MT6306_clkStopTimer(sim_HW_cb *hw_cb)
+{
+
+ Sim_Card *SimCard;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ usim_dcb_struct *usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ switch_CB = switch_CB;
+ /*in case that previous gpt timer expire right after we set clkStopQueued to kal_true*/
+ sim_MT6306_clkStopTimerStop(hw_cb);
+ MT6306_DBG("[%s]: Interface:%d, Switch:%d\r\n", __func__, hw_cb->simInterface, switch_CB->MT6306ChipNo);
+ /*in the case that two SIM commands send in L1sim_cmd_all, we have to re-count timeout, thus, we must set previouse kal_true to kal_false*/
+ sim_MT6306_deClkStopQueue(hw_cb);
+ sim_MT6306_addMsg(SIM_MT6306_CLKSTOP_START, hw_cb->simInterface, drv_get_current_time(), 0);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ /*1860 clk is about 572 u-sec << 1 mili-second, no matter we use kal timer or gpt timer, 2 is enough*/
+ DRV_ICC_GPTI_StartItem(card_cb->sim_MT6306_gptHandle, 1, sim_MT6306_clkStopTimeoutHandler, (void *)hw_cb);
+ /*This flag is used to check is cmd clock stop timer is started. If cmd clock stop timer is
+ started and stoped again, we should allow this case for d2R */
+ SimCard->clkstoping = KAL_TRUE;
+ usim_dcb->stopSimClkInEndOfAction = KAL_FALSE;
+ hw_cb->needStopGptISR = KAL_FALSE;
+ kal_give_spinlock(hw_cb->spinlockid);
+}
+
+void sim_MT6306_clkStopTimerStop(sim_HW_cb *hw_cb)
+{
+ Sim_Card *SimCard;
+ sim_MT6306_cardInfo *card_cb;
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+ kal_uint32 log_size = 0;
+ sim_HW_cb *peerHWCb;
+ peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+
+
+ DRV_GET_RET_ADDR(retAddr);
+ sim_MT6306_addMsg(SIM_MT6306_CLKSTOP_STOP, hw_cb->simInterface, (kal_uint32)retAddr, 0);
+
+ card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ DRV_ICC_GPTI_StopItem(card_cb->sim_MT6306_gptHandle);
+ /*This flag is used to check is cmd clock stop timer is started. If cmd clock stop timer is
+ started and stoped again, we should allow this case for d2R */
+ SimCard->clkstoping = KAL_FALSE;
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->needStopGptISR = KAL_TRUE;
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ while (1)
+ {
+ Data_Sync_Barrier();
+ if (hw_cb->waitGptISR_MT6306 == 0 && peerHWCb->waitGptISR_MT6306 == 0) break;
+ kal_give_spinlock(hw_cb->spinlockid);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for GPT ISR:%d, peer:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, hw_cb->waitGptISR_MT6306, peerHWCb->waitGptISR_MT6306, drv_get_current_time());
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL);
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ }
+ sim_MT6306_deClkStopQueue(hw_cb);
+ kal_give_spinlock(hw_cb->spinlockid);
+
+}
+
+void sim_MT6306_controlPeerSwitchVSIM(sim_HW_cb *hw_cb, kal_uint8 regValue)
+{
+ sim_MT6306_switchInfo *peerSwitch_CB;
+
+ /*this API is only for VSIM control, so we have to make sure the register address is 3*/
+ if ((regValue & 0xf0) != 0x30)
+ SIM_DEBUG_ASSERT(0);
+
+ /*find our peer switch's switch_cb*/
+#if (SIM_MT6302_MAX_MT6302 == 2)
+ if (0 == hw_cb->simSwitchChipNo)
+ peerSwitch_CB = &switchCBMT6306[1];
+ else
+ peerSwitch_CB = &switchCBMT6306[0];
+#else
+ SIM_DEBUG_ASSERT(0);
+#endif
+
+ sim_MT6306_SPIWrite(peerSwitch_CB, regValue);
+}
+void sim_MT6306_switchInit(sim_MT6306_switchInfo *switch_CB, kal_uint32 MT6306Interface)
+{
+
+ switch_CB->sim_MT6306_arb = kal_create_sem("MT6306_LOCK", 1);
+ switch_CB->sim_MT6306_Check_arb = kal_create_sem("MT6306_Check", 1);//unused?
+ if (switch_CB_63062.sim_MT6306_arb == NULL)
+ switch_CB_63062.sim_MT6306_arb = kal_create_sem("MT6306_SEC_LOCK", 1);
+ switch_CB->sim_MT6306_servingInterface = SIM_MT6306_SERVING_INTERFACE_NONE;
+ switch_CB->MT6306ChipNo = MT6306Interface;
+ switch_CB->MT6306_LCD_pdnHandle = 0xff;
+ spiWriterFlag = KAL_FALSE;
+#if defined(__DRV_2_SIM_USING_MT6306__)
+
+#if 0 //Blue mark this when early UT, will open it and consider whether to move security check's position
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ /*Blue turn on in HW I2C development*/
+ //sim_MT63062_Init(1);
+
+ /*MT6306 related init*/
+ MT6306_i2cInit(&switch_CB->sim_MT6320_writer, MT6306Interface);
+
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST] = 0x00;//default all value 0, and addr is 0
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK] = 0x13;//CLK register is default in block low state
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT] = 0x20;//default all value 0, and addr is 2
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC] = 0x30;//default all value 0, and addr is 3
+ switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CARDSS] = 0x8C;//SIM1=card 1/2, SIM2=card 3/4
+
+ /*when use MT6318 PMIC, MT6306 may not have been reset here, write to 4 registers for safety*/
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CLK]);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_RST]);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_DAT]);
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_VCC]);
+
+ sim_MT6306_SPIWrite(switch_CB, switch_CB->sim_MT6306_regValue[SIM_MT6306_REG_CARDSS]);
+
+
+// TODO: temp remove
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef GEMINI25_EVB
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+ /*disable PH resister for FTA issue*/
+ sim_MT6306_SPIWrite(switch_CB, 0x130);
+
+
+#elif defined (DRV_2_SIM_USING_LTC4558)
+ /*LTC4558 related init*/
+ GPIO_ModeSetup(4, 0);
+ GPIO_ModeSetup(7, 0);
+ GPIO_ModeSetup(8, 0);
+ GPIO_ModeSetup(9, 0);
+ GPIO_ModeSetup(11, 0);
+ GPIO_ModeSetup(12, 0);
+ GPIO_ModeSetup(13, 0);
+ GPIO_InitIO(1, 4);
+ GPIO_InitIO(1, 7);
+ GPIO_InitIO(1, 8);
+ GPIO_InitIO(1, 9);
+ GPIO_InitIO(1, 11);
+ GPIO_InitIO(1, 12);
+ GPIO_InitIO(1, 13);
+
+ /*in first Gemini EVB, we use MT6227EVB to attach MT6225DTB, GPIO13 in MT6227EVB caonnect to MT6225 DTB GPIO28
+ * this GPIO is set to BPI_BUS9 and has a pull low strength, must set this to GPIO mode to make GPIO13 work correctly
+ */
+ GPIO_ModeSetup(28, 0);
+#else
+ IMPLEMENTING_ASSERT;
+#endif
+}
+
+void sim_MT6306_init()
+{
+ kal_uint32 maskedValue;
+ kal_uint32 i;
+ sim_MT6306_switchInfo *switch_CB;
+ sim_MT6306_cardInfo *card_cb;
+ for (i = 0; i < SIM_MT6302_MAX_MT6302; i++)
+ {
+ switch_CB = &switchCBMT6306[i];
+ switch_CB->peerSwitch = &switchCBMT6306[1-i];
+ maskedValue = SaveAndSetIRQMask();
+ if (KAL_FALSE == switch_CB->sim_MT6306_initialized)
+ {
+ switch_CB->sim_MT6306_initialized = KAL_TRUE;
+ RestoreIRQMask(maskedValue);
+
+ sim_MT6306_switchInit(switch_CB, i);
+ }
+ else
+ {
+ RestoreIRQMask(maskedValue);
+ }
+ }
+
+
+ for (i = 0; i < DRV_SIM_MAX_LOGICAL_INTERFACE; i++)
+ {
+ card_cb = &sim_MT6306_card[i];
+ if (0 == card_cb->sim_MT6306_gptHandle)
+ DRV_ICC_GPTI_GetHandle(&card_cb->sim_MT6306_gptHandle);
+ if (0 == card_cb->sim_MT6306_gptHandle)
+ SIM_DEBUG_ASSERT(0);
+ card_cb->pins.CLK = sim_MT6306_NoLDO_CLKPass;
+ card_cb->pins.RST = sim_MT6306_NoLDO_RSTPass_Low;
+ card_cb->pins.DAT = sim_MT6306_NoLDO_DATBlockedHigh;
+ card_cb->pins.VCC = sim_MT6306_VCC18VDisable;
+ }
+
+ DRV_ICC_GPTI_GetHandle(&sim_MT6306_gptHandle_clkStopQueue);
+ if (0 == sim_MT6306_gptHandle_clkStopQueue) SIM_DEBUG_ASSERT(0);
+}
+#if defined(SIM_DRV_GEMINI_WITH_MT6306)
+extern kal_uint32 hwCbArray[];
+void sim_MT6306_init_for_GEMINI()
+{
+ //dbg_print("\r\n!!!!!!!!!!!!!!! %s !!!!!!!!!!!!!!!!!!!\r\n\r\n",__func__);
+ DRV_ICC_print_str("Init Gemini_6306");
+ kal_uint32 simInterface;
+ sim_HW_cb* hw_cb;
+ sim_MT6306_switchInfo *switch_CB;
+ //kal_uint8 iccSlotNum = sizeof(iccMappingTable)/sizeof(SIM_ICC_HW_SW_MAPPING);
+ for (simInterface = 0; simInterface < 4; simInterface++)
+ {
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+ switch_CB->sim_MT6306_taskAccessing = KAL_TRUE;
+ if (simInterface == 2 || simInterface == 3)
+ sim_MT6306_blockAllSignal(hw_cb);
+ else if (simInterface == 0 || simInterface == 1)
+ {
+ sim_MT6306_passAllSignal(hw_cb);
+ sim_set_logical_to_SIMIF(sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface), hw_cb->simInterface);
+ }
+ }
+}
+#endif
+void sim_MT6306_deClkStopQueue(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ if (KAL_TRUE == clockStopQueue[hw_cb->simInterface].queued)
+ {
+ clockStopQueue[hw_cb->simInterface].queued = KAL_FALSE;
+ clockStopQueue[hw_cb->simInterface].hw_cb = NULL;
+ card_cb->sim_MT6306_clkStopQueued = KAL_FALSE;
+ }
+}
+
+void sim_MT6306_enClkStopQueue(sim_HW_cb *hw_cb)
+{
+ sim_MT6306_cardInfo *card_cb = sim_MT6306_get_MT6306CardCB(hw_cb);
+ clockStopQueue[hw_cb->simInterface].hw_cb = hw_cb;
+ clockStopQueue[hw_cb->simInterface].queued = KAL_TRUE;
+ card_cb->sim_MT6306_clkStopQueued = KAL_TRUE;
+}
+
+sim_HW_cb *retreiveQueuedCb(kal_uint32 i)
+{
+ if (KAL_TRUE == clockStopQueue[i].queued)
+ {
+ if (clockStopMap[i].isHandleCmd == KAL_TRUE)
+ return NULL;
+ else
+ {
+ clockStopQueue[i].queued = KAL_FALSE;
+ return clockStopQueue[i].hw_cb;
+ }
+ }
+
+ return NULL;
+}
+#endif //#if defined(SIM_DRV_SWITCH_MT6306)
+#endif //DRV_MULTIPLE_SIM
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
+
+#endif //DRV_SIM_OFF
+
diff --git a/mcu/driver/devdrv/usim/mt63062/src/MT63062.c b/mcu/driver/devdrv/usim/mt63062/src/MT63062.c
new file mode 100644
index 0000000..1e934a6
--- /dev/null
+++ b/mcu/driver/devdrv/usim/mt63062/src/MT63062.c
@@ -0,0 +1,674 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MT63062.C
+ *
+ * Project:
+ * --------
+ * Gemini
+ *
+ * Description:
+ * ------------
+ * this file is to be adaption layer for MT6306 security
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#include "drv_comm.h"
+#include "reg_base.h"
+//#include "gpio_sw.h"
+#include "sim_reg_adp.h"
+#include "mt6306_i2c.h"
+//#include "sim_trc.h"
+#include "mt63062.h"
+#include "stdlib.h"
+
+#define SIM_TRC_MSG 0xffff0000
+
+//#ifdef MT6306_Protection //WPLin20110309
+
+#define MT6306_SEM_PROTECT //WPLin20110314
+
+//#define DUMMY_MT63062_OBJ //WPLin 20110407 add dummy function when MT63062 not yet enabled
+
+#define MT6306_READ_CACHE_READ //WPLin 20110509
+//#define MT6306_SEC_AVERAGE //WPLin 20110505
+#ifdef MT6306_SEC_AVERAGE //WPLin 20110505
+ #define MT6306_SEC_AVERAGE_CHECK_NUM (5)
+ #define MT6306_SEC_AVERAGE_CHECK_THRESHOLD (3)
+#endif
+
+#define SIM_MT6306_REG_NUMBER (32)
+
+typedef struct
+{
+ kal_uint32 MT6306ChipNo; //for which MT6306 chip does this control block stand
+#ifdef MT6306_SEM_PROTECT //WPLin20110314
+ kal_semid sim_MT6306_arb;
+#endif
+ kal_uint8 sim_MT6306_regValue[SIM_MT6306_REG_NUMBER];
+ kal_uint8 sim_MT6306_internal_bypass_sem; //WPLin 20110407 remove usage of MT6306_Writer_GPIO_Krl()
+#ifdef MT6306_SEC_AVERAGE //WPLin 20110505
+ kal_uint8 sim_MT6306_prev_check_result[MT6306_SEC_AVERAGE_CHECK_NUM]; // [0] means oldest result
+#else
+ kal_uint8 sim_MT6306_prev_check_result; //WPLin 20110407
+#endif
+} sim_MT63062_switchCB;
+
+extern kal_uint8 MT6306_Reader_AL(kal_uint8 chipno, kal_uint16 addr);
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+extern void MT6306_Writer_AL(kal_uint8 chipno, kal_uint16 data);
+#ifdef DUMMY_MT6306_SECURITY_OBJ
+
+void sim_MT63062_Init(kal_uint32 chipNo)
+{
+}
+
+void sim_MT63062_TakeI2Csem()
+{
+
+}
+
+void sim_MT63062_GiveI2Csem()
+{
+
+}
+
+void sim_MT63062_CacheRegVal(kal_uint32 chipNo, kal_uint8 addr, kal_uint8 value)
+{
+
+}
+
+kal_uint8 sim_MT63062_Cmd(sim_HW_cb *hw_cb)
+{
+ return (KAL_TRUE);
+}
+
+#else //#define DUMMY_MT6306_SECURITY_OBJ
+
+sim_MT63062_switchCB switch_CB_63062;
+
+void sim_MT63062_Init(kal_uint32 chipNo)
+{
+ kal_uint8 i;
+
+ // this register cache shall before any I2C writing
+ for (i = 0; i < SIM_MT6306_REG_NUMBER; i ++)
+ {
+ switch_CB_63062.sim_MT6306_regValue[i] = 0xF0; // 0xF0 is impossible for 4-bits MT6306 registers
+ }
+#ifdef MT6306_SEM_PROTECT
+ // setup semaphore
+ {
+ if (switch_CB_63062.sim_MT6306_arb == NULL)
+ switch_CB_63062.sim_MT6306_arb = kal_create_sem("MT6306_SEC_LOCK", 1);
+ switch_CB_63062.sim_MT6306_internal_bypass_sem = KAL_FALSE;
+ }
+#endif
+
+
+#ifdef MT6306_SEC_AVERAGE //WPLin 20110505
+ for (i = 0; i < MT6306_SEC_AVERAGE_CHECK_NUM; i ++)
+ {
+ switch_CB_63062.sim_MT6306_prev_check_result[i] = KAL_TRUE;
+ }
+#else
+ switch_CB_63062.sim_MT6306_prev_check_result = KAL_FALSE;
+#endif
+
+ return;
+}
+
+void sim_MT63062_TakeI2Csem(void) //WPLin 20110407 separate functions from MT6306_I2C.c --> MT6306_security.c
+{
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+ DRV_GET_RET_ADDR(retAddr);
+
+ sim_addMsg(0x11042002, 0, 0, (kal_uint32)retAddr);
+
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ kal_take_sem(switch_CB_63062.sim_MT6306_arb, KAL_INFINITE_WAIT);
+ /*
+ //kal_char str_buf[255];
+
+#ifdef MT6306_SEM_PROTECT //WPLin20110314
+ if (kal_query_systemInit() != KAL_TRUE) // KAL_TRUE means init not yet finished
+ {
+ if (switch_CB_63062.sim_MT6306_internal_bypass_sem != KAL_TRUE) //WPLin 20110407 remove usage of MT6306_Writer_GPIO_Krl()
+ {
+ //semaphore protect
+ //kal_sprintf(str_buf, "[MT6306] take\n");
+ //kal_print(str_buf);
+ kal_take_sem(switch_CB_63062.sim_MT6306_arb, KAL_INFINITE_WAIT);
+ //kal_sprintf(str_buf, "[MT6306] take done\n");
+ //kal_print(str_buf);
+ }
+ }
+#endif
+ */
+}
+
+void sim_MT63062_GiveI2Csem(void) //WPLin 20110407 separate functions from MT6306_I2C.c --> MT6306_security.c
+{
+#if defined(__ARMCC_VERSION)
+ kal_uint32 retAddr;
+#else
+ void *retAddr;
+#endif
+
+ DRV_GET_RET_ADDR(retAddr);
+ sim_addMsg(0x11042003, 0, 0, (kal_uint32)retAddr);
+
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ kal_give_sem(switch_CB_63062.sim_MT6306_arb);
+ /*
+ //kal_char str_buf[255];
+
+#ifdef MT6306_SEM_PROTECT //WPLin20110314
+ if (kal_query_systemInit() != KAL_TRUE) // KAL_TRUE means init not yet finished
+ {
+ if (switch_CB_63062.sim_MT6306_internal_bypass_sem != KAL_TRUE) //WPLin 20110407 remove usage of MT6306_Writer_GPIO_Krl()
+ {
+ //semaphore protect
+ //kal_sprintf(str_buf, "[MT6306] give\n");
+ //kal_print(str_buf);
+ kal_give_sem(switch_CB_63062.sim_MT6306_arb);
+ //kal_sprintf(str_buf, "[MT6306] give done\n");
+ //kal_print(str_buf);
+ }
+ }
+#endif
+ */
+}
+
+void sim_MT63062_CacheRegVal(kal_uint32 chipNo, kal_uint8 addr, kal_uint8 value) //WPLin 20110407 separate functions from MT6306_I2C.c --> MT6306_security.c
+{
+ if (addr < SIM_MT6306_REG_NUMBER)
+ {
+ switch_CB_63062.sim_MT6306_regValue[addr] = value & 0x0F;
+ }
+}
+
+/*
+* FUNCTION
+* sim_MT63062_Read_GPIO_Cache
+*
+* DESCRIPTION
+* This function is the
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* kal_uint16
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+kal_uint8 sim_MT63062_Read_GPIO_Cache(kal_uint8 addr)
+{
+ kal_uint8 cache_reg_val;
+
+ if (addr < SIM_MT6306_REG_NUMBER)
+ {
+ cache_reg_val = switch_CB_63062.sim_MT6306_regValue[addr];
+
+ if (cache_reg_val & 0xF0)
+ {
+#ifdef MT6306_READ_CACHE_READ //WPLin 20110509
+ cache_reg_val = MT6306_Reader_AL(0, addr);
+ sim_MT63062_CacheRegVal(0, addr, cache_reg_val);
+ return (cache_reg_val);
+#else
+ return (MT6306_Reader_AL(0, addr));
+#endif
+ }
+ else
+ {
+ return (cache_reg_val);
+ }
+ }
+ else
+ {
+ return (0x00);
+ }
+}
+
+/*
+* FUNCTION
+* MT6306_ValidateCRC
+*
+* DESCRIPTION
+* This function is the
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* kal_uint8
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+kal_uint8 sim_MT6306_Active(kal_uint16 *pwHiddenRegSeed, kal_uint8 *pbRandom2, kal_uint8 bHWCRCVal) //WPLin 20110331 support separate stages
+{
+ kal_uint8 bRandom1;
+ kal_uint8 i, j, k, data_bit, bBit7, bBit2, bBit1, bCRCBit, bCRC;
+
+ for (bRandom1 = 0; bRandom1 < 16; bRandom1 ++)
+ {
+ bCRC = 0x89; // CRC initial value
+ for (i = 0; i < 16; i ++)
+ {
+ for (j = 4; j > 0; j --)
+ {
+ k = j - 1;
+ data_bit = ((pbRandom2[i] >> k) & 0x01) ^ ((bRandom1 >> k) & 0x01);
+ data_bit = data_bit ^ (((pwHiddenRegSeed[i] >> (k + 4)) & 0x01) & ((pwHiddenRegSeed[i] >> 8) & 0x01));
+ data_bit = data_bit ^ (((pwHiddenRegSeed[i] >> k) & 0x01) & (~((pwHiddenRegSeed[i] >> 8) & 0x01)));
+
+ bBit7 = (bCRC >> 7) & 0x01;
+ bBit2 = (bCRC >> 2) & 0x01;
+ bBit1 = (bCRC >> 1) & 0x01;
+ bCRCBit = bBit7 ^ bBit2 ^ bBit1;
+
+ if ((pwHiddenRegSeed[i] & (1 << 4)) == 0)
+ {
+ bCRC = ((bCRC << 1) & 0xFF) | bCRCBit;
+ }
+ else
+ {
+ bCRC = ((bCRC << 4) & 0xF0) | ((bCRC >> 4) & 0x07) | ((bCRCBit << 3) & 0x08);
+ }
+
+ if (bCRCBit == 0)
+ {
+ bCRC = bCRC ^ (data_bit << 6);
+ }
+ else
+ {
+ bCRC = bCRC ^ (data_bit << 5);
+ }
+ }
+ }
+
+ if (bCRC == bHWCRCVal)
+ {
+ return (KAL_TRUE);
+ }
+ }
+
+ return (KAL_FALSE); // not match any of 16 possible FW CRC results
+}
+
+/*
+* FUNCTION
+* sim_MT6306_GetHiddenRegSeed
+*
+* DESCRIPTION
+* This function is the
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* kal_uint16
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+kal_uint16 sim_MT63062_GetHiddenRegSeed(void)
+{
+ kal_uint16 wHiddenRegSeed = 0;
+
+ // reg_seed[8] = 1A[3]
+ //MT6306 regisetr cached in global variables
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x1A) >> 3) & 0x01) << 8);
+
+ // reg_seed[7] = 07[2]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x07) >> 2) & 0x01) << 7);
+
+ // reg_seed[6] = 01[2]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x01) >> 2) & 0x01) << 6);
+
+ // reg_seed[5] = 01[1]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x01) >> 1) & 0x01) << 5);
+
+ // reg_seed[4] = 04[0]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x04) >> 0) & 0x01) << 4);
+
+ // reg_seed[3] = 06[3]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x06) >> 3) & 0x01) << 3);
+
+ // reg_seed[2] = 03[0]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x03) >> 0) & 0x01) << 2);
+
+ // reg_seed[1] = 06[0]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x06) >> 0) & 0x01) << 1);
+
+ // reg_seed[0] = 08[3]
+ wHiddenRegSeed |= (((sim_MT63062_Read_GPIO_Cache(0x08) >> 3) & 0x01) << 0);
+
+ return wHiddenRegSeed;
+}
+
+extern kal_bool spiWriterFlag;
+/*
+* FUNCTION
+* sim_MT63062_Cmd
+*
+* DESCRIPTION
+* This function is the
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* kal_uint8
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+kal_uint8 sim_MT63062_Cmd(sim_HW_cb *hw_cb)
+{
+ kal_uint16 pwHiddenRegSeed[16];
+ kal_uint8 pbRandom2[16] = {0x5, 0xA, 0x5, 0x7, 0x2, 0xF, 0x2, 0xE, 0x8, 0x5, 0xC, 0xD, 0xD, 0x5, 0x3, 0xA};
+ kal_uint8 bHWCRCVal;
+ kal_uint8 i;
+ kal_uint32 temp_time_stamp = 0;
+ /* fix build warning */
+ temp_time_stamp = temp_time_stamp;
+
+#ifdef TEST_NG_CASE
+ kal_uint8 purpose_ng_case;
+#endif
+ //kal_char str_buf[255]; its too danger to have so huge buffer internally
+
+// if (switch_CB_63062.sim_MT6306_prev_check_result == KAL_TRUE) //WPLin 20110407
+// {
+// return (KAL_TRUE);
+// }
+
+// kal_sprintf(str_buf, "[MT6306] check point 1\n");
+// kal_print(str_buf);
+
+//************* HW value ******************//
+//[Stage 1]
+// a) Stop randon number rand_6306
+// b) generae 64bits rand_bb(random2)
+// c) Setting 64bits rand_bb to MT6306
+// d) Get MT6306 9 bits register seed from MT6306
+// e) Obtain H/W results from MT6306
+
+//************* FW value ******************//
+//[Stage 2]
+// a) Calculate 0~15 case, 64bits engine result
+// b) Obtain F/W results
+
+//************* Equal. check **************//
+//[Stage 3]
+// a) Check H/W result is equal to FW results?
+// b) Return Yes/No
+
+ // =============== [1.a] ===============
+ // Start OSCEN and RNG, delay (4~N)T, then Stop RNG to generate 'random1'
+// kal_sprintf(str_buf, "[MT6306] original reg value 0x11(OSCEN) = 0x%08X, 0x1E(RAND_STOP) = 0x%08X\n", MT6306_Read_GPIO_Cache(0x11), MT6306_Read_GPIO_Cache(0x1E));
+// kal_print(str_buf); // shall be (0,0)
+
+// MT6306_Writer_GPIO(0, ((0x11 << 4) + (0x01 | MT6306_Read_GPIO_Cache(0x11)))); // OSCEN=1
+#ifdef MT6306_SEM_PROTECT
+ sim_MT63062_TakeI2Csem();
+ spiWriterFlag = KAL_TRUE;
+#endif
+ MT6306_Writer_AL(0, ((0x11 << 4) + 0x01)); // OSCEN=1
+ MT6306_Writer_AL(0, ((0x1E << 4) + 0x00)); // RAND_STOP=0
+#ifdef MT6306_SEM_PROTECT
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+#endif
+
+ //delay at least 4T = 20us
+ //temp_time_stamp = drv_get_current_time(); //in 32KHz=30us
+ //while (drv_get_current_time() < (temp_time_stamp + 2));
+
+#ifdef MT6306_SEM_PROTECT
+ sim_MT63062_TakeI2Csem();
+ spiWriterFlag = KAL_TRUE;
+#endif
+ MT6306_Writer_AL(0, ((0x1E << 4) + 0x01)); // RAND_STOP=1
+ MT6306_Writer_AL(0, ((0x11 << 4) + 0x00)); // OSCEN=0
+// MT6306_Writer_GPIO(0, ((0x11 << 4) + (0x0E & MT6306_Read_GPIO_Cache(0x11)))); // OSCEN=0
+#ifdef MT6306_SEM_PROTECT
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+#endif
+
+
+ // =============== [1.b] ===============
+ // MT6223/6253/6252 system random numbers (64bits)
+ for (i = 0; i < 16; i ++)
+ {
+ pbRandom2[i] = (kal_uint8)(rand() & 0x0F);
+ }
+
+#ifdef TEST_NG_CASE
+ purpose_ng_case = 1;
+// purpose_ng_case = ((rand() & 0x01) == 0) ? 1 : 0;
+// purpose_ng_case = ((rand() & 0x0F) == 0) ? 1 : 0;
+
+ if (purpose_ng_case == 1)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(str_buf, "[MT6306] write wrong rand_bb purposely\n");
+ if (log_size > 0) kal_print(str_buf);
+ }
+#endif
+
+ for (i = 0; i < 16; i ++)
+ {
+#ifdef MT6306_SEM_PROTECT
+ sim_MT63062_TakeI2Csem();
+ spiWriterFlag = KAL_TRUE;
+
+ switch_CB_63062.sim_MT6306_internal_bypass_sem = KAL_TRUE;
+
+// IRQMask(hw_cb->mtk_lisrCode);
+#endif
+ // =============== [1.c] ===============
+ // Setting 64bits rand_bb to MT6306
+#ifdef TEST_NG_CASE
+ if (purpose_ng_case == 1)
+ {
+ MT6306_Writer_AL(0, ((0x1C << 4) + (~pbRandom2[i]))); // RAND_IN[3:0] : puprposely incorrect value
+ }
+ else
+#endif
+ {
+ MT6306_Writer_AL(0, ((0x1C << 4) + pbRandom2[i])); // RAND_IN[3:0]
+ }
+ // =============== [1.d] ===============
+ // Get MT6306 9 bits register seed from MT6306
+ pwHiddenRegSeed[i] = sim_MT63062_GetHiddenRegSeed();
+
+#ifdef MT6306_SEM_PROTECT
+// IRQUnmask(hw_cb->mtk_lisrCode);
+
+ switch_CB_63062.sim_MT6306_internal_bypass_sem = KAL_FALSE;
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+#endif
+ }
+ // =============== [1.e] ===============
+ // Obtain H/W results from MT6306
+#ifdef MT6306_SEM_PROTECT
+ sim_MT63062_TakeI2Csem();
+ spiWriterFlag = KAL_TRUE;
+#endif
+ bHWCRCVal = MT6306_Reader_AL(0, 0x1C); // CRC[7:4]
+ bHWCRCVal <<= 4;
+ bHWCRCVal |= (MT6306_Reader_AL(0, 0x1D) & 0x0F); // CRC[3:0]
+#ifdef MT6306_SEM_PROTECT
+ spiWriterFlag = KAL_FALSE;
+ sim_MT63062_GiveI2Csem();
+#endif
+
+// #ifdef MT6306_SEM_PROTECT
+// sim_MT63062_TakeI2Csem();
+// spiWriterFlag = KAL_TRUE;
+// #endif
+// MT6306_Writer_GPIO(0, ((0x1E << 4) + 0x00)); // RAND_STOP=0
+// #ifdef MT6306_SEM_PROTECT
+// spiWriterFlag = KAL_FALSE;
+// sim_MT63062_GiveI2Csem();
+// #endif
+
+ // =============== [2.a] ===============
+ // Calculate 0~15 case, 64bits engine result
+ // =============== [2.b] ===============
+ // Obtain F/W results
+ // =============== [3.a] ===============
+ // Check H/W result is equal to FW results?
+
+#ifdef MT6306_SEC_AVERAGE //WPLin 20110505
+ // shift previous results, [0] as oldest result
+ for (i = 0; i < (MT6306_SEC_AVERAGE_CHECK_NUM - 1); i ++)
+ {
+ switch_CB_63062.sim_MT6306_prev_check_result[i] = switch_CB_63062.sim_MT6306_prev_check_result[i + 1];
+ }
+
+ // update latest result at last element
+ switch_CB_63062.sim_MT6306_prev_check_result[MT6306_SEC_AVERAGE_CHECK_NUM - 1] = sim_MT6306_Active(pwHiddenRegSeed, pbRandom2, bHWCRCVal);
+
+ for (i = 0, temp_time_stamp = 0; i < MT6306_SEC_AVERAGE_CHECK_NUM; i ++)
+ {
+ if (switch_CB_63062.sim_MT6306_prev_check_result[i] == KAL_TRUE)
+ {
+ temp_time_stamp ++;
+ }
+ }
+
+ // only return check OK if >= threshold
+ if (temp_time_stamp >= MT6306_SEC_AVERAGE_CHECK_THRESHOLD)
+ {
+ return (KAL_TRUE);
+ }
+#else
+ if (sim_MT6306_Active(pwHiddenRegSeed, pbRandom2, bHWCRCVal) == KAL_TRUE)
+ {
+ switch_CB_63062.sim_MT6306_prev_check_result = KAL_TRUE;
+
+//kal_sprintf(str_buf, "[MT63062] CRC check OK\n");
+//kal_print(str_buf);
+
+ return (KAL_TRUE);
+ }
+
+ switch_CB_63062.sim_MT6306_prev_check_result = KAL_FALSE;
+#endif
+
+ return (KAL_FALSE);
+
+ //SIM_DEBUG_ASSERT(0);
+}
+
+#endif //#define DUMMY_MT6306_SECURITY_OBJ
+
+
diff --git a/mcu/driver/devdrv/usim/src/dcl_sim.c b/mcu/driver/devdrv/usim/src/dcl_sim.c
new file mode 100644
index 0000000..cb3d77e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/src/dcl_sim.c
@@ -0,0 +1,945 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_sim.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines DCL (Driver Common Layer) of the SIM card driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#include "drv_features.h"
+#include "drv_comm.h"
+#include "dcl.h"
+
+#include "sim_al.h"
+#include "sim_drv_HW_reg_MTK.h"
+#include "sim_drv_HW_def_MTK.h"
+#include "sim_drv_SW_struct.h"
+#include "sim_drv_SW_function.h"
+#include "sim_drv_SW_API.h"
+#include "multi_icc_custom.h"
+
+#include "intrCtrl.h"
+
+#include "cache_sw.h"
+#include "init.h"
+#include "kal_public_api.h"
+
+#ifdef DCL_SIM_INTERFACE
+
+#if !defined(DRV_SIM_OFF)
+/**************************************************************************
+following defines static global variables used in this file
+***************************************************************************/
+static kal_bool fgSIMInit = KAL_FALSE;
+static kal_semid dclSimArb = 0;
+
+kal_char sim_shared_dbgstr[256];
+
+#define SIM_RESOURCE_HEAD 0x5a5a5a5a
+#define SIM_RESOURCE_TAIL 0xa5a5a5a5
+
+#define SIM_RSC_HANDLE_UDEF 0xffffffff
+
+typedef struct
+{
+ kal_uint32 guardHead;
+ kal_bool assigned;
+ kal_uint32 thdId;
+ kal_uint32 allocatedPoint;
+ DCL_SIMDriver_t *driver;
+ DCL_SIM_HW_CB driverHandle;
+ kal_uint32 guardTail;
+} DCL_SIM_RESOURCE;
+
+static DCL_SIM_RESOURCE simResource[DCL_SIM_MAX_INTERFACE];
+
+/******************************************************************************************
+*following are extern variables from other file
+******************************************************************************************/
+extern DCL_SIMDriver_t sim_ctrlDriver_All;
+
+extern void sim_init_all_cb(void);
+
+#if 0//defined(SIM_DRV_IC_USB)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/***************************************************************************************
+followings are DCL SD API exported
+*****************************************************************************************/
+/*************************************************************************
+* FUNCTION
+* DclSD_Initialize
+*
+* DESCRIPTION
+* This function is to initialize the SD driver related resource.
+* This function should be called in system initialization before tasks are scheduling.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_OK : this should be the only return value since MSDC_initialize returns nothing.
+*
+*************************************************************************/
+DCL_STATUS DclSIM_Initialize(void)
+{
+ kal_uint32 maskedValue;
+ kal_uint32 loopIndex;
+
+ maskedValue = SaveAndSetIRQMask();
+ if (KAL_FALSE == fgSIMInit)
+ {
+ fgSIMInit = KAL_FALSE;
+ RestoreIRQMask(maskedValue);
+ kal_mem_set(simResource, 0, sizeof(DCL_SIM_RESOURCE) * DCL_SIM_MAX_INTERFACE);
+ if (dclSimArb == 0) dclSimArb = kal_create_sem("SIM_DCL", 1);
+ for (loopIndex = 0; DCL_SIM_MAX_INTERFACE > loopIndex; loopIndex++)
+ {
+ simResource[loopIndex].guardHead = SIM_RESOURCE_HEAD;
+ simResource[loopIndex].guardTail = SIM_RESOURCE_TAIL;
+ simResource[loopIndex].driverHandle = SIM_RSC_HANDLE_UDEF;
+ }
+ sim_init_all_cb();
+#ifdef MEUT_ON_FPGA
+ MT6302_test();
+#endif
+ }
+ else
+ {
+ RestoreIRQMask(maskedValue);
+ }
+
+//#include "drv_iomux.h"
+//IOMUX_set_moudle_func(2, sel_misc_bsi_0);
+
+ return STATUS_OK;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclSD_Initialize
+*
+* DESCRIPTION
+* This function is to get SD DCL handler.
+*
+* PARAMETERS
+* eDev - only valid for DCL_SD.
+* flags -following bit stand for specific meaning.
+* DCL_SD_FLAGS_CARD1: to get a handle for card 1
+* DCL_SD_FLAGS_CARD2: to get a handle for card 2
+* DCL_SD_FLAGS_SIMPLUS: to get a handle for sim plus
+* Other values are prohibited
+* RETURNS
+* DCL_HANDLE_INVALID - Open failed.
+* other value - a valid handle
+*
+*************************************************************************/
+DCL_HANDLE DclSIM_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+ kal_uint32 retAddr = 0;
+ kal_uint32 thdId;
+ kal_uint32 loopIndex;
+
+ if (dev != DCL_SIM)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(sim_shared_dbgstr, "Invalid 'dev' param in %s\n\r", __func__);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ return DCL_HANDLE_INVALID;
+ }
+
+#if defined(__RVCT__)
+ /* RVCT doesn't support inline assemlber; bypass temporarily */
+ retAddr = 0;
+#else /* __RVCT__ */
+ /* get the return address */
+ /*__asm
+ {
+ mov retAddr,lr
+ } */
+ __asm__
+ (
+ "move %0, $ra"
+ :"=r"(retAddr)
+ );
+#endif /* __RVCT__ */
+
+ thdId = (kal_uint32)kal_get_current_thread_ID();
+
+ /*
+ In SIM DCL open, we only mark control block as assigned and return handle to user.
+ We don't support one resource used by multiple applications, so the control block will be not re-assigned.
+ Every time this function is called, we just find an unused control block, mark it assigned, and return the handle.
+ */
+
+ kal_take_sem(dclSimArb, KAL_INFINITE_WAIT);
+ for (loopIndex = 0; DCL_SIM_MAX_INTERFACE > loopIndex; loopIndex++)
+ {
+ if (KAL_FALSE == simResource[loopIndex].assigned)
+ {
+ simResource[loopIndex].assigned = KAL_TRUE;
+ simResource[loopIndex].thdId = thdId;
+ simResource[loopIndex].allocatedPoint = retAddr;
+ kal_give_sem(dclSimArb);
+ return (DCL_HANDLE)(&simResource[loopIndex]);
+ }
+ }
+ kal_give_sem(dclSimArb);
+ return DCL_HANDLE_NONE;
+}
+
+DCL_STATUS DclSIM_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+DCL_STATUS DclSIM_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+
+/*************************************************************************
+* FUNCTION
+* DclSIM_Configure
+*
+* DESCRIPTION
+* This function is to configure SIM interface. This is an important funciton since we rely on this function to hook correct function table.
+*
+* PARAMETERS
+* handle - a valid handle return by DclSIM_Open()
+* configure - a ponter to SIM_CONFIG_T structure which is a member of union
+* DCL_CONFIGURE_T.
+* RETURNS
+* STATUS_OK - the configuration is done correctly.
+* STATUS_INVALID_DCL_HANDLE - It's a invalid handle.
+* STATUS_NOT_OPENED - The module has not been opened.
+* STATUS_INVALID_CONFIGURATION - the configuration is not valid.
+*
+*************************************************************************/
+DCL_STATUS DclSIM_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+ SIM_CONFIG_T *prConfg;
+ DCL_SIM_RESOURCE *resource;
+ DCL_STATUS status;
+
+ /*check the handle*/
+ if (0 == handle)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(sim_shared_dbgstr, "Invalid 'handle' param in %s\n\r", __func__);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ return STATUS_INVALID_DCL_HANDLE;
+ }
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ if (SIM_RESOURCE_HEAD != resource->guardHead || SIM_RESOURCE_TAIL != resource->guardTail)
+ SIM_DEBUG_ASSERT(0);
+
+ /*state check*/
+ if (SIM_RSC_HANDLE_UDEF != resource->driverHandle || NULL != resource->driver)
+ SIM_DEBUG_ASSERT(0);
+
+ /*configure to use sim_ctrlDriver_Single for single SIM platform*/
+ prConfg = (SIM_CONFIG_T *)configure;
+
+ switch (prConfg->apType)
+ {
+ case SIM_CONFIG_AP_TYPE_PHONE1:
+ resource->driver = (DCL_SIMDriver_t *)&sim_ctrlDriver_All;
+ /*driver handle will be the pointer to hw control block in the future, but before we finish SMD, we fix a workable uint32 here*/
+ resource->driverHandle = SIM_ICC_APPLICATION_PHONE1;
+ status = STATUS_OK;
+ break;
+ case SIM_CONFIG_AP_TYPE_PHONE2:
+ resource->driver = (DCL_SIMDriver_t *)&sim_ctrlDriver_All;
+ /*driver handle will be the pointer to hw control block in the future, but before we finish SMD, we fix a workable uint32 here*/
+ resource->driverHandle = SIM_ICC_APPLICATION_PHONE2;
+ status = STATUS_OK;
+ break;
+ case SIM_CONFIG_AP_TYPE_PHONE3:
+ resource->driver = (DCL_SIMDriver_t *)&sim_ctrlDriver_All;
+ /*driver handle will be the pointer to hw control block in the future, but before we finish SMD, we fix a workable uint32 here*/
+ resource->driverHandle = SIM_ICC_APPLICATION_PHONE3;
+ status = STATUS_OK;
+ break;
+ case SIM_CONFIG_AP_TYPE_PHONE4:
+ resource->driver = (DCL_SIMDriver_t *)&sim_ctrlDriver_All;
+ /*driver handle will be the pointer to hw control block in the future, but before we finish SMD, we fix a workable uint32 here*/
+ resource->driverHandle = SIM_ICC_APPLICATION_PHONE4;
+ status = STATUS_OK;
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ status = STATUS_INVALID_CONFIGURATION;
+ break;
+ }
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ SIM_RegHotPlugCb(prConfg->apType, prConfg->hotPlugInCb, prConfg->hotPlugOutCb);
+#endif
+ return status;
+}
+DCL_STATUS DclSIM_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ SIM_DEBUG_ASSERT(0);
+ return STATUS_UNSUPPORTED;
+}
+
+typedef DCL_STATUS(*DCL_SIM_CTRL_API)(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*dcl add new api : 6. add to new DCL control function*/
+
+DCL_STATUS DCL_SIM_CTRL_API_RST(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ DCL_SIM_STATUS status;
+ SIM_CTRL_RST_T *prRst;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prRst = &(data->rSIMRst);
+ status = resource->driver->rst(prRst->ExpectVolt, prRst->ResultVolt, prRst->warm, resource->driverHandle);
+ prRst->rstResult = status;
+#if 0//defined(SIM_DRV_IC_USB)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_CMD(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ kal_uint32 status;
+ SIM_CTRL_CMD_T *prCmd;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prCmd = &(data->rSIMCmd);
+
+ status = resource->driver->cmd(prCmd->txData, prCmd->txSize, prCmd->rxData, prCmd->rxSize, resource->driverHandle, prCmd->bypass6263);
+
+ *prCmd->statusWord = status;
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_PWOFF(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ resource->driver->pwOff(resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_GET_CARD_INFO(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_GET_CARD_INFO_T *prInfo;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prInfo = &(data->rSIMGetCardInfo);
+ resource->driver->getCardInfo(prInfo->info, resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_GET_CARD_ERROR_TYPES_INFO(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_GET_CARD_ERROR_TYPES_INFO_T *prInfo;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prInfo = &(data->rSIMGetCardErrorTypesInfo);
+ resource->driver->getCardErrorTypesInfo(prInfo->info, resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_SET_SPEED(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_SET_MAX_SPEED_T *prSetSpeed;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prSetSpeed = &(data->rSIMSetMaxSpeed);
+ resource->driver->setSpeed(prSetSpeed->speed, resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_SET_PREFER_PROTOCOL(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_SET_PREFER_PROTOCOL_T *prSetT;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prSetT = &(data->rSIMSetPreferProtocol);
+ resource->driver->setPreferT(prSetT->T, resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_SET_CLK_STOP_MODE(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_SET_CLK_STOP_MODE_T *prSetClkStop;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prSetClkStop = &(data->rSIMSetClkStopMode);
+ resource->driver->setClockStopMode(prSetClkStop->mode, resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_TOUT_TEST(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_TOUT_TEST_T *toutTest;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ toutTest = &(data->rSIMToutTest);
+ resource->driver->toutTest(toutTest->toutValue, resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_GET_CARD_SPEED(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_GET_SPEED_T *prSpeed; /*dcl add new api : 8. declare a pointer for the type*/
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prSpeed = &(data->rSIMGetSpeed); /*dcl add new api : 9. cast to the pointer of the type*/
+ *prSpeed->speed = resource->driver->getCardSpeed(resource->driverHandle); /*dcl add new api : 10. call the driver function*/
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_QUERY_9000(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ SIM_CTRL_QUERY_9000_T *prQuery9000;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prQuery9000 = &(data->rSIMQuery9000);
+ *prQuery9000->got9000 = resource->driver->query9000WhenSelect(resource->driverHandle);
+
+ return STATUS_OK;
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_SET_OWNER_TASK(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ resource->driver->setOwnerTask(resource->driverHandle);
+
+ return STATUS_OK;
+
+}
+
+DCL_STATUS DCL_SIM_CTRL_API_GET_CARD_DETECT_STATUS(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+#ifdef __SIM_GET_CARD_DETECT_STATUS_SUPPORT__
+ SIM_CTRL_GET_CARD_DETECT_STATUS_T *prInfo;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+ prInfo = &(data->rSIMGetCardDetectStatus);
+ resource->driver->getCardDetectStatus(prInfo->info, resource->driverHandle);
+
+ return STATUS_OK;
+#else
+ return STATUS_UNSUPPORTED;
+#endif
+
+}
+DCL_STATUS DCL_SIM_CTRL_API_SET_SLT_RLT(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+#ifdef IC_MODULE_TEST
+ SIM_CTRL_SET_SLT_RLT_T *pSIMSetSltRlt;
+ DCL_SIM_RESOURCE *resource;
+
+ resource = (DCL_SIM_RESOURCE *)handle;
+
+ pSIMSetSltRlt = &(data->rSIMSetSltRlt);
+ L1sim_Set_Slt_Rlt(pSIMSetSltRlt->rlt, resource->driverHandle);
+#endif
+ return STATUS_OK;
+}
+
+/*dcl add new api : 7. add to function table*/
+DCL_SIM_CTRL_API DclSIM_APITbl[] =
+{
+ DCL_SIM_CTRL_API_RST, // 0-th
+ DCL_SIM_CTRL_API_CMD,
+ DCL_SIM_CTRL_API_PWOFF,
+ DCL_SIM_CTRL_API_GET_CARD_INFO,
+ DCL_SIM_CTRL_API_GET_CARD_ERROR_TYPES_INFO,
+ DCL_SIM_CTRL_API_SET_SPEED,
+ DCL_SIM_CTRL_API_SET_PREFER_PROTOCOL, // 5-th
+ DCL_SIM_CTRL_API_SET_CLK_STOP_MODE,
+ DCL_SIM_CTRL_API_TOUT_TEST,
+ DCL_SIM_CTRL_API_GET_CARD_SPEED,
+ DCL_SIM_CTRL_API_QUERY_9000,
+ DCL_SIM_CTRL_API_SET_OWNER_TASK,
+ DCL_SIM_CTRL_API_GET_CARD_DETECT_STATUS,
+ DCL_SIM_CTRL_API_SET_SLT_RLT
+};
+
+
+DCL_STATUS DclSIM_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ DCL_STATUS status;
+ DCL_SIM_RESOURCE *resource;
+
+ /*check the handle*/
+ if (0 == handle)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(sim_shared_dbgstr, "Invalid 'handle' param in %s\n\r", __func__);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ return STATUS_INVALID_DCL_HANDLE;
+ }
+ resource = (DCL_SIM_RESOURCE *)handle;
+ if (SIM_RESOURCE_HEAD != resource->guardHead || SIM_RESOURCE_TAIL != resource->guardTail)
+ SIM_DEBUG_ASSERT(0);
+
+ /*state check*/
+ if (SIM_RSC_HANDLE_UDEF == resource->driverHandle)
+ SIM_DEBUG_ASSERT(0);
+
+ /*dispatch*/
+ if (SIM_CTRL_CMD_MAX_VALUE > cmd)
+ {
+ status = DclSIM_APITbl[cmd](handle, cmd, data);
+ }
+ else
+ {
+ SIM_DEBUG_ASSERT(0);
+ status = STATUS_INVALID_CMD;
+ }
+
+ return status;
+}
+
+DCL_STATUS DclSIM_Close(DCL_HANDLE handle)
+{
+ DCL_SIM_RESOURCE *resource;
+
+ /*check the handle*/
+ if (0 == handle)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(sim_shared_dbgstr, "Invalid 'handle' param in %s\n\r", __func__);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ return STATUS_INVALID_DCL_HANDLE;
+ }
+ resource = (DCL_SIM_RESOURCE *)handle;
+
+ kal_take_sem(dclSimArb, KAL_INFINITE_WAIT);
+ resource->assigned = KAL_FALSE;
+ resource->thdId = 0;
+ resource->allocatedPoint = 0;
+ /*Blue added*/
+ resource->driverHandle = SIM_RSC_HANDLE_UDEF;
+ resource->driver = NULL;
+ kal_give_sem(dclSimArb);
+
+ return STATUS_OK;
+}
+#else /*!defined(DRV_SIM_OFF)*/
+
+
+DCL_STATUS DclSIM_Initialize(void)
+{
+ return STATUS_FAIL;
+}
+
+DCL_HANDLE DclSIM_Open(DCL_DEV dev, DCL_FLAGS flags)
+{
+ return DCL_HANDLE_INVALID;
+}
+
+DCL_STATUS DclSIM_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIM_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIM_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
+{
+ return STATUS_UNSUPPORTED;
+}
+
+DCL_STATUS DclSIM_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
+{
+ return STATUS_FAIL;
+}
+
+DCL_STATUS DclSIM_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
+{
+ return STATUS_FAIL;
+}
+
+DCL_STATUS DclSIM_Close(DCL_HANDLE handle)
+{
+ return STATUS_FAIL;
+}
+
+#endif /*!defined(DRV_SIM_OFF) */
+
+#endif /*DCL_SIM_INTERFACE*/
diff --git a/mcu/driver/devdrv/usim/src/icc_sim_common_mtk.c b/mcu/driver/devdrv/usim/src/icc_sim_common_mtk.c
new file mode 100644
index 0000000..21a006b
--- /dev/null
+++ b/mcu/driver/devdrv/usim/src/icc_sim_common_mtk.c
@@ -0,0 +1,2794 @@
+#ifndef DRV_SIM_OFF
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+#include "drv_comm.h"
+#include "dhl_trace.h"
+#include "sim_drv_trc.h"
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+
+#include "intrCtrl.h"
+#include "sim_reg_adp.h"
+
+#include "sim_hw.h"
+#include "sim_al.h"
+#include "sim_sw_comm.h"
+#include "multi_icc_custom.h"
+#include "dcl.h"
+#include "sim_drv_trc.h"
+//#include "sim_trc.h"
+#include "devdrv_ls.h"
+
+#include "kal_trace.h"
+#if !defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+#include "dcl_pmu_common_sw.h"
+#endif
+
+#include "drvpdn.h"
+#include "drv_gdma.h"
+#include "drv_gpio.h"
+#if defined(SIM_DRV_SWITCH_MT6306)
+ #include "sim_mt6306.h"
+#endif
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ #include "eint.h"
+ extern SIM_ICC_HOT_PLUG iccHotPlugTable[];
+#endif
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM) || defined(__SIM_HOT_SWAP_SUPPORT__)
+ #include "ccci_rpc_if.h"
+#endif
+#include "sleepdrv_interface.h"
+#if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD) || defined(LPWR_SLIM)
+ #if defined(DRV_SIM_6290_SERIES)
+ extern void MD_TOPSM_SRCLK_SW_Control(kal_bool fOn);
+ #endif // #if defined(DRV_SIM_6290_SERIES)
+#endif // #if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD) || defined(LPWR_SLIM)
+
+static Sim_Card SimCard_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+static usim_dcb_struct usim_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+sim_HW_cb simHWCbArray[DRV_SIM_MAX_LOGICAL_INTERFACE];
+extern kal_uint32 hwCbArray[];
+extern sim_ctrlDriver sim_ctrlDriver_MT6302, sim_ctrlDriver_MTK, sim_ctrlDriver_Single, sim_ctrlDriver_MT6306, sim_ctrlDriver_AW6314;
+extern sim_ctrlDriver *sim_driverTable[];
+extern kal_bool sim_physicalSlotChanged;
+
+#if defined (__SIM_HOT_SWAP_SUPPORT__) && defined (__SIM_HOT_SWAP_POLL_TIMER__)
+extern volatile kal_spinlockid spinlockid_poll_timer;
+#endif
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+extern volatile kal_semid wait_sim_MT6306_RACE_PROTECT[SIM_MT6306_MAX_PROTECTION_NUM];
+extern volatile kal_spinlockid switch_spinlock;
+extern volatile kal_spinlockid spinlockid_simClkStop;
+#endif
+#if defined(__SIM_DRV_CO_LOAD_MT6306__) && defined(SIM_DRV_SWITCH_MT6306)
+ extern kal_bool sim_connectMT6306;
+#endif
+extern void SIM_SetEvent_MTK(Sim_Card *SIMCARD, kal_uint8 result, sim_HW_cb *hw_cb);
+kal_uint32 sim_mtkIf2Logical[SIM_DRV_MTK_INTERFACE_NUM];
+void DRV_ICC_CLKSRC_Lock(kal_uint32 hwInterfaceNo, kal_bool fLock);
+void sim_PDNEnable_MTK(sim_HW_cb *hw_cb);
+
+
+#ifndef __DEBUG_ASSERT_SUPPORT__
+kal_char SIM_DEBUG_ASSERT_STR[512];
+#endif
+
+ #ifdef SIM_CACHED_SUPPORT
+ kal_uint32 sim_uncachedTxBuffer0[260] DEVDRV_LS_NONCACHEDZI;
+ kal_uint32 sim_uncachedRxBuffer0[260] DEVDRV_LS_NONCACHEDZI;
+ kal_uint32 sim_uncachedTxBuffer1[260] DEVDRV_LS_NONCACHEDZI;
+ kal_uint32 sim_uncachedRxBuffer1[260] DEVDRV_LS_NONCACHEDZI;
+ #if defined(SIM_DRV_IC_USB)
+ kal_uint8 uncachedDmaBuffer0[512] DEVDRV_LS_NONCACHEDZI;
+ kal_uint8 uncachedDmaBuffer1[512] DEVDRV_LS_NONCACHEDZI;
+ #else
+ kal_uint8 uncachedDmaBuffer0[260] DEVDRV_LS_NONCACHEDZI;
+ kal_uint8 uncachedDmaBuffer1[260] DEVDRV_LS_NONCACHEDZI;
+ #endif
+ #endif
+
+
+#ifdef SIM_REMOVE_ATR_ASSERT
+#define SIM_FATAL_ERROR_REPORT_PERIOD 1000 /*uint is 10ms*/
+
+typedef struct
+{
+ sim_HW_cb *hw_cb;
+ kal_uint32 gptHandle;
+} sim_fatalErrorReport;
+
+sim_fatalErrorReport sim_fatalReportArray[DRV_SIM_MAX_LOGICAL_INTERFACE];
+#endif
+
+extern kal_uint32 sim_get_logicalNum_from_app(SIM_ICC_APPLICATION application);
+extern void sim_MT6306_init(void);
+extern void sim_AW6314_init(void);
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+extern void l1usim_init_hisr(sim_HW_cb *hw_cb);
+extern void l1sim_init_hisr(sim_HW_cb *hw_cb);
+#endif
+
+#if defined(SIM_DRV_IC_USB)
+ typedef kal_uint32(*sim_icusb_Handler)(sim_HW_cb *hw_cb);
+ kal_bool usim_icusb_ccci_channel_status = KAL_FALSE;
+#endif
+
+/*
+ functions here are those the same in single SIM, MT6302 and dual controller solutiions.
+ I put them in the same place so that we won't have multiply defined error.
+ We should not use solution option here and should do the same thing in different solutions.
+*/
+
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+void SIM_RegHotPlugCb(SIM_ICC_APPLICATION application, DCL_SIM_PLUG_IN_CALLBACK hotPlugInCb, DCL_SIM_PLUG_OUT_CALLBACK hotPlugOutCb)
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ /* register sim task hot plug call back function to customer files */
+ if (sim_physicalSlotChanged == KAL_TRUE)
+ {
+ application = 1 - application; // need to switch to get correct hwcb and SIMIF number
+ }
+ sim_reg_hot_plug_cb(application, hotPlugInCb, hotPlugOutCb);
+}
+
+#ifdef SIM_HOT_SWAP_V2
+void SIM_PlugEvent_Cb(SIM_ICC_APPLICATION app)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+ usim_dcb_struct *usim_dcb;
+
+ if (sim_physicalSlotChanged == KAL_TRUE)
+ {
+ app = 1 - app; // need to switch to get correct hwcb and SIMIF number
+ }
+ // logical SIM 1 not exactly work on physical SIM1 interface, we only know interrrupt comes from SIM1, have to find its logical
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logicalNum_from_app(app)]);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+#if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ usim_dcb->retry_3v_prefer = KAL_FALSE;
+#endif
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ usim_dcb->retry_special_mode_prefer = KAL_FALSE;
+#endif
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ if (SimCard->sim_nullByteIssueGPT != (kal_uint32) NULL)
+ {
+ // Stop gpt timer for null byte
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount = 0;
+ // must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger
+ SimCard->simMagic1++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ }
+
+ // Stop CMD timer
+#if defined(SIM_DRV_SWITCH_MT6306)
+ sim_MT6306_switchInfo *switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306 == KAL_FALSE)
+ {
+ USIM_DISABLE_TOUT();
+ }
+ else
+#endif
+ {
+ if (switch_CB->sim_MT6306_servingInterface == hw_cb->simInterface)
+ {
+ USIM_DISABLE_TOUT();
+ }
+ }
+#else
+ USIM_DISABLE_TOUT();
+#endif
+
+ SimCard->timeout = KAL_TRUE;
+ usim_dcb->present = KAL_FALSE;
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ hw_cb->canUse_4_33_SCLK = KAL_FALSE;
+#endif
+#if defined(SIM_DRV_IC_USB)
+ usim_dcb->forceISO = KAL_FALSE;
+ SimCard->forceISO = KAL_FALSE;
+ usim_icusb_ccci_channel_status = KAL_FALSE;
+ usim_dcb->isIcUsb = KAL_FALSE;
+ SimCard->isIcUsb = KAL_FALSE;
+#endif
+ hw_cb->SlowClock = KAL_FALSE;
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306 == KAL_FALSE)
+ {
+ if ((void *) SimCard->event != NULL && (void *) SimCard->gpt_handle != NULL && usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ SimCard->EvtFlag = 0xFFFF;
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ }
+ if ((void *) usim_dcb->event != NULL && (void *) usim_dcb->gpt_handle != NULL && usim_dcb->phy_proto == T1_PROTOCOL)
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ else
+#endif
+ {
+ if (switch_CB->sim_MT6306_servingInterface == hw_cb->simInterface)
+ {
+ if ((void *) SimCard->event != NULL && (void *) SimCard->gpt_handle != NULL && usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ SimCard->EvtFlag = 0xFFFF;
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ }
+ if ((void *) usim_dcb->event != NULL && (void *) usim_dcb->gpt_handle != NULL && usim_dcb->phy_proto == T1_PROTOCOL)
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ }
+#else
+ if ((void *) SimCard->event != NULL && (void *) SimCard->gpt_handle != NULL && usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ SimCard->EvtFlag = 0xFFFF;
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ }
+ if ((void *) usim_dcb->event != NULL && (void *) usim_dcb->gpt_handle != NULL && usim_dcb->phy_proto == T1_PROTOCOL)
+ USIM_SET_EVENT_Multiple(usim_dcb);
+#endif
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC64, app, SimCard->simMagic2, drv_get_current_time(), SimCard->State, SimCard->EvtFlag);
+
+ USIM_low_power_related_setting(hw_cb, USIM_LP_MASK_NORMAL_26M | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+}
+#endif
+#endif
+void SIM_EINT_Mask(sim_HW_cb *hw_cb, kal_bool enable, kal_uint32 line_num)
+{
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (enable)
+ {
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ kal_take_spinlock(hw_cb->spinlockid_sim_hot_swap, KAL_INFINITE_WAIT);
+#else
+ IRQMask(IRQ_EIT_CODE);
+#endif
+ // kal_sprintf(hw_cb->dbgStr, "sim(%d) eint mask @ %d\n\r", hw_cb->simInterface, line_num);
+ // DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else
+ {
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ kal_give_spinlock(hw_cb->spinlockid_sim_hot_swap);
+#else
+ IRQUnmask(IRQ_EIT_CODE);
+#endif
+ // kal_sprintf(hw_cb->dbgStr, "sim(%d) eint unmask @ %d\n\r", hw_cb->simInterface, line_num);
+ // DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+#endif
+ return;
+}
+
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+#include "sim_public_enum.h"
+extern void sim_hot_swap_poll_timer_set(kal_uint32 which_sim);
+void SIM_PlugEvent_Poll_Timer_Cb(SIM_ICC_APPLICATION app)
+{
+ //Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+ //usim_dcb_struct *usim_dcb;
+
+ if (sim_physicalSlotChanged == KAL_TRUE)
+ {
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logicalNum_from_app(1 - app)]);
+ }
+ else
+ {
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logicalNum_from_app(app)]);
+ }
+ // logical SIM 1 not exactly work on physical SIM1 interface, we only know interrrupt comes from SIM1, have to find its logical
+ //SimCard = GET_SIM_CB(hw_cb->simInterface);
+ //usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ //SimCard->poll_sim_2s = KAL_TRUE;
+ //usim_dcb->poll_sim_2s = KAL_TRUE;
+ hw_cb->PollTimerStart = KAL_TRUE;
+ hw_cb->PollTimerPluggedOut = KAL_FALSE;
+ hw_cb->PollTimerEnd = KAL_TRUE;
+ sim_hot_swap_poll_timer_set(app);
+ DRV_ICC_print_str("[SIM DRV]start timer\n\r");
+
+ return;
+}
+#endif
+
+void DRV_ICC_print(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5)
+{
+ kal_char *dbgStr;
+ kal_uint32 log_size = 0;
+
+ if (kal_if_hisr())
+ {
+ dbgStr = hw_cb->hisrDbgStr;
+ }
+ else
+ {
+ dbgStr = hw_cb->dbgStr;
+ }
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV:%d] %d : %x, %x, %x, %x, %x\n\r", hw_cb->simInterface, messageType, value1, value2, value3, value4, value5);
+ if (log_size > 0) dbg_print(dbgStr);
+#else
+ switch (hw_cb->simInterface)
+ {
+ case 0:
+ MD_TRC(LOG_SIM_DRV_1_X,messageType, value1, value2, value3, value4, value5);
+ break;
+ case 1:
+ MD_TRC(LOG_SIM_DRV_2_X,messageType, value1, value2, value3, value4, value5);
+ break;
+ case 2:
+ MD_TRC(LOG_SIM_DRV_3_X,messageType, value1, value2, value3, value4, value5);
+ break;
+ case 3:
+ MD_TRC(LOG_SIM_DRV_4_X,messageType, value1, value2, value3, value4, value5);
+ break;
+ default:
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV:%d] %d : %x, %x, %x, %x, %x\n\r", hw_cb->simInterface, messageType, value1, value2, value3, value4, value5);
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV,dbgStr);
+ break;
+ }
+#endif
+
+ return;
+}
+
+void DRV_ICC_print_dec(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5)
+{
+ kal_char *dbgStr;
+ kal_uint32 log_size = 0;
+
+ if (kal_if_hisr())
+ {
+ dbgStr = hw_cb->hisrDbgStr;
+ }
+ else
+ {
+ dbgStr = hw_cb->dbgStr;
+ }
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV:%d] %d : %d, %d, %d, %d, %d\n\r", hw_cb->simInterface, messageType, value1, value2, value3, value4, value5);
+ if (log_size > 0) dbg_print(dbgStr);
+#else
+ switch (hw_cb->simInterface)
+ {
+ case 0:
+ MD_TRC(LOG_SIM_DRV_1_D,messageType, value1, value2, value3, value4, value5);
+ break;
+ case 1:
+ MD_TRC(LOG_SIM_DRV_2_D,messageType, value1, value2, value3, value4, value5);
+ break;
+ case 2:
+ MD_TRC(LOG_SIM_DRV_3_D,messageType, value1, value2, value3, value4, value5);
+ break;
+ case 3:
+ MD_TRC(LOG_SIM_DRV_4_D,messageType, value1, value2, value3, value4, value5);
+ break;
+ default:
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV:%d] %d : %d, %d, %d, %d, %d\n\r", hw_cb->simInterface, messageType, value1, value2, value3, value4, value5);
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV,dbgStr);
+ break;
+ }
+#endif
+
+ return;
+}
+
+void DRV_ICC_print_str(kal_char sim_dbg_str[])
+{
+#ifdef ATEST_DRV_ENABLE
+ dbg_print(sim_dbg_str);
+#else
+ MD_TRC(LOG_SIM_DRV,sim_dbg_str);
+#endif
+}
+
+void DRV_ICC_print_err_msg(sim_HW_cb *hw_cb, kal_char sim_dbg_str[])
+{
+#ifdef ATEST_DRV_ENABLE
+ dbg_print("[SIM_DRV:%d][ERR]%s\n\r", hw_cb->simInterface, sim_dbg_str);
+#else
+ MD_TRC(LOG_SIM_DRV_ERR,hw_cb->simInterface, sim_dbg_str);
+#endif
+}
+
+void sim_dump_fifo(sim_HW_cb *hw_cb)
+{
+ Data_Sync_Barrier();
+#if !defined(ATEST_DRV_ENABLE) && !defined(__FPGA__)
+ kal_uint32 i = 0, log_size = 0;
+ kal_uint16 tmp_buf[16];
+
+ for (i = 0; i < 16; i++)
+ {
+ tmp_buf[i] = DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_DBGDATA_MTK);
+ }
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
+ tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4], tmp_buf[5], tmp_buf[6], tmp_buf[7],
+ tmp_buf[8], tmp_buf[9], tmp_buf[10], tmp_buf[11], tmp_buf[12], tmp_buf[13], tmp_buf[14], tmp_buf[15]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ return;
+}
+
+#define SIM_FIFO_RECORD_CAPACITY 5
+#define SIM_FIFO_LEN 16
+kal_uint8 sim_fifoRecord[DRV_SIM_MAX_LOGICAL_INTERFACE][SIM_FIFO_RECORD_CAPACITY][SIM_FIFO_LEN];
+kal_uint8 sim_fifoRecordIdx[DRV_SIM_MAX_LOGICAL_INTERFACE] = {0};
+void sim_storeFifo(sim_HW_cb *hw_cb)
+{
+ Data_Sync_Barrier();
+#if !defined(ATEST_DRV_ENABLE) && !defined(__FPGA__)
+ kal_uint8 interface = hw_cb->simInterface;
+ kal_uint8 idx = sim_fifoRecordIdx[interface];
+ kal_uint32 i = 0;
+
+ for (i = 0; i < SIM_FIFO_LEN; i++)
+ {
+ sim_fifoRecord[interface][idx][i] = DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_DBGDATA_MTK) & 0xFF;
+ }
+
+ sim_fifoRecordIdx[interface] = (idx + 1) % SIM_FIFO_RECORD_CAPACITY;
+#endif
+ return;
+}
+
+void sim_printFifo(sim_HW_cb *hw_cb)
+{
+ Data_Sync_Barrier();
+#if !defined(ATEST_DRV_ENABLE) && !defined(__FPGA__)
+ kal_uint8 interface = hw_cb->simInterface;
+ kal_uint8 idx = sim_fifoRecordIdx[interface];
+ kal_uint32 i = 0, log_size = 0;
+
+ for (i = 0; i < SIM_FIFO_RECORD_CAPACITY; i++)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
+ sim_fifoRecord[interface][idx][0], sim_fifoRecord[interface][idx][1], sim_fifoRecord[interface][idx][2], sim_fifoRecord[interface][idx][3],
+ sim_fifoRecord[interface][idx][4], sim_fifoRecord[interface][idx][5], sim_fifoRecord[interface][idx][6], sim_fifoRecord[interface][idx][7],
+ sim_fifoRecord[interface][idx][8], sim_fifoRecord[interface][idx][9], sim_fifoRecord[interface][idx][10], sim_fifoRecord[interface][idx][11],
+ sim_fifoRecord[interface][idx][12], sim_fifoRecord[interface][idx][13], sim_fifoRecord[interface][idx][14], sim_fifoRecord[interface][idx][15]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ idx = (idx + 1) % SIM_FIFO_RECORD_CAPACITY;
+ }
+#endif
+ return;
+}
+
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+kal_uint32 GPIO_SIM1_SIMIO = 0, GPIO_SIM1_SIMRST = 0, GPIO_SIM1_SIMCLK = 0, GPIO_SIM2_SIMIO = 0, GPIO_SIM2_SIMRST = 0, GPIO_SIM2_SIMCLK = 0;
+#endif
+void sim_dump_sim_pins(sim_HW_cb *hw_cb)
+{
+#if !defined(__FPGA__)
+#if defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+ MD_TRC(LOG_SIM_DRV_SIM_PINS,
+ GPIO_ReadIO(GPIO_SIM1_SIMIO), GPIO_ReadIO(GPIO_SIM1_SIMRST), GPIO_ReadIO(GPIO_SIM1_SIMCLK),
+ GPIO_ReadIO(GPIO_SIM2_SIMIO), GPIO_ReadIO(GPIO_SIM2_SIMRST), GPIO_ReadIO(GPIO_SIM2_SIMCLK));
+#endif
+#else
+ MD_TRC(LOG_SIM_DRV_SIM_PINS,
+ GPIO_ReadIO(GPIO_SIM1_SIMIO), GPIO_ReadIO(GPIO_SIM1_SIMRST), GPIO_ReadIO(GPIO_SIM1_SIMCLK),
+ GPIO_ReadIO(GPIO_SIM2_SIMIO), GPIO_ReadIO(GPIO_SIM2_SIMRST), GPIO_ReadIO(GPIO_SIM2_SIMCLK));
+#endif
+#endif
+ return;
+}
+
+void sim_dump_reg(kal_uint32 trc_num, sim_HW_cb *hw_cb)
+{
+ Data_Sync_Barrier();
+#if !defined(ATEST_DRV_ENABLE)
+ // USIM
+ DRV_ICC_print(hw_cb, trc_num, SIM0_BASE_ADDR_MTK, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_VERSION_MTK),
+ DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CONFSTA_MTK));
+
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),
+ DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_STS_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK));
+
+ // DRV_ICC_print(trc_num, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ DRV_ICC_print(hw_cb, trc_num, 0, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DTIME_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK));
+
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_GTIME_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ETIME_MTK),
+ DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_EXT_TIME_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CGTIME_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK));
+
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_COMDLEN_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_LEFTLEN_MTK),
+ DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_SW2_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK));
+
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_STATUS_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DBG_MTK), 0, 0, drv_get_current_time());
+
+ // HDMA
+ if (hw_cb->simInterface) // SIM2
+ {
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(REG_HDMA_HDCSR0), DRV_Reg32(REG_HDMA_HDSR),
+ DRV_Reg32(REG_HDMA_HDCPR), DRV_Reg32(REG_HDMA_HDCTRR1), DRV_Reg32(REG_HDMA_HDC0R1));
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(REG_HDMA_HDC1R1), DRV_Reg32(REG_HDMA_HPRGA0R1),
+ DRV_Reg32(REG_HDMA_HPRGA1R1), DRV_Reg32(REG_HDMA_HCCR1), DRV_Reg32(REG_HDMA_HDCPR1));
+ }
+ else // SIM1
+ {
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(REG_HDMA_HDCSR0), DRV_Reg32(REG_HDMA_HDSR),
+ DRV_Reg32(REG_HDMA_HDCPR), DRV_Reg32(REG_HDMA_HDCTRR0), DRV_Reg32(REG_HDMA_HDC0R0));
+ DRV_ICC_print(hw_cb, trc_num, DRV_Reg32(REG_HDMA_HDC1R0), DRV_Reg32(REG_HDMA_HPRGA0R0),
+ DRV_Reg32(REG_HDMA_HPRGA1R0), DRV_Reg32(REG_HDMA_HCCR0), DRV_Reg32(REG_HDMA_HDCPR0));
+ }
+
+ // GPIO MODE
+#if !defined(__FPGA__)
+ sim_dump_gpio(hw_cb);
+#endif
+ sim_dump_eint(hw_cb);
+
+ // PDN
+ // low power vsim
+ // 26MHz
+#endif // #if !defined(ATEST_DRV_ENABLE)
+ return;
+}
+void sim_dump_gpio(sim_HW_cb *hw_cb)
+{
+ kal_char *dbgStr;
+ kal_uint32 log_size = 0;
+
+ if (kal_if_hisr())
+ {
+ dbgStr = hw_cb->hisrDbgStr;
+ }
+ else
+ {
+ dbgStr = hw_cb->dbgStr;
+ }
+
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV][GPIO] : %x, %x, %x, %x, %x, %x\n\r", DRV_Reg32(REG_GPIO_MODE_0_FOR_SIM), DRV_Reg32(REG_GPIO_MODE_1_FOR_SIM),
+ DRV_Reg32(REG_GPIO_IES_0_FOR_SIM), DRV_Reg32(REG_GPIO_IES_1_FOR_SIM), DRV_Reg32(REG_GPIO_SMT_0_FOR_SIM), DRV_Reg32(REG_GPIO_SMT_1_FOR_SIM));
+ if (log_size > 0) DRV_ICC_print_str(dbgStr);
+
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV][GPIO] : %x, %x, %x, %x, %x, %x\n\r", DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM), DRV_Reg32(REG_GPIO_DRV_1_FOR_SIM),
+ DRV_Reg32(REG_GPIO_RDSEL_0_FOR_SIM), DRV_Reg32(REG_GPIO_RDSEL_1_FOR_SIM), DRV_Reg32(REG_GPIO_TDSEL_0_FOR_SIM), DRV_Reg32(REG_GPIO_TDSEL_1_FOR_SIM));
+ if (log_size > 0) DRV_ICC_print_str(dbgStr);
+
+ log_size = kal_sprintf(dbgStr, "[SIM_DRV][GPIO] : %x, %x\n\r", DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM), DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM));
+ if (log_size > 0) DRV_ICC_print_str(dbgStr);
+
+ return;
+}
+
+void sim_dump_eint(sim_HW_cb *hw_cb)
+{
+#if !defined(__FPGA__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_uint32 log_size = 0;
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+ kal_uint32 GPIO_FOR_SIM3_EINT = 0, GPIO_FOR_CODEC_EINT = 0;
+ if(hwCbArray[2] != 0)
+ {
+ if (((sim_HW_cb *) hwCbArray[2])->spinlockid != 0)
+ GPIO_FOR_SIM3_EINT = ((sim_HW_cb *) hwCbArray[2])->gpioCardDetPin;
+ }
+#if defined (__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ if(((sim_HW_cb *) hwCbArray[0])->gpioCardDetPin != 0x0) GPIO_FOR_CODEC_EINT = ((sim_HW_cb *) hwCbArray[0])->gpioCardDetPin;
+ else GPIO_FOR_CODEC_EINT = ((sim_HW_cb *) hwCbArray[1])->gpioCardDetPin;
+#endif
+ // IO: sim1, sim2, sim3, codec
+ MD_TRC(LOG_SIM_DRV_EINT,GPIO_ReadIO(((sim_HW_cb *) hwCbArray[0])->gpioCardDetPin),
+ GPIO_ReadIO(((sim_HW_cb *) hwCbArray[1])->gpioCardDetPin), GPIO_ReadIO(GPIO_FOR_SIM3_EINT), GPIO_ReadIO(GPIO_FOR_CODEC_EINT));
+ // GPIO mode: sim1, sim2, sim3, codec
+ log_size = kal_sprintf(hw_cb->dbgStr, "[EINT] : %x, %x, %x, %x\n\r", GPIO_ReturnMode(((sim_HW_cb *) hwCbArray[0])->gpioCardDetPin),
+ GPIO_ReturnMode(((sim_HW_cb *) hwCbArray[1])->gpioCardDetPin), GPIO_ReturnMode(GPIO_FOR_SIM3_EINT), GPIO_ReturnMode(GPIO_FOR_CODEC_EINT));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+#if defined(MT6763)
+#define GPIO_FOR_SIM1_EINT 47
+#define GPIO_FOR_SIM2_EINT 46
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 20
+#elif defined(MT6739)
+#define GPIO_FOR_SIM1_EINT 18
+#define GPIO_FOR_SIM2_EINT 19
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 127
+#elif defined(MT6771)
+#define GPIO_FOR_SIM1_EINT 47
+#define GPIO_FOR_SIM2_EINT 46
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 0
+#elif defined(MT6765)
+#define GPIO_FOR_SIM1_EINT 47
+#define GPIO_FOR_SIM2_EINT 46
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 0
+#elif defined(MT6297)
+#define GPIO_FOR_SIM1_EINT 16
+#define GPIO_FOR_SIM2_EINT 17
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 0
+#elif defined(MT6885)
+#define GPIO_FOR_SIM1_EINT 43
+#define GPIO_FOR_SIM2_EINT 44
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 0
+#elif defined(MT6853)
+#define GPIO_FOR_SIM1_EINT 77
+#define GPIO_FOR_SIM2_EINT 78
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 0
+#elif defined(CHIP10992)
+#define GPIO_FOR_SIM1_EINT 83
+#define GPIO_FOR_SIM2_EINT 84
+#define GPIO_FOR_SIM3_EINT 0
+#define GPIO_FOR_CODEC_EINT 0
+#endif
+ // IO: sim1, sim2, sim3, codec
+ MD_TRC(LOG_SIM_DRV_EINT,
+ GPIO_ReadIO(GPIO_FOR_SIM1_EINT), GPIO_ReadIO(GPIO_FOR_SIM2_EINT), GPIO_ReadIO(GPIO_FOR_SIM3_EINT), GPIO_ReadIO(GPIO_FOR_CODEC_EINT));
+ // GPIO mode: sim1, sim2, sim3, codec
+ log_size = kal_sprintf(hw_cb->dbgStr, "[EINT] : %x, %x, %x, %x\n\r",
+ GPIO_ReturnMode(GPIO_FOR_SIM1_EINT), GPIO_ReturnMode(GPIO_FOR_SIM2_EINT), GPIO_ReturnMode(GPIO_FOR_SIM3_EINT), GPIO_ReturnMode(GPIO_FOR_CODEC_EINT));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+#endif
+ return;
+}
+
+
+//TOUT register's unit is 16 etu
+void SIM_SetTOUT(kal_uint32 TOUT, sim_HW_cb *hw_cb)
+{
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+ if (TOUT < 0xffffff)
+ SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), ((TOUT) / 4));
+ else
+ SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffffff);
+ //Write clear
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+}
+
+
+#ifdef SIM_REMOVE_ATR_ASSERT
+void SIM_fatalErrorReporter(void *param)
+{
+ kal_uint32 log_size = 0;
+ extern kal_bool DRV_ICC_GPTI_StartItem(kal_uint32 handle, kal_uint16 tick, void (*gptimer_func)(void *), void *parameter);
+ sim_fatalErrorReport *report;
+ report = param;
+
+ log_size = kal_sprintf(report->hw_cb->hisrDbgStr, "sim fatal error on interface %d, this card is broken", report->hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(report->hw_cb->hisrDbgStr);
+ DRV_ICC_GPTI_StartItem(report->gptHandle, SIM_FATAL_ERROR_REPORT_PERIOD, SIM_fatalErrorReporter, report);
+}
+
+void SIM_StartFaltalReport(sim_HW_cb *hw_cb)
+{
+ extern kal_bool DRV_ICC_GPTI_StartItem(kal_uint32 handle, kal_uint16 tick, void (*gptimer_func)(void *), void *parameter);
+ extern void DRV_ICC_GPTI_StopItem(kal_uint32 handle);
+ sim_fatalErrorReport *report;
+ kal_uint32 gptHandle;
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->keepAtrFatal = KAL_TRUE;
+ #if defined (__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,4, __LINE__, SimCard->keepAtrFatal, SimCard->State, 0, 0, 0, 0);
+ #endif
+ /*
+ We trigger a gpt timer to alarm this error periodically. Since this SIM card is abnormal and GPT for null-byte
+ will not be used, we can use it.
+ */
+ report = &sim_fatalReportArray[hw_cb->simInterface];
+ gptHandle = SimCard->sim_nullByteIssueGPT;
+
+ DRV_ICC_GPTI_StopItem(gptHandle);
+ report->gptHandle = gptHandle;
+ report->hw_cb = hw_cb;
+ DRV_ICC_GPTI_StartItem(report->gptHandle, SIM_FATAL_ERROR_REPORT_PERIOD, SIM_fatalErrorReporter, report);
+
+ return;
+}
+#endif
+
+kal_uint32 SIM_GetCurrentTime(void)
+{
+ return drv_get_current_time();
+}
+
+kal_uint32 SIM_GetDurationTick(kal_uint32 previous_time, kal_uint32 current_time)
+{
+ return drv_get_duration_tick(previous_time, current_time);
+}
+
+void SIM_SetRXTIDE(kal_uint16 RXTIDE, sim_HW_cb *hw_cb)
+{
+ kal_uint16 TIDE;
+ Data_Sync_Barrier();
+ TIDE = SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK));
+ TIDE &= ~SIM_TIDE_RXMASK;
+ TIDE |= (RXTIDE - 1);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK), TIDE);
+}
+
+void SIM_SetTXTIDE(kal_uint16 _TXTIDE, sim_HW_cb *hw_cb)
+{
+ kal_uint16 TIDE;
+ Data_Sync_Barrier();
+ TIDE = SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK));
+ TIDE &= ~SIM_TIDE_TXMASK;
+ TIDE |= ((_TXTIDE + 1) << 8);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK), TIDE);
+}
+
+/*
+* FUNCTION
+* L1sim_Enable_Enhanced_Speed
+*
+* DESCRIPTION
+* The function must call before L1sim_Reset. Otherwise, enhance speed is disable.
+* This function can enable enhance speed mode or not.
+*
+* CALLS
+*
+* PARAMETERS
+* enable: KAL_TRUE: enable enhanced speed. KAL_FALSE: disable it.
+*
+* RETURNS
+* NULL
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void L1sim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb)
+{
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->PTS_check = enable;
+}
+
+/*
+* FUNCTION
+* L1sim_Cmd
+*
+* DESCRIPTION
+* The function is used to implement re-try command mechanism.
+*
+* CALLS
+*
+* PARAMETERS
+* txData: Pointer to the transmitted command and data.
+* txSize: The size of the transmitted command and data from AL to driver.
+* expSize: The size of expected data from SIM
+* result: Pointer to received data
+* rcvSize: Pointer to the size of data received
+* parityError: 1 (parity error) or 0(no parity error)
+*
+* RETURNS
+* status(high byte:sw1 low byte: sw2)
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+
+
+void *sim_get_sim_cb(kal_uint32 simInterface)
+{
+
+ return &SimCard_cb[simInterface];
+}
+
+
+void *sim_get_usim_cb(kal_uint32 simInterface)
+{
+ return &usim_cb[simInterface];
+}
+
+/*below is the adaptation to GPT driver*/
+kal_uint8 DRV_ICC_GPTI_GetHandle(kal_uint32 *handle)
+{
+ *handle = DclSGPT_Open(DCL_GPT_CB, 0);
+ return 0;
+}
+
+void DRV_ICC_GPTI_StopItem(kal_uint32 handle)
+{
+ DclSGPT_Control(handle, SGPT_CMD_STOP, 0);
+}
+
+kal_bool DRV_ICC_GPTI_StartItem(kal_uint32 handle, kal_uint16 tick, void (*gptimer_func)(void *), void *parameter)
+{
+ SGPT_CTRL_START_T ctrlVariable;
+ DCL_STATUS status;
+
+#if defined(__HAPS_FPGA_CLK_ADJUST__)
+ ctrlVariable.u2Tick = kal_milli_secs_to_ticks_real(tick * 10);
+#else
+ ctrlVariable.u2Tick = tick;
+#endif
+ ctrlVariable.pfCallback = gptimer_func;
+ ctrlVariable.vPara = parameter;
+ status = DclSGPT_Control(handle, SGPT_CMD_START, (DCL_CTRL_DATA_T *)&ctrlVariable);
+ if (STATUS_OK == status)
+ return KAL_TRUE;
+ else
+ return KAL_FALSE;
+}
+
+#ifdef __FPGA__
+#else
+#if !defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+/*below is the adaptation to PMU driver*/
+DCL_HANDLE simPmuHandle;
+void DRV_ICC_PMU_INIT()
+{
+ simPmuHandle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
+}
+#endif
+
+void DRV_ICC_PMU_setVolt(kal_uint32 hwInterfaceNo, usim_power_enum volt)
+{
+#if defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+ DCL_HANDLE handle;
+ SPMI_CTRL_EXT_REGISTER_WRITEL cmd;
+ sim_HW_cb *hw_cb = (sim_HW_cb *)(hwCbArray[hwInterfaceNo]);
+ kal_uint32 log_size = 0;
+ DCL_STATUS ret = STATUS_OK;
+
+ handle = DclSPMI_Open(DCL_SPMI, FLAGS_NONE);
+ cmd.type = DCL_MAIN_PMIC;
+ cmd.len = 1;
+
+ if (0 == hwInterfaceNo) {
+ cmd.addr = RG_VSIM1_ANA_CON1;
+ } else if (1 == hwInterfaceNo) {
+ cmd.addr = RG_VSIM2_ANA_CON1;
+ } else {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (volt == CLASS_C_18V) {
+ cmd.value = LDO_VSIM_1P8V;
+ log_size = kal_sprintf(hw_cb->dbgStr, "vsim%d:1.8V\n\r", hwInterfaceNo);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ } else if (volt == CLASS_B_30V) {
+ cmd.value = LDO_VSIM_3P0V;
+ log_size = kal_sprintf(hw_cb->dbgStr, "vsim%d:3.0V\n\r", hwInterfaceNo);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ } else {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ ret = DclSPMI_Control(handle, EXT_REGISTER_WRITEL, (DCL_CTRL_DATA_T *)&cmd);
+ SIM_DEBUG_ASSERT(ret==STATUS_OK);
+ DclSPMI_Close(handle);
+#else
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE_EN val;
+ sim_HW_cb *hw_cb = (sim_HW_cb *)(hwCbArray[hwInterfaceNo]);
+ kal_uint32 log_size = 0;
+
+ switch (volt)
+ {
+ case CLASS_B_30V:
+ val.voltage = PMU_VOLT_03_000000_V;
+ log_size = kal_sprintf(hw_cb->dbgStr, "vsim%d:3.0V\n\r", hwInterfaceNo);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ break;
+ case CLASS_C_18V:
+ val.voltage = PMU_VOLT_01_800000_V;
+ log_size = kal_sprintf(hw_cb->dbgStr, "vsim%d:1.8V\n\r", hwInterfaceNo);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ /*select corresponding VSIM module according to hwInterfaceNo*/
+ if (0 == hwInterfaceNo)
+ {
+ val.mod = VSIM;
+ }
+ else if (1 == hwInterfaceNo)
+ {
+ val.mod = VSIM2;
+ }
+
+ /*select corresponding cmd according to platform characteristic*/
+ DRV_ICC_PMU_INIT();
+ DclPMU_Control(simPmuHandle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *) &val);
+ DclPMU_Close(simPmuHandle);
+#endif
+}
+#endif // __FPGA__
+
+#if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+
+ kal_uint8 handleNumSrclkSwCtrl = 0;
+
+kal_bool simSrcClkLockSts[4] = {KAL_FALSE, KAL_FALSE, KAL_FALSE, KAL_FALSE};
+void DRV_ICC_CLKSRC_Lock(kal_uint32 hwInterfaceNo, kal_bool fLock)
+{
+ kal_bool fShouldLock;
+
+ simSrcClkLockSts[hwInterfaceNo] = fLock;
+ fShouldLock = simSrcClkLockSts[0] + simSrcClkLockSts[1] + simSrcClkLockSts[2] + simSrcClkLockSts[3];
+
+
+ if (fShouldLock)
+ MD_TOPSM_SRCLK_SW_Control( SRCLK_FORCEON_USER_SIM, KAL_TRUE);
+ else
+ MD_TOPSM_SRCLK_SW_Control( SRCLK_FORCEON_USER_SIM, KAL_FALSE);
+
+ #if 0
+ #if !defined(DRV_SIM_6290_SERIES) && defined(DRV_SIM_LTE_SERIES)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(DRV_SIM_6290_SERIES)
+/* under construction !*/
+#elif !defined(DRV_SIM_6290_SERIES) && defined(DRV_SIM_LTE_SERIES)
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(DRV_SIM_6290_SERIES)
+/* under construction !*/
+#elif !defined(DRV_SIM_6290_SERIES) && defined(DRV_SIM_LTE_SERIES)
+/* under construction !*/
+#endif
+/* under construction !*/
+ #endif
+}
+#endif // defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+
+#if !defined(__FPGA__)
+void DRV_ICC_PMU_switch(kal_uint32 hwInterfaceNo, kal_bool enable)
+{
+#if defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+ DCL_HANDLE handle;
+ SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD cmd;
+ sim_HW_cb *hw_cb = (sim_HW_cb *)(hwCbArray[hwInterfaceNo]);
+ kal_uint32 log_size = 0;
+ DCL_STATUS ret = STATUS_OK;
+
+ handle = DclSPMI_Open(DCL_SPMI, FLAGS_NONE);
+ cmd.type = DCL_MAIN_PMIC;
+ cmd.len = 1;
+ cmd.value = enable?1:0;
+
+ if (0 == hwInterfaceNo) {
+ cmd.addr = RG_LDO_VSIM1_CON0;
+ cmd.mask = RG_LDO_VSIM1_EN_MASK;
+ cmd.shift = RG_LDO_VSIM1_EN_SHIFT;
+ } else if (1 == hwInterfaceNo) {
+ cmd.addr = RG_LDO_VSIM2_CON0;
+ cmd.mask = RG_LDO_VSIM2_EN_MASK;
+ cmd.shift = RG_LDO_VSIM2_EN_SHIFT;
+ } else {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (enable) {
+ sim_custom_setting_before_turning_on_vsim(hwInterfaceNo);
+ log_size = kal_sprintf(hw_cb->dbgStr, "turn on vsim%d\n\r", hwInterfaceNo);
+ } else {
+ log_size = kal_sprintf(hw_cb->dbgStr, "turn off vsim%d\n\r", hwInterfaceNo);
+ }
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+
+ ret = DclSPMI_Control(handle, EXT_REGISTER_WRITEL_FIELD, (DCL_CTRL_DATA_T *)&cmd);
+ SIM_DEBUG_ASSERT(ret==STATUS_OK);
+ DclSPMI_Close(handle);
+
+ if (!enable) {
+ //kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL); // ansel: useless
+ sim_custom_setting_after_turning_off_vsim(hwInterfaceNo);
+ }
+#else
+ PMU_CTRL_LDO_BUCK_SET_EN val;
+ val.enable = enable;
+ sim_HW_cb *hw_cb = (sim_HW_cb *)(hwCbArray[hwInterfaceNo]);
+ kal_uint32 log_size = 0;
+
+ /*select corresponding VSIM module according to hwInterfaceNo*/
+ if (0 == hwInterfaceNo)
+ {
+ val.mod = VSIM;
+ }
+ else if (1 == hwInterfaceNo)
+ {
+ val.mod = VSIM2;
+ }
+
+ if (enable)
+ {
+ sim_custom_setting_before_turning_on_vsim(hwInterfaceNo);
+ log_size = kal_sprintf(hw_cb->dbgStr, "turn on vsim%d\n\r", hwInterfaceNo);
+ }
+ else
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "turn off vsim%d\n\r", hwInterfaceNo);
+ }
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ /*select corresponding cmd according to platform characteristic*/
+
+ DRV_ICC_PMU_INIT();
+ DclPMU_Control(simPmuHandle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
+ DclPMU_Close(simPmuHandle);
+
+
+ if (!enable)
+ {
+ //kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL); // ansel: useless
+ sim_custom_setting_after_turning_off_vsim(hwInterfaceNo);
+ }
+#endif
+}
+#endif /*__FPGA__*/
+
+
+
+void DRV_ICC_PMU_Set_SW_LpMode(kal_uint32 hwInterfaceNo, kal_bool mode)
+{
+#if defined(__DRV_SIM_LP_MODE__)
+#if defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+ DCL_HANDLE handle;
+ SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD cmd;
+ DCL_STATUS ret = STATUS_OK;
+
+ handle = DclSPMI_Open(DCL_SPMI, FLAGS_NONE);
+ cmd.type = DCL_MAIN_PMIC;
+ cmd.len = 1;
+ cmd.value = mode?1:0;
+
+ if (0 == hwInterfaceNo) {
+ cmd.addr = RG_LDO_VSIM1_CON0;
+ cmd.mask = RG_LDO_VSIM1_LP_MASK;
+ cmd.shift = RG_LDO_VSIM1_LP_SHIFT;
+ } else if (1 == hwInterfaceNo) {
+ cmd.addr = RG_LDO_VSIM2_CON0;
+ cmd.mask = RG_LDO_VSIM2_LP_MASK;
+ cmd.shift = RG_LDO_VSIM2_LP_SHIFT;
+ } else {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ ret = DclSPMI_Control(handle, EXT_REGISTER_WRITEL_FIELD, (DCL_CTRL_DATA_T *)&cmd);
+ SIM_DEBUG_ASSERT(ret == STATUS_OK);
+ DclSPMI_Close(handle);
+#else
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET val;
+
+ // select corresponding VSIM module according to hwInterfaceNo
+ if (0 == hwInterfaceNo)
+ {
+ val.mod = VSIM;
+ }
+ else if (1 == hwInterfaceNo)
+ {
+ val.mod = VSIM2;
+ }
+
+ val.enable = mode;
+
+ // select corresponding cmd according to platform characteristic
+ DRV_ICC_PMU_INIT();
+ DclPMU_Control(simPmuHandle, LDO_BUCK_SET_LP_MODE_SET, (DCL_CTRL_DATA_T *) &val);
+ DclPMU_Close(simPmuHandle);
+#endif
+#endif
+ return;
+}
+
+#if defined(__DRV_SIM_LP_MODE__)
+void DRV_ICC_SetLp(kal_uint32 hwInterfaceNo, kal_bool isOn)
+{
+ //sim_HW_cb *hw_cb = (sim_HW_cb *)(hwCbArray[hwInterfaceNo]);
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+ return;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+ //kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] %s, %d\n\r", hwInterfaceNo, __FUNCTION__, isOn);
+ if (isOn == KAL_TRUE)
+ {
+ DRV_ICC_PMU_Set_SW_LpMode(hwInterfaceNo, 1);
+ }
+ else
+ {
+ DRV_ICC_PMU_Set_SW_LpMode(hwInterfaceNo, 0);
+ }
+
+ //DRV_ICC_print_str(hw_cb->dbgStr);
+ return;
+}
+#endif // #ifdef __DRV_SIM_LP_MODE__
+
+kal_uint8 DRV_ICC_makeCLA(kal_uint8 CLAHighBits, kal_uint8 CLAFromApdu)
+{
+ /*
+ CLA has different combinations on different spec version, especiaaly from release 7.
+ We should compose different CLA according to the CLA from SIM task APDU.
+ We plan to implement as following, but currently we only implement the part before R7, and assert the case after R7.
+
+ If(b7 == 0) //before release 7
+ {
+ //CLA of GET RESPONSE could be 0x0X
+
+ Copy b4~b1 of previous command
+ Bitwise OR with 0x0X to get CLA of GET RESPONSE
+
+ }
+ Else if(b7 ==1) //release 7 or later
+ {
+ //CLA of GET RESPONSE could be 0x4X, 0x6X
+
+ Copy b6, b4~b1 of previous command
+ Bitwise OR with 0x4X to get CLA of GET RESPONSE
+
+ }
+ Else //should not happen in current release
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ */
+ if (0 == (CLAFromApdu & 0x40)) //before release 7
+ {
+ return ((CLAHighBits & 0xf0) | (CLAFromApdu & 0x03)); // for CMCC NFC
+ }
+ else if (0x40 == (CLAFromApdu & 0x40)) // For Extended AT Command
+ {
+ return ((CLAHighBits & 0xf0) | (CLAFromApdu & 0x4f));
+ }
+ /*
+ else if (1 == (CLAFromApdu & 0x40)) //release 7 or later
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ */
+ else
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ return 0;
+}
+
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+void DRV_ICC_Interface_init_HISR(SIM_ICC_APPLICATION application)
+{
+ sim_HW_cb *hw_cb;
+ kal_uint32 simInterface = sim_get_logicalNum_from_app(application);
+ hw_cb = &simHWCbArray[simInterface];
+
+ l1usim_init_hisr(hw_cb);
+ l1sim_init_hisr(hw_cb);
+}
+#endif
+
+void DRV_ICC_interface_init(SIM_ICC_APPLICATION application)
+{
+ sim_HW_cb *hw_cb;
+ kal_uint32 simInterface;
+#if defined(SIM_DRV_SWITCH_MT6306) || defined(SIM_DRV_SWITCH_MT6302)
+ kal_uint32 peerInterface;
+#endif
+ kal_uint32 MT6302Info;
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ hw_cb = &simHWCbArray[simInterface];
+ hwCbArray[simInterface] = (kal_uint32)hw_cb;
+
+ hw_cb->PollTimerStart = KAL_FALSE;
+ hw_cb->PollTimerPluggedOut = KAL_FALSE;
+ hw_cb->PollTimerEnd = KAL_TRUE;
+ hw_cb->sim_task_group = CORE1;
+
+ if (MTK_SIMIF0 == sim_get_hwCtrl_from_logicalNum(simInterface))
+ {
+ hw_cb->mtk_baseAddr = SIM_base;
+
+
+
+ hw_cb->mtk_lisrCode = IRQ_USIM0_CODE;
+ }
+ else if (MTK_SIMIF1 == sim_get_hwCtrl_from_logicalNum(simInterface))
+ {
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ hw_cb->mtk_baseAddr = SIM2_base;
+ hw_cb->mtk_lisrCode = IRQ_USIM1_CODE;
+#else
+ /*for the platform that has single SIM controller, we shouldn't uses MTK_SIMIF1*/
+ SIM_DEBUG_ASSERT(0);
+#endif /*(2 == SIM_DRV_MTK_INTERFACE_NUM)*/
+
+ }
+ hw_cb->simInterface = simInterface;
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ hw_cb->canUse_4_33_SCLK = KAL_FALSE;
+#endif
+#if defined(LPWR_SLIM)
+ hw_cb->smHandler = SLEEP_CTL_USIM0 + hw_cb->simInterface;
+#endif // #if defined(LPWR_SLIM)
+
+#if (defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)) && defined(SIM_DRV_SWITCH_MT6306)
+ if (wait_sim_MT6306_RACE_PROTECT[0] == 0)
+ {
+ wait_sim_MT6306_RACE_PROTECT[0]= kal_create_sem("mt6306_rp_0",1);
+ wait_sim_MT6306_RACE_PROTECT[1]= kal_create_sem("mt6306_rp_1",1);
+ wait_sim_MT6306_RACE_PROTECT[2]= kal_create_sem("mt6306_rp_2",1);
+ wait_sim_MT6306_RACE_PROTECT[3]= kal_create_sem("mt6306_rp_3",1);
+ wait_sim_MT6306_RACE_PROTECT[4]= kal_create_sem("mt6306_rp_4",1);
+ wait_sim_MT6306_RACE_PROTECT[5]= kal_create_sem("mt6306_rp_5",1);
+ wait_sim_MT6306_RACE_PROTECT[6]= kal_create_sem("mt6306_rp_6",1);
+ wait_sim_MT6306_RACE_PROTECT[7]= kal_create_sem("mt6306_rp_7",1);
+ if (switch_spinlock==0)
+ switch_spinlock=kal_create_spinlock("MT6306_spinlock");
+ }
+ spinlockid_simClkStop = kal_create_spinlock("simClkSqtopQueue");
+#endif
+
+
+ MT6302Info = sim_get_MT6302_from_logicalNum(simInterface);
+ if (SIM_ICC_MT6302_NONE == MT6302Info)
+ {
+ sim_driverTable[simInterface] = &sim_ctrlDriver_MTK;
+ hw_cb->MT6302ChipNo = SIM_MT6302_INFO_UDF;
+ hw_cb->MT6302PortNo = SIM_MT6302_INFO_UDF;
+ hw_cb->MT6302PeerInterfaceCb = 0x0;
+ /*
+ this driver need to know which logical interface he is service to, so we have to create a shortcut from hw to logical interface.
+ Since this information will be used in HISR and if we don't create the shortchut, we will take lots time search custom table.
+ */
+ sim_mtkIf2Logical[sim_get_hwCtrl_from_logicalNum(simInterface)] = simInterface;
+ }
+ else if ((MT6302Info >> 16) > KAL_TRUE)
+ {
+ /* Judge if support 6306 or 6314 */
+ switch ((MT6302Info >> 16) & 0x000000ff)
+ {
+ case SIM_SWITCH_6306:
+#if defined(SIM_DRV_SWITCH_MT6306)
+ sim_driverTable[simInterface] = &sim_ctrlDriver_MT6306;
+ hw_cb->simSwitchChipNo = ((MT6302Info >> 8) & 0x000000ff);
+ hw_cb->simSwitchPortNo = (MT6302Info & 0x000000ff);
+ peerInterface = sim_get_MT6302PeerInterface(hw_cb->simSwitchChipNo, 1 - hw_cb->simSwitchPortNo);
+ hw_cb->simSwitchPeerInterfaceCb = &simHWCbArray[peerInterface];
+ sim_MT6306_init();
+#endif
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+#ifdef SIM_DRV_SWITCH_MT6302
+ sim_driverTable[simInterface] = &sim_ctrlDriver_MT6302;
+ hw_cb->MT6302ChipNo = ((MT6302Info >> 8) & 0x000000ff);
+ hw_cb->MT6302PortNo = (MT6302Info & 0x000000ff);
+ peerInterface = sim_get_MT6302PeerInterface(MT6302Info >> 8, 1 - (MT6302Info & 0x000000ff));
+ hw_cb->MT6302PeerInterfaceCb = &simHWCbArray[peerInterface];
+
+ sim_MT6302_init();
+#endif
+ }
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ DRV_ICC_Interface_init_HISR(application);
+#endif
+ if (hw_cb->spinlockid == 0)
+ {
+ if (application == SIM_ICC_APPLICATION_PHONE1)
+ {
+ hw_cb->spinlockid = kal_create_spinlock("usim1_spin");
+ }
+ else if (application == SIM_ICC_APPLICATION_PHONE2)
+ {
+ hw_cb->spinlockid = kal_create_spinlock("usim2_spin");
+ }
+ else if (application == SIM_ICC_APPLICATION_PHONE3)
+ {
+ hw_cb->spinlockid = kal_create_spinlock("usim3_spin");
+ }
+ else if (application == SIM_ICC_APPLICATION_PHONE4)
+ {
+ hw_cb->spinlockid = kal_create_spinlock("usim4_spin");
+ }
+ else SIM_DEBUG_ASSERT(0);
+ }
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (hw_cb->spinlockid_sim_hot_swap == 0)
+ {
+ if (application == SIM_ICC_APPLICATION_PHONE1)
+ {
+ hw_cb->spinlockid_sim_hot_swap = kal_create_spinlock("slot1_spin");
+ }
+ else if (application == SIM_ICC_APPLICATION_PHONE2)
+ {
+ hw_cb->spinlockid_sim_hot_swap = kal_create_spinlock("slot2_spin");
+ }
+ else if (application == SIM_ICC_APPLICATION_PHONE3)
+ {
+ hw_cb->spinlockid_sim_hot_swap = kal_create_spinlock("slot3_spin");
+ }
+ else if (application == SIM_ICC_APPLICATION_PHONE4)
+ {
+ hw_cb->spinlockid_sim_hot_swap = kal_create_spinlock("slot4_spin");
+ }
+ else SIM_DEBUG_ASSERT(0);
+ }
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__)
+ if (spinlockid_poll_timer == 0)
+ {
+ spinlockid_poll_timer = kal_create_spinlock("sim_poll_timer");
+ }
+#endif
+#endif
+
+
+#if defined(MT6739)
+ // clear R0, Set R1
+ DRV_WriteReg32(REG_GPIO_R0_CFG0_CLR_FOR_SIM, 0x3F00);
+ DRV_WriteReg32(REG_GPIO_R1_CFG0_SET_FOR_SIM, 0x3F00);
+#elif defined(MT6765)
+ /* Use default value: Pull UP 5Kohm for SIO */
+#elif defined(MT3967)
+ // SIM1 R0/R1:0/1
+ DRV_WriteReg32(REG_GPIO_R0_CFG0_CLR_0_FOR_SIM, 0x7);
+ DRV_WriteReg32(REG_GPIO_R1_CFG0_SET_0_FOR_SIM, 0x7);
+ // SIM2 R0/R1:0/1
+ DRV_WriteReg32(REG_GPIO_R0_CFG0_CLR_1_FOR_SIM, 0x1C0);
+ DRV_WriteReg32(REG_GPIO_R1_CFG0_SET_1_FOR_SIM, 0x1C0);
+ // SIM1 SR: 10
+ DRV_WriteReg32(REG_GPIO_SR_CFG0_SET_0_FOR_SIM, 0x2A);
+ // SIM2 SR: 10
+ DRV_WriteReg32(REG_GPIO_SR_CFG0_SET_1_FOR_SIM, 0xA80);
+#elif defined(MT6779) || defined(MT6785) || defined(MT6873) || defined(MT6853)
+ // SIM1/2 SR: 10
+ DRV_WriteReg32(REG_GPIO_SR_CFG_0_FOR_SIM + 8, 0x15540);
+ DRV_WriteReg32(REG_GPIO_SR_CFG_0_FOR_SIM + 4, 0x2AA80);
+ // SIM1/2 R0/R1:0/1
+ DRV_WriteReg32(REG_GPIO_R0_CFG_0_CLR_FOR_SIM, 0xFC0);
+ DRV_WriteReg32(REG_GPIO_R1_CFG_0_SET_FOR_SIM, 0xFC0);
+#elif defined(MT6297) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ DRV_WriteReg32(0xD0005324, 0x11); //GPIO 16/17 to mode 1
+ DRV_WriteReg32(0XD1D20064, 0x60000); //Enable PU
+ DRV_WriteReg32(0XD1D20058, 0x60000); //Disable PD
+#elif defined(MT6885)
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM+8, 0x12); //Pull up SIO
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM+4, 0x2D); //Pull down RST/CLK
+
+ DRV_WriteReg32(REG_GPIO_R0_CFG0_CLR_0_FOR_SIM, 0x12); //R0=0
+ DRV_WriteReg32(REG_GPIO_R1_CFG0_SET_0_FOR_SIM, 0x12); //R1=1
+#elif defined(CHIP10992)
+ // SR: 2b'10
+ DRV_WriteReg32(REG_GPIO_SR_CFG_0_FOR_SIM, 0xAAA);
+
+ // SIO:PU, RST/CLK: PD
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM+8, 0x12); //Pull up SIO
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM+4, 0x2D); //Pull down RST/CLK
+
+ // R0/R1:0/1
+ DRV_WriteReg32(REG_GPIO_R0_CFG0_CLR_0_FOR_SIM, 0x12); //R0=0
+ DRV_WriteReg32(REG_GPIO_R1_CFG0_SET_0_FOR_SIM, 0x12); //R1=1
+#elif defined(MT6833)
+ // SIM1/2 SR: 10
+ DRV_WriteReg32(REG_GPIO_SR_CFG_0_FOR_SIM + 8, 0x0555);
+ DRV_WriteReg32(REG_GPIO_SR_CFG_0_FOR_SIM + 4, 0x0AAA);
+ // SIM1/2 R0/R1:0/1
+ DRV_WriteReg32(REG_GPIO_R0_CFG_0_CLR_FOR_SIM, 0x3F);
+ DRV_WriteReg32(REG_GPIO_R1_CFG_0_SET_FOR_SIM, 0x3F);
+#endif
+
+#if defined(DRV_SIM_6297_SERIES) || defined(DRV_SIM_6298_SERIES)
+ SIM_ClearBits32(REG_GDMA_GPMTR5, ((simInterface == 0) ? 0x00FF : 0xFF00)); //set HDMA0/1 channel priority to high
+#endif
+
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__) && defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+ kal_uint8 *query= (kal_uint8 *) "GPIO_SIM1_HOT_PLUG";
+ switch (simInterface)
+ {
+ case 0:
+ query = (kal_uint8 *) "GPIO_SIM1_HOT_PLUG";
+ break;
+ case 1:
+ query = (kal_uint8 *) "GPIO_SIM2_HOT_PLUG";
+ break;
+ case 2:
+ query = (kal_uint8 *) "GPIO_SIM3_HOT_PLUG";
+ break;
+ case 3:
+ query = (kal_uint8 *) "GPIO_SIM4_HOT_PLUG";
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+ if (IPC_RPC_GPIO_GetPin(query, 19, (void *)&hw_cb->gpioCardDetPin) < 0)
+ {
+ hw_cb->gpioCardDetPin = 0;
+ }
+#endif
+ Data_Sync_Barrier();
+ sim_PDNEnable_MTK(hw_cb);
+}
+
+kal_uint32 sim_get_logical_from_SIMIF(kal_uint32 HWIf)
+{
+ return sim_mtkIf2Logical[HWIf];
+}
+
+void sim_set_logical_to_SIMIF(kal_uint32 HWIf, kal_uint32 logical)
+{
+ if (SIM_DRV_MTK_INTERFACE_NUM <= HWIf)
+ SIM_DEBUG_ASSERT(0);
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= logical)
+ SIM_DEBUG_ASSERT(0);
+
+ sim_mtkIf2Logical[HWIf] = logical;
+}
+
+sim_HW_cb *sim_get_hwCb(kal_uint32 simInterface)
+{
+ return &simHWCbArray[simInterface];
+}
+
+void sim_init_hwCb()
+{
+ kal_uint32 loopIndex;
+ for (loopIndex = 0; DRV_SIM_MAX_LOGICAL_INTERFACE > loopIndex; loopIndex++)
+ {
+ simHWCbArray[loopIndex].head = SIM_HW_CB_HEAD;
+ simHWCbArray[loopIndex].tail = SIM_HW_CB_TAIL;
+ }
+}
+
+#ifdef IC_MODULE_TEST
+typedef enum
+{
+ SIM_SLT_UNTEST,
+ SIM_SLT_FAIL,
+ SIM_SLT_PASS,
+} sim_slt_rlt_enum;
+sim_slt_rlt_enum sltRlt[DRV_SIM_MAX_LOGICAL_INTERFACE] = {SIM_SLT_UNTEST, SIM_SLT_UNTEST,
+ SIM_SLT_UNTEST, SIM_SLT_UNTEST
+ };
+kal_bool isSimSltFailSet[DRV_SIM_MAX_LOGICAL_INTERFACE] = {KAL_FALSE, KAL_FALSE,
+ KAL_FALSE, KAL_FALSE
+ };
+extern void module_test_print(char *fmt, ...);
+void L1sim_Set_Slt_Rlt(kal_bool rlt, SIM_ICC_APPLICATION application)
+{
+ kal_uint32 simInterface;
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ /* If any time slt test result is fail, keep fail result */
+ if (isSimSltFailSet[simInterface] == KAL_TRUE)
+ return;
+
+ if (rlt == KAL_FALSE)
+ {
+ sltRlt[simInterface] = SIM_SLT_FAIL;
+ isSimSltFailSet[simInterface] = KAL_TRUE;
+// module_test_print("\r\n");
+// module_test_print("MT6256 SLT Test 8 FALSE\r\n");
+
+ }
+ else
+ {
+ sltRlt[simInterface] = SIM_SLT_PASS;
+// module_test_print("\r\n");
+// module_test_print("MT6256 SLT Test 8 TRUE\r\n");
+
+ }
+}
+
+kal_bool SIM_ModuleTest_Report(void)
+{
+ kal_uint8 i;
+ kal_bool rlt = KAL_TRUE;
+
+ for (i = 0; i < sim_get_ToalInterfaceCount(); i++)
+ {
+ /* If any interface slt result is fail, just return fail */
+ if (sltRlt[i] != SIM_SLT_PASS)
+ {
+ rlt = KAL_FALSE;
+ break;
+ }
+ }
+ return rlt;
+}
+#endif
+
+/*
+* FUNCTION
+* DRV_ICC_Calc_WWT
+*
+* DESCRIPTION
+* The function is used to calc WWT.
+*
+* CALLS
+*
+* PARAMETERS
+* Fi: value of the clock rate conversion integer
+* Di: value of baud rate adjustment integer
+* Wi: waiting time integer
+* *WWT: work waiting time
+*
+* RETURNS
+* void
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void DRV_ICC_Calc_WWT(kal_uint16 Fi, kal_uint8 Di, kal_uint8 Wi, kal_uint32 *WWT)
+{
+ switch (Fi)
+ {
+ case 372:
+ /* 400*Wi to cover some slow card, margin: 3% */
+ *WWT = (960 * Wi + 400 * Wi) * Di;
+ break;
+ default:
+ /* 40*Wi to cover some slow card, margin: 4% */
+ *WWT = (960 * Wi + 40 * Wi) * Di;
+ break;
+ }
+}
+
+#if defined(SIM_DRV_IC_USB)
+/*
+* FUNCTION
+* DRV_ICC_GetBytes
+*
+* DESCRIPTION
+* The function is used to get bytes from AP by CCCI.
+*
+* CALLS
+*
+* PARAMETERS
+* Fi: value of the clock rate conversion integer
+* Di: value of baud rate adjustment integer
+* Wi: waiting time integer
+* *WWT: work waiting time
+*
+* RETURNS
+* void
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+kal_uint16 DRV_ICC_GetBytes(kal_uint8 *buffer, kal_uint16 length, sim_HW_cb *hw_cb)
+{
+#if defined(__SMART_PHONE_MODEM__)
+ kal_uint16 readLen = 0;
+ kal_uint8 status;
+ UART_CTRL_GET_BYTES_T data;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (hw_cb->simInterface != 0)
+ SIM_DEBUG_ASSERT(0);
+ data.u4OwenrId = MOD_SIM;
+ data.u2Length = length;
+ data.puBuffaddr = buffer;
+ data.pustatus = &status;
+ DclSerialPort_Control(usim_dcb->uart_sim_ccci_handle, SIO_CMD_GET_BYTES, (DCL_CTRL_DATA_T*)&data);
+ readLen = data.u2RetSize;
+
+ return readLen;
+#else
+ return 0;
+#endif /* __SMART_PHONE_MODEM__ */
+}
+
+/*
+* FUNCTION
+* DRV_ICC_PutBytes
+*
+* DESCRIPTION
+* The function is used to get bytes from AP by CCCI.
+*
+* CALLS
+*
+* PARAMETERS
+* Fi: value of the clock rate conversion integer
+* Di: value of baud rate adjustment integer
+* Wi: waiting time integer
+* *WWT: work waiting time
+*
+* RETURNS
+* void
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+kal_uint16 SIM_icusb_PutBytes(kal_uint8 *buffer, kal_uint16 length, sim_HW_cb *hw_cb)
+{
+#if defined(__SMART_PHONE_MODEM__)
+ kal_uint16 writeLen = 0;
+ UART_CTRL_PUT_BYTES_T data;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (hw_cb->simInterface != 0)
+ SIM_DEBUG_ASSERT(0);
+ data.u4OwenrId = MOD_SIM;
+ data.u2Length = length;
+ data.puBuffaddr = buffer;
+ DclSerialPort_Control(usim_dcb->uart_sim_ccci_handle, SIO_CMD_PUT_BYTES, (DCL_CTRL_DATA_T*)&data);
+ writeLen = data.u2RetSize;
+ return writeLen;
+#else
+ return 0;
+#endif
+}
+
+void SIM_icusb_Timeout(void *parameter)
+{
+ kal_int32 SIM_ICUSB_Timeout = 0;
+ ASSERT(SIM_ICUSB_Timeout);
+}
+kal_uint16 SIM_icusb_GetAllBytes(kal_uint8 *buffer, kal_uint16 length, sim_HW_cb *hw_cb)
+{
+ /* totalLen: amount of readLen
+ readLen: one time read length
+ expLen: total length we wish to read, set volt is 0x8
+ lastLen: how many length we still need to read */
+ kal_uint32 totalLen = 0, readLen = 0, expLen = 0, lastLen = 0, endCnt = 0;
+ kal_uint8 *buf_ptr;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ expLen = lastLen = length;
+ buf_ptr = buffer;
+ while (totalLen != expLen)
+ {
+ /* use Gpt timer to check if we did not receive bytes larger than 3s*/
+ DRV_ICC_GPTI_StartItem(usim_dcb->gpt_handle, 300, SIM_icusb_Timeout, hw_cb);
+ readLen = DRV_ICC_GetBytes(buffer, lastLen, hw_cb);
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ lastLen = expLen - readLen;
+ totalLen += readLen;
+ buffer += readLen;
+// if (readLen != 0)
+// DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC64, totalLen, readLen, lastLen,expLen,0xaaaaaaa1);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL);
+ endCnt ++;
+ if (endCnt == usim_dcb->waitingTime)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC74, *buf_ptr, *(buf_ptr + 1), *(buf_ptr + 2), *(buf_ptr + 3), *(buf_ptr + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC74, *(buf_ptr + 5), *(buf_ptr + 6), *(buf_ptr + 7), *(buf_ptr + 8), *(buf_ptr + 9));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC74, totalLen, readLen, lastLen, expLen, endCnt);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC74, usim_dcb->icusb_state, usim_dcb->waitingTime, 0, 0, 0);
+ sim_addMsg(0xE013, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ //break;
+ }
+ }
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC64, *buf_ptr, *(buf_ptr + 1), *(buf_ptr + 2), *(buf_ptr + 3), *(buf_ptr + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC64, *(buf_ptr + 5), *(buf_ptr + 6), *(buf_ptr + 7), *(buf_ptr + 8), *(buf_ptr + 9));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC64, totalLen, readLen, lastLen, expLen, endCnt);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC64, usim_dcb->icusb_state, 0, 0, 0, 0);
+#endif
+ return totalLen;
+}
+
+kal_uint32 SIM_icusb_errorHandling(kal_uint8 *buffer, kal_uint16 length, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /* just used to print error message */
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_ERRORHANDLING;
+ return 0;
+}
+
+kal_uint16 SIM_icusb_control(kal_uint8 *txbuffer, kal_uint16 txlength, kal_uint8 *rxbuffer, kal_uint16 rxlength, sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry, readLen;
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ for (retry = 0; retry < 3; retry++)
+ {
+ SIM_icusb_PutBytes(txbuffer, txlength, hw_cb);
+ readLen = SIM_icusb_GetAllBytes(rxbuffer, rxlength, hw_cb);
+ if (readLen == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE014, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+ if (readLen == rxlength)
+ {
+ return 0;
+ }
+ /* if readlen != 0x8, we just retry */
+ }
+ /* should not reach here */
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, rxlength, readLen, usim_dcb->icusb_state, txlength, SIM_ICUSB_CCCI_TIMEOUT);
+ SIM_DEBUG_ASSERT(0);
+ return 0;
+}
+
+kal_uint32 SIM_icusb_init(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+// usim_dcb->isIcUsb = KAL_TRUE;
+ usim_dcb->isIcUsbRecPPS = KAL_FALSE;
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_SETVOLT;
+ usim_dcb->waitingTime = 9000;
+ return 0;
+}
+
+kal_uint32 SIM_icusb_setVolt(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_icusb_ackStatus status = SIM_ICUSB_ACK_OK;
+ kal_uint16 ctrlStatus = 0;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (hw_cb->simInterface == 0x0)
+ {
+ //only SIM1 support ICUSB, other interface bypass
+ kal_uint8 setVoltReq[SIM_ICUSB_CONTROL_MESSAGE_LEN] = {0x00, 0x80, 0x00, 0x00, 0x03, 0x00, 0x01, 0x01, 0x01};
+
+ if (usim_dcb->power == CLASS_C_18V)
+ {
+ setVoltReq[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1] = 0x0;
+ }
+ ctrlStatus = SIM_icusb_control(setVoltReq, SIM_ICUSB_CONTROL_MESSAGE_LEN, uncachedDmaBuffer1, SIM_ICUSB_CONTROL_MESSAGE_LEN, hw_cb);
+ if (ctrlStatus == (kal_uint16) SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE015, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+
+ sim_addMsg(0xE00D, uncachedDmaBuffer1[1], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ switch (uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1])
+ {
+ case SIM_ICUSB_ACK_OK:
+ status = SIM_ICUSB_ACK_OK;
+ break;
+ case SIM_ICUSB_ACK_PREFER_3V:
+ case SIM_ICUSB_ACK_CMD_TYPE_ERROR:
+ case SIM_ICUSB_ACK_NEED_RX_TO_ACK:
+ case SIM_ICUSB_ACK_CMD_ERROR:
+ case SIM_ICUSB_ACK_TIMEOUT:
+ case SIM_ICUSB_ACK_NO_CARD:
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, usim_dcb->icusb_state,
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 4],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 3],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ status = SIM_ICUSB_CCCI_TIMEOUT;
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_ENABLESESSION;
+ }
+ //only SIM1 support ICUSB, other interface bypass
+ return status;
+}
+kal_uint32 SIM_icusb_enableSession(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_icusb_ackStatus status = SIM_ICUSB_ACK_OK;
+ kal_uint16 ctrlStatus = 0;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (hw_cb->simInterface == 0x0)
+ {
+ //only SIM1 support ICUSB, other interface bypass
+ kal_uint8 enableSessionReq[SIM_ICUSB_CONTROL_MESSAGE_LEN] = {0x00, 0x80, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0x01};
+ usim_dcb->waitingTime = 2000;
+ ctrlStatus = SIM_icusb_control(enableSessionReq, SIM_ICUSB_CONTROL_MESSAGE_LEN, uncachedDmaBuffer1, SIM_ICUSB_CONTROL_MESSAGE_LEN, hw_cb);
+ if (ctrlStatus == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE016, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+ sim_addMsg(0xE00E, uncachedDmaBuffer1[1], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ switch (uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1])
+ {
+ case SIM_ICUSB_ACK_OK:
+ status = SIM_ICUSB_ACK_OK;
+ break;
+ case SIM_ICUSB_ACK_PREFER_3V:
+ status = SIM_ICUSB_ACK_PREFER_3V;
+ break;
+ case SIM_ICUSB_ACK_CMD_TYPE_ERROR:
+ case SIM_ICUSB_ACK_NEED_RX_TO_ACK:
+ case SIM_ICUSB_ACK_CMD_ERROR:
+ case SIM_ICUSB_ACK_TIMEOUT:
+ case SIM_ICUSB_ACK_NO_CARD:
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, usim_dcb->icusb_state,
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 4],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 3],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ status = SIM_ICUSB_CCCI_TIMEOUT;
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_POWERON;
+ }
+ //only SIM1 support ICUSB, other interface bypass
+ return status;
+}
+
+kal_uint32 SIM_icusb_powerOn(sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry;
+ kal_uint16 readLen = 0, msglen = 0;
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (hw_cb->simInterface == 0x0)
+ {
+ //only SIM1 support ICUSB, other interface bypass
+ kal_uint8 powerOnReq[SIM_ICUSB_CONTROL_MESSAGE_LEN] = {0x00, 0x80, 0x00, 0x00, 0x03, 0x00, 0x10, 0x01, 0x00};
+
+ sim_addMsg(0xE010, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ for (retry = 0; retry < 3; retry++)
+ {
+ SIM_icusb_PutBytes(powerOnReq, SIM_ICUSB_CONTROL_MESSAGE_LEN, hw_cb);
+ readLen = SIM_icusb_GetAllBytes(uncachedDmaBuffer1, SIM_ICUSB_MESSAGE_HEADER_LEN, hw_cb);
+ if (readLen == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE017, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+
+ /* check if icusb card broken */
+ if (uncachedDmaBuffer1[1] == SIM_ICUSB_CONTROL_MESSAGE_TYPE)
+ {
+ usim_icusb_ackStatus status = SIM_ICUSB_ACK_OK;
+ readLen = SIM_icusb_GetAllBytes(&uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN], 0x3, hw_cb);
+ if (readLen == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE020, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+ sim_addMsg(0xE027, uncachedDmaBuffer1[1], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ switch (uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1])
+ {
+ case SIM_ICUSB_ACK_OK:
+ case SIM_ICUSB_ACK_PREFER_3V:
+ case SIM_ICUSB_ACK_CMD_TYPE_ERROR:
+ case SIM_ICUSB_ACK_NEED_RX_TO_ACK:
+ case SIM_ICUSB_ACK_NO_CARD:
+ case SIM_ICUSB_ACK_TIMEOUT:
+ case SIM_ICUSB_ACK_CMD_ERROR:
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, usim_dcb->icusb_state,
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 4],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 3],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ status = SIM_ICUSB_CCCI_TIMEOUT;
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ return status;
+ }
+
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC72, uncachedDmaBuffer1[0],
+ uncachedDmaBuffer1[1],
+ uncachedDmaBuffer1[2],
+ uncachedDmaBuffer1[3],
+ uncachedDmaBuffer1[4]);
+#endif
+ msglen = uncachedDmaBuffer1[4] | (uncachedDmaBuffer1[5] << 8);
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC72, uncachedDmaBuffer1[5], msglen, 0, 0, 0);
+#endif
+ if ((readLen != 0) && (msglen != 0))
+ {
+ readLen = SIM_icusb_GetAllBytes(&uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN], msglen, hw_cb);
+ if (readLen == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE018, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC73, uncachedDmaBuffer1[0],
+ uncachedDmaBuffer1[1],
+ uncachedDmaBuffer1[2],
+ uncachedDmaBuffer1[3],
+ uncachedDmaBuffer1[4]);
+#endif
+ if ((uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN] == 0x3B) || (uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN] == 0x3F))
+ {
+ /* receive all atr, normal return */
+ kal_mem_cpy(usim_dcb->icusb_ATR_data, uncachedDmaBuffer1, msglen);
+ usim_dcb->icusb_ATR_index = msglen;
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[5],
+ uncachedDmaBuffer1[6],
+ uncachedDmaBuffer1[7],
+ uncachedDmaBuffer1[8],
+ uncachedDmaBuffer1[9]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[10],
+ uncachedDmaBuffer1[11],
+ uncachedDmaBuffer1[12],
+ uncachedDmaBuffer1[13],
+ uncachedDmaBuffer1[14]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[15],
+ uncachedDmaBuffer1[16],
+ uncachedDmaBuffer1[17],
+ uncachedDmaBuffer1[18],
+ uncachedDmaBuffer1[19]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[20],
+ uncachedDmaBuffer1[21],
+ uncachedDmaBuffer1[22],
+ uncachedDmaBuffer1[23],
+ uncachedDmaBuffer1[24]);
+#endif
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_CMD;
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[25],
+ uncachedDmaBuffer1[26],
+ uncachedDmaBuffer1[27],
+ uncachedDmaBuffer1[28],
+ usim_dcb->icusb_ATR_index);
+#endif
+ return 0;
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[0],
+ uncachedDmaBuffer1[1],
+ uncachedDmaBuffer1[2],
+ uncachedDmaBuffer1[3],
+ uncachedDmaBuffer1[4]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[5],
+ uncachedDmaBuffer1[6],
+ uncachedDmaBuffer1[7],
+ uncachedDmaBuffer1[8],
+ uncachedDmaBuffer1[9]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, uncachedDmaBuffer1[10],
+ uncachedDmaBuffer1[11],
+ uncachedDmaBuffer1[12],
+ uncachedDmaBuffer1[13],
+ uncachedDmaBuffer1[14]);
+ SIM_DEBUG_ASSERT(0);
+ }
+ }
+ }
+ /* should not reach here */
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC66, readLen, usim_dcb->icusb_state, uncachedDmaBuffer1[4], uncachedDmaBuffer1[5], uncachedDmaBuffer1[6]);
+ SIM_DEBUG_ASSERT(0);
+ }
+ //only SIM1 support ICUSB, other interface bypass
+ return 0;
+}
+
+kal_uint32 SIM_icusb_cmd(sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry = 0, readLen = 0, SW = 0;
+ kal_uint16 msglen = 0;
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ if (hw_cb->simInterface == 0x0)
+ {
+ //only SIM1 support ICUSB, other interface bypass
+ uncachedDmaBuffer0[0] = uncachedDmaBuffer0[1] = uncachedDmaBuffer0[2] = uncachedDmaBuffer0[3] = 0x0;
+ uncachedDmaBuffer0[4] = SimCard->sim_icusb_T0cmd.txSize;
+ uncachedDmaBuffer0[5] = 0x00;
+ kal_mem_cpy(&uncachedDmaBuffer0[6], SimCard->sim_icusb_T0cmd.txData, SimCard->sim_icusb_T0cmd.txSize);
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC67, *SimCard->sim_icusb_T0cmd.txData,
+ *(SimCard->sim_icusb_T0cmd.txData + 1),
+ *(SimCard->sim_icusb_T0cmd.txData + 2),
+ *(SimCard->sim_icusb_T0cmd.txData + 3),
+ *(SimCard->sim_icusb_T0cmd.txData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC67, *(SimCard->sim_icusb_T0cmd.txData + 5),
+ *(SimCard->sim_icusb_T0cmd.txData + 6),
+ *(SimCard->sim_icusb_T0cmd.txData + 7),
+ *(SimCard->sim_icusb_T0cmd.txData + 8),
+ *(SimCard->sim_icusb_T0cmd.txData + 9));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC67, uncachedDmaBuffer0[0],
+ uncachedDmaBuffer0[1],
+ uncachedDmaBuffer0[2],
+ uncachedDmaBuffer0[3],
+ uncachedDmaBuffer0[4]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC67, uncachedDmaBuffer0[5],
+ uncachedDmaBuffer0[6],
+ uncachedDmaBuffer0[7],
+ uncachedDmaBuffer0[8],
+ uncachedDmaBuffer0[9]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC67, uncachedDmaBuffer0[10],
+ uncachedDmaBuffer0[11],
+ uncachedDmaBuffer0[12],
+ uncachedDmaBuffer0[13],
+ uncachedDmaBuffer0[14]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC67, SimCard->sim_icusb_T0cmd.txSize, SimCard->sim_icusb_T0cmd.rcvSize, 0, 0, 0);
+#endif
+ for (retry = 0; retry < 3; retry++)
+ {
+ SIM_icusb_PutBytes(uncachedDmaBuffer0, SimCard->sim_icusb_T0cmd.txSize + SIM_ICUSB_MESSAGE_HEADER_LEN, hw_cb);
+ /* read header at first */
+ readLen = SIM_icusb_GetAllBytes(uncachedDmaBuffer1, SIM_ICUSB_MESSAGE_HEADER_LEN, hw_cb);
+ if (readLen == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE019, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+
+ /* check if icusb card broken */
+ if (uncachedDmaBuffer1[1] == SIM_ICUSB_CONTROL_MESSAGE_TYPE)
+ {
+ kal_uint32 status = 0;
+ readLen = SIM_icusb_GetAllBytes(&uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN], 0x3, hw_cb);
+ if (readLen == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE020, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+ sim_addMsg(0xE028, uncachedDmaBuffer1[1], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ switch (uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1])
+ {
+ case SIM_ICUSB_ACK_OK:
+ case SIM_ICUSB_ACK_PREFER_3V:
+ case SIM_ICUSB_ACK_CMD_TYPE_ERROR:
+ case SIM_ICUSB_ACK_NEED_RX_TO_ACK:
+ case SIM_ICUSB_ACK_NO_CARD:
+ case SIM_ICUSB_ACK_TIMEOUT:
+ case SIM_ICUSB_ACK_CMD_ERROR:
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, usim_dcb->icusb_state,
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 4],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 3],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ status = 0x0000;
+ break;
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+ return status;
+ }
+
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC85, uncachedDmaBuffer1[0],
+ uncachedDmaBuffer1[1],
+ uncachedDmaBuffer1[2],
+ uncachedDmaBuffer1[3],
+ uncachedDmaBuffer1[4]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC85, uncachedDmaBuffer1[5],
+ uncachedDmaBuffer1[6],
+ uncachedDmaBuffer1[7],
+ uncachedDmaBuffer1[8],
+ uncachedDmaBuffer1[9]);
+#endif
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ msglen = uncachedDmaBuffer1[4] | (uncachedDmaBuffer1[5] << 8);
+
+ if ((readLen != 0) && (msglen != 0))
+ {
+ readLen = SIM_icusb_GetAllBytes(&uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN], msglen, hw_cb);
+ if (readLen == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE020, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC86, uncachedDmaBuffer1[5],
+ uncachedDmaBuffer1[6],
+ uncachedDmaBuffer1[7],
+ uncachedDmaBuffer1[8],
+ uncachedDmaBuffer1[9]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC86, uncachedDmaBuffer1[10],
+ uncachedDmaBuffer1[11],
+ uncachedDmaBuffer1[12],
+ uncachedDmaBuffer1[13],
+ uncachedDmaBuffer1[14]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC86, readLen,
+ uncachedDmaBuffer1[4],
+ msglen,
+ 0,
+ 0);
+#endif
+ if (readLen != 0)
+ {
+ SW = (uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN - 1 + readLen] | (uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN - 1 + (readLen - 1)] << 8)); //SW2
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC76, uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN - 1 + readLen],
+ uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN - 1 + (readLen - 1)],
+ SW,
+ 0,
+ 0);
+#endif
+ /* readLen - 2: not need to include SW1/SW2 */
+ if ((readLen - 2) != 0)
+ {
+ kal_mem_cpy(SimCard->sim_icusb_T0cmd.result, &uncachedDmaBuffer1[SIM_ICUSB_MESSAGE_HEADER_LEN], readLen - 2);
+#if defined SIM_DRV_IC_USB_DBG
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC75, *SimCard->sim_icusb_T0cmd.result,
+ *(SimCard->sim_icusb_T0cmd.result + 1),
+ *(SimCard->sim_icusb_T0cmd.result + 2),
+ *(SimCard->sim_icusb_T0cmd.result + 3),
+ *(SimCard->sim_icusb_T0cmd.result + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC75, uncachedDmaBuffer1[0],
+ uncachedDmaBuffer1[1],
+ uncachedDmaBuffer1[2],
+ uncachedDmaBuffer1[3],
+ uncachedDmaBuffer1[4]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC75, uncachedDmaBuffer1[5],
+ uncachedDmaBuffer1[6],
+ uncachedDmaBuffer1[7],
+ uncachedDmaBuffer1[8],
+ uncachedDmaBuffer1[9]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC75, SimCard->sim_icusb_T0cmd.txSize,
+ SimCard->sim_icusb_T0cmd.rcvSize,
+ readLen,
+ SW,
+ 0);
+#endif
+ }
+
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_CMD;
+ return SW;
+ }
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ }
+ /* should not reach here */
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC68, 0x8, readLen, usim_dcb->icusb_state, 0, 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_CMD;
+ return 0;
+}
+kal_uint32 SIM_icusb_powerOff(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_DISABLESESSION;
+ return 0;
+}
+
+kal_uint32 SIM_icusb_disconnectDone(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_icusb_ackStatus status = SIM_ICUSB_ACK_OK;
+ kal_uint16 ctrlStatus = 0;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (hw_cb->simInterface == 0x0)
+ {
+ //only SIM1 support ICUSB, other interface bypass
+ kal_uint8 disconnDoneReq[SIM_ICUSB_CONTROL_MESSAGE_LEN] = {0x00, 0x80, 0x00, 0x00, 0x03, 0x00, 0x02, 0x01, 0x00};
+ usim_dcb->waitingTime = 2000;
+ ctrlStatus = SIM_icusb_control(disconnDoneReq, SIM_ICUSB_CONTROL_MESSAGE_LEN, uncachedDmaBuffer1, SIM_ICUSB_CONTROL_MESSAGE_LEN, hw_cb);
+ if (ctrlStatus == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc4);
+ sim_addMsg(0xE021, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+ sim_addMsg(0xE011, uncachedDmaBuffer1[1], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ switch (uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1])
+ {
+ case SIM_ICUSB_ACK_OK:
+ status = SIM_ICUSB_ACK_OK;
+ break;
+ case SIM_ICUSB_ACK_PREFER_3V:
+ case SIM_ICUSB_ACK_CMD_TYPE_ERROR:
+ case SIM_ICUSB_ACK_NEED_RX_TO_ACK:
+ case SIM_ICUSB_ACK_CMD_ERROR:
+ case SIM_ICUSB_ACK_TIMEOUT:
+ case SIM_ICUSB_ACK_NO_CARD:
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, usim_dcb->icusb_state,
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 4],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 3],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ status = SIM_ICUSB_CCCI_TIMEOUT;
+ break;
+ default:
+ break;
+ }
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_DEINIT;
+ }
+ //only SIM1 support ICUSB, other interface bypass
+ return status;
+}
+
+kal_uint32 SIM_icusb_disableSession(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_icusb_ackStatus status = SIM_ICUSB_ACK_OK;
+ kal_uint16 ctrlStatus = 0;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (hw_cb->simInterface == 0x0)
+ {
+ //only SIM1 support ICUSB, other interface bypass
+ kal_uint8 disableSessionReq[SIM_ICUSB_CONTROL_MESSAGE_LEN] = {0x00, 0x80, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0x00};
+ if (usim_icusb_ccci_channel_status)
+ {
+ usim_dcb->waitingTime = 20000;
+ }
+ else
+ {
+ usim_dcb->waitingTime = 2000;
+ }
+ ctrlStatus = SIM_icusb_control(disableSessionReq, SIM_ICUSB_CONTROL_MESSAGE_LEN, uncachedDmaBuffer1, SIM_ICUSB_CONTROL_MESSAGE_LEN, hw_cb);
+ if (ctrlStatus == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc5);
+ sim_addMsg(0xE022, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ return SIM_ICUSB_CCCI_TIMEOUT;
+ }
+ sim_addMsg(0xE006, uncachedDmaBuffer1[1], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2], uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ switch (uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1])
+ {
+ case SIM_ICUSB_ACK_OK:
+ status = SIM_ICUSB_ACK_OK;
+ break;
+ case SIM_ICUSB_ACK_PREFER_3V:
+ case SIM_ICUSB_ACK_CMD_TYPE_ERROR:
+ case SIM_ICUSB_ACK_NEED_RX_TO_ACK:
+ case SIM_ICUSB_ACK_CMD_ERROR:
+ case SIM_ICUSB_ACK_TIMEOUT:
+ case SIM_ICUSB_ACK_NO_CARD:
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, usim_dcb->icusb_state,
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 4],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 3],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 2],
+ uncachedDmaBuffer1[SIM_ICUSB_CONTROL_MESSAGE_LEN - 1]);
+ status = SIM_ICUSB_CCCI_TIMEOUT;
+ usim_icusb_ccci_channel_status = KAL_FALSE;
+ break;
+ default:
+ break;
+ }
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_DEINIT;
+ usim_icusb_ccci_channel_status = KAL_TRUE;
+ }
+ //only SIM1 support ICUSB, other interface bypass
+ return status;
+}
+
+kal_uint32 SIM_icusb_deinit(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /* Set current state */
+ usim_dcb->icusb_state = SIM_ICUSB_INIT;
+ return 0;
+}
+
+#endif
+
+#if defined(DRV_SIM_DBG_LOW_COST_ULC)
+ #define SIM_MSG_NUM 1
+#elif defined(DRV_SIM_DBG_LOW_COST_COMMON)
+ #define SIM_MSG_NUM 256
+#else
+ #define SIM_MSG_NUM 1024
+#endif
+
+sim_msg sim_msgArray[SIM_MSG_NUM];
+kal_uint32 sim_msgIndex;
+void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2)
+{
+ sim_msg *msgPtr;
+ kal_uint32 savedMask;
+
+ savedMask = SaveAndSetIRQMask();
+ msgPtr = &sim_msgArray[sim_msgIndex];
+ msgPtr->tag = (sim_msgTag)tag;
+ msgPtr->event = event;
+ msgPtr->data1 = data1;
+ msgPtr->data2 = data2;
+ msgPtr->time = drv_get_current_time();
+ sim_msgIndex = (sim_msgIndex + 1) & (SIM_MSG_NUM - 1);
+ RestoreIRQMask(savedMask);
+}
+
+void sim_PDNEnable_MTK(sim_HW_cb *hw_cb)
+{
+ switch (hw_cb->mtk_baseAddr)
+ {
+ case SIM_base:
+ HDMA_PDN_SET(0); // channel 0
+ if (hw_cb->forceOn26M == KAL_FALSE)
+ {
+ PDN_SET(PDN_USIM1);
+ }
+
+ PDN_SET(PDN_USIM1_BCLK);
+
+ break;
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ case SIM2_base:
+ HDMA_PDN_SET(1); // channel 1
+
+ if (hw_cb->forceOn26M == KAL_FALSE)
+ {
+ PDN_SET(PDN_USIM2);
+ }
+
+ PDN_SET(PDN_USIM2_BCLK);
+
+ break;
+#endif // #if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+}
+
+void sim_PDNDisable_MTK(sim_HW_cb *hw_cb)
+{
+ switch (hw_cb->mtk_baseAddr)
+ {
+ case SIM_base:
+ HDMA_PDN_CLR(0); // channel 0
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ PDN_CLR(PDN_USIM1_BCLK);
+#endif
+ PDN_CLR(PDN_USIM1);
+ break;
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ case SIM2_base:
+ HDMA_PDN_CLR(1); // channel 1
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ PDN_CLR(PDN_USIM2_BCLK);
+#endif
+ PDN_CLR(PDN_USIM2);
+ break;
+#endif // #if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ default:
+ SIM_DEBUG_ASSERT(0);
+ break;
+ }
+}
+
+// low power related functions
+extern void USIM_WAIT_EVENT_MTK(usim_dcb_struct *usim_dcb);
+extern void USIM_SET_EVENT_Multilpe(usim_dcb_struct *usim_dcb);
+extern void SIM_SetEvent_MTK(Sim_Card *SIMCARD, kal_uint8 result, sim_HW_cb *hw_cb);
+extern void SIM_WaitEvent_MTK(Sim_Card *SIMCARD, kal_uint32 flag, kal_bool unmaskSIMIntr, sim_HW_cb *hw_cb);
+#if defined(SIM_DRV_SWITCH_MT6306)
+ kal_bool sim_MT6306_noneNeedClk(sim_HW_cb *hw_cb);
+#endif
+void USIM_low_power_related_setting(sim_HW_cb *hw_cb, kal_uint8 option)
+{
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 hwInterfaceNo = hw_cb->simInterface;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ kal_uint32 log_size = 0;
+
+ hwInterfaceNo = hwInterfaceNo; // remove build warning
+
+ if ((option & (USIM_LP_DISABLE | USIM_LP_ENABLE)) == (USIM_LP_DISABLE | USIM_LP_ENABLE))
+ SIM_DEBUG_ASSERT(0);
+#if defined(SIM_DRV_SWITCH_MT6306)
+ sim_MT6306_switchInfo *switch_CB = sim_MT6306_get_MT6306switchCB(hw_cb);
+#if defined(LPWR_SLIM)
+ sim_HW_cb *peerHWCb = hw_cb->simSwitchPeerInterfaceCb;
+#endif
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+
+ option &= ~(USIM_LP_MASK_START_SCLK | USIM_LP_MASK_STOP_SCLK);
+ if (option & USIM_LP_DISABLE)
+ switch_CB->sim_MT6306_LPDisabled |= 1 << hw_cb->simSwitchPortNo;
+ if (option & USIM_LP_ENABLE)
+ switch_CB->sim_MT6306_LPDisabled &= ~(1 << hw_cb->simSwitchPortNo);
+
+ if (sim_MT6306_noneNeedClk(hw_cb) == KAL_FALSE || switch_CB->sim_MT6306_LPDisabled != 0)
+ option &= ~(USIM_LP_ENABLE);
+ if (MTK_SIMIF0 == sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface))
+ hwInterfaceNo = 0;
+ else if (MTK_SIMIF1 == sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface))
+ hwInterfaceNo = 1;
+ else SIM_DEBUG_ASSERT(0);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "[LP]:Interface:%d, Option:%x,%x\n\r", hw_cb->simInterface, option, switch_CB->sim_MT6306_LPDisabled);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+
+ if (option & USIM_LP_DISABLE)
+ {
+ hw_cb->must_not_enable_sleep = KAL_TRUE;
+ Data_Sync_Barrier();
+ usim_waitISR_with_spinlock(hw_cb->spinlockid);
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQMask(hw_cb->mtk_lisrCode);
+#if defined(LPWR_SLIM)
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+#endif // #if defined(LPWR_SLIM)
+ hw_cb->must_not_enable_sleep = KAL_FALSE;
+ sim_PDNDisable_MTK(hw_cb);
+#if !defined(SIM_DRV_SWITCH_MT6306) || defined(SIM_DRV_GEMINI_WITH_MT6306)
+ SIM_DisAllIntr();
+ USIM_DISABLE_TOUT();
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, 0xFFFF);
+#elif defined(__SIM_DRV_CO_LOAD_MT6306__) && defined(SIM_DRV_SWITCH_MT6306)
+ if (sim_connectMT6306 == KAL_FALSE)
+ {
+ SIM_DisAllIntr();
+ USIM_DISABLE_TOUT();
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, 0xFFFF);
+ }
+#endif
+ Data_Sync_Barrier();
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+#if defined(__DRV_SIM_LP_MODE__)
+ if (option & USIM_LP_MASK_NORMAL_VSIM_CURRENT)
+ {
+ DRV_ICC_SetLp(hwInterfaceNo, KAL_FALSE);
+ }
+#endif // #if defined(__DRV_SIM_LP_MODE__)
+#if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+ if (option & USIM_LP_MASK_FORCE_ON_26M)
+ {
+ DRV_ICC_CLKSRC_Lock(hwInterfaceNo, KAL_TRUE);
+ hw_cb->forceOn26M = KAL_TRUE;
+ }
+#endif // #if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+ if (option & USIM_LP_MASK_START_SCLK)
+ {
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)) & SIM_CTRL_HALT)
+ {
+ SIM_ActiveClk_MTK(hw_cb);
+
+ if (!(SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON)) // activation only
+ {
+ // Do not need any delay
+ kal_give_spinlock(hw_cb->spinlockid);
+ }
+ else // sim command, deactivation
+ {
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_ClearBits(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, SIM_CONF_TOUTEN);
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ SimCard->cmdState = SIM_ProcessClk;
+ }
+ else // T1_PROTOCOL
+ {
+ usim_dcb->main_state = CLK_STOPPED_STATE;
+ }
+ SIM_SetTOUT((700 / ((DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) & SIM_BRR_ETUMSK) >> 2) + 1 + 16) >> 2, hw_cb); // longer than spec
+ SIM_SetBits(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, SIM_CONF_TOUTEN);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ kal_give_spinlock(hw_cb->spinlockid);
+ SIM_WaitEvent_MTK(SimCard, CLK_PROC, KAL_FALSE, hw_cb);
+ }
+ else // T1_PROTOCOL
+ {
+ kal_give_spinlock(hw_cb->spinlockid);
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+ }
+
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] clear IRQEN, previous \"wait event\" is set by SIM_RegHotPlugCb\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ kal_uint32 div = DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) & SIM_BRR_CLKMSK;
+ if (div == 0x800)
+ ust_us_busyloop(190);
+ else if (div == 0x0)
+ ust_us_busyloop(163);
+ else if (div == 0x1)
+ ust_us_busyloop(217);
+ else
+ ust_us_busyloop(432);
+ }
+
+ SimCard->t_debug[1] = ust_get_current_time();
+ }
+ }
+ else
+ kal_give_spinlock(hw_cb->spinlockid);
+ }
+ else
+ kal_give_spinlock(hw_cb->spinlockid);
+ }
+ else if (option & USIM_LP_ENABLE)
+ {
+#if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+ if (option & USIM_LP_MASK_FORCE_ON_26M)
+ {
+ DRV_ICC_CLKSRC_Lock(hwInterfaceNo, KAL_TRUE);
+ hw_cb->forceOn26M = KAL_TRUE;
+ }
+ else if (option & USIM_LP_MASK_NORMAL_26M)
+ {
+ DRV_ICC_CLKSRC_Lock(hwInterfaceNo, KAL_FALSE);
+ hw_cb->forceOn26M = KAL_FALSE;
+ }
+#endif // #if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+#if defined(__DRV_SIM_LP_MODE__)
+ if (option & USIM_LP_MASK_REDUCE_VSIM_CURRENT)
+ {
+ DRV_ICC_SetLp(hwInterfaceNo, KAL_TRUE);
+ }
+#endif // #if defined(__DRV_SIM_LP_MODE__)
+ sim_PDNEnable_MTK(hw_cb);
+#if defined(LPWR_SLIM)
+ if (hw_cb->must_not_enable_sleep == KAL_FALSE)
+ {
+ SleepDrv_UnlockSleep(hw_cb->smHandler, hw_cb->sim_task_group);
+ }
+#if defined(SIM_DRV_SWITCH_MT6306)
+ //Make Sure Peer is not Entered and Don't Need CLK
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+ if (sim_MT6306_noneNeedClk(hw_cb) == KAL_TRUE && switch_CB->sim_MT6306_LPDisabled == 0)
+ {
+#if !defined(SIM_DRV_GEMINI_WITH_MT6306)
+ SleepDrv_UnlockSleep(peerHWCb->smHandler, hw_cb->sim_task_group);
+#endif
+ }
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+#endif // #if defined(LPWR_SLIM)
+ }
+ else
+ {
+ if (option & USIM_LP_MASK_STOP_SCLK)
+ {
+ if ((SimCard->clkStop == KAL_TRUE && usim_dcb->phy_proto == T0_PROTOCOL)
+ || (usim_dcb->clock_stop_en == KAL_TRUE && usim_dcb->phy_proto == T1_PROTOCOL))
+ {
+ SIM_DisAllIntr();
+ SIM_ClearBits(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, SIM_CONF_TOUTEN);
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ SimCard->cmdState = SIM_StopClk;
+ }
+ else // T1_PROTOCOL
+ {
+ usim_dcb->main_state = CLK_STOPPING_STATE;
+ }
+ Data_Sync_Barrier();
+ if (hw_cb->issueCardStatus == SIM_CLOCK_FETCH__TERMINAL_RESPONSE)
+ {
+ SIM_SetTOUT(((1860 / ((DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) & SIM_BRR_ETUMSK) >> 2) + 1 + 16) >> 2) + 100, hw_cb); // longer than spec
+ }
+ else
+ {
+ SIM_SetTOUT((1860 / ((DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) & SIM_BRR_ETUMSK) >> 2) + 1 + 16) >> 2, hw_cb); // longer than spec
+ }
+ SIM_SetBits(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, SIM_CONF_TOUTEN);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ }
+ }
+#if defined(__DRV_SIM_LP_MODE__)
+ if (option & USIM_LP_MASK_REDUCE_VSIM_CURRENT)
+ {
+ DRV_ICC_SetLp(hwInterfaceNo, KAL_TRUE);
+ }
+ else if (option & USIM_LP_MASK_NORMAL_VSIM_CURRENT)
+ {
+ DRV_ICC_SetLp(hwInterfaceNo, KAL_FALSE);
+ }
+#endif // #if defined(__DRV_SIM_LP_MODE__)
+#if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+ if (option & USIM_LP_MASK_FORCE_ON_26M)
+ {
+ DRV_ICC_CLKSRC_Lock(hwInterfaceNo, KAL_TRUE);
+ hw_cb->forceOn26M = KAL_TRUE;
+ }
+ else if (option & USIM_LP_MASK_NORMAL_26M)
+ {
+ DRV_ICC_CLKSRC_Lock(hwInterfaceNo, KAL_FALSE);
+ hw_cb->forceOn26M = KAL_FALSE;
+ }
+#endif // #if defined(SIM_LOCK_SRCCLK_FOR_NONE_STOP_CLK_CARD)
+ }
+}
+
+#if defined(__SIM_DRV_CO_LOAD_MT6306__) && defined(SIM_DRV_SWITCH_MT6306)
+void USIM_connect_mt6306(void)
+{
+ extern kal_uint8 MT6306_getDeviceAddr(void);
+ extern kal_uint32 MT6306_geti2cInterface(kal_uint32 MT6306Interface);
+ extern void MT6306_GPIO_init(kal_uint8 deviceAddress);
+ extern void MT6306_Restore_GPIO_Mode(void);
+ extern void MT6306_Writer_GPIO(kal_uint8 device_addr, kal_uint8 data_addr, kal_uint8 data_value);
+ extern kal_uint8 MT6306_Read_GPIO(kal_uint8 device_addr, kal_uint8 data_addr);
+ extern void MT6306_HW_I2C_init(kal_uint8 deviceAddress);
+ extern void MT6306_HW_I2C_writer(kal_uint8 addr, kal_uint8 data_addr, kal_uint8 data_value);
+ extern kal_uint8 MT6306_HW_I2C_reader(kal_uint8 device_addr, kal_uint8 data_addr);
+
+ kal_uint8 i = 0;
+
+ sim_connectMT6306 = KAL_TRUE;
+
+ MT6306_GPIO_init(MT6306_getDeviceAddr());
+
+ if (MT6306_I2C_USE_DEDICATED_GPIO == MT6306_geti2cInterface(0))
+ {
+ for ( i = 1; i < 6; i++)
+ {
+ MT6306_Writer_GPIO(MT6306_getDeviceAddr(), 8, i);
+ if (MT6306_Read_GPIO(0, 8) != i)
+ {
+ sim_connectMT6306 = KAL_FALSE;
+ MT6306_Restore_GPIO_Mode();
+ break;
+ }
+ }
+ }
+ else if (MT6306_I2C_USE_HW_I2C == MT6306_geti2cInterface(0))
+ {
+ MT6306_HW_I2C_init(MT6306_getDeviceAddr());
+ for ( i = 1; i < 6; i++)
+ {
+ MT6306_HW_I2C_writer(MT6306_getDeviceAddr(), 8, i);
+ if (MT6306_HW_I2C_reader(MT6306_getDeviceAddr(), 8) != i)
+ {
+ sim_connectMT6306 = KAL_FALSE;
+ MT6306_Restore_GPIO_Mode();
+ break;
+ }
+ }
+ }
+
+ return;
+}
+#endif
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+void sim_query_GpioNumOfSimPins(void)
+{
+ kal_uint8 *query;
+
+ query = (kal_uint8 *) "GPIO_SIM1_SIO";
+ if (IPC_RPC_GPIO_GetPin(query, 14, (void *) &GPIO_SIM1_SIMIO) < 0) GPIO_SIM1_SIMIO = 0;
+
+ query = (kal_uint8 *) "GPIO_SIM1_SCLK";
+ if (IPC_RPC_GPIO_GetPin(query, 15, (void *) &GPIO_SIM1_SIMCLK) < 0) GPIO_SIM1_SIMCLK = 0;
+
+ query = (kal_uint8 *) "GPIO_SIM1_SRST";
+ if (IPC_RPC_GPIO_GetPin(query, 15, (void *) &GPIO_SIM1_SIMRST) < 0) GPIO_SIM1_SIMRST = 0;
+
+ query = (kal_uint8 *) "GPIO_SIM2_SIO";
+ if (IPC_RPC_GPIO_GetPin(query, 14, (void *) &GPIO_SIM2_SIMIO) < 0) GPIO_SIM2_SIMIO = 0;
+
+ query = (kal_uint8 *) "GPIO_SIM2_SCLK";
+ if (IPC_RPC_GPIO_GetPin(query, 15, (void *) &GPIO_SIM2_SIMCLK) < 0) GPIO_SIM2_SIMCLK = 0;
+
+ query = (kal_uint8 *) "GPIO_SIM2_SRST";
+ if (IPC_RPC_GPIO_GetPin(query, 15, (void *) &GPIO_SIM2_SIMRST) < 0) GPIO_SIM2_SIMRST = 0;
+
+ return;
+}
+#endif
+#endif // #ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#else // #ifndef DRV_SIM_OFF
+/*following is dummy API*/
+void sim_init_hwCb(void) {}
+void DRV_ICC_interface_init(void) {}
+#endif // #ifndef DRV_SIM_OFF
diff --git a/mcu/driver/devdrv/usim/src/icc_switchControl_al.c b/mcu/driver/devdrv/usim/src/icc_switchControl_al.c
new file mode 100644
index 0000000..47def27
--- /dev/null
+++ b/mcu/driver/devdrv/usim/src/icc_switchControl_al.c
@@ -0,0 +1,1666 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * switchControl_al.c(originally named sim_ctrl_al.c)
+ *
+ * Project:
+ * --------
+ * Gemini
+ *
+ * Description:
+ * ------------
+ * this file to handle original SIM task APIs on multiple SIM interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "drv_comm.h"
+#include "sim_drv_trc.h"
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#include "reg_base.h"
+#include "intrCtrl.h"
+#include "sim_al.h"
+#include "sim_hw_mtk.h"
+#include "sim_sw_comm.h"
+#include "sim_drv_SW_API.h"
+#include "sync_data.h"
+
+#include "multi_icc_custom.h"
+//#include "gpt_sw.h"
+//#include "gpio_sw.h"
+#include "drv_hisr.h"
+
+
+#include "sim_ctrl_al.h"
+
+#ifdef DCL_SIM_INTERFACE
+ #include "dcl.h"
+#endif
+
+#include "kal_trace.h"
+
+#include "multi_icc_custom.h"
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ #include "eint.h"
+ #if defined(__SIM_HOT_SWAP_POLL_TIMER__)
+ #include "sim_public_enum.h"
+ #endif
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+#if defined(__SIM_HOT_SWAP_SUPPORT__) || defined(__LOCK_VSIM__)
+ #include "ccci_rpc_if.h"
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+#if defined(LPWR_SLIM)
+ #include "sleepdrv_interface.h"
+#endif
+
+//#ifdef DRV_MULTIPLE_SIM //DRV_2_SIM_CONTROLLER
+#if (defined(DRV_SIM_ALL_SOLUTION_BUILT) || defined(DRV_MULTIPLE_SIM))
+
+
+extern sim_ctrlDriver sim_ctrlDriver_MT6302;
+extern sim_ctrlDriver sim_ctrlDriver_MTK;
+extern sim_ctrlDriver sim_ctrlDriver_MT6306;
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ extern SIM_ICC_HOT_PLUG iccHotPlugTable[];
+ extern const SIM_ICC_HW_SW_MAPPING iccMappingTable[];
+ #if defined(SIM_DRV_SWITCH_MT6306)
+ #define iccSlotNum 4
+ #else
+ #define iccSlotNum 2
+ #endif
+ #if defined(__SIM_HOT_SWAP_POLL_TIMER__)
+ extern void sim_hot_swap_poll_timer_rollback(kal_uint32 which_sim);
+ extern void sim_hot_swap_poll_timer_rollback_codeck_peer(kal_uint32 which_sim);
+ #endif
+ extern kal_uint32 SIM_EINT_GetAttribute(kal_uint32 simInterface,kal_uint8 *EintName, kal_uint32 EintNameLength, kal_uint32 queryType, void *result, kal_uint32 resultLength);
+#endif
+//static usim_dcb_struct usim_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+kal_uint32 hwCbArray[DRV_SIM_MAX_LOGICAL_INTERFACE]; //from logical number to sim_HW_cb
+
+/*default driver used in pre-defined macro, customer can call sim_hookCtrlDriver to relpace what they want*/
+#if defined(DRV_2_SIM_MT6302)
+sim_ctrlDriver *sim_driverTable[DRV_SIM_MAX_LOGICAL_INTERFACE] = {&sim_ctrlDriver_MT6302, &sim_ctrlDriver_MT6302};
+#elif defined(SIM_DRV_SWITCH_MT6306)
+sim_ctrlDriver *sim_driverTable[DRV_SIM_MAX_LOGICAL_INTERFACE] = {&sim_ctrlDriver_MT6306, &sim_ctrlDriver_MT6306};
+#elif defined(DRV_2_SIM_CONTROLLER)
+sim_ctrlDriver *sim_driverTable[DRV_SIM_MAX_LOGICAL_INTERFACE] = {&sim_ctrlDriver_MTK, &sim_ctrlDriver_MTK};
+#else
+sim_ctrlDriver *sim_driverTable[DRV_SIM_MAX_LOGICAL_INTERFACE] = {&sim_ctrlDriver_MT6302, &sim_ctrlDriver_MT6302};
+#endif
+
+kal_bool sim_physicalSlotChanged;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ kal_bool sim_connectMT6306 = KAL_FALSE;
+#endif
+
+extern kal_uint8 is_HW_VERIFICATION_enabled(void);
+//extern kal_taskid kal_get_current_thread_ID(void);
+
+#define SIM_AL_ACTION_RESET 0x000F0001
+#define SIM_AL_ACTION_POWOFF 0x000F0002
+#define SIM_AL_ACTION_COMMAND 0x000F0003
+#define SIM_AL_ACTION_EOC 0x000F0004
+
+
+kal_bool sim_switchPhysicalSlotMapping(kal_bool inverse)
+{
+ kal_uint32 maskValue;
+
+ maskValue = SaveAndSetIRQMask();
+ sim_physicalSlotChanged = inverse;
+ RestoreIRQMask(maskValue);
+
+ if (KAL_FALSE == maskValue)
+ {
+ DRV_ICC_print_str("SIM slots mapping is default mapping now\n\r");
+ }
+ else
+ {
+ DRV_ICC_print_str("SIM slots mapping is inverse mapping now\n\r");
+ }
+
+ return sim_physicalSlotChanged;
+}
+
+/*this is just adaption layer, protections, project dependent work arounds should not be implemented here*/
+void sim_hookCtrlDriver(kal_uint32 simInterface, sim_ctrlDriver *driver)
+{
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = DRV_SIM_MAX_LOGICAL_INTERFACE - simInterface;
+
+
+ if (0 != simInterface)
+ SIM_DEBUG_ASSERT(0);
+ sim_driverTable[simInterface] = driver;
+}
+
+extern const unsigned char USIM1_EINT_NO;
+extern const unsigned char USIM2_EINT_NO;
+extern kal_uint32 eint_src_map[];
+#if defined (__SIM_HOT_SWAP_SUPPORT__) && defined (__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ kal_bool eint_is_registered = KAL_FALSE;
+#endif
+#if defined (__SIM_HOT_SWAP_SUPPORT__) && defined(__SIM_HOT_SWAP_POLL_TIMER__)
+ volatile kal_spinlockid spinlockid_poll_timer = 0;
+#endif
+usim_status_enum L1sim_Reset_All(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, SIM_ICC_APPLICATION application)
+{
+ sim_ctrlDriver *simDriver;
+ usim_status_enum status;
+ kal_uint32 simInterface;
+ sim_HW_cb *hw_cb;
+ Sim_Card *SimCard;
+
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ kal_int32 ipcStatus = 0, log_size = 0;
+ kal_uint8 *query, querystring[25] = "MD1_SIM1_HOT_PLUG_EINT";
+ #ifdef __SIM_GET_CARD_DETECT_STATUS_SUPPORT__
+ kal_uint8 *sim_detect_pin_query, sim_detect_pin_querystring[20] = "GPIO_SIM1_HOT_PLUG";
+ sim_detect_pin_query = &sim_detect_pin_querystring[0];
+ #endif
+
+ SIM_ICC_HOT_PLUG iccHotPlug = {KAL_FALSE, KAL_FALSE, KAL_FALSE, KAL_FALSE, 0, 0, 0, 0, 0, 0, NULL, NULL};
+ query = &querystring[0];
+#endif // __SIM_HOT_SWAP_SUPPORT__
+#ifdef SIM_4_CARD_SMT_TEST
+ SIM_ICC_APPLICATION anotherApplication;
+ kal_uint32 anotherSimInterface;
+ sim_power_enum anotherResultVolt;
+ sim_ctrlDriver *anotherSimDriver;
+ usim_status_enum anotherStatus;
+#endif
+
+ simInterface = sim_get_logicalNum_from_app(application);
+#ifdef SIM_4_CARD_SMT_TEST
+ if (SIM_ICC_APPLICATION_PHONE1 == application)
+ anotherApplication = SIM_ICC_APPLICATION_PHONE3;
+ else if (SIM_ICC_APPLICATION_PHONE2 == application)
+ anotherApplication = SIM_ICC_APPLICATION_PHONE4;
+ else
+ SIM_DEBUG_ASSERT(0);
+ anotherSimInterface = sim_get_logicalNum_from_app(anotherApplication);
+#endif
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+#ifdef SIM_4_CARD_SMT_TEST
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= anotherSimInterface)
+ SIM_DEBUG_ASSERT(0);
+#endif
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ {
+ DRV_ICC_print_str("sim interface inversed!!\n\r");
+ simInterface = 1 - simInterface;
+ application = 1 - application; // need to switch to get correct hwcb and SIMIF number
+ }
+
+ if (0x0 == ResultVolt)
+ SIM_DEBUG_ASSERT(0);
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC21, ExpectVolt, warm, application, sim_physicalSlotChanged, 0);
+
+ SimCard = GET_SIM_CB(simInterface);
+ SimCard->t_debug[0] = 0;
+ SimCard->t_debug[1] = 0;
+ SimCard->t_debug[2] = 0;
+ SimCard->t_debug[3] = 0;
+ SimCard->t_debug[4] = 0;
+ SimCard->t_debug[5] = 0;
+
+#ifdef __CUSTOMER_HW_VERIFICATION__
+ simInterface = 0;
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ sim_MT6302_addMsg(SIM_MT6302_ACTION_RESET, simInterface, 0, 0);
+
+ USIM_low_power_related_setting(hw_cb, USIM_LP_DISABLE | USIM_LP_MASK_NORMAL_VSIM_CURRENT | USIM_LP_MASK_FORCE_ON_26M | USIM_LP_MASK_START_SCLK);
+
+ status = simDriver->reset(ExpectVolt, ResultVolt, warm, (sim_HW_cb *)(hwCbArray[simInterface]));
+
+ if (status == USIM_NO_ERROR)
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+ else
+ {
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_NORMAL_26M | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+#if defined(__ABNORMAL_CARD__)
+ usim_set_sim_io_special_mode(simInterface, KAL_FALSE);
+#endif // #if defined(__ABNORMAL_CARD__)
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ hw_cb->canUse_4_33_SCLK = KAL_FALSE;
+#endif
+ }
+
+ sim_MT6302_addMsg(SIM_MT6302_ACTION_EOC, simInterface, drv_get_current_time(), 0);
+ simDriver->EOC((sim_HW_cb *)(hwCbArray[simInterface]));
+
+ simInterface = 1;
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ sim_MT6302_addMsg(SIM_MT6302_ACTION_RESET, simInterface, 0, 0);
+ /*when we release single SIM MMI, we only release SIM1 MMI, cusrtomer won't get SIM2 MMI, SIM1 is what MMI need*/
+ //status = simDriver->reset(ExpectVolt, ResultVolt, warm, simInterface);
+ sim_MT6302_addMsg(SIM_MT6302_ACTION_EOC, simInterface, drv_get_current_time(), 0);
+ simDriver->EOC(simInterface);
+#else
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ simDriver->addMessage(SIM_AL_ACTION_RESET, simInterface, (kal_uint32)kal_get_current_thread_ID(), 0);
+
+ USIM_low_power_related_setting(hw_cb, USIM_LP_DISABLE | USIM_LP_MASK_NORMAL_VSIM_CURRENT | USIM_LP_MASK_FORCE_ON_26M | USIM_LP_MASK_START_SCLK);
+
+#if defined(__LOCK_VSIM__)
+ sim_nfc_communication sim_nfc_msg, nfc_sim_msg;
+ sim_nfc_msg.lock_vsim = (sim_get_hwCtrl_from_logicalNum(simInterface) << 4) | 1;
+ nfc_sim_msg.lock_vsim = 0;
+ DRV_ICC_print_str("vsim lock!!\n\r");
+ IPC_RPC_General_Query(IPC_RPC_USIM2NFC_OP, (void *) &sim_nfc_msg, sizeof(sim_nfc_msg), (void *) &nfc_sim_msg, sizeof(nfc_sim_msg));
+#endif // #if defined(__LOCK_VSIM__)
+
+ sim_custom_setting_before_resetting_sim(simInterface);
+ status = simDriver->reset(ExpectVolt, ResultVolt, warm, (sim_HW_cb *)(hwCbArray[simInterface]));
+
+#if defined(__LOCK_VSIM__)
+ sim_nfc_msg.lock_vsim = (sim_get_hwCtrl_from_logicalNum(simInterface) << 4) | 0;
+ nfc_sim_msg.lock_vsim = 0;
+ IPC_RPC_General_Query(IPC_RPC_USIM2NFC_OP, (void *) &sim_nfc_msg, sizeof(sim_nfc_msg), (void *) &nfc_sim_msg, sizeof(nfc_sim_msg));
+ DRV_ICC_print_str("vsim unlock!!\n\r");
+#endif // #if defined(__LOCK_VSIM__)
+
+ if (status == USIM_NO_ERROR)
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+ else
+ {
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_NORMAL_26M | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+#if defined(__ABNORMAL_CARD__)
+ usim_set_sim_io_special_mode(simInterface, KAL_FALSE);
+#endif // #if defined(__ABNORMAL_CARD__)
+#if !defined(__FPGA__)
+ sim_dump_gpio(hw_cb);
+#endif
+ }
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+#if defined(SIM_DRV_SWITCH_MT6306) && defined(__SIM_DRV_CO_LOAD_MT6306__)
+ // does not support
+ extern kal_bool MT6306_disable_SIM_HOT_SWAP_feature(void);
+ if (sim_connectMT6306 == KAL_TRUE && MT6306_disable_SIM_HOT_SWAP_feature() == KAL_TRUE)
+ {
+ DRV_ICC_print_str("does not support SIM HOT SWAP feature\n\r");
+ goto LEAVE_REG_EINT;
+ }
+#endif
+#if defined(__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ if (eint_is_registered == KAL_TRUE)
+ {
+ DRV_ICC_print_str("[SIM_DRV][CO_DECK]EINT is registered\n\r");
+ goto HAVE_REG_EINT;
+ }
+ else
+ {
+ eint_is_registered = KAL_TRUE;
+ ipcStatus = SIM_EINT_GetAttribute(simInterface, query, 23, SIM_HOT_PLUG_EINT_NUMBER, (void *)&iccHotPlug.eintNo, 4);
+
+ if (ipcStatus < 0)
+ {
+ hw_cb->no_md_eint_settings = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "get eint no fail %d %d\n\r", ipcStatus, iccHotPlug.eintNo);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ // we should always register eint. If we bootup without plugin simcard, status will display NO_CARD. we will never get insert event because eint is not registered
+
+ if (application == SIM_ICC_APPLICATION_PHONE2)
+ query = (kal_uint8 *)"MD1_SIM2_HOT_PLUG_EINT";
+ else if (application == SIM_ICC_APPLICATION_PHONE3)
+ query = (kal_uint8 *)"MD1_SIM3_HOT_PLUG_EINT";
+
+
+#if defined (__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ }
+ }
+#endif
+
+ kal_uint32 i = 0;
+ for (i = 0; i < iccSlotNum; i++)
+ {
+ if (application == iccHotPlugTable[i].application)
+ {
+ if (iccHotPlugTable[i].registed == KAL_TRUE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[registed]EINT: %d, %d %d %d %d %d %d\n\r",
+ application,
+ iccHotPlugTable[i].eintNo,
+ iccHotPlugTable[i].debounceTime,
+ iccHotPlugTable[i].polarity,
+ iccHotPlugTable[i].sensitivity,
+ iccHotPlugTable[i].socketType,
+ eint_src_map[iccHotPlug.eintNo]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto HAVE_REG_EINT;
+ }
+ }
+ }
+ if (hw_cb->no_md_eint_settings == KAL_TRUE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "no md eint settings in DWS, LEAVE_REG_EINT");
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto LEAVE_REG_EINT;
+ }
+ // if any rpc error happens, we should leave register eint
+ ipcStatus = SIM_EINT_GetAttribute(simInterface, query, 23, SIM_HOT_PLUG_EINT_NUMBER, (void *)&iccHotPlug.eintNo, 4);
+ if (ipcStatus < 0)
+ {
+ hw_cb->no_md_eint_settings = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "get eint no fail %d %d, please request HW to check ALPS DWS setting.\n\r", ipcStatus, iccHotPlug.eintNo);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto LEAVE_REG_EINT;
+ }
+ ipcStatus = SIM_EINT_GetAttribute(simInterface, query, 23, SIM_HOT_PLUG_EINT_DEBOUNCETIME, (void *)&iccHotPlug.debounceTime, 4);
+
+ if (ipcStatus < 0)
+ {
+ hw_cb->no_md_eint_settings = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "get debounce fail %d %d, please request HW to check ALPS DWS setting.\n\r", ipcStatus, iccHotPlug.debounceTime);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto LEAVE_REG_EINT;
+ }
+
+ ipcStatus = SIM_EINT_GetAttribute(simInterface, query, 23, SIM_HOT_PLUG_EINT_POLARITY, (void *)&iccHotPlug.polarity, 4);
+
+ if (ipcStatus < 0)
+ {
+ hw_cb->no_md_eint_settings = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "get polarity fail %d %d, please request HW to check ALPS DWS setting.\n\r", ipcStatus, iccHotPlug.polarity);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto LEAVE_REG_EINT;
+ }
+
+ ipcStatus = SIM_EINT_GetAttribute(simInterface, query, 23, SIM_HOT_PLUG_EINT_SENSITIVITY, (void *)&iccHotPlug.sensitivity, 4);
+
+ if (ipcStatus < 0)
+ {
+ hw_cb->no_md_eint_settings = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "get sensitivity fail %d %d, please request HW to check ALPS DWS setting.\n\r", ipcStatus, iccHotPlug.sensitivity);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto LEAVE_REG_EINT;
+ }
+
+ ipcStatus = SIM_EINT_GetAttribute(simInterface, query, 23, SIM_HOT_PLUG_EINT_SOCKETTYPE, (void *)&iccHotPlug.socketType, 4);
+
+ if (ipcStatus < 0)
+ {
+ hw_cb->no_md_eint_settings = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "get socket fail %d %d, please request HW to check ALPS DWS setting.\n\r", ipcStatus, iccHotPlug.socketType);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ goto LEAVE_REG_EINT;
+ }
+#ifdef __SIM_GET_CARD_DETECT_STATUS_SUPPORT__
+#if !defined(__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ if (application == SIM_ICC_APPLICATION_PHONE2)
+ {
+ sim_detect_pin_query = (kal_uint8 *)"GPIO_SIM2_HOT_PLUG";
+ }
+
+ ipcStatus = IPC_RPC_GPIO_GetPin(sim_detect_pin_query, 19, (void *)&hw_cb->sim_detect_pin_num);
+ if (ipcStatus < 0)
+ {
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "get SIM%d HOT PLUG pin fail %d, please request HW to check ALPS DWS setting.\n\r", hw_cb->simInterface, ipcStatus);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else
+ {
+ hw_cb->polarity = iccHotPlug.polarity;
+ }
+
+#else //CO_DECK
+ ipcStatus = IPC_RPC_GPIO_GetPin(sim_detect_pin_query, 19, (void *)&hw_cb->sim_detect_pin_num);
+ if (ipcStatus < 0)
+ {
+ sim_detect_pin_query = (kal_uint8 *)"GPIO_SIM2_HOT_PLUG";
+ ipcStatus = IPC_RPC_GPIO_GetPin(sim_detect_pin_query, 19, (void *)&hw_cb->sim_detect_pin_num);
+ if (ipcStatus < 0)
+ {
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "get SIM%d HOT PLUG pin fail %d, please request HW to check ALPS DWS setting.\n\r", hw_cb->simInterface, ipcStatus);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else
+ {
+ hw_cb->polarity = iccHotPlug.polarity;
+ ((sim_HW_cb *)(hwCbArray[1 - simInterface]))->polarity = iccHotPlug.polarity;
+ ((sim_HW_cb *)(hwCbArray[1 - simInterface]))->sim_detect_pin_num = hw_cb->sim_detect_pin_num;
+ }
+ }
+ else
+ {
+ hw_cb->polarity = iccHotPlug.polarity;
+ ((sim_HW_cb *)(hwCbArray[1 - simInterface]))->polarity = iccHotPlug.polarity;
+ ((sim_HW_cb *)(hwCbArray[1 - simInterface]))->sim_detect_pin_num = hw_cb->sim_detect_pin_num;
+ }
+#endif
+#endif
+
+ sim_reg_hot_plug_eint(application, iccHotPlug.eintNo, iccHotPlug.debounceTime, iccHotPlug.polarity, iccHotPlug.sensitivity, iccHotPlug.socketType);
+
+LEAVE_REG_EINT:
+ log_size = kal_sprintf(hw_cb->dbgStr, "EINT: %d, %d %d %d %d %d %d %d\n\r", application, ipcStatus, iccHotPlug.eintNo, iccHotPlug.debounceTime, iccHotPlug.polarity, iccHotPlug.sensitivity, iccHotPlug.socketType, eint_src_map[iccHotPlug.eintNo]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+HAVE_REG_EINT:
+ sim_dump_eint(hw_cb);
+#endif // End of #ifdef __SIM_HOT_SWAP_SUPPORT__
+ simDriver->addMessage(SIM_AL_ACTION_EOC, simInterface, 0, 0);
+ simDriver->EOC((sim_HW_cb *)(hwCbArray[simInterface]));
+
+#ifdef SIM_4_CARD_SMT_TEST
+ /*find out the hooked function table*/
+ anotherSimDriver = sim_driverTable[anotherSimInterface];
+ SIM_DEBUG_ASSERT(0 != anotherSimDriver);
+ anotherSimDriver->addMessage(SIM_AL_ACTION_RESET, anotherSimInterface, (kal_uint32)kal_get_current_thread_ID(), 0);
+ anotherStatus = anotherSimDriver->reset(UNKNOWN_POWER_CLASS, &anotherResultVolt, warm, (sim_HW_cb *)(hwCbArray[anotherSimInterface]));
+ if (USIM_NO_ERROR == anotherStatus)
+ {
+ DRV_ICC_print_str("another SIM card found!!\n\r");
+ }
+ else
+ {
+ DRV_ICC_print_str("another SIM card not found!!\n\r");
+ }
+
+ anotherSimDriver->addMessage(SIM_AL_ACTION_EOC, anotherSimInterface, 0, 0);
+ anotherSimDriver->EOC((sim_HW_cb *)(hwCbArray[anotherSimInterface]));
+#endif
+
+#endif
+
+ return status;
+}
+
+#if 0
+#ifndef __MAUI_BASIC__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+
+sim_status L1sim_Cmd_All(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, SIM_ICC_APPLICATION application, kal_uint8 *bypass6263)
+{
+ sim_ctrlDriver *simDriver;
+ sim_status status;
+
+ kal_uint32 simInterface;
+ sim_HW_cb *hw_cb;
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+
+ kal_uint32 auth_start = 0, auth_end = 0;
+
+ kal_uint32 status_start = 0, status_end = 0;
+ simInterface = sim_get_logicalNum_from_app(application);
+
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined (__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ sim_HW_cb *peer_hw_cb = (sim_HW_cb *)(hwCbArray[1 - simInterface]);
+ Sim_Card * peer_SimCard = GET_SIM_CB(1 - simInterface);
+ usim_dcb_struct *peer_usim_dcb = GET_USIM_CB(1 - simInterface);
+#endif
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ if (0x0 == txData || 0x0 == txSize || 0x0 == rxSize)
+ SIM_DEBUG_ASSERT(0);
+
+ if (txData[1] == 0x88)
+ auth_start = ust_get_current_time();
+
+ if (txData[1] == 0xF2)
+ status_start = ust_get_current_time();
+
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ simDriver->addMessage(SIM_AL_ACTION_COMMAND, simInterface, (kal_uint32)kal_get_current_thread_ID(), 0);
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ SimCard = GET_SIM_CB(simInterface);
+
+ SimCard->bypass6263 = *bypass6263;
+
+ usim_dcb = GET_USIM_CB(simInterface);
+
+ if (SimCard->cmd_duration_count >= 200 || SimCard->cmd_duration_count == 0)
+ {
+ kal_uint32 avg = (SimCard->cmd_duration_count == 0) ? 0 : SimCard->cmd_duration_sum / SimCard->cmd_duration_count;
+#if !defined(__MAUI_BASIC__)
+
+ MD_TRC(LOG_SIM_DRV_AVG_CMD_TIME,hw_cb->simInterface, SIM_PRINT_L1SIM_CMD_TRC126,
+ hw_cb->simInterface, SimCard->cmd_duration_count, SimCard->cmd_duration_sum, avg, 0);
+ SimCard->cmd_duration_count = 0;
+ SimCard->cmd_duration_sum = 0;
+#else
+ DRV_ICC_print_dec(hw_cb, SIM_PRINT_L1SIM_CMD_TRC126, hw_cb->simInterface, SimCard->cmd_duration_count, SimCard->cmd_duration_sum, avg, 0);
+#endif
+ }
+
+ DRV_ICC_print_dec(hw_cb, SIM_PRINT_L1SIM_CMD_TRC129,
+ (SimCard->t_debug[1] == 0) ? 0 : ust_us_duration(SimCard->t_debug[0], SimCard->t_debug[1]),
+ ust_us_duration(SimCard->t_debug[0], SimCard->t_debug[4]),
+ (SimCard->t_debug[5] == 0) ? 0 : ust_us_duration(SimCard->t_debug[4], SimCard->t_debug[5]),
+ (SimCard->t_debug[5] == 0) ? ust_us_duration(SimCard->t_debug[0], SimCard->t_debug[4]) : ust_us_duration(SimCard->t_debug[0], SimCard->t_debug[5]),
+ (SimCard->t_debug[5] == 0) ? ust_us_duration(SimCard->t_debug[4], ust_get_current_time()) : ust_us_duration(SimCard->t_debug[5], ust_get_current_time()));
+ SimCard->t_debug[0] = 0;
+ SimCard->t_debug[1] = 0;
+ SimCard->t_debug[2] = 0;
+ SimCard->t_debug[3] = 0;
+ SimCard->t_debug[4] = 0;
+ SimCard->t_debug[5] = 0;
+
+ SimCard->t_debug[0] = ust_get_current_time();
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (hw_cb->PollTimerStart == KAL_TRUE)
+ {
+ hw_cb->PollTimerStart = KAL_FALSE;
+ hw_cb->PollTimerEnd = KAL_FALSE;
+ SimCard->poll_sim_2s = KAL_TRUE;
+ usim_dcb->poll_sim_2s = KAL_TRUE;
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] Start Real Timer", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+#endif
+ USIM_low_power_related_setting(hw_cb, USIM_LP_DISABLE | USIM_LP_MASK_NORMAL_VSIM_CURRENT | USIM_LP_MASK_START_SCLK);
+#if defined(DRV_SIM_6292_SERIES) && defined(SIM_DRV_SWITCH_MT6306)
+ extern void sim_MT6306_clkStopTimerStop(sim_HW_cb * hw_cb);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+ sim_MT6306_clkStopTimerStop(hw_cb);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+ status = simDriver->command(txData, txSize, rxData, rxSize, (sim_HW_cb *)(hwCbArray[simInterface]));
+
+ if (status == SIM_SW_STATUS_FAIL)
+ {
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_REDUCE_VSIM_CURRENT | USIM_LP_MASK_NORMAL_26M);
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ hw_cb->canUse_4_33_SCLK = KAL_FALSE;
+#endif
+ }
+ else if ((usim_dcb->clock_stop_en == KAL_TRUE && usim_dcb->phy_proto == T1_PROTOCOL)
+ || (SimCard->clkStop == KAL_TRUE && usim_dcb->phy_proto == T0_PROTOCOL))
+ {
+ if (hw_cb->doNotStopSimClock)
+ ;
+ else
+ USIM_low_power_related_setting(hw_cb, USIM_LP_MASK_REDUCE_VSIM_CURRENT | USIM_LP_MASK_STOP_SCLK);
+ }
+ else
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+
+ simDriver->addMessage(SIM_AL_ACTION_EOC, simInterface, 0, 0);
+ simDriver->EOC((sim_HW_cb *)(hwCbArray[simInterface]));
+
+ SimCard->t_debug[4] = ust_get_current_time();
+
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ kal_uint32 need_rollback[2] = {0}, need_callBack[2] = {0};
+ kal_take_spinlock(spinlockid_poll_timer, KAL_INFINITE_WAIT);
+
+ if (SimCard->poll_sim_2s || usim_dcb->poll_sim_2s)
+ {
+ SimCard->poll_sim_2s = KAL_FALSE;
+ usim_dcb->poll_sim_2s = KAL_FALSE;
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] Stop timer", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ need_rollback[0] = 1;
+#if defined (__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ if ((peer_hw_cb->PollTimerStart == KAL_TRUE || peer_SimCard->poll_sim_2s == KAL_TRUE || peer_usim_dcb->poll_sim_2s == KAL_TRUE) && simInterface < 2)
+ {
+ peer_hw_cb->PollTimerStart = KAL_FALSE;
+ peer_SimCard->poll_sim_2s = KAL_FALSE;
+ peer_usim_dcb->poll_sim_2s = KAL_FALSE;
+ need_rollback[1] = 1;
+ }
+#endif
+ }
+
+ if (hw_cb->PollTimerEnd == KAL_FALSE) // Check SW for Poll Timer STATUS, regardless of the timer state
+ {
+ hw_cb->PollTimerEnd = KAL_TRUE;
+ if (status == 0x0000 && hw_cb->PollTimerPluggedOut == KAL_FALSE)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM DRV:%d]real hot plug", simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ hw_cb->PollTimerPluggedOut = KAL_TRUE;
+ need_callBack[0] = 1;
+ #if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ usim_dcb->retry_3v_prefer = KAL_FALSE;
+ #endif
+ #if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ usim_dcb->retry_special_mode_prefer = KAL_FALSE;
+ #endif
+ }
+#if defined (__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)
+ if (status == 0x0000 && peer_hw_cb->PollTimerPluggedOut == KAL_FALSE)
+ {
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM DRV:%d]real hot plug", 1 - simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ peer_hw_cb->PollTimerPluggedOut = KAL_TRUE;
+ need_callBack[1] = 1;
+ #if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ peer_usim_dcb->retry_3v_prefer = KAL_FALSE;
+ #endif
+ #if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ peer_usim_dcb->retry_special_mode_prefer = KAL_FALSE;
+ #endif
+ }
+#endif
+ }
+ kal_give_spinlock(spinlockid_poll_timer);
+
+ if (need_rollback[0] == 1)
+ sim_hot_swap_poll_timer_rollback(application);
+ if (need_rollback[1] == 1)
+ sim_hot_swap_poll_timer_rollback_codeck_peer(1 - application);
+
+ if (need_callBack[0] == 1 && iccHotPlugTable[simInterface].plugOutcb != NULL)
+ iccHotPlugTable[simInterface].plugOutcb(application);
+ if (need_callBack[1] == 1 && iccHotPlugTable[1 - simInterface].plugOutcb != NULL)
+ iccHotPlugTable[1 - simInterface].plugOutcb(1 - application);
+#endif
+#if defined(__ABNORMAL_CARD__)
+ if (status == 0x0000)
+ {
+ usim_set_sim_io_special_mode(simInterface, KAL_FALSE);
+ }
+#endif // #if defined(__ABNORMAL_CARD__)
+ if (txData[1] == 0x88)
+ {
+ auth_end = ust_get_current_time();
+#if !defined(__MAUI_BASIC__)
+ MD_TRC(LOG_SIM_DRV_AVG_AUTH_TIME,hw_cb->simInterface, SIM_PRINT_L1SIM_CMD_TRC125, ust_us_duration(auth_start, auth_end));
+#else
+ DRV_ICC_print_dec(hw_cb, SIM_PRINT_L1SIM_CMD_TRC125, ust_us_duration(auth_start, auth_end), 0, 0, 0, 0);
+#endif
+
+ }
+ if (txData[1] == 0xF2)
+ {
+ status_end = ust_get_current_time();
+ SimCard->status_duration_count++;
+ SimCard->status_duration_sum += status_end - status_start;
+ if (SimCard->status_duration_count == 10)
+ {
+ MD_TRC(LOG_SIM_DRV_AVG_STATUS_TIME,hw_cb->simInterface, SIM_PRINT_L1SIM_CMD_TRC124, SimCard->status_duration_sum, SimCard->status_duration_count);
+ SimCard->status_duration_count = 0;
+ SimCard->status_duration_sum = 0;
+ }
+
+ }
+ return status;
+}
+
+void L1sim_PowerOff_All(SIM_ICC_APPLICATION application)
+{
+ sim_ctrlDriver *simDriver;
+ kal_uint32 simInterface;
+ sim_HW_cb *hw_cb;
+
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+
+ simDriver->addMessage(SIM_AL_ACTION_POWOFF, simInterface, (kal_uint32)kal_get_current_thread_ID(), 0);
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ USIM_low_power_related_setting(hw_cb, USIM_LP_DISABLE | USIM_LP_MASK_NORMAL_VSIM_CURRENT | USIM_LP_MASK_START_SCLK);
+
+ // VSIM lock: To prevent NFC open VSIM again
+#if defined(__LOCK_VSIM__)
+ {
+ sim_nfc_communication req, rsp;
+ req.lock_vsim = KAL_TRUE;
+ rsp.lock_vsim = KAL_FALSE;
+ IPC_RPC_General_Query(IPC_RPC_USIM2NFC_OP, (void *) &req, sizeof(sim_nfc_communication), (void *) &rsp, sizeof(sim_nfc_communication));
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV] vsim lock rsp: %d\n\r", rsp.lock_vsim);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+#endif // #if defined(__LOCK_VSIM__)
+
+ simDriver->powerOff((sim_HW_cb *)(hwCbArray[simInterface]));
+
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_NORMAL_26M | USIM_LP_MASK_REDUCE_VSIM_CURRENT);
+
+ // VSIM unlock
+#if defined(__LOCK_VSIM__)
+ {
+ sim_nfc_communication req, rsp;
+ req.lock_vsim = KAL_FALSE;
+ rsp.lock_vsim = KAL_TRUE;
+ IPC_RPC_General_Query(IPC_RPC_USIM2NFC_OP, (void *) &req, sizeof(sim_nfc_communication), (void *) &rsp, sizeof(sim_nfc_communication));
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV] vsim unlock rsp: %d\n\r", rsp.lock_vsim);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+#endif // #if defined(__LOCK_VSIM__)
+
+#if defined(__ABNORMAL_CARD__)
+ usim_set_sim_io_special_mode(simInterface, KAL_FALSE);
+#endif // #if defined(__ABNORMAL_CARD__)
+
+ simDriver->addMessage(SIM_AL_ACTION_EOC, simInterface, 0, 0);
+ simDriver->EOC((sim_HW_cb *)(hwCbArray[simInterface]));
+
+ sim_releaseOwner(application);
+}
+
+void L1sim_Get_Card_Info_All(sim_info_struct *info, SIM_ICC_APPLICATION application)
+{
+ sim_ctrlDriver *simDriver;
+ kal_uint32 simInterface;
+
+ simInterface = sim_get_logicalNum_from_app(application);
+
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ simDriver->getCardInfo(info, (sim_HW_cb *)(hwCbArray[simInterface]));
+}
+
+void L1sim_Get_Card_Error_Types_Info_All(sim_info_struct *info, SIM_ICC_APPLICATION application)
+{
+ Sim_Card *SimCard;
+ kal_uint32 simInterface;
+
+ simInterface = sim_get_logicalNum_from_app(application);
+
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ /*find out the hooked function table*/
+ SimCard = GET_SIM_CB(simInterface);
+ ASSERT(0 != SimCard);
+
+ info->sim_result = SimCard->result;
+}
+
+void L1sim_Enable_Enhanced_Speed_All(kal_bool enable, SIM_ICC_APPLICATION application)
+{
+ sim_ctrlDriver *simDriver;
+ kal_uint32 simInterface;
+
+
+ ///dbg_print("L1sim_Enable_Enhanced_Speed_All\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ simDriver->enableEnhancedSpeed(enable, (sim_HW_cb *)(hwCbArray[simInterface]));
+}
+
+void L1sim_Select_Prefer_PhyLayer_All(sim_protocol_phy_enum T, SIM_ICC_APPLICATION application)
+{
+ sim_ctrlDriver *simDriver;
+ kal_uint32 simInterface;
+
+ ///dbg_print("L1sim_Select_Prefer_PhyLayer_All\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ simDriver->selectPreferPhyLayer(T, (sim_HW_cb *)(hwCbArray[simInterface]));
+}
+
+kal_bool L1sim_Set_ClockStopMode_All(sim_clock_stop_enum mode, SIM_ICC_APPLICATION application)
+{
+ sim_ctrlDriver *simDriver;
+ kal_bool status;
+ kal_uint32 simInterface;
+ sim_HW_cb *hw_cb;
+
+ // dbg_print("L1sim_Set_ClockStopMode_All\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+ // find out the hooked function table
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ USIM_low_power_related_setting(hw_cb, USIM_LP_DISABLE);
+
+ status = simDriver->setClockStopMode(mode, (sim_HW_cb *)(hwCbArray[simInterface]));
+
+ if (mode & CLOCK_STOP_MSK)
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_NORMAL_26M);
+ else
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE | USIM_LP_MASK_FORCE_ON_26M);
+
+ return status;
+}
+
+/*for specific purpose, SIM task should not call this */
+void sim_releaseOwner(SIM_ICC_APPLICATION application)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 simInterface;
+
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+ usim_dcb = GET_USIM_CB(simInterface);
+ SIM_DEBUG_ASSERT(0 != usim_dcb);
+
+ usim_dcb->ownerTask = 0;
+}
+
+/*following are pure SW query, no matter of different driver solutions*/
+sim_card_speed_type L1sim_Get_CardSpeedType(SIM_ICC_APPLICATION application)
+{
+ Sim_Card *SimCard;
+ kal_uint32 simInterface;
+
+ //dbg_print("L1sim_Get_CardSpeedType\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+ SimCard = GET_SIM_CB(simInterface);
+ SIM_DEBUG_ASSERT(0 != SimCard);
+
+ return SimCard->sim_card_speed;
+}
+
+kal_bool sim_queryGet9000WhenSelect(SIM_ICC_APPLICATION application)
+{
+ Sim_Card *SimCard;
+ kal_uint32 simInterface;
+
+ //dbg_print("[DRV] sim_queryGet9000WhenSelect\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+ SimCard = GET_SIM_CB(simInterface);
+ SIM_DEBUG_ASSERT(0 != SimCard);
+
+ return SimCard->get9000WhenSelect;
+}
+
+void L1sim_Set_Owner_Task(SIM_ICC_APPLICATION application)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 simInterface;
+
+ ///dbg_print("[DRV] sim_set_owner_task\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+ usim_dcb = GET_USIM_CB(simInterface);
+ SIM_DEBUG_ASSERT(0 != usim_dcb);
+ usim_dcb->ownerTask = kal_get_current_thread_ID();
+}
+
+enum{
+ SIM_TRAY_STATUS_UNKOWN,
+ SIM_TRAY_ABSENT,
+ SIM_TRAY_DETECTED,
+};
+void L1sim_Get_Card_Detect_Status(sim_info_struct *info, SIM_ICC_APPLICATION application)
+{
+ kal_uint32 simInterface;
+ sim_HW_cb *hw_cb;
+ DCL_HANDLE gpio_handle;
+ GPIO_CTRL_READ_T readIO;
+ kal_uint32 Sim_Detect_Pin_indate;
+
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if(KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1-simInterface;
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[simInterface]);
+ if(DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ ASSERT(0);
+
+ gpio_handle = DclGPIO_Open(DCL_GPIO, hw_cb->sim_detect_pin_num);
+ DclGPIO_Control(gpio_handle, GPIO_CMD_READ, (DCL_CTRL_DATA_T *)&readIO);
+ Sim_Detect_Pin_indate = readIO.u1IOData;
+ DclGPIO_Close(gpio_handle);
+
+ if(Sim_Detect_Pin_indate == hw_cb->polarity)
+ {
+ info->sim_tray_status = SIM_TRAY_ABSENT;
+
+ }
+ else
+ {
+ if(Sim_Detect_Pin_indate == !(hw_cb->polarity))
+ {
+ info->sim_tray_status = SIM_TRAY_DETECTED;
+
+ }
+ else
+ {
+ info->sim_tray_status = SIM_TRAY_STATUS_UNKOWN;
+
+ }
+ }
+}
+
+void sim_toutTest_al(kal_uint32 toutValue, SIM_ICC_APPLICATION application)
+{
+
+ sim_ctrlDriver *simDriver;
+ kal_uint32 simInterface;
+
+ ///dbg_print("sim_toutTest_al\r\n");
+ simInterface = sim_get_logicalNum_from_app(application);
+
+ if (DRV_SIM_MAX_LOGICAL_INTERFACE <= simInterface)
+ SIM_DEBUG_ASSERT(0);
+
+ if (KAL_TRUE == sim_physicalSlotChanged)
+ simInterface = 1 - simInterface;
+
+
+ /*find out the hooked function table*/
+ simDriver = sim_driverTable[simInterface];
+ SIM_DEBUG_ASSERT(0 != simDriver);
+ simDriver->toutTest(toutValue, (sim_HW_cb *)(hwCbArray[simInterface]));
+
+}
+#endif
+
+#ifdef DCL_SIM_INTERFACE
+/*dcl add new api : 1. fill table*/
+DCL_SIMDriver_t sim_ctrlDriver_All =
+{
+ (DCL_SIM_RST)L1sim_Reset_All,
+ (DCL_SIM_CMD)L1sim_Cmd_All,
+ (DCL_SIM_PWOFF)L1sim_PowerOff_All,
+ (DCL_SIM_GET_CARD_INFO)L1sim_Get_Card_Info_All,
+ (DCL_SIM_GET_CARD_ERROR_TYPES_INFO)L1sim_Get_Card_Error_Types_Info_All,
+ (DCL_SIM_SET_MAX_SPEED)L1sim_Enable_Enhanced_Speed_All,
+ (DCL_SIM_SET_PREFER_PROTOCOL)L1sim_Select_Prefer_PhyLayer_All,
+ (DCL_SIM_SET_CLK_STOP_MODE)L1sim_Set_ClockStopMode_All,
+ (DCL_SIM_TOUT_TEST)sim_toutTest_al,
+ NULL,
+ (DCL_SIM_GAT_CARD_SPEED)L1sim_Get_CardSpeedType,
+ (DCL_SIM_QUERY_GET_9000_WHEN_SELECT)sim_queryGet9000WhenSelect,
+ (DCL_SIM_SET_OWNER_TASK)L1sim_Set_Owner_Task,
+ (DCL_SIM_GET_CARD_DETECT_STATUS)L1sim_Get_Card_Detect_Status
+};
+#endif //DCL_SIM_INTERFACE
+
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
+
+#else //DRV_SIM_OFF
+#include "drv_comm.h"
+
+#ifdef DCL_SIM_INTERFACE
+#include "dcl.h"
+void sim_dummyAPI(void) {}
+DCL_SIMDriver_t sim_ctrlDriver_All =
+{
+ (DCL_SIM_RST)sim_dummyAPI,
+ (DCL_SIM_CMD)sim_dummyAPI,
+ (DCL_SIM_PWOFF)sim_dummyAPI,
+ (DCL_SIM_GET_CARD_INFO)sim_dummyAPI,
+ (DCL_SIM_SET_MAX_SPEED)sim_dummyAPI,
+ (DCL_SIM_SET_PREFER_PROTOCOL)sim_dummyAPI,
+ (DCL_SIM_SET_CLK_STOP_MODE)sim_dummyAPI,
+ NULL,
+ (DCL_SIM_GAT_CARD_SPEED)sim_dummyAPI,
+ (DCL_SIM_QUERY_GET_9000_WHEN_SELECT)sim_dummyAPI
+};
+#endif //DCL_SIM_INTERFACE
+
+#endif //DRV_SIM_OFF
diff --git a/mcu/driver/devdrv/usim/src/icc_switchControl_mtk_0.c b/mcu/driver/devdrv/usim/src/icc_switchControl_mtk_0.c
new file mode 100644
index 0000000..ae37b1e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/src/icc_switchControl_mtk_0.c
@@ -0,0 +1,5979 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * switchControl_mtk_0.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the SIM driver in dual SIM controller (MT6238, MT6235) solution.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+//#include "stack_common.h"
+#include "stack_msgs.h"
+#include "stack_ltlcom.h" /* Task message communiction */
+//RHR#include "syscomp_config.h"
+//RHR#include "task_config.h"
+//RHR#include "stacklib.h"
+#include "drv_comm.h"
+#include "nvram_msgid.h"
+#include "us_timer.h"
+
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#include "reg_base.h"
+#include "sim_drv_trc.h"
+#include "intrCtrl.h"
+
+
+#include "sim_reg_adp.h"
+
+#include "sim_hw_mtk.h"
+#include "sim_al.h"
+
+#include "sim_sw_comm.h"
+#include "sim_drv_SW_API.h"
+#include "drvpdn.h"
+
+#if defined(LPWR_SLIM)
+#include "sleepdrv_interface.h"
+#endif
+
+#ifdef __MTK_TARGET__
+#if (defined(DRV_SIM_ALL_SOLUTION_BUILT) || (defined(DRV_MULTIPLE_SIM) && defined(DRV_2_SIM_CONTROLLER)))
+#if !defined(DRV_SIM_MT6208_SERIES)
+//#ifdef MT6318
+//#include "pmic6318_sw.h"
+//#endif /*MT6318*/
+//RHR#include "init.h"
+
+
+#ifndef __MAUI_BASIC__
+//RHR#include "nvram_user_defs.h"
+#include "nvram_struct.h"
+#endif
+
+#include "sim_mtk.h"
+
+//#include "pwic.h"
+
+//#if defined(MT6223PMU)
+//#include "pmu_sw.h"
+//#endif
+
+#include "sync_data.h"
+
+
+#ifdef SIM_CACHED_SUPPORT
+#include "cache_sw.h"
+#endif
+//#endif
+
+/*RHR*/
+#include "drv_features.h"
+//#include "kal_non_specific_general_types.h"
+#include "string.h"
+#include "sim_nvram_def.h"
+#include "stack_config.h"
+#include "stack_ltlcom.h"
+#include "stdio.h"
+//#include "pmic_features.h"
+#include "kal_trace.h"
+/*RHR*/
+
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+#include "hisr_config.h"
+#else
+static kal_hisrid sim_hisrid = NULL;
+static kal_hisrid sim2_hisrid = NULL;
+#endif
+
+extern kal_uint32 SIM_GetCurrentTime(void);
+#define SIM_NULLBYTE_ISSUE
+#ifdef SIM_NULLBYTE_ISSUE
+/*
+magic1 is an increasing counter, increases when 1) start new command, 2)get SIM timeout, 3)get T0 end
+for case 2 and 3, it means that one of the ends of SIM commands has appeared.
+*/
+//kal_uint32 simMagic1_0, simMagic1_1;
+/*
+magic2 is used to compared with magic1 every time GPT expires. It is set to magic1 in the start of a new command,
+if they were compared equally in GPT timer, we know that we are still waiting for SIM controller's event.
+*/
+//kal_uint32 simMagic2_0, simMagic2_1;
+//kal_uint8 sim_nullByteIssueGPT_0, sim_nullByteIssueNullCount_0, sim_nullByteIssueGPT_1, sim_nullByteIssueNullCount_1;
+//extern kal_bool GPTI_StartItem(kal_uint8 module,kal_uint16 tick,void (*gptimer_func)(void *),void *parameter);
+//extern void GPTI_StopItem(kal_uint8 module);
+//extern kal_uint8 GPTI_GetHandle(kal_uint8 *handle);
+
+extern sim_env SIM_GetCurrentEnv(kal_uint32 simInterface);
+extern void sim_get_card_status(kal_uint32 logicalNum, kal_bool *isRemoved);
+#endif
+
+
+
+extern void pmic6326_ccci_lock(kal_bool lock);
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+extern void SIM_HISR_MT6306(void);
+extern void SIM_HISR2_MT6306(void);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+extern kal_bool sim_connectMT6306;
+#endif
+#endif
+
+/*#if defined(MT6290)
+//the unit of mt6290 is 16etu
+#define SIM_DEFAULT_TOUT_VALUE 0x260
+#define SIM_CMD_TOUT_VALUE 0x1400 //to be updated
+#else*/
+//#define SIM_DEFAULT_TOUT_VALUE 0x983
+//#define SIM_CMD_TOUT_VALUE 0x1400
+//#endif
+
+#define FILE_SWITCHCONTROL0 1
+
+extern kal_uint32 hwCbArray[];
+
+
+//I set the number of element to a fixed value, since this code is for analog-switch solution, I have no power to support more than 2 interface
+//static Sim_Card SimCard_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+
+extern usim_dcb_struct usim_cb[];
+//Sim_Card *SimCard = &SimCard_cb[0];
+//kal_uint8 reset_index;
+//kal_uint8 PTS_data[4];
+
+#if defined(__USIM_DRV__)
+//kal_bool sim_ATR_fail;
+#endif
+
+//static kal_bool PTS_check = KAL_TRUE;
+
+//extern kal_bool sim_workingTaskWaiting; //this is used in Gemini projects, but sim_sw_comm.h used this, so we declared it
+
+static kal_uint32 SIM_ERROR_LINE[MAX_SIM_ERROR_LINE];
+static kal_uint8 SIM_ERROR_LINE_INDEX;
+static kal_bool sim_error_tag;
+
+#ifdef SIM_CACHED_SUPPORT
+extern kal_uint32 sim_uncachedTxBuffer0[], sim_uncachedRxBuffer0[], sim_uncachedTxBuffer1[], sim_uncachedRxBuffer1[];
+#define GET_NCACHEDTX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedTxBuffer0; else p=(kal_uint8 *)sim_uncachedTxBuffer1;}
+#define GET_NCACHEDRX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedRxBuffer0; else p=(kal_uint8 *)sim_uncachedRxBuffer1;}
+#endif
+
+
+void sim_PDNDisable_MTK(sim_HW_cb *hw_cb);
+void sim_PDNEnable_MTK(sim_HW_cb *hw_cb);
+kal_bool OSTD_Infinite_Sleep_Query(void);
+
+/*********************************************************************************************
+*we move this macro from sim_sw_comm.h to here, since we need a distinguish from dual controllers or MT6302.
+*In dual controllers solution, we need to enable interrupt according to simInterface, but in MT6302 solution, we only need to enable SIM's.
+**********************************************************************************************/
+static void sim_assert_update_nvram(void)
+{
+
+#ifndef __MAUI_BASIC__
+ ilm_struct internal_ilm;
+ peer_buff_struct *peer_buffer_ptr;
+ sim_nvram_param_struct* data_stream;
+ nvram_write_req_struct* parm_stream;
+ kal_uint16 data_len;
+
+ parm_stream = (nvram_write_req_struct *)construct_local_para(sizeof(nvram_write_req_struct), TD_CTRL);
+ peer_buffer_ptr = construct_peer_buff(sizeof(SIM_ERROR_LINE), 0, 0, TD_CTRL);
+
+
+
+ data_stream = (sim_nvram_param_struct *)get_peer_buff_pdu(peer_buffer_ptr, &data_len);
+
+ memcpy(data_stream, SIM_ERROR_LINE, sizeof(SIM_ERROR_LINE));
+
+ //data_stream->ptr = SIM_ERROR_LINE;
+ //data_stream->size = sizeof(SIM_ERROR_LINE);
+
+ ((nvram_write_req_struct*) parm_stream)->file_idx = NVRAM_EF_SIM_ASSERT_LID;
+ ((nvram_write_req_struct*) parm_stream)->para = 1;
+
+ //ilm_ptr = allocate_ilm(MOD_SIM);
+ internal_ilm.src_mod_id = MOD_SIM;
+ internal_ilm.msg_id = MSG_ID_NVRAM_WRITE_REQ;
+ internal_ilm.sap_id = DRIVER_PS_SAP;
+ internal_ilm.local_para_ptr = (local_para_struct *)parm_stream;
+ internal_ilm.peer_buff_ptr = (peer_buff_struct *)peer_buffer_ptr;
+ internal_ilm.dest_mod_id = MOD_NVRAM;
+ msg_send_ext_queue(&internal_ilm);
+#endif
+
+}
+
+static void sim_dump_error_line(sim_HW_cb *hw_cb)
+{
+ if (sim_error_tag != KAL_FALSE)
+ {
+ //kal_sprintf(hw_cb->dbgStr, "[SIM_DRV]:I=%d,L=%d,%d,%d,%d", SIM_ERROR_LINE_INDEX, SIM_ERROR_LINE[0], SIM_ERROR_LINE[1], SIM_ERROR_LINE[2], SIM_ERROR_LINE[3]);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_DUMP_ERROR_LINE, SIM_ERROR_LINE_INDEX, SIM_ERROR_LINE[0], SIM_ERROR_LINE[1], SIM_ERROR_LINE[2], SIM_ERROR_LINE[3]);
+ sim_error_tag = KAL_FALSE;
+ sim_assert_update_nvram();
+ }
+}
+
+void SIM_SetEvent_MTK(Sim_Card *SIMCARD, kal_uint8 result, sim_HW_cb *hw_cb);
+static void sim_gpt_timeout_handler(void *parameter)
+{
+ sim_HW_cb *hw_cb;
+ Sim_Card * SimCard;
+
+ hw_cb = (sim_HW_cb *)parameter;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC45, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+
+ SIM_SetEvent_MTK(SimCard, SIM_GPT_TIMEOUT, hw_cb);
+}
+
+void SIM_WaitEvent_MTK(Sim_Card *SIMCARD, kal_uint32 flag, kal_bool unmaskSIMIntr, sim_HW_cb *hw_cb)
+{
+ kal_uint32 event_group;
+
+ SIMCARD->event_state = KAL_TRUE;
+ SIMCARD->EvtFlag = flag;
+ if (KAL_TRUE == unmaskSIMIntr)
+ {
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ }
+
+ DRV_ICC_GPTI_StartItem(SIMCARD->gpt_handle,
+ USIM_GPT_TIMEOUT_PERIOD,
+ sim_gpt_timeout_handler,
+ hw_cb);
+
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ {
+ kal_retrieve_eg_events(SIMCARD->event, flag, KAL_OR_CONSUME, &event_group, KAL_SUSPEND);
+ }
+ else
+ {
+ kal_retrieve_eg_events(SIMCARD->event, flag, KAL_OR_CONSUME, &event_group, 0);
+ }
+
+ sim_dump_error_line(hw_cb);
+ if (SIMCARD->result != SIM_GPT_TIMEOUT)
+ DRV_ICC_GPTI_StopItem(SIMCARD->gpt_handle);
+}
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+void SIM_SetEvent_MTK(Sim_Card *SIMCARD, kal_uint8 result, sim_HW_cb *hw_cb)
+{
+ DRV_ICC_GPTI_StopItem(SIMCARD->gpt_handle);
+ SIMCARD->result = result;
+ SIMCARD->event_state = KAL_FALSE;
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);
+ MO_Sync();
+ if (0 == SIMCARD->EvtFlag)
+ kal_set_eg_events(SIMCARD->event, SIM_EVT_CMD_END, KAL_OR);
+ else
+ kal_set_eg_events(SIMCARD->event, SIMCARD->EvtFlag, KAL_OR);
+
+
+ sim_addMsg(0x12345678, SIMCARD->EvtFlag, __LINE__, drv_get_current_time());
+}
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+void SIM_Reject_MTK(sim_HW_cb *hw_cb)
+{
+ Sim_Card *SimCard;
+
+ SIM_DisAllIntr();
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ Data_Sync_Barrier();
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)
+ {
+ sim_addMsg(SIM_DRIVER_DEACT_SIMD, hw_cb->simInterface, 2, 0);
+ SimCard->State = SIM_PWROFF;
+ //SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_SIMOFF);
+ SIM_FIFO_Flush();
+ SIM_Deactive();
+ Data_Sync_Barrier();
+ while (!(DRV_Reg32(hw_cb->mtk_baseAddr + SIM_ATRSTA_MTK) & 0x0001));
+#if !defined(__FPGA__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_FALSE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_FALSE);
+ }
+#endif
+ }
+ else
+ {
+ if (SimCard->reject_set_event)
+ SIM_SetEvent_MTK(SimCard, SIM_NOREADY, hw_cb);
+ }
+
+ // Do clean up
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, 0x0);
+ SIM_FIFO_Flush();
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, 0xFFFF);
+}
+
+static void sim_assert(kal_uint32 line)
+{
+ sim_error_tag = KAL_TRUE;
+ SIM_ERROR_LINE[SIM_ERROR_LINE_INDEX & (MAX_SIM_ERROR_LINE - 1)] = line;
+ SIM_ERROR_LINE_INDEX++;
+}
+
+
+
+static void SIM_Initialize(kal_uint8 format, kal_uint8 power, sim_HW_cb *hw_cb);
+
+
+static void SIM_L1Reset(sim_HW_cb *hw_cb, kal_bool maskSIMIntr)
+{
+ Sim_Card *SimCard;
+ kal_uint32 t1, t2, log_size = 0;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ SIM_DisAllIntr();
+
+#ifdef SIM_ADDDMA
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+#endif // SIM_ADDDMA
+
+ SIM_FIFO_Flush();
+ // De-activate SIM card
+ if (DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON)
+ {
+ sim_addMsg(SIM_DRIVER_DEACT_SIMD, hw_cb->simInterface, 1, 0);
+ SimCard->State = SIM_WaitRejectDone;
+// DRV_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_SIMOFF | SIM_IRQEN_NATR));
+ DRV_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_NATR));
+ // DRV_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);
+ SIM_Deactive();
+ Data_Sync_Barrier();
+ t2=t1= ust_get_current_time();
+ while (!(DRV_Reg32(hw_cb->mtk_baseAddr + SIM_ATRSTA_MTK) & 0x0001))
+ {
+ t2=ust_get_current_time();
+ if(ust_us_duration(t1,t2)>1000*1000)
+ {
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d][ERR][%s:%d] SIM_DEBUG_ASSERT! %x %x %x %x\n\r", hw_cb->simInterface,__func__,__LINE__,SimCard->State,DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK),DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ SIM_DEBUG_ASSERT(0);
+ }
+ if (t1>t2)
+ t1=ust_get_current_time();
+ }
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC48, SimCard->State, SimCard->result,t1,t2,t2-t1);
+#if !defined(__FPGA__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_FALSE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_FALSE);
+ }
+#endif
+
+ /* Need delay of at least 10ms before next activate operation */
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+
+ if (SimCard->State == SIM_WaitRejectDone)
+ {
+ //dbg_print("%d:SIM_Initialize\n\r", __LINE__);
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+ }
+
+ // since we have do lots actions, if its context is task, there maybe chance that hisr occur before we wait event
+ // to prevent this race condition, if maskSIMIntr is true, we have to disable SIM's interrupt
+ if (KAL_TRUE == maskSIMIntr)
+ {
+ IRQMask(hw_cb->mtk_lisrCode);
+ }
+ }
+ else
+ {
+ // since we have do lots actions, if its context is task, there maybe chance that hisr occur before we wait event
+ // to prevent this race condition, if maskSIMIntr is true, we have to disable SIM's interrupt
+ if (KAL_TRUE == maskSIMIntr)
+ {
+ IRQMask(hw_cb->mtk_lisrCode);
+ }
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC46, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ }
+}
+
+#ifdef NoT0CTRL
+kal_uint8 SIM_CheckSW(kal_uint16 ACK)
+{
+ if ((ACK & 0x00f0) == 0x0060)
+ return KAL_TRUE;
+ if ((ACK & 0x00f0) == 0x0090)
+ return KAL_TRUE;
+
+ return KAL_FALSE;
+}
+#endif /*NoT0CTRL*/
+
+static kal_bool SIM_ResetNoATR(kal_uint8 pow, sim_HW_cb *hw_cb) //For normal case reset
+{
+ //Only enable SIM interrupt
+
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->State = SIM_WAIT_FOR_ATR;
+ SimCard->reset_index = 0;
+ SimCard->Power = pow;
+
+ kal_set_eg_events(SimCard->event, 0, KAL_AND);
+
+ //Deactivate the SIM card
+ SIM_L1Reset(hw_cb, KAL_TRUE);
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (usim_dcb->present == KAL_FALSE)
+ return KAL_FALSE;
+#endif
+
+ SIM_WaitEvent_MTK(SimCard, RST_READY, KAL_TRUE, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC47, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ if (SimCard->result == SIM_SUCCESS)
+ {
+ return KAL_TRUE;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+}
+
+static void SIM_Initialize(kal_uint8 format, kal_uint8 power, sim_HW_cb *hw_cb)
+{
+ kal_uint16 Conf;
+ Sim_Card *SimCard;
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div7;
+#elif defined(SIM_DRV_4_33MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div8;
+#else
+ kal_uint32 clk_div = SIM_BRR_CLK_Div4;
+#endif
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ //tmp = *(volatile kal_uint16 *)0x80140070;
+ //if (tmp != 1)
+ //while(1);
+ SimCard->Data_format = format;
+ SimCard->Power = power;
+#if defined(SIM_DEBUG_INFO)
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->dbgStr, "SIM_Initialize power: %d, format: %d, TS_HSK_ENABLE: %d\n\r", power, format, SimCard->TS_HSK_ENABLE);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ //Setup the SIM control module, SIM_BRR, SIM_CONF
+ //Set SIMCLK = 13M/4, and BAUD RATE = default value(F=372,D=1);
+ DRV_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div372));
+
+ if (format != SIM_direct)
+ {
+ Conf = SIM_CONF_InDirect;
+ }
+ else
+ {
+ Conf = SIM_CONF_Direct;
+ }
+#if 0
+#if defined(__DRV_SIM_NEED_CUSTOM_CONTROL__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif (!defined(__DRV_SIM_SIMIF_CONTROL_VSIM__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#else //configure through SIMIF setting
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef DRV_SIM_VSIM2_ISSUE_76_SERIES
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //DRV_SIM_VSIM2_ISSUE_76_SERIES
+/* under construction !*/
+#endif //configure through SIMIF setting
+#else
+ if (power == SIM_30V)
+ {
+ Conf |= SIM_CONF_SIMSEL;
+#ifdef __FPGA__
+#else
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(0, CLASS_B_30V);
+ }
+ else
+ {
+ DRV_ICC_PMU_setVolt(1, CLASS_B_30V);
+ }
+#endif
+ }
+#ifdef __FPGA__
+#else
+ else
+ {
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(0, CLASS_C_18V);
+ }
+ else
+ {
+ DRV_ICC_PMU_setVolt(1, CLASS_C_18V);
+ }
+ }
+#endif
+#endif
+
+ if (SimCard->TS_HSK_ENABLE == KAL_TRUE)
+ Conf |= (SIM_CONF_TXHSK | SIM_CONF_RXHSK);
+
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, Conf);
+
+ if (SimCard->TS_HSK_ENABLE == KAL_TRUE)
+ {
+ SIM_SetRXRetry(1);
+ SIM_SetTXRetry(1);
+ }
+ else
+ {
+ SIM_SetRXRetry(0);
+ SIM_SetTXRetry(0);
+ }
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ // Set the ATRTout as 9600etu
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+
+ // reset interrupts, flush rx, tx fifo
+ SIM_FIFO_Flush();
+
+ //Set the txfifo and rxfifo tide mark
+ SIM_SetRXTIDE(1, hw_cb);
+
+ //Read Interrupt Status
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ //Interrupt Status of MT6290 is write clear instead
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+
+ SimCard->State = SIM_WAIT_FOR_ATR;
+
+ //Enable Interrupt
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_Normal & ~SIM_IRQEN_RXERR));
+ SimCard->recDataErr = KAL_FALSE;
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if defined(__SIM_ACTIVATION_V2__)
+ if (SimCard->activation_v2 == KAL_TRUE)
+ {
+ DclGPIO_Control(SimCard->gpio_handle_for_SIO, GPIO_CMD_SET_MODE_0, NULL);
+ MO_Sync();
+ }
+#endif
+
+#if defined(__SIM_DRV_SET_OE_BEFOR_PWRON__)
+ SIM_SET_OE_BIT() ;
+#else
+ SIM_CLR_OE_BIT() ;
+#endif
+
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+#endif
+ //activate the SIM card, and activate the SIMCLK
+#if !defined(__FPGA__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_TRUE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_TRUE);
+ }
+#endif
+ sim_addMsg(SIM_DRIVER_ACT_SIMD, hw_cb->simInterface, 1, power);
+ SIM_Active();
+ ////dbg_print("SIM ACtive\r\n");
+#if defined(__SIM_ACTIVATION_V2__)
+ if (SimCard->activation_v2 == KAL_TRUE)
+ {
+ DRV_ICC_GPTI_StopItem(SimCard->gpt_handle_for_SIM_activation);
+ DRV_ICC_GPTI_StartItem(SimCard->gpt_handle_for_SIM_activation, 1, usim_gpt_timeout_handler_for_SIM_activation, hw_cb);
+ }
+#endif
+}
+
+static kal_bool SIM_PTSProcess(kal_uint8 *TxBuffaddr, kal_uint8 Txlength, sim_HW_cb *hw_cb) //Bool lalasun
+{
+ kal_uint8 index;
+ kal_uint8 tmp;
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ kal_set_eg_events(SimCard->event, 0, KAL_AND); //2: NU_AND
+
+#ifdef DRV_DEBUG
+ dbg_print("SIM process PTS..\r\n");
+#endif
+#if defined(__USIM_DRV__)
+#ifdef SIM_ACTIVATE_BY_PTS_ERROR
+ Data_Sync_Barrier();
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON) == 0)
+ {
+ SimCard->sim_ATR_fail = KAL_TRUE;
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC49, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_WaitEvent_MTK(SimCard, RST_READY, KAL_TRUE, hw_cb);
+
+ if (SimCard->result != SIM_SUCCESS)
+ {
+ return KAL_FALSE;
+ }
+ //Got TS, need to wait for all ATR received
+ kal_sleep_task(KAL_TICKS_500_MSEC_REAL);
+ }
+#endif
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK))
+ USIM_CLR_FIFO();
+ if (usim_dcb->reset_mode == USIM_RESET_SPECIFIC && (usim_dcb->TA2 & 0x10) == 0)
+ return KAL_TRUE;
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+#endif
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && SimCard->forceISO == KAL_FALSE)
+ {
+ Txlength = 4;
+ *(TxBuffaddr) = 0xFF;
+ *(TxBuffaddr + 1) = 0x2F;
+ *(TxBuffaddr + 2) = 0xC0;
+ *(TxBuffaddr + 3) = 0x10;
+ }
+#endif
+ /* fix plug out cause this flag set as true, but let next PPS response can't reveice data at Rxtide interrupt */
+ SimCard->timeout = KAL_FALSE;
+
+ for (index = 0; index < Txlength; index++)
+ {
+ SimCard->PTS_data[index] = 0;
+ tmp = *(TxBuffaddr + index);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, tmp);
+ }
+
+ SimCard->State = SIM_PROCESS_PTS;
+
+ SIM_SetRXTIDE(Txlength, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_Normal);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ return KAL_FALSE;
+#endif
+ // fix plug out cause this flag set as true, but let next PPS response can't reveice data at Rxtide interrupt
+ SimCard->timeout = KAL_FALSE;
+ SIM_WaitEvent_MTK(SimCard, PTS_END, KAL_FALSE, hw_cb);
+
+ if ((SimCard->recDataErr == KAL_TRUE)
+ || (SimCard->result == SIM_INIPTSERR))
+ {
+#ifndef __MAUI_BASIC__
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__, SimCard->recDataErr, drv_get_current_time(), *TxBuffaddr, *(TxBuffaddr + 1), *(TxBuffaddr + 2), *(TxBuffaddr + 3));
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+#endif
+ SimCard->recDataErr = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC50, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ DRV_ICC_print_err_msg(hw_cb, "SIM_INIPTSERR");
+ return KAL_FALSE;
+ }
+
+ for (index = 0; index < Txlength; index++)
+ {
+ if (SimCard->PTS_data[index] != *(TxBuffaddr + index))
+ {
+#ifndef __MAUI_BASIC__
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__, *TxBuffaddr, *(TxBuffaddr + 1), *(TxBuffaddr + 2), *(TxBuffaddr + 3), SimCard->PTS_data[index], index);
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC51, SimCard->PTS_data[0], SimCard->PTS_data[1], SimCard->PTS_data[2], SimCard->PTS_data[3], 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC51, *(TxBuffaddr + 0), *(TxBuffaddr + 1), *(TxBuffaddr + 2), *(TxBuffaddr + 3), 0);
+
+ SimCard->result = SIM_PTS_RX_INVALID;
+ return KAL_FALSE;
+ }
+ }
+ // Some high speed SIM card after clock rate change have to wait a while to
+ // to receive the first command.
+ if (SimCard->PTS_data[1] != 0x00)
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+
+ return KAL_TRUE;
+}
+
+static kal_bool SIM_ProcessATRData(sim_HW_cb *hw_cb)
+{
+ kal_uint8 index;
+ kal_uint16 tmp, tmp1, Fi = 372;
+ kal_uint8 ptsdata[4];
+ // TOUT is an uint32 value
+ kal_uint32 WWT = 0;
+ kal_uint8 Dvalue = 1;
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+ kal_char *p;
+ kal_uint32 i, log_size = 0;
+
+ // fix build warning
+ // WWT = WWT;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+#if defined(__USIM_DRV__)
+ if (SimCard->sim_ATR_fail)
+ {
+ SIM_WaitEvent_MTK(SimCard, ATR_END, KAL_FALSE, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC52, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ SimCard->recDataErr = KAL_FALSE;
+ return KAL_FALSE;
+ }
+
+ DRV_ICC_print_str("[SIM_DRV]Bad Card Recovery Success.");
+
+ /* For DHL Limitation, Log length should <= 116bytes */
+ p = hw_cb->dbgStr;
+ log_size = kal_sprintf(p, "[SIM_DRV:%d]SIM ATR= ", hw_cb->simInterface);
+ p += strlen(p);
+ for (i = 0; i < SimCard->recDataLen; i++)
+ {
+ log_size += kal_sprintf(p, "%02X", SimCard->recData[i]);
+ p += 2;
+ }
+
+#ifdef ATEST_DRV_ENABLE
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ATR,hw_cb->dbgStr);
+#endif
+ }
+ else
+ {
+ kal_mem_cpy(SimCard->recData, usim_dcb->ATR_data, usim_dcb->ATR_index);
+ }
+#else
+ SIM_WaitEvent_MTK(SimCard, ATR_END, KAL_FALSE, hw_cb);
+
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ SimCard->recDataErr = KAL_FALSE;
+ return KAL_FALSE;
+ }
+#endif // __USIM_DRV__
+
+ index = 2;
+ if (SimCard->recData[1] & 0x00f0)
+ {
+ if (SimCard->recData[1] & TAMask)
+ {
+ tmp = SimCard->recData[index]; // TA1
+ index++;
+ // dbg_print("TA1=%x\r\n",tmp);
+ // default value of Fi, Di, or TA2 with bit5==1
+ if ((tmp == 0x0011) || (tmp == 0x0001) || (usim_dcb->reset_mode == USIM_RESET_SPECIFIC && (usim_dcb->TA2 & 0x10)))
+ {
+ // Don't process ATR data!!
+ SimCard->State = SIM_PROCESSCMD;
+ SIMCmdInit(); // if not defined NoT0CTRL, enable T0 controller
+#ifdef NoT0CTRL
+ SimCard->cmdState = SIMD_CmdIdle;
+#endif
+ // Use 372/1 as default TOUT
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ // SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ return KAL_TRUE;
+ }
+ else
+ {
+ // Set default Fi as 512
+ Fi = 512;
+ switch (tmp)
+ {
+ case 0x0094: // F = 512,D=8
+ SimCard->sim_card_speed = sim_card_enhance_speed_64;
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ // Use 372/1 as default TOUT
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 8;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x94;
+ ptsdata[3] = 0x7b;
+ SimCard->Speed = Speed64;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div64);
+ SimCard->TOUT_Factor = 8; //hw-specific
+ /* calc 512/8 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 8, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+
+ case 0x0095: //F=512,D=16
+ SimCard->sim_card_speed = sim_card_enhance_speed_32;
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 16;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x95;
+ ptsdata[3] = 0x7a;
+ SimCard->Speed = Speed32;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div32);
+ SimCard->TOUT_Factor = 16;
+ /* calc 512/16 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 16, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+ case 0x0096: //F=512,D=32
+ SimCard->sim_card_speed = sim_card_enhance_speed_16;
+
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 32;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x96;
+ ptsdata[3] = 0x79;
+ SimCard->Speed = Speed16;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div16);
+ SimCard->TOUT_Factor = 32;
+ /* calc 512/32 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 32, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+ case 0x0097: //F=512,D=64
+ SimCard->sim_card_speed = sim_card_enhance_speed_8;
+
+ if (!SimCard->PTS_check)
+ {
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ else
+ {
+ Dvalue = 64;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x10;
+ ptsdata[2] = 0x97;
+ ptsdata[3] = 0x78;
+ SimCard->Speed = Speed8;
+
+ if (!SIM_PTSProcess(ptsdata, 4, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ SIM_SetData((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_BRR_ETUMSK, SIM_BRR_BAUD_Div8);
+ SimCard->TOUT_Factor = 64;
+ /* calc 512/64 TOUT value */
+ DRV_ICC_Calc_WWT(Fi, 64, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+
+ //SimCard->TOUTValue = SimCard->TOUT_Factor*SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ }
+ break;
+
+ default: //F=372,D=1
+ Dvalue = 1;
+ ptsdata[0] = 0xff;
+ ptsdata[1] = 0x00;
+ ptsdata[2] = 0xff;
+ if (!SIM_PTSProcess(ptsdata, 3, hw_cb))
+ {
+ return KAL_FALSE;
+ }
+ /* Use 372/1 as default TOUT */
+ Fi = 372;
+ DRV_ICC_Calc_WWT(Fi, 1, 10, &WWT);
+
+ SimCard->TOUTValue = WWT >> 2;
+ //SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ break;
+ }
+ }
+ } /*if (SimCard->recData[1] & TAMask)*/
+
+ SimCard->Fi = Fi;
+
+
+ if (SimCard->recData[1] & TBMask)
+ {
+ tmp = SimCard->recData[index];
+ ////dbg_print("TB1=%x\r\n",tmp);
+ index++;
+ }
+ if (SimCard->recData[1] & TCMask)
+ {
+ tmp = SimCard->recData[index];
+ ////dbg_print("TC1=%x\r\n",tmp);
+ if (tmp != 0xff && tmp != 0x00)
+ {
+ return KAL_FALSE;
+ }
+ index++;
+ }
+
+ if (SimCard->recData[1] & TDMask)
+ {
+ tmp = SimCard->recData[index]; // TD1
+ index++;
+ // dbg_print("TD1=%x\r\n",tmp);
+ if (tmp & TCMask) // TC2 is obtain
+ {
+ if (tmp & TAMask)
+ {
+ tmp1 = SimCard->recData[index];
+ // dbg_print("TA2=%x\r\n",tmp1);
+ index++;
+ }
+ if (tmp & TBMask)
+ {
+ tmp1 = SimCard->recData[index];
+ // dbg_print("TB2=%x\r\n",tmp1);
+ index++;
+ }
+ if (tmp & TCMask) // TC2
+ {
+ tmp1 = SimCard->recData[index];
+ // dbg_print("TC2=%x\r\n",tmp1);
+ // TOUT is an uint32 value
+ // TOUT = (960*Dvalue);
+ // TOUT = (TOUT*tmp1)/4; // (/4)is hw-specific
+ index++;
+ // SimCard->TOUTValue = TOUT+8;
+ // dbg_print("TOUT=%x\r\n",TOUT);
+ SimCard->TC2Present = KAL_TRUE;
+ // Calc 512/Dvalue TOUT value
+ DRV_ICC_Calc_WWT(Fi, Dvalue, tmp1, &WWT);
+ SimCard->TOUTValue = WWT >> 2;
+ // SimCard->TOUTValue = SIM_CMD_TOUT_VALUE;
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+//#ifdef SIM_TOUT_REG_V2
+// if (TOUT < 0xffffff){
+//#ifdef SIM_TOUT_REG_V3
+// SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), TOUT/4);
+//#else
+// SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), TOUT);
+//#endif
+// }
+// else
+// SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffffff);
+//#else
+// if (TOUT < 0xffff)
+// SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), TOUT);
+// else
+// SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffff);
+//#endif
+ }
+ }
+ } // if (SimCard->recData[1] & TDMask)
+ } // if (SimCard->recData[1] & 0x00f0)
+ SimCard->State = SIM_PROCESSCMD;
+ SIMCmdInit();
+#ifdef NoT0CTRL
+ SimCard->cmdState = SIMD_CmdIdle;
+#endif //NoT0CTRL
+
+ return KAL_TRUE;
+}
+
+static void SIM_Cmdhandler(sim_HW_cb *hw_cb)
+{
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+#ifndef SIM_ADDDMA
+ while (SIM_FIFO_GetLev())
+ {
+ *(SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK));
+ SimCard->recDataLen++;
+ }
+#endif // SIM_ADDDMA
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+
+ return;
+}
+
+#ifndef SIM_ADDDMA
+void SIM_Txhandler(sim_HW_cb *hw_cb)
+{
+#ifdef NoT0CTRL
+ kal_uint8 index;
+ kal_uint16 reslen;
+ reslen = SimCard->txsize - SimCard->txindex;
+ if (reslen <= 15)
+ {
+ for (index = 0; index < reslen; index++)
+ {
+ SIM_WriteReg(SIM_DATA, *(SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_SetRXTIDE(2);
+ SimCard->cmdState = SIM_WaitProcByte;
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ }
+ else
+ {
+ for (index = 0; index < 15; index++)
+ {
+ SIM_WriteReg(SIM_DATA, *(SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_SetTXTIDE(0);
+ SIM_WriteReg(SIM_IRQEN, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ }
+ return;
+#else /*NoT0CTRL*/
+ kal_uint8 index;
+ kal_uint16 reslen;
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+
+ reslen = SimCard->txsize - SimCard->txindex;
+ if (reslen <= 15)
+ {
+ for (index = 0; index < reslen; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, *(SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDNormal);
+ }
+ else
+ {
+ for (index = 0; index < 15; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, *(SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ }
+ SIM_SetTXTIDE(0, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ }
+#endif /*NoT0CTRL*/
+}
+#endif /*SIM_ADDDMA*/
+
+static void SIM_Rxhandler(kal_uint16 sim_int, sim_HW_cb *hw_cb)
+{
+ kal_uint16 TS;
+ kal_uint8 index;
+ Sim_Card *SimCard;
+ kal_uint32 log_size = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ if (SimCard->State == SIM_WAIT_FOR_ATR)
+ {
+ TS = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+
+ if ((TS == 0x003f) || (TS == 0x003b))
+ {
+ SimCard->State = SIM_PROCESS_ATR;
+
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK | SIM_CONF_RXHSK | SIM_CONF_TOUTEN));
+
+ /* *(volatile kal_uint16 *)SIM_CONF |= SIM_CONF_TOUTEN; */
+ SIM_SetRXTIDE(12, hw_cb);
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ SimCard->recData[0] = TS;
+ SimCard->recDataLen = 1;
+
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+ SimCard->EvtFlag = ATR_END;
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_Normal);
+ }
+ else
+ {
+ SimCard->reset_index++; //Change format!!, don't change power
+ if (SimCard->reset_index > 1)
+ {
+ SimCard->reset_index = 0;
+ SIM_SetEvent_MTK(SimCard, SIM_CARDERR, hw_cb);
+ SIM_ASSERT(0);
+ /* fix build warning */
+ sim_assert(0);
+ }
+ else
+ {
+ if (SimCard->Data_format == SIM_indirect)
+ {
+ SimCard->Data_format = SIM_direct;
+ SIM_L1Reset(hw_cb, KAL_FALSE);
+ }
+ else
+ {
+ SimCard->Data_format = SIM_indirect;
+ SIM_L1Reset(hw_cb, KAL_FALSE);
+ }
+ }
+ }
+ return;
+ }
+
+ if (SimCard->State == SIM_PROCESS_ATR)
+ {
+ while (1)
+ {
+ if (SIM_FIFO_GetLev())
+ {
+ if (40 <= SimCard->recDataLen)
+ {
+ sim_addMsg(0x20080213, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK));
+
+#ifdef SIM_REMOVE_ATR_ASSERT
+ SIM_StartFaltalReport(hw_cb);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__, 0, SimCard->State, SimCard->result, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+
+ return;
+#else
+ SIM_DEBUG_ASSERT(0);
+#endif
+ }
+ SimCard->recData[SimCard->recDataLen] = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ SimCard->recDataLen++;
+ }
+ else
+ {
+ if (sim_int & SIM_STS_TOUT)
+ {
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+ }
+ break;
+ }
+ }
+ return;
+ }
+
+ if (SimCard->State == SIM_PROCESS_PTS)
+ {
+ index = 0;
+ while (KAL_TRUE)
+ {
+ kal_uint8 ch;
+ ch = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ if (index < PPS_LEN)
+ {
+ /* to avoid overflow other members of SimCard_cb */
+ SimCard->PTS_data[index] = ch;
+ }
+ index++;
+ if (SIM_FIFO_GetLev() == 0)
+ {
+ if (index > PPS_LEN)
+ {
+ /* received too many data when processing PTS */
+ sim_addMsg(0x20140415, index, SimCard->recDataErr, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK));
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "Too many PTS:%d", index);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+ }
+ if (SimCard->recDataErr == KAL_FALSE)
+ {
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+ }
+ else
+ {
+ /* SetEvent should be called when handling TOUT */
+ }
+ break;
+ }
+ }
+ SIM_DisAllIntr();
+ return;
+ }
+
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+#ifdef SIM_ADDDMA
+ ////dbg_print("something error\r\n");
+#else /*SIM_ADDDMA*/
+#ifdef NoT0CTRL
+ {
+ kal_uint16 ACK;
+ while (SIM_FIFO_GetLev())
+ {
+ if (SimCard->cmdState == SIM_WaitProcByte)
+ {
+ ACK = SIM_Reg(SIM_DATA);
+ if ((ACK == SimCard->INS) || (ACK == (SimCard->INS + 1))) //ACK
+ {
+ if (SimCard->txsize != 5)
+ {
+ /*Trx command*/
+ SIM_WriteReg(SIM_DATA, *(SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ SIM_SetTXTIDE(0);
+ SIM_WriteReg(SIM_IRQEN, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ SimCard->cmdState = SIM_AckDataState;
+ return;
+ }
+ else
+ {
+ SIM_SetTXTIDE(0xffff);
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ SimCard->cmdState = SIM_AckDataState;
+ continue;
+ }
+ }
+
+ if ((ACK == (~SimCard->INS & 0x00ff)) || (ACK == (~(SimCard->INS + 1) & 0x00ff))) ///NACK
+ {
+ if (SimCard->txsize != 5)
+ {
+ SIM_WriteReg(SIM_DATA, *(SimCard->txbuffer + SimCard->txindex));
+ SimCard->txindex++;
+ SIM_SetRXTIDE(1);
+ SimCard->cmdState = SIM_WaitProcByte;
+ /*Trx command*/
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ return;
+ }
+ else
+ {
+ SIM_SetTXTIDE(0xffff);
+ SimCard->cmdState = SIM_NAckDataState;
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ }
+ continue;
+ }
+
+ if (ACK == 0x60) //ACK
+ {
+ continue;
+ }
+ if (SIM_CheckSW(ACK)) //ACK
+ {
+ SimCard->SW1 = (kal_uint8)ACK;
+ SIM_SetRXTIDE(1);
+ SimCard->recDataLen++;
+ SimCard->cmdState = SIM_WaitSWByte;
+ continue;
+ }
+ }
+
+ if (SimCard->cmdState == SIM_WaitSWByte)
+ {
+ SimCard->SW2 = (kal_uint8)SIM_Reg(SIM_DATA);
+ /*SimCard->recDataLen++;*/
+ SimCard->recDataLen--;
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+ return;
+ }
+
+ if (SimCard->cmdState == SIM_AckDataState)
+ {
+ *(SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg(SIM_DATA);
+ SimCard->recDataLen++;
+ if (SimCard->recsize == SimCard->recDataLen)
+ {
+ SimCard->cmdState = SIM_WaitProcByte;
+ }
+ continue;
+ }
+
+ if (SimCard->cmdState == SIM_NAckDataState)
+ {
+ *(SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg(SIM_DATA);
+ SimCard->recDataLen++;
+ SimCard->cmdState = SIM_WaitProcByte;
+ continue;
+ }
+ } /*while(SIM_FIFO_GetLev())*/
+ if (SimCard->txsize == 5)
+ {
+ if ((SimCard->recsize + 2 - SimCard->recDataLen) > 15)
+ {
+ SIM_SetRXTIDE(CMD_RECBUFSIZE - 8);
+ }
+ else
+ {
+ SIM_SetRXTIDE(SimCard->recsize + 2 - SimCard->recDataLen);
+ }
+
+ SIM_WriteReg(SIM_IRQEN, SIM_IRQEN_CMDNormal);
+ }
+ }
+#else /*NoT0CTRL*/
+ while (SIM_FIFO_GetLev())
+ {
+ *(SimCard->rxbuffer + SimCard->recDataLen) = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ SimCard->recDataLen++;
+ }
+#endif /*NoT0CTRL*/
+#endif /*SIM_ADDDMA*/
+ return;
+ }
+}
+
+void SIM_HISR_Multiple(void)
+{
+ kal_uint16 sim_int;
+ Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+
+ /*logical SIM 1 not exactly work on physical SIM1 interface, we only know interrrupt comes from SIM1, have to find its logical */
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(0)]);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitISR = KAL_TRUE;
+ Data_Sync_Barrier();
+ kal_give_spinlock(hw_cb->spinlockid);
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306)
+ {
+#endif
+ SIM_HISR_MT6306();
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+ return;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ Data_Sync_Barrier();
+ sim_int = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, sim_int);
+#if defined(ATEST_DRV_ENABLE)
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "SIM_int:%x IRQEN:%x\n\r", sim_int, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_HISR,hw_cb->simInterface, sim_int, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),SimCard->State);
+#endif
+
+ sim_addMsg(SIM_INT_SIM, 0, sim_int, SimCard->State);
+
+ if (SimCard->previous_state == SIM_WAIT_FOR_ATR || SimCard->previous_state == SIM_PROCESS_ATR)
+ {
+ SimCard->previous_state = SimCard->State;
+ SimCard->atr_count++;
+ if (SimCard->atr_count > 40)
+ {
+ SIM_DisAllIntr();
+ SIM_Reject_MTK(hw_cb);
+ SimCard->atr_count = 0;
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ DRV_ICC_print_str("[SIM DRV]SIM1 card send too many ATR data\n\r");
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+ return;
+ }
+ }
+ else
+ {
+ SimCard->previous_state = SimCard->State;
+ SimCard->atr_count = 0;
+ }
+
+#if !defined(ATEST_DRV_ENABLE)
+ if (sim_int == 0xa)
+ {
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_fifo(hw_cb);
+ }
+#endif
+ if (sim_int & SIM_STS_TXERR)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "SIM_STS_TXERR");
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SimCard->State = SIM_SERIOUSERR;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x7, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else
+ {
+ SIM_Reject_MTK(hw_cb);
+ SIM_ASSERT(0);
+ // SIM_SetEvent_MTK(SimCard,SIM_INIPTSERR,hw_cb);
+ }
+ }
+
+ if (sim_int & SIM_STS_TX)
+ {
+ //dbg_print("[DRV] SIM_STS_TX\r\n");
+ //SIM_DisIntr(SIM_IRQEN_TX);
+#ifdef SIM_ADDDMA
+ ////dbg_print("something error\r\n");
+#else /*SIM_ADDDMA*/
+ SIM_Txhandler(hw_cb); /* Only used for no DMA */
+#endif /*SIM_ADDDMA*/
+ }
+
+ if (sim_int & SIM_STS_TOUT)
+ {
+ //dbg_print("703SIM_STS_TOUT\r\n");
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x8, SimCard->State, drv_get_current_time(), SimCard->cmdState, hw_cb->simInterface);
+
+ if (SimCard->State == SIM_WAIT_FOR_ATR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC54, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_INIPTSERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+
+ if (SimCard->State == SIM_PROCESS_ATR)
+ {
+ SIM_Rxhandler(sim_int, hw_cb);
+ }
+
+ if (SimCard->State == SIM_PROCESS_PTS)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC55, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_INIPTSERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC56, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SimCard->EvtFlag, hw_cb->simInterface, SimCard->result, SimCard->recDataErr, __LINE__);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SIM_Reg(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDCTRRx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDC0Rx), 0, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else
+ {
+ switch (SimCard->cmdState)
+ {
+ case SIM_ProcessClk:
+ SimCard->EvtFlag = CLK_PROC;
+ SIM_SetEvent_MTK(SimCard, SIM_CLKPROC, hw_cb);
+ break;
+ case SIM_StopClk:
+ if (SimCard->clkStop)
+ {
+ SIM_Idle_MTK(SimCard->clkStopLevel, hw_cb);
+#ifndef __DRV_SIM_REG_ON_PDN_V2__
+ // controller's clock must now stopped, verify it
+ Data_Sync_Barrier();
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & 0x2) != 0x2)
+ SIM_DEBUG_ASSERT(0);
+#endif
+ }
+ SimCard->t_debug[5] = ust_get_current_time();
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE);
+ break;
+ default: /*normal command case*/
+#ifdef NoT0CTRL
+ if (SimCard->cmdState == SIM_WaitProcByte)
+ {
+ kal_uint8 ACK;
+ kal_uint8 Error;
+ Error = KAL_TRUE;
+ while (SIM_FIFO_GetLev())
+ {
+ ACK = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ if (ACK == 0x60) //NULL
+ {
+ continue;
+ }
+ if (SIM_CheckSW(ACK)) //ACK
+ {
+ SimCard->SW1 = ACK;
+ SimCard->SW2 = (kal_uint8)SIM_Reg(SIM_DATA);
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+ Error = KAL_FALSE;
+ }
+ else
+ {
+ break;
+ }
+ }
+ if (Error)
+ {
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x9, 1, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ SIM_ASSERT(0);
+ }
+#else /*NoT0CTRL*/
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->simMagic1 ++;
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x9, 0, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_ASSERT(0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+#endif /*NoT0CTRL*/
+ break;
+ }/*endof switch*/
+ }
+ }/*if (SimCard->State == SIM_PROCESSCMD)*/
+
+ if (SimCard->State == SIM_SERIOUSERR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC57, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTXERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ SIM_DisAllIntr();
+ }
+
+ if (sim_int & SIM_STS_OV)
+ {
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC56, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SimCard->EvtFlag, hw_cb->simInterface, SimCard->result, SimCard->recDataErr, __LINE__);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SIM_Reg(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDCTRRx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDC0Rx), 0, 0);
+#endif
+ DRV_ICC_print_str("[DRV] SIM_STS_OV\r\n");
+ SimCard->recDataErr = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x4, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetTOUT(0x4, hw_cb); // set TOUT ASAP
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard, SIM_OVERRUN, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if (sim_int & SIM_STS_RXERR)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "SIM_STS_RXERR");
+ SimCard->recDataErr = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x6, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetTOUT(0x4, hw_cb); // set TOUT ASAP
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else if(SimCard->State == SIM_PROCESS_PTS)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard,SIM_PTS_RX_INVALID,hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if (sim_int & SIM_STS_RX)
+ {
+ //dbg_print("[DRV] SIM_STS_RX\r\n");
+ if (SimCard->timeout != KAL_TRUE)
+ SIM_Rxhandler(sim_int, hw_cb);
+ }
+
+ if ((sim_int & SIM_IRQEN_T0END) && (SimCard->State == SIM_PROCESSCMD))
+ {
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->simMagic1 ++;
+#endif
+ //dbg_print("[DRV] SIM_IRQEN_T0END\r\n");
+ SIM_Cmdhandler(hw_cb);
+ SIM_DisAllIntr();
+ }
+
+ if (sim_int & SIM_STS_NATR && (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK) & SIM_IRQEN_NATR))
+ {
+ DRV_ICC_print_err_msg(hw_cb, "No ATR");
+ SIM_DisAllIntr();
+ if (SimCard->SIM_ENV == ME_18V_30V)
+ {
+ if (SimCard->Power == SimCard->initialPower)
+ {
+ if (SimCard->Power != SIM_30V)
+ {
+ SimCard->Power = SIM_30V;
+ }
+ else
+ {
+ SimCard->Power = SIM_18V;
+ }
+ SIM_L1Reset(hw_cb, KAL_FALSE);
+ }
+ else
+ {
+ SIM_Reject_MTK(hw_cb);
+ }
+ }
+ else
+ {
+ SIM_Reject_MTK(hw_cb);
+ }
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, SimCard->SIM_ENV, SimCard->Power, SimCard->Data_format, 0, 0x1014);
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ SIM_SetEvent_MTK(SimCard, SIM_NO_ATR, hw_cb);
+ }
+
+ if (sim_int & SIM_STS_SIMOFF)
+ {
+ // dbg_print("[DRV] SIM_STS_SIMOFF\r\n");
+ SIM_DisAllIntr();
+
+ if (SimCard->State == SIM_PWROFF)
+ {
+ if (SimCard->reject_set_event)
+ {
+ SIM_SetEvent_MTK(SimCard, SIM_NOREADY, hw_cb);
+ //mask by mtk04122
+ //SIM_ASSERT(0);
+ }
+ }
+ else
+ {
+ if (SimCard->State == SIM_WaitRejectDone)
+ {
+#if defined(__FPGA__)
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+#endif // #if defined(__FPGA__)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC58, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ }
+ else
+ {
+ SIM_ASSERT(0);
+ }
+
+ }
+ }
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+}
+
+
+void SIM_HISR2_Multiple(void)
+{
+ kal_uint16 sim_int;
+ Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+
+ /*logical SIM 1 not exactly work on physical SIM1 interface, we only know interrrupt comes from SIM1, have to find its logical */
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(1)]);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitISR = KAL_TRUE;
+ Data_Sync_Barrier();
+ kal_give_spinlock(hw_cb->spinlockid);
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306)
+ {
+#endif
+ SIM_HISR2_MT6306();
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+ return;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ Data_Sync_Barrier();
+ sim_int = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, sim_int);
+#if defined(ATEST_DRV_ENABLE)
+ kal_uint32 log_size = 0;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "SIM_int:%x IRQEN:%x\n\r", sim_int, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_HISR,hw_cb->simInterface, sim_int, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),SimCard->State);
+#endif
+
+
+ sim_addMsg(SIM_INT_SIM, 1, sim_int, SimCard->State);
+ ////dbg_print("sim_int=%x\r\n",sim_int);
+
+ if (SimCard->previous_state == SIM_WAIT_FOR_ATR || SimCard->previous_state == SIM_PROCESS_ATR)
+ {
+ SimCard->previous_state = SimCard->State;
+ SimCard->atr_count++;
+ if (SimCard->atr_count > 40)
+ {
+ SIM_DisAllIntr();
+ SIM_Reject_MTK(hw_cb);
+ SimCard->atr_count = 0;
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ DRV_ICC_print_str("[SIM DRV]SIM2 card send too many ATR data\n\r");
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+ return;
+ }
+ }
+ else
+ {
+ SimCard->previous_state = SimCard->State;
+ SimCard->atr_count = 0;
+ }
+
+#if !defined(ATEST_DRV_ENABLE)
+ if (sim_int == 0xa)
+ {
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_fifo(hw_cb);
+ }
+#endif
+ if (sim_int & SIM_STS_TXERR)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "SIM_STS_TXERR");
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SimCard->State = SIM_SERIOUSERR;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x7, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else
+ {
+ SIM_Reject_MTK(hw_cb);
+ SIM_ASSERT(0);
+ // SIM_SetEvent_MTK(SimCard,SIM_INIPTSERR,hw_cb);
+ }
+ }
+
+ if (sim_int & SIM_STS_TX)
+ {
+ ////dbg_print("SIM_STS_TX\r\n");
+ //SIM_DisIntr(SIM_IRQEN_TX);
+#ifdef SIM_ADDDMA
+ ////dbg_print("something error\r\n");
+#else /*SIM_ADDDMA*/
+ SIM_Txhandler(hw_cb); /* Only used for no DMA */
+#endif /*SIM_ADDDMA*/
+ }
+
+ if (sim_int & SIM_STS_TOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x8, SimCard->State, drv_get_current_time(), SimCard->cmdState, hw_cb->simInterface);
+ //dbg_print("703SIM_STS_TOUT\r\n");
+ if (SimCard->State == SIM_WAIT_FOR_ATR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC54, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_INIPTSERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+
+ if (SimCard->State == SIM_PROCESS_ATR)
+ {
+ SIM_Rxhandler(sim_int, hw_cb);
+ }
+
+ if (SimCard->State == SIM_PROCESS_PTS)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC55, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_INIPTSERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ if (SimCard->recDataErr == KAL_TRUE)
+ {
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC56, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SimCard->EvtFlag, hw_cb->simInterface, SimCard->result, SimCard->recDataErr, __LINE__);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SIM_Reg(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDCTRRx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDC0Rx), 0, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else
+ {
+ switch (SimCard->cmdState)
+ {
+ case SIM_ProcessClk:
+ SimCard->EvtFlag = CLK_PROC;
+ SIM_SetEvent_MTK(SimCard, SIM_CLKPROC, hw_cb);
+ break;
+ case SIM_StopClk:
+ if (SimCard->clkStop)
+ {
+ SIM_Idle_MTK(SimCard->clkStopLevel, hw_cb);
+#ifndef __DRV_SIM_REG_ON_PDN_V2__
+ // controller's clock must now stopped, verify it
+ Data_Sync_Barrier();
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & 0x2) != 0x2)
+ SIM_DEBUG_ASSERT(0);
+#endif
+ }
+ SimCard->t_debug[5] = ust_get_current_time();
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE);
+ break;
+
+ default: /*normal command case*/
+#ifdef NoT0CTRL
+ if (SimCard->cmdState == SIM_WaitProcByte)
+ {
+ kal_uint8 ACK;
+ kal_uint8 Error;
+ Error = KAL_TRUE;
+ while (SIM_FIFO_GetLev())
+ {
+ ACK = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ if (ACK == 0x60) //NULL
+ {
+ continue;
+ }
+ if (SIM_CheckSW(ACK)) //ACK
+ {
+ SimCard->SW1 = ACK;
+ SimCard->SW2 = (kal_uint8)SIM_Reg(SIM_DATA);
+ SIM_SetEvent_MTK(SimCard, SIM_SUCCESS, hw_cb);
+ Error = KAL_FALSE;
+ }
+ else
+ {
+ break;
+ }
+ }
+ if (Error)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x9, 1, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+ else
+ {
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+ SIM_ASSERT(0);
+ }
+#else /*NoT0CTRL*/
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->simMagic1 ++;
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x9, 0, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_ASSERT(0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTOUT, hw_cb);
+#endif /*NoT0CTRL*/
+ break;
+ }/*endof switch*/
+ }
+ }/*if (SimCard->State == SIM_PROCESSCMD)*/
+
+ if (SimCard->State == SIM_SERIOUSERR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC57, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ SIM_SetEvent_MTK(SimCard, SIM_CMDTXERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ SIM_DisAllIntr();
+ }
+
+ if (sim_int & SIM_STS_RX)
+ {
+ //dbg_print("SIM_STS_RX\r\n");
+ if (SimCard->timeout != KAL_TRUE)
+ SIM_Rxhandler(sim_int, hw_cb);
+ }
+
+ if (sim_int & SIM_STS_OV)
+ {
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC56, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SimCard->EvtFlag, hw_cb->simInterface, SimCard->result, SimCard->recDataErr, __LINE__);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC56, SIM_Reg(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDCTRRx), SIM_Reg(SimCard->dma_config.ADDR_HDMA_HDC0Rx), 0, 0);
+#endif
+ DRV_ICC_print_str("SIM_STS_OV\r\n");
+ SimCard->recDataErr = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x4, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetTOUT(0x4, hw_cb); // set TOUT ASAP
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard, SIM_OVERRUN, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if (sim_int & SIM_STS_RXERR)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "SIM_STS_RXERR");
+ SimCard->recDataErr = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x6, SimCard->State, drv_get_current_time(), 0, hw_cb->simInterface);
+ SIM_SetTOUT(0x4, hw_cb); // set TOUT ASAP
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_TOUT);
+ if (SimCard->State == SIM_PROCESSCMD)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard, SIM_CMDRECERR, hw_cb);
+ SIM_ASSERT(0);
+ }
+ else if(SimCard->State == SIM_PROCESS_PTS)
+ {
+ SIM_DisAllIntr();
+ SIM_SetEvent_MTK(SimCard,SIM_PTS_RX_INVALID,hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+
+ if ((sim_int & SIM_IRQEN_T0END)
+ && (SimCard->State == SIM_PROCESSCMD))
+ {
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->simMagic1 ++;
+#endif
+ ////dbg_print("SIM_IRQEN_T0END\r\n");
+ SIM_Cmdhandler(hw_cb);
+ SIM_DisAllIntr();
+ }
+ if (sim_int & SIM_STS_NATR && (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK) & SIM_IRQEN_NATR))
+ {
+ DRV_ICC_print_err_msg(hw_cb, "No ATR");
+ SIM_DisAllIntr();
+ if (SimCard->SIM_ENV == ME_18V_30V)
+ {
+ if (SimCard->Power == SimCard->initialPower)
+ {
+ if (SimCard->Power != SIM_30V)
+ {
+ SimCard->Power = SIM_30V;
+ }
+ else
+ {
+ SimCard->Power = SIM_18V;
+ }
+ SIM_L1Reset(hw_cb, KAL_FALSE);
+ }
+ else
+ {
+ SIM_Reject_MTK(hw_cb);
+ }
+ }
+ else
+ {
+ SIM_Reject_MTK(hw_cb);
+ }
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC69, SimCard->SIM_ENV, SimCard->Power, SimCard->Data_format, 0, 0x1014);
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ SIM_SetEvent_MTK(SimCard, SIM_NO_ATR, hw_cb);
+ }
+
+ if (sim_int & SIM_STS_SIMOFF)
+ {
+
+ // dbg_print("SIM_STS_SIMOFF\r\n");
+ SIM_DisAllIntr();
+
+ if (SimCard->State == SIM_PWROFF)
+ {
+ if (SimCard->reject_set_event)
+ {
+ SIM_SetEvent_MTK(SimCard, SIM_NOREADY, hw_cb);
+ SIM_ASSERT(0);
+ }
+ }
+ else
+ {
+ if (SimCard->State == SIM_WaitRejectDone)
+ {
+#if defined(__FPGA__)
+ SIM_Initialize(SimCard->Data_format, SimCard->Power, hw_cb);
+#endif // #if defined(__FPGA__)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC58, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ }
+ else
+ {
+ SIM_ASSERT(0);
+ }
+
+ }
+ }
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+}
+
+
+void SIM_LISR_Multiple(kal_uint32 vector)
+//void SIM_LISR_Multiple(void)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(0)]);
+ IRQMask(hw_cb->mtk_lisrCode);
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(SIM_HISR);
+#else
+ kal_activate_hisr(sim_hisrid);
+#endif
+}
+
+void SIM_LISR2_Multiple(kal_uint32 vector)
+//void SIM_LISR2_Multiple(void)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(1)]);
+ IRQMask(hw_cb->mtk_lisrCode);
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(SIM2_HISR);
+#else
+ kal_activate_hisr(sim2_hisrid);
+#endif
+}
+
+#if 1
+//==========================SIM adaption=============================
+/*
+* FUNCTION
+* L1sim_PowerOff
+*
+* DESCRIPTION
+* The function requests the driver to deactivate SIM
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void sim_PowerOff_MTK(sim_HW_cb *hw_cb) //Validate
+{
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC65, 0, 0, drv_get_current_time(), 0, hw_cb->simInterface);
+
+ SIM_DisAllIntr();
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ SIM_icusb_disableSession(hw_cb);
+ sim_addMsg(0xE014, hw_cb->simInterface, 0, 0);
+ }
+#endif // #if defined(SIM_DRV_IC_USB)
+ SimCard->reject_set_event = KAL_FALSE;
+ SIM_Reject_MTK(hw_cb);
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ // tell USB to reset MAC & PHY
+ SIM_icusb_disconnectDone(hw_cb);
+ sim_addMsg(0xE015, hw_cb->simInterface, 0, 0);
+ SIM_icusb_deinit(hw_cb);
+ }
+#endif // #if defined(SIM_DRV_IC_USB)
+ // DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_SIM,PDN_SIM);
+}
+
+/*
+* FUNCTION
+* L1sim_Reset
+*
+* DESCRIPTION
+* The function L1sim_Reset is used to reset SIM by specific voltage
+*
+* CALLS
+*
+* PARAMETERS
+* resetVolt: Request the driver to reset SIM at voltage resetVolt
+* resultVolt: The pointer to the voltage after the driver reset SIM.
+* (RESET_3V,RESET_5V)
+* Info: The pointer to buffer of ATR data returned from SIM
+*
+* RETURNS
+* SIM_NO_ERROR No SIM error
+* SIM_NO_INSERT No SIM inserted
+* SIM_CARD_ERROR SIM fatal error
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+static kal_uint8 L1sim_Core_Reset(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info, sim_HW_cb *hw_cb) //Validate
+{
+ kal_uint8 index;
+ Sim_Card *SimCard;
+ usim_dcb_struct *usim_dcb;
+ kal_bool returnBool;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ kal_sleep_task(KAL_TICKS_10_MSEC_REAL);
+ SIM_DisAllIntr();
+ SimCard->sim_card_speed = sim_card_normal_speed;
+ SimCard->reject_set_event = KAL_TRUE;
+
+ /*
+ SIM_DEFAULT_TOUT_VALUE is 0x260 in ../inc/sim_drv_HW_def_MTK.h
+ It has been divide by 16
+ */
+ SimCard->TOUTValue = SIM_DEFAULT_TOUT_VALUE << 2;
+
+ SimCard->TOUT_Factor = 1;
+ SimCard->clkStop = KAL_FALSE;
+ SimCard->Speed = Speed372;
+ SimCard->State = SIM_WAIT_FOR_ATR;
+ SimCard->Power = resetVolt;
+ SimCard->initialPower = resetVolt;
+ SimCard->power_class = UNKNOWN_POWER_CLASS;
+ SimCard->TC2Present = KAL_FALSE;
+ SimCard->timeout = KAL_FALSE;
+ // SimCard->gpt_handle = usim_dcb->gpt_handle;
+ SimCard->previous_state = 0;
+ SimCard->atr_count = 0;
+ SimCard->keepAtrFatal = 0;
+#if defined(SIM_DRV_IC_USB)
+ SimCard->isIcUsb = usim_dcb->isIcUsb;
+ SimCard->TB15 = usim_dcb->TB15;
+ SimCard->isIcUsbRecPPS = usim_dcb->isIcUsbRecPPS;
+ SimCard->uart_sim_ccci_handle = usim_dcb->uart_sim_ccci_handle;
+#endif // #if defined(SIM_DRV_IC_USB)
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ SimCard->poll_sim_2s = KAL_FALSE;
+#endif // #if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+#if defined(__USIM_DRV__)
+ {
+ // dbg_print("SIM does not reset againg.....\r\n");
+ SimCard->Data_format = usim_dcb->dir;
+ SimCard->result = SIM_SUCCESS;
+ SimCard->sim_ATR_fail = KAL_FALSE;
+ SimCard->power_class = usim_dcb->power_class;
+ // mtk04122: Reset failed due to TS_HSK_ENABLE is enabled, we need to do activation for following process
+ /*
+ if(SimCard->TS_HSK_ENABLE == KAL_FALSE)
+ {
+ returnBool = SIM_ResetNoATR(SimCard->Power, hw_cb);
+ if(KAL_TRUE != returnBool)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_NOATR_FAIL, SimCard->Power,0, 0, 0, 0);
+ return SIM_CARD_ERROR;
+ }
+ SIM_WaitEvent_MTK(SimCard,ATR_END, KAL_FALSE, hw_cb);
+ }
+ */
+ }
+#else // #if defined(__USIM_DRV__)
+ // dbg_print("SIM reset againg.....\r\n");
+ SimCard->Data_format = SIM_direct;
+ reset_index = 0;
+ SimCard->result = SIM_NOREADY;
+ SIM_L1Reset();
+
+ SIM_WaitEvent_MTK(SimCard, RST_READY, KAL_FALSE, hw_cb);
+
+ if (SimCard->result == SIM_NOREADY)
+ {
+ //L1sim_PowerOff();
+ return SIM_NO_INSERT;
+ }
+
+ if (SimCard->result == SIM_CARDERR)
+ {
+ if (SimCard->Power == SIM_30V)
+ {
+ SimCard->Power = SIM_18V;
+ SIM_L1Reset();
+ }
+ else
+ {
+ SimCard->Power = SIM_30V;
+ SIM_L1Reset();
+ }
+ SIM_WaitEvent_MTK(SimCard, RST_READY, KAL_FALSE, hw_cb);
+ }
+#endif // #if defined(__USIM_DRV__)
+ if (SimCard->result == SIM_SUCCESS)
+ {
+ index = 0;
+ while (1)
+ {
+ if (!SIM_ProcessATRData(hw_cb))
+ {
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ DRV_ICC_print_err_msg(hw_cb, "Bad card/Hw contact issue, cause PTS error. Enter recovery process\n\r");
+
+ index++;
+ // if(index == 3)
+ if (index == 2)
+ {
+ SimCard->PTS_check = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC59, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ }
+ else if (index > 2 || KAL_TRUE == SimCard->keepAtrFatal) //else if (index > 3)
+ {
+ SimCard->PTS_check = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC60, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ sim_PowerOff_MTK(hw_cb);
+ if((SimCard->result == SIM_INIPTSERR) ||(SimCard->result == SIM_PTS_RX_INVALID))
+ {
+ return SimCard->result;
+ }
+ else
+ {
+ return SIM_CARD_ERROR;
+ }
+ }
+#ifdef DRV_SIM_RETRY_18V_ONLY_USIM_ON_PTS_ERROR
+ else if ((SimCard->Power == SIM_18V) && SimCard->power_class == CLASS_C_18V)
+ {
+ DRV_ICC_print_str("RETRY_18V_ONLY_USIM\n\r");
+ SimCard->PTS_check = KAL_TRUE;
+ SimCard->SIM_ENV = ME_18V_ONLY;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC61, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ //index = 0;
+ }
+#endif // #ifdef DRV_SIM_RETRY_18V_ONLY_USIM_ON_PTS_ERROR
+#ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+ /* For [MAUI_01321659] begin, retry 3V when we fail in 1.8V */
+ else if ((SimCard->Power == SIM_18V) && (SIM_GetCurrentEnv(hw_cb->simInterface) == ME_18V_30V))
+ {
+ DRV_ICC_print_str("RETRY_3V_ON_PTS_ERROR\n\r");
+ SimCard->Power = SIM_30V;
+ SimCard->PTS_check = KAL_TRUE;
+ //index = 0;
+ }/* For [MAUI_01321659] end */
+#endif // #ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+#if defined(__USIM_DRV__)
+ SimCard->sim_ATR_fail = KAL_TRUE;
+#endif // #if defined(__USIM_DRV__)
+ /*since we may power off the card and set SIM pdn, we have to disable PDN here, or we may trapped in wait event*/
+
+#ifdef DRV_SIM_RETRY_VOLTAGE_ON_PPS_TIMEOUT
+ if (index == 2)
+ {
+ if (SimCard->SIM_ENV == ME_18V_30V)
+ {
+ if (SimCard->Power == SIM_30V)
+ {
+ SimCard->Power = SIM_18V;
+ }
+ else
+ {
+ SimCard->Power = SIM_30V;
+ }
+ }
+ }
+#endif // #ifdef DRV_SIM_RETRY_VOLTAGE_ON_PPS_TIMEOUT
+ returnBool = SIM_ResetNoATR(SimCard->Power, hw_cb);
+ if (KAL_TRUE != returnBool)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_NOATR_FAIL, SimCard->Power, index, 0, 0, 0);
+ return SIM_CARD_ERROR;
+ }
+ }
+ else
+ {
+
+ if (resultVolt != NULL)
+ {
+ *resultVolt = SimCard->Power;
+ }
+ if (Info != NULL)
+ {
+ for (index = 0; index < SimCard->recDataLen; index++)
+ {
+ Info->info[index] = SimCard->recData[index];
+ }
+ }
+ return SIM_NO_ERROR;
+ }
+ }
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC62, SimCard->EvtFlag, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SimCard->result, 0);
+ sim_PowerOff_MTK(hw_cb);
+
+ return SIM_CARD_ERROR;
+ }
+}
+
+kal_uint8 sim_Reset_MTK(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info, sim_HW_cb *hw_cb) //Validate
+{
+ kal_uint8 result;
+ Sim_Card *SimCard;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->TS_HSK_ENABLE = KAL_TRUE;
+ result = L1sim_Core_Reset(resetVolt, resultVolt, Info, hw_cb);
+ if (result != SIM_NO_ERROR && KAL_FALSE == SimCard->keepAtrFatal)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_FAIL_WITH_TS_HSK_ENABLE, 0, 0, 0, 0, 0);
+ SimCard->TS_HSK_ENABLE = KAL_FALSE;
+ result = L1sim_Core_Reset(resetVolt, resultVolt, Info, hw_cb);
+ }
+ if (result == SIM_NO_ERROR)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_OK_POWER_SPEED, SimCard->Power, SimCard->Speed, 0, 0, 0);
+ }
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_RESET_FAIL_RESULT, result, 0, 0, 0, 0);
+ }
+ return result;
+}
+
+
+
+/*
+* FUNCTION
+* L1sim_Configure
+*
+* DESCRIPTION
+* The function indicates clock mode when idle.
+*
+* CALLS
+*
+* PARAMETERS
+* clockMode: The clockMode defines the clock mode when idle.
+* CLOCK_STOP_AT_HIGH,CLOCK_STOP_AT_LOW,CLOCK_STOP_NOT_ALLOW
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void L1sim_Configure_MTK(kal_uint8 clockMode, sim_HW_cb *hw_cb) //Validate
+{
+ Sim_Card *SimCard;
+ kal_uint32 t1 = 0, log_size = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC128, hw_cb->simInterface, clockMode, 0, 0, 0);
+
+ switch (clockMode)
+ {
+ case CLOCK_STOP_AT_HIGH:
+ // #if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN);
+#endif /*MT6205,MT6205B,MT6218*/
+ SimCard->clkStop = KAL_TRUE;
+ SimCard->clkStopLevel = KAL_TRUE;
+ break;
+
+ case CLOCK_STOP_AT_LOW:
+ //#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN);
+#endif /*MT6205,MT6205B,MT6218*/
+ SimCard->clkStop = KAL_TRUE;
+ SimCard->clkStopLevel = KAL_FALSE;
+ break;
+
+ case CLOCK_STOP_NOT_ALLOW:
+ //#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN);
+#endif /*MT6205,MT6205B,MT6218*/
+ SimCard->clkStop = KAL_FALSE;
+ break;
+
+ default:
+ break;
+ }
+
+ if (clockMode != CLOCK_STOP_NOT_ALLOW)
+ {
+ t1 = SIM_GetCurrentTime();
+ while ((SIM_GetCurrentTime() - t1) < 20); // delay 600 clock cycles (600us)
+ //SIM_Idle_MTK(SimCard->clkStopLevel, hw_cb);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]stop SIM clock\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+}
+
+#ifdef SIM_NULLBYTE_ISSUE
+/*in MT6302 solution, there is only one task to access card in the same time, so we don't need the interface parameter*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+void sim_nullByteIssueGptTimeout_0(void *parameter)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+ kal_uint32 log_size = 0;
+
+ hw_cb = (sim_HW_cb *)parameter;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ Data_Sync_Barrier();
+ /* [ALPS00600930]we should stop wait event gpt timer;otherwise it will cause null byte process fail */
+ DRV_ICC_GPTI_StopItem(SimCard->gpt_handle);
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+
+ /* [MAUI_03009364]If card is removed, we don't need to wait null bytes */
+ if (hw_cb->IsCardRemove == KAL_TRUE)
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount = 0;
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+ /*must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger*/
+ SimCard->simMagic1++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ return;
+ }
+#endif
+ if (SimCard->simMagic1 != SimCard->simMagic2) /*cmd finished before GPT timeout*/
+ {
+ DRV_ICC_print_str("sim_nullByteIssueGptTimeout_0:cmd finished before GPT timeout");
+ }
+ else /*the GPT timer is used to find out these cases, it means we still haven't complete the CMD for so long duration*/
+ {
+
+ /*it means the last byte received is null byte, we wait for 5 consecutive null byte noticed before ending the CMD*/
+ if (0x60 == SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK))
+ {
+ SimCard->sim_nullByteIssueNullCount ++;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] : null timeout %d\n\r", hw_cb->simInterface, SimCard->sim_nullByteIssueNullCount);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_NULL_TOUT,hw_cb->simInterface, SimCard->sim_nullByteIssueNullCount);
+#endif
+ if (38 < SimCard->sim_nullByteIssueNullCount)
+ {
+ /*we have receive 5 null byte*/
+ SIM_DisAllIntr();
+ //DRV_ICC_print(hw_cb, SIM_PRINT_NULL_TIME_OUT, hw_cb->simInterface, 0, 0, 0, 0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else
+ {
+ // DRV_ICC_print(hw_cb, SIM_PRINT_NULL_BYTE, hw_cb->simInterface, SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0, 0, 0);
+#if 0 //defined(SIM_HOT_SWAP_V2)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ /*polling status every 3 sec*/
+ if (msg_get_task_extq_messages(SimCard->mod_id) > SimCard->mod_extq_cap - 5)
+ {
+ SIM_DisAllIntr();
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM:%d] : extq num:%d\n\r", __LINE__, msg_get_task_extq_messages(SimCard->mod_id));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ //DRV_ICC_print(SIM_PRINT_NULL_TIME_OUT, hw_cb->simInterface, 0, 0, 0, 0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else if (OSTD_Infinite_Sleep_Query() == KAL_FALSE) //No EPOF
+ {
+ /*polling status every 1 sec*/
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 100, sim_nullByteIssueGptTimeout_0, parameter);
+ }
+ else
+ {
+ SIM_DisAllIntr();
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] Quit waiting null byte\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ }
+ }
+ else /*received is not null*/
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount ++;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] : non-null timeout %d\n\r", hw_cb->simInterface, SimCard->sim_nullByteIssuenonNullCount);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_NON_NULL_TOUT,hw_cb->simInterface, SimCard->sim_nullByteIssuenonNullCount);
+#endif
+ if (48 < SimCard->sim_nullByteIssuenonNullCount)
+ {
+ /*we have receive 84 non null byte*/
+ SIM_DisAllIntr();
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else
+ {
+ // DRV_ICC_print(hw_cb, SIM_PRINT_NON_NULL_BYTE, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0, 0);
+#if 0 //defined(SIM_HOT_SWAP_V2)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC66, SimCard->TOUTValue, drv_get_current_time(), 0, 0, 0);
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC66, hw_cb);
+ sim_dump_fifo(hw_cb);
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 100, sim_nullByteIssueGptTimeout_0, parameter);
+ }
+ }
+ }
+}
+
+void sim_nullByteIssueGptTimeout_1(void *parameter)
+{
+ Sim_Card *SimCard;
+ sim_HW_cb *hw_cb;
+ kal_uint32 log_size = 0;
+
+ hw_cb = (sim_HW_cb *)parameter;
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ Data_Sync_Barrier();
+ /* [ALPS00600930]we should stop wait event gpt timer;otherwise it will cause null byte process fail */
+ DRV_ICC_GPTI_StopItem(SimCard->gpt_handle);
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+
+ /* [MAUI_03009364]If card is removed, we don't need to wait null bytes */
+ if (hw_cb->IsCardRemove == KAL_TRUE)
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount = 0;
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+ /*must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger*/
+ SimCard->simMagic1++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ return;
+ }
+#endif
+
+ if (SimCard->simMagic1 != SimCard->simMagic2) /*cmd finished before GPT timeout*/
+ {
+ DRV_ICC_print_str("sim_nullByteIssueGptTimeout_1:cmd finished before GPT timeout");
+ }
+ else /*the GPT timer is used to find out these cases, it means we still haven't complete the CMD for so long duration*/
+ {
+
+ /*it means the last byte received is null byte, we wait for 5 consecutive null byte noticed before ending the CMD*/
+ if (0x60 == SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK))
+ {
+ SimCard->sim_nullByteIssueNullCount ++;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] : null timeout %d\n\r", hw_cb->simInterface, SimCard->sim_nullByteIssueNullCount);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_NULL_TOUT,hw_cb->simInterface, SimCard->sim_nullByteIssueNullCount);
+#endif
+ if (38 < SimCard->sim_nullByteIssueNullCount)
+ {
+ /*we have receive 5 null byte*/
+ SIM_DisAllIntr();
+ // DRV_ICC_print(hw_cb, SIM_PRINT_NULL_TIME_OUT, hw_cb->simInterface, 0, 0, 0, 0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else
+ {
+ // DRV_ICC_print(hw_cb, SIM_PRINT_NULL_BYTE, hw_cb->simInterface, SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0, 0, 0);
+#if 0 //defined(SIM_HOT_SWAP_V2)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ if (msg_get_task_extq_messages(SimCard->mod_id) > SimCard->mod_extq_cap - 5)
+ {
+ SIM_DisAllIntr();
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM:%d] : extq num:%d\n\r", __LINE__, msg_get_task_extq_messages(SimCard->mod_id));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ //DRV_ICC_print(SIM_PRINT_NULL_TIME_OUT, hw_cb->simInterface, 0, 0, 0, 0);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else if (OSTD_Infinite_Sleep_Query() == KAL_FALSE) //No EPOF
+ {
+ /*polling status every 1 sec*/
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 100, sim_nullByteIssueGptTimeout_1, parameter);
+ }
+ else
+ {
+ SIM_DisAllIntr();
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] Quit waiting null byte\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ }
+ }
+ else /*received is not null*/
+ {
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount ++;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d] : non-null timeout %d\n\r", hw_cb->simInterface, SimCard->sim_nullByteIssuenonNullCount);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_NON_NULL_TOUT,hw_cb->simInterface, SimCard->sim_nullByteIssuenonNullCount);
+#endif
+ if (48 < SimCard->sim_nullByteIssuenonNullCount)
+ {
+ /*we have receive 84 non null byte*/
+ SIM_DisAllIntr();
+ SimCard->timeout = KAL_TRUE;
+ SIM_SetEvent_MTK(SimCard, SIM_NULLTIMEOUT, hw_cb);
+ }
+ else
+ {
+ // DRV_ICC_print(hw_cb, SIM_PRINT_NON_NULL_BYTE, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0, 0);
+#if 0 //defined(SIM_HOT_SWAP_V2)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC66, SimCard->TOUTValue, drv_get_current_time(), 0, 0, 0);
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC66, hw_cb);
+ sim_dump_fifo(hw_cb);
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 100, sim_nullByteIssueGptTimeout_1, parameter);
+ }
+ }
+ }
+}
+
+#endif
+
+
+/*
+* FUNCTION
+* SIM_CMD
+*
+* DESCRIPTION
+* The function is used to transmit coded command and
+* its following data to the driver.
+*
+* CALLS
+*
+* PARAMETERS
+* txData: Pointer to the transmitted command and data.
+* txSize: The size of the transmitted command and data from AL to driver.
+* expSize: The size of expected data from SIM
+* result: Pointer to received data
+* rcvSize: Pointer to the size of data received
+* parityError: 1 (parity error) or 0(no parity error)
+*
+* RETURNS
+* status(high byte:sw1 low byte: sw2)
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+
+
+
+
+static kal_uint16 SIM_CMD(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error, sim_HW_cb *hw_cb)
+//kal_uint16 L1sim_Cmd(kal_uint8 *txData,kal_uint16 txSize,kal_uint8 expSize, kal_uint8 *result,kal_uint8 *rcvSize, kal_uint8 *Error)
+{
+ kal_uint16 SW;
+ kal_uint8 index = 0;
+ kal_uint16 INS;
+ kal_uint16 expSize = *rcvSize;
+#ifdef SIM_ADDDMA
+ kal_bool txDelay = KAL_FALSE;
+ kal_uint32 txaddr;
+ kal_uint32 rxaddr;
+#endif // #ifdef SIM_ADDDMA
+ Sim_Card *SimCard;
+
+ kal_uint32 savedMask;
+ kal_uint32 hwCtrl, log_size = 0;
+ kal_uint8 tmpsts;
+
+ // Special Case: AP issued case2 command with le < Lr (Real response data length), Then expsize should equal txData[4]
+ if (5 == txSize && 0 != txData[4])
+ {
+ expSize = txData[4];
+ }
+
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ *Error = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ SimCard->t_debug[2] = ust_get_current_time();
+
+ hw_cb->doNotStopSimClock = 0;
+
+ if (result == NULL && *rcvSize != 0)
+ {
+ *Error = KAL_TRUE;
+
+ return 0;
+ }
+ if (SimCard->State != SIM_PROCESSCMD)
+ {
+ *Error = KAL_TRUE;
+
+ return 0;
+ }
+
+#ifdef NoT0CTRL
+ if ((SimCard->cmdState != SIMD_CmdIdle) && (SimCard->cmdState != SIM_StopClk))
+ {
+ *Error = KAL_TRUE;
+
+ return 0;
+ }
+#endif // #ifdef NoT0CTRL
+#if !defined(ATEST_DRV_ENABLE)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *txData, *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ if (result == NULL)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, 0, drv_get_current_time(), SimCard->timeout);
+ else
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, (kal_uint32) result, drv_get_current_time(), SimCard->timeout);
+#endif
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *result, *(result + 1), *(result + 2), *(result + 3), *(result + 4));
+#endif // #if defined(SIM_DEBUG_INFO)
+
+ // for clock stop mode
+ SIM_DisAllIntr();
+#if defined(SIM_DRV_IC_USB)
+ if ((SimCard->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && SimCard->forceISO == KAL_FALSE)
+ {
+#if defined(SIM_DRV_IC_USB_DBG_2)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *txData, *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, *(txData + 5), *(txData + 6), *(txData + 7), *(txData + 8), *(txData + 9));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, index, drv_get_current_time(), 0xaaaa);
+#endif // #if defined(SIM_DRV_IC_USB_DBG_2)
+ kal_set_eg_events(SimCard->event, 0, KAL_AND); //2: NU_AND
+ *Error = KAL_FALSE;
+ SimCard->recDataErr = KAL_FALSE;
+ SimCard->sim_icusb_T0cmd.txData = txData;
+ SimCard->sim_icusb_T0cmd.txSize = txSize;
+ SimCard->sim_icusb_T0cmd.result = result;
+ SimCard->sim_icusb_T0cmd.rcvSize = rcvSize;
+ SW = SIM_icusb_cmd(hw_cb);
+ if (SW == (kal_uint16)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE023, hw_cb->simInterface, 0, 0);
+ SW = 0x0000;
+ }
+#if defined(SIM_DRV_IC_USB_DBG)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC83, SimCard->icusb_state, SW, hw_cb->simInterface, SimCard->TB15, SimCard->isIcUsbRecPPS);
+#endif // #if defined(SIM_DRV_IC_USB_DBG)
+#if defined(SIM_DRV_IC_USB_DBG_2)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, txSize, *rcvSize, index, drv_get_current_time(), 0xaaab);
+#endif // #if defined(SIM_DRV_IC_USB_DBG_2)
+ return SW;
+ }
+#endif // #if defined(SIM_DRV_IC_USB)
+
+ SIM_DisAllIntr();
+
+
+ Data_Sync_Barrier();
+ if (0x3 == SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))
+ SIM_DEBUG_ASSERT(0);
+
+#ifndef __MAUI_BASIC__
+ if (0 != SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK))
+ {
+ // we print index
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK)
+);
+#endif // #if !defined(__L1_STANDALONE__)
+#endif // #if defined(__SIM_DRV_TRACE__)
+ }
+#endif // #ifndef __MAUI_BASIC__
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+ kal_set_eg_events(SimCard->event, 0, KAL_AND); //2: NU_AND
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ // DRVPDN_Disable(DRVPDN_CON0,DRVPDN_CON0_DMA,PDN_DMA);
+
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+
+ SIM_SetTOUT(SimCard->TOUTValue, hw_cb);
+ SIM_FIFO_Flush();
+
+ {
+ int fifo_cnt = DRV_Reg32(SIM0_BASE_ADDR_MTK + 0x44);
+ if (fifo_cnt != 0)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "SIM FIFO_CNT=%d after clear FIFO !!!!!!!!!!!!!", fifo_cnt);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ }
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ // dbg_print("[DRV] TOUTValue = %d\r\n",SimCard->TOUTValue);
+ *Error = KAL_FALSE;
+ SimCard->recDataErr = KAL_FALSE;
+
+#ifdef SIM_ADDDMA
+ txaddr = (kal_uint32)txData;
+ rxaddr = (kal_uint32)result;
+#else // #ifdef SIM_ADDDMA
+ SimCard->txbuffer = txData;
+ SimCard->txsize = txSize;
+ SimCard->rxbuffer = result;
+ SimCard->recDataLen = 0;
+#ifdef NoT0CTRL
+ SimCard->recsize = expSize;
+ SimCard->txindex = 0;
+ SimCard->INS = *(txData + 1);
+#endif // #ifdef NoT0CTRL
+#endif// #ifdef SIM_ADDDMA
+
+#ifndef NoT0CTRL
+ INS = (kal_uint16) txData[1];
+ SIM_SetCOMDLEN(txData[4]);
+ SimCard->cmdState = SIM_WaitCmdEnd;
+#endif // #ifndef NoT0CTRL
+
+#ifdef SIM_ADDDMA
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), 0, 0
+);
+
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif // #if defined (__SIM_DVT__)
+ savedMask = SaveAndSetIRQMask();
+ for (index = 0; index < 5; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, *(txData + index));
+ }
+ sim_addMsg(SIM_CMD_TX_LOG, *(txData + 1), *(txData + 4), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+ RestoreIRQMask(savedMask);
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94)
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x94), 0, 0
+);
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif // #if defined (__SIM_DVT__)
+
+ SIM_SetRXTIDE(1, hw_cb); //set rxtide 0
+
+ if (expSize == 0)
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("SIM TX\n\r");
+#endif // #if defined(SIM_DEBUG_INFO)
+
+ SIM_SetTXTIDE(0, hw_cb);
+ Data_Sync_Barrier();
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)(txaddr + 5));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(0) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(txSize - 5) | HDCR_START0);
+ Data_Sync_Barrier();
+ INS |= SIM_INS_INSD;
+ }
+ else
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("SIM RX\n\r");
+#endif // #if defined(SIM_DEBUG_INFO)
+ SIM_SetTXTIDE(0xffff, hw_cb);
+
+ Data_Sync_Barrier();
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)(rxaddr));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(SimCard->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(expSize) | HDCR_START0);
+ Data_Sync_Barrier();
+
+ }
+
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ usim_waitISR_with_spinlock(hw_cb->spinlockid);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDDMANormal);
+ kal_give_spinlock(hw_cb->spinlockid);
+
+#else // #ifdef SIM_ADDDMA
+#ifdef NoT0CTRL
+ for (index = 0; index < 5; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, *(txData + index));
+ }
+ SimCard->txindex = 5;
+ SimCard->cmdState = SIM_WaitProcByte;
+
+ if (expSize == 0) //Transmit
+ {
+ if (txSize == 5)
+ {
+ SIM_SetRXTIDE(2, hw_cb);
+ }
+ else
+ {
+ SIM_SetRXTIDE(1, hw_cb);
+ }
+ }
+ else
+ {
+ if ((expSize + 3) > 15)
+ {
+ SIM_SetRXTIDE(CMD_RECBUFSIZE - 8, hw_cb);
+ }
+ else
+ {
+ SIM_SetRXTIDE(expSize + 3, hw_cb);
+ }
+ }
+ //SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ usim_waitISR_with_spinlock(hw_cb->spinlockid);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDNormal);
+ kal_give_spinlock(hw_cb->spinlockid);
+#else // #ifdef NoT0CTRL
+
+ if (txSize <= 15)
+ {
+ for (index = 0; index < txSize; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, *(txData + index));
+ }
+ SimCard->txindex = txSize;
+
+ Data_Sync_Barrier();
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ usim_waitISR_with_spinlock(hw_cb->spinlockid);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_CMDNormal);
+ kal_give_spinlock(hw_cb->spinlockid);
+ }
+ else
+ {
+ for (index = 0; index < 15; index++)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK, *(txData + index));
+ }
+ SimCard->txindex = 15;
+ SIM_SetTXTIDE(0, hw_cb);
+
+ Data_Sync_Barrier();
+ tmpsts = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, tmpsts);
+ usim_waitISR_with_spinlock(hw_cb->spinlockid);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_IRQEN_CMDNormal | SIM_IRQEN_TX));
+ kal_give_spinlock(hw_cb->spinlockid);
+ }
+
+ if (expSize > 0)
+ {
+ if (expSize > 15)
+ {
+ SIM_SetRXTIDE(CMD_RECBUFSIZE, hw_cb);
+ }
+ else
+ {
+ SIM_SetRXTIDE(expSize, hw_cb);
+ }
+ /* maybe changed for 64k rate */
+ }
+ else
+ {
+ INS |= SIM_INS_INSD;
+ }
+#endif /*NoT0CTRL*/
+#endif// #ifdef SIM_ADDDMA
+
+#ifdef SIM_ADDDMA
+
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC40, hw_cb);
+#endif
+#endif // #ifdef SIM_DMA
+ {
+ usim_waitISR_with_spinlock(hw_cb->spinlockid);
+#ifndef NoT0CTRL
+#ifdef SIM_NULLBYTE_ISSUE
+ SimCard->sim_nullByteIssueNullCount = 0;
+ SimCard->sim_nullByteIssuenonNullCount = 0;
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+ // must change magic after we confirm GPT won't trigger, since this code run in task context, we can run this code means GPT won't trigger
+ SimCard->simMagic1++;
+ SimCard->simMagic2 = SimCard->simMagic1;
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+ if (MTK_SIMIF0 == hwCtrl)
+ {
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 300, sim_nullByteIssueGptTimeout_0, hw_cb);
+ }
+ else if (MTK_SIMIF1 == hwCtrl)
+ {
+ DRV_ICC_GPTI_StartItem(SimCard->sim_nullByteIssueGPT, 300, sim_nullByteIssueGptTimeout_1, hw_cb);
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+#endif // #if NoT0CTRL
+#endif // #ifdef NoT0CTRL
+
+#ifndef __MAUI_BASIC__
+ // use PDN_STATUS(dev, s, t) to fullfill my dbg usage, add the code later
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ drv_trace8(TRACE_GROUP_4, SIM_GEMINI_CMD1, 0, hw_cb->simInterface, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),
+ INS, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK)
+ );
+#endif // #if defined(__SIM_DRV_TRACE__)
+#endif // #if !defined(__L1_STANDALONE__)
+
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ drv_trace8(TRACE_GROUP_4, SIM_GEMINI_CMD2, SimCard->sim_menu.addr, SimCard->sim_input.type, SimCard->sim_input.count, 0,
+ drv_get_current_time(), SimCard->sim_input.count,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK)
+ );
+ drv_trace8(TRACE_GROUP_4, SIM_GEMINI_CMD3, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x70),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x74),
+ *txData, *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4)
+ );
+#endif // #if defined(__SIM_DRV_TRACE__)
+#endif // #ifdef __L1_STANDALONE__
+#endif // #if__MAUI_BASIC__
+ // in case
+ SimCard->EvtFlag = 0x0;
+
+ if (SimCard->simMagic2 != SimCard->simMagic1)
+ SIM_DEBUG_ASSERT(0);
+
+ kal_give_spinlock(hw_cb->spinlockid);
+
+ if (txDelay == KAL_FALSE)
+ savedMask = SaveAndSetIRQMask();
+#ifndef NoT0CTRL
+ {
+
+ // we should not use the same variable to store the return value twice
+ kal_uint32 savedMask2;
+
+ savedMask2 = SaveAndSetIRQMask();
+ sim_addMsg(SIM_CMD_INS_LOG, hw_cb->simInterface, INS, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+
+ SIM_SetCmdCTRL(INS);
+ SIM_CMDSTART();
+
+ RestoreIRQMask(savedMask2);
+
+ }
+#endif // #ifnedf NoT0CTRL
+
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif // #if defined (__SIM_DVT__)
+
+
+#ifdef SIM_ADDDMA
+#endif // #ifdef SIM_ADDDMA
+ if (txDelay == KAL_FALSE)
+ RestoreIRQMask(savedMask);
+ }
+#ifdef SIM_ADDDMA
+ sim_addMsg(0x2468024, hw_cb->simInterface, txDelay, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK));
+#endif // #ifdef SIM_ADDDMA
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if 0 //def SIM_HOT_SWAP_V2
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#if defined (__SIM_DVT__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90),
+ SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90)
+);
+#endif // #if defined (__SIM_DVT__)
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC42, hw_cb);
+#endif // #if defined(SIM_DEBUG_INFO)
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ *Error = KAL_TRUE;
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ SIM_FIFO_Flush();
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+
+ SIM_WaitEvent_MTK(SimCard, SIM_EVT_CMD_END, KAL_FALSE, hw_cb);
+ SimCard->t_debug[3] = ust_get_current_time();
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ SIM_DisAllIntr();
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ sim_storeFifo(hw_cb);
+#if defined(SIM_DEBUG_INFO)
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC43, hw_cb);
+#endif // #if defined(SIM_DEBUG_INFO)
+#ifdef SIM_NULLBYTE_ISSUE
+ DRV_ICC_GPTI_StopItem(SimCard->sim_nullByteIssueGPT);
+#endif // #ifdef SIM_NULLBYTE_ISSUE
+
+#ifdef SIM_ADDDMA
+ SIM_DMA_STOP(SimCard->dma_config.channel);
+#endif // #ifdef SIM_ADDDMA
+
+#ifdef NoT0CTRL
+ SimCard->initialPower = SimCard->cmdState;
+ SimCard->cmdState = SIMD_CmdIdle;
+#endif // #ifdef NoT0CTRL
+
+ Data_Sync_Barrier();
+ if (0x3 == SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))
+ SIM_DEBUG_ASSERT(0);
+
+ if (SimCard->result == SIM_SUCCESS && SimCard->recDataErr == KAL_FALSE)
+ {
+#ifdef SIM_ADDDMA
+ if (expSize != 0)
+ {
+ kal_uint16 leftlen = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_LEFTLEN_MTK);
+ if (leftlen > expSize)
+ {
+ *rcvSize = expSize;
+ log_size = kal_sprintf(hw_cb->dbgStr, "SIM Error : in SIM_CMD Leftlen(%d) > expSize(%d)!!!\r\n", leftlen, expSize);
+ if (log_size > 0) tst_sys_trace(hw_cb->dbgStr);
+ }
+ else
+ {
+ *rcvSize = expSize - leftlen;
+ }
+ }
+
+#else // #ifdef SIM_ADDDMA
+ *rcvSize = SimCard->recDataLen;
+#endif // #ifdef SIM_ADDDMA
+
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("SIM_SUCCESS\n\r");
+#endif // #if defined(SIM_DEBUG_INFO)
+
+#ifdef NoT0CTRL
+ SW = (SimCard->SW2 | (SimCard->SW1 << 8));
+#else // #ifdef NoT0CTRL
+ SIM_ObtainSW(SW);
+#endif // #ifdef NoT0CTRL
+
+#if !defined(ATEST_DRV_ENABLE)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC16, hw_cb->simInterface/*SimCard->sim_menu.addr*/, /*SimCard->sim_input.type*/ ust_us_duration(SimCard->t_debug[2], SimCard->t_debug[3]), /*SimCard->sim_input.count*/ 0, SW, *rcvSize);
+ if (result == NULL)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC16, txSize, *Error, 0, 0, drv_get_current_time());
+ else
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC16, txSize, *Error, *result, *(result + 1), drv_get_current_time());
+#endif
+
+ return SW;
+ }
+ else
+ {
+ if (SimCard->result == SIM_CMDTOUT)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "CMD_TOUT");
+ }
+#ifdef NoT0CTRL
+ SW = (SimCard->SW2 | (SimCard->SW1 << 8));
+#else // #ifdef NoT0CTRL
+ SIM_ObtainSW(SW);
+#endif // #ifdef NoT0CTRL
+ DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SimCard->result, SW, drv_get_current_time(), *rcvSize, hw_cb->simInterface);
+ // DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, SimCard->sim_menu.addr, SimCard->sim_input.type, SimCard->sim_input.count,*result,*(result+1));
+ if (result == NULL)
+ DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, 0, 0, 0, expSize, txSize);
+ else
+ DRV_ICC_print(hw_cb, SIM_PRINT_SIM_CMD_FAIL_STATUS, *(result + 2), *(result + 3), *(result + 4), expSize, txSize);
+ sim_dump_reg(SIM_PRINT_SIM_CMD_FAIL_STATUS, hw_cb);
+#ifndef __MAUI_BASIC__
+ // we print DMA lefting, SIM controller power, SW1, SW2, 0x70, 0x74
+ if (0 != expSize)
+ {
+ // we print P3, rx buffer addr, ((EV_GCB *)SimCard->event)->ev_current_events, data count, rx 1st, 2nd byte
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), (kal_uint32)result, 0, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ *result, *(result + 1)
+
+ );
+#endif // #if defined(__SIM_DRV_TRACE__)
+#endif // #if !defined(__L1_STANDALONE__)
+ }
+#endif // #ifndef __MAUI_BASIC__
+ // SimCard->recDataErr = KAL_FALSE;
+ SimCard->is_err = KAL_TRUE;
+ *Error = KAL_TRUE;
+
+ return 0;
+ }
+}
+
+/*
+* FUNCTION
+* L1sim_Cmd
+*
+* DESCRIPTION
+* The function is used to implement re-try command mechanism.
+*
+* CALLS
+*
+* PARAMETERS
+* txData: Pointer to the transmitted command and data.
+* txSize: The size of the transmitted command and data from AL to driver.
+* expSize: The size of expected data from SIM
+* result: Pointer to received data
+* rcvSize: Pointer to the size of data received
+* parityError: 1 (parity error) or 0(no parity error)
+*
+* RETURNS
+* status(high byte:sw1 low byte: sw2)
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+static kal_uint16 L1sim_Cmd(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error, sim_HW_cb *hw_cb)
+{
+ kal_uint8 index;
+ kal_uint16 SW;
+ kal_uint32 log_size = 0;
+ Sim_Card *SimCard;
+#ifdef SIM_CACHED_SUPPORT
+ kal_uint8 *pNoncachedTx, *pNoncachedRx;
+#endif
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "L1sim_Cmd(1) txSize=%d, rcvSize=%d\n\r", txSize, *rcvSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+
+ if (SimCard->State != SIM_PROCESSCMD)
+ {
+ *Error = KAL_TRUE;
+ return 0;
+ }
+ SimCard->get9000WhenSelect = KAL_FALSE;
+
+ // while encounter physical errors, deactivate the SIM immediately
+ for (index = 0; index < 3; index++)
+ {
+ SimCard->timeout = KAL_FALSE;
+
+#ifdef SIM_CACHED_SUPPORT
+ if ((INT_QueryIsCachedRAM(txData, txSize)) || (INT_QueryIsCachedRAM(result, 512)))
+ {
+
+ GET_NCACHEDTX_P(pNoncachedTx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ GET_NCACHEDRX_P(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ kal_mem_cpy(pNoncachedTx, txData, txSize);
+ if (INT_QueryIsCachedRAM(result, 512))
+ {
+ //dbg_print("[DRV] CACHED TX and RX\r\n");
+ SW = SIM_CMD((kal_uint8 *)pNoncachedTx, txSize, (kal_uint8 *)pNoncachedRx, rcvSize, Error, hw_cb);
+ if (0 != *rcvSize)
+ {
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef __DRV_SIM_DMA_TX2RX__
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef __MAUI_BASIC__
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ kal_mem_cpy(result, pNoncachedRx, *rcvSize);
+ }
+ }
+ else
+ {
+ SW = SIM_CMD((kal_uint8 *)pNoncachedTx, txSize, result, rcvSize, Error, hw_cb);
+ }
+ }
+ else
+#endif // SIM_CACHED_SUPPORT
+ {
+ SW = SIM_CMD(txData, txSize, result, rcvSize, Error, hw_cb);
+ }
+
+ if (0x9000 == SW && 0xA4 == txData[1])
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_9000_ON_SELECT, 0, 0, 0, 0, 0);
+ SimCard->get9000WhenSelect = KAL_TRUE;
+ }
+
+ if (hw_cb->issueCardStatus == SIM_CLOCK_FETCH__TERMINAL_RESPONSE)
+ {
+ if ((0x9000 == SW && 0x12 == txData[1])
+ || 0x9100 == (SW & 0xFF00))
+ {
+ hw_cb->doNotStopSimClock = 1;
+ log_size = kal_sprintf(hw_cb->dbgStr, "Do not stop SIM clock this time\n\r");
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ }
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "L1sim_Cmd(2) txSize=%d, rcvSize=%d, fifo: %d\n\r", txSize, *rcvSize, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+#ifdef SIM_HOT_SWAP_V2
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+
+ /* [MAUI_03009364]If card is removed, we don't need to wait status words */
+ if (hw_cb->IsCardRemove && *Error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x3, SW, drv_get_current_time(), *rcvSize, hw_cb->simInterface);
+ /* SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave */
+ SimCard->timeout = KAL_FALSE;
+ return SW;
+ }
+#endif
+#endif
+
+ if (SimCard->timeout && SimCard->app_proto == USIM_PROTOCOL)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC18, txSize, *rcvSize, drv_get_current_time(), SW, hw_cb->simInterface);
+ /*SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave*/
+ SimCard->timeout = KAL_FALSE;
+
+ sim_PowerOff_MTK(hw_cb);
+
+ /*to deactivation SIMIF takes time, we must make sure it deactivated done*/
+ kal_sleep_task(KAL_TICKS_100_MSEC_REAL);
+
+ return SW;
+ }
+#ifdef __SIM_HOT_SWAP_SUPPORT__
+ sim_get_card_status(hw_cb->simInterface, &hw_cb->IsCardRemove);
+ /* [MAUI_03009364]If card is removed, we don't need to wait status words */
+ if (hw_cb->IsCardRemove && *Error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC70, 0x5, SW, drv_get_current_time(), *rcvSize, hw_cb->simInterface);
+ /*SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave*/
+ SimCard->timeout = KAL_FALSE;
+ return SW;
+ }
+#endif
+
+ if (*Error == 0)
+ break;
+ }
+
+ if (((SW & 0xf000) != 0x6000) && ((SW & 0xf000) != 0x9000))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Illegal SW:%x", SW);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+ sim_dump_reg(SIM_PRINT_SIM_CMD_FAIL_STATUS, hw_cb);
+ *Error = KAL_TRUE;
+ }
+
+ if ((SW == 0x9000 || (SW & 0xFF00) == 0x9100 || (SW & 0xFF00) == 0x9200) && 0xB0 == txData[1] && *rcvSize == 0)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "READ BINARY, SW:%x, rcvSize:%d", SW, *rcvSize);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+
+ //ALPS04172135: Don't change sw to 0x6281 for AT+CGLA command
+#ifdef __TC01__
+ if (SimCard->bypass6263 != KAL_TRUE)
+ {
+#endif
+ //*Error = KAL_TRUE;
+ SW = 0x6281;
+ log_size = kal_sprintf(hw_cb->dbgStr, "Convert SW to :%x", SW);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+#ifdef __TC01__
+ }
+#endif
+ }
+
+ if (*Error)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_CMD_FAIL_RESULT_STATUS, SimCard->result, SW, drv_get_current_time(), 0, 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_RECEIVE_ERR_1, SimCard->recDataErr, SimCard->timeout, SimCard->cmdState, SimCard->event_state, SimCard->EvtFlag);
+ DRV_ICC_print(hw_cb, SIM_PRINT_RECEIVE_ERR_2, SimCard->clkStop, SimCard->app_proto, 0, 0, 0);
+
+#ifndef __MAUI_BASIC__
+ if (0 != result)
+ {
+ /*we print P3, rx buffer addr, ((EV_GCB *)SimCard->event)->ev_current_events, data count, rx 1st, 2nd byte*/
+#if !defined(__L1_STANDALONE__)
+#if defined(__SIM_DRV_TRACE__)
+ MD_TRC(LOG_SIM_DRV_GEMINI_GEN1,FILE_SWITCHCONTROL0, __LINE__,
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), (kal_uint32)result, 0, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK),
+ *result, *(result + 1)
+);
+#endif /*__SIM_DRV_TRACE__*/
+#endif
+ }
+#endif
+ }
+
+#ifdef SIM_CACHED_SUPPORT_WRITE_THROUGH_SERIES
+ invalidate_wt_cache((kal_uint32)result, *rcvSize);
+#endif
+
+ if (SW != 0 && *Error == KAL_FALSE)
+ {
+ SimCard->cmd_duration_count++;
+ SimCard->cmd_duration_sum += ust_us_duration(SimCard->t_debug[2], SimCard->t_debug[3]);
+ }
+ /*SimCard->timeout's life cycle should be only in this L1sim_Cmd, reset to false before we leave*/
+ SimCard->timeout = KAL_FALSE;
+ /*Get ICCID*/
+ if (SimCard->EF_ICCID_Selected == KAL_TRUE && *rcvSize == 10 && txData[1] == 0xB0 && result != NULL)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x",
+ result[0], result[1], result[2], result[3], result[4], result[5], result[6], result[7], result[8], result[9]);
+
+#ifdef ATEST_DRV_ENABLE
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ICCID,hw_cb->simInterface, hw_cb->dbgStr);
+#endif
+ SimCard->EF_ICCID_Selected = KAL_FALSE;
+ }
+ if (txData[1] == 0xA4)
+ {
+ if (txSize >= 7 && txData[5] == 0x2F && txData[6] == 0xE2)
+ SimCard->EF_ICCID_Selected = KAL_TRUE;
+ else
+ SimCard->EF_ICCID_Selected = KAL_FALSE;
+ }
+ return SW;
+}
+
+/*
+* FUNCTION
+* L1sim_Init
+*
+* DESCRIPTION
+* The function L1sim_Init initialize the SIM driver.
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* external_global
+*/
+void L1sim_Init_MTK(sim_HW_cb *hw_cb) //Validate
+{
+ Sim_Card *SimCard;
+ kal_uint32 hwCtrl;
+#ifdef SIM_ADDDMA
+ kal_uint8 DMA_channel = 0;
+#endif
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ SimCard->SIM_ENV = SIM_GetCurrentEnv(hw_cb->simInterface);
+ if (SimCard->SIM_ENV == ME_30V_ONLY)
+ {
+ SimCard->Power = SIM_30V;
+ }
+ else
+ {
+ SimCard->Power = SIM_18V;
+ }
+ usim_dcb->simInitialized=KAL_TRUE;
+
+ SimCard->Data_format = SIM_direct;
+ SimCard->State = SIM_WAIT_FOR_ATR;
+ SimCard->clkStop = KAL_FALSE;
+ SimCard->Speed = Speed372;
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+#ifdef SIM_ADDDMA
+ SimCard->dma_config.BURST_SIZE = HDCTRR_BST_SIZE_16;
+ SimCard->dma_config.DEV_BUS_WIDTH = HDCTRR_BUS_WIDTH_8;
+ SimCard->dma_config.MEM_BUS_WIDTH = HDCTRR_BUS_WIDTH_32;
+ DMA_channel = (MTK_SIMIF0 == hwCtrl) ? 0 : 1;
+ SimCard->dma_config.channel = DMA_channel;
+ SimCard->dma_config.ADDR_HDMA_HPRGA0Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA0R0 : REG_HDMA_HPRGA0R1;
+ SimCard->dma_config.ADDR_HDMA_HPRGA1Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA1R0 : REG_HDMA_HPRGA1R1;
+ SimCard->dma_config.ADDR_HDMA_HDCTRRx = (DMA_channel == 0) ? REG_HDMA_HDCTRR0 : REG_HDMA_HDCTRR1;
+ SimCard->dma_config.ADDR_HDMA_HDC0Rx = (DMA_channel == 0) ? REG_HDMA_HDC0R0 : REG_HDMA_HDC0R1;
+ SimCard->dma_config.ADDR_HDMA_HDC1Rx = (DMA_channel == 0) ? REG_HDMA_HDC1R0 : REG_HDMA_HDC1R1;
+
+#endif /*SIM_ADDDMA*/
+ SimCard->cmd_duration_sum = 0;
+ SimCard->cmd_duration_count = 0;
+ SimCard->status_duration_sum = 0;
+ SimCard->status_duration_count = 0;
+
+ /*following members are originally RW global variable, need additional initialize here*/
+ //dbg_print("SIM_DEFAULT_TOUT_VALUE = %x\r\n",SIM_DEFAULT_TOUT_VALUE);
+
+ SimCard->TOUTValue = SIM_DEFAULT_TOUT_VALUE << 2;
+
+ SimCard->TOUT_Factor = 1;
+ SimCard->PTS_check = KAL_TRUE;
+
+ SimCard->Fi = 372;
+
+ SimCard->EF_ICCID_Selected = KAL_FALSE;
+ //DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ DRV_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), DRV_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+
+ if (SimCard->event == NULL)
+ {
+ if (MTK_SIMIF0 == hwCtrl)
+ {
+ SimCard->event = kal_create_event_group("SIMEVT");
+ }
+ else if (MTK_SIMIF1 == hwCtrl)
+ {
+ SimCard->event = kal_create_event_group("SIMEVT2");
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ /*hisr and lisr should be different in both interfaces*/
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (sim_hisrid == NULL)
+ {
+ sim_hisrid = kal_init_hisr(SIM_HISR);
+ }
+#endif
+ //IRQ_Register_LISR(hw_cb->mtk_lisrCode, SIM_LISR_Multiple, "SIM handler");
+
+#ifdef SIM_NULLBYTE_ISSUE
+ if (NULL == (void*)SimCard->sim_nullByteIssueGPT)
+ DRV_ICC_GPTI_GetHandle(&SimCard->sim_nullByteIssueGPT);
+#if 0
+#ifdef SIM_HOT_SWAP_V2
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#endif
+#if defined(__SIM_ACTIVATION_V2__)
+ if ((void *)SimCard->gpt_handle_for_SIM_activation == NULL)
+ DRV_ICC_GPTI_GetHandle(&SimCard->gpt_handle_for_SIM_activation);
+ if ((void *)SimCard->gpio_handle_for_SIO == NULL)
+ {
+ SimCard->gpio_handle_for_SIO = DclGPIO_Open(DCL_GPIO, GPIO_SIM1_SIMIO);
+ }
+#endif
+ if (SimCard->gpt_handle == (kal_uint32)NULL)
+ DRV_ICC_GPTI_GetHandle(&SimCard->gpt_handle);
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ }
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (sim2_hisrid == NULL)
+ {
+ sim2_hisrid = kal_init_hisr(SIM2_HISR);
+ }
+#endif
+
+
+#ifdef SIM_NULLBYTE_ISSUE
+ if (NULL == (void*)SimCard->sim_nullByteIssueGPT)
+ DRV_ICC_GPTI_GetHandle(&SimCard->sim_nullByteIssueGPT);
+#if 0
+#ifdef SIM_HOT_SWAP_V2
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#endif
+#if defined(__SIM_ACTIVATION_V2__)
+ if ((void *)SimCard->gpt_handle_for_SIM_activation == NULL)
+ DRV_ICC_GPTI_GetHandle(&SimCard->gpt_handle_for_SIM_activation);
+ if ((void *)SimCard->gpio_handle_for_SIO == NULL)
+ {
+ SimCard->gpio_handle_for_SIO = DclGPIO_Open(DCL_GPIO, GPIO_SIM2_SIMIO);
+ }
+#endif
+ if (SimCard->gpt_handle == (kal_uint32)NULL)
+ DRV_ICC_GPTI_GetHandle(&SimCard->gpt_handle);
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+
+ }
+#endif
+ else
+ SIM_DEBUG_ASSERT(0);
+}
+#endif
+//================================ Layer type SIM driver start ==================================
+/*************************************************************************
+* FUNCTION
+* L1sim_Cmd_Layer
+*
+* DESCRIPTION
+* Layer type sim driver (transport layer) which maps C-APDU into C-TPDU for T=0
+*
+* PARAMETERS
+* txData: address of the tx buffer including the command header and optional tx data
+* txSize: size of data to be transfer including command buffer(5 bytes):(Lc+5) and
+ will be updated by real transfered data count.
+* rxData: address of the rx buffer
+* rxSize: expect received data size not including the sw1 and sw2 and will be updataed
+ by the real received data coung
+*
+* RETURNS
+* kal_uint16: status bytes of (sw1<<8|sw2), and 0 to indicate a physical error detected
+ by the driver such as timeout.
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+sim_status L1sim_Cmd_Layer_MTK(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb, kal_bool *isSW6263)
+{
+ kal_bool warn, case4, sim_card, isSw6310 = KAL_FALSE;
+ kal_uint8 sw1, sw2, error, gp, rs, *tx;
+ kal_uint8 sim_get_resp_sim[] = {0xa0, 0xc0, 0x00, 0x00, 0x00 }; // 0xa0: SIM, 0x00: USIM
+ sim_status status, status_w = 0;
+ kal_uint32 rx_len, rx_buf_len;
+ // sim_protocol_app_enum p = SimCard->app_proto;
+ Sim_Card *SimCard;
+ kal_uint32 count_62cb=0;
+#ifdef SIM_DRV_EXTENDED_APDU
+ kal_uint32 cur_tx_size = 0, transmitted_size = 0;
+ kal_int32 tx_left_size = *txSize;
+ kal_uint8 sim_envlelop_tx[260] = {0x0}; //5+255 data
+#endif
+ kal_uint32 num_transactions = 0, log_size = 0;
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]%s P3=%d txSize=%d, rxData%s=NULL, *rxSize=%d\n\r",
+ hw_cb->simInterface, __FUNCTION__, txData[4], *txSize, (rxData == NULL) ? "=" : "!", (rxData != NULL) ? *rxSize : 0);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_CMD_LEN,hw_cb->simInterface, txData[4], *txSize, (rxData == NULL) ? '=' : '!', (rxData != NULL) ? *rxSize : 0);
+#endif
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ /* [MAUI_03035883]clear status word 0x62xx 0x63xx flag */
+ *isSW6263 = KAL_FALSE;
+
+ if (rxData != NULL && *rxSize == 0)
+ {
+ rx_buf_len = 256;
+#ifdef SIM_DRV_EXTENDED_APDU
+ if (SimCard->cmd_case == usim_case_2E || SimCard->cmd_case == usim_case_3E || SimCard->cmd_case == usim_case_4E)
+ {
+ rx_buf_len = 2500;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] Case%d, rx_buf_len:%d\r\n", hw_cb->simInterface, SimCard->cmd_case, rx_buf_len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ }
+#endif
+ }
+ else
+ rx_buf_len = *rxSize;
+
+ if (*rxSize > 256) *rxSize = 256;
+
+ if (SimCard->cmd_case == usim_case_4)
+ {
+ case4 = KAL_TRUE;
+ *txSize -= 1; //the last byte is expected length of rxdata and shall not be sent
+ *rxSize = 0;
+ }
+#ifdef SIM_DRV_EXTENDED_APDU
+ else if (SimCard->cmd_case == usim_case_4E)
+ {
+ case4 = KAL_TRUE;
+ *txSize -= 2; //the last byte is expected length of rxdata and shall not be sent
+ *rxSize = 0;
+ }
+#endif
+ else
+ case4 = KAL_FALSE;
+ tx = txData;
+#ifdef SIM_DRV_EXTENDED_APDU
+ if (SimCard->cmd_case == usim_case_3E || SimCard->cmd_case == usim_case_4E)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] Case%d, tx_left_size:%d,transmitted_size:%d\r\n", hw_cb->simInterface, SimCard->cmd_case, tx_left_size, transmitted_size);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ sim_envlelop_tx[0] = tx[0];
+ sim_envlelop_tx[1] = 0xC2;
+ do
+ {
+ cur_tx_size = tx_left_size > 255 ? 255 : tx_left_size;
+
+ sim_envlelop_tx[4] = cur_tx_size;
+ tx_left_size = tx_left_size - 255;
+
+ sim_envlelop_tx[0] |= 0x10; //chain
+
+ kal_mem_cpy(sim_envlelop_tx + 5, txData + transmitted_size, cur_tx_size);
+ transmitted_size += cur_tx_size;
+ cur_tx_size += 5;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] %x,%x,%x,%x,%x, transmitted_size:%d,tx_left_size:%d\r\n", hw_cb->simInterface, sim_envlelop_tx[0], sim_envlelop_tx[1], sim_envlelop_tx[2], sim_envlelop_tx[3], sim_envlelop_tx[4], transmitted_size, tx_left_size);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ status = L1sim_Cmd(sim_envlelop_tx, (kal_uint16) * (&cur_tx_size), rxData, (kal_uint16*)rxSize, &error, hw_cb);
+
+
+ if (status != 0x9000 || error == KAL_TRUE)
+ {
+ break;
+ }
+ }
+ while (tx_left_size > 0);
+ *txSize = transmitted_size;
+ sim_envlelop_tx[0] &= ~0x10; //last part
+ sim_envlelop_tx[4] = 0; //last part with txsize=0
+ cur_tx_size = 5;
+ if (error != KAL_TRUE)
+ status = L1sim_Cmd(sim_envlelop_tx, (kal_uint16) * (&cur_tx_size), rxData, (kal_uint16*)rxSize, &error, hw_cb);
+
+ }
+ else
+#endif
+ status = L1sim_Cmd(tx, (kal_uint16) * txSize, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+
+
+ rx_len = *rxSize;
+ rxData += *rxSize;
+ rs = SW1_RESEND_USIM;
+ //if(SIM_PROTOCOL == p)
+ if (txData[0] == 0xA0) // some usim will compatiable with SIM after received 0xa0....
+ {
+ gp = SW1_GET_RESP_SIM;
+ sim_get_resp_sim[0] = GET_RESP_CLA_SIM;
+ sim_card = KAL_TRUE;
+ }
+ else
+ {
+ // USIM_PROTOCOL (0x61 and 0x6c are only for case2 and case4
+ gp = SW1_GET_RESP_USIM;
+ /*
+ 2009/3/28, from Nagra SMD, we should uses previouse CLA byte as the CLA of get response payload
+ Snce CLA in usim is a run time variable depends on the channl opened in card, only protocol layer knows what is correct CLA.
+ */
+ /*
+ 2011/2/11, CLA need to have a revise :
+ for version before R7, bit5 to bit8 of CLA is defined by spec; bit1 to bit 4 is from SIM task.
+ for version after R7, bit7 to bit8 of CLA is defined by spec; bit1 to bit 6 is from SIM task.
+ */
+ sim_get_resp_sim[0] = DRV_ICC_makeCLA(GET_RESP_CLA_USIM, tx[0]);
+#ifdef __KOR_CUSTOMIZATION__
+ if (((txData[0] >> 4) != 0x0) && ((txData[0] >> 4) != 0x4) && ((txData[0] >> 4) != 0x6))
+ {
+ sim_get_resp_sim[0] = txData[0];
+ }
+#endif
+ sim_card = KAL_FALSE;
+ }
+ warn = KAL_FALSE;
+ for (;;)
+ {
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000009, drv_get_current_time(), case4, status_w, status);
+ sim_printFifo(hw_cb);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ sw1 = status >> 8;
+ sw2 = status & 0xff;
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, rs, gp, sw1, sw2, status);
+#endif
+
+ if (SimCard->bypass6263 && (sw1 == SW1_WARN1 || sw1 == SW1_WARN2))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]return warning status1:%x \r\n", hw_cb->simInterface, status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ *isSW6263 = KAL_TRUE; //set 0x62xx 0x63xx flag
+ return status;
+ }
+
+ if (txData[0] == 0x80 && sw1 == SW1_GET_RESP_SIM)
+ {
+ // 0x80 is Only For UIM/CSIM CMD
+ gp = SW1_GET_RESP_SIM;
+ sim_get_resp_sim[0] = 0xA0;
+ sim_card = KAL_TRUE; // by default, 0x80 will be treated as UICC CMD
+ }
+
+ if (sw1 == gp)
+ {
+ // get response 0x61
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC4, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC4, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC4, rs, gp, sw1, sw2, status);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "get response %x\r\n", sw1);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (rxData == NULL)
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("!!! ERR NULL rx buffer\r\n");
+#endif
+ return status;
+ }
+ //add 9exx judegement
+ if (sw1 == SW1_SIM_WARN1)
+ {
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "warning status %x %x\r\n", sw1, sw2);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ *isSW6263 = KAL_TRUE; //set 0x9exx flag
+ warn = KAL_TRUE;
+ status_w = status;
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC5, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC5, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC5, rs, gp, sw1, sw2, status);
+#endif
+ }
+ tx = sim_get_resp_sim;
+ if (0 != sw2)
+ {
+ if (sw2 > (rx_buf_len - rx_len))
+ {
+ if (sim_card || rx_len == 0)
+ {
+ // P3 can < SW2 (ALPS02566156)
+ *rxSize = (rx_buf_len - rx_len);
+ tx[LEN_INDEX] = (rx_buf_len - rx_len);
+ }
+ else
+ {
+ // buffer not enough, don't send GET_RESPONSE, for passing NFC test case (ALPS02534326)
+ *rxSize = 0;
+ }
+ }
+ else
+ {
+ *rxSize = sw2;
+ tx[LEN_INDEX] = sw2;
+ }
+ }
+ else
+ {
+ if (256 > (rx_buf_len - rx_len))
+ {
+ if (sim_card || rx_len == 0)
+ {
+ // P3 can < SW2 (ALPS02566156)
+ *rxSize = (rx_buf_len - rx_len);
+ tx[LEN_INDEX] = (rx_buf_len - rx_len);
+ }
+ else
+ {
+ // buffer not enough, don't send GET_RESPONSE, for passing NFC test case (ALPS02534326)
+ *rxSize = 0;
+ }
+ }
+ else
+ {
+ *rxSize = 256;
+ tx[LEN_INDEX] = 0;
+ }
+ }
+
+ if (0 == *rxSize) /*we have to take care one condition that SIM task gave not enough space for next action*/
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Rx buffer not enough, don't send GET_RESPONSE, SW2=0x%02X, rx_buff_len=%d, rx_len=%d", sw2, rx_buf_len, rx_len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ *rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+ }
+
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000007, drv_get_current_time(), case4, status_w, status);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ if (sim_card)
+ break;
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC6, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC6, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC6, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else if (sim_card && sw1 == SW1_GET_RESP_USIM) /*this is a work around for that, a SIM card replies USIM procedure byte*/
+ {
+ // get response 0x61
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC7, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC7, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC7, rs, gp, sw1, sw2, status);
+
+ //dbg_print("0x6100 from SIM card");
+ DRV_ICC_print(hw_cb, SIM_PRINT_6100_FROM_CARD, 0, 0, 0, 0, 0);
+#endif
+
+ if (rxData == NULL)
+ {
+#if defined(SIM_DEBUG_INFO)
+ dbg_print("!!! ERR NULL rx buffer \r\n");
+#endif
+ return status;
+ }
+ tx = sim_get_resp_sim;
+ if (0 != sw2)
+ {
+ if (sw2 > (rx_buf_len - rx_len))
+ sw2 = (rx_buf_len - rx_len);
+ *rxSize = sw2;
+ tx[LEN_INDEX] = sw2;
+ }
+ else
+ {
+ if (256 > (rx_buf_len - rx_len))
+ {
+ *rxSize = (rx_buf_len - rx_len);
+ tx[LEN_INDEX] = (rx_buf_len - rx_len);
+ }
+ else
+ {
+ *rxSize = 256;
+ tx[LEN_INDEX] = 0;
+ }
+ }
+ if (0 == *rxSize) /*we have to take care one condition that SIM task gave not enough space for next action*/
+ {
+ *rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ return status;
+ }
+
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ if (error == KAL_TRUE)
+ {
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ if (sim_card)
+ break;
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC8, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC8, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC8, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else if (!sim_card && sw1 == rs)
+ {
+ // resend the previous cmd 0x6c
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC9, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC9, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC9, rs, gp, sw1, sw2, status);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "resend command %x\r\n", sw1);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (rxData == NULL)
+ {
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("!!! ERR NULL rx buffer\r\n");
+#endif
+ return status;
+ }
+ /*there is one card that keep asking host to do get response.
+ but in this case we did not prepare enough buffer, so we should check buffer size here.
+ */
+ if (sim_get_resp_sim == tx && (rx_buf_len - rx_len) < sw2)
+ {
+ break;
+ }
+
+ /*we should check the valid buffer size here*/
+ if ((NULL != rxData) && ((rx_buf_len - rx_len) < sw2))
+ {
+ break;
+ }
+
+ tx[LEN_INDEX] = sw2;
+ *rxSize = sw2;
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ /*
+ In FTA test, SIM may reply 0x62, 0x6c then we get status word 0x9000 while resend.
+ Since we have resend many CMD and got correct status word, if we return old warning status word,
+ we will make SIM task take wrong action. Here is we got success SW, we set warn as FALSE
+ */
+ if (0x9000 == status && KAL_TRUE == warn)
+ warn = KAL_FALSE;
+
+
+ /* [ALPS00315325]we should add rxSize to rx_len to record total received length */
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000010, drv_get_current_time(), case4, status_w, status);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC10, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC10, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC10, rs, gp, sw1, sw2, status);
+#endif
+ }
+ /*else if( !sim_card &&
+ case4 &&
+ (sw1 == SW1_WARN1 || sw1== SW1_WARN2 ||
+ ((status != SIM_SW_STATUS_OK )&& ((sw1&0xf0) == 0x90))
+ )
+ )*/
+ //mtk04122: modify condition for preventing recognizing normal ending status byte(0x92XX and 0x91XX) as error status
+ else if (!sim_card && case4 &&
+ (sw1 == SW1_WARN1 || sw1 == SW1_WARN2 || ((status != SIM_SW_STATUS_OK) && ((sw1 & 0xf0) == 0x90) && (sw1 != 0x91) && (sw1 != 0x92))))
+ {
+ // warning status
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC11, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC11, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC11, rs, gp, sw1, sw2, status);
+ log_size = kal_sprintf(hw_cb->dbgStr, "warning status %x %x\r\n", sw1, sw2);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (sw1 == 0x93 && sw2 == 0x00 && ((tx[1] == 0xC0) || (tx[1] == 0xC2)))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Return 9300, case4:%d, rxSize:%d,rxLen:%d", case4, *rxSize, rx_len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ return 0x9300;
+ }
+
+ // [MAUI_03035883]set status word 0x62xx 0x63xx flag
+ *isSW6263 = KAL_TRUE; //set 0x62xx 0x63xx flag
+#if defined (DTAG_WALLET_V1)
+ if (sw1 == SW1_WARN2 && sw2 == 0x10)
+ {
+ isSw6310 = KAL_TRUE;
+ // [ALPS00459948]Review DTAG requirement for multipart APDUs
+ // If we enconter status 0x6310, it is specific for DTAG wallet development
+ // we just return status to sim task and let ril drive to send get response
+ log_size = kal_sprintf(hw_cb->dbgStr, "sw1:%x, isSW6263:%d, warn:%d, isSW6310:%d, status:%x", sw1, *isSW6263, warn, isSw6310, status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ // *rxSize = rx_len; // *rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ // return status;
+ }
+#endif
+#if defined(SIM_BY_PASS_6310)
+ if (sw1 == SW1_WARN2 && sw2 == 0x10 && *rxSize != 0)
+ {
+#if defined(__SIM_NFC_GET_RESPONSE_WHEN_WARNING_SW__)
+ if(SimCard->bypass6263 == KAL_TRUE)
+ {
+#endif
+ *rxSize = rx_len; // *rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+ log_size = kal_sprintf(hw_cb->dbgStr, "1.CLA:%x, INS:%x, isSW6263:%d, warn:%d, rx_len:%d, *rxSize:%x", *txData, *(txData + 1), *isSW6263, warn, rx_len, *rxSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return 0x6310;
+#if defined(__SIM_NFC_GET_RESPONSE_WHEN_WARNING_SW__)
+ }
+#endif
+ }
+ else
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "CLA:%x, INS:%x, isSW6263:%d, warn:%d, rx_len:%d, *rxSize:%x", *txData, *(txData + 1), sw1, sw2, rx_len, *rxSize);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+ if (tx[1] == 0xC0 && (((*rxSize) == tx[LEN_INDEX] && tx[LEN_INDEX] != 0) || ((*rxSize) == 256 && tx[LEN_INDEX] == 0)))
+ {
+#if defined(__SIM_NFC_GET_RESPONSE_WHEN_WARNING_SW__)
+ if(SimCard->bypass6263 == KAL_TRUE)
+ {
+#endif
+ log_size = kal_sprintf(hw_cb->dbgStr, "Le(%d) == *rxSize(%d)\n\r", tx[LEN_INDEX], *rxSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return status;
+#if defined(__SIM_NFC_GET_RESPONSE_WHEN_WARNING_SW__)
+ }
+#endif
+ }
+ else
+ {
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "Le(%d), *rxSize(%d), tx[1](%d)\n\r", tx[LEN_INDEX], *rxSize, tx[1]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (sw1==0x62 && sw2==0xcb && tx[1] == 0xC0 && *rxSize==0)//for 0x62cb with no response
+ {
+ if(count_62cb++ > 3)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "Return 62CB Count %d", count_62cb);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return 0x62CB;
+ }
+ }
+ }
+ }
+#endif
+
+
+ warn = KAL_TRUE;
+ status_w = status;
+ tx = sim_get_resp_sim;
+ if (sw1 == SW1_WARN2 && sw2 == 0x10)
+ {
+ status_w = 0x6310;
+ }
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "DBG sw1:%x, isSW6263:%d, warn:%d, isSW6310:%d, status:%x", sw1, *isSW6263, warn, isSw6310, status_w);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ tx[LEN_INDEX] = 0;
+
+ // ALPS04975608: a SIM card replies specific SW, 9F2F
+ if (sw1 == SW1_GET_RESP_SIM && sw2 != 0x00 && sw2 != 0x04 && tx[1] == 0xC0)
+ {
+ tx[LEN_INDEX] = sw2;
+ }
+
+ if (sw1 == SW1_WARN2 && sw2 == 0x10)
+ {
+ *rxSize = 256;
+ }
+ else
+ {
+ *rxSize = 0;
+ }
+ status = L1sim_Cmd(tx, LEN_OF_CMD, rxData, (kal_uint16*)rxSize, &error, hw_cb);
+ if (error == KAL_TRUE)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000011, drv_get_current_time(), case4, status_w, status);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ else
+ {
+ rx_len += *rxSize;
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+ rxData += *rxSize;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC12, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC12, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC12, rs, gp, sw1, sw2, status);
+#endif
+ }
+ else
+ {
+ // command complete
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "command complete %x\r\n", status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ SIM_DEBUG_ASSERT(rx_len <= rx_buf_len);
+
+ *rxSize = rx_len; //*rxSize was used in every L1sim_Cmd, not a overall result, need to update it in the last
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC13, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC13, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC13, rs, gp, sw1, sw2, status);
+#endif
+ if (warn == KAL_TRUE || isSw6310 == KAL_TRUE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "DBG2 sw1:%x, sw2:%x, isSW6263:%d, warn:%d, isSW6310:%d, status:%x", sw1, sw2, *isSW6263, warn, isSw6310, status_w);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC3, 0x00000012, drv_get_current_time(), case4, status_w, status);
+#if defined(__SIM_NFC_GET_RESPONSE_WHEN_WARNING_SW__)
+ if((SW1_WARN1 != (status_w >> 8)) && (SW1_WARN2 != (status_w >> 8)))
+ {
+#endif
+ return status_w;
+#if defined(__SIM_NFC_GET_RESPONSE_WHEN_WARNING_SW__)
+ }
+#endif
+ }
+ return status;
+ }
+
+ // ALPS04975608: a SIM card replies specific SW, 9F2F, continuously, then, SIM driver sends Get Response command again and again.
+ num_transactions++;
+ if(num_transactions > 100)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "The SIM Transaction is > 100\n\r");
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->dbgStr);
+ status = SIM_SW_STATUS_FAIL;
+ return status;
+ }
+ }
+
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, sim_card, warn, case4, status_w, status);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, sim_get_resp_sim[0], error, *rxSize, rx_buf_len, rx_len);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, rs, gp, sw1, sw2, status);
+#endif
+
+ return status;
+}
+
+
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+void l1sim_init_hisr(sim_HW_cb *hw_cb)
+{
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ if (sim_hisrid == NULL)
+ {
+ sim_hisrid = kal_init_hisr(SIM_HISR);
+ }
+ }
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+ if (sim2_hisrid == NULL)
+ {
+ sim2_hisrid = kal_init_hisr(SIM2_HISR);
+ }
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+
+}
+#endif
+
+
+
+//================================ Layer type SIM driver end ==================================
+//================================SIM test code==================================
+#ifdef DEVDRV_TEST
+#undef DEVDRV_TEST
+#endif
+#ifdef DEVDRV_TEST
+kal_uint8 Volt;
+kal_uint8 resVolt;
+AtrStruct ATRInfo;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 1
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#if defined(DRV_SIM_CLKSTOP_6250B_SERIES)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /*MT6205,MT6205B,MT6218*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 1
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+void Sim_test(void)
+{
+ kal_uint8 result;
+ result = sim_Reset_MTK(SIM_30V, &resVolt, &ATRInfo);
+ if (result == SIM_NO_ERROR)
+ {
+ //dbg_print("SIM has no Error!\r\n");
+ }
+ if (result == SIM_CARD_ERROR)
+ {
+ //dbg_print("SIM CARD has something error!\r\n");
+ return;
+ }
+
+ if (result == SIM_NO_INSERT)
+ {
+ //dbg_print("SIM CARD no insert!\r\n");
+ return;
+ }
+ //dbg_print("the resVolt=%x\r\n",resVolt);
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 1
+ if (vcc_check())
+ {
+ //dbg_print("VCC check is ok\r\n");
+ // break;
+ }
+ else
+ {
+ //dbg_print("VCC check is Failed\r\n");
+ }
+#endif
+ //return;
+ CheckPinCMD();
+ //////dbg_print("=========================================\r\n");
+#if 1
+ //////dbg_print("Will be close the sim!!\r\n");
+ //delay1s(50);
+ closeSIMcmd();
+ //SIM_Reject_MTK();
+ //dbg_print("SIM is closed!!\r\n");
+#endif
+}
+#endif /* DEVDRV_TEST */
+
+#endif
+#endif //DRV_MULTIPLE_SIM
+#endif //__MTK_TARGET__
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
+
+#endif //DRV_SIM_OFF
diff --git a/mcu/driver/devdrv/usim/src/icc_switchControl_mtk_1.c b/mcu/driver/devdrv/usim/src/icc_switchControl_mtk_1.c
new file mode 100644
index 0000000..ecdea77
--- /dev/null
+++ b/mcu/driver/devdrv/usim/src/icc_switchControl_mtk_1.c
@@ -0,0 +1,6502 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * switchControl_mtk_1.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * USIM driver functions on for MTK multiple SIM controllers.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DRV_SIM_OFF
+#include "drv_comm.h"
+#include "dhl_trace.h"
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+#include "reg_base.h"
+#include "sim_drv_trc.h"
+
+#include "intrCtrl.h"
+
+#include "drv_gdma.h"
+#ifdef MTK_SLEEP_ENABLE
+ #include "sleepdrv_interface.h"
+#endif
+
+#include "sim_reg_adp.h"
+
+#include "sim_al.h"
+#include "sim_hw_mtk.h"
+
+
+#include "sim_sw_comm.h"
+#include "sim_drv_SW_API.h"
+//#include "gpt_sw.h"
+//RHR#include "gpio_sw.h"
+#include "sim_mtk.h"
+
+//#ifdef DRV_MULTIPLE_SIM
+#if (defined(DRV_SIM_ALL_SOLUTION_BUILT) || (defined(DRV_MULTIPLE_SIM) && defined(DRV_2_SIM_CONTROLLER)))
+//#ifdef MT6318
+//#include "pmic6318_sw.h"
+//#endif /*MT6318*/
+
+#if defined(__SIM_PLUS__)
+ #include "msdc_def.h"
+#endif
+
+#if defined(__USIM_DRV__)
+
+//#include "pwic.h"
+
+//#if defined(MT6223PMU)
+//#include "pmu_sw.h"
+//#endif
+//#ifdef DRV_2_SIM_CONTROLLER
+#include "sim_ctrl_al.h"
+#include "sync_data.h"
+
+
+//#endif
+#ifdef SIM_CACHED_SUPPORT
+ //RHR#include "init.h"
+ #include "cache_sw.h"
+#endif
+
+//#endif
+
+/*RHR*/
+#include "drv_features.h"
+//#include "kal_non_specific_general_types.h"
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+#include "kal_trace.h"
+#include "stack_config.h"
+#include "stdio.h"
+#include "string.h"
+/*RHR*/
+
+#include "us_timer.h" //for ust_get_current_time()
+
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ #include "hisr_config.h"
+#else
+ static kal_hisrid usim_hisrid = NULL;
+ static kal_hisrid usim2_hisrid = NULL;
+#endif
+
+/*following decalration were moved from gpt_sw.h*, we should change them to dcl form eventually*/
+//extern kal_uint8 GPTI_GetHandle(kal_uint8 *handle);
+//extern kal_bool GPTI_StartItem(kal_uint8 module,kal_uint16 tick,void (*gptimer_func)(void *),void *parameter);
+//extern void GPTI_StopItem(kal_uint8 module);
+#ifdef __TC01__
+extern void sim_drv_debug_ind_callback(kal_uint32 which_sim, kal_uint8 *buffer, kal_uint8 buffer_len);
+#endif
+
+extern kal_uint32 SIM_GetCurrentTime(void);
+extern void pmic6326_ccci_lock(kal_bool lock);
+
+static void L1usim_PowerOff(sim_HW_cb *hw_cb);
+extern void SIM_SetRXTIDE(kal_uint16 RXTIDE, sim_HW_cb *hw_cb);
+extern void SIM_SetTXTIDE(kal_uint16 _TXTIDE, sim_HW_cb *hw_cb);
+#if defined(SIM_DRV_SWITCH_MT6306)
+ extern void usim_hisr_MT6306(void);
+ extern void usim_hisr2_MT6306(void);
+ #if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ extern kal_bool sim_connectMT6306;
+ #endif
+#endif
+extern Sim_Card *SimCard;
+//extern kal_bool TS_HSK_ENABLE;
+
+#define FILE_SWITCHCONTROL1 2
+
+extern kal_uint32 hwCbArray[];
+//static usim_dcb_struct usim_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+//static Sim_Card SimCard_cb[DRV_SIM_MAX_LOGICAL_INTERFACE];
+
+//usim_dcb_struct *usim_dcb = &usim_cb[0];
+
+static kal_uint8 BWT_Factor[5] = {1, 6, 12, 24, 48}; // 372/64 = 6, 372/32 = 12, 23< 372/16 < 24
+
+
+
+#if defined(USIM_DEBUG)
+#define BUF_COUNT 1024
+kal_uint16 int_buffer[BUF_COUNT];
+kal_uint32 buf_index;
+#define PUSH_INT(a) int_buffer[(buf_index&(BUF_COUNT-1))] = a;\
+ buf_index++;
+#else
+#define PUSH_INT(a)
+#endif
+
+// have been modified since MT6290
+#ifdef SIM_CACHED_SUPPORT
+ extern kal_uint32 sim_uncachedTxBuffer0[], sim_uncachedRxBuffer0[], sim_uncachedTxBuffer1[], sim_uncachedRxBuffer1[];
+ #define GET_NCACHEDTX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedTxBuffer0; else p=(kal_uint8 *)sim_uncachedTxBuffer1;}
+ #define GET_NCACHEDRX_P(p, a) {if(0==a) p=(kal_uint8 *)sim_uncachedRxBuffer0; else p=(kal_uint8 *)sim_uncachedRxBuffer1;}
+ extern kal_uint8 uncachedDmaBuffer0[], uncachedDmaBuffer1[];//the instance is declared in icc_sim_common_mtk.c
+ #define GET_NCACHED_USIM_DMA_BUF_P(p, a) {if(0==a) p=(kal_uint8 *)uncachedDmaBuffer0; else p=(kal_uint8 *)uncachedDmaBuffer1;}
+ #define GET_NCACHED_USIM_DMA_BUF_INT(p, a) {if(0==a) p=(kal_uint32)uncachedDmaBuffer0; else p=(kal_uint32)uncachedDmaBuffer1;}
+#endif
+
+#if defined(USIM_DEBUG)
+extern void dbg_print(char * fmt, ...);
+static kal_uint32 start, end;
+kal_uint32 get_current_time(void)
+{
+ return (SIM_Reg32(0x80200230));
+}
+kal_uint32 get_duration_tick(kal_uint32 previous_time)
+{
+ kal_uint32 result, current_time;
+
+ current_time = SIM_Reg32(0x80200230);
+ if (previous_time > current_time)
+ {
+ result = 0x80000 - previous_time + current_time;
+ }
+ else
+ {
+ result = current_time - previous_time;
+ }
+ return result;
+}
+#endif
+
+// proto type
+static kal_bool usim_check_input_volt(usim_power_enum volt, sim_HW_cb *hw_cb);
+static usim_status_enum usim_process_ATR(sim_HW_cb *hw_cb);
+static void usim_process_TA1(kal_uint8 TA1, sim_HW_cb *hw_cb);
+static kal_bool usim_process_PTS(sim_HW_cb *hw_cb);
+static kal_uint32 usim_process_HISTORICAL(sim_HW_cb *hw_cb);
+static void usim_set_speed(usim_speed_enum speed, sim_HW_cb *hw_cb);
+static void usim_set_protocol(usim_protocol_enum T, sim_HW_cb *hw_cb);
+static void usim_set_timeout(kal_uint32 timeout, sim_HW_cb *hw_cb);
+static kal_bool usim_select_power(usim_power_enum ExpectVolt, sim_HW_cb *hw_cb);
+static void usim_activation(sim_HW_cb *hw_cb);
+//void usim_lisr_Multiple(void);
+void usim_lisr_Multiple(kal_uint32 v);
+static void usim_deactivation(sim_HW_cb *hw_cb) ;
+static void usim_t1end_handler(sim_HW_cb *hw_cb);
+void usim_hisr(void);
+
+extern void SIM_HISR_Multiple(void);
+extern void SIM_HISR2_Multiple(void);
+
+static void usim_rx_handler(kal_uint32 int_status, sim_HW_cb *hw_cb);
+static void usim_send_block(kal_uint8 *adrs, sim_HW_cb *hw_cb);
+static kal_bool usim_rx_block_handler(kal_uint32 *adrs, sim_HW_cb *hw_cb);
+static sim_status usim_send_i_block(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb);
+void sim_PDNDisable_MTK(sim_HW_cb *hw_cb);
+void sim_PDNEnable_MTK(sim_HW_cb *hw_cb);
+//kal_taskid kal_get_current_thread_ID(void);
+
+extern sim_env SIM_GetCurrentEnv(kal_uint32 simInterface);
+extern void L1sim_Init_MTK(sim_HW_cb *hw_cb);
+extern kal_uint8 sim_Reset_MTK(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info, sim_HW_cb *hw_cb);
+extern void L1sim_Configure_MTK(kal_uint8 clockMode, sim_HW_cb *hw_cb);
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+
+/*defines here since these functions will be called in sim_drv_SW_function.h*/
+static void usim_gpt_timeout_handler(void *parameter);
+extern void sim_PowerOff_MTK(sim_HW_cb *hw_cb);
+extern sim_status L1sim_Cmd_Layer_MTK(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb, kal_bool *isSW6263);
+//kal_bool sim_workingTaskWaiting; //this is used in Gemini projects, but sim_sw_comm.h used this, so we declared it
+
+
+#if defined(__CHAINING_TEST__)
+ kal_bool Send_IFS_REQ(kal_uint8 ifs, kal_uint8 interface);
+ void Set_IFSC(kal_uint8 ifs, kal_uint8 interface);
+#endif
+
+#if defined(__SPEED_TEST__)
+ usim_speed_enum speed_test;
+ kal_bool speed_test_enable = KAL_FALSE;
+ void Set_Speed(kal_uint8 select_speed);
+#endif
+
+sim_HW_cb *usim_get_hw_cb_from_usim_cb(usim_dcb_struct *usim_dcb)
+{
+ kal_uint32 idx;
+
+ for (idx = 0; idx < DRV_SIM_MAX_LOGICAL_INTERFACE; idx ++)
+ {
+ if (GET_USIM_CB(idx) == usim_dcb)
+ {
+ return (sim_HW_cb *)(hwCbArray[idx]);
+ }
+ }
+
+ return NULL;
+}
+
+void USIM_WAIT_EVENT_MTK(usim_dcb_struct *usim_dcb)
+{
+ kal_uint32 log_size = 0;
+ DRV_ICC_GPTI_StartItem(usim_dcb->gpt_handle, USIM_GPT_TIMEOUT_PERIOD, usim_gpt_timeout_handler, usim_dcb);
+ if (KAL_FALSE == kal_if_hisr() && KAL_FALSE == kal_query_systemInit())
+ {
+ kal_retrieve_eg_events(usim_dcb->event, USIM_EVENT, KAL_AND_CONSUME, &usim_dcb->ev_flag, KAL_SUSPEND);
+ }
+ else
+ {
+ kal_retrieve_eg_events(usim_dcb->event, USIM_EVENT, KAL_AND_CONSUME, &usim_dcb->ev_flag, 0);
+ }
+ if (usim_dcb->status != USIM_GPT_TIMEOUT)
+ {
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ }
+ else
+ {
+ // Abnormal case, should dump registers for further anaysis
+ sim_HW_cb *hw_cb = usim_get_hw_cb_from_usim_cb(usim_dcb);
+
+ if (hw_cb != NULL)
+ {
+ DRV_ICC_print_err_msg(hw_cb, "GPT TIMEOUT !!!");
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] %x, %x, %x, %x, %x, %x\n\r", hw_cb->simInterface,
+ SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK),
+ SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_STS_MTK),
+ SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), SIM_Reg32(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+
+ // clear usim_dcb->status
+ usim_dcb->status = USIM_NO_ERROR;
+ }
+}
+
+void USIM_SET_EVENT_Multiple(usim_dcb_struct *usim_dcb)
+{
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ kal_set_eg_events(usim_dcb->event, USIM_EVENT, KAL_OR);
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_check_input_volt
+*
+* DESCRIPTION
+* check if the input volt is supported by the interface device
+*
+* PARAMETERS
+* volt: voltage used by SIM card
+*
+* RETURNS
+* KAL_TRUE: it is supported
+* KAL_FALSE: not supported
+*
+* GLOBALS AFFECTED
+*
+*
+*************************************************************************/
+static kal_bool usim_check_input_volt(usim_power_enum volt, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (usim_dcb->sim_env == ME_18V_30V)
+ return KAL_TRUE;
+ if (usim_dcb->sim_env == ME_30V_ONLY && volt == CLASS_B_30V)
+ return KAL_TRUE;
+ if (usim_dcb->sim_env == ME_18V_ONLY && volt == CLASS_C_18V)
+ return KAL_TRUE;
+
+ return KAL_FALSE;
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_check_TCK
+*
+* DESCRIPTION
+* check if TCK present and the checksum of ATR is correct
+*
+* PARAMETERS
+*
+* RETURNS
+* KAL_TRUE: TCK is not present or chekcsum is correct
+* KAL_FALSE: Chekcsum is incorrect
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static kal_bool usim_check_TCK(sim_HW_cb *hw_cb)
+{
+ kal_uint32 i = 0;
+ kal_uint8 ck = 0;
+ kal_uint8 *ptr;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ ptr = usim_dcb->ATR_data;
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_CHECK_TCK, 0, 0, 0, 0, 0);
+
+ while (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK) == 0 && i++ <= 22) // 9600 etu
+ {
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+ }
+
+ if (i >= 23)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_NOT_PRESENT, 0, 0, 0, 0, 0);
+ return KAL_TRUE;
+ }
+
+ if (usim_dcb->ATR_index >= 33)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_CHECKSUM_ERR, 0, 0, 0, 0, 0);
+ return KAL_FALSE;
+ }
+
+ ptr[usim_dcb->ATR_index++] = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ for (i = 1; i < usim_dcb->ATR_index; i++) ck ^= ptr[i];
+ if (ck != 0)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_CHECKSUM_ERR, 0, 0, 0, 0, 0);
+ return KAL_FALSE;
+ }
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_TCK_CHECKSUM_OK, 0, 0, 0, 0, 0);
+
+ return KAL_TRUE;
+}
+
+
+static kal_bool usim_if_atr_valid(usim_dcb_struct *usim_dcb)
+{
+ /* ATR format: TS T0 ... Hist [TCK] */
+ kal_uint32 atr_len = 1; /* Init to be index to T0 */
+ kal_uint8 tdi, count;
+ kal_uint8 hist_count = usim_dcb->ATR_data[1] & 0xF;
+
+ if (usim_dcb->ATR_index < 2)
+ {
+ // TS, T0 is not success fully received
+ return KAL_FALSE;
+ }
+
+ do
+ {
+ tdi = usim_dcb->ATR_data[atr_len];
+
+ /* use to calc index offset to next TDi */
+ count = 1;
+
+ /* check if next TAi,TBi, TCi exist */
+ USIM_CAL_TD_COUNT(tdi, count);
+
+ /* update atr_len, it's index to T0, TDi, first Hist, TCK */
+ atr_len += count;
+
+ if (!(tdi & TDMask))
+ {
+ // TDi not exist, atr_len is index to first hist byte
+ atr_len += hist_count;
+ // Then, atr_len should be index to TCK
+ break;
+ }
+ }
+ while (atr_len < usim_dcb->ATR_index);
+
+ if (usim_dcb->ATR_index >= atr_len)
+ {
+ // Actually usim_dcb->ATR_index should be atr_len (no TCK) or atr_len+1 (with TCK)
+ return KAL_TRUE;
+ }
+ else
+ {
+ // Less ATR Data
+ return KAL_FALSE;
+ }
+}
+
+
+/*************************************************************************
+* FUNCTION
+* usim_process_ATR
+*
+* DESCRIPTION
+* 1. wait all ATR characters received at HISR and put into usim_dcb->ATR_data
+* 2. Get parameters from ATR, Fi, Di, T0_support, T1_support, reset mode, WWT(T0)
+* IFSC(T1), CWI, BWI, X, U
+*
+* PARAMETERS
+* None
+* RETURNS
+* KAL_TRUE: Valid TS is received
+* KAL_FALSE: Valid TS is not received, card is not present or not supported
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static usim_status_enum usim_process_ATR(sim_HW_cb *hw_cb)
+{
+ kal_uint8 data, TD;
+ kal_bool T15;
+ kal_uint8 *ptr;
+ kal_uint32 index = 1; // skip the first TS byte
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ ptr = usim_dcb->ATR_data;
+
+ if (usim_if_atr_valid(usim_dcb) == KAL_FALSE)
+ {
+ kal_uint32 i;
+ kal_char *p;
+
+ p = hw_cb->dbgStr;
+ log_size = kal_sprintf(p, "[SIM_DRV:%d]Invalid SIM ATR= ", hw_cb->simInterface);
+ p += strlen(p);
+ for (i = 0; i < usim_dcb->ATR_index; i++)
+ {
+ log_size += kal_sprintf(p, "%02X", usim_dcb->ATR_data[i]);
+ p += 2;
+ }
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ATR,hw_cb->dbgStr);
+
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+
+
+ // get the application protocol of the sim card
+ if ((ptr[index] & 0x0f) == 0)
+ {
+ usim_dcb->app_proto = SIM_PROTOCOL; // no historical char imply SIM_PROTOCOL
+ }
+ else
+ {
+ do
+ {
+ data = ptr[index++];
+ USIM_CAL_TD_COUNT(data, index);
+ }
+ while (data & TDMask);
+ usim_dcb->hist_index = index;
+
+ if (ptr[index] == HIST_FIRST_USIM && ptr[index + 1] == HIST_SEC_USIM && ptr[index + 3] == HIST_FOUR_USIM)
+ {
+ usim_dcb->app_proto = USIM_PROTOCOL;
+ }
+ else if (ptr[index] == HIST_FIRST_USIM && ptr[index + 1] == HIST_SEC_USIM && ptr[index + 3] == 0x51 && ptr[index + 5] == HIST_FOUR_USIM)
+ {
+ //dbg_print("historycal byte error");
+ DRV_ICC_print(hw_cb, SIM_PRINT_HISTORICAL_BYTE_ERR, 0, 0, 0, 0, 0);
+ usim_dcb->app_proto = USIM_PROTOCOL;
+ }
+ else
+ usim_dcb->app_proto = SIM_PROTOCOL;
+ }
+
+ // parse the content of ATR
+ T15 = KAL_FALSE;
+ index = 1;
+ TD = ptr[index++]; //T0
+ if (TD & TAMask)
+ {
+ // TA1 (FI, DI)
+ data = ptr[index++];
+ usim_process_TA1(data, hw_cb);
+ //usim_dcb->WWT = INIT_WWT_T0*usim_dcb->Di;
+ DRV_ICC_Calc_WWT(usim_dcb->Fi, usim_dcb->Di, 10, &usim_dcb->WWT);
+ }
+ if (TD & TBMask)
+ {
+ // TB1 (PI, II) (neglect it)
+ //data = ptr[index++];
+ index++;
+ }
+ if (TD & TCMask)
+ {
+ // TC1 (N: extra guard time) (neglect it)
+ data = ptr[index++];
+ if (data != 0 && data != 255)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+ }
+ if (!(TD & TDMask))
+ {
+ usim_dcb->T0_support = KAL_TRUE;
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+
+ TD = ptr[index++]; // TD1
+ if ((TD & 0x0f) == 0)
+ usim_dcb->T0_support = KAL_TRUE;
+ else if ((TD & 0x0f) == 1)
+ usim_dcb->T1_support = KAL_TRUE;
+ else if ((TD & 0x0f) == 0x0f)
+ {
+ // T = 15 is forbidden in TD1
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+
+ if (TD & TAMask)
+ {
+ //TA2 (specific mode)
+ usim_dcb->TA2 = ptr[index++];
+ //data = ptr[index++];
+
+ usim_dcb->reset_mode = USIM_RESET_SPECIFIC;
+ // chage the clock to the one before reset.
+ }
+ if (TD & TBMask)
+ {
+ // TB2 (PI2)(neglect it)
+ index++;
+ //data = ptr[index++];
+ }
+ if (TD & TCMask)
+ {
+ // TC2 (work waiting time = 960xWIxDi etu)(T0)
+ data = ptr[index++];
+ //usim_dcb->WWT = 960*data*usim_dcb->Di;
+ DRV_ICC_Calc_WWT(usim_dcb->Fi, usim_dcb->Di, data, &usim_dcb->WWT);
+ }
+
+ //dbg_print("WWT: %d \r\n",usim_dcb->WWT);
+
+ if (!(TD & TDMask))
+ {
+ if (usim_dcb->T0_support && !usim_dcb->T1_support && !T15)
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ else
+ {
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+ else
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ }
+ }
+
+ TD = ptr[index++]; // TD2
+ if ((TD & 0x0f) == 1)
+ {
+ usim_dcb->T1_support = KAL_TRUE;
+ }
+ else if ((TD & 0x0f) == 0x0f)
+ {
+ T15 = KAL_TRUE;
+ goto global_interface;
+ }
+ if (TD & TAMask)
+ {
+ //TA3 (ISFC)
+ data = ptr[index++];
+ usim_dcb->ifsc = data;
+ //dbg_print("IFSC: %d \r\n",data);
+ }
+ if (TD & TBMask)
+ {
+ kal_uint8 cwi, bwi;
+
+ // TB3 (PI2)
+ data = ptr[index++];
+ cwi = data & 0xf; // range from 0~5
+ bwi = (data & 0xf0) >> 4;
+ if (cwi > MAX_CWI)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+ if (bwi > MAX_BWI)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+ usim_dcb->CWT = (1 << cwi) + 11;
+ usim_dcb->BWT = (1 << bwi) * 960;
+ //usim_dcb->BWT = (1<<bwi)*960 + 11;
+ }
+ else
+ {
+ usim_dcb->CWT = USIM_CWT_DEFAULT;
+ usim_dcb->BWT = USIM_BWT_DEFAULT;
+ }
+
+ //dbg_print("BWT: %d \r\n",usim_dcb->BWT);
+ if (TD & TCMask)
+ {
+ // TC3 (neglect)
+ index++;
+ //data = ptr[index++];
+ }
+ if (!(TD & TDMask))
+ {
+ if (usim_dcb->T0_support && !usim_dcb->T1_support && !T15)
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ else
+ {
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+ else
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ }
+ }
+ TD = ptr[index++]; // TD3
+ if ((TD & 0x0f) != 0x0f)
+ {
+ if (usim_dcb->T0_support && !usim_dcb->T1_support && !T15)
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ else
+ {
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+ else
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ }
+ }
+
+global_interface:
+
+ if (usim_check_TCK(hw_cb) == KAL_FALSE)
+ {
+ usim_dcb->error_status = USIM_INVALID_ATR;
+ return USIM_INVALID_ATR;
+ }
+
+ if (TD & TAMask)
+ {
+ //TAi (clock stop(X) and power class(U))
+ data = ptr[index++];
+ usim_dcb->clock_stop_type = (usim_clock_stop_enum)(data & CLOCK_STOP_MSK);
+ usim_power_enum PowerClass = (usim_power_enum)(data & USIM_POW_CLASS_MSK);
+ usim_dcb->hasPowerClass = KAL_TRUE;
+ usim_dcb->PowerClass = PowerClass;
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ /*[ALPS00378979]
+ fix BJ TMC NFC fail 5_5_4_2 TC1 Power provided in full power mode (Class B)
+ */
+ {
+ if (PowerClass == CLASS_C_18V)
+ usim_dcb->power_class = CLASS_C_18V;
+ else if (PowerClass == CLASS_B_30V)
+ usim_dcb->power_class = CLASS_B_30V;
+ else
+ usim_dcb->power_class = CLASS_ALLSUPPORT;
+ }
+ else
+ {
+ usim_dcb->power_class = (usim_power_enum)(data & USIM_POW_CLASS_MSK);
+ }
+ //dbg_print("clock stop[7:8]|power class[1:6]: %x \r\n",data);
+
+ /*SIM task need following information for UICC identification*/
+ usim_dcb->TAiExist = KAL_TRUE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC50, data, usim_dcb->clock_stop_type, usim_dcb->power_class, usim_dcb->TAiExist, 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC50, usim_dcb->app_proto, usim_dcb->sim_env, usim_dcb->power, usim_dcb->power_in, usim_dcb->power_class);
+ }
+ else
+ {
+ //from latest 7816-3, if ATR is valid without class indicator, host should continue normal operation
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+
+ if (TD & TBMask)
+ {
+ data = ptr[index];
+ usim_dcb->TB15 = data;
+ }
+
+#if defined(SIM_DRV_IC_USB)
+ if (TD & TBMask && usim_dcb->forceISO == KAL_FALSE)
+ {
+ // TBi indicate supporting IC-USB interface
+ data = ptr[index++];
+ if ((data & TB15_ICUSB_MASK) == TB15_ICUSB_MASK)
+ {
+ usim_dcb->isIcUsb = KAL_TRUE;
+ usim_dcb->TB15 = data;
+ }
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC51, data, usim_dcb->clock_stop_type, usim_dcb->power_class, usim_dcb->TAiExist, usim_dcb->isIcUsb);
+ }
+ else
+ {
+ usim_dcb->isIcUsb = KAL_FALSE;
+ }
+#endif
+
+ // check if used power is supported by the UICC
+ if ((usim_dcb->power & usim_dcb->power_class) == 0)
+ {
+ if (usim_dcb->sim_env == ME_18V_30V)
+ {
+ if (usim_dcb->power == CLASS_C_18V)
+ usim_dcb->power = CLASS_B_30V;
+ else if (usim_dcb->power == CLASS_B_30V)
+ usim_dcb->power = CLASS_C_18V;
+ //dbg_print("USIM_VOLT_NOT_SUPPORT\r\n");
+ usim_dcb->error_status = USIM_VOLT_NOT_SUPPORT;
+ return USIM_VOLT_NOT_SUPPORT;
+ }
+ }
+ else if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ usim_dcb->error_status = USIM_NO_ERROR;
+ return USIM_NO_ERROR;
+ }
+ usim_dcb->error_status = USIM_NO_ERROR;
+
+ return USIM_NO_ERROR;
+}
+/*************************************************************************
+* FUNCTION
+* usim_process_TA1
+*
+* DESCRIPTION
+ 1.
+Get Di and Fi from TA1
+*
+* PARAMETERS
+ TA1: first interface character used to indicate the Fi and Di
+
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* usim_dcb->Fi, usim_dcb->Di
+*
+*************************************************************************/
+static void usim_process_TA1(kal_uint8 TA1, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (TA1 == ATR_TA1_64)
+ {
+ //dbg_print("SPEED64 \r\n");
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 8;
+ usim_dcb->card_speed = SPEED_64;
+ }
+ else if (TA1 == ATR_TA1_32)
+ {
+ //dbg_print("SPEED32 \r\n");
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 16;
+ usim_dcb->card_speed = SPEED_32;
+ }
+ else if (TA1 == ATR_TA1_16)
+ {
+ // only support speed32 even encounter a speed16 card
+ //dbg_print("SPEED16 \r\n");
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 32;
+ usim_dcb->card_speed = SPEED_16;
+
+ }
+ else if (TA1 == ATR_TA1_8)
+ {
+ //dbg_print("SPEED8 \r\n");
+ usim_dcb->Fi = 512;
+ usim_dcb->Di = 64;
+ usim_dcb->card_speed = SPEED_8;
+ }
+
+ else if (((TA1 & 0xF0) == 0x70) || ((TA1 & 0xF0) == 0x80)\
+ || ((TA1 & 0xF0) == 0xE0) || ((TA1 & 0xF0) == 0xF0)\
+ || ((TA1 & 0x0F) == 0x00) || ((TA1 & 0x0F) == 0x0A)\
+ || ((TA1 & 0x0F) == 0x0B) || ((TA1 & 0x0F) == 0x0C)\
+ || ((TA1 & 0x0F) == 0x0D) || ((TA1 & 0x0F) == 0x0E)\
+ || ((TA1 & 0x0F) == 0x0F))
+ {
+ usim_dcb->Fi = 372;
+ usim_dcb->Di = 1;
+ usim_dcb->card_speed = SPEED_RFU;
+ }
+ else
+ {
+ //dbg_print("SPEED372 \r\n");
+ usim_dcb->Fi = 372;
+ usim_dcb->Di = 1;
+ usim_dcb->card_speed = SPEED_372;
+ }
+
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_process_PTS
+*
+* DESCRIPTION
+* 1. Perform the PTS to select the protocol and enhanced speed parameter(Fn,Dn).
+ T1 has higher priority than T0
+* 2. Change the clock rate according to the PTS response
+* 3. Enable the T0 or T1 controller according to the PTS response
+*
+* PARAMETERS
+ None
+
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+* usim_dcb->speed
+*
+*************************************************************************/
+static kal_bool usim_process_PTS(sim_HW_cb *hw_cb)
+{
+ kal_uint32 i;
+ kal_uint8 pts[PPS_LEN] = {0}, pts_r[PPS_LEN] = {0}, pck;
+ usim_speed_enum speed;
+ kal_bool echoed = KAL_TRUE;
+ usim_dcb_struct *usim_dcb;
+ kal_uint8 pps_length = PPS_LEN;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ usim_dcb->error_status = USIM_NO_ERROR;
+
+ //dbg_print("usim_process_PTS \r\n");
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ //dbg_print("PTS not performed (SIM_PROTOCOL) \r\n");
+ echoed = KAL_FALSE;
+
+ // move codes from exit:
+ usim_dcb->phy_proto = T0_PROTOCOL;
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ return KAL_TRUE;
+ }
+ if (usim_dcb->reset_mode == USIM_RESET_SPECIFIC)
+ {
+ //dbg_print("not performed (specific mode)\r\n");
+ echoed = KAL_TRUE;
+ if (usim_dcb->TA2 & 0x10)
+ {
+ goto exit;
+ }
+ }
+ if (usim_dcb->high_speed_en)
+ {
+ if (usim_dcb->Di == 1)
+ speed = SPEED_372;
+ else if (usim_dcb->Di == 8)
+ speed = SPEED_64;
+ else if (usim_dcb->Di == 16)
+ speed = SPEED_32;
+ else if (usim_dcb->Di == 32)
+ speed = SPEED_16;
+ else if (usim_dcb->Di == 64)
+ speed = SPEED_8;
+ else
+ speed = SPEED_372;
+ }
+ else
+ {
+ speed = SPEED_372;
+ }
+ if (usim_dcb->reset_mode == USIM_RESET_SPECIFIC)
+ {
+ usim_set_speed(speed, hw_cb);
+ goto exit;
+ }
+#if defined(__SPEED_TEST__)
+ if (KAL_TRUE == speed_test_enable)
+ {
+ speed = speed_test;
+ speed_test_enable = KAL_FALSE;
+ }
+#endif
+ //dbg_print("select speed %d(372:64:32, 0:1:2)\r\n", speed);
+
+ // generate PTS packet
+ pts[PPSS] = 0xff;
+ pck = 0xff;
+ pts[PPS0] = USIM_PTS_PS1_MSK;
+
+ /*******************************************************************************************/
+//mtk04122: due to the stability considerations, we use T1 physical protocol when card only supports T1
+// However, in test mode, we still need to verify T1 functionailiy. Hence, we add a compiler flag
+// only used in test mode for T1 testing.
+ /*******************************************************************************************/
+#if !defined(__T1_HIGT_PRIORITY__)
+ if (usim_dcb->T1_support && usim_dcb->app_proto == USIM_PROTOCOL && !usim_dcb->T0_support) // priority T1 > T0
+#else
+ if (usim_dcb->T1_support && usim_dcb->app_proto == USIM_PROTOCOL) //modified by MTK04122
+#endif
+ {
+ // T1 only usim card will go to here
+ //dbg_print("select T=1\r\n");
+ pts[PPS0] |= USIM_PTS_PS0_T1;
+ }
+ else
+ {
+ //dbg_print("select T=0\r\n");
+ }
+
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && usim_dcb->forceISO == KAL_FALSE)
+ {
+ pts[PPS0] = 0x2F;
+ }
+#endif
+
+ pck ^= pts[PPS0];
+ if (speed == SPEED_372)
+ pts[PPS1] = ATR_TA1_372_5;
+ else if (speed == SPEED_64)
+ pts[PPS1] = ATR_TA1_64;
+ else if (speed == SPEED_32) // SPEED_32
+ pts[PPS1] = ATR_TA1_32;
+ else if (speed == SPEED_16) // SPEED_16
+ pts[PPS1] = ATR_TA1_16;
+ else if (speed == SPEED_8) // SPEED_8
+ pts[PPS1] = ATR_TA1_8;
+
+
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && usim_dcb->forceISO == KAL_FALSE)
+ {
+ pts[PPS1] = 0xC0;
+ }
+#endif
+
+ pck ^= pts[PPS1];
+
+ // send PTS packet
+ usim_dcb->main_state = PTS_STATE;
+ pts[PCK] = pck;
+ if (usim_dcb->card_speed == SPEED_RFU)
+ {
+ pts[PPSS] = 0xFF;
+ pts[PPS0] = 0x00;
+ pts[PPS1] = 0xFF;
+ pps_length = 3;
+ }
+ SIM_FIFO_Flush();
+
+ SIM_SetRXTIDE(pps_length, hw_cb);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK,SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK) | SIM_STS_RXERR);
+ for (i = 0; i < pps_length; i++)
+ {
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), pts[i]);
+ ////dbg_print("%d: %x\r\n",i,pts[i]);
+ }
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ usim_set_timeout(0, hw_cb);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ if (usim_dcb->ev_status != USIM_NO_ERROR)
+ {
+ echoed = KAL_FALSE;
+ if(usim_dcb->ev_status == USIM_RX_INVALID)
+ {
+ usim_dcb->error_status = USIM_PTS_RX_INVALID;
+ }
+ else if(usim_dcb->ev_status == USIM_BWT_TIMEOUT)
+ {
+ usim_dcb->error_status = USIM_PTS_TIMEOUT;
+ }
+ else
+ {
+ usim_dcb->error_status = USIM_PTS_FAIL;
+ }
+ }
+ // read the response
+ if (echoed)
+ {
+ for (i = 0; i < pps_length; i++)
+ {
+ pts_r[i] = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ if (pts[i] != pts_r[i])
+ {
+ echoed = KAL_FALSE;
+ usim_dcb->error_status = USIM_PTS_RX_INVALID;
+ }
+ }
+ }
+#if defined(SIM_DRV_IC_USB)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC71, usim_dcb->isIcUsbRecPPS, echoed, usim_dcb->ev_status, usim_dcb->isIcUsb, 0);
+#endif
+
+ if (echoed)
+ {
+ //dbg_print("PTS OK!\r\n");
+ usim_set_speed(speed, hw_cb);
+ // Some high speed SIM card after clock rate change have to wait a while to
+ // to receive the first command.
+ if (pts[1] != 0x00)
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+ }
+ else
+ {
+ DRV_ICC_print_err_msg(hw_cb, "PPS exchange fail");
+ usim_set_speed(SPEED_372, hw_cb);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC71, pts[0], pts[1], pts[2], pts[3], 0);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC71, pts_r[0], pts_r[1], pts_r[2], pts_r[3], 0);
+ }
+
+exit:
+ // GSM will only use T=0, no matter t=1 is supported.
+#if !defined(__T1_HIGT_PRIORITY__)
+ if (usim_dcb->T1_support && !usim_dcb->T0_support &&
+ (usim_dcb->app_proto == USIM_PROTOCOL) && echoed)
+#else
+ if (usim_dcb->T1_support &&
+ (usim_dcb->app_proto == USIM_PROTOCOL) && echoed)
+#endif
+ {
+ // T1 only usim card will go to here
+ usim_dcb->phy_proto = T1_PROTOCOL;
+ usim_set_protocol(T1_PROTOCOL, hw_cb);
+ USIM_DISABLE_TXRX_HANSHAKE();
+ SIM_SetRXRetry(0);
+ SIM_SetTXRetry(0);
+ }
+ else
+ {
+ usim_dcb->phy_proto = T0_PROTOCOL;
+ if (usim_dcb->app_proto == USIM_PROTOCOL && echoed)
+ usim_set_protocol(T0_PROTOCOL, hw_cb); // SIM_PROTOCOL is enabled at simd.c
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ }
+#if defined(__DBG_MSG__)
+ //dbg_print("phy_proto = %d\r\n",usim_dcb->phy_proto);
+#endif
+
+ return echoed;
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_set_timeout
+*
+* DESCRIPTION
+* setup the timeout value in the unit of etu
+*
+* PARAMETERS
+* timeout: timeout value in the unit of etu , 0 means disabling timeout
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void usim_set_timeout(kal_uint32 timeout, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (timeout)
+ {
+ //timeout >>= 4; //the unit of mt6290 is 16 etu (use TOUT_REG_V2)
+ timeout >>= 2; //(use TOUT_REG_V3)
+ SIM_SetTOUT(timeout + TOUT_OFFSET, hw_cb);
+ usim_dcb->timeout = timeout + TOUT_OFFSET;
+ }
+ else
+ {
+ USIM_DISABLE_TOUT();
+ }
+}
+/*************************************************************************
+* FUNCTION
+* usim_set_speed
+*
+* DESCRIPTION
+* setup the baudrate of the SIM card, only support 372, 64 and 32.
+* speed 16 is not supported, use speed32 insteadly.
+*
+* PARAMETERS
+* timeout: timeout value in the unit of etu , 0 means disabling timeout
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void usim_set_speed(usim_speed_enum speed, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div7;
+#elif defined(SIM_DRV_4_33MHZ_SCLK)
+ kal_uint32 clk_div = SIM_BRR_CLK_Div8;
+#else
+ kal_uint32 clk_div = SIM_BRR_CLK_Div4;
+#endif
+ kal_uint32 log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ if (hw_cb->canUse_4_33_SCLK == KAL_TRUE)
+ {
+ clk_div = SIM_BRR_CLK_Div6;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]Set SIM clock to 4.33MHz\n\r",hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+#endif
+
+ if (hw_cb->SlowClock == KAL_TRUE)
+ {
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ clk_div = SIM_BRR_CLK_Div16;
+#else
+ clk_div = SIM_BRR_CLK_Div8;
+#endif
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]Set Slow CLK speed!!!!\n\r",hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON) // use origianl frequency for warm reset, PPS Exchange
+ {
+ clk_div = DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK) & ~SIM_BRR_ETUMSK;
+ }
+
+ switch (speed)
+ {
+ case SPEED_372:
+ // clock: 13/4 = 3.25M, with default etu F/372
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div372));
+ break;
+ case SPEED_64:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div64));
+ break;
+ case SPEED_32:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div32));
+ break;
+ case SPEED_16:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div16));
+ break;
+ case SPEED_8:
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK, (clk_div | SIM_BRR_BAUD_Div8));
+ break;
+
+ default:
+ SIM_DEBUG_ASSERT(0);
+ }
+ usim_dcb->speed = speed;
+ usim_dcb->BWT = usim_dcb->BWT * BWT_Factor[speed] + 11;
+}
+/*************************************************************************
+* FUNCTION
+* usim_set_protocol
+*
+* DESCRIPTION
+* setup the physical protocol layer including T=0 and T=1.
+*
+* PARAMETERS
+* T: physical protocol layer including T=0 and T=1.
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void usim_set_protocol(usim_protocol_enum T, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (T == T1_PROTOCOL)
+ {
+ USIM_ENABLE_T1();
+ }
+ else
+ {
+ USIM_ENABLE_T0();
+ }
+ usim_dcb->phy_proto = T;
+}
+/*************************************************************************
+* FUNCTION
+* usim_select_power
+*
+* DESCRIPTION
+ 1. Try the input voltage from application layer if availabe.
+ 2. Try the possible voltage which the ME can support.
+ 3. Get the valid TS
+*
+* PARAMETERS
+ 1. ExpectVolt: application layer give a expected power class
+
+* RETURNS
+* KAL_TRUE: Valid TS is received
+* KAL_FALSE: Valid TS is not received, card is not present or not supported
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static kal_bool usim_select_power(usim_power_enum ExpectVolt, sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ // dbg_print("usim_select_power with power: %d \r\n", ExpectVolt);
+
+ SIM_FIFO_Flush();
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ {
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE004, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ usim_deactivation(hw_cb);
+ // decide the initial power class
+ usim_dcb->power_in = ExpectVolt;
+ if (ExpectVolt != UNKNOWN_POWER_CLASS)
+ {
+ usim_dcb->power = ExpectVolt;
+ }
+ else
+ {
+ if (usim_dcb->sim_env == ME_30V_ONLY)
+ {
+ usim_dcb->power = CLASS_B_30V;
+ }
+ else // ME_18_ONLY, ME_18V_30V
+ {
+ usim_dcb->power = CLASS_C_18V;
+ }
+ }
+ }
+ // start from low power class to high, if no ATR received, try another power class
+ // if the an invalid TS byte is received, change the convention with the same power class
+ retry = 0;
+ while (retry++ < 3)
+ {
+ //2007_04_12, some 3G card will give wrong ATR in the first time, and we should reset it twice
+ //If we don't reset these 2 variables, former wrong path will affect next time we process ATR
+ usim_set_speed(SPEED_372, hw_cb);
+ usim_dcb->abort = usim_dcb->resync = KAL_FALSE;
+ usim_activation(hw_cb);
+ //dbg_print("Enter wait event...\r\n");
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE009, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ if (usim_dcb->ev_status == USIM_NO_ERROR)
+ {
+ // a correct TS byte is received
+ //dbg_print("Correct TS byte is received\r\nEnter wait event...\r\n");
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ if (usim_dcb->present == KAL_FALSE)
+ {
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_ALLOFF);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC130, hw_cb->simInterface, __LINE__, 0, 0, 0);
+ return KAL_FALSE;
+ }
+#endif // #if defined(__SIM_HOT_SWAP_SUPPORT__)
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+ // all ATR characters are received
+ if (usim_dcb->ev_status != USIM_ATR_REC)
+ {
+ return KAL_FALSE;
+ }
+ else
+ {
+ return KAL_TRUE;
+ }
+ }
+ else if (usim_dcb->ev_status == USIM_ATR_REC)
+ {
+ // all ATR characters are received
+ return KAL_TRUE;
+ }
+ else if (usim_dcb->warm_rst == KAL_TRUE)
+ {
+ //dbg_print("warm reset fail!!\r\n");
+ usim_deactivation(hw_cb);
+ return KAL_FALSE;
+ }
+ else if ((usim_dcb->ev_status == USIM_TS_INVALID || usim_dcb->ev_status == USIM_RX_INVALID)
+ && (usim_dcb->dir == USIM_DIRECT))
+ {
+ // try another convention
+ usim_dcb->dir = (USIM_INVERSE == usim_dcb->dir) ? USIM_DIRECT : USIM_INVERSE;
+ usim_deactivation(hw_cb);
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE00A, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ //dbg_print("change another convention %d !!\r\n", usim_dcb->dir);
+ }
+ else if (usim_dcb->ev_status == USIM_NO_ATR || usim_dcb->ev_status == USIM_BWT_TIMEOUT ||
+ usim_dcb->ev_status == USIM_GPT_TIMEOUT ||
+ (usim_dcb->ev_status == USIM_TS_INVALID || usim_dcb->ev_status == USIM_RX_INVALID))
+ {
+#if defined(__DBG_MSG__)
+ //dbg_print("some error...!!\r\n");
+#endif
+ retry = 0;
+ usim_dcb->dir = USIM_DIRECT;
+ // deactivate and delay
+ usim_deactivation(hw_cb);
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE00B, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+ // change another power class if availabe, no retry with the same power class
+ if (usim_dcb->sim_env == ME_18V_30V)
+ {
+ if (usim_dcb->power_in == UNKNOWN_POWER_CLASS && usim_dcb->power == CLASS_C_18V)
+ {
+ usim_dcb->power = CLASS_B_30V;
+ }
+ else if (usim_dcb->power_in != UNKNOWN_POWER_CLASS && usim_dcb->power_in == usim_dcb->power)
+ {
+ if (usim_dcb->power_in == CLASS_C_18V)
+ usim_dcb->power = CLASS_B_30V;
+ else
+ usim_dcb->power = CLASS_C_18V;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+ ////dbg_print("continue select power loop...!!\r\n");
+ }
+ else
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ }
+ return KAL_FALSE;
+}
+/*************************************************************************
+* FUNCTION
+* usim_activation
+*
+* DESCRIPTION
+* Perform the activation of USIM
+* It is a cold reset
+* select the power according to usim_dcb->power (input)
+* select the convention according to usim_dcb->dir (input)
+* the clock rate adopted is SPEED_372
+* set the default timeout value
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void usim_activation(sim_HW_cb *hw_cb)
+{
+ kal_uint16 reg = 0;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ // dbg_print("usim_activation, pow = %d, dir: %d \r\n",usim_dcb->power, usim_dcb->dir);
+
+ /*extract from above*/
+ if (usim_dcb->power == CLASS_B_30V)
+ {
+ reg = SIM_CONF_SIMSEL;
+#ifdef __FPGA__
+#else
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(0, CLASS_B_30V);
+ //dbg_print("VSIM0 select 3.0V\n\r");
+ }
+ else
+ {
+ DRV_ICC_PMU_setVolt(1, CLASS_B_30V);
+ //dbg_print("VSIM1 select 3.0V\n\r");
+ }
+#endif
+ }
+ else
+ {
+ reg &= ~SIM_CONF_SIMSEL;
+#ifdef __FPGA__
+#else
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_setVolt(0, CLASS_C_18V);
+ //dbg_print("VSIM0 select 1.8V\n\r");
+ }
+ else
+ {
+ DRV_ICC_PMU_setVolt(1, CLASS_C_18V);
+ //dbg_print("VSIM1 select 1.8V\n\r");
+ }
+#endif
+ }
+
+ if (usim_dcb->dir == USIM_DIRECT)
+ {
+ //reg |= SIM_CONF_Direct;
+ reg &= ~(SIM_CONF_CONV);
+ }
+ else
+ {
+ //reg |= SIM_CONF_InDirect;
+ reg |= SIM_CONF_CONV;
+ }
+
+ if (KAL_TRUE == usim_dcb->ts_hsk_en)
+ {
+ reg |= (SIM_CONF_TXHSK | SIM_CONF_RXHSK);
+ SIM_SetRXRetry(1);
+ SIM_SetTXRetry(1);
+ }
+ else
+ {
+ SIM_SetRXRetry(0);
+ SIM_SetTXRetry(0);
+ }
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_CONF_MTK, reg);
+
+ SIM_FIFO_Flush();
+ SIM_SetRXTIDE(2, hw_cb); // generate a interrupt while TS byte and T0 is received
+ //Clear IRQ STS
+ reg = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, reg);
+
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ usim_set_timeout(INIT_WWT_T0, hw_cb); /* In case of card only response 1 byte, we need TOUT here */
+
+ // Enable IRQ
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, USIM_IRQEN_ATR | SIM_IRQEN_RXERR | SIM_IRQEN_TOUT);
+#if defined(__SIM_DRV_SET_OE_BEFOR_PWRON__)
+ SIM_SET_OE_BIT() ;
+#else
+ SIM_CLR_OE_BIT() ;
+#endif
+ usim_dcb->main_state = ACTIVATION_STATE;
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ {
+#if defined(__SIM_ACTIVATION_V2__)
+ if (usim_dcb->activation_v2 == KAL_TRUE)
+ {
+ DclGPIO_Control(usim_dcb->gpio_handle_for_SIO, GPIO_CMD_SET_MODE_0, NULL);
+ MO_Sync();
+ }
+#endif
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+#endif
+#if !defined( __FPGA__)
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_TRUE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_TRUE);
+ }
+#endif
+ sim_addMsg(SIM_DRIVER_ACT, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#if defined(SIM_DRV_GEMINI_WITH_MT6306)
+ sim_MT6306_VCCCtrl(hw_cb, 1);
+#endif
+ USIM_POW_ON();
+#if defined(__SIM_ACTIVATION_V2__)
+ if (usim_dcb->activation_v2 == KAL_TRUE)
+ {
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle_for_SIM_activation);
+ DRV_ICC_GPTI_StartItem(usim_dcb->gpt_handle_for_SIM_activation, 1, usim_gpt_timeout_handler_for_SIM_activation, hw_cb);
+ }
+#endif
+ }
+ else
+ {
+ USIM_WRST();
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+ }
+ // go to usim_hisr of case RXTIDE, ATRERR, RXERR(parity error)
+}
+
+//void usim_lisr_Multiple(void)
+void usim_lisr_Multiple(kal_uint32 v)
+{
+ sim_HW_cb *hw_cb;
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(0)]);
+ usim_dcb_struct * usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ IRQMask(hw_cb->mtk_lisrCode);
+ if (usim_dcb->phy_proto==T1_PROTOCOL)
+ {
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(USIM_HISR);
+#else
+ kal_activate_hisr(usim_hisrid);
+#endif
+ }
+ else
+ {
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (usim_dcb->simInitialized==KAL_TRUE)
+ kal_activate_hisr_index(SIM_HISR);
+ else
+ kal_activate_hisr_index(USIM_HISR);
+#else
+ kal_activate_hisr(sim_hisrid);
+#endif
+ }
+}
+
+//void usim_lisr2_Multiple(void)
+void usim_lisr2_Multiple(kal_uint32 v)
+{
+ sim_HW_cb *hw_cb;
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(1)]);
+ usim_dcb_struct * usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ IRQMask(hw_cb->mtk_lisrCode);
+ if (usim_dcb->phy_proto==T1_PROTOCOL)
+ {
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ kal_activate_hisr_index(USIM2_HISR);
+#else
+ kal_activate_hisr(usim2_hisrid);
+#endif
+ }
+ else
+ {
+#if defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (usim_dcb->simInitialized==KAL_TRUE)
+ kal_activate_hisr_index(SIM2_HISR);
+ else
+ kal_activate_hisr_index(USIM2_HISR);
+#else
+ kal_activate_hisr(sim2_hisrid);
+#endif
+ }
+}
+/*************************************************************************
+* FUNCTION
+* usim_deactivation
+*
+* DESCRIPTION
+* 1. deactivate the UICC card
+* 2. wait util the the deactivation is complete
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb->main_state
+*
+*************************************************************************/
+static void usim_deactivation(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ // dbg_print("usim_deactivation\r\n");
+
+ Data_Sync_Barrier();
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON)
+ {
+ sim_addMsg(SIM_DRIVER_DEACT, hw_cb->simInterface, hw_cb->mtk_baseAddr, 0);
+ // before deactivate the SIM interface, turn on the clock first.
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ //kal_set_eg_events(usim_dcb->event, USIM_EVENT,KAL_OR);
+ sim_addMsg(SIM_DEACTIVATE_1, hw_cb->simInterface, usim_dcb->main_state, usim_dcb->ev_status);
+ DRV_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);
+ Data_Sync_Barrier();
+ SIM_Deactive();
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+ //usim_dcb->ev_status = USIM_POWER_OFF;
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ USIM_CLR_FIFO();
+ //SIM_DisAllIntr(); // disable SIMOFF INT
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ // tell USB to reset MAC & PHY
+ SIM_icusb_disableSession(hw_cb);
+ sim_addMsg(0xE005, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ }
+#endif // #if defined(SIM_DRV_IC_USB)
+
+ // turn off LDO
+#if defined(__FPGA__)
+#else // #if defined(__FPGA__)
+ Data_Sync_Barrier();
+ while (!(DRV_Reg32(hw_cb->mtk_baseAddr + SIM_ATRSTA_MTK) & 0x0001));
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ DRV_ICC_PMU_switch(0, KAL_FALSE);
+ }
+ else
+ {
+ DRV_ICC_PMU_switch(1, KAL_FALSE);
+ }
+#endif // #if defined(__FPGA__)
+
+ // Need delay of at least 10ms before next activate operation
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()))
+ {
+ // tell USB to reset MAC & PHY
+ SIM_icusb_disconnectDone(hw_cb);
+ sim_addMsg(0xE007, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ }
+#endif // #if defined(SIM_DRV_IC_USB)
+
+ sim_addMsg(SIM_DEACTIVATE_2, hw_cb->simInterface, usim_dcb->main_state, usim_dcb->ev_status);
+
+ usim_dcb->main_state = DEACTIVATION_STATE;
+ if (usim_dcb->ev_status == USIM_POWER_OFF)
+ usim_dcb->main_state = DEACTIVATION_STATE;
+ else
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC20, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), 0, 0, usim_dcb->ev_status, 0x1116);
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC20, hw_cb);
+ }
+ // else
+ // SIM_DEBUG_ASSERT(0);
+ }
+#if defined(SIM_DRV_IC_USB)
+ else
+ {
+ sim_addMsg(0xE008, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ }
+#endif
+}
+/*************************************************************************
+* FUNCTION
+* usim_t1end_handler
+*
+* DESCRIPTION
+* 1. it is called while t1end interrupt is generated.
+* 2. there are two different states in this function:
+ CMD_TX_STATE: a complete block is sent to UICC
+ CMD_RX_INF_STATE: a complete block is received from UICC
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb->main_state
+*
+*************************************************************************/
+static void usim_t1end_handler(sim_HW_cb *hw_cb)
+{
+ kal_uint32 log_size = 0;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ switch (usim_dcb->main_state)
+ {
+ case (volatile usim_main_state_enum) CMD_TX_STATE:
+ USIM_DMA_RX_TIDE();
+
+ if (usim_dcb->wtx == KAL_TRUE)
+ {
+ usim_dcb->wtx = KAL_FALSE;
+ usim_set_timeout(usim_dcb->BWT * usim_dcb->wtx_m, hw_cb);
+ }
+ else
+ usim_set_timeout(usim_dcb->BWT, hw_cb);
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ usim_dcb->main_state = CMD_RX_STATE;
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, (SIM_STS_EDCERR | SIM_STS_RXERR | SIM_STS_T1END | SIM_STS_OV | SIM_STS_TOUT));
+ break;
+ case (volatile usim_main_state_enum) CMD_RX_STATE:
+ {
+ kal_uint8 len, pcb;
+#ifdef SIM_CACHED_SUPPORT
+ kal_uint8 *dma_buffer;
+ GET_NCACHED_USIM_DMA_BUF_P(dma_buffer, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+#else
+ kal_uint8 *dma_buffer = usim_dcb->dma_buffer;
+#endif /*SIM_CACHED_SUPPORT*/
+
+
+
+ usim_set_timeout(0, hw_cb);
+ SIM_DMA_STOP(usim_dcb->dma_config.channel);
+
+ if (usim_dcb->ev_status == USIM_RX_INVALID)
+ {
+ // comes from EDC or parity error
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "usim_dcb->ev_status Status:%x\n\r", usim_dcb->ev_status);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+
+ return;
+ }
+ // receive a complete block, except a S-block received, there still is one
+ // parameter byte in the fifo
+
+ usim_dcb->header_rx[T1_NAD_INDEX] = dma_buffer[T1_NAD_INDEX]; // NAD
+ pcb = usim_dcb->header_rx[T1_PCB_INDEX] = dma_buffer[T1_PCB_INDEX]; // PCB
+ len = usim_dcb->header_rx[T1_LEN_INDEX] = dma_buffer[T1_LEN_INDEX]; // LEN
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "CMD_RX_STATE (reveive a block!! len: %d)\n\r", len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#endif
+
+#if defined (__SIM_DVT__)
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "CMD_RX_STATE (reveive a block!! len: %d)\n\r", len);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#endif /* End of #if defined (__SIM_DVT__) */
+
+ if (len)
+ {
+ if (len == 1 && USIM_IS_SBLOCK(pcb))
+ {
+ usim_dcb->header_rx[T1_INF_INDEX] = dma_buffer[T1_INF_INDEX];
+ }
+ else
+ {
+ kal_mem_cpy(usim_dcb->rx_buf + usim_dcb->rx_index, &dma_buffer[T1_INF_INDEX], len);
+ }
+ }
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ break;
+ default: // MTK04122: add default for handling error state
+ SIM_ASSERT(0);
+ break;
+ }
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print_str("\n\r");
+#endif
+}
+static void usim_timeout_handler(sim_HW_cb *hw_cb)
+{
+ kal_uint32 log_size = 0;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ switch (usim_dcb->main_state)
+ {
+ case (volatile usim_main_state_enum) ATR_STATE:
+ // may be optimized by parsing the content instead of using timeout.
+ // read the remaining bytes of ATR
+ {
+ kal_uint32 count;
+
+ count = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK);
+ while (count--)
+ {
+ if (usim_dcb->ATR_index >= 33)
+ {
+ USIM_CLR_FIFO();
+ /* maybe the atr is correct??? */
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ return;
+ }
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ }
+ usim_dcb->ev_status = USIM_ATR_REC;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "ATR TOUT, usim_dcb->ev_status:%x", usim_dcb->ev_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+ }
+ break;
+ case (volatile usim_main_state_enum) CLK_STOPPING_STATE:
+ {
+ kal_bool level;
+
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->main_state = CLK_STOPPED_STATE;
+ if (usim_dcb->clock_stop_type == CLOCK_STOP_HIGH)
+ level = KAL_TRUE;
+ else
+ level = KAL_FALSE;
+ SIM_Idle_MTK(level, hw_cb);
+ USIM_SET_EVENT_Multiple(usim_dcb);
+#ifndef __DRV_SIM_REG_ON_PDN_V2__
+ /*controller's clock must now stopped, verify it*/
+ if ((SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & 0x2) != 0x2)
+ SIM_DEBUG_ASSERT(0);
+#endif
+ SIM_DisAllIntr();
+#if defined(USIM_DEBUG)
+ end = get_duration_tick(start);
+#endif
+ USIM_low_power_related_setting(hw_cb, USIM_LP_ENABLE);
+ }
+ break;
+ case CLK_STOPPED_STATE:
+ {
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ break;
+ default:
+ SIM_DMA_STOP(usim_dcb->dma_config.channel);
+
+
+ usim_dcb->ev_status = USIM_BWT_TIMEOUT;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+}
+void usim_hisr(void)
+{
+ kal_uint32 int_status, log_size = 0;
+ sim_HW_cb *hw_cb;
+ usim_dcb_struct *usim_dcb;
+
+ /*logical SIM 1 not exactly work on physical SIM1 interface, we only know interrrupt comes from SIM1, have to find its logical */
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(0)]);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitISR = KAL_TRUE;
+ Data_Sync_Barrier();
+ kal_give_spinlock(hw_cb->spinlockid);
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306)
+ {
+#endif
+ usim_hisr_MT6306();
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+ return;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+
+ //not like Gemini project, in dual controller solution, we need 2 individual HISR and thus every HISR mapping fixed interface
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ Data_Sync_Barrier();
+ int_status = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+#if !defined(ATEST_DRV_ENABLE)
+ MD_TRC(LOG_SIM_DRV_HISR_USIM,hw_cb->simInterface, int_status, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),usim_dcb->ev_status);
+#endif
+ /*In mt6290, INT status is write clear*/
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, int_status);
+ sim_addMsg(SIM_INT_USIM, 0, int_status, usim_dcb->ev_status);
+ usim_dcb->int_status = int_status;
+ PUSH_INT(int_status);
+ if (usim_dcb->previous_state == ACTIVATION_STATE || usim_dcb->previous_state == ATR_STATE)
+ {
+ usim_dcb->previous_state = usim_dcb->main_state;
+ usim_dcb->atr_count++;
+ if (usim_dcb->atr_count > 40)
+ {
+ SIM_DisAllIntr(); // disable SIMOFF INT
+ usim_dcb->ev_status = USIM_NO_ATR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ usim_dcb->atr_count = 0;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d]SIM1 card send too many ATR data\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]SIM1 card send too many ATR data", hw_cb->simInterface);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+ goto end_of_hisr;
+ }
+ }
+ else
+ {
+ usim_dcb->previous_state = usim_dcb->main_state;
+ usim_dcb->atr_count = 0;
+ }
+#if !defined(ATEST_DRV_ENABLE)
+ if (int_status == 0xa)
+ {
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_fifo(hw_cb);
+ }
+#endif
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] usim_hisr int:%x, FIFO count = %d\r\n",int_status, SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK));
+#endif
+ if (int_status & SIM_STS_RXERR)
+ {
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] parity error \r\n");
+#endif
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "RXERR, usim_dcb->ev_status:%x, int_status:%x", usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]RXERR, usim_dcb->ev_status:%x, int_status:%x", hw_cb->simInterface, usim_dcb->ev_status, int_status);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+ if((usim_dcb->main_state == ACTIVATION_STATE) ||(usim_dcb->main_state == PTS_STATE))
+ {
+ SIM_DisAllIntr();
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ goto end_of_hisr;
+ }
+ // wait t1end interrupt
+ }
+
+ if (int_status & SIM_STS_EDCERR)
+ {
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] EDC error \r\n");
+#endif
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ }
+ if (int_status & SIM_STS_TOUT)
+ {
+ usim_timeout_handler(hw_cb);
+ goto end_of_hisr;
+ }
+ if (int_status & SIM_STS_T1END)
+ {
+ usim_t1end_handler(hw_cb);
+ }
+ if (int_status & SIM_STS_RX)
+ {
+ usim_rx_handler(int_status, hw_cb);
+ }
+ if (int_status & SIM_STS_SIMOFF)
+ {
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] Power off \r\n");
+#endif
+ usim_dcb->ev_status = USIM_POWER_OFF;
+ SIM_DisAllIntr(); // disable SIMOFF INT
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ goto end_of_hisr;
+ }
+ if (int_status & SIM_STS_TXERR || int_status & SIM_STS_OV)
+ {
+ // SIM_DEBUG_ASSERT(0); [ALPS00426103]not need assert
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "TXERR, usim_dcb->ev_status:%x, int_status:%x", usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]TXERR, usim_dcb->ev_status:%x, int_status:%x", hw_cb->simInterface, usim_dcb->ev_status, int_status);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+ }
+ if (int_status & SIM_STS_NATR)
+ {
+ usim_set_timeout(0, hw_cb);
+ SIM_DisAllIntr();
+ usim_dcb->ev_status = USIM_NO_ATR;
+ DRV_ICC_print_err_msg(hw_cb, "No ATR");
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr,"[SIM_DRV:%d]No ATR, voltage:%d",hw_cb->simInterface, usim_dcb->power);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+
+end_of_hisr:
+
+ IRQClearInt(IRQ_USIM0_CODE);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+}
+
+
+void usim_hisr2(void)
+{
+ kal_uint32 int_status, log_size = 0;
+ sim_HW_cb *hw_cb;
+ usim_dcb_struct *usim_dcb;
+
+ hw_cb = (sim_HW_cb *)(hwCbArray[sim_get_logical_from_SIMIF(1)]);
+
+ kal_take_spinlock(hw_cb->spinlockid, KAL_INFINITE_WAIT);
+ hw_cb->waitISR = KAL_TRUE;
+ Data_Sync_Barrier();
+ kal_give_spinlock(hw_cb->spinlockid);
+
+#if defined(SIM_DRV_SWITCH_MT6306)
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if (sim_connectMT6306)
+ {
+#endif
+ usim_hisr2_MT6306();
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+ return;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+ //not like Gemini project, in dual controller solution, we need 2 individual HISR and thus every HISR mapping fixed interface
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ Data_Sync_Barrier();
+ int_status = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+#if !defined(ATEST_DRV_ENABLE)
+ MD_TRC(LOG_SIM_DRV_HISR_USIM,hw_cb->simInterface, int_status, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK),usim_dcb->ev_status);
+#endif
+ /*In mt6290, INT status is write clear*/
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK, int_status);
+
+ sim_addMsg(SIM_INT_USIM, 1, int_status, usim_dcb->ev_status);
+ usim_dcb->int_status = int_status;
+ PUSH_INT(int_status);
+ if (usim_dcb->previous_state == ACTIVATION_STATE || usim_dcb->previous_state == ATR_STATE)
+ {
+ usim_dcb->previous_state = usim_dcb->main_state;
+ usim_dcb->atr_count++;
+ if (usim_dcb->atr_count > 40)
+ {
+ SIM_DisAllIntr(); // disable SIMOFF INT
+ usim_dcb->ev_status = USIM_NO_ATR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ usim_dcb->atr_count = 0;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "[SIM_DRV:%d]SIM2 card send too many ATR data\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]SIM2 card send too many ATR data", hw_cb->simInterface);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+ goto end_of_hisr;
+ }
+ }
+ else
+ {
+ usim_dcb->previous_state = usim_dcb->main_state;
+ usim_dcb->atr_count = 0;
+ }
+
+#if !defined(ATEST_DRV_ENABLE)
+ if (int_status == 0xa)
+ {
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_fifo(hw_cb);
+ }
+#endif
+ if (int_status & SIM_STS_RXERR)
+ {
+ // dbg_print("parity error \r\n");
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "RXERR, usim_dcb->ev_status:%x, int_status:%x", usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]RXERR, usim_dcb->ev_status:%x, int_status:%x", hw_cb->simInterface, usim_dcb->ev_status, int_status);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+
+ if((usim_dcb->main_state == ACTIVATION_STATE) ||(usim_dcb->main_state == PTS_STATE))
+ {
+ SIM_DisAllIntr();
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ goto end_of_hisr;
+ }
+ // wait t1end interrupt
+ }
+
+ if (int_status & SIM_STS_EDCERR)
+ {
+ ////dbg_print("EDC error \r\n");
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ }
+ if (int_status & SIM_STS_TOUT)
+ {
+ usim_timeout_handler(hw_cb);
+ goto end_of_hisr;
+ }
+ if (int_status & SIM_STS_T1END)
+ {
+ usim_t1end_handler(hw_cb);
+ }
+ if (int_status & SIM_STS_RX)
+ {
+ usim_rx_handler(int_status, hw_cb);
+ }
+ if (int_status & SIM_STS_SIMOFF)
+ {
+ ////dbg_print("Power off \r\n");
+ usim_dcb->ev_status = USIM_POWER_OFF;
+ SIM_DisAllIntr(); // disable SIMOFF INT
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ goto end_of_hisr;
+ }
+ if (int_status & SIM_STS_TXERR || int_status & SIM_STS_OV)
+ {
+ // SIM_DEBUG_ASSERT(0); [ALPS00426103]not need assert
+ usim_set_timeout(0, hw_cb);
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "TXERR, usim_dcb->ev_status:%x, int_status:%x", usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]TXERR, usim_dcb->ev_status:%x, int_status:%x", hw_cb->simInterface, usim_dcb->ev_status, int_status);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+ }
+ if (int_status & SIM_STS_NATR)
+ {
+ usim_set_timeout(0, hw_cb);
+ SIM_DisAllIntr();
+ usim_dcb->ev_status = USIM_NO_ATR;
+ DRV_ICC_print_err_msg(hw_cb, "No ATR");
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr,"[SIM_DRV:%d]No ATR, voltage:%d",hw_cb->simInterface, usim_dcb->power);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+
+end_of_hisr:
+
+ IRQClearInt(hw_cb->mtk_lisrCode);
+ IRQUnmask(hw_cb->mtk_lisrCode);
+ hw_cb->waitISR = KAL_FALSE;
+ Data_Sync_Barrier();
+}
+
+
+
+/*************************************************************************
+* FUNCTION
+* usim_rx_handler
+*
+* DESCRIPTION
+* 1. It is called byt usim_hisr
+* 2. It is called while RXTIDE interrupt is triggerred
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void usim_rx_handler(kal_uint32 int_status, sim_HW_cb *hw_cb)
+{
+ kal_uint32 log_size = 0;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ // dbg_print("[DRV] usim_rx_handler \r\n");
+
+ Data_Sync_Barrier();
+ switch (usim_dcb->main_state)
+ {
+ case (volatile usim_main_state_enum) ACTIVATION_STATE:
+ // dbg_print("ACTIVATION_STATE \r\n");
+ {
+ kal_uint8 TS = 0, T0 = 0, count = 0;
+
+ TS = SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK));
+ // dbg_print("TS = %x \r\n", TS);
+ if (TS == 0x3B || TS == 0x3F)
+ {
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ SIM_SetRXRetry(USIM_RETRY);
+ SIM_SetTXRetry(USIM_RETRY);
+ count = 0;
+ T0 = SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK));
+ usim_dcb->hist_index = T0 & 0xf; // use to contain the length of historical char (temperary)
+ USIM_CAL_TD_COUNT(T0, count);
+ //if((T0 & TDMask) == NULL)
+ if (!(T0 & TDMask))
+ {
+ count += usim_dcb->hist_index;
+ if (count >= SIM_TOTAL_FIFO_LEN)
+ {
+ usim_dcb->abort = KAL_TRUE; // for temp usage (separate two times)
+ count -= 6;
+ }
+ usim_dcb->resync = KAL_TRUE; // for temp usage (last time)
+ }
+ else
+ count++;
+ if (count == 0)
+ {
+ usim_dcb->ev_status = USIM_ATR_REC;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ else
+ {
+ usim_dcb->rx_size = count + 1; // for temp usage (index to TD byte)
+ SIM_SetRXTIDE(count, hw_cb);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), USIM_IRQEN_NORMAL);
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ }
+
+ usim_dcb->main_state = ATR_STATE;
+ usim_dcb->ATR_index = 0;
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = TS;
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = T0;
+ }
+ else
+ {
+ usim_dcb->ev_status = USIM_TS_INVALID;
+ SIM_DisAllIntr(); // prevent the following ATR bytes trigger RX interrupt
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+ DRV_ICC_print_str("[SIM_DRV]Card Error, Enter find Card Process.\n\r");
+ log_size = kal_sprintf(hw_cb->hisrDbgStr, "Check HW Waveform for HW issue. TS:%x T0:%x usim_dcb->ev_status:%x, int_status:%x", TS, T0, usim_dcb->ev_status, int_status);
+ if (log_size > 0) DRV_ICC_print_err_msg(hw_cb, hw_cb->hisrDbgStr);
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]Check HW Waveform for HW issue. TS:%x T0:%x usim_dcb->ev_status:%x, int_status:%x", hw_cb->simInterface, TS, T0, usim_dcb->ev_status, int_status);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+#if !defined(ATEST_DRV_ENABLE)
+ sim_dump_sim_pins(hw_cb);
+ sim_dump_eint(hw_cb);
+#endif
+ }
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ break;
+ case (volatile usim_main_state_enum) ATR_STATE:
+ {
+ // receive all ATR data without timeout to indicate
+ kal_uint32 count;
+ kal_uint8 TD;
+
+ count = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK);
+ // dbg_print("ATR_STATE : %d ",count);
+ while (count--)
+ {
+ if (usim_dcb->ATR_index >= 33)
+ {
+ USIM_CLR_FIFO();
+ /* maybe the atr is correct??? */
+ usim_dcb->ev_status = USIM_RX_INVALID;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ return;
+ }
+ usim_dcb->ATR_data[usim_dcb->ATR_index++] = (kal_uint8)SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_DATA_MTK);
+ }
+ if (usim_dcb->abort == KAL_TRUE)
+ {
+ usim_dcb->abort = KAL_FALSE;
+ SIM_SetRXTIDE(6, hw_cb);
+ usim_dcb->resync = KAL_TRUE;
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ DRV_ICC_GPTI_StartItem(usim_dcb->gpt_handle, USIM_GPT_TIMEOUT_PERIOD+(6*100), usim_gpt_timeout_handler, usim_dcb);
+ break;
+ }
+ if (usim_dcb->resync == KAL_FALSE)
+ {
+ TD = usim_dcb->ATR_data[usim_dcb->rx_size];
+ // dbg_print(", TD = %x ,%d ", TD,usim_dcb->rx_size);
+ count = 0;
+ USIM_CAL_TD_COUNT(TD, count);
+
+ //if((TD & TDMask) == NULL)
+ if (!(TD & TDMask))
+ {
+ count += usim_dcb->hist_index;
+ if (count >= SIM_TOTAL_FIFO_LEN)
+ {
+ // usim_dcb->rx_index = count; // for temp usage (total ATR len)
+ usim_dcb->abort = KAL_TRUE; // for temp usage (separate two times)
+ count -= 6;
+ }
+ usim_dcb->resync = KAL_TRUE; // for temp usage (last time)
+ }
+ else
+ count++;
+ usim_dcb->rx_size += (count); // for temp usage (index to TD byte)
+ SIM_SetRXTIDE(count, hw_cb);
+ DRV_ICC_GPTI_StopItem(usim_dcb->gpt_handle);
+ DRV_ICC_GPTI_StartItem(usim_dcb->gpt_handle, USIM_GPT_TIMEOUT_PERIOD+(count*100), usim_gpt_timeout_handler, usim_dcb);
+
+ }
+ else
+ {
+ usim_set_timeout(0, hw_cb);
+ // dbg_print("\r\n!! all ATR received \r\n");
+ usim_dcb->hist_index = 0;
+ usim_dcb->rx_size = 0;
+ usim_dcb->resync = KAL_FALSE;
+ usim_dcb->abort = KAL_FALSE;
+ usim_dcb->ev_status = USIM_ATR_REC;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ }
+ }
+ break;
+ case (volatile usim_main_state_enum) PTS_STATE:
+ SIM_DisAllIntr();
+ usim_dcb->ev_status = USIM_NO_ERROR;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+ break;
+ default:
+#if defined(__MSG_DBG__)
+ //dbg_print("[DRV] other state.....\r\n");
+#endif
+ //MTK04122: other states shall not invoke rx_handler
+ SIM_ASSERT(0);
+ break;
+ }
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_send_block
+*
+* DESCRIPTION
+* 1. sending a block to UICC, with header in usim_dcb->header_tx
+* 2. if len > 0 then using DMA to transfer data from tx buffer to the fifo of sim
+ interface.
+ 3. after a complete block is sent, T1END is generated
+ 4. after that, three bytes of received block header will come into rx fifo
+*
+* PARAMETERS
+ adrs: tx buffer address
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void usim_send_block(kal_uint8 *adrs, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 len, pcb;
+ kal_uint8 *header;
+ kal_uint32 pNoncachedRx;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ //usim_dcb_struct *dcb = usim_dcb;
+
+ header = usim_dcb->header_tx;
+ usim_dcb->main_state = CMD_TX_STATE;
+ USIM_CLR_FIFO();
+
+ // some old USIM cards need more time to send next SIM command
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL);
+
+ // write header into fifo
+ len = header[T1_LEN_INDEX];
+ pcb = header[T1_PCB_INDEX];
+#if defined(USIM_DEBUG)
+ {
+ dbg_print("usim_send_block [00][%x][%x]\r\n", pcb, len);
+ kal_uint32 i;
+ dbg_print("tx:");
+ if (USIM_IS_SBLOCK(pcb) && len == 1)
+ {
+ dbg_print(" %x", header[T1_INF_INDEX]);
+ }
+ else
+ {
+ for (i = 0; i < len; i++)
+ {
+ dbg_print(" %x", adrs[i]);
+ }
+ }
+ dbg_print("\r\n");
+ }
+#endif
+
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), header[T1_NAD_INDEX]);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), pcb);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), len);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COMDLEN_MTK), len);
+
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+
+ SIM_EINT_Mask(hw_cb, KAL_TRUE, __LINE__);
+
+ // transfer by DMA if the count > 12, otherwise by MCU
+ SIM_SetTXTIDE(1, hw_cb);
+ if (len > 12)
+ {
+ //dbg_print("[DRV] LEN > 12, do dma autoTx2Rx...\r\n");
+ SIM_SetRXTIDE(1, hw_cb); //set rxtide = 0
+
+
+ //enable autoTX2RX
+ SIM_SetBits32((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T1TX2RXEN);
+ GET_NCACHED_USIM_DMA_BUF_INT(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ Data_Sync_Barrier();
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)adrs); //TX buf 0
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA1Rx, pNoncachedRx); //RX buf 1
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(0) | HDCTRR_RX_SEL1(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(len) | HDCR_START1); //TX
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC1Rx, HDCR_XFER_SIZE0(USIM_DMA_MAX_SIZE) | HDCR_START1); //RX
+ Data_Sync_Barrier();
+
+
+ USIM_TX_START_T1();
+
+
+ }
+ else if (USIM_IS_SBLOCK(pcb) && len == 1)
+ {
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), header[T1_INF_INDEX]);
+
+ /********************/
+ //dma config is moved from t1endhandler to here...
+ USIM_DMA_RX_TIDE();
+ GET_NCACHED_USIM_DMA_BUF_INT(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ Data_Sync_Barrier();
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx, (kal_uint32)pNoncachedRx);
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ //SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, (HDCR_XFER_SIZE0(4) | HDCR_START1));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, HDCR_XFER_SIZE0(USIM_DMA_MAX_SIZE) | HDCR_START1);
+ Data_Sync_Barrier();
+
+ /********************/
+ USIM_TX_START_T1();
+ }
+ else
+ {
+ kal_uint32 i;
+#if defined(__DBG_MSG__)
+ //dbg_print("[DRV] LEN < 12, only do dma Rx...\r\n");
+#endif
+ for (i = 0; i < len; i++)
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DATA_MTK), adrs[i]);
+
+ /********************/
+ //dma config is moved from t1endhandler to here...
+ USIM_DMA_RX_TIDE();
+ GET_NCACHED_USIM_DMA_BUF_INT(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ Data_Sync_Barrier();
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx, pNoncachedRx);
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDCTRRx, (HDCTRR_RX_SEL0(1) |
+ HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) |
+ HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) |
+ HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32)));
+ SIM_WriteReg32(usim_dcb->dma_config.ADDR_HDMA_HDC0Rx, (HDCR_XFER_SIZE0(USIM_DMA_MAX_SIZE) | HDCR_START1));
+ Data_Sync_Barrier();
+
+ /*********************/
+ USIM_TX_START_T1();
+ }
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_STS_T1END);
+
+ SIM_EINT_Mask(hw_cb, KAL_FALSE, __LINE__);
+}
+/*
+1. send S blocks of request or response.
+2. if sending request, check if the response is correct.
+3. if sending response,
+4. EDC will be generated(tx) and removed(rx) by T1 controller
+
+id: PCB of the S block
+param: parameter of the S-block
+
+*/
+static usim_status_enum usim_send_s_block(usim_s_block_id_enum id, kal_uint8 param, sim_HW_cb *hw_cb)
+{
+ kal_uint8 *tx_buf, *rx_buf, len, t;
+ kal_bool is_resp;
+ kal_uint32 i;
+ //usim_dcb_struct *dcb = usim_dcb;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+
+ //dbg_print("usim_send_s_block id:%x, param:%d \r\n", id, param);
+ tx_buf = usim_dcb->header_tx;
+ rx_buf = usim_dcb->header_rx;
+ tx_buf[T1_NAD_INDEX] = USIM_NAD_DEFAULT;
+ tx_buf[T1_PCB_INDEX] = id;
+ //is_resp = ((id & PCB_S_RESP) != 0);
+ is_resp = (((kal_uint32)id & PCB_S_RESP) != 0) ? KAL_TRUE : KAL_FALSE;
+ usim_dcb->cmd_state = (is_resp) ? (S_BlOCK_RESP_TX) : (S_BlOCK_REQ_TX);
+ if (id == IFS_REQ || id == WTX_REQ || id == IFS_RESP || id == WTX_RESP)
+ {
+ len = 4;
+ tx_buf[T1_LEN_INDEX] = 1;
+ }
+ else
+ {
+ len = 3;
+ tx_buf[T1_LEN_INDEX] = 0;
+ }
+ tx_buf[T1_INF_INDEX] = param;
+ usim_dcb->retry = 0;
+
+ while (usim_dcb->retry++ < 3)
+ {
+ usim_send_block(¶m, hw_cb);
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+ if (usim_dcb->ev_status == USIM_NO_ERROR)
+ {
+ if (!is_resp)
+ {
+ for (t = 0, i = 0; i < len; i++)
+ t += rx_buf[i] ^ tx_buf[i];
+ if (t != PCB_S_RESP)
+ continue;
+ }
+ break;
+ }
+ }
+ if (usim_dcb->retry == 4)
+ {
+ usim_deactivation(hw_cb);
+ }
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ return USIM_NO_ERROR;
+
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_rx_block_handler
+*
+* DESCRIPTION
+* 1. process the received block including I, R, and S blocks
+* 2. prepare the next sending block header in the usim_dcb->header_tx
+*
+* PARAMETERS
+ adrs: address of the data buffer
+
+* RETURNS
+ KAL_TRUE: a valid block is received
+ KAL_FALSE: an invalid block is received
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static kal_bool usim_rx_block_handler(kal_uint32 *adrs, sim_HW_cb *hw_cb)
+{
+ kal_uint8 pcb, len;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+
+ if (usim_dcb->header_rx[T1_NAD_INDEX] != 0)
+ {
+ //dbg_print("(invlid block) invalid NAD\r\n");
+ return KAL_FALSE;
+ }
+ pcb = usim_dcb->header_rx[T1_PCB_INDEX];
+ len = usim_dcb->header_rx[T1_LEN_INDEX];
+ if (len > usim_dcb->ifsd) // 0 <= len <= IFSC (max 254)
+ return KAL_FALSE;
+#if defined(USIM_DEBUG)
+ {
+ kal_uint32 log_size = 0
+ log_size = kal_sprintf(hw_cb->dbgStr, "rx:%x %x %x", usim_dcb->header_rx[0], usim_dcb->header_rx[1], usim_dcb->header_rx[2]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (USIM_IS_SBLOCK(usim_dcb->header_rx[1]))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, " %x\r\n", usim_dcb->rx_buf[3]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+
+ }
+#endif
+ // USIM_INV_N(usim_dcb->ns);
+ if (USIM_IS_IBLOCK(pcb))
+ {
+ // I-block
+ //dbg_print("received a I-block\r\n");
+ if (pcb & PCB_I_RFU)
+ {
+ //dbg_print("(invlid block) error PCB \r\n");
+ return KAL_FALSE;
+ }
+#if defined(USIM_DEBUG)
+ {
+ kal_uint32 i, log_size = 0
+ for (i = 0; i < len; i++)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, " %x", usim_dcb->rx_buf[usim_dcb->rx_index + i]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ DRV_ICC_print_str("\r\n");
+ }
+#endif
+ if ((pcb & PCB_I_SEQ) != usim_dcb->nr)
+ {
+ //dbg_print("(invlid block) receive sequence err\r\n");
+ return KAL_FALSE;
+ }
+ if (usim_dcb->header_rx[T1_LEN_INDEX] > usim_dcb->ifsd)
+ {
+ //dbg_print("(invalid block) receive lenght > IFSD \r\n");
+ return KAL_FALSE;
+ }
+ if (usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ // must receive a S RESP not any other block
+ //dbg_print("(invalid block) must receive a S RESP not any other block \r\n");
+ return KAL_FALSE;
+ }
+
+ usim_dcb->tx_chain = KAL_FALSE;
+ USIM_INV_N(usim_dcb->nr);
+ usim_dcb->retry = 0;
+ usim_dcb->tx_size -= usim_dcb->header_tx[T1_LEN_INDEX];
+ usim_dcb->tx_index += usim_dcb->header_tx[T1_LEN_INDEX];
+ usim_dcb->rx_size -= usim_dcb->header_rx[T1_LEN_INDEX];
+ usim_dcb->rx_index += usim_dcb->header_rx[T1_LEN_INDEX];
+ if (pcb & PCB_I_M)
+ {
+ // a chaining I-block received send a R-block
+ usim_dcb->rx_chain = KAL_TRUE;
+ //dbg_print("chaining...\r\n");
+ USIM_MAKE_R_BLOCK_Multiple(PCB_R_STATUS_OK);
+ }
+ else
+ {
+ // command complete
+ //dbg_print("command complete!!\r\n");
+ usim_dcb->rx_chain = KAL_FALSE;
+ usim_dcb->retry = 0;
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ }
+ }
+ else if (USIM_IS_RBLOCK(pcb))
+ {
+ // R-block
+ //dbg_print("received a R-block\r\n");
+ if (usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ // must receive a S RESP not any other block
+ //dbg_print("(invalid block) must receive a S RESP not any other block \r\n");
+ return KAL_FALSE;
+ }
+ if (len)
+ {
+ //dbg_print("(invalid block) R block of len = %d \r\n", len);
+ return KAL_FALSE;
+ }
+ if (usim_dcb->tx_chain && (pcb & PCB_R_STATUS) == 0)
+ {
+ // receive a err free R block
+ if (((pcb & PCB_R_SEQ) << 2) == usim_dcb->ns)
+ {
+ // send next chaining block
+ if (usim_dcb->abort == KAL_TRUE)
+ {
+ /* clear abort flag */
+ usim_dcb->abort = KAL_FALSE;
+
+ /* should re-send cmd */
+ usim_dcb->tx_size += usim_dcb->tx_index;
+ usim_dcb->tx_index = 0;
+ *adrs = (kal_uint32)(usim_dcb->tx_buf + usim_dcb->tx_index);
+
+ pcb = PCB_I_M;
+ len = usim_dcb->ifsc;
+ usim_dcb->cmd_state = I_BLOCK_M1_TX;
+
+ if (usim_dcb->ns)
+ pcb |= PCB_I_SEQ;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ usim_dcb->header_tx_bak[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx_bak[T1_LEN_INDEX] = len;
+ USIM_INV_N(usim_dcb->ns);
+
+ //usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ }
+ else if (usim_dcb->tx_size != 0)
+ {
+ // normal chaining case
+ usim_dcb->retry = 0;
+ usim_dcb->tx_size -= usim_dcb->ifsc;
+ usim_dcb->tx_index += usim_dcb->ifsc;
+ *adrs = (kal_uint32)(usim_dcb->tx_buf + usim_dcb->tx_index);
+ if (usim_dcb->tx_size <= usim_dcb->ifsc)
+ {
+ pcb = 0;
+ len = usim_dcb->tx_size;
+ usim_dcb->cmd_state = I_BLOCK_M0_TX;
+ }
+ else // txSize > IFSC
+ {
+ pcb = PCB_I_M;
+ len = usim_dcb->ifsc;
+ usim_dcb->cmd_state = I_BLOCK_M1_TX;
+ }
+ if (usim_dcb->ns)
+ pcb |= PCB_I_SEQ;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ usim_dcb->header_tx_bak[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx_bak[T1_LEN_INDEX] = len;
+ USIM_INV_N(usim_dcb->ns);
+ }
+ }
+ else
+ {
+ // sending the previous I block again
+ usim_dcb->retry++;
+ usim_dcb->cmd_state = usim_dcb->cmd_state_bak;
+ usim_dcb->header_tx[T1_PCB_INDEX] = usim_dcb->header_tx_bak[T1_PCB_INDEX];
+ usim_dcb->header_tx[T1_LEN_INDEX] = usim_dcb->header_tx_bak[T1_LEN_INDEX];
+ }
+ }
+ else
+ {
+ // error handling R-Block received
+ if ((pcb & PCB_R_SEQ) << 2 != (usim_dcb->ns))
+ {
+ // previous sending sequence
+ usim_dcb->retry++;
+ usim_dcb->cmd_state = usim_dcb->cmd_state_bak;
+ usim_dcb->header_tx[T1_PCB_INDEX] = usim_dcb->header_tx_bak[T1_PCB_INDEX];
+ usim_dcb->header_tx[T1_LEN_INDEX] = usim_dcb->header_tx_bak[T1_LEN_INDEX];
+ }
+ else
+ {
+ // next sending sequence
+ // send the previous R-block again
+ usim_dcb->retry = 0;
+ return KAL_FALSE;
+ }
+ }
+ }
+ else if (USIM_IS_SBLOCK(pcb))
+ {
+ // S-block(REQ)
+ //dbg_print("receive S-block(%x)\r\n",pcb);
+ if (USIM_IS_RESP(pcb))
+ {
+ // response (only resync response block will be received.)
+ //dbg_print("receive RESP block!\r\n");
+ if (pcb == RESYNC_RESP && usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ if (len != 0)
+ {
+ //dbg_print("Invalid len of RESYNC");
+ return KAL_FALSE;
+ }
+ // resync complete (the card is reset to the initial state)
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ usim_dcb->ns = 0;
+ usim_dcb->nr = 0;
+ usim_dcb->resync = KAL_TRUE;
+ usim_dcb->retry = 0;
+ // usim_dcb->ifsc = USIM_IFSC_DEFAULT;
+ }
+ else
+ {
+ //dbg_print("receive a error S RESP,[%x]\r\n", pcb);
+ return KAL_FALSE;
+ }
+ }
+ else
+ {
+ // receiving a S-block of request
+ if (usim_dcb->header_tx[T1_PCB_INDEX] == RESYNC_REQ)
+ {
+ // must receive a S RESP not any other block
+ //dbg_print("(invalid block) must receive a S RESP not any other block \r\n");
+ return KAL_FALSE;
+ }
+
+ usim_dcb->cmd_state = S_BlOCK_RESP_TX;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb | PCB_S_RESP;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ if (len)
+ {
+ usim_dcb->header_tx[T1_INF_INDEX] = usim_dcb->header_rx[T1_INF_INDEX];
+ }
+ switch (pcb)
+ {
+ case RESYNC_REQ:
+ //dbg_print("(ERR) receive RESYNC_REQ\r\n");
+ return KAL_FALSE;
+ //break; //remove for for RVCT warning
+ case IFS_REQ:
+ //dbg_print("receive IFS_REQ\r\n");
+ if (len != 1)
+ return KAL_FALSE;
+ usim_dcb->ifsc = usim_dcb->header_rx[T1_INF_INDEX];
+ break;
+ case ABORT_REQ:
+ //dbg_print("receive ABORT_REQ\r\n");
+ if (len != 0)
+ return KAL_FALSE;
+ usim_dcb->retry = 0;
+ usim_dcb->abort = KAL_TRUE;
+ /*in the FTA test 7.3.11, after the abbort request, card will resend data, so we should reset rx_index to zero*/
+ usim_dcb->rx_index = 0;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC38, usim_dcb->tx_size, usim_dcb->tx_index, usim_dcb->rx_size, usim_dcb->rx_index, pcb);
+
+ break;
+ case WTX_REQ:
+ if (len != 1)
+ return KAL_FALSE;
+ usim_dcb->retry = 0;
+ // re-start the BWT( according to the spec, the timer should be restart after
+ // the WTX response has been sent.
+ usim_dcb->wtx = KAL_TRUE;
+ usim_dcb->wtx_m = usim_dcb->header_rx[T1_INF_INDEX];;
+ break;
+ default:
+ return KAL_FALSE;
+ }
+ }
+ }
+ else
+ {
+ //dbg_print("Invalid PCB \r\n");
+ return KAL_FALSE;
+ }
+
+ return KAL_TRUE;
+}
+/*************************************************************************
+* FUNCTION
+* usim_err_handler
+*
+* DESCRIPTION
+* 1. send R block to UICC to indicate the previous block is error at previous two retry.
+* 2. send S(RESYN) to UICC to recover the errors.
+* 3. deactivate the UICC
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+* usim_dcb->retry
+*
+*************************************************************************/
+static void usim_err_handler(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ // send R block
+ usim_dcb->retry++;
+ //dbg_print("usim_err_handler %d \r\n",usim_dcb->retry);
+ USIM_CLR_FIFO();
+ if (usim_dcb->retry < 3)
+ {
+ //dbg_print("send R block!\r\n");
+ {
+ if (usim_dcb->ev_status == USIM_RX_INVALID)
+ {
+ USIM_MAKE_R_BLOCK_Multiple(PCB_R_STATUS_EDC_ERR);
+ }
+ else
+ {
+ USIM_MAKE_R_BLOCK_Multiple(PCB_R_STATUS_OTHER_ERR);
+ }
+ }
+ }
+ else if (usim_dcb->retry < 6)
+ {
+ // next level error handling => resync
+ //dbg_print("send RESYNC REQ !\r\n");
+ USIM_MAKE_S_RESYNC_Multiple();
+ }
+ else
+ {
+ // deactivate
+ usim_deactivation(hw_cb);
+ }
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_send_i_block
+*
+* DESCRIPTION
+* 1. send I block to UICC with length of ifsc including case 1~4.
+*
+* PARAMETERS
+* 1. txData: tx buffer containing command header optional with tx data.
+* 2. txSize: length of the tx data
+* 3. rxData: rx buffer (must inluding two extra one for sw1 and sw2)
+* 4. rxSize: length of the rx data except sw1|sw2
+*
+* RETURNS
+* status bytes(SW1|SW2), 0 means a physical error.
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static sim_status usim_send_i_block(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb)
+{
+ kal_uint8 pcb, len;
+ kal_uint32 count, adrs;
+ usim_status_enum status;
+ kal_uint16 sw;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ usim_set_timeout(0, hw_cb);
+
+ //dbg_print("\r\n\r\n @@@@ usim_send_i_block @@@@\r\n");
+ do
+ {
+ status = USIM_NO_ERROR;
+ usim_dcb->tx_index = 0;
+ usim_dcb->rx_index = 0;
+ usim_dcb->tx_buf = txData;
+ if (rxData == NULL)
+ usim_dcb->rx_buf = usim_dcb->sw;
+ else
+ usim_dcb->rx_buf = rxData;
+ usim_dcb->tx_size = *txSize;
+ usim_dcb->rx_size = *rxSize + 2; // include SW1, SW2
+ usim_dcb->retry = 0;
+ usim_dcb->abort = KAL_FALSE;
+ usim_dcb->resync = KAL_FALSE;
+ usim_dcb->rx_chain = KAL_FALSE;
+
+ count = *txSize;
+ adrs = (kal_uint32)usim_dcb->tx_buf;
+ if (count <= usim_dcb->ifsc)
+ {
+ pcb = 0;
+ len = count;
+ usim_dcb->tx_chain = KAL_FALSE;
+ usim_dcb->cmd_state = I_BLOCK_M0_TX;
+ }
+ else // txSize > IFSC
+ {
+ pcb = PCB_I_M;
+ len = usim_dcb->ifsc;
+ usim_dcb->tx_chain = KAL_TRUE;
+ usim_dcb->cmd_state = I_BLOCK_M1_TX;
+ }
+ if (usim_dcb->ns)
+ pcb |= PCB_I_SEQ;
+
+ usim_dcb->cmd_state_bak = usim_dcb->cmd_state;
+ usim_dcb->header_tx[T1_NAD_INDEX] = USIM_NAD_DEFAULT;
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx_bak[T1_PCB_INDEX] = pcb;
+ usim_dcb->header_tx[T1_LEN_INDEX] = len;
+ usim_dcb->header_tx_bak[T1_LEN_INDEX] = len;
+ USIM_INV_N(usim_dcb->ns);
+
+ while (1)
+ {
+ usim_send_block((kal_uint8*)adrs, hw_cb);
+ USIM_WAIT_EVENT_MTK(usim_dcb);
+ if (usim_dcb->ev_status == USIM_NO_ERROR)
+ {
+ // a complete block is received
+ if (usim_rx_block_handler(&adrs, hw_cb) == KAL_FALSE)
+ usim_err_handler(hw_cb);
+ }
+ else
+ {
+ usim_err_handler(hw_cb);
+ }
+ if (usim_dcb->main_state == MAIN_CMD_READY_STATE)
+ {
+ // command complete
+ *rxSize = usim_dcb->rx_index;
+ break;
+ }
+ if (DEACTIVATION_STATE == usim_dcb->main_state)
+ {
+ status = USIM_DEACTIVATED;
+ break;
+ }
+
+ }
+
+ /* [ALPS00411009][MT6589][in-house FTA][UICC] 7.3.11(UICC)
+ receive s-abort request and reply s-abort resp is defined by spec. it is not error
+ if(usim_dcb->abort == KAL_TRUE)
+ {
+ status = USIM_DATA_ABORT;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC42, sw, txSize, *rxSize,status,usim_dcb->resync);
+ break;
+ }
+ */
+ if (usim_dcb->main_state == DEACTIVATION_STATE)
+ {
+ status = USIM_DEACTIVATED;
+ break;
+ }
+ }
+ while (usim_dcb->resync == KAL_TRUE);
+
+ usim_dcb->status = status;
+ if (status != USIM_NO_ERROR)
+ return SIM_SW_STATUS_FAIL;
+ // the *rxsize include the sw1 and sw1, the upper layer should prepare it.
+ *rxSize -= 2;
+ if (rxData == NULL)
+ {
+ sw = (kal_uint16)((usim_dcb->sw[0] << 8) | (usim_dcb->sw[1]));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC34, sw, *txSize, *rxSize, usim_dcb->sw[0], usim_dcb->sw[1]);
+ *rxSize = 0;
+
+ return sw;
+ }
+ sw = (rxData[*rxSize] << 8) | (rxData[*rxSize + 1]);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC30, sw, *txSize, *rxSize, 0, 0);
+
+ return sw;
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_InterfaceCheck
+*
+* DESCRIPTION
+* do platform sim interface support check, mainly on checking whether this platform support second sim interface
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void static usim_InterfaceCheck(sim_HW_cb *hw_cb)
+{
+ if (hw_cb->simInterface > 2)
+ SIM_DEBUG_ASSERT(0);
+}
+
+/*************************************************************************
+* FUNCTION
+* usim_update_sim_to_ready
+*
+* DESCRIPTION
+* 1. update the ATR informations from usim_dcb into SimCard
+* to make sim(t=0) driver work..
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+* SimCard
+* TOUTValue
+*
+*************************************************************************/
+void static usim_update_sim_to_ready(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ Sim_Card *SimCard;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ SimCard->app_proto = usim_dcb->app_proto;
+ SimCard->State = SIM_PROCESSCMD;
+ SimCard->Data_format = usim_dcb->dir;
+ if (usim_dcb->power == CLASS_B_30V)
+ SimCard->Power = SIM_30V;
+ else if (usim_dcb->power == CLASS_C_18V)
+ SimCard->Power = SIM_18V;
+ SimCard->SIM_ENV = usim_dcb->sim_env;
+ SimCard->Speed = usim_dcb->speed;
+ SimCard->clkStop = usim_dcb->clock_stop_en;
+ if (usim_dcb->clock_stop_type == CLOCK_STOP_HIGH)
+ SimCard->clkStopLevel = KAL_TRUE;
+ else if (usim_dcb->clock_stop_type == CLOCK_STOP_LOW)
+ SimCard->clkStopLevel = KAL_FALSE;
+ SimCard->sim_card_speed = (sim_card_speed_type)usim_dcb->card_speed;
+ // dbg_print("[DRV] usim_dcb->WWT = %d\r\n",usim_dcb->WWT);
+ SimCard->TOUTValue = usim_dcb->WWT >> 2; // SIM_TOUT_REG_V3
+ //SimCard->TOUTValue = usim_dcb->WWT >> 4; // SIM_TOUT_REG_V2
+ SimCard->TOUT_Factor = usim_dcb->Di;
+
+ SimCard->Fi = usim_dcb->Fi;
+
+ SimCard->power_class = usim_dcb->power_class;
+#if defined(SIM_DRV_IC_USB)
+ SimCard->isIcUsb = usim_dcb->isIcUsb;
+ SimCard->isIcUsbRecPPS = usim_dcb->isIcUsbRecPPS;
+ SimCard->uart_sim_ccci_handle = usim_dcb->uart_sim_ccci_handle;
+ SimCard->isPrefer3V = usim_dcb->isPrefer3V;
+ SimCard->forceISO = usim_dcb->forceISO;
+#endif
+ SimCard->TB15 = usim_dcb->TB15;
+ SimCard->previous_state = usim_dcb->previous_state;
+ SimCard->atr_count = usim_dcb->atr_count;
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ SimCard->poll_sim_2s = usim_dcb->poll_sim_2s;
+#endif
+#if defined(__SIM_ACTIVATION_V2__)
+ SimCard->activation_v2 = usim_dcb->activation_v2;
+#endif
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Init
+*
+* DESCRIPTION
+* 1. It is the initialization function of usim driver
+* 2. It shall be called only once.
+* 3. It gets the customization data of borad-supported voltage.
+* 4. It initialize the structure of usim control block .
+* 5. It get a GPT handler, a dma port,and register lisr, hisr, a event groug
+*
+* PARAMETERS
+ None
+
+* RETURNS
+ None
+
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static void L1usim_Init(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 hwCtrl;
+#if defined(SIM_DRV_IC_USB)
+ UART_CTRL_OPEN_T data;
+ kal_uint8 status;
+#endif
+ kal_uint8 DMA_channel = 0;
+
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ sim_addMsg(SIM_INIT_USIM, hw_cb->simInterface, 0, 0);
+ hwCtrl = sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface);
+
+ hw_cb->forceOn26M = KAL_TRUE;
+
+ if (usim_dcb->warm_rst == KAL_FALSE)
+ {
+ usim_dcb->sim_env = SIM_GetCurrentEnv(hw_cb->simInterface);
+ usim_dcb->dir = USIM_DIRECT;
+ usim_dcb->speed = SPEED_372;
+ usim_dcb->clock_stop_en = KAL_FALSE;
+ usim_dcb->clock_stop_type = CLOCK_STOP_UNKONW;
+ usim_dcb->phy_proto = T1_PROTOCOL;
+ usim_dcb->warm_rst = KAL_FALSE;
+ usim_dcb->rx_size = 0;
+ usim_dcb->rx_buf = NULL;
+ usim_dcb->tx_size = 0;
+ usim_dcb->tx_buf = NULL;
+ usim_dcb->Fi = FI_DEFAULT;
+ usim_dcb->Di = DI_DEFAULT;
+ usim_dcb->header_tx[0] = NAD;
+ usim_dcb->ts_hsk_en = KAL_TRUE;
+#if defined(__SIM_ACTIVATION_V2__)
+ usim_dcb->activation_v2 = KAL_FALSE;
+#endif
+ usim_dcb->WWT = INIT_WWT_T0;
+ usim_dcb->etu_of_1860 = (1860 / 32);
+ usim_dcb->etu_of_700 = (700 / 32);
+ usim_dcb->present = KAL_TRUE;
+ usim_dcb->power_class = UNKNOWN_POWER_CLASS;
+ usim_dcb->T0_support = KAL_FALSE;
+ usim_dcb->T1_support = KAL_FALSE;
+ usim_dcb->reset_mode = USIM_RESET_NEGOTIABLE;
+ usim_dcb->TB15 = 0;
+ usim_dcb->hasPowerClass = KAL_FALSE;
+#if defined(SIM_DRV_IC_USB)
+ usim_dcb->icusb_state = SIM_ICUSB_INIT;
+ SIM_icusb_init(hw_cb);
+#endif
+ usim_dcb->previous_state = 0;
+ usim_dcb->atr_count = 0;
+ /*there will be no enable enhanced_speed function, we should set this myself*/
+ usim_dcb->high_speed_en = KAL_TRUE;
+
+ // Set GDMA to MD Side. USIM0, USIM1 two bits
+ usim_dcb->dma_config.BURST_SIZE = HDCTRR_BST_SIZE_16;
+ usim_dcb->dma_config.DEV_BUS_WIDTH = HDCTRR_BUS_WIDTH_8;
+ usim_dcb->dma_config.MEM_BUS_WIDTH = HDCTRR_BUS_WIDTH_32;
+ DMA_channel = (MTK_SIMIF0 == hwCtrl) ? 0 : 1;
+ usim_dcb->dma_config.channel = DMA_channel;
+ usim_dcb->dma_config.ADDR_HDMA_HPRGA0Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA0R0 : REG_HDMA_HPRGA0R1;
+ usim_dcb->dma_config.ADDR_HDMA_HPRGA1Rx = (DMA_channel == 0) ? REG_HDMA_HPRGA1R0 : REG_HDMA_HPRGA1R1;
+ usim_dcb->dma_config.ADDR_HDMA_HDCTRRx = (DMA_channel == 0) ? REG_HDMA_HDCTRR0 : REG_HDMA_HDCTRR1;
+ usim_dcb->dma_config.ADDR_HDMA_HDC0Rx = (DMA_channel == 0) ? REG_HDMA_HDC0R0 : REG_HDMA_HDC0R1;
+ usim_dcb->dma_config.ADDR_HDMA_HDC1Rx = (DMA_channel == 0) ? REG_HDMA_HDC1R0 : REG_HDMA_HDC1R1;
+ usim_dcb->CWT = USIM_CWT_DEFAULT;
+ usim_dcb->BWT = USIM_BWT_DEFAULT;
+#ifdef SIM_DRV_EXTENDED_APDU
+ usim_dcb->Support_Extended_Length = KAL_FALSE;
+#endif
+ if (usim_dcb->event == NULL)
+ {
+ if (MTK_SIMIF0 == hwCtrl)
+ {
+ usim_dcb->event = kal_create_event_group("USIM_EV");
+ }
+ else if (MTK_SIMIF1 == hwCtrl)
+ {
+ usim_dcb->event = kal_create_event_group("USIM_EV2");
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ if ((kal_uint32)hw_cb != hwCbArray[hw_cb->simInterface])
+ SIM_DEBUG_ASSERT(0);
+ if (IRQ_USIM0_CODE != hw_cb->mtk_lisrCode)
+ SIM_DEBUG_ASSERT(0);
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (usim_hisrid == NULL)
+ {
+ usim_hisrid = kal_init_hisr(USIM_HISR);
+ }
+#endif
+ if ((void *)usim_dcb->gpt_handle == NULL)
+ DRV_ICC_GPTI_GetHandle(&usim_dcb->gpt_handle);
+#if defined(__SIM_ACTIVATION_V2__)
+ if ((void *)usim_dcb->gpt_handle_for_SIM_activation == NULL)
+ DRV_ICC_GPTI_GetHandle(&usim_dcb->gpt_handle_for_SIM_activation);
+ if ((void *)usim_dcb->gpio_handle_for_SIO == NULL)
+ {
+ usim_dcb->gpio_handle_for_SIO = DclGPIO_Open(DCL_GPIO, GPIO_SIM1_SIMIO);
+ }
+#endif
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+#if defined(SIM_DRV_IC_USB)
+ // only SIM1 support ICUSB
+ if (usim_dcb->uart_sim_ccci_handle == (kal_uint32)NULL)
+ {
+ usim_dcb->forceISO = KAL_FALSE;
+ data.u4OwenrId = MOD_SIM;
+ usim_dcb->uart_sim_ccci_handle = DclSerialPort_Open(uart_port_sim_ccci, 0);
+ status = DclSerialPort_Control(usim_dcb->uart_sim_ccci_handle, SIO_CMD_OPEN, (DCL_CTRL_DATA_T*)&data);
+ if (status != STATUS_OK)
+ SIM_DEBUG_ASSERT(0);
+ kal_bool indication = KAL_FALSE;
+ DclSerialPort_Control(usim_dcb->uart_sim_ccci_handle, TTY_CMD_SET_INDICATION, (DCL_CTRL_DATA_T*) &indication);
+ }
+#endif
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ usim_dcb->poll_sim_2s = KAL_FALSE;
+#endif
+ }
+#if (2 == SIM_DRV_MTK_INTERFACE_NUM)
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+ if ((kal_uint32)hw_cb != hwCbArray[hw_cb->simInterface])
+ SIM_DEBUG_ASSERT(0);
+ if (IRQ_USIM1_CODE != hw_cb->mtk_lisrCode)
+ SIM_DEBUG_ASSERT(0);
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+ if (usim2_hisrid == NULL)
+ {
+ usim2_hisrid = kal_init_hisr(USIM2_HISR);
+ }
+#endif
+ if ((void *)usim_dcb->gpt_handle == NULL)
+ DRV_ICC_GPTI_GetHandle(&usim_dcb->gpt_handle);
+#if defined(__SIM_ACTIVATION_V2__)
+ if ((void *)usim_dcb->gpt_handle_for_SIM_activation == NULL)
+ DRV_ICC_GPTI_GetHandle(&usim_dcb->gpt_handle_for_SIM_activation);
+ if ((void *)usim_dcb->gpio_handle_for_SIO == NULL)
+ {
+ usim_dcb->gpio_handle_for_SIO = DclGPIO_Open(DCL_GPIO, GPIO_SIM2_SIMIO);
+ }
+#endif
+ //IRQSensitivity(hw_cb->mtk_lisrCode, LEVEL_SENSITIVE);
+ }
+#endif
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ // reset these value no matter cold or warm reset
+ usim_dcb->main_state = ACTIVATION_STATE;
+ usim_dcb->ifsc = USIM_IFSC_DEFAULT;
+ usim_dcb->ifsd = USIM_IFSD_DEFAULT;
+ usim_dcb->ns = 0;
+ usim_dcb->nr = 0;
+ usim_dcb->simInitialized=KAL_FALSE;
+}
+
+#if defined(__ABNORMAL_CARD__)
+void usim_set_sim_io_special_mode(kal_int32 simIF, kal_bool enable)
+{
+ Data_Sync_Barrier();
+ /*
+ For some abnormal cards, SIM IO's low voltage is relative high, for example @ 1.2V
+ the special mode is used to make sim controller can sample data from SIM IO correctly
+ */
+ if (enable)
+ {
+ ENABLE_ABNORMAL_SIM(simIF);
+ }
+ else
+ {
+ DISABLE_ABNORMAL_SIM(simIF);
+ }
+ Data_Sync_Barrier();
+
+ return;
+}
+#endif
+
+/*************************************************************************
+* FUNCTION
+* L1sim_Reset
+*
+* DESCRIPTION
+* 1. Reset the sim card and parse the ATR and perform the PTS(optional) and
+ enter the command ready mode
+* 2. First time it is a cold reset, second it's a warm reset
+* 3. If the ExpectVolt equal to the current volt, perform a warm reset.
+ Otherwise perform a cold reset.
+* 4. Finally, S-block of IFS request is sent the UICC to configure the IFSD
+*
+* PARAMETERS
+ 1. ExpectVolt: application layer give a expected power class
+
+* RETURNS
+* USIM_VOLT_NOT_SUPPORT: Valid TS is received
+* KAL_FALSE: Valid TS is not received, card is not present or not supported
+*
+* GLOBALS AFFECTED
+* usim_dcb
+*
+*************************************************************************/
+static usim_status_enum L1usim_Reset(usim_power_enum ExpectVolt, usim_power_enum *ResultVolt, sim_HW_cb *hw_cb)
+{
+ kal_uint32 retry, log_size = 0;
+ kal_uint32 ori_ExpectVolt = (kal_uint32) ExpectVolt;
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ usim_dcb->isPrefer3V = KAL_FALSE;
+#if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ if (usim_dcb->retry_3v_prefer)
+ {
+ ExpectVolt = CLASS_B_30V;
+ }
+#endif
+PREFER_3V:
+ if (usim_dcb->isPrefer3V == KAL_TRUE)
+ {
+ sim_addMsg(0xE002, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ ExpectVolt = CLASS_B_30V;
+ }
+#if defined(SIM_DRV_IC_USB)
+PREFER_ORI:
+#endif // #if defined(SIM_DRV_IC_USB)
+restart_new_clock:
+ //dbg_print("L1usim_Reset\r\n");
+ L1usim_Init(hw_cb);
+ if (usim_check_input_volt(ExpectVolt, hw_cb) == KAL_FALSE)
+ return USIM_VOLT_NOT_SUPPORT;
+ // 1. Activate the USIM interface
+ SIM_DisAllIntr();
+ SIM_DMA_STOP(usim_dcb->dma_config.channel);
+
+ usim_set_timeout(INIT_WWT_T0, hw_cb);
+
+ // dbg_print("BRR = %x \r\n", SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_BRR_MTK));
+ // dbg_print("TOUT = %d \r\n", SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK));
+ /*
+ if(TS_HSK_ENABLE)
+ {
+ SIM_SetRXRetry(7);
+ SIM_SetTXRetry(7);
+ USIM_ENABLE_TXRX_HANSHAKE();
+ }
+ */
+ // if corrupted ATRs are received, retry 3 times
+#if defined(__ABNORMAL_CARD__)
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ if (usim_dcb->retry_special_mode_prefer == KAL_TRUE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] Prefer reset with Abnormal mode \r\n", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ usim_set_sim_io_special_mode(hw_cb->simInterface, KAL_TRUE);
+ }
+ else
+ {
+#endif
+ usim_set_sim_io_special_mode(hw_cb->simInterface, KAL_FALSE);
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ }
+#endif
+#endif // #if defined(__ABNORMAL_CARD__)
+ for (retry = 0; retry < ATR_RETRY; retry++)
+ {
+#if defined(SIM_DRV_IC_USB)
+ sim_addMsg(0xE003, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif // #if defined(SIM_DRV_IC_USB)
+ if (usim_select_power(ExpectVolt, hw_cb) == KAL_FALSE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[%s,%d] retry %d, ori_ExpectVolt:%d\n\r", __FUNCTION__, __LINE__, retry, ori_ExpectVolt);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (usim_dcb->warm_rst == KAL_TRUE)
+ {
+ return USIM_ATR_ERR;
+ }
+ if (usim_dcb->ts_hsk_en == KAL_TRUE)
+ {
+ usim_dcb->ts_hsk_en = KAL_FALSE;
+ }
+ else
+ {
+#if defined(__SIM_ACTIVATION_V2__)
+ usim_dcb->activation_v2 = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]try SIM activation v2\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (usim_select_power((usim_power_enum) ori_ExpectVolt, hw_cb) == KAL_FALSE)
+ {
+ if (usim_dcb->warm_rst == KAL_TRUE)
+ {
+ return USIM_ATR_ERR;
+ }
+ }
+ else if (usim_process_ATR(hw_cb) == USIM_NO_ERROR)
+ {
+ break;
+ }
+
+ usim_dcb->activation_v2 = KAL_FALSE;
+#endif
+#if defined(__ABNORMAL_CARD__)
+
+ usim_set_sim_io_special_mode(hw_cb->simInterface, KAL_TRUE);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]try special mode\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ if (usim_select_power((usim_power_enum) ori_ExpectVolt, hw_cb) == KAL_FALSE)
+ {
+ if (usim_dcb->warm_rst == KAL_TRUE)
+ {
+ return USIM_ATR_ERR;
+ }
+ }
+ else if (usim_process_ATR(hw_cb) == USIM_NO_ERROR)
+ {
+ MD_TRC(LOG_SIM_DRV_ABNORMAL_CARD,hw_cb->simInterface);
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ usim_dcb->retry_special_mode_prefer = KAL_TRUE;
+#endif
+ break;
+ }
+#endif // #if defined(__ABNORMAL_CARD__)
+ return USIM_NO_ATR;
+ }
+ //continue;
+ }
+ else if (usim_process_ATR(hw_cb) == USIM_NO_ERROR)
+ {
+ break;
+ }
+
+ ExpectVolt = usim_dcb->power;
+ }
+
+ if (retry == ATR_RETRY)
+ return usim_dcb->error_status;
+
+ hw_cb->issueCardStatus = usim_process_HISTORICAL(hw_cb);
+ if (hw_cb->SlowClock == KAL_FALSE && hw_cb->issueCardStatus == SIM_SLOW_CLOCK)
+ {
+ goto restart_new_clock;
+ }
+ else if (usim_dcb->power == CLASS_C_18V && hw_cb->issueCardStatus == SIM_FORCE_3V)
+ {
+ goto PREFER_3V;
+ }
+
+ *ResultVolt = usim_dcb->power;
+ // 3. Process PTS
+ //if(usim_dcb->reset_mode == USIM_RESET_NEGOTIABLE)
+ {
+ if (usim_process_PTS(hw_cb) == KAL_FALSE)
+ {
+ for (retry = 0; retry < 3; retry++)
+ {
+#if !defined(ATEST_DRV_ENABLE)
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d] retry PTS %d\n\r", hw_cb->simInterface, retry);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ if (usim_select_power(ori_ExpectVolt, hw_cb) == KAL_FALSE) continue;
+ if (usim_process_ATR(hw_cb) != USIM_NO_ERROR) continue;
+ if (usim_process_PTS(hw_cb) == KAL_TRUE) break;
+ }
+ if (retry == 3) return usim_dcb->error_status;
+ }
+ // 4. Configure the IFSD
+ if (usim_dcb->phy_proto == T1_PROTOCOL)
+ {
+ if (usim_send_s_block(IFS_REQ, USIM_IFSD_MAX, hw_cb) == USIM_NO_ERROR)
+ {
+ // if we failed to send S block when negotiating IFSD and deactivate the card, we should report the reset status correctly
+ if (DEACTIVATION_STATE == usim_dcb->main_state)
+ return USIM_S_BLOCK_FAIL;
+
+ usim_dcb->ifsd = USIM_IFSD_MAX;
+ }
+ }
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ // after usim_process_PTS only
+ if (usim_dcb->app_proto == USIM_PROTOCOL && hw_cb->issueCardStatus == SIM_NORMAL)
+ {
+ hw_cb->canUse_4_33_SCLK = KAL_TRUE;
+ }
+ else
+ {
+ hw_cb->canUse_4_33_SCLK = KAL_FALSE;
+ }
+#endif
+ }
+ // NOTE: can't turn off the PDN bit of SIM interface over, it will cause
+ // the SIM behavior abnormal.
+ usim_dcb->main_state = MAIN_CMD_READY_STATE;
+ usim_dcb->cmd_state = USIM_CMD_READY;
+ kal_set_eg_events(usim_dcb->event, 0, KAL_AND);
+#if defined(SIM_DRV_IC_USB)
+ if ((usim_dcb->isIcUsb == KAL_TRUE) && (hw_cb->simInterface == 0x0) && (FACTORY_BOOT != kal_query_boot_mode()) && usim_dcb->forceISO == KAL_FALSE)
+ {
+ kal_uint32 icusbStatus = 0;
+ sim_addMsg(0xE00C, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+
+ // power off ISO mode
+ if (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK)&SIM_CTRL_SIMON)
+ {
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);
+ USIM_CLR_FIFO();
+
+ // tell USB to reset MAC & PHY
+ icusbStatus = SIM_icusb_disableSession(hw_cb);
+ if (icusbStatus == SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE005, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+
+ // Need delay of at least 10ms before next activate operation
+ kal_sleep_task(KAL_TICKS_50_MSEC_REAL);
+
+ // tell USB to reset MAC & PHY
+ icusbStatus = SIM_icusb_disconnectDone(hw_cb);
+ if (icusbStatus == SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ sim_addMsg(0xE007, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+ }
+ usim_dcb->isPrefer3V = KAL_FALSE;
+ //notify AP libusb
+ if (SIM_icusb_setVolt(hw_cb) == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc0);
+ sim_addMsg(0xE024, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+
+ icusbStatus = SIM_icusb_enableSession(hw_cb);
+ if (icusbStatus == SIM_ICUSB_ACK_PREFER_3V)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc1);
+ L1usim_PowerOff(hw_cb);
+ usim_dcb->isPrefer3V = KAL_TRUE;
+ sim_addMsg(0xE00F, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto PREFER_3V;
+ }
+ else if (icusbStatus == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc2);
+ sim_addMsg(0xE025, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+ if (SIM_icusb_powerOn(hw_cb) == (kal_uint32)SIM_ICUSB_CCCI_TIMEOUT)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xccc3);
+ sim_addMsg(0xE026, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+ goto LEAVE_ICUSB_INIT;
+ }
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC66, usim_dcb->isIcUsbRecPPS, usim_dcb->main_state, usim_dcb->isIcUsb, usim_dcb->icusb_state, 0);
+ }
+#if defined SIM_DRV_IC_USB_DBG_2
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xaaad);
+#endif // #if defined SIM_DRV_IC_USB_DBG_2
+#endif // #if defined(SIM_DRV_IC_USB)
+ return USIM_NO_ERROR;
+
+#if defined(SIM_DRV_IC_USB)
+LEAVE_ICUSB_INIT:
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL);
+ usim_deactivation(hw_cb);
+ usim_dcb->forceISO = KAL_TRUE;
+ usim_dcb->isIcUsb = KAL_FALSE;
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xaaae);
+ if (usim_dcb->isPrefer3V == KAL_TRUE || usim_dcb->power == CLASS_B_30V) goto PREFER_3V;
+ else goto PREFER_ORI;
+#endif // #if defined(SIM_DRV_IC_USB)
+}
+
+/*************************************************************************
+* FUNCTION
+* L1usim_PowerOff
+*
+* DESCRIPTION
+* 1. perform the deactivation to UICC
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_PowerOff(sim_HW_cb *hw_cb)
+{
+#if defined(SIM_DRV_IC_USB)
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ sim_addMsg(0xE012, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif // #if defined(SIM_DRV_IC_USB)
+ // DRVPDN_Disable(DRVPDN_CON1,DRVPDN_CON1_SIM,PDN_SIM);
+ usim_deactivation(hw_cb);
+ // DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_SIM,PDN_SIM);
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Get_Card_Info
+*
+* DESCRIPTION
+* get the card informations
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_Get_Card_Info(sim_info_struct *info, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ SIM_DEBUG_ASSERT(usim_dcb->main_state >= ATR_STATE);
+ info->power = usim_dcb->power;
+ info->speed = usim_dcb->speed;
+ info->clock_stop = usim_dcb->clock_stop_type;
+ info->app_proto = usim_dcb->app_proto;
+ info->phy_proto = usim_dcb->phy_proto;
+ info->T0_support = usim_dcb->T0_support;
+ info->T1_support = usim_dcb->T1_support;
+ info->hist_index = usim_dcb->hist_index;
+ info->ATR = usim_dcb->ATR_data;
+ info->TAiExist = usim_dcb->TAiExist;
+ info->ATR_length = usim_dcb->ATR_index;
+ info->isSW6263 = usim_dcb->isSW6263;
+ info->TB15 = usim_dcb->TB15;
+ info->hasPowerClass = usim_dcb->hasPowerClass;
+ info->PowerClass = usim_dcb->PowerClass;
+#ifdef SIM_DRV_EXTENDED_APDU
+ info->SupportExtendedLength = usim_dcb->Support_Extended_Length;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* L1usim_Enable_Enhanced_Speed
+*
+* DESCRIPTION
+* 1. enable the enhance speed mode if UICC supports
+* 2. shall be called before reset after init
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ //ASSERT(usim_dcb->main_state == IDLE_STATE);
+ usim_dcb->high_speed_en = enable;
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Set_ClockStopMode
+*
+* DESCRIPTION
+* setup the clock stop mode according to the ATR information.
+*
+* PARAMETERS
+* mode: clock stop mode
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static void L1usim_Set_ClockStopMode(usim_clock_stop_enum mode, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint32 t1 = 0, log_size = 0;
+ //kal_bool level = KAL_FALSE;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ if (mode & CLOCK_STOP_MSK)
+ {
+ // calculate the clock to etu for 1860 and 700
+ usim_dcb->etu_of_1860 = (1860 / (usim_dcb->Fi / usim_dcb->Di)) + 10; // longer than spec.
+ usim_dcb->etu_of_700 = (700 / (usim_dcb->Fi / usim_dcb->Di)) + 5;
+ usim_dcb->clock_stop_en = KAL_TRUE;
+ if (mode == CLOCK_STOP_ANY)
+ {
+ usim_dcb->clock_stop_type = CLOCK_STOP_LOW;
+ //level = KAL_FALSE;
+ }
+ else
+ {
+ usim_dcb->clock_stop_type = mode;
+ //level = KAL_TRUE;
+ }
+
+ t1 = SIM_GetCurrentTime();
+ while ((SIM_GetCurrentTime() - t1) < 20); // delay 600 clock cycles (600us)
+ //SIM_Idle_MTK(level, hw_cb);
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]stop SIM clock\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else
+ {
+ usim_dcb->clock_stop_en = KAL_FALSE;
+ }
+}
+/*************************************************************************
+* FUNCTION
+* L1usim_Cmd
+*
+* DESCRIPTION
+* usim T=1 command
+*
+* PARAMETERS
+* 1. txData: tx buffer containing command header optional with tx data.
+* 2. txSize: length of the tx data
+* 3. rxData: rx buffer (must inluding two extra one for sw1 and sw2)
+* 4. rxSize: length of the rx data except sw1|sw2
+*
+* RETURNS
+* status bytes(SW1|SW2), 0 means a physical error.
+
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+static sim_status L1usim_Cmd(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+#ifdef SIM_CACHED_SUPPORT
+ sim_status SW;
+ kal_uint8 *pNoncachedTx, *pNoncachedRx;
+#endif
+ kal_uint32 log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ log_size = kal_sprintf(hw_cb->dbgStr, "%s(%d) P3=%d txSize=%d, rxData%s=NULL, *rxSize=%d\n\r",
+ __FUNCTION__, hw_cb->simInterface, txData[4], *txSize, (rxData == NULL) ? "=" : "!", (rxData != NULL) ? *rxSize : 0);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+
+ /*
+ if(usim_dcb->main_state != MAIN_CMD_READY_STATE && usim_dcb->main_state != CLK_STOPPED_STATE)
+ {
+ kal_prompt_trace(MOD_SIM,"[SIM_DRV]:L1usim_Cmd is called at err state");
+ return SIM_SW_STATUS_FAIL;
+ }
+ */
+ if (rxData == NULL && *rxSize != 0)
+ SIM_DEBUG_ASSERT(0);
+ if (usim_dcb->cmd_case == usim_case_1)
+ {
+ // for case1, only 4 bytes need to be transfer
+ *txSize = 4;
+ *rxSize = 0;
+ }
+
+#ifdef SIM_CACHED_SUPPORT
+ if (INT_QueryIsCachedRAM(txData, *txSize))
+ {
+ GET_NCACHEDTX_P(pNoncachedTx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ kal_mem_cpy(pNoncachedTx, txData, *txSize);
+ }
+ else
+ {
+ pNoncachedTx = txData;
+ }
+
+ if (rxData != NULL && INT_QueryIsCachedRAM(rxData, 512))
+ {
+ GET_NCACHEDRX_P(pNoncachedRx, sim_get_hwCtrl_from_logicalNum(hw_cb->simInterface));
+ }
+ else
+ {
+ pNoncachedRx = rxData;
+ }
+
+ SW = usim_send_i_block((kal_uint8 *)pNoncachedTx, txSize, (kal_uint8 *)pNoncachedRx, rxSize, hw_cb);
+
+ if (rxData != NULL && INT_QueryIsCachedRAM(rxData, 512))
+ {
+ if (0 != *rxSize)
+ {
+ if (512 < *rxSize)
+ {
+ SIM_DEBUG_ASSERT(0);
+ }
+ kal_mem_cpy(rxData, pNoncachedRx, *rxSize);
+ }
+ }
+
+ return SW;
+#endif
+
+#ifdef SIM_CACHED_SUPPORT_WRITE_THROUGH_SERIES
+ invalidate_wt_cache((kal_uint32)rxData, *rxSize);
+#endif
+
+#ifndef SIM_CACHED_SUPPORT
+ return usim_send_i_block(txData, txSize, rxData, rxSize, hw_cb);
+#endif
+}
+/*************************************************************************
+* FUNCTION
+* usim_TimeOutHandler
+*
+* DESCRIPTION
+* Callback function of gpt timer, and launched while MSDC busy for a while
+
+*
+* PARAMETERS
+*
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*
+*************************************************************************/
+static void usim_gpt_timeout_handler(void *parameter)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = (usim_dcb_struct *)parameter;
+
+ /*
+ kal_prompt_trace(MOD_SIM,"[SIM_DRV]: usim gpt timeout !");
+ */
+ usim_dcb->status = USIM_GPT_TIMEOUT;
+ usim_dcb->ev_status = USIM_GPT_TIMEOUT;
+ USIM_SET_EVENT_Multiple(usim_dcb);
+}
+
+#if defined(__SIM_ACTIVATION_V2__)
+void usim_gpt_timeout_handler_for_SIM_activation(void *parameter)
+{
+ sim_HW_cb *hw_cb;
+ usim_dcb_struct *usim_dcb;
+
+ hw_cb = (sim_HW_cb *) parameter;
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+#if defined(__SIM_SAME_GPIO_MODE__)
+ DclGPIO_Control(usim_dcb->gpio_handle_for_SIO, GPIO_CMD_SET_MODE_1, NULL);
+#else
+ DclGPIO_Control(usim_dcb->gpio_handle_for_SIO, GPIO_CMD_SET_MODE_2, NULL);
+#endif
+ MO_Sync();
+}
+#endif
+
+//------------------------------------------------------------------------//
+// General interfaces of sim driver
+//------------------------------------------------------------------------//
+/*************************************************************************
+* FUNCTION
+* L1sim_Reset_All
+*
+* DESCRIPTION
+* 1. general interface of sim reset for T=0 and T=1
+* 2. it support warm reset for UICC
+* 3. first enable error repeat handling process to cover parity error at ATR, if not
+* success, disable it.
+* 4. for SIM protocol with T=0, additional reset will be perfromed.
+*
+* PARAMETERS
+* ExpectVolt: expected input voltage for the SIM card.
+* ResultVolt: finally used power voltage.
+* warm: specify warm reset for UICC
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+usim_status_enum L1sim_Reset_MTK(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, sim_HW_cb *hw_cb)
+{
+ usim_status_enum status;
+ usim_dcb_struct *usim_dcb;
+ Sim_Card *SimCard;
+ kal_uint32 log_size = 0;
+
+#if defined(__DUAL_SIM_HOT_SWAP_CO_DECK_SUPPORT__)&& defined(__SIM_HOT_SWAP_POLL_TIMER__)
+ if (hw_cb->PollTimerStart == KAL_TRUE)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]: Skip reset while PollTimerStart!\n\r", hw_cb->simInterface);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return USIM_NO_INSERT;
+ }
+#endif
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ /*we should do platform check here, not allow to access interface 2 on one-SIM platform*/
+ usim_InterfaceCheck(hw_cb);
+
+ /*we should additionally check whether this interface has owner or not*/
+ if (0 != usim_dcb->ownerTask && kal_get_current_thread_ID() != usim_dcb->ownerTask)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC122, SIM_ASSERT_REASON_WRONG_OWNERTASK, SIM_ASSERT_OWNER_SIMTASK,
+ (kal_uint32) usim_dcb->ownerTask, (kal_uint32) kal_get_current_thread_ID(), 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+
+#if defined(SIM_DRV_IC_USB)
+#if defined(SIM_DRV_IC_USB_DBG_2)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC15, 0, 0, 0, drv_get_current_time(), 0xaaac);
+#endif
+ sim_addMsg(0xE001, hw_cb->simInterface, usim_dcb->power_in, usim_dcb->power);
+#endif
+
+#if 0 //defined(SIM_DRV_IC_USB)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ if (warm == KAL_FALSE)
+ {
+ //dbg_print("cold reset \r\n");
+ //TS_HSK_ENABLE = KAL_TRUE;
+ status = L1usim_Reset(ExpectVolt, ResultVolt, hw_cb);
+ usim_dcb->ownerTask = kal_get_current_thread_ID();
+ if (status < 0)
+ {
+ //these string should cross over sometimes, fix when we meet
+ //kal_sprintf(hw_cb->dbgStr, "L1usim_Reset failed!(%d, %d)", status, hw_cb->simInterface);
+ //dbg_print(hw_cb->dbgStr);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RESET_FAIL, status, hw_cb->simInterface, (kal_uint32)usim_dcb->ev_status, (kal_uint32)ExpectVolt, (kal_uint32)ResultVolt);
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RESET_FAIL, SIM_Reg(SIM0_BASE_ADDR_MTK + 0x08), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x20), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x24), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x34), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x60));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RESET_FAIL, SIM_Reg(SIM0_BASE_ADDR_MTK + 0x74), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x90), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x70), SIM_Reg(SIM0_BASE_ADDR_MTK + 0x00), 0);
+ //L1sim_PowerOff_All(simInterface);
+ L1usim_PowerOff(hw_cb);
+ if (status == USIM_NO_INSERT)
+ usim_dcb->present = KAL_FALSE;
+
+
+ return status;
+ /*
+ TS_HSK_ENABLE = KAL_FALSE;
+ status = L1usim_Reset(ExpectVolt, ResultVolt);
+ if(status <0)
+ {
+ L1sim_PowerOff_All();
+ MT6302_RACE_RELEASE(sim_MT6302_protectionRst);
+ return status;
+ }
+ */
+ }
+ else
+ {
+ kal_uint32 i;
+ kal_char *p;
+
+
+ if (USIM_DIRECT != usim_dcb->dir)
+ {
+ //dbg_print("indirect card!!!!");
+ }
+
+ p = hw_cb->dbgStr;
+ log_size = kal_sprintf(p, "[SIM_DRV:%d]SIM ATR= ", hw_cb->simInterface);
+ p += strlen(p);
+ for (i = 0; i < usim_dcb->ATR_index; i++)
+ {
+ kal_sprintf(p, "%02X", usim_dcb->ATR_data[i]);
+ p += 2;
+ }
+#ifdef ATEST_DRV_ENABLE
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ if (log_size > 0) MD_TRC(LOG_SIM_DRV_ATR,hw_cb->dbgStr);
+#endif
+
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1USIM_RST_OK, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed, 0);
+#ifdef ATEST_DRV_ENABLE
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]L1usim_Reset OK voltage: %d, T: %d, app: %d, speed:%d\n\r", hw_cb->simInterface, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#else
+ MD_TRC(LOG_SIM_DRV_BASIC_SIM_INFO,hw_cb->simInterface, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed);
+#endif
+#ifdef __TC01__
+ kal_sprintf(hw_cb->l4cDbgStr, "[SIM_DRV:%d]L1usim_Reset OK voltage: %d, T: %d, app: %d, speed:%d", hw_cb->simInterface, usim_dcb->power, usim_dcb->phy_proto, usim_dcb->app_proto, usim_dcb->card_speed);
+ sim_drv_debug_ind_callback(hw_cb->simInterface, (kal_uint8 *)hw_cb->l4cDbgStr, strlen(hw_cb->l4cDbgStr));
+#endif
+
+ Data_Sync_Barrier();
+ // reset successfully, record its IR or AL state
+ if (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & SIM_ATRSTA_AL)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "AL card, convention: %x\n\r", usim_dcb->ATR_data[0]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else if (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_ATRSTA_MTK) & SIM_ATRSTA_IR)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "IR card, convention: %x\n\r", usim_dcb->ATR_data[0]);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+ }
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+
+ kal_uint8 s;
+ kal_uint8 power;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ L1sim_Init_MTK(hw_cb);
+ if (usim_dcb->power == CLASS_C_18V)
+ power = SIM_18V;
+ else
+ power = SIM_30V;
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ s = sim_Reset_MTK(power, NULL, NULL, hw_cb);
+#ifdef SIM_REMOVE_ATR_ASSERT
+ if (SIM_NO_ERROR != s)
+ {
+ usim_dcb->present = KAL_FALSE;
+ status = s;
+ return status;
+ }
+#endif
+ SIM_DEBUG_ASSERT(s == SIM_NO_ERROR);
+#ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+ {
+ /* For [MAUI_01321659] begin */
+ if (SimCard->Power == SIM_18V)
+ *ResultVolt = CLASS_C_18V;
+ else if (SimCard->Power == SIM_30V)
+ *ResultVolt = CLASS_B_30V;
+ else
+ SIM_DEBUG_ASSERT(0);
+ } /* For [MAUI_01321659] end */
+#endif
+ }
+ else
+ usim_update_sim_to_ready(hw_cb);
+
+ SimCard->mod_id = kal_get_active_module_id();
+ SimCard->mod_extq_cap = msg_get_task_extq_capacity(SimCard->mod_id);
+ }
+ }
+ else
+ {
+ if (usim_dcb->app_proto == USIM_PROTOCOL)
+ {
+ usim_dcb->warm_rst = KAL_TRUE;
+ status = L1usim_Reset(usim_dcb->power, ResultVolt, hw_cb);
+ usim_dcb->warm_rst = KAL_FALSE;
+ if (status < 0)
+ {
+ //L1sim_PowerOff_All(simInterface);
+ L1usim_PowerOff(hw_cb);
+ return status;
+ }
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ kal_uint8 power = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+
+ L1sim_Init_MTK(hw_cb);
+ if (usim_dcb->power == CLASS_C_18V)
+ power = SIM_18V;
+ else
+ power = SIM_30V;
+ if (usim_dcb->app_proto == SIM_PROTOCOL)
+ {
+ sim_Reset_MTK(power, NULL, NULL, hw_cb);
+#ifdef DRV_SIM_RETRY_3V_ON_PTS_ERROR
+ {
+ /* For [MAUI_01321659] begin */
+ if (SimCard->Power == SIM_18V)
+ *ResultVolt = CLASS_C_18V;
+ else if (SimCard->Power == SIM_30V)
+ *ResultVolt = CLASS_B_30V;
+ else
+ SIM_DEBUG_ASSERT(0);
+ } /* For [MAUI_01321659] end */
+#endif
+ }
+ else
+ usim_update_sim_to_ready(hw_cb);
+
+ SimCard->mod_id = kal_get_active_module_id();
+ SimCard->mod_extq_cap = msg_get_task_extq_capacity(SimCard->mod_id);
+ }
+ }
+ else
+ {
+ //mtk04122: have confirmed with original owner that warm reset is not supported for sim
+ status = USIM_INVALID_WRST;
+ }
+ }
+ return status;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Enable_Enhanced_Speed_All
+*
+* DESCRIPTION
+* enable the enhance speed
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_Enable_Enhanced_Speed_MTK(kal_bool enable, sim_HW_cb *hw_cb)
+{
+#if defined(__DBG_MSG__)
+ //dbg_print("L1sim_Enable_Enhanced_Speed_MTK\r\n");
+#endif
+ L1sim_Enable_Enhanced_Speed(enable, hw_cb);
+ L1usim_Enable_Enhanced_Speed(enable, hw_cb);
+
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Select_Prefer_PhyLayer_All
+*
+* DESCRIPTION
+* select the prefer physical layer protocol, the selected one has higher priority
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_Select_Prefer_PhyLayer_MTK(sim_protocol_phy_enum T, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ usim_dcb->perfer_phy_proto = T;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Set_ClockStopMode_All
+*
+* DESCRIPTION
+* configure the clock stop mode.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+kal_bool L1sim_Set_ClockStopMode_MTK(sim_clock_stop_enum mode, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ if (mode == CLOCK_STOP_HIGH)
+ L1sim_Configure_MTK(CLOCK_STOP_AT_HIGH, hw_cb);
+ else if (mode == CLOCK_STOP_LOW || mode == CLOCK_STOP_ANY)
+ L1sim_Configure_MTK(CLOCK_STOP_AT_LOW, hw_cb);
+ else
+ L1sim_Configure_MTK(CLOCK_STOP_NOT_ALLOW, hw_cb);
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ }
+ else
+ {
+ L1usim_Set_ClockStopMode(mode, hw_cb);
+ }
+
+ return KAL_TRUE;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_PowerOff_All
+*
+* DESCRIPTION
+* turn off the SIM card.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_PowerOff_MTK(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+
+ /*we should additionally check whether this interface has owner or not*/
+ if (0 != usim_dcb->ownerTask && kal_get_current_thread_ID() != usim_dcb->ownerTask)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC122, SIM_ASSERT_REASON_WRONG_OWNERTASK, SIM_ASSERT_OWNER_SIMTASK,
+ (kal_uint32) usim_dcb->ownerTask, (kal_uint32) kal_get_current_thread_ID(), 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ if (usim_dcb->phy_proto == T0_PROTOCOL)
+ {
+ sim_PowerOff_MTK(hw_cb);
+ }
+ else
+ {
+ L1usim_PowerOff(hw_cb);
+ }
+ usim_dcb->present = KAL_FALSE;
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Get_Card_Info_All
+*
+* DESCRIPTION
+* get the card information
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+void L1sim_Get_Card_Info_MTK(sim_info_struct *info, sim_HW_cb *hw_cb)
+{
+ L1usim_Get_Card_Info(info, hw_cb);
+}
+/*************************************************************************
+* FUNCTION
+* L1sim_Cmd_All
+*
+* DESCRIPTION
+* 1. check which case the command belongs to.
+* 2. direct the command into T=0 or T=1 protocol layer.
+*
+* PARAMETERS
+* 1. txData: tx buffer containing command header optional with tx data.
+* 2. txSize: length of the tx data
+* 3. rxData: rx buffer (for T=1, must inluding two extra one for sw1 and sw2)
+* 4. rxSize: length of the rx data except sw1|sw2
+*
+* RETURNS
+* status bytes(SW1|SW2), 0 means a physical error.
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+sim_status L1sim_Cmd_MTK(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usimCard;
+ sim_status result;
+ Sim_Card *SimCard;
+ kal_uint32 log_size = 0;
+
+ SimCard = GET_SIM_CB(hw_cb->simInterface);
+ usimCard = GET_USIM_CB(hw_cb->simInterface);
+ /*we should do platform check here, not allow to access interface 2 on one-SIM platform*/
+ usim_InterfaceCheck(hw_cb);
+
+ /*we should additionally check whether this interface has owner or not*/
+ if (0 != usimCard->ownerTask && kal_get_current_thread_ID() != usimCard->ownerTask)
+ {
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC122, SIM_ASSERT_REASON_WRONG_OWNERTASK, SIM_ASSERT_OWNER_SIMTASK,
+ (kal_uint32) usimCard->ownerTask, (kal_uint32) kal_get_current_thread_ID(), 0);
+ SIM_DEBUG_ASSERT(0);
+ }
+
+ // SIM card is plugout || SIM card is not activated
+ if (usimCard->present == KAL_FALSE || (DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON) == 0x0)
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "usimCard->present:%x, SIMON:%x\n\r", usimCard->present, DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) & SIM_CTRL_SIMON);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return SIM_SW_STATUS_FAIL;
+ }
+
+ // check cmd cases
+ if (*txSize == 5 && rxData == NULL)
+ {
+ usimCard->cmd_case = usim_case_1;
+ ////dbg_print("usim_case_1 \r\n");
+ }
+ else if (*txSize == 5 && rxData != NULL)
+ {
+ usimCard->cmd_case = usim_case_2;
+ if ((0 == txData[LEN_INDEX] && 256 > *rxSize) || (*rxSize < txData[LEN_INDEX]))
+ {
+ return 0x0000;
+ }
+ ////dbg_print("usim_case_2 \r\n");
+ }
+#ifndef SIM_DRV_EXTENDED_APDU
+ else if (*txSize != 5 && rxData == NULL)
+ {
+ usimCard->cmd_case = usim_case_3;
+ ////dbg_print("usim_case_3 \r\n");
+ }
+ else if (*txSize != 5 && rxData != NULL)
+ {
+ usimCard->cmd_case = usim_case_4;
+ ////dbg_print("usim_case_4 \r\n");
+ }
+#else
+ else
+ {
+ if (usimCard->Support_Extended_Length == KAL_TRUE)
+ {
+ if (*txSize == 7 && rxData != NULL && txData[LEN_INDEX] == 0) //2E, p3 is 0
+ usimCard->cmd_case = usim_case_2E;
+
+ else if (rxData == NULL && txData[LEN_INDEX] != 0) // 3S
+ usimCard->cmd_case = usim_case_3;
+ else if (rxData == NULL && txData[LEN_INDEX] == 0) // 3E
+ usimCard->cmd_case = usim_case_3E;
+ else if (rxData != NULL && txData[LEN_INDEX] != 0) // 4S
+ usimCard->cmd_case = usim_case_4;
+ else if (rxData != NULL && txData[LEN_INDEX] == 0) // 4E
+ usimCard->cmd_case = usim_case_4E;
+ }
+ else
+ {
+ if (*txSize != 5 && rxData == NULL)
+ {
+ usimCard->cmd_case = usim_case_3;
+ }
+ else if (*txSize != 5 && rxData != NULL)
+ {
+ usimCard->cmd_case = usim_case_4;
+ }
+ }
+ }
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d]: Case:%d, txSize:%d", hw_cb->simInterface, usimCard->cmd_case, *txSize);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ SimCard->cmd_case = usimCard->cmd_case;
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC1, *txData, *(txData + 1), *(txData + 2), *(txData + 3), drv_get_current_time());
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC1, *txSize, *rxSize, hw_cb->simInterface, *rxData, SimCard->cmd_case);
+#endif
+
+ if (usimCard->phy_proto == T0_PROTOCOL)
+ {
+ result = L1sim_Cmd_Layer_MTK(txData, txSize, rxData, rxSize, hw_cb, &usimCard->isSW6263);
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC19, drv_get_current_time(), *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC19, *rxData, *(rxData + 1), *(rxData + 2), *(rxData + 3), *(rxData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC19, *txSize, *rxSize, result, usimCard->isSW6263, SimCard->cmd_case);
+#endif
+ }
+ else
+ {
+ result = L1usim_Cmd(txData, txSize, rxData, rxSize, hw_cb);
+#if defined(SIM_DEBUG_INFO)
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC41, drv_get_current_time(), *(txData + 1), *(txData + 2), *(txData + 3), *(txData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC41, *rxData, *(rxData + 1), *(rxData + 2), *(rxData + 3), *(rxData + 4));
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC14, *txSize, *rxSize, result, usimCard->isSW6263, SimCard->cmd_case);
+#endif
+ }
+
+#if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ if (result == SIM_SW_STATUS_FAIL && usimCard->present)
+ {
+ if (usimCard->hasPowerClass && usimCard->PowerClass != CLASS_C_18V)
+ usimCard->retry_3v_prefer = KAL_TRUE;
+ }
+#endif
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ if (result == SIM_SW_STATUS_FAIL && usimCard->present)
+ {
+ usimCard->retry_special_mode_prefer = KAL_TRUE;
+ }
+#endif
+
+ return result;
+}
+
+void L1sim_EOC_MTK(sim_HW_cb *hw_cb)
+{
+ /*there should be nothing to do in EOC in dual controller solution*/
+}
+
+static kal_uint32 usim_process_HISTORICAL(sim_HW_cb *hw_cb)
+{
+ usim_dcb_struct *usim_dcb;
+ kal_uint8 *ptr;
+ kal_uint8 hist_length = 0, i = 1;
+ kal_uint8 tag, len;
+ kal_uint32 log_size = 0;
+
+ usim_dcb = GET_USIM_CB(hw_cb->simInterface);
+ ptr = usim_dcb->ATR_data + usim_dcb->hist_index;
+
+ hist_length = usim_dcb->ATR_index - usim_dcb->hist_index - 1;
+ kal_uint8 pre_issuing_data[6] = {0x86, 0x88, 0xC6, 0x18, 0x1E, 0x10};
+ kal_uint8 pre_issuing_data_2[6] = {0xd0, 0x01, 0xa4, 0x10, 0x71, 0xcf};
+ kal_uint8 pre_issuing_data_3[7] = {0x37, 0x86, 0x60, 0xa6, 0x00, 0x80, 0x12};
+ kal_uint8 pre_issuing_data_4[22] = {0x3B, 0x9F, 0x94, 0x80, 0x1F, 0xC7, 0x80, 0x31, 0xE0, 0x73, 0xFE, 0x21, 0x13, 0x57, 0x86, 0x8C, 0x02, 0x86, 0x98, 0xE0, 0x43, 0x5F};
+
+ if (usim_dcb->ATR_index == 22)
+ {
+ if (0 == kal_mem_cmp(usim_dcb->ATR_data, pre_issuing_data_4, 22))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[SIM_DRV:%d]: GOT SPECIAL ATR(%d)!!!", hw_cb->simInterface, SIM_3_25MHZ_ONLY);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return SIM_3_25MHZ_ONLY;
+ }
+ }
+
+ //dbg_print("\r\nATR_LENGTH:%d hist_index:%d ptr:%x\r\n", usim_dcb->ATR_index,usim_dcb->hist_index,*ptr);
+ if (usim_dcb->hist_index == 0 || hist_length <= 0 || hist_length > 15 || *ptr != 0x80) /*Category indicator byte*/
+ {
+ return SIM_NORMAL;
+ }
+
+ while (i < hist_length)
+ {
+ tag = ptr[i++];
+ len = tag & 0xf;
+ if (tag == 0x66)
+ {
+ /*Special pre-issuing data for some c2k card*/
+ if (0 == kal_mem_cmp(ptr + i, pre_issuing_data, 6))
+ {
+ hw_cb->SlowClock = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[SIM_DRV:%d]: GOT SPECIAL HISTORICAL(%d)!!!", hw_cb->simInterface, SIM_SLOW_CLOCK);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return SIM_SLOW_CLOCK;
+ }
+ }
+ if (tag == 0x65)
+ {
+ if (0 == kal_mem_cmp(ptr + i, pre_issuing_data_2, 6))
+ {
+ if ((usim_dcb->power_class != CLASS_C_18V && usim_dcb->app_proto == SIM_PROTOCOL)
+ || ((usim_dcb->power_class & 0x2) && usim_dcb->app_proto == USIM_PROTOCOL))
+ {
+ usim_dcb->isPrefer3V = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[SIM_DRV:%d]: GOT SPECIAL HISTORICAL(%d)!!!", hw_cb->simInterface, SIM_FORCE_3V);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return SIM_FORCE_3V;
+ }
+ }
+ }
+
+ if (tag == 0x57)
+ {
+ if (0 == kal_mem_cmp(ptr + i, pre_issuing_data_3, 7))
+ {
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[SIM_DRV:%d]: GOT SPECIAL HISTORICAL(%d)!!!", hw_cb->simInterface, SIM_CLOCK_FETCH__TERMINAL_RESPONSE);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ return SIM_CLOCK_FETCH__TERMINAL_RESPONSE;
+ }
+ }
+#ifdef SIM_DRV_EXTENDED_APDU
+ if (tag == 0x73) //Card Capabilities
+ {
+ kal_uint8 sw_table3 = ptr[i + 2]; //3rd byte
+ if ((sw_table3 & 0x40) == 0x40)
+ {
+ usim_dcb->Support_Extended_Length = KAL_TRUE;
+ log_size = kal_sprintf(hw_cb->dbgStr, "\r\n[SIM_DRV:%d]:Support Extended Length(%x) !!!", hw_cb->simInterface, sw_table3);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+ }
+ }
+#endif
+ i += len;
+ }
+
+ return SIM_NORMAL;
+}
+
+void sim_toutTest(kal_uint32 toutValue, sim_HW_cb *hw_cb)
+{
+#ifdef SIM_HW_TEST
+ kal_uint32 time2, time1, log_size = 0;
+ kal_uint16 tmp;
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "tout test with value : %d\n\r", toutValue);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+ IRQMask(hw_cb->mtk_lisrCode);
+
+ // set speed 8
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_BRR_MTK), 0x21);
+
+ // make sure SIM_IRQEN TOUT is set
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), 0x8);
+
+ // set WTIME
+ DRV_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), toutValue);
+
+ // write clear IRQ
+ tmp = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_STS_MTK), tmp);
+
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), 0x80);
+
+ // mtk04122: may be replaced by ust_get_current_time();
+ time1 = ust_get_current_time();
+ DRV_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), 0x80);
+ while (0x8 != SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK));
+
+ time2 = ust_us_duration(time1);
+ time2 = time2;
+ IRQUnmask(hw_cb->mtk_lisrCode);
+
+#if defined(SIM_DEBUG_INFO)
+ log_size = kal_sprintf(hw_cb->dbgStr, "tout test done with period : %d ms\n\r", time2);
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr);
+#endif
+
+#endif // SIM_HW_TEST
+}
+
+#if defined(__CHAINING_TEST__)
+kal_bool Send_IFS_REQ(kal_uint8 ifs, kal_uint8 interface)
+{
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(interface);
+
+ sim_PDNDisable_MTK((sim_HW_cb *) hwCbArray[interface]);
+ if (usim_send_s_block(IFS_REQ, ifs, (sim_HW_cb *) hwCbArray[interface]) == USIM_NO_ERROR)
+ {
+ usim_dcb->ifsd = ifs;
+// sim_PDNEnable_MTK((sim_HW_cb *) hwCbArray[interface]);
+ return KAL_TRUE;
+ }
+ else
+ {
+// sim_PDNEnable_MTK((sim_HW_cb *) hwCbArray[interface]);
+ return KAL_FALSE;
+ }
+}
+
+void Set_IFSC(kal_uint8 ifs, kal_uint8 interface)
+{
+ usim_dcb_struct *usim_dcb;
+
+ usim_dcb = GET_USIM_CB(interface);
+ usim_dcb->ifsc = ifs;
+}
+#endif
+
+#if defined(__SPEED_TEST__)
+void Set_Speed(kal_uint8 select_speed)
+{
+ speed_test = select_speed;
+ speed_test_enable = KAL_TRUE;
+}
+#endif
+
+#if !defined(SIM_DRV_HISR_INIT_CENTRALIZATION)
+void l1usim_init_hisr(sim_HW_cb *hw_cb)
+{
+ if (SIM_base == hw_cb->mtk_baseAddr)
+ {
+ if (usim_hisrid == NULL)
+ {
+ usim_hisrid = kal_init_hisr(USIM_HISR);
+ }
+ }
+ else if (SIM2_base == hw_cb->mtk_baseAddr)
+ {
+ if (usim2_hisrid == NULL)
+ {
+ usim2_hisrid = kal_init_hisr(USIM2_HISR);
+ }
+ }
+ else
+ SIM_DEBUG_ASSERT(0);
+
+}
+#endif
+
+sim_ctrlDriver sim_ctrlDriver_MTK =
+{
+ L1sim_Reset_MTK,
+ L1sim_Cmd_MTK,
+ L1sim_PowerOff_MTK,
+ L1sim_Get_Card_Info_MTK,
+ L1sim_Enable_Enhanced_Speed_MTK,
+ L1sim_Select_Prefer_PhyLayer_MTK,
+ L1sim_Set_ClockStopMode_MTK,
+ L1sim_EOC_MTK,
+ sim_addMsg,
+ sim_toutTest
+};
+
+
+//--------------------------------------------------------------------------//
+// usim driver unit test code
+//--------------------------------------------------------------------------//
+/*
+The behavior of the T1 controller
+1. enable T1 controller
+2. write NAD, PCB, LEN into SIM_DATA
+3. write LEN into SIMP3
+4. configure the DMA for data transfer (INF field)
+5. write any value into SIM_INS (trigger to start)
+6. generate the T1END interrupt.
+7. if a response block is received, T1END is generated again
+8. The received block is in the data buffer, the EDC is checked and removed.
+*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef PINCODE_TEST
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if 0
+#ifdef GEMINI_UNIT_TEST_ON_2_TASK
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else // USIM_DEBUG
+void usim_ut_main(void)
+{
+}
+#endif // USIM_DEBUG
+#endif // __USIM_DRV__
+#endif //DRV_MULTIPLE_SIM
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
+
+#endif //DRV_SIM_OFF
diff --git a/mcu/driver/devdrv/usim/src/usim_smt.c b/mcu/driver/devdrv/usim/src/usim_smt.c
new file mode 100644
index 0000000..7ebc59f
--- /dev/null
+++ b/mcu/driver/devdrv/usim/src/usim_smt.c
@@ -0,0 +1,1594 @@
+#include "kal_public_api.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+
+#include "sim_hw_mtk.h"
+#include "sim_drv_HW_def_MTK.h"
+#include "sim_al.h"
+#include "sim_drv_SW_struct.h"
+#include "sim_drv_SW_API.h"
+
+#include "sim_drv_SW_function.h"
+
+#include "drv_rstctl.h"
+#include "drvpdn.h"
+#include "drv_gdma.h"
+#include "us_timer.h"
+
+
+#define USIM_ATRSTA_OFF 0x0001
+
+#define USIM_3_3V KAL_TRUE
+#ifdef USIM_3_3V
+ #define USIM_VOL_CFG 0x1
+#else
+ #define USIM_VOL_CFG 0x0
+#endif
+
+#define USIM_SMT_NO_ERROR 0x0
+#define USIM_SMT_NO_TS 0x1
+#define USIM_SMT_NO_TOUT 0x2
+#define USIM_SMT_NO_T0END 0x3
+#define USIM_SMT_NO_ATRSTA_OFF 0x4
+#define USIM_SMT_SW_ERROR 0x5
+#define USIM_SMT_COUNT_ERROR 0x6
+#define USIM_SMT_HDMA_ERROR 0x7
+#define USIM_SMT_IFCLR_ERROR 0x8
+#define USIM_SMT_PPS_ERROR 0x9
+#define USIM_SMT_MT6306_ERROR 0xA
+#define USIM_SMT_INVALID_TS 0xB
+#define USIM_SMT_TOO_MANY_ATR 0xC
+#define USIM_SMT_ATR_TIMEOUT 0xD
+#define USIM_SMT_UNEXPT_DATA 0xE
+#define USIM_SMT_INTERFACE_ERROR 0xF
+
+// macro
+#define USIM_SMT_UPDATE_USIM_IF_FLAG(_if) do { \
+ if((_if) == 0) \
+ { \
+ usim_base = SIM_base; \
+ } else if((_if) == 1) \
+ { \
+ usim_base = SIM2_base; \
+ } else SIM_DEBUG_ASSERT(0); \
+ } while(0)
+
+#define USIM_SMT_BASIC_SETTING(_if) do { \
+ if((_if) == 0) \
+ { \
+ PDN_CLR(PDN_USIM1); \
+ HDMA_PDN_CLR(0); \
+ } else if((_if) == 1) \
+ { \
+ PDN_CLR(PDN_USIM2); \
+ HDMA_PDN_CLR(1); \
+ } else SIM_DEBUG_ASSERT(0); \
+ usim_iftest_sw_reset_usim((_if)); \
+ } while(0)
+
+#ifdef __FPGA__
+#define USIM_SMT_DEACTIVATION(_if) do { \
+ DRV_Reg32(usim_base + SIM_CTRL_MTK) = (DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON)); \
+ } while(0)
+#else
+#define USIM_SMT_DEACTIVATION(_if) do { \
+ DRV_WriteReg32((usim_base + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF); \
+ DRV_WriteReg32((usim_base + SIM_CTRL_MTK), DRV_Reg32(usim_base + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ DRV_Reg32(usim_base + SIM_CTRL_MTK) = (DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON)); \
+ while(!(DRV_Reg32(usim_base + SIM_ATRSTA_MTK) & 0x0001)); \
+ DRV_ICC_PMU_switch((_if), KAL_FALSE); \
+ } while(0)
+#endif
+
+extern kal_uint32 sim_uncachedTxBuffer0[], sim_uncachedRxBuffer0[], sim_uncachedTxBuffer1[], sim_uncachedRxBuffer1[];
+
+int usim_iftest_for_smt(kal_uint32 hwInterfaceNo);
+void usim_iftest_sw_reset_usim(kal_uint32 hwInterfaceNo);
+
+extern kal_char sim_shared_dbgstr[];
+#if !defined(ATEST_DRV_ENABLE)
+extern void slt_dbg_print(char *fmt, ...);
+#else
+#define slt_dbg_print(...) dbg_print( __VA_ARGS__)
+#endif
+
+#ifdef SIM_DRV_SWITCH_MT6306
+#include "sim_mt6306.h"
+extern void MT6306_Writer_GPIO(kal_uint8 device_addr, kal_uint8 data_addr, kal_uint8 data_value);
+extern void MT6306_HW_I2C_writer(kal_uint8 addr, kal_uint8 data_addr, kal_uint8 data_value);
+extern kal_uint32 MT6306_geti2cInterface(kal_uint32 MT6306Interface);
+extern kal_uint8 MT6306_Reader_AL(kal_uint8 chipno, kal_uint16 addr);
+extern kal_bool MT6306_ShowReg(int chip);
+extern DCL_HANDLE clkHandle, datHandle;;
+
+static int MT6306_validateREG(kal_uint8 chipno, kal_uint8 reg, kal_uint8 writeVal)
+{
+ kal_uint8 readvalue = MT6306_Reader_AL(chipno, reg);
+ kal_uint32 log_size = 0;
+
+ if (readvalue != writeVal)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]MT6306 Error: chip:%d, reg:%x, Write:%x, Read:%x\n\r", chipno, reg, writeVal, readvalue);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+
+ return USIM_SMT_MT6306_ERROR;
+ }
+
+ return USIM_SMT_NO_ERROR;
+}
+
+int MT6306_blockRST(kal_uint8 chipno, kal_uint8 port, kal_uint8 level)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_RST);
+
+ value |= (1 << port);
+ value &= ~(4 << port);
+ if (level) value |= (4 << port);
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_RST, value);
+}
+
+int MT6306_blockCLK(kal_uint8 chipno, kal_uint8 port)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_CLK);
+
+ value &= ~(1 << port);
+ value &= ~(4 << port);
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_CLK, value);
+}
+
+int MT6306_blockDAT(kal_uint8 chipno, kal_uint8 port)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_DAT);
+
+ value &= ~(1 << port);
+ value &= ~(4 << port);
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_DAT, value);
+}
+
+int MT6306_passRST(kal_uint8 chipno, kal_uint8 port)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_RST);
+
+ value &= ~(1 << port);
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_RST, value);
+}
+
+int MT6306_passCLK(kal_uint8 chipno, kal_uint8 port)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_CLK);
+
+ value |= (1 << port);
+ value &= ~(4 << port);
+
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_CLK, value);
+}
+
+int MT6306_passDAT(kal_uint8 chipno, kal_uint8 port)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_DAT);
+
+ value |= (1 << port);
+ value &= ~(4 << port);
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_DAT, value);
+}
+
+int MT6306_setVCC(kal_uint8 chipno, kal_uint8 port, kal_uint32 onoff, kal_uint32 level)
+{
+ kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_VCC);
+
+ if (onoff == 0) value &= ~(4 << port);
+ else value |= (4 << port);
+
+ if (level == 0) value &= ~(1 << port);
+ else value |= (1 << port);
+
+ if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
+ MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_VCC + (chipno * 4), value);
+ else
+ MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_VCC + (chipno * 4), value);
+
+ return MT6306_validateREG(chipno, SIM_MT6306_REG_VCC, value);
+}
+
+int MT6306_passALLSignal(kal_uint8 chipno, kal_uint8 port)
+{
+ int result = USIM_SMT_NO_ERROR;
+
+ result |= MT6306_passRST(chipno, port);
+ result |= MT6306_passCLK(chipno, port);
+ result |= MT6306_passDAT(chipno, port);
+
+ return result;
+}
+
+int MT6306_blockALLSignal(kal_uint8 chipno, kal_uint8 port)
+{
+ int result = USIM_SMT_NO_ERROR;
+
+ result |= MT6306_blockRST(chipno, port, 0);
+ result |= MT6306_blockCLK(chipno, port);
+ result |= MT6306_blockDAT(chipno, port);
+
+ return result;
+}
+#endif // #ifdef SIM_DRV_SWITCH_MT6306
+
+#ifdef __FPGA__
+#else
+// extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
+#endif
+
+static int usim_iftest_sim_activation_conv(kal_uint32 hwInterfaceNo, kal_uint32 class_b_or_c, usim_dir_enum conv)
+{
+ kal_uint32 usim_base = 0;
+ kal_uint16 reg_val = 0;
+
+ // 0. Update USIM interface flag
+ USIM_SMT_BASIC_SETTING(hwInterfaceNo);
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ // 1. get ATR STR
+#ifdef __FPGA__
+#else
+ // 1.0 Deactivate SIM
+ DRV_ICC_PMU_switch(hwInterfaceNo, KAL_FALSE);
+ ust_us_busyloop(50000);
+#endif
+#if defined(DRV_SIM_6292_SERIES)|| defined(DRV_SIM_6293_SERIES)
+ DRV_Reg32(usim_base + SIM_BRR_MTK) = (372 << 2);
+#elif defined(SIM_DRV_3_71MHZ_SCLK)
+ DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x0800) | (372 << 2);
+#else
+ DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | (372 << 2);
+#endif
+ DRV_Reg32(usim_base + SIM_TOUT_MTK) = (10000 >> 4) + 1;
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN);
+ DRV_Reg32(usim_base + SIM_CTRL_MTK) = DRV_Reg32(usim_base + SIM_CTRL_MTK) & ~(SIM_CTRL_SIMON);
+
+ // 1.1 Set RXTIDE of SIM_TIDE to 0 and TXTIDE to 1
+ DRV_Reg32(usim_base + SIM_TIDE_MTK) = (DRV_Reg32(usim_base + SIM_TIDE_MTK) & (~SIM_TIDE_RXMASK) & (~SIM_TIDE_TXMASK)) | 0x0100;
+
+ // 1.2 Clear Interrupt
+ DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
+
+ // 1.3 If TOUT = 1, T0EN/T1EN = 0
+ reg_val = (DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_T0EN | SIM_CONF_T1EN | SIM_CONF_TOUTEN | USIM_VOL_CFG)) | (SIM_CONF_TOUTEN | USIM_VOL_CFG);
+ if (conv == USIM_DIRECT)
+ {
+ reg_val &= ~(SIM_CONF_CONV);
+ }
+ else
+ {
+ reg_val |= SIM_CONF_CONV;
+ }
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = reg_val;
+#ifdef __FPGA__
+#else
+ DRV_ICC_PMU_setVolt(hwInterfaceNo, class_b_or_c);
+ DRV_ICC_PMU_switch(hwInterfaceNo, KAL_TRUE);
+#endif
+ // 1.4 Set SIMON, Activate SIM
+ DRV_Reg32(usim_base + SIM_CTRL_MTK) = (DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON)) | SIM_CTRL_SIMON;
+
+ return 0;
+}
+
+int usim_iftest_sim_activation(kal_uint32 hwInterfaceNo, kal_uint32 class_b_or_c)
+{
+ return usim_iftest_sim_activation_conv(hwInterfaceNo, class_b_or_c, USIM_DIRECT);
+}
+
+int usim_iftest_sim_activation_inverse(kal_uint32 hwInterfaceNo, kal_uint32 class_b_or_c)
+{
+ return usim_iftest_sim_activation_conv(hwInterfaceNo, class_b_or_c, USIM_INVERSE);
+}
+
+int usim_iftest_tout_test(kal_uint32 hwInterfaceNo) {
+ kal_uint32 usim_base = 0;
+ kal_uint32 orig_brr = 0;
+ kal_uint32 ret_val = USIM_SMT_NO_ERROR;
+ kal_uint32 etu_setting = 0, tout_setting = 0, int_sts = 0;
+
+ // 0. Update USIM interface flag
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ // 1. Disable Interrupt & Clear Interrupt Status
+ DRV_Reg32(usim_base + SIM_IRQEN_MTK) = 0;
+ DRV_Reg32(usim_base + SIM_STS_MTK) = 0xFFFFFFFF;
+
+ // 2. Save BRR, will restore before case complete
+ orig_brr = DRV_Reg32(usim_base + SIM_BRR_MTK);
+
+ for (etu_setting = 16; etu_setting <= 32 && ret_val == USIM_SMT_NO_ERROR; etu_setting *= 2) {
+ // Set 1ETU = etu_setting CLK
+ DRV_Reg32(usim_base + SIM_BRR_MTK) = (orig_brr & (~(0x1FF<<2))) | (16<<2);
+
+ for (tout_setting = 5; tout_setting < 10; tout_setting += 2) {
+ // 3. Set TOUT to (tout_setting+1)*16ETU
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & (~SIM_CONF_TOUTEN);
+ DRV_Reg32(usim_base + SIM_TOUT_MTK) = tout_setting; // means (tout_setting+1)*16 ETU
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) | (SIM_CONF_TOUTEN);
+
+ // 4. Wait TOUT Interrupt Status
+ kal_uint32 start_time = ust_get_current_time();
+ kal_uint32 duration;
+ while ((duration = ust_us_duration(start_time, ust_get_current_time())) < 10*1000) {
+ // TOUT should happen after ([6,8,10])*16*([16,32])=1536~5120 SIM CLKs@3.25MHz < 1.58ms
+ if ((int_sts = DRV_Reg32(usim_base + SIM_STS_MTK)) & SIM_STS_TOUT) {
+ break;
+ }
+ }
+
+ DRV_Reg32(usim_base + SIM_STS_MTK) = int_sts;
+ if ((int_sts & SIM_STS_TOUT) == 0) {
+ ret_val = USIM_SMT_NO_TOUT;
+ slt_dbg_print("[SIM_SMT]: TOUT not happen when etu=%d tout=%d\r\n", etu_setting, tout_setting);
+ break;
+ }
+
+ // Check duration ???
+ }
+ }
+
+ // 5. Disable TOUT & Clear Interrupt Status & Restore BRR
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & (~SIM_CONF_TOUTEN);
+ DRV_Reg32(usim_base + SIM_STS_MTK) = 0xFFFFFFFF;
+ DRV_Reg32(usim_base + SIM_BRR_MTK) = orig_brr;
+
+ return ret_val;
+}
+
+void pmic_dump(void)
+{
+/*
+ int i, j = 0;
+ kal_uint32 val = 0;
+
+ for (i = 0; i < 0xff0; i += 2)
+ {
+ if (j % 5) slt_dbg_print("[PMIC_DVT] ");
+#ifdef __FPGA__
+#else
+ val = DRV_Read_PMIC_Data(i);
+#endif
+
+ if (val != 0x5aa5) slt_dbg_print("[0x%x]= 0x%x ", i, val);
+
+ j++;
+
+ if ((j % 5) == 0) slt_dbg_print("\n\r");
+ }
+*/
+ return;
+}
+
+void sim_dump_reg_debug(kal_uint32 usim_base)
+{
+ slt_dbg_print("SIM Reg Dump: \n\r");
+ slt_dbg_print("%x, %x, %x, %x, %x\n\r", usim_base, DRV_Reg32(usim_base + SIM_VERSION_MTK),
+ DRV_Reg32(usim_base + SIM_CTRL_MTK), DRV_Reg32(usim_base + SIM_CONF_MTK), DRV_Reg32(usim_base + SIM_CONFSTA_MTK));
+
+ slt_dbg_print("%x, %x, %x, %x, %x\n\r", DRV_Reg32(usim_base + SIM_BRR_MTK), DRV_Reg32(usim_base + SIM_IRQEN_MTK),
+ DRV_Reg32(usim_base + SIM_STS_MTK), DRV_Reg32(usim_base + SIM_RETRY_MTK), DRV_Reg32(usim_base + SIM_TIDE_MTK));
+
+ slt_dbg_print("%x, %x, %x, %x, %x\n\r", 0, DRV_Reg32(usim_base + SIM_COUNT_MTK),
+ DRV_Reg32(usim_base + SIM_ATIME_MTK), DRV_Reg32(usim_base + SIM_DTIME_MTK), DRV_Reg32(usim_base + SIM_TOUT_MTK));
+
+ slt_dbg_print("%x, %x, %x, %x, %x\n\r", DRV_Reg32(usim_base + SIM_GTIME_MTK), DRV_Reg32(usim_base + SIM_ETIME_MTK),
+ DRV_Reg32(usim_base + SIM_EXT_TIME_MTK), DRV_Reg32(usim_base + SIM_CGTIME_MTK), DRV_Reg32(usim_base + SIM_COMDCTRL_MTK));
+
+ slt_dbg_print("%x, %x, %x, %x, %x\n\r", DRV_Reg32(usim_base + SIM_COMDLEN_MTK), DRV_Reg32(usim_base + SIM_LEFTLEN_MTK),
+ DRV_Reg32(usim_base + SIM_SW1_MTK), DRV_Reg32(usim_base + SIM_SW2_MTK), DRV_Reg32(usim_base + SIM_ATRSTA_MTK));
+
+ return;
+}
+
+int usim_iftest_get_atr(kal_uint32 hwInterfaceNo, kal_uint8 atr_bytes[])
+{
+ kal_uint32 usim_base = 0, log_size = 0;
+ kal_uint8 *atr_ptr = atr_bytes + 1;
+ kal_uint8 TS, TDi, hist_cnt, next_cnt;
+ kal_uint32 start_time = 0;
+ kal_bool T0_Recved = KAL_FALSE, Hist_Recved = KAL_FALSE;
+ int ret_val = USIM_SMT_NO_ERROR;
+
+start:
+
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+ start_time = ust_get_current_time();
+
+ // Wait first bytes of ATR
+ while (DRV_Reg32(usim_base + SIM_COUNT_MTK) == 0) {
+ if (DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_NATR) {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: NO TS, %x, %d\n\r", usim_base, hwInterfaceNo);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ ret_val = USIM_SMT_NO_TS;
+ goto end;
+ }
+ }
+
+ // Check if TS is valid
+ TS = DRV_Reg32(usim_base + SIM_DATA_MTK);
+ if (TS != 0x3B && TS != 0x3F) {
+ if (TS == 0x03) {
+ // Inverse Convention 0x3F will be decoded as 0x03 in Direct Convention
+ usim_iftest_sim_activation_inverse(hwInterfaceNo, CLASS_B_30V);
+ goto start;
+ } else {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Invalid TS, %x, %d, %x\n\r", usim_base, hwInterfaceNo, TS);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ ret_val = USIM_SMT_INVALID_TS;
+ goto end;
+ }
+ }
+
+
+ // Got Valid TS
+ *atr_ptr++ = TS;
+
+ // Receive other ATR bytes
+ next_cnt = 1; // To read T0
+ for (;;) {
+ while (next_cnt > 0) {
+ if (DRV_Reg32(usim_base + SIM_COUNT_MTK) > 0) {
+ *atr_ptr++ = DRV_Reg32(usim_base + SIM_DATA_MTK);
+ next_cnt --;
+
+ if (atr_ptr - atr_bytes - 1 > 32) {
+ ret_val = USIM_SMT_TOO_MANY_ATR;
+ DRV_ICC_print_str("[SIM_SMT]: Received ATR data > 32 bytes");
+ goto end;
+ }
+ }
+
+ if ((DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_TOUT) != 0
+ || ust_us_duration(start_time, ust_get_current_time()) > 2*1000*1000L ) {
+ // Actually TOUT should happen if it's functinality is OK
+ ret_val = USIM_SMT_ATR_TIMEOUT;
+ DRV_ICC_print_str("[SIM_SMT]: Timeout when receiving ATR data");
+ goto end;
+ }
+ }
+
+ if (Hist_Recved == KAL_TRUE) {
+ // All ATR bytes have been received, excluding the optional byte of TCK
+ kal_uint32 tck_poll_start = ust_get_current_time();
+ while(ust_us_duration(tck_poll_start, ust_get_current_time()) < 10*1000) {
+ // TCK will come in 12 ETU, 1.4ms@3.25MHz SIM CLK, if not coming TCK is not exist
+ if (DRV_Reg32(usim_base + SIM_COUNT_MTK) > 0) {
+ *atr_ptr++ = DRV_Reg32(usim_base + SIM_DATA_MTK); // TCK
+ break;
+ }
+ }
+
+ // SIO should be idle now, Check TOUT function
+ if (usim_iftest_tout_test(hwInterfaceNo) != USIM_SMT_NO_ERROR) {
+ ret_val = USIM_SMT_NO_TOUT;
+ goto end;
+ }
+
+ // Check if more data in FIFO, it's error if there are more data
+ if (DRV_Reg32(usim_base + SIM_COUNT_MTK) > 0) {
+ ret_val = USIM_SMT_UNEXPT_DATA;
+ DRV_ICC_print_str("[SIM_SMT]: ATR received, but have unexpected data in FIFO");
+ goto end;
+ }
+
+ // Now, every thing should be good
+ atr_bytes[0] = atr_ptr - atr_bytes - 1;
+ goto end;
+ }
+
+ TDi = atr_ptr[-1]; // T0, TD1, TD2, ...
+
+ if (T0_Recved == KAL_FALSE) {
+ T0_Recved = KAL_TRUE;
+ hist_cnt = TDi&0x0F;
+ }
+
+ next_cnt = 0; // actually, it have already been 0
+ USIM_CAL_TD_COUNT(TDi, next_cnt);
+
+ if (TDi & TDMask) {
+ next_cnt ++;
+ } else {
+ next_cnt += hist_cnt;
+ Hist_Recved = KAL_TRUE;
+ }
+ }
+
+end:
+ if (ret_val != USIM_SMT_NO_ERROR) {
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN);
+ DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
+
+ sim_dump_reg_debug(usim_base);
+ pmic_dump();
+
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ }
+ return ret_val;
+}
+
+int usim_iftest_send_pps(kal_uint32 hwInterfaceNo, kal_uint8 atr_bytes[], kal_uint8 pps_buf[], kal_bool *need_pps)
+{
+ kal_uint32 usim_base = 0, j = 0, log_size = 0;
+ kal_uint32 cksum = 0xFF;
+
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ if (atr_bytes[2] & 0x80) // TD1
+ {
+ j = 0;
+ if (atr_bytes[2] & 0x10) j++;
+ if (atr_bytes[2] & 0x20) j++;
+ if (atr_bytes[2] & 0x40) j++;
+ if (atr_bytes[2] & 0x80) j++;
+ if (atr_bytes[2 + j] & 0x10) // TA2
+ {
+ // TA1 && negotiable TA2
+ if ((atr_bytes[2] & 0x10) && (atr_bytes[2 + j + 1] & 0x80) == 0x0) *need_pps = KAL_TRUE;
+ }
+ else
+ {
+ // TA1 && TD1
+ if ((atr_bytes[2] & 0x10)) *need_pps = KAL_TRUE;
+ }
+ }
+ else if (atr_bytes[2] & 0x10) // TA1 && no TD1
+ {
+ *need_pps = KAL_TRUE;
+ }
+
+ *need_pps = atr_bytes[3] != 0x01 && atr_bytes[3] != 0x11 && (atr_bytes[2] & 0x10) && *need_pps;
+
+ if (*need_pps)
+ {
+ // Set TOUT = 1
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = (DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN | USIM_VOL_CFG)) | (SIM_CONF_TOUTEN | USIM_VOL_CFG);
+ // Clear
+ DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) = DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) | SIM_CTRL_IFCLR;
+ j = 0;
+ while (DRV_Reg32(usim_base + SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON)
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: IFCLR ERROR\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_IFCLR_ERROR;
+ }
+ j++;
+ }
+
+ // Set RXTIDE of SIM_TIDE to 0 and TXTIDE to 1
+ DRV_Reg32(usim_base + SIM_TIDE_MTK) = (DRV_Reg32(usim_base + SIM_TIDE_MTK) & (~SIM_TIDE_RXMASK) & (~SIM_TIDE_TXMASK)) | 0x0100;
+
+ j = 0;
+ // Send PPSS
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = 0xFF;
+ pps_buf[j++] = 0xFF;
+ // Send PPS0
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = 0x10;
+ cksum ^= 0x10;
+ pps_buf[j++] = 0x10;
+ // Send PPS1
+ // Propose new Fi, Di
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = atr_bytes[3];
+ cksum ^= atr_bytes[3];
+ pps_buf[j++] = atr_bytes[3];
+
+ // Send PCK
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = cksum;
+ pps_buf[j++] = cksum;
+
+ // Wait Until TX FIFO Empty
+ j = 0;
+ while (DRV_Reg32(usim_base + SIM_COUNT_MTK) != 0)
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: COUNT ERROR\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_COUNT_ERROR;
+ }
+ j++;
+
+ }
+ }
+
+ return 0; // temp
+}
+
+int usim_iftest_get_pps(kal_uint32 hwInterfaceNo, kal_uint8 atr_bytes[], kal_uint8 pps_buf[], kal_bool need_pps)
+{
+ kal_uint32 usim_base = 0, i = 0, j = 0;
+ kal_uint32 data = 0, fifo_cnt = 0, log_size = 0;
+
+ if (need_pps == KAL_FALSE) return 0;
+
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ // PPS Exchange RX
+ while (1)
+ {
+ fifo_cnt = DRV_Reg32(usim_base + SIM_COUNT_MTK);
+
+ // FIFO Non-Empty
+ if (fifo_cnt != 0x0)
+ {
+ for (i = 0; i < fifo_cnt; i++)
+ {
+ data = DRV_Reg32(usim_base + SIM_DATA_MTK);
+ if (pps_buf[j++] != data)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: not consistent:%x %x\n\r", data, pps_buf[j - 1]);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ return USIM_SMT_PPS_ERROR;
+ }
+ }
+ }
+
+ // TOUT status = 1
+ if ((DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_TOUT) || (j >= 4))
+ {
+ if (data == 0)
+ {
+ if (DRV_Reg32(usim_base + SIM_COUNT_MTK) == 0x0)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: USIM does not reply on time\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ return USIM_SMT_PPS_ERROR;
+ }
+ }
+
+ // Clear Interrupt
+ DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
+ // Clear IP's Internal TOUT enable bit
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = (DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN | USIM_VOL_CFG)) | (USIM_VOL_CFG);
+ break;
+ }
+ }
+
+ if (atr_bytes[3] == ATR_TA1_64) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 8) << 2);
+ else if (atr_bytes[3] == ATR_TA1_32) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 16) << 2);
+ else if (atr_bytes[3] == ATR_TA1_16) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 32) << 2);
+ else if (atr_bytes[3] == ATR_TA1_8) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 64) << 2);
+ else SIM_DEBUG_ASSERT(0);
+
+ return 0;
+}
+
+
+
+int usim_iftest_send_sim_command(kal_uint32 hwInterfaceNo, kal_uint8 tx_buf[], kal_uint32 tx_len, kal_uint32 rx_len)
+{
+ kal_uint32 usim_base = 0, i = 0, j = 0, log_size = 0;
+
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ // clear
+ DRV_Reg32(usim_base + SIM_CTRL_MTK) = DRV_Reg32(usim_base + SIM_CTRL_MTK) | SIM_CTRL_IFCLR;
+ j = 0;
+ while (DRV_Reg32(usim_base + SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON)
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, " [SIM_SMT]: IFCLR ERROR\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_IFCLR_ERROR ;
+ }
+ j++;
+ }
+ // 2.0 Select File of ICCID
+ // 2.0 set file id
+
+ // 2.1 Set RXTIDE of SIM_TIDE to 0 and TXTIDE to 1 (Note: TXTIDE cannot be 0 for DMA)
+ DRV_Reg32(usim_base + SIM_TIDE_MTK) = (DRV_Reg32(usim_base + SIM_TIDE_MTK) & (~SIM_TIDE_RXMASK) & (~SIM_TIDE_TXMASK)) | 0x0100;
+
+ // 2.2 Enable T0
+ DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) | SIM_CONF_T0EN;
+
+ // 2.3 Directly Write File ID to USIM FIFO
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[0];
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[1];
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[2];
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[3];
+ DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[4];
+
+ if (tx_len > 5)
+ {
+ if (hwInterfaceNo)
+ {
+ // HDMA TX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
+ for (i = 5; i < tx_len; i++)
+ DRV_Reg8(((kal_uint32) sim_uncachedTxBuffer1) + i - 5) = tx_buf[i];
+
+ MM_Sync();
+
+ DRV_Reg32(REG_HDMA_HDCTRR1) = HDCTRR_RX_SEL0(0) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
+ DRV_Reg32(REG_HDMA_HPRGA0R1) = (kal_uint32) sim_uncachedTxBuffer1;
+ DRV_Reg32(REG_HDMA_HDC0R1) = HDCR_XFER_SIZE0(tx_buf[4]) | HDCR_START0;
+ }
+ else
+ {
+ // HDMA TX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
+ for (i = 5; i < tx_len; i++)
+ DRV_Reg8(((kal_uint32) sim_uncachedTxBuffer0) + i - 5) = tx_buf[i];
+
+ MM_Sync();
+
+ DRV_Reg32(REG_HDMA_HDCTRR0) = HDCTRR_RX_SEL0(0) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
+ DRV_Reg32(REG_HDMA_HPRGA0R0) = (kal_uint32) sim_uncachedTxBuffer0;
+ DRV_Reg32(REG_HDMA_HDC0R0) = HDCR_XFER_SIZE0(tx_buf[4]) | HDCR_START0;
+ }
+ }
+
+ // for Get Responseo
+ if (rx_len && tx_len <= 5)
+ {
+ if (hwInterfaceNo)
+ {
+ // HDMA RX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
+ DRV_Reg32(REG_HDMA_HDCTRR1) = HDCTRR_RX_SEL0(1) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
+ DRV_Reg32(REG_HDMA_HPRGA0R1) = (kal_uint32) sim_uncachedRxBuffer1;
+ DRV_Reg32(REG_HDMA_HDC0R1) = HDCR_XFER_SIZE0(rx_len) | HDCR_START0;
+ }
+ else
+ {
+ // HDMA RX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
+ DRV_Reg32(REG_HDMA_HDCTRR0) = HDCTRR_RX_SEL0(1) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
+ DRV_Reg32(REG_HDMA_HPRGA0R0) = (kal_uint32) sim_uncachedRxBuffer0;
+ DRV_Reg32(REG_HDMA_HDC0R0) = HDCR_XFER_SIZE0(rx_len) | HDCR_START0;
+ }
+ }
+
+ DRV_Reg32(usim_base + SIM_COMDLEN_MTK) = tx_buf[4];
+
+ if (tx_len > 5)
+ {
+ DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) = SIM_INS_START | SIM_INS_INSD | tx_buf[1]; // Expect to Send
+ }
+ else if (rx_len && tx_len <= 5)
+ {
+ DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) = SIM_INS_START | tx_buf[1]; // Expect to Send
+ }
+
+ MO_Sync();
+
+ return 0;
+}
+
+int usim_iftest_get_sim_response(kal_uint32 hwInterfaceNo, kal_bool rx_data, kal_uint32 *sw1, kal_uint32 *sw2)
+{
+ kal_uint32 usim_base = 0, log_size = 0;
+ kal_uint32 j = 0;
+
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ // Wait Until TX FIFO Empty
+ j = 0;
+ while (DRV_Reg32(usim_base + SIM_COUNT_MTK) != 0)
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: COUNT ERROR\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_COUNT_ERROR;
+ }
+ j++;
+ }
+
+ // 2.4 Wait for Operation Done (Including Response)
+ j = 0;
+ while (!(DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_T0END))
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT:%d]: NO T0END\n\r", __LINE__);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_NO_T0END;
+ }
+ j++;
+ }
+
+ if (rx_data)
+ {
+ j = 0;
+ if (hwInterfaceNo)
+ {
+ while ((DRV_Reg32(REG_HDMA_HDSR) & HDMA_STAT0_1))
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: HDMA ERROR\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_HDMA_ERROR;
+ }
+ j++;
+ }
+ /*
+ kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
+ sim_uncachedRxBuffer1[0], sim_uncachedRxBuffer1[1], sim_uncachedRxBuffer1[2], sim_uncachedRxBuffer1[3], sim_uncachedRxBuffer1[4],
+ sim_uncachedRxBuffer1[5], sim_uncachedRxBuffer1[6], sim_uncachedRxBuffer1[7], sim_uncachedRxBuffer1[8], sim_uncachedRxBuffer1[9],
+ sim_uncachedRxBuffer1[10], sim_uncachedRxBuffer1[11], sim_uncachedRxBuffer1[12], sim_uncachedRxBuffer1[13], sim_uncachedRxBuffer1[14]);
+ */
+
+ for (j=0;j<15;j++)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %d:%x\r\n", j, *(((kal_uint8 *) sim_uncachedRxBuffer1) + j));
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ }
+
+ }
+ else
+ {
+ while ((DRV_Reg32(REG_HDMA_HDSR) & HDMA_STAT0_0))
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: HDMA ERROR\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_HDMA_ERROR;
+ }
+ j++;
+ }
+ /*
+ kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
+ sim_uncachedRxBuffer0[0], sim_uncachedRxBuffer0[1], sim_uncachedRxBuffer0[2], sim_uncachedRxBuffer0[3], sim_uncachedRxBuffer0[4],
+ sim_uncachedRxBuffer0[5], sim_uncachedRxBuffer0[6], sim_uncachedRxBuffer0[7], sim_uncachedRxBuffer0[8], sim_uncachedRxBuffer0[9],
+ sim_uncachedRxBuffer0[10], sim_uncachedRxBuffer0[11], sim_uncachedRxBuffer0[12], sim_uncachedRxBuffer0[13], sim_uncachedRxBuffer0[14]);
+ */
+ for (j=0;j<15;j++)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %d:%x\r\n", j, *(((kal_uint8 *) sim_uncachedRxBuffer0) + j));
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ }
+ }
+ //DRV_ICC_print_str(sim_shared_dbgstr);
+ }
+
+ // 2.5 Clear Interrupt
+ DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
+
+ // 2.6 Check Returned Status Bytes
+ *sw1 = DRV_Reg32(usim_base + SIM_SW1_MTK);
+ *sw2 = DRV_Reg32(usim_base + SIM_SW2_MTK);
+
+ if ((*sw1 & 0xF0) != 0x90 && *sw1 != 0x69)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: SW ERROR %x %x\n\r", *sw1, *sw2);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_SW_ERROR;
+ }
+
+ return 0;
+}
+
+int usim_iftest_sim_deactivation(kal_uint32 hwInterfaceNo)
+{
+ kal_uint32 usim_base = 0, log_size = 0;
+ kal_uint32 j = 0;
+
+ USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
+
+ // 3. Deactivation
+ // 3.0 If SIM Aleady Activated, Deactivate it
+ DRV_Reg32(usim_base + SIM_CTRL_MTK) = DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON);
+ j = 0;
+ while (!(DRV_Reg32(usim_base + SIM_ATRSTA_MTK) & USIM_ATRSTA_OFF))
+ {
+ if (j > 0xFFFFFF)
+ {
+ USIM_SMT_DEACTIVATION(hwInterfaceNo);
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: NO ATRSTA OFF\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_NO_ATRSTA_OFF;
+ }
+ j++;
+ }
+#ifdef __FPGA__
+#else
+ DRV_ICC_PMU_switch(hwInterfaceNo, KAL_FALSE);
+#endif
+
+ return 0;
+}
+
+#if defined(__SIM_DRV_CO_LOAD_MT6306__) && defined(SIM_DRV_SWITCH_MT6306)
+ extern kal_bool sim_connectMT6306;
+#endif
+int usim_iftest_for_smt(kal_uint32 interfaceNo)
+{
+ kal_uint32 func_status = 0;
+ kal_uint8 atr_bytes[50] = {0}, tx_buf[25] = {0}, pps_buf[10] = {0};
+ kal_uint32 sw1 = 0, sw2 = 0;
+ kal_bool need_pps = KAL_FALSE, forced_18v = KAL_FALSE;
+ kal_uint32 class_b_or_c = CLASS_B_30V, hwInterfaceNo = interfaceNo & 0xF, log_size = 0;
+
+ if (interfaceNo & 0xF0)
+ forced_18v = KAL_TRUE;
+
+ interfaceNo = interfaceNo & 0xF;
+
+ // for 3-SIM project, check sim_connectMT6306
+ if (interfaceNo == 4)
+ {
+#if defined(SIM_DRV_SWITCH_MT6306) && defined(__SIM_DRV_CO_LOAD_MT6306__)
+ return (kal_uint32) sim_connectMT6306;
+#elif defined(SIM_DRV_SWITCH_MT6306) && !defined(__SIM_DRV_CO_LOAD_MT6306__)
+ return (kal_uint32) KAL_TRUE;
+#else
+ return (kal_uint32) KAL_FALSE;
+#endif
+ }
+
+#ifdef SIM_DRV_SWITCH_MT6306
+ // for 3-SIM project, interfaceNo != hwInterfaceNo
+ kal_uint8 port = 0, chip = 0;
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if(sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+ // hwInterfaceNo will be 0, 1, 2
+ hwInterfaceNo = interfaceNo / 2;
+ port = interfaceNo % 2;
+ chip = hwInterfaceNo;
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]hwInterfaceNo:%d, chip:%d, port:%d", hwInterfaceNo, chip, port);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+
+ // check hwInterfaceNo
+ if (hwInterfaceNo > 1)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Invalid Interface:%d\n\r",hwInterfaceNo);
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_INTERFACE_ERROR;
+ }
+
+ // Cards may be activated by other AT+CMD
+ usim_dcb_struct *usim_dcb;
+ usim_dcb = GET_USIM_CB(interfaceNo);
+ if (usim_dcb->present)
+ {
+ log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: driver status is correct\n\r");
+ if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
+ return USIM_SMT_NO_ERROR;
+ }
+
+ // adjust VCC (default 3V)
+#if defined(SIM_DRV_SWITCH_MT6306) && defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if(sim_connectMT6306 == KAL_TRUE) class_b_or_c = CLASS_C_18V;
+#elif defined(SIM_DRV_SWITCH_MT6306) && !defined(__SIM_DRV_CO_LOAD_MT6306__)
+ class_b_or_c = CLASS_C_18V;
+#else
+ if (forced_18v) class_b_or_c = CLASS_C_18V;
+#endif
+
+#ifdef SIM_DRV_SWITCH_MT6306
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if(sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+ //Block all chip, all port
+ if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(0, 0))
+ return USIM_SMT_MT6306_ERROR;
+ if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(0, 1))
+ return USIM_SMT_MT6306_ERROR;
+ if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(1, 0))
+ return USIM_SMT_MT6306_ERROR;
+ if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(1, 1))
+ return USIM_SMT_MT6306_ERROR;
+ if (USIM_SMT_NO_ERROR != MT6306_setVCC(chip, 0, 0, 0))//turn off port 0
+ return USIM_SMT_MT6306_ERROR;
+ if (USIM_SMT_NO_ERROR != MT6306_setVCC(chip, 1, 0, 0))//turn off port 1
+ return USIM_SMT_MT6306_ERROR;
+
+ // adjsut VCC
+ if (forced_18v == KAL_TRUE)
+ {
+ // CLASS_C_18V
+ MT6306_setVCC(hwInterfaceNo, port, 1, 0);
+ }
+ else
+ {
+ // CLASS_B_30V
+ MT6306_setVCC(hwInterfaceNo, port, 1, 1);
+ }
+
+ // pass all signals of (chip, port)
+ MT6306_passALLSignal(chip, port);
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+
+ usim_iftest_sim_activation(hwInterfaceNo, class_b_or_c);
+
+ func_status = usim_iftest_get_atr(hwInterfaceNo, atr_bytes);
+ if (func_status) return func_status;
+
+ func_status = usim_iftest_send_pps(hwInterfaceNo, atr_bytes, pps_buf, &need_pps);
+ if (func_status) return func_status;
+ func_status = usim_iftest_get_pps(hwInterfaceNo, atr_bytes, pps_buf, need_pps);
+ if (func_status) return func_status;
+ if (need_pps) kal_sleep_task(KAL_TICKS_50_MSEC);
+
+#define EF_ICCID 0x2FE2
+ tx_buf[0] = 0xA0;
+ tx_buf[1] = 0xA4;
+ tx_buf[2] = 0x00;
+ tx_buf[3] = 0x00;
+ tx_buf[4] = 0x02;
+ tx_buf[5] = 0x2F;
+ tx_buf[6] = 0xE2;
+ func_status = usim_iftest_send_sim_command(hwInterfaceNo, tx_buf, 7, 0);
+ if (func_status) return func_status;
+ func_status = usim_iftest_get_sim_response(hwInterfaceNo, KAL_FALSE, &sw1, &sw2);
+ if (func_status) return func_status;
+// --
+ tx_buf[0] = 0xA0;
+ tx_buf[1] = 0xC0;
+ tx_buf[2] = 0x00;
+ tx_buf[3] = 0x00;
+ tx_buf[4] = sw2;
+ func_status = usim_iftest_send_sim_command(hwInterfaceNo, tx_buf, 5, tx_buf[4]);
+ if (func_status) return func_status;
+ func_status = usim_iftest_get_sim_response(hwInterfaceNo, KAL_TRUE, &sw1, &sw2);
+ if (func_status) return func_status;
+// --
+ tx_buf[0] = 0xA0;
+ tx_buf[1] = 0xB0;
+ tx_buf[2] = 0x00;
+ tx_buf[3] = 0x00;
+ tx_buf[4] = 10;
+ func_status = usim_iftest_send_sim_command(hwInterfaceNo, tx_buf, 5, tx_buf[4]);
+ if (func_status) return func_status;
+ func_status = usim_iftest_get_sim_response(hwInterfaceNo, KAL_TRUE, &sw1, &sw2);
+ if (func_status) return func_status;
+
+ func_status = usim_iftest_sim_deactivation(hwInterfaceNo);
+
+#ifdef SIM_DRV_SWITCH_MT6306
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ if(sim_connectMT6306 == KAL_TRUE)
+ {
+#endif
+ // patch for 3-SIM USIMSMT
+ MT6306_blockALLSignal(chip, port);
+ MT6306_setVCC(hwInterfaceNo, port, 0, 0); //Turn off VSIM
+#if defined(__SIM_DRV_CO_LOAD_MT6306__)
+ }
+#endif
+#endif
+
+ if (func_status) return func_status;
+
+ return USIM_SMT_NO_ERROR;
+}
+
+void usim_iftest_sw_reset_usim(kal_uint32 hwInterfaceNo)
+{
+#if defined(MT6752)
+#endif
+ return;
+}
+#if defined(__IC_SLT__)
+typedef enum
+{
+ REG_GROUP_HDMA = 0,
+ REG_GROUP_USIM,
+ REG_GROUP_USIM2,
+ REG_GROUP_NUM,
+} REG_GROUP;
+typedef struct
+{
+ kal_uint32 addr;
+ kal_char attr[32];
+ kal_char reset_val[32];
+} usim_reg_desc_t;
+#define BASE_HDMA BASE_ADDR_MDGDMA
+#define REG_HDMA_HDCSR0 (BASE_HDMA + 0x0100)
+#define HDMA_MODE_0 (1 << 9) //channel 0
+#define HDMA_MODE_1 (1 << 25) //channel 1
+#define REG_HDMA_HDSR (BASE_HDMA + 0x0120) // shared
+#define HDMA_STAT0_0 (1 << 0) // buffer 0, channel 0
+#define HDMA_STAT0_1 (1 << 1) // buffer 0, channel 1
+#define HDMA_STAT1_0 (1 << 16) // buffer 1, channel 0
+#define HDMA_STAT1_1 (1 << 17) // buffer 1, channel 1
+#define REG_HDMA_HDCPR (BASE_HDMA + 0x0124) // shared
+#define HDMA_HCURR_PTR_0 (1 << 0) // channel 0
+#define HDMA_HCURR_PTR_1 (1 << 1) // channel 1
+#define REG_HDMA_HDCTRR0 (BASE_HDMA + 0x0140) // channel 0
+#define REG_HDMA_HDCTRR1 (BASE_HDMA + 0x0160) // channel 1
+#define HDCTRR_STOP (1 << 2)
+#define HDCTRR_MEM_BUS_WIDTH(n) ((n) << 4)
+#define HDCTRR_DEV_BUS_WIDTH(n) ((n) << 6)
+#define HDCTRR_BUS_WIDTH_8 0
+#define HDCTRR_BUS_WIDTH_16 1
+#define HDCTRR_BUS_WIDTH_32 2
+#define HDCTRR_BST_SIZE(n) ((n) << 12)
+#define HDCTRR_BST_SIZE_4 2
+#define HDCTRR_BST_SIZE_8 3
+#define HDCTRR_BST_SIZE_16 4
+#define HDCTRR_BST_SIZE_32 5 // reserved
+#define HDCTRR_BST_SIZE_64 6 // reserved
+#define HDCTRR_BST_SIZE_128 7 // reserved
+#define HDCTRR_RX_SEL0(n) ((n) << 30)
+#define HDCTRR_RX_SEL1(n) ((n) << 31)
+#define REG_HDMA_HDC0R0 (BASE_HDMA + 0x0144) // channel 0
+#define REG_HDMA_HDC0R1 (BASE_HDMA + 0x0164) // channel 1
+#define HDCR_XFER_SIZE0(n) ((n) << 16)
+#define HDCR_START0 (1 << 0)
+#define REG_HDMA_HDC1R0 (BASE_HDMA + 0x0148) // channel 0
+#define REG_HDMA_HDC1R1 (BASE_HDMA + 0x0168) // channel 1
+#define HDCR_XFER_SIZE1(n) ((n) << 16)
+#define HDCR_START1 (1 << 0)
+#define REG_HDMA_HPRGA0R0 (BASE_HDMA + 0x014C) // channel 0
+#define REG_HDMA_HPRGA0R1 (BASE_HDMA + 0x016C) // channel 1
+#define REG_HDMA_HPRGA1R0 (BASE_HDMA + 0x0150) // channel 0
+#define REG_HDMA_HPRGA1R1 (BASE_HDMA + 0x0170) // channel 1
+#define REG_HDMA_HCCR0 (BASE_HDMA + 0x0154) // channel 0
+#define REG_HDMA_HCCR1 (BASE_HDMA + 0x0174) // channel 1
+#define HDMA_HCURR_CNT0 0x0000FFFF
+#define HDMA_HCURR_CNT1 0xFFFF0000
+#define REG_HDMA_HDCPR0 (BASE_HDMA + 0x0158) // channel 0
+#define REG_HDMA_HDCPR1 (BASE_HDMA + 0x0178) // channel 1
+#define REG_GDMA_GISAR2 (BASE_HDMA + 0x608)
+#define HDMA_DONE_0x (1<<0)
+#define HDMA_DONE_1x (1<<1)
+#define REG_GDMA_GIMRK4 (BASE_HDMA + 0x630)
+
+
+#define UT_USIM_BASE_ADDR_USIM1 BASE_ADDR_USIM1
+#define UT_USIM_BASE_ADDR_USIM2 BASE_ADDR_USIM2
+
+usim_reg_desc_t hdma_reg[] =
+{
+ // 8 4 0 6 2 8 4 0 8 4 0 6 2 8 4 0
+ {REG_HDMA_HDCSR0, {"axxxxaaaxxxxxxxxaxxxxaaaxxxxxxxx"}, {"0xxxx010xxxxxxxx0xxxx010xxxxxxxx"}},
+ {REG_HDMA_HDSR, {"xxxxxxxxxxxxxxrrxxxxxxxxxxxxxxrr"}, {"xxxxxxxxxxxxxx00xxxxxxxxxxxxxx00"}},
+ {REG_HDMA_HDCPR, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrr"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00"}},
+
+ {REG_HDMA_HDCTRR0, {"aaxxxxxxxxxxxxxxaaaaxxxxaaaaxfxx"}, {"00xxxxxxxxxxxxxx0100xxxx0010x0xx"}},
+ {REG_HDMA_HDCTRR1, {"aaxxxxxxxxxxxxxxaaaaxxxxaaaaxfxx"}, {"00xxxxxxxxxxxxxx0100xxxx0010x0xx"}},
+ {REG_HDMA_HDC0R0, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
+ {REG_HDMA_HDC0R1, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
+ {REG_HDMA_HDC1R0, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
+ {REG_HDMA_HDC1R1, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
+
+ {REG_HDMA_HPRGA0R0, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HPRGA0R1, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HPRGA1R0, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HPRGA1R1, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HCCR0, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HCCR1, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HDCPR0, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
+ {REG_HDMA_HDCPR1, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
+
+ {REG_GDMA_GISAR2, {"xxccxxccxxxxxxccxxxxxxccxxxxxxcc"}, {"xx00xx00xxxxxx00xxxxxx00xxxxxx00"}},
+ {REG_GDMA_GIMRK4, {"xxaaxxaaxxxxxxaaxxxxxxaaxxxxxxaa"}, {"xx11xx11xxxxxx11xxxxxx11xxxxxx11"}}, //97 Change
+
+};
+
+// USIM IP
+usim_reg_desc_t usim_reg[] =
+{
+ // 8 4 0 6 2 8 4 0 8 4 0 6 2 8 4 0
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0000, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_CODA_VERSION
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0010, {"xxxxxxxxxxxxxxxxxxxxxxxxxxpaapaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx000000"}}, //REG_USIM_CTRL
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0014, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_CONF
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0018, {"xxxxxxxxxxxxxxxxxxxxxuxxxxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxx0xxxxxxxxx0"}}, //REG_USIM_CONFSTA
+ {UT_USIM_BASE_ADDR_USIM1 + 0x001C, {"xxxxxxxxxxxxxxxxxxaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxx00010111010000"}}, //REG_USIM_BRR
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0020, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_IRQEN
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0024, {"xxxxxxxxxxxxxxxxxxxxccccccccccuu"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_STS
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0030, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0011xxxx0011"}}, //REG_USIM_RETRY
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0034, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxx0000"}}, //REG_USIM_TIDE
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0040, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DATA: special, FIFO type
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0044, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxx00000"}}, //REG_USIM_COUNT
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0054, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_DTIME
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0058, {"xxxxxxxxxxaaaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxx0000000000001001100000"}}, //REG_USIM_WTIME
+ {UT_USIM_BASE_ADDR_USIM1 + 0x005C, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx1010"}}, //REG_USIM_GTIME
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0060, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_ETIME
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0064, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx0001"}}, //REG_USIM_EXT_TIME
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0068, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000010"}}, //REG_USIM_CGTIME
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0070, {"xxxxxxxxxxxxxxxxpxxxxxxaaaaaaaaa"}, {"xxxxxxxxxxxxxxxx0xxxxxx000000000"}}, //REG_USIM_COMDCTRL
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0074, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_COMDLEN
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0078, {"xxxxxxxxxxxxxxxxxxxxxxxuuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxx000000000"}}, //REG_USIM_LEFTLEN
+ {UT_USIM_BASE_ADDR_USIM1 + 0x007C, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH1
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0080, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH2
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0090, {"xxxxxxxxxxxxxxxxxxxxxxxuuxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxxxx00xxxxxx1"}}, //REG_USIM_ATRSTA
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0094, {"xxxxxxxxxxxxxxxxxxxxxxxxxuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxx0000001"}}, //REG_USIM_T0PTLSTA
+ {UT_USIM_BASE_ADDR_USIM1 + 0x0098, {"xxxxuuuuxxxuuuuuxxxuuuuuxxxuuuuu"}, {"xxxx0000xxx00000xxx00000xxx00000"}}, //REG_USIM_DBG
+ {UT_USIM_BASE_ADDR_USIM1 + 0x009C, {"xxxxxxxxxxxxxxxxxxxxuuuuffffffff"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxxxxxx"}}, //REG_USIM_DBGDATA: special, read will cause side effect
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00A0, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DMADATA: special, FIFO type
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00A8, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0"}}, //REG_USIM_RPTR_LOCK_EN
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00B0, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME1
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00B4, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME2
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00B8, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME3
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00BC, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME4
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00C0, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0"}}, //REG_USIM_SIMOE_MODE
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00D0, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG1
+ {UT_USIM_BASE_ADDR_USIM1 + 0x00D4, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG2
+
+};
+
+usim_reg_desc_t usim_reg2[] =
+{
+ // 8 4 0 6 2 8 4 0 8 4 0 6 2 8 4 0
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0000, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_CODA_VERSION
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0010, {"xxxxxxxxxxxxxxxxxxxxxxxxxxpaapaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx000000"}}, //REG_USIM_CTRL
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0014, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_CONF
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0018, {"xxxxxxxxxxxxxxxxxxxxxuxxxxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxx0xxxxxxxxx0"}}, //REG_USIM_CONFSTA
+ {UT_USIM_BASE_ADDR_USIM2 + 0x001C, {"xxxxxxxxxxxxxxxxxxaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxx00010111010000"}}, //REG_USIM_BRR
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0020, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_IRQEN
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0024, {"xxxxxxxxxxxxxxxxxxxxccccccccccuu"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_STS
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0030, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0011xxxx0011"}}, //REG_USIM_RETRY
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0034, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxx0000"}}, //REG_USIM_TIDE
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0040, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DATA: special, FIFO type
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0044, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxx00000"}}, //REG_USIM_COUNT
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0054, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_DTIME
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0058, {"xxxxxxxxxxaaaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxx0000000000001001100000"}}, //REG_USIM_WTIME
+ {UT_USIM_BASE_ADDR_USIM2 + 0x005C, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx1010"}}, //REG_USIM_GTIME
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0060, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_ETIME
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0064, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx0001"}}, //REG_USIM_EXT_TIME
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0068, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000010"}}, //REG_USIM_CGTIME
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0070, {"xxxxxxxxxxxxxxxxpxxxxxxaaaaaaaaa"}, {"xxxxxxxxxxxxxxxx0xxxxxx000000000"}}, //REG_USIM_COMDCTRL
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0074, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_COMDLEN
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0078, {"xxxxxxxxxxxxxxxxxxxxxxxuuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxx000000000"}}, //REG_USIM_LEFTLEN
+ {UT_USIM_BASE_ADDR_USIM2 + 0x007C, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH1
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0080, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH2
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0090, {"xxxxxxxxxxxxxxxxxxxxxxxuuxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxxxx00xxxxxx1"}}, //REG_USIM_ATRSTA
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0094, {"xxxxxxxxxxxxxxxxxxxxxxxxxuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxx0000001"}}, //REG_USIM_T0PTLSTA
+ {UT_USIM_BASE_ADDR_USIM2 + 0x0098, {"xxxxuuuuxxxuuuuuxxxuuuuuxxxuuuuu"}, {"xxxx0000xxx00000xxx00000xxx00000"}}, //REG_USIM_DBG
+ {UT_USIM_BASE_ADDR_USIM2 + 0x009C, {"xxxxxxxxxxxxxxxxxxxxuuuuffffffff"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxxxxxx"}}, //REG_USIM_DBGDATA: special, read will cause side effect
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00A0, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DMADATA: special, FIFO type
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00A8, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0"}}, //REG_USIM_RPTR_LOCK_EN
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00B0, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME1
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00B4, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME2
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00B8, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME3
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00BC, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME4
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00D0, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG1
+ {UT_USIM_BASE_ADDR_USIM2 + 0x00D4, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG2
+
+};
+#define GET_FIELD(val, bit_offset, bit_len) \
+ (((val) >> (bit_offset)) & (~(0xFFFFFFFF << (bit_len))))
+#define SET_FIELD(val, bit_offset, bit_len, field_val) \
+ ((val) = ((val) & ~((1 << ((bit_offset) + (bit_len))) - (1 << ((bit_offset))))) | ( ((field_val) << (bit_offset)) & ((1 << ((bit_offset) + (bit_len))) - (1 << ((bit_offset))))))
+
+
+kal_bool USIM_SLT_reg_read_write_test()
+{
+
+ kal_bool ut_usim_breset_status = KAL_TRUE;
+ kal_uint32 reg_index, reg_group_index, bit_index;
+
+ kal_uint32 reg_addr, expected_val, i;
+ kal_char *reset_val, *attr;
+ kal_uint32 reg_num;
+ kal_char bypass_items[] = { 0x40, 0x9C, 0xA0};
+
+ for (reg_group_index = 0; reg_group_index < REG_GROUP_NUM; reg_group_index++)
+ {
+ switch (reg_group_index)
+ {
+ case REG_GROUP_HDMA:
+ slt_dbg_print( " ---- %s ----\r\n", "HDMA");
+ reg_num = sizeof(hdma_reg) / sizeof(usim_reg_desc_t);
+ break;
+ case REG_GROUP_USIM:
+ slt_dbg_print( " ---- %s ----\r\n", "USIM0");
+ reg_num = sizeof(usim_reg) / sizeof(usim_reg_desc_t);
+ break;
+ case REG_GROUP_USIM2:
+ slt_dbg_print( " ---- %s ----\r\n", "USIM1");
+ reg_num = sizeof(usim_reg2) / sizeof(usim_reg_desc_t);
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ /*
+ * Check Default Values
+ */
+ for (reg_index = 0; reg_index < reg_num; reg_index++)
+ {
+ switch (reg_group_index)
+ {
+ case REG_GROUP_HDMA:
+ reg_addr = hdma_reg[reg_index].addr;
+ reset_val = hdma_reg[reg_index].reset_val;
+ break;
+ case REG_GROUP_USIM:
+ reg_addr = usim_reg[reg_index].addr;
+ reset_val = usim_reg[reg_index].reset_val;
+ break;
+ case REG_GROUP_USIM2:
+ reg_addr = usim_reg2[reg_index].addr;
+ reset_val = usim_reg2[reg_index].reset_val;
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ if (reg_group_index == REG_GROUP_USIM || reg_group_index == REG_GROUP_USIM2)
+ {
+ for (i = 0; i < (sizeof(bypass_items) / sizeof(kal_char)); i++)
+ if ((reg_addr & 0xFF) == bypass_items[i])
+ break;
+ if (i < (sizeof(bypass_items) / sizeof(kal_char)))
+ continue;
+ }
+
+ expected_val = DRV_Reg32(reg_addr);
+ //slt_dbg_print("Check default Value, addr:%x, expected value:%x\r\n",reg_addr,expected_val);
+
+ for (bit_index = 0; bit_index < 32; bit_index++)
+ {
+ kal_uint32 expected_bit_type = reset_val[bit_index];
+ kal_uint32 expected_bit_val = GET_FIELD(expected_val, 32 - 1 - bit_index, 1);
+
+ switch (expected_bit_type)
+ {
+ case '0':
+ if (expected_bit_val != 0)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is not '0'\r\n", 32 - 1 - bit_index);
+ slt_dbg_print("Reg Val: 0x%08X\r\n", expected_val);
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+ break;
+ case '1':
+ if (expected_bit_val != 1)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is not '1'\r\n", 32 - 1 - bit_index);
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+ break;
+ case 'x':
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ /*
+ * Check Types That Cause No Side Effects
+ */
+ for (reg_index = 0; reg_index < reg_num; reg_index++)
+ {
+ switch (reg_group_index)
+ {
+ case REG_GROUP_HDMA:
+ reg_addr = hdma_reg[reg_index].addr;
+ attr = hdma_reg[reg_index].attr;
+ break;
+ case REG_GROUP_USIM:
+ reg_addr = usim_reg[reg_index].addr;
+ attr = usim_reg[reg_index].attr;
+ break;
+ case REG_GROUP_USIM2:
+ reg_addr = usim_reg2[reg_index].addr;
+ attr = usim_reg2[reg_index].attr;
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ if (reg_group_index == REG_GROUP_USIM || reg_group_index == REG_GROUP_USIM2)
+ {
+ for (i = 0; i < (sizeof(bypass_items) / sizeof(kal_char)); i++)
+ if ((reg_addr & 0xFF) == bypass_items[i])
+ break;
+ if (i < (sizeof(bypass_items) / sizeof(kal_char)))
+ continue;
+ }
+ //slt_dbg_print("Check default Attr, addr:%x,0x98:%x_%x\r\n",reg_addr,DRV_Reg32(0xB0040098)>>16,DRV_Reg32(0xB0040098)&0xFFFF);
+ for (bit_index = 0; bit_index < 32; bit_index++)
+ {
+ kal_uint32 expected_bit_attr = attr[bit_index];
+ kal_uint32 expected_bit_val = GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1);
+
+ switch (expected_bit_attr)
+ {
+ /*
+ * Check if '0' & '1'' Write-able
+ */
+ case 'a':
+ // Set Bit to '0' and Check
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 0));
+
+ if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != 0)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is not '0' Write-able\r\n", 32 - 1 - bit_index);
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+
+ // Set Bit to '1' and Check
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 1));
+
+ if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != 1)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is not '1' Write-able\r\n", 32 - 1 - bit_index);
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+
+ // Set Bit to Default Value
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, expected_bit_val));
+ break;
+ case 'k':
+ case 'p':
+ case 'c':
+ // Set 1 and Check if Bit is 0
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 1));
+
+ if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != 0)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is Write-one-clear, but currently read to be 1\r\n", 32 - 1 - bit_index);
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+ break;
+ case 'r':
+ // Set Bit to Inverse of Default Value and Check if Bit Changed
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, ~expected_bit_val));
+
+ if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != expected_bit_val)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is write-able, but expected to be read-only\r\n", 32 - 1 - bit_index);
+
+ // Set Bit to Default Value For Future Tests
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, expected_bit_val));
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+ break;
+ /*
+ * Bypass Don't Care Bit
+ */
+ case 'u': /* May Update by Design */
+ case 'f': /* Special Type */
+ case 'x':
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ /*
+ * Check Types That Cause Side Effects
+ */
+ for (reg_index = 0; reg_index < reg_num; reg_index++)
+ {
+ switch (reg_group_index)
+ {
+ case REG_GROUP_HDMA:
+ reg_addr = hdma_reg[reg_index].addr;
+ attr = hdma_reg[reg_index].attr;
+ break;
+ case REG_GROUP_USIM:
+ reg_addr = usim_reg[reg_index].addr;
+ attr = usim_reg[reg_index].attr;
+ break;
+ case REG_GROUP_USIM2:
+ reg_addr = usim_reg2[reg_index].addr;
+ attr = usim_reg2[reg_index].attr;
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ if (reg_group_index == REG_GROUP_USIM || reg_group_index == REG_GROUP_USIM2)
+ {
+ for (i = 0; i < (sizeof(bypass_items) / sizeof(kal_char)); i++)
+ if ((reg_addr & 0xFF) == bypass_items[i])
+ break;
+ if (i < (sizeof(bypass_items) / sizeof(kal_char)))
+ continue;
+ }
+
+ for (bit_index = 0; bit_index < 32; bit_index++)
+ {
+ kal_uint32 expected_bit_attr = attr[bit_index];
+
+ switch (expected_bit_attr)
+ {
+ case 's':
+ // Set Bit to 1 and Check if Bit Changed
+ DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 1));
+
+ if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) == 1)
+ {
+ slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
+ slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
+ slt_dbg_print("Bit[%d] is write-able, but expected to be read-only\r\n", 32 - 1 - bit_index);
+
+ ut_usim_breset_status = KAL_FALSE;
+ }
+ break;
+ /*
+ * Bypass All Others
+ */
+ default:
+ break;
+ }
+ }
+ }
+
+ }
+ //Reset Interface
+ for (i=0;i<2;i++)
+ {
+ if (i==0)
+ reg_addr = UT_USIM_BASE_ADDR_USIM1;
+ else
+ reg_addr = UT_USIM_BASE_ADDR_USIM2;
+
+ DRV_WriteReg32(reg_addr + SIM_CTRL_MTK,SIM_CTRL_SIMON|SIM_CTRL_IFCLR);
+ while ((DRV_Reg32(reg_addr +SIM_ATRSTA_MTK) & (SIM_ATRSTA_IR | SIM_ATRSTA_AL)) == 0);
+ while (DRV_Reg32(reg_addr+SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON);
+ DRV_WriteReg32(reg_addr + SIM_CTRL_MTK,0x0); //SIM
+ }
+ return ut_usim_breset_status;
+}
+#endif