[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/devdrv/usim/inc/sim_al.h b/mcu/driver/devdrv/usim/inc/sim_al.h
new file mode 100644
index 0000000..c7c6f06
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_al.h
@@ -0,0 +1,209 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_al.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is used for including files for AL_SIM
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef SIM_AL_H
+#define SIM_AL_H
+
+//#define TEST /* test option for win32 simulation */
+/*Besnon 20040407 add for Jensen's request*/
+#define RESET_18V 0 /* Driver reset result = 1.8V */
+#define RESET_30V 1 /* Driver reset result = 3V */
+/*End Benson 20040407*/
+
+#define SIM_NO_ERROR 0 /* return value for SIM no error found */
+#define SIM_NO_INSERT 1 /* return value for no SIM insert */
+#define SIM_CARD_ERROR 3 /* return value for SIM error found */
+
+#define CLOCK_STOP_AT_HIGH 0x00 /* config SIM colck stop at high */
+#define CLOCK_STOP_AT_LOW 0x01 /* config SIM clock stop at low */
+#define CLOCK_STOP_NOT_ALLOW 0x02 /* config SIM clock stop not allowed */
+
+/* Define SIM command instruction ID */
+#define GSM_CLS 0xA0
+#define CMD_SELECT 0xA4
+#define CMD_GETRES 0xC0
+#define CMD_STATUS 0xF2
+#define CMD_READB 0xB0
+#define CMD_UPDATEB 0xD6
+#define CMD_READR 0xB2
+#define CMD_UPDATER 0xDC
+#define CMD_INCREASE 0x32
+#define CMD_VERIFYCHV 0x20
+#define CMD_CHANGECHV 0x24
+#define CMD_DISABLECHV 0x26
+#define CMD_ENABLECHV 0x28
+#define CMD_UNBLOCKCHV 0x2C
+#define CMD_INVALIDATE 0x04
+#define CMD_REHABILITATE 0x44
+#define CMD_RUNGSMALGO 0x88
+#define CMD_TERMINALPRO 0x10
+#define CMD_TERMINALRES 0x14
+#define CMD_ENVELOPE 0xC2
+#define CMD_FETCH 0x12
+
+/* define SIM file ID */
+#define SIM_DF_GSM 0x7F20
+#define SIM_DF_1800 0x7F21
+
+typedef enum
+{
+ ME_UNKNOW = 0,
+ ME_18V_30V,
+ ME_30V_ONLY,
+ ME_18V_ONLY
+} sim_env;
+
+typedef enum
+{
+ sim_card_normal_speed = 0,
+ sim_card_enhance_speed_64,
+ sim_card_enhance_speed_32,
+ sim_card_enhance_speed_16,
+ sim_card_enhance_speed_8
+} sim_card_speed_type;
+
+/* define ATR data Structure */
+typedef struct
+{
+ kal_uint8 info [40];
+} AtrStruct;
+
+#if !defined(DRV_MULTIPLE_SIM) && !defined(__SIM_DRV_MULTI_DRV_ARCH__)
+ /*this definition is only used when build old single SIM driver, the latest definitions are moved to sim_drv_sw_api.h*/
+ extern kal_uint8 L1sim_Reset(kal_uint8 resetVolt, kal_uint8 *resultVolt, AtrStruct *Info);
+ extern void L1sim_Configure(kal_uint8 clockMode);
+ extern kal_uint16 L1sim_Cmd(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error);
+ extern void L1sim_PowerOff(void);
+ extern void L1sim_Init(void);
+ extern sim_env SIM_GetCurrentEnv(void);
+#endif
+
+#endif /*SIM_AL_H*/
+
+
diff --git a/mcu/driver/devdrv/usim/inc/sim_ctrl_al.h b/mcu/driver/devdrv/usim/inc/sim_ctrl_al.h
new file mode 100644
index 0000000..ef5cf79
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_ctrl_al.h
@@ -0,0 +1,139 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_ctrl_al.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for common header files for different SIM controller drivers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if defined( DRV_MULTIPLE_SIM) && !defined(__SIM_DRV_MULTI_DRV_ARCH__)
+
+/*RHR*/
+#include "sim_sw_comm.h"
+#include "usim_MT6302.h"
+/*RHR*/
+
+#define SIM_MAX_INTERFACE 2 //maybe this should be defined in makefile
+typedef struct
+{
+ usim_status_enum(*reset)(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, kal_uint32 simInterface);
+ sim_status(*command)(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, kal_uint32 simInterface);
+ void (*powerOff)(kal_uint32 simInterface);
+ void (*getCardInfo)(sim_info_struct *info, kal_uint32 simInterface);
+ void (*enableEnhancedSpeed)(kal_bool enable, kal_uint32 simInterface);
+ void (*selectPreferPhyLayer)(sim_protocol_phy_enum T, kal_uint32 simInterface);
+ kal_bool(*setClockStopMode)(sim_clock_stop_enum mode, kal_uint32 simInterface);
+ void (*EOC)(kal_uint32 simInterface); /*use this to hook necessary action before return to SIM task, this is called by adaption layer, not SIM task*/
+ void (*addMessage)(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+} sim_ctrlDriver;
+
+#endif//DRV_MULTIPLE_SIM
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_HW_def_MTK.h b/mcu/driver/devdrv/usim/inc/sim_drv_HW_def_MTK.h
new file mode 100644
index 0000000..1c1abaf
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_HW_def_MTK.h
@@ -0,0 +1,658 @@
+#ifndef __SIM_DRV_HW_DEF_MTK_H__
+#define __SIM_DRV_HW_DEF_MTK_H__
+
+
+/* SIM_ADDDMA & NoT0CTRL can't active concurrently */
+#define SIM_ADDDMA
+
+/* SIM Format */
+#define SIM_direct 0
+#define SIM_indirect 1
+
+/* SIM Power */
+#define SIM_30V RESET_30V
+#define SIM_18V RESET_18V
+
+#define CMD_RECBUFSIZE 13
+/*DMA setting, such usb*/
+/* Size = 8bit, sinc en, dinc disable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimTxNormal 0x0074
+/* Size = 8bit, sinc disable, dinc enable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimRxNormal 0x0078
+
+/* SIM State */
+#define SIM_WAIT_FOR_ATR 0 /* reset SIM card and wait ATR */
+#define SIM_PROCESS_ATR 1 /* receiving ATR data */
+#define SIM_PROCESS_PTS 2 /* receiving PTS response data */
+#define SIM_PROCESSCMD 3
+#define SIM_SERIOUSERR 4 /* serous error due to txerr*/
+#define SIM_PWROFF 5
+#define SIM_WaitRejectDone 6
+
+
+/* SIM Miner State */
+#ifdef NoT0CTRL
+ #define SIMD_CmdIdle 0
+ #define SIM_WaitProcByte 1
+ #define SIM_AckDataState 2
+ #define SIM_NAckDataState 3
+ #define SIM_WaitSWByte 4
+#endif /*NoT0CTRL*/
+/*just for clock stop mode*/
+#define SIM_ProcessClk 5
+#define SIM_StopClk 6
+#define SIM_WaitCmdEnd 7
+
+
+/* Event */
+#define ATR_END 0x0100
+#define PTS_END 0x0008
+//#ifdef DCL_SIM_INTERFACE
+#define SIM_EVT_CMD_END 0x0004
+//#else
+//#define CMD_END 0x0004
+//#endif
+#define RST_READY 0x0002
+#define CLK_PROC 0x0020
+#define ACTIVATE_DONE 0x0040
+#define DEACTIVATE_DONE 0x0080
+#define SWRST_INT_END 0x0100
+
+
+/*#define INIRET 0x0001*/
+
+/*ATR data define*/
+#define TAMask 0x0010
+#define TBMask 0x0020
+#define TCMask 0x0040
+#define TDMask 0x0080
+
+/* Result */
+#define SIM_SUCCESS SIM_NO_ERROR
+#define SIM_NOREADY SIM_NO_INSERT
+#define SIM_CARDERR SIM_CARD_ERROR
+#define SIM_INITXERR 5
+#define SIM_INIPTSERR 6
+#define SIM_CMDTXERR 7 /* parity error */
+#define SIM_CMDRECERR 8
+#define SIM_CMDTOUT 9
+#define SIM_CLKPROC 10
+#define SIM_NULLTIMEOUT 11
+#define SIM_TS_INVALID 12
+#define SIM_NO_ATR 13
+#define SIM_RX_INVALID 14
+#define SIM_SWRST 15
+#define SIM_CLKSTOP 16
+#define SIM_GPT_TIMEOUT 17
+#define SIM_PTS_RX_INVALID 18
+#define SIM_OVERRUN 19
+
+#define SW1_GET_RESP_SIM 0x9f
+#define SW1_GET_RESP_USIM 0x61
+#define SW1_RESEND_USIM 0x6c
+#define LEN_INDEX 4 // index to the P3 of command header
+#define LEN_OF_CMD 5
+#define GET_RESP_CLA_SIM 0xa0
+#define GET_RESP_CLA_USIM 0x00
+#define SW1_WARN1 0x62
+#define SW1_WARN2 0x63
+//#ifdef DCL_SIM_INTERFACE
+#define SIM_SW_STATUS_OK 0x9000
+#define SIM_SW_STATUS_FAIL 0x00
+//#else
+//#define STATUS_OK 0x9000
+//#define STATUS_FAIL 0x00
+//#endif
+
+#define Speed372 0
+#define Speed64 1
+#define Speed32 2
+#define Speed16 3
+#define Speed8 4
+
+typedef kal_uint16 sim_status;
+
+#define SW1_GET_RESP_SIM 0x9f
+#define SW1_SIM_WARN1 0x9e
+#define SW1_GET_RESP_USIM 0x61
+#define SW1_RESEND_USIM 0x6c
+#define LEN_INDEX 4 // index to the P3 of command header
+#define LEN_OF_CMD 5
+#define GET_RESP_CLA_SIM 0xa0
+#define GET_RESP_CLA_USIM 0x00
+#define SW1_WARN1 0x62
+#define SW1_WARN2 0x63
+//#ifdef DCL_SIM_INTERFACE
+#define SIM_SW_STATUS_OK 0x9000
+#define SIM_SW_STATUS_FAIL 0x00
+
+#define MAX_SIM_ERROR_LINE 4
+
+
+
+typedef enum
+{
+ SIM_PROTOCOL,
+ USIM_PROTOCOL
+} sim_protocol_app_enum;
+
+typedef enum
+{
+ T0_PROTOCOL,
+ T1_PROTOCOL,
+ UNKNOWN_PROTOCOL
+} sim_protocol_phy_enum;
+
+typedef enum
+{
+ UNKNOWN_POWER_CLASS = 0,
+ CLASS_A_50V = 1,
+ CLASS_B_30V = 2,
+ CLASS_AB = 3,
+ CLASS_C_18V = 4,
+ ClASS_BC = 6,
+ CLASS_ABC = 7,
+ CLASS_ALLSUPPORT = 0xff
+} sim_power_enum;
+
+typedef enum
+{
+ CLOCK_STOP_NOT_SUPPORT = 0x0,
+ CLOCK_STOP_LOW = 0x40,
+ CLOCK_STOP_HIGH = 0x80,
+ CLOCK_STOP_ANY = 0xc0,
+ CLOCK_STOP_MSK = 0xc0,
+ CLOCK_STOP_UNKONW = 0x0f
+} sim_clock_stop_enum;
+
+typedef enum
+{
+ SPEED_372,
+ SPEED_64,
+ SPEED_32,
+ SPEED_16,
+ SPEED_8,
+ SPEED_RFU,
+ SPEED_MAX
+} sim_speed_enum;
+
+typedef enum
+{
+ SIM_DIRECT,
+ SIM_INVERSE
+} sim_dir_enum;
+
+typedef enum
+{
+ usim_case_1 = 1,
+ usim_case_2,
+ usim_case_3,
+ usim_case_4,
+ usim_case_2E,
+ usim_case_3E,
+ usim_case_4E
+} usim_cmd_case_enum;
+
+typedef enum
+{
+ USIM_DIRECT,
+ USIM_INVERSE
+} usim_dir_enum;
+
+typedef enum
+{
+ PPSS = 0, // initial character 0xFF
+ PPS0 = 1, // format character 0x1x
+ PPS1 = 2, // indicate the baudrate F, D
+ PCK = 3, // exclusive-or PPSS to PCK should be null
+ PPS_LEN = 4
+} usim_pts_enum;
+
+#define usim_protocol_enum sim_protocol_phy_enum
+#define usim_speed_enum sim_speed_enum
+#define usim_clock_stop_enum sim_clock_stop_enum
+#define usim_power_enum sim_power_enum
+
+typedef enum
+{
+ ERR_INVALID_BLOCK,
+ ERR_TIMEOUT
+} usim_err_enum;
+
+typedef enum
+{
+ USIM_RESET_NEGOTIABLE, // type 1
+ USIM_RESET_SPECIFIC // type 2
+} usim_reset_type_enum;
+
+typedef enum
+{
+ IDLE_STATE,
+ ACTIVATION_STATE,
+ ATR_STATE,
+ PTS_STATE,
+ MAIN_CMD_READY_STATE,
+ CMD_TX_STATE,
+ //CMD_RX_HEADER_STATE,
+ CMD_RX_BLOCK_REC_STATE,
+ //CMD_RX_S_BLOCK_STATE,
+ CMD_RX_STATE,
+ CLK_STOPPING_STATE,
+ CLK_STOPPED_STATE,
+ DEACTIVATION_STATE
+} usim_main_state_enum;
+
+typedef enum
+{
+ EVENT_TX = 0x1,
+ EVENT_RX = 0x2,
+ EVENT_OV = 0x4,
+ EVENT_TOUT = 0x8,
+ EVENT_TXERR = 0x10,
+ EVENT_NATR = 0x20,
+ EVENT_OFF = 0x40,
+ EVENT_T0END = 0x80,
+ EVENT_RXERR = 0x100,
+ EVENT_T1END = 0x200,
+ EVENT_EDCERR = 0x400
+} usim_event_type_enum;
+
+typedef enum
+{
+ USIM_NO_ERROR = 0,
+
+ // expected status
+ USIM_WAITING_EVENT = 1, // initial wait event status
+ USIM_BLOCK_REC = 2, // successfully received a complete block
+ USIM_POWER_OFF = 3, // successfully powered off
+ USIM_ATR_REC = 4, // successfully reveived all ATR
+ USIM_S_BLOCK_REC = 5, // successfully reveived S RESP
+
+ // error status
+ USIM_NO_INSERT = -1,
+ USIM_VOLT_NOT_SUPPORT = -2,
+ USIM_NO_ATR = -3,
+ USIM_TS_INVALID = -4,
+ USIM_ATR_ERR = -5,
+ USIM_INVALID_ATR = -6,
+ USIM_PTS_FAIL = -7,
+ USIM_RX_INVALID = -8, // EDC error or parity error
+ USIM_BWT_TIMEOUT = -9,
+ USIM_DATA_ABORT = -10,
+ USIM_DEACTIVATED = -11,
+ USIM_S_BLOCK_FAIL = -12,
+ USIM_INVALID_WRST = -13,
+ USIM_GPT_TIMEOUT = -14,
+ USIM_PTS_TIMEOUT = -15,
+ USIM_PTS_RX_INVALID = -16
+} usim_status_enum;
+
+typedef enum
+{
+ USIM_CMD_READY,
+ I_BLOCK_RX,
+ I_BLOCK_TX,
+ I_BLOCK_M0_RX,
+ I_BLOCK_M0_TX,
+ I_BLOCK_M1_RX,
+ I_BLOCK_M1_TX,
+ R_BLOCK_RX,
+ R_BLOCK_TX,
+ S_BlOCK_REQ_RX,
+ S_BlOCK_REQ_TX,
+ S_BlOCK_RESP_RX,
+ S_BlOCK_RESP_TX
+} usim_cmd_state_enum;
+
+typedef enum
+{
+ T1_NAD_INDEX = 0,
+ T1_PCB_INDEX = 1,
+ T1_LEN_INDEX = 2,
+ T1_INF_INDEX = 3,
+ T1_EDC_INDEX = 4
+} usim_t1_header_index_enum;
+
+typedef enum
+{
+ SIM_NORMAL = 0,
+ SIM_SLOW_CLOCK,
+ SIM_FORCE_3V,
+ SIM_CLOCK_FETCH__TERMINAL_RESPONSE,
+ SIM_3_25MHZ_ONLY
+} usim_process_hitorical_enum;
+
+typedef enum
+{
+ SIM_ASSERT_REASON_WRONG_OWNERTASK = 0x00,
+} usim_assert_reason;
+
+typedef enum
+{
+ SIM_ASSERT_OWNER_SIMTASK = 0x00,
+} usim_assert_owner;
+
+#if defined(SIM_DRV_IC_USB)
+typedef enum
+{
+ SIM_ICUSB_INIT,
+ SIM_ICUSB_SETVOLT,
+ SIM_ICUSB_ENABLESESSION,
+ SIM_ICUSB_POWERON,
+ SIM_ICUSB_CMD,
+ SIM_ICUSB_POWEROFF,
+ SIM_ICUSB_DISABLESESSION,
+ SIM_ICUSB_DEINIT,
+ SIM_ICUSB_ERRORHANDLING,
+} usim_icusb_state_enum;
+
+typedef enum
+{
+ SIM_ICUSB_ACK_OK = 0x00,
+ SIM_ICUSB_ACK_PREFER_3V = 0x10,
+ SIM_ICUSB_ACK_CMD_EN_SESSION_ERROR = 0xEA,
+ SIM_ICUSB_ACK_SET_VOLTAGE_ERROR = 0xEB,
+ SIM_ICUSB_ACK_CMD_TYPE_ERROR = 0xEC,
+ SIM_ICUSB_ACK_NEED_RX_TO_ACK = 0xEE,
+ SIM_ICUSB_ACK_CMD_ERROR = 0xFD,
+ SIM_ICUSB_ACK_TIMEOUT = 0xFE,
+ SIM_ICUSB_ACK_NO_CARD = 0xFF,
+
+ // error status
+ SIM_ICUSB_CCCI_CMD_EN_SESSION_ERROR = 0x1000,
+ SIM_ICUSB_CCCI_SET_VOLTAGE_ERROR,
+ SIM_ICUSB_CCCI_CMD_TYPE_ERROR,
+ SIM_ICUSB_CCCI_NEED_RX_TO_ACK,
+ SIM_ICUSB_CCCI_CMD_ERROR,
+ SIM_ICUSB_CCCI_TIMEOUT,
+ SIM_ICUSB_CCCI_NO_CARD,
+} usim_icusb_ackStatus;
+
+#define SIM_ICUSB_CONTROL_MESSAGE_LEN 0x9
+#define SIM_ICUSB_MESSAGE_HEADER_LEN 0x6
+#define TB15_ICUSB_MASK 0xC0
+#define SIM_ICUSB_CONTROL_MESSAGE_TYPE 0x80
+#define SIM_ICUSB_DATA_MESSAGE_TYPE 0x80
+
+#endif
+
+
+// definitions
+#define SELECT_PW_RETRY 3
+#define SELECT_DIR_RETRY 2
+#define ATR_RETRY 3
+#define INVALID_RETRY 3
+#define RESYNC_RETRY 3
+#define IFS_RETRY 2
+#define USIM_IFSD_MAX 0xFE
+
+#define FI_DEFAULT 372
+#define DI_DEFAULT 1
+#define INIT_WWT_T0 (9600+400) // etu (initial work waiting time) +400 to cover some slow card
+
+#define TOUT_OFFSET 0x04 // apply a offset to all timeout settings (4*16 = 64 etu), the unit of mt6290 is 16
+#define BGT_T1 22 // etu (block guard time)
+#define NAD 0 // node address byte
+
+#define SIM_DEFAULT_TOUT_VALUE 0x260
+//#define SIM_DEFAULT_TOUT_VALUE 0x983
+#define SIM_CMD_TOUT_VALUE 0x1400 //mtk04122: not used....
+
+// coding of PCB for I-block (0xxxxxxx)
+#define PCB_I_BIT8 0x80 // I-block must be 0, others(R,S) are 1
+#define PCB_I_SEQ 0x40 // sequence number
+#define PCB_I_M 0x20 // chaining more data bit(M)
+#define PCB_I_RFU 0x1F // RFU should be zero
+
+// coding of PCB for R-block (100xxxxx)
+#define PCB_R_N1 0x90
+#define PCB_R_N0 0x80
+#define PCB_R_BIT7 0x40 // R: 0, S:1, use to distinguish R-block with S-block
+#define PCB_R_SEQ 0x10 // sequence number
+#define PCB_R_STATUS 0x0f // 0: error free, 1:EDC or parity error, 2: other errors
+#define PCB_R_STATUS_EDC_ERR 0x1
+#define PCB_R_STATUS_OTHER_ERR 0x2
+#define PCB_R_STATUS_OK 0x0
+#define PCB_R_DEFAULT 0xe0
+
+// coding of PCB for S-block (11xxxxxx)
+#define PCB_S_DEFAULT 0xc0
+#define PCB_S_RESP 0x20 // 1: a response, 0: a request
+#define PCB_S_ID 0x1f
+
+
+#define LEN_MIN_T1 0
+#define LEN_MAX_T1 254
+#define USIM_IFSC_DEFAULT 32
+#define USIM_IFSD_DEFAULT 32
+#define USIM_CWT_DEFAULT 8203 // (11 + 1>>13) etu
+#define USIM_BWT_DEFAULT 15360 // (1<<4)*960
+#define USIM_POW_CLASS_MSK 0x3f // TAi bit 1~6
+#define USIM_PTS_PS1_MSK 0x10
+#define USIM_PTS_PS0_T1 0x1 // select T1 protocol
+#define USIM_NAD_DEFAULT 0x0
+
+#define USIM_EVENT 0x1
+
+#define ATR_TA1_372_5 0x11
+#define ATR_TA1_372_4 0x01
+#define ATR_TA1_64 0x94
+#define ATR_TA1_32 0x95
+#define ATR_TA1_16 0x96 //speed 16
+#define ATR_TA1_8 0x97 //speed 8
+
+
+#define USIM_RETRY 3
+#define INDEX_COUNT 4 // the count of the wline and sline
+#define MAX_BWI 9
+#define MAX_CWI 16
+#define SIM_TOTAL_FIFO_LEN 16 // excep 6208
+#define HIST_FIRST_USIM 0x80 // the first of the historical character of USIM
+#define HIST_SEC_USIM 0x31 // the second of the historical character of USIM
+#define HIST_FOUR_USIM 0x73 // the fourth of the historical character of USIM
+#define USIM_DMA_MAX_SIZE 260
+#define USIM_GPT_TIMEOUT_PERIOD 500 // x 10ms
+
+typedef enum
+{
+ RESYNC_REQ = PCB_S_DEFAULT,
+ IFS_REQ = (PCB_S_DEFAULT | 1),
+ ABORT_REQ = (PCB_S_DEFAULT | 2),
+ WTX_REQ = (PCB_S_DEFAULT | 3),
+ RESYNC_RESP = RESYNC_REQ | PCB_S_RESP,
+ IFS_RESP = IFS_REQ | PCB_S_RESP,
+ ABORT_RESP = ABORT_REQ | PCB_S_RESP,
+ WTX_RESP = WTX_REQ | PCB_S_RESP
+} usim_s_block_id_enum;
+
+typedef enum
+{
+ SIM_DRIVER_ACT = 0x00000001,
+ SIM_DRIVER_DEACT = 0x00000002,
+ SIM_PDNDIS = 0x00000003,
+ SIM_PDNEN = 0x00000004,
+ SIM_INT_SIM = 0x00000005,
+ SIM_INT_USIM = 0x00000006,
+ SIM_DRIVER_ACT_SIMD = 0x00000007,
+ SIM_DRIVER_DEACT_SIMD = 0x00000008,
+ SIM_CMD_TX_LOG = 0x00010001,
+ SIM_CMD_INS_LOG = 0x00010002,
+ SIM_CMD_TXDELAY = 0x00010003,
+ SIM_INIT_USIM = 0x00020001,
+ SIM_DEACTIVATE_1 = 0x00030001,
+ SIM_DEACTIVATE_2 = 0x00030002,
+ SIM_ACTION_RESET = 0x000F0001,
+ SIM_ACTION_POWOFF = 0x000F0002,
+ SIM_ACTION_COMMAND = 0x000F0003,
+ SIM_ACTION_EOC = 0x000F0004
+} sim_msgTag;
+
+
+typedef enum
+{
+ /*following is error*/
+ SIM_PRINT_DUMP_ERROR_LINE,
+ SIM_PRINT_RESET_NOATR_FAIL,
+ SIM_PRINT_RESET_FAIL_WITH_TS_HSK_ENABLE,
+ SIM_PRINT_RESET_FAIL_RESULT,
+ SIM_PRINT_SIM_CMD_FAIL_STATUS,
+ SIM_PRINT_CMD_FAIL_RESULT_STATUS,
+ SIM_PRINT_RECEIVE_ERR_1,
+ SIM_PRINT_RECEIVE_ERR_2,
+ SIM_PRINT_TCK_CHECKSUM_ERR,
+ SIM_PRINT_HISTORICAL_BYTE_ERR,
+ SIM_PRINT_L1USIM_RESET_FAIL,
+
+ /*following is information*/
+ SIM_PRINT_INFO_BASE = 1000,
+ SIM_PRINT_RESET_OK_POWER_SPEED,
+ SIM_PRINT_NULL_TIME_OUT,
+ SIM_PRINT_NULL_BYTE,
+ SIM_PRINT_NON_NULL_BYTE,
+ SIM_PRINT_9000_ON_SELECT,
+ SIM_PRINT_6100_FROM_CARD,
+ SIM_PRINT_CHECK_TCK,
+ SIM_PRINT_TCK_NOT_PRESENT,
+ SIM_PRINT_TCK_CHECKSUM_OK,
+ SIM_PRINT_IR_CARD,
+ SIM_PRINT_INDIRECT_CARD,
+ SIM_PRINT_L1USIM_RST_OK,
+
+ SIM_PRINT_L1SIM_CMD_TRC1 = 1101,
+ SIM_PRINT_L1SIM_CMD_TRC2,
+ SIM_PRINT_L1SIM_CMD_TRC3,
+ SIM_PRINT_L1SIM_CMD_TRC4,
+ SIM_PRINT_L1SIM_CMD_TRC5,
+ SIM_PRINT_L1SIM_CMD_TRC6,
+ SIM_PRINT_L1SIM_CMD_TRC7,
+ SIM_PRINT_L1SIM_CMD_TRC8,
+ SIM_PRINT_L1SIM_CMD_TRC9,
+
+ SIM_PRINT_L1SIM_CMD_TRC10 = 1110,
+ SIM_PRINT_L1SIM_CMD_TRC11,
+ SIM_PRINT_L1SIM_CMD_TRC12,
+ SIM_PRINT_L1SIM_CMD_TRC13,
+ SIM_PRINT_L1SIM_CMD_TRC14,
+ SIM_PRINT_L1SIM_CMD_TRC15,
+ SIM_PRINT_L1SIM_CMD_TRC16,
+ SIM_PRINT_L1SIM_CMD_TRC17,
+ SIM_PRINT_L1SIM_CMD_TRC18,
+ SIM_PRINT_L1SIM_CMD_TRC19,
+
+ SIM_PRINT_L1SIM_CMD_TRC20 = 1120,
+ SIM_PRINT_L1SIM_CMD_TRC21,
+ SIM_PRINT_L1SIM_CMD_TRC22,
+ SIM_PRINT_L1SIM_CMD_TRC23,
+ SIM_PRINT_L1SIM_CMD_TRC24,
+ SIM_PRINT_L1SIM_CMD_TRC25,
+ SIM_PRINT_L1SIM_CMD_TRC26,
+ SIM_PRINT_L1SIM_CMD_TRC27,
+ SIM_PRINT_L1SIM_CMD_TRC28,
+ SIM_PRINT_L1SIM_CMD_TRC29,
+
+ SIM_PRINT_L1SIM_CMD_TRC30 = 1130,
+ SIM_PRINT_L1SIM_CMD_TRC31,
+ SIM_PRINT_L1SIM_CMD_TRC32,
+ SIM_PRINT_L1SIM_CMD_TRC33,
+ SIM_PRINT_L1SIM_CMD_TRC34,
+ SIM_PRINT_L1SIM_CMD_TRC35,
+ SIM_PRINT_L1SIM_CMD_TRC36,
+ SIM_PRINT_L1SIM_CMD_TRC37,
+ SIM_PRINT_L1SIM_CMD_TRC38,
+ SIM_PRINT_L1SIM_CMD_TRC39,
+
+ SIM_PRINT_L1SIM_CMD_TRC40 = 1140,
+ SIM_PRINT_L1SIM_CMD_TRC41,
+ SIM_PRINT_L1SIM_CMD_TRC42,
+ SIM_PRINT_L1SIM_CMD_TRC43,
+ SIM_PRINT_L1SIM_CMD_TRC44,
+ SIM_PRINT_L1SIM_CMD_TRC45,
+ SIM_PRINT_L1SIM_CMD_TRC46,
+ SIM_PRINT_L1SIM_CMD_TRC47,
+ SIM_PRINT_L1SIM_CMD_TRC48,
+ SIM_PRINT_L1SIM_CMD_TRC49,
+
+ SIM_PRINT_L1SIM_CMD_TRC50 = 1150,
+ SIM_PRINT_L1SIM_CMD_TRC51,
+ SIM_PRINT_L1SIM_CMD_TRC52,
+ SIM_PRINT_L1SIM_CMD_TRC53,
+ SIM_PRINT_L1SIM_CMD_TRC54,
+ SIM_PRINT_L1SIM_CMD_TRC55,
+ SIM_PRINT_L1SIM_CMD_TRC56,
+ SIM_PRINT_L1SIM_CMD_TRC57,
+ SIM_PRINT_L1SIM_CMD_TRC58,
+ SIM_PRINT_L1SIM_CMD_TRC59,
+
+ SIM_PRINT_L1SIM_CMD_TRC60 = 1160,
+ SIM_PRINT_L1SIM_CMD_TRC61,
+ SIM_PRINT_L1SIM_CMD_TRC62,
+ SIM_PRINT_L1SIM_CMD_TRC63,
+ SIM_PRINT_L1SIM_CMD_TRC64,
+ SIM_PRINT_L1SIM_CMD_TRC65, //last
+ SIM_PRINT_L1SIM_CMD_TRC66,
+ SIM_PRINT_L1SIM_CMD_TRC67,
+ SIM_PRINT_L1SIM_CMD_TRC68,
+ SIM_PRINT_L1SIM_CMD_TRC69,
+ SIM_PRINT_L1SIM_CMD_TRC70,
+ SIM_PRINT_L1SIM_CMD_TRC71,
+ SIM_PRINT_L1SIM_CMD_TRC72,
+ SIM_PRINT_L1SIM_CMD_TRC73,
+ SIM_PRINT_L1SIM_CMD_TRC74,
+ SIM_PRINT_L1SIM_CMD_TRC75,
+ SIM_PRINT_L1SIM_CMD_TRC76,
+ SIM_PRINT_L1SIM_CMD_TRC77,
+ SIM_PRINT_L1SIM_CMD_TRC78,
+ SIM_PRINT_L1SIM_CMD_TRC79,
+ SIM_PRINT_L1SIM_CMD_TRC80,
+ SIM_PRINT_L1SIM_CMD_TRC81,
+ SIM_PRINT_L1SIM_CMD_TRC82,
+ SIM_PRINT_L1SIM_CMD_TRC83,
+ SIM_PRINT_L1SIM_CMD_TRC84,
+ SIM_PRINT_L1SIM_CMD_TRC85,
+ SIM_PRINT_L1SIM_CMD_TRC86,
+ SIM_PRINT_L1SIM_CMD_TRC87,
+ SIM_PRINT_L1SIM_CMD_TRC88,
+ SIM_PRINT_L1SIM_CMD_TRC89,
+ SIM_PRINT_L1SIM_CMD_TRC90,
+ SIM_PRINT_L1SIM_CMD_TRC91,
+ SIM_PRINT_L1SIM_CMD_TRC92,
+ SIM_PRINT_L1SIM_CMD_TRC93,
+ SIM_PRINT_L1SIM_CMD_TRC94,
+ SIM_PRINT_L1SIM_CMD_TRC95,
+ SIM_PRINT_L1SIM_CMD_TRC96,
+ SIM_PRINT_L1SIM_CMD_TRC97,
+ SIM_PRINT_L1SIM_CMD_TRC98,
+ SIM_PRINT_L1SIM_CMD_TRC99,
+ SIM_PRINT_L1SIM_CMD_TRC100,
+ SIM_PRINT_L1SIM_CMD_TRC101,
+ SIM_PRINT_L1SIM_CMD_TRC102,
+ SIM_PRINT_L1SIM_CMD_TRC103,
+ SIM_PRINT_L1SIM_CMD_TRC104,
+ SIM_PRINT_L1SIM_CMD_TRC105,
+ SIM_PRINT_L1SIM_CMD_TRC106,
+ SIM_PRINT_L1SIM_CMD_TRC107,
+ SIM_PRINT_L1SIM_CMD_TRC108,
+ SIM_PRINT_L1SIM_CMD_TRC109,
+ SIM_PRINT_L1SIM_CMD_TRC110,
+ SIM_PRINT_L1SIM_CMD_TRC111,
+ SIM_PRINT_L1SIM_CMD_TRC112,
+ SIM_PRINT_L1SIM_CMD_TRC113,
+ SIM_PRINT_L1SIM_CMD_TRC114,
+ SIM_PRINT_L1SIM_CMD_TRC115,
+ SIM_PRINT_L1SIM_CMD_TRC116,
+ SIM_PRINT_L1SIM_CMD_TRC117,
+ SIM_PRINT_L1SIM_CMD_TRC118,
+ SIM_PRINT_L1SIM_CMD_TRC119,
+ SIM_PRINT_L1SIM_CMD_TRC120,
+ SIM_PRINT_L1SIM_CMD_TRC121,
+ SIM_PRINT_L1SIM_CMD_TRC122,
+ SIM_PRINT_L1SIM_CMD_TRC123,
+ SIM_PRINT_L1SIM_CMD_TRC124,
+ SIM_PRINT_L1SIM_CMD_TRC125,
+ SIM_PRINT_L1SIM_CMD_TRC126,
+ SIM_PRINT_L1SIM_CMD_TRC127,
+ SIM_PRINT_L1SIM_CMD_TRC128,
+ SIM_PRINT_L1SIM_CMD_TRC129,
+ SIM_PRINT_L1SIM_CMD_TRC130,
+} sim_printEnum;
+#endif /*__SIM_DRV_HW_DEF_MTK_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_HW_reg_MTK.h b/mcu/driver/devdrv/usim/inc/sim_drv_HW_reg_MTK.h
new file mode 100644
index 0000000..0405876
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_HW_reg_MTK.h
@@ -0,0 +1,1165 @@
+#ifndef __SIM_DRV_HW_REG_MTK_H__
+#define __SIM_DRV_HW_REG_MTK_H__
+
+
+
+#ifdef SIM_base
+ #undef SIM_base
+#endif
+#define SIM_base SIM0_base
+
+#ifdef SIM2_base
+ #undef SIM2_base
+#endif
+#define SIM2_base SIM1_base
+
+
+
+
+#define ACK_NULL_CHAR 0x60
+
+#define SIM_CTRL (SIM_base+0x0)
+#define SIM_CONF (SIM_base+0x4)
+#define SIM_BRR (SIM_base+0x8)
+#define SIM_IRQEN (SIM_base+0x10)
+#define SIM_STS (SIM_base+0x14)
+
+#define SIM_RETRY (SIM_base+0x20)
+#define SIM_TIDE (SIM_base+0x24)
+
+#define SIM_DATA (SIM_base+0x30)
+#define SIM_COUNT (SIM_base+0x34)
+
+#define SIM_ATIME (SIM_base+0x40)
+#define SIM_DTIME (SIM_base+0x44)
+#define SIM_TOUT (SIM_base+0x48)
+
+#define SIM_INS (SIM_base+0x60)
+#define SIM_IMP3 (SIM_base+0x64)
+#define SIM_SW1 (SIM_base+0x68)
+#define SIM_SW2 (SIM_base+0x6c)
+#define SIM_REG_STATUS (SIM_base+0x74)
+
+
+/*
+ This is the most important define to combine single SIM and multiple SIM macro.
+ In DRV_SIM_ALL_SOLUTION_BUILT, single SIM driver's macro will use this variable, too.
+ DRV_SIM_BUILD_SINGLE_SIM is only defined in simd.c and usim_drv.c before including this header file.
+*/
+extern kal_uint32 simBaseAddr, simBaseAddrSpace;
+#ifdef DRV_SIM_BUILD_SINGLE_SIM
+ #define SIM0_BASE_ADDR_MTK (simBaseAddr )
+#else
+ /*in DRV_SIM_ALL_SOLUTION_BUILT, we use two variables, starting address and adress space, to calculate the actual address*/
+ //#define SIM0_BASE_ADDR_MTK (simBaseAddr + (simBaseAddrSpace * simInterface))
+ #define SIM0_BASE_ADDR_MTK (hw_cb->mtk_baseAddr)
+#endif
+
+// MTK04122: updated for MT6290
+#define SIM_VERSION_MTK 0x0
+#define SIM_CTRL_MTK 0x10
+#define SIM_CONF_MTK 0x14
+#define SIM_CONFSTA_MTK 0x18
+#define SIM_BRR_MTK 0x1C
+#define SIM_IRQEN_MTK 0x20
+#define SIM_STS_MTK 0x24
+
+#define SIM_RETRY_MTK 0x30
+#define SIM_TIDE_MTK 0x34
+
+#define SIM_DATA_MTK 0x40
+#define SIM_COUNT_MTK 0x44
+
+#if !defined(DRV_SIM_6293_SERIES) && !defined(DRV_SIM_6295_SERIES) && !defined(DRV_SIM_6297_SERIES)
+ #define SIM_ATIME_MTK 0x50
+#endif
+#define SIM_DTIME_MTK 0x54
+#define SIM_TOUT_MTK 0x58
+
+#define SIM_GTIME_MTK 0x5C
+#define SIM_ETIME_MTK 0x60
+#define SIM_EXT_TIME_MTK 0x64
+#define SIM_CGTIME_MTK 0x68
+
+
+/********************/
+//MTK04122: be removed in mt6290
+#define SIM_INS_MTK 0x60
+#define SIM_IMP3_MTK 0x64
+/********************/
+
+#define SIM_COMDCTRL_MTK 0x70
+#define SIM_COMDLEN_MTK 0x74
+#define SIM_LEFTLEN_MTK 0x78
+
+#define SIM_SW1_MTK 0x7C
+#define SIM_SW2_MTK 0x80
+
+#define SIM_ATRSTA_MTK 0x90
+#define SIM_STATUS_MTK 0x94
+#define SIM_DBG_MTK 0x98
+#define SIM_DBGDATA_MTK 0x9C
+
+/*************** since Gen93 ***************/
+#if defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES)|| defined(DRV_SIM_6297_SERIES)
+ #define SIM_ATIME1_MTK 0xB0
+ #define SIM_ATIME2_MTK 0xB4
+ #define SIM_ATIME3_MTK 0xB8
+ #define SIM_ATIME4_MTK 0xBC
+ #define SIM_ATIME_MTK SIM_ATIME1_MTK
+
+ #define SIM_SIMOE_MODE_MTK 0xC0
+ #define SIM_MANUAL_CTRL_MTK 0xA4
+#endif
+/*******************************************/
+/*************** since Gen95 ***************/
+#if defined(SIM_DRV_PRINT_DEBUG1_2)
+#define SIM_DEBUG1_MTK 0xD0
+#define SIM_DEBUG2_MTK 0xD4
+#endif
+/*******************************************/
+
+//SIM_CTRL
+#define SIM_CTRL_SIMON 0x0001
+#define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+#define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+#define SIM_CTRL_RSTLV 0x0008
+#define SIM_CTRL_RSTCTRL 0x0010
+#define SIM_CTRL_IFCLR 0x0020
+
+//SIM_CONF
+#define SIM_CONF_RXHSK 0x0001
+#define SIM_CONF_TXHSK 0x0002
+#define SIM_CONF_CLKPO 0x0004
+
+/********************/
+//MTK04122: be removed in mt6290
+#define SIM_CONF_SINV 0x0008
+#define SIM_CONF_SDIR 0x0010
+#define SIM_CONF_ODDPARITY 0x0020
+
+#define SIM_CONF_Direct 0x0000
+#define SIM_CONF_InDirect 0x0038
+/********************/
+#define SIM_CONF_CONV 0x0008
+
+#define SIM_CONF_SIMSEL 0x0010
+#define SIM_CONF_TOUTEN 0x0020
+#define SIM_CONF_T1EN 0x0040
+#define SIM_CONF_T0EN 0x0080
+#define SIM_CONF_HFEN 0x0100
+#define SIM_CONF_RXRDIS 0x0200
+#define SIM_CONF_TXRDIS 0x0400
+#define SIM_CONF_T1TX2RXEN 0x0800
+
+//SIM_CONFSTA
+#define SIM_CONFSTA_IFCLR_ON 0x0001
+#define SIM_CONFSTA_TXRDIS_S 0x0400
+
+//SIM_BRR
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+#define SIM_BRR_CLKMSK 0x3803
+#else
+#define SIM_BRR_CLKMSK 0x0003
+#endif
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ #define SIM_BRR_CLK_Div6 0x0000
+ #define SIM_BRR_CLK_Div8 0x0001
+ #define SIM_BRR_CLK_Div16 0x0002
+ #define SIM_BRR_CLK_Div32 0x0003
+#if defined(SIM_DRV_3_71MHZ_SCLK)
+ #define SIM_BRR_CLK_Div7 0x0800
+#endif
+#else
+ /********************/
+ //MTK04122: be removed in mt6290
+ #define SIM_BRR_CLK_Div2 0x0000
+ /********************/
+
+ #define SIM_BRR_CLK_Div4 0x0001
+ #define SIM_BRR_CLK_Div8 0x0002
+ #define SIM_BRR_CLK_Div12 0x0003
+#endif
+
+#define SIM_BRR_ETUMSK 0x07FC
+
+//MTK04122:need to clarify
+#define SIM_BRR_BAUDMSK 0x000C
+
+
+#define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1
+#define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8
+#define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16
+#define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32
+#define SIM_BRR_BAUD_Div8 (8<<2) //F=512,D=64
+
+//SIM_IRQEN
+#define SIM_IRQEN_TX 0x0001
+#define SIM_IRQEN_RX 0x0002
+#define SIM_IRQEN_OV 0x0004
+#define SIM_IRQEN_TOUT 0x0008
+#define SIM_IRQEN_TXERR 0x0010
+#define SIM_IRQEN_NATR 0x0020
+#define SIM_IRQEN_SIMOFF 0x0040
+#define SIM_IRQEN_T0END 0x0080
+#define SIM_IRQEN_RXERR 0x0100
+#define SIM_IRQEN_T1END 0x0200
+#define SIM_IRQEN_EDCERR 0x0400
+#define SIM_IRQEN_UDRUN 0x0800
+
+/*TX, RX ,OV, TOUT, TXER, NATR, SIMOFF, RXER*/
+#define SIM_IRQEN_ALL 0x01bf
+#define SIM_IRQEN_ALLOFF 0x0000
+
+/* SIM_IRQEN_RXErr, SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT, SIM_IRQEN_OV, SIM_IRQEN_RX*/
+#define SIM_IRQEN_Normal 0x013e
+
+/*SIM_IRQEN_RXERR, SIM_IRQEN_T0END,SIM_IRQEN_TXErr, SIM_IRQEN_TOUT, SIM_IRQEN_OV, SIM_IRQEN_RX*/
+#define SIM_IRQEN_CMDNormal 0x019e
+/*#define SIM_IRQEN_CMDNormal 0x019c*/
+
+/*SIM_IRQEN_RXERR, SIM_IRQEN_T0END,SIM_IRQEN_TXErr, SIM_IRQEN_TOUT, SIM_IRQEN_OV*/
+#define SIM_IRQEN_CMDDMANormal 0x019c
+
+#define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR)
+#define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR)
+#define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \
+ SIM_STS_OV|SIM_STS_TOUT)
+#define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX)
+#define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END)
+
+//SIM_STS
+#define SIM_STS_TX 0x0001
+#define SIM_STS_RX 0x0002
+#define SIM_STS_OV 0x0004
+#define SIM_STS_TOUT 0x0008
+#define SIM_STS_TXERR 0x0010
+#define SIM_STS_NATR 0x0020
+#define SIM_STS_SIMOFF 0x0040
+#define SIM_STS_T0END 0x0080
+#define SIM_STS_RXERR 0x0100
+#define SIM_STS_T1END 0x0200
+#define SIM_STS_EDCERR 0x0400
+#define SIM_STS_UDRUN 0x0800
+
+//SIM_TOUT
+#define SIM_TOUT_MSK 0x3fff //??
+
+//SIM_RETRY
+#define SIM_RETRY_RXMASK 0x0007
+#define SIM_RETRY_TXMASK 0x0700
+
+//SIM_TIDE
+#define SIM_TIDE_RXMASK 0x000f
+#define SIM_TIDE_TXMASK 0x0f00
+
+//SIM_COUNT
+#define SIM_COUNT_MASK 0x001f
+
+//SIM_COMDCTRL: shall be re-named
+#define SIM_INS_MASK 0x00ff
+#define SIM_INS_INSD 0x0100
+#define SIM_INS_START 0x8000
+
+//SIM_COMDLEN
+#define SIM_IMP3_MASK 0x00ff
+
+//SIM_ATRSTA
+#define SIM_ATRSTA_OFF 0x0001
+#define SIM_ATRSTA_IR 0x0080
+#define SIM_ATRSTA_AL 0x0100
+
+/*MTK04122: to be update for mt6290 (TBC)*/
+// SIM_STATUS
+#define SIM_STATUS_EDC 0x40
+#define SIM_STATUS_ACK 0x20
+#define SIM_STATUS_NACK 0x10
+#define SIM_STATUS_IDLE 0x01
+#define SIM_STATUS_INS 0x02
+#define SIM_STATUS_SW1 0x04
+#define SIM_STATUS_SW2 0x08
+
+#define SIM_TX_DELAY_LEN 0x4
+#define SIM_TX_DELAY_LOOP 4000
+
+#define SIM_SIMOE_ENABLE 0x1
+/*
+ * HDMA Register Definitions
+ */
+#define BASE_HDMA BASE_ADDR_MDGDMA
+#define REG_HDMA_HDCSR0 (BASE_HDMA + 0x0100)
+#define HDMA_MODE_0 (1 << 9) //channel 0
+#define HDMA_MODE_1 (1 << 25) //channel 1
+#define REG_HDMA_HDSR (BASE_HDMA + 0x0120) // shared
+#define HDMA_STAT0_0 (1 << 0) // buffer 0, channel 0
+#define HDMA_STAT0_1 (1 << 1) // buffer 0, channel 1
+#define HDMA_STAT1_0 (1 << 16) // buffer 1, channel 0
+#define HDMA_STAT1_1 (1 << 17) // buffer 1, channel 1
+#define REG_HDMA_HDCPR (BASE_HDMA + 0x0124) // shared
+#define HDMA_HCURR_PTR_0 (1 << 0) // channel 0
+#define HDMA_HCURR_PTR_1 (1 << 1) // channel 1
+#define REG_HDMA_HDCTRR0 (BASE_HDMA + 0x0140) // channel 0
+#define REG_HDMA_HDCTRR1 (BASE_HDMA + 0x0160) // channel 1
+#define HDCTRR_STOP (1 << 2)
+#define HDCTRR_MEM_BUS_WIDTH(n) ((n) << 4)
+#define HDCTRR_DEV_BUS_WIDTH(n) ((n) << 6)
+#define HDCTRR_BUS_WIDTH_8 0
+#define HDCTRR_BUS_WIDTH_16 1
+#define HDCTRR_BUS_WIDTH_32 2
+#if defined(DRV_SIM_6290_SERIES) || defined(DRV_SIM_6291_SERIES) || defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES)
+#define HDCTRR_BST_SIZE(n) ((n) << 13)
+#else
+#define HDCTRR_BST_SIZE(n) ((n) << 12)
+#endif
+#define HDCTRR_BST_SIZE_4 2
+#define HDCTRR_BST_SIZE_8 3
+#define HDCTRR_BST_SIZE_16 4
+#define HDCTRR_BST_SIZE_32 5 // reserved
+#define HDCTRR_BST_SIZE_64 6 // reserved
+#define HDCTRR_BST_SIZE_128 7 // reserved
+#define HDCTRR_RX_SEL0(n) ((n) << 30)
+#define HDCTRR_RX_SEL1(n) ((n) << 31)
+#define REG_HDMA_HDC0R0 (BASE_HDMA + 0x0144) // channel 0
+#define REG_HDMA_HDC0R1 (BASE_HDMA + 0x0164) // channel 1
+#define HDCR_XFER_SIZE0(n) ((n) << 16)
+#define HDCR_START0 (1 << 0)
+#define REG_HDMA_HDC1R0 (BASE_HDMA + 0x0148) // channel 0
+#define REG_HDMA_HDC1R1 (BASE_HDMA + 0x0168) // channel 1
+#define HDCR_XFER_SIZE1(n) ((n) << 16)
+#define HDCR_START1 (1 << 0)
+#define REG_HDMA_HPRGA0R0 (BASE_HDMA + 0x014C) // channel 0
+#define REG_HDMA_HPRGA0R1 (BASE_HDMA + 0x016C) // channel 1
+#define REG_HDMA_HPRGA1R0 (BASE_HDMA + 0x0150) // channel 0
+#define REG_HDMA_HPRGA1R1 (BASE_HDMA + 0x0170) // channel 1
+#define REG_HDMA_HCCR0 (BASE_HDMA + 0x0154) // channel 0
+#define REG_HDMA_HCCR1 (BASE_HDMA + 0x0174) // channel 1
+#define HDMA_HCURR_CNT0 0x0000FFFF
+#define HDMA_HCURR_CNT1 0xFFFF0000
+#define REG_HDMA_HDCPR0 (BASE_HDMA + 0x0158) // channel 0
+#define REG_HDMA_HDCPR1 (BASE_HDMA + 0x0178) // channel 1
+#define REG_GDMA_GPMTR5 (BASE_HDMA + 0x0424) // HDMA channel promotion
+
+
+#if defined(SIM_DRV_USE_MDGPIO_I2C)
+ #define MD_AP_DUMMY_I2C (BASE_MADDR_MDPERIMISC+0x100) //0xA0060000
+ #define AP_MD_DUMMY_I2C (BASE_MADDR_MDPERIMISC+0x300)
+ #define MD_AP_SCL (1<<15)
+ #define MD_AP_SDA (1<<14)
+ #define MD_AP_SDA_OE (1<<13)
+#endif
+
+
+#if defined(MT6763) // shall use this format afterall
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x350)
+#define IO_CFG_LB_BASE 0xC1E70000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_LB_BASE + 0x010)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LB_BASE + 0x010)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x020)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x020)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x040)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x040)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_LB_BASE + 0x0A0)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LB_BASE + 0x0A0)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_LB_BASE + 0x0C0)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LB_BASE + 0x0C0)
+#define SIM1_INS 0x00888000
+#define SIM2_INS 0x00000888
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x04); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) | SIM2_INS)); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x40); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM1_INS)); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x02); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) & ~(SIM2_INS))); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x20); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM1_INS))); \
+ }
+
+
+
+ #if defined(__SIM_SAME_GPIO_MODE__)
+ #define GPIO_SIM2_SIMIO 35
+ #define GPIO_SIM2_SIMRST 36
+ #define GPIO_SIM2_SIMCLK 37
+ #define GPIO_SIM1_SIMCLK 38
+ #define GPIO_SIM1_SIMRST 39
+ #define GPIO_SIM1_SIMIO 40
+ #else
+ #define GPIO_SIM1_SIMIO 35
+ #define GPIO_SIM1_SIMRST 36
+ #define GPIO_SIM1_SIMCLK 37
+ #define GPIO_SIM2_SIMCLK 38
+ #define GPIO_SIM2_SIMRST 39
+ #define GPIO_SIM2_SIMIO 40
+ #endif
+
+#elif defined(MT6739)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x390)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3A0)
+#define IOCFG_LB_BASE 0xC0002400
+#define REG_GPIO_IES_0_FOR_SIM (IOCFG_LB_BASE + 0x020)
+#define REG_GPIO_IES_1_FOR_SIM (IOCFG_LB_BASE + 0x020)
+#define REG_GPIO_SMT_0_FOR_SIM (IOCFG_LB_BASE + 0x090)
+#define REG_GPIO_SMT_1_FOR_SIM (IOCFG_LB_BASE + 0x090)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x070)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x080)
+#define REG_GPIO_DRV_0_FOR_SIM (IOCFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IOCFG_LB_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IOCFG_LB_BASE + 0x030)
+#define REG_GPIO_PUPD_1_FOR_SIM (IOCFG_LB_BASE + 0x040) // for abnormal SIM
+#define SIM1_INS 0x00000007
+#define SIM2_INS 0x00000038
+#define REG_GPIO_R0_CFG0_CLR_FOR_SIM (IOCFG_LB_BASE + 0x058)
+#define REG_GPIO_R1_CFG0_SET_FOR_SIM (IOCFG_LB_BASE + 0x064)
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF0000)) | 0x50000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM2_INS)); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF000)) | 0x5000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM1_INS)); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF0000)) | 0x50000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM2_INS))); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~(0xF000)) | 0x5000); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM1_INS))); \
+ }
+
+ #if defined(__SIM_SAME_GPIO_MODE__)
+ #define GPIO_SIM2_SIMCLK 80
+ #define GPIO_SIM2_SIMRST 81
+ #define GPIO_SIM2_SIMIO 82
+ #define GPIO_SIM1_SIMCLK 77
+ #define GPIO_SIM1_SIMRST 78
+ #define GPIO_SIM1_SIMIO 79
+ #else
+ #define GPIO_SIM1_SIMCLK 80
+ #define GPIO_SIM1_SIMRST 81
+ #define GPIO_SIM1_SIMIO 82
+ #define GPIO_SIM2_SIMCLK 77
+ #define GPIO_SIM2_SIMRST 78
+ #define GPIO_SIM2_SIMIO 79
+ #endif
+#elif defined(MT6765)
+#define IOCFG_LB_BASE 0xC0002400
+
+#define REG_GPIO_INS_CFG0 (IOCFG_LB_BASE + 0x030)
+#define REG_GPIO_INS_CFG0_SET (IOCFG_LB_BASE + 0x034)
+#define REG_GPIO_INS_CFG0_CLR (IOCFG_LB_BASE + 0x038)
+
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+
+#define REG_GPIO_IES_0_FOR_SIM (IOCFG_LB_BASE + 0x020)
+#define REG_GPIO_IES_1_FOR_SIM (IOCFG_LB_BASE + 0x020)
+
+#define REG_GPIO_SMT_0_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+#define REG_GPIO_SMT_1_FOR_SIM (IOCFG_LB_BASE + 0x0B0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x0D0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x0D0)
+
+#define REG_GPIO_RDSEL_0_FOR_SIM (IOCFG_LB_BASE + 0x090)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IOCFG_LB_BASE + 0x0A0)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IOCFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IOCFG_LB_BASE + 0x000)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IOCFG_LB_BASE + 0x070) // R0_CFG0
+#define REG_GPIO_PUPD_1_FOR_SIM (IOCFG_LB_BASE + 0x080) // R1_CFG0
+
+#define SIM1_INS 0x00000007
+#define SIM2_INS 0x00000038
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_SET, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_SET, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_CLR, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_INS_CFG0_CLR, SIM1_INS); \
+ }
+
+#if defined(__SIM_SAME_GPIO_MODE__)
+ #define GPIO_SIM2_SIMCLK 37
+ #define GPIO_SIM2_SIMRST 36
+ #define GPIO_SIM2_SIMIO 35
+ #define GPIO_SIM1_SIMCLK 38
+ #define GPIO_SIM1_SIMRST 39
+ #define GPIO_SIM1_SIMIO 40
+#else
+ #define GPIO_SIM1_SIMCLK 37
+ #define GPIO_SIM1_SIMRST 36
+ #define GPIO_SIM1_SIMIO 35
+ #define GPIO_SIM2_SIMCLK 38
+ #define GPIO_SIM2_SIMRST 39
+ #define GPIO_SIM2_SIMIO 40
+#endif
+
+#elif defined(MT6295M) || defined(MT3967)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x370)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x380)
+#define IO_CFG_BL_BASE 0xC1D10000
+#define IO_CFG_LB_BASE 0xC1E70000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x050)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LB_BASE + 0x060)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x0F0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LB_BASE + 0x120)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x130)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x160)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x0D0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x0F0)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x020)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LB_BASE + 0x020)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LB_BASE + 0x0A0)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x060)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_LB_BASE + 0x080)
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000002
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x0A8)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0B4)
+#define REG_GPIO_R0_CFG0_CLR_1_FOR_SIM (IO_CFG_LB_BASE + 0x0C8)
+#define REG_GPIO_R1_CFG0_SET_1_FOR_SIM (IO_CFG_LB_BASE + 0x0D4)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x104)
+#define REG_GPIO_SR_CFG0_SET_1_FOR_SIM (IO_CFG_LB_BASE + 0x134)
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x1400); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x1400); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x0A00); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM, 0); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x0A00); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM, 0); \
+ }
+#elif defined(MT6779)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x400)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x400)
+#define IOCFG_RM_BASE 0xC1C20000
+#define REG_GPIO_IES_0_FOR_SIM (IOCFG_RM_BASE + 0x030)
+#define REG_GPIO_IES_1_FOR_SIM (IOCFG_RM_BASE + 0x030)
+#define REG_GPIO_SMT_0_FOR_SIM (IOCFG_RM_BASE + 0x0C0)
+#define REG_GPIO_SMT_1_FOR_SIM (IOCFG_RM_BASE + 0x0C0)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IOCFG_RM_BASE + 0x0F0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IOCFG_RM_BASE + 0x0F0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IOCFG_RM_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IOCFG_RM_BASE + 0x0B0)
+#define REG_GPIO_DRV_0_FOR_SIM (IOCFG_RM_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IOCFG_RM_BASE + 0x010)
+#define REG_GPIO_PUPD_0_FOR_SIM (IOCFG_RM_BASE + 0x060)
+#define REG_GPIO_PUPD_1_FOR_SIM (IOCFG_RM_BASE + 0x060)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IOCFG_RM_BASE + 0x040)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IOCFG_RM_BASE + 0x040)
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IOCFG_RM_BASE + 0x0D0)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IOCFG_RM_BASE + 0x088)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IOCFG_RM_BASE + 0x094)
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x000000FC); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x000000A8); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, 0x78000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x00000003); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x50000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000002); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x000000FC); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000054); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, 0x78000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, 0x00000003); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x28000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000001); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MT6297)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x330)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x340)
+#define IO_CFG_BL_BASE 0xC1D00000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x010)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BL_BASE + 0x010)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x0A0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x0A0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x060)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x070)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x030)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BL_BASE + 0x030)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x020)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BL_BASE + 0x020 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x048)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x058)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x044)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x054)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x090)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x94)
+#define SIM1_DRIVING_MASK 0x1FF
+#define SIM2_DRIVING_MASK 0x3FE00
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x9200); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x049); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x0); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x0); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MT6885)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x350)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x360)
+#define IO_CFG_LT_BASE 0xC1F20000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_LT_BASE + 0x040)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LT_BASE + 0x014)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_LT_BASE + 0x0E0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LT_BASE + 0x0E0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_LT_BASE + 0x110)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LT_BASE + 0x110)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_LT_BASE + 0x090)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LT_BASE + 0x090)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_LT_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LT_BASE + 0x010)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_LT_BASE + 0x070)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LT_BASE + 0x070)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_LT_BASE + 0x050)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_LT_BASE + 0x050 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_LT_BASE + 0x098)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_LT_BASE + 0x0A8)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_LT_BASE + 0x094)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_LT_BASE + 0x0A4)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_LT_BASE + 0x0F0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_LT_BASE + 0xF4)
+#define SIM1_DRIVING_MASK 0x3F000000
+#define SIM2_DRIVING_MASK_1 0xC0000000
+#define SIM2_DRIVING_MASK_2 0x0000000F
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK_1); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK_2); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x80000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0xA); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x2A000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK_1); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK_2); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x40000000); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x5); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x15000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MT6873)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x350)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x360)
+#define IO_CFG_RM_BASE 0xC1C20000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_RM_BASE + 0x030)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_RM_BASE + 0x030)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_RM_BASE + 0x0C0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_RM_BASE + 0x0C0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x0F0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x0F0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_RM_BASE + 0x010)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_RM_BASE + 0x010)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_RM_BASE + 0x060)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_RM_BASE + 0x060)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x040)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_RM_BASE + 0x040 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x088)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x098)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x084)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x0D0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x0D4)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IO_CFG_RM_BASE + 0x088)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+#define SIM1_DRIVING_MASK 0x00000300
+#define SIM2_DRIVING_MASK 0x000000C0
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00000080); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00000200); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00000040); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00000100); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+#elif defined(MERCURY)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define IO_CFG_BL_BASE 0xC1D00000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BL_BASE + 0x000 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x00)
+#define SIM1_DRIVING_MASK 0x1FF
+#define SIM2_DRIVING_MASK 0x3FE00
+
+#define ENABLE_ABNORMAL_SIM(_n) ;
+
+#define DISABLE_ABNORMAL_SIM(_n) ;
+#elif defined(MT6853)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3E0)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3F0)
+#define IO_CFG_RM_BASE 0xC1C20000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_RM_BASE + 0x020)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_RM_BASE + 0x020)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_RM_BASE + 0x094)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_RM_BASE + 0x080)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_RM_BASE + 0x080)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_RM_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_RM_BASE + 0x010)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_RM_BASE + 0x040)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_RM_BASE + 0x040)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x030)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_RM_BASE + 0x030 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x058)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_RM_BASE + 0x068)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x054)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x064)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_RM_BASE + 0x0A0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_RM_BASE + 0x0A4)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IO_CFG_RM_BASE + 0x058)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IO_CFG_RM_BASE + 0x064)
+#define SIM1_DRIVING_MASK 0x00300000
+#define SIM2_DRIVING_MASK 0x000C0000
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00080000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00200000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00040000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00100000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+
+#elif defined(CHIP10992)
+#define IO_CFG_BL_BASE 0xC1D00000
+
+// only for reg dump
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3A0)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3B0)
+
+// only for reg dump
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BL_BASE + 0x040)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BL_BASE + 0x050)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BL_BASE + 0x0e0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BL_BASE + 0x0e0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x100)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x100)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BL_BASE + 0x0c0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BL_BASE + 0x0c0)
+
+// for both dump and config !!!
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BL_BASE + 0x000)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BL_BASE + 0x080)
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x0a8)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BL_BASE + 0x0b8)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0a4)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0b4)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x060)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BL_BASE + 0x060 )
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BL_BASE + 0x0f0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BL_BASE + 0x0f4)
+
+#define SIM1_DRIVING_MASK 0x00003000
+#define SIM2_DRIVING_MASK 0x00003000
+
+// When abnormal mode enabled, driving @ 3rd gear
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00002000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00002000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+// When abnormal mode disabled, driving @ 2nd gear
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x00001000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x00001000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+
+#elif defined(MT6833)
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3E0)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x3F0)
+#define IO_CFG_BR_BASE 0xC1D40000
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_BR_BASE + 0x040)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_BR_BASE + 0x040)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_BR_BASE + 0x0C0)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_BR_BASE + 0x0C0)
+
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_BR_BASE + 0x0E0)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_BR_BASE + 0x0F0)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_BR_BASE + 0x0B0)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_BR_BASE + 0x0B0)
+
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_BR_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_BR_BASE + 0x000)
+
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_BR_BASE + 0x070)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_BR_BASE + 0x070)
+
+#define REG_GPIO_INS_CFG_0_FOR_SIM (IO_CFG_BR_BASE + 0x050)
+#define REG_GPIO_INS_CFG_1_FOR_SIM (IO_CFG_BR_BASE + 0x050)
+#define SIM1_INS 0x00000002
+#define SIM2_INS 0x00000010
+#define REG_GPIO_R0_CFG0_CLR_0_FOR_SIM (IO_CFG_BR_BASE + 0x098)
+#define REG_GPIO_R1_CFG0_CLR_0_FOR_SIM (IO_CFG_BR_BASE + 0x0A8)
+#define REG_GPIO_R0_CFG0_SET_0_FOR_SIM (IO_CFG_BR_BASE + 0x094)
+#define REG_GPIO_R1_CFG0_SET_0_FOR_SIM (IO_CFG_BR_BASE + 0x0A4)
+
+#define REG_GPIO_SR_CFG_0_FOR_SIM (IO_CFG_BR_BASE + 0x0D0)
+#define REG_GPIO_SR_CFG0_SET_0_FOR_SIM (IO_CFG_BR_BASE + 0x0D4)
+#define REG_GPIO_R0_CFG_0_CLR_FOR_SIM (IO_CFG_BR_BASE + 0x098)
+#define REG_GPIO_R1_CFG_0_SET_FOR_SIM (IO_CFG_BR_BASE + 0x0A4)
+#define SIM1_DRIVING_MASK 0x18000000
+#define SIM2_DRIVING_MASK 0x60000000
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x40000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x4, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x10000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x4, SIM1_INS); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x8, SIM2_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_1_FOR_SIM + 0x4, 0x20000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_1_FOR_SIM + 0x8, SIM2_INS); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x8, SIM1_DRIVING_MASK); \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM + 0x4, 0x08000000); \
+ DRV_WriteReg32(REG_GPIO_INS_CFG_0_FOR_SIM + 0x8, SIM1_INS); \
+ }
+
+#else
+#define REG_GPIO_MODE_0_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define REG_GPIO_MODE_1_FOR_SIM (BASE_MADDR_AP_GPIOMUX + 0x000)
+#define IO_CFG_LB_BASE BASE_MADDR_AP_GPIOMUX
+#define REG_GPIO_IES_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_IES_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_SMT_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_SMT_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_TDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_TDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_RDSEL_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_RDSEL_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_DRV_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_PUPD_0_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define REG_GPIO_PUPD_1_FOR_SIM (IO_CFG_LB_BASE + 0x000)
+#define SIM1_INS 0x00000000
+#define SIM2_INS 0x00000000
+
+#define ENABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x02); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) | SIM2_INS)); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x20); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) | SIM1_INS)); \
+ }
+
+#define DISABLE_ABNORMAL_SIM(_n) \
+ if(_n) \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x07) | 0x01); \
+ DRV_WriteReg32(REG_GPIO_PUPD_0_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_0_FOR_SIM) & ~(SIM2_INS))); \
+ } \
+ else \
+ { \
+ DRV_WriteReg32(REG_GPIO_DRV_0_FOR_SIM, (DRV_Reg32(REG_GPIO_DRV_0_FOR_SIM) & ~0x70) | 0x10); \
+ DRV_WriteReg32(REG_GPIO_PUPD_1_FOR_SIM, (DRV_Reg32(REG_GPIO_PUPD_1_FOR_SIM) & ~(SIM1_INS))); \
+ }
+#define SET_SIM1_SR(_n)
+#define SET_SIM2_SR(_n)
+
+#endif
+
+
+#if defined(SIM_DRV_CTRL_VSIM_BY_SPMI)
+#if defined(MT6330)
+/* writel_field to config vsim en and lp; only valid when SW_OP_EN=1 (default 1) */
+#define RG_LDO_VSIM1_CON0 0x1c07
+#define RG_LDO_VSIM1_EN_MASK 0x1
+#define RG_LDO_VSIM1_EN_SHIFT 0x0
+#define RG_LDO_VSIM1_LP_MASK 0x1
+#define RG_LDO_VSIM1_LP_SHIFT 0x1
+
+#define RG_LDO_VSIM1_OP_EN1 0x1c0e
+#define RG_LDO_VSIM1_OP_EN1_SET 0x1c0f
+#define RG_LDO_VSIM1_OP_EN1_CLR 0x1c10
+#define RG_LDO_VSIM1_SW_OP_EN (0x1<<7)
+
+#define RG_LDO_VSIM2_CON0 0x1c18
+#define RG_LDO_VSIM2_EN_MASK 0x1
+#define RG_LDO_VSIM2_EN_SHIFT 0x0
+#define RG_LDO_VSIM2_LP_MASK 0x1
+#define RG_LDO_VSIM2_LP_SHIFT 0x1
+
+#define RG_LDO_VSIM2_OP_EN1 0x1c1f
+#define RG_LDO_VSIM2_OP_EN1_SET 0x1c20
+#define RG_LDO_VSIM2_OP_EN1_CLR 0x1c20
+#define RG_LDO_VSIM2_SW_OP_EN (0x1<<7)
+
+/* writel to config vsim voltage */
+#define RG_VSIM1_ANA_CON1 0x1e93
+// #define RG_VSIM1_VOSEL_MASK 0xF
+// #define RG_VSIM1_VOSEL_SHIFT 0
+
+#define RG_VSIM2_ANA_CON1 0x1e96
+// #define RG_VSIM2_VOSEL_MASK 0xF
+// #define RG_VSIM2_VOSEL_SHIFT 0
+
+#define LDO_VSIM_1P7V 0x3 //4'b0011: 1.7V
+#define LDO_VSIM_1P8V 0x4 //4'b0100: 1.8V
+#define LDO_VSIM_2P9V 0xA //4'b1010: 2.9V
+#define LDO_VSIM_3P0V 0xB //4b'1011: 3.0V
+
+
+#define RG_LDO_VSIM1_EINT 0x1c17
+#define RG_LDO_VSIM2_EINT 0x1c28
+
+#define RG_LDO_VSIMx_EINT_EN (0x1<<0) // 0: disable, 1:enable
+#define RG_LDO_VSIMx_EINT_POL (0x1<<2) // 0: Low active, 1: High active
+#define RG_LDO_VSIMx_EINT_DB_SEL (0x1<<4) // 0: 5us, 1: 10us
+
+#else
+#if defined(__MTK_TARGET__)
+#error "Please add VSIM related PMIC register defination for New PMIC"
+#endif
+#endif
+#endif /* SIM_DRV_CTRL_VSIM_BY_SPMI */
+
+#endif /*__SIM_DRV_HW_REG_MTK_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_SW_API.h b/mcu/driver/devdrv/usim/inc/sim_drv_SW_API.h
new file mode 100644
index 0000000..ae5b3f0
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_SW_API.h
@@ -0,0 +1,98 @@
+#ifndef __SIM_DRV_SW_API_H__
+#define __SIM_DRV_SW_API_H__
+#include "multi_icc_custom.h"
+
+#ifdef DRV_SIM_BUILD_SINGLE_SIM
+ //extern kal_uint16 SIM_CMD(kal_uint8 *txData,kal_uint16 txSize,kal_uint8 *result,kal_uint16 *rcvSize, kal_uint8 *Error);
+ extern void L1sim_ChangeBaud(void);
+ extern void L1sim_NormalBaud(void);
+ extern sim_card_speed_type L1sim_Get_CardSpeedType(void);
+ extern void L1sim_Enable_Enhanced_Speed(kal_bool enable);
+ extern kal_uint16 L1sim_Cmd_Layer(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize);
+
+ extern void SIM1_LDO_enable(kal_bool enable);
+ extern void SIM2_LDO_enable(kal_bool enable);
+
+ usim_status_enum L1sim_Reset_All(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm);
+ void L1sim_Enable_Enhanced_Speed_All(kal_bool enable);
+ kal_bool L1sim_Set_ClockStopMode_All(sim_clock_stop_enum mode);
+ void L1sim_PowerOff_All(void);
+ void L1sim_Get_Card_Info_All(sim_info_struct *info);
+ sim_status L1sim_Cmd_All(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize);
+ void L1sim_Select_SIM_PLUS(kal_bool isSIMPLUS);
+ void L1sim_Select_Prefer_PhyLayer_All(sim_protocol_phy_enum T);
+#endif
+
+sim_HW_cb *sim_get_hwCb(kal_uint32 simInterface);
+kal_uint32 sim_get_logical_from_SIMIF(kal_uint32 HWIf);
+void SIM_StartFaltalReport(sim_HW_cb *hw_cb);
+kal_uint8 DRV_ICC_GPTI_GetHandle(kal_uint32 *handle);
+void DRV_ICC_GPTI_StopItem(kal_uint32 handle);
+kal_bool DRV_ICC_GPTI_StartItem(kal_uint32 handle, kal_uint16 tick, void (*gptimer_func)(void *), void *parameter);
+kal_uint8 DRV_ICC_makeCLA(kal_uint8 CLAHighBits, kal_uint8 CLAFromApdu);
+extern void sim_MT6302_init(void);
+extern sim_status L1sim_Cmd_Layer_MT6302(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb, kal_bool *isSW6263);
+extern void sim_addMsg(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+extern void sim_set_logical_to_SIMIF(kal_uint32 HWIf, kal_uint32 logical);
+/* custom setting */
+extern kal_uint32 sim_get_logicalNum_from_app(SIM_ICC_APPLICATION application);
+extern kal_uint32 sim_get_MT6302_from_logicalNum(kal_uint32 logicalNum);
+extern kal_uint32 sim_get_hwCtrl_from_logicalNum(kal_uint32 logicalNum);
+extern kal_uint32 sim_get_MT6302PeerInterface(kal_uint8 chipNum, kal_uint32 portNum);
+extern kal_uint32 sim_custom_task_2_driver(kal_uint32 taskInterface);
+extern void *kal_get_current_thread_ID(void);
+extern void L1sim_Set_Slt_Rlt(kal_bool rlt, SIM_ICC_APPLICATION application);
+extern void sim_custom_setting_before_turning_on_vsim(kal_uint32 hwInterfaceNo);
+extern void sim_custom_setting_after_turning_off_vsim(kal_uint32 hwInterfaceNo);
+extern void sim_custom_setting_before_resetting_sim(kal_uint32 hwInterfaceNo);
+
+#ifndef __TBD__
+ extern kal_uint32 SIM_GetCurrentTime(void);
+ extern kal_uint32 SIM_GetDurationTick(kal_uint32 previous_time, kal_uint32 current_time);
+#endif
+
+#ifndef __FPGA__
+ void DRV_ICC_PMU_setVolt(kal_uint32 hwInterfaceNo, usim_power_enum volt);
+ void DRV_ICC_PMU_switch(kal_uint32 hwInterfaceNo, kal_bool enable);
+ #if defined(__DRV_SIM_LP_MODE__)
+ void DRV_ICC_SetLp(kal_uint32 hwInterfaceNo, kal_bool isOn);
+ #endif
+#endif
+#if defined(LPWR_SLIM)
+ extern void DRV_ICC_CLKSRC_Lock(kal_uint32 hwInterfaceNo, kal_bool fLock);
+#endif
+extern void USIM_low_power_related_setting(sim_HW_cb *hw_cb, kal_uint8 option);
+
+extern void SIM_SetRXTIDE(kal_uint16 RXTIDE, sim_HW_cb *hw_cb);
+extern void SIM_SetTXTIDE(kal_uint16 _TXTIDE, sim_HW_cb *hw_cb);
+extern void L1sim_Enable_Enhanced_Speed(kal_bool enable, sim_HW_cb *hw_cb);
+extern void USIM_SET_EVENT_Multiple(usim_dcb_struct *usim_dcb);
+extern void SIM_SetTOUT(kal_uint32 TOUT, sim_HW_cb *hw_cb);
+extern void DRV_ICC_print(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5);
+extern void DRV_ICC_print_dec(sim_HW_cb *hw_cb, sim_printEnum messageType, kal_uint32 value1, kal_uint32 value2, kal_uint32 value3, kal_uint32 value4, kal_uint32 value5);
+extern void DRV_ICC_print_str(kal_char sim_dbg_str[]);
+extern void DRV_ICC_print_err_msg(sim_HW_cb *hw_cb, kal_char sim_dbg_str[]);
+extern void sim_dump_fifo(sim_HW_cb *hw_cb);
+extern void sim_MT6306_clkStopper(sim_HW_cb *hw_cb);
+extern void SIM_RegHotPlugCb(SIM_ICC_APPLICATION application, DCL_SIM_PLUG_IN_CALLBACK hotPlugInCb, DCL_SIM_PLUG_OUT_CALLBACK hotPlugOutCb);
+extern void DRV_ICC_Calc_WWT(kal_uint16 Fi, kal_uint8 Di, kal_uint8 Wi, kal_uint32 *WWT);
+extern void SIM_EINT_Mask(sim_HW_cb *hw_cb, kal_bool enable, kal_uint32 line_num);
+#if defined(SIM_DRV_IC_USB)
+ extern kal_uint32 SIM_icusb_init(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_setVolt(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_enableSession(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_powerOn(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_cmd(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_disableSession(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_disconnectDone(sim_HW_cb *hw_cb);
+ extern kal_uint32 SIM_icusb_deinit(sim_HW_cb *hw_cb);
+#endif
+#if defined(__ABNORMAL_CARD__)
+ extern void usim_set_sim_io_special_mode(kal_int32 simIF, kal_bool enable);
+#endif // #if defined(__ABNORMAL_CARD__)
+
+extern void sim_releaseOwner(SIM_ICC_APPLICATION application);
+#if defined(__SIM_ACTIVATION_V2__)
+ extern void usim_gpt_timeout_handler_for_SIM_activation(void *parameter);
+#endif
+#endif /*__SIM_DRV_SW_API_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_SW_function.h b/mcu/driver/devdrv/usim/inc/sim_drv_SW_function.h
new file mode 100644
index 0000000..c9ec04e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_SW_function.h
@@ -0,0 +1,585 @@
+#ifndef __SIM_DRV_SW_FUNCTION_H__
+#define __SIM_DRV_SW_FUNCTION_H__
+
+#include "us_timer.h"
+
+
+
+#if defined(ATEST_DRV_ENABLE) || defined (__IC_SLT__)
+ #define SIM_DEBUG_ASSERT(_condition) ASSERT(_condition)
+#else //#ifdef defined(ATEST_DRV_ENABLE)|| defined (__IC_SLT__)
+#ifndef __DEBUG_ASSERT_SUPPORT__
+extern kal_char SIM_DEBUG_ASSERT_STR[512];
+ #define SIM_DEBUG_ASSERT(_condition)\
+ { \
+ if (!(_condition))\
+ {\
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(SIM_DEBUG_ASSERT_STR, "[SIM_DRV][ERR][%s:%d][%s] SIM_DEBUG_ASSERT !!!!!\r\n", __FILE__, __LINE__,__FUNCTION__); \
+ if (log_size > 0) DRV_ICC_print_str(SIM_DEBUG_ASSERT_STR); \
+ DEBUG_ASSERT(_condition); \
+ }\
+ }
+#else //#ifndef __DEBUG_ASSERT_SUPPORT__
+ #define SIM_DEBUG_ASSERT(_condition) DEBUG_ASSERT(_condition)
+#endif
+#endif
+
+
+#ifdef SIM_DBG_OPTION_ENABLE
+#define SIM_ASSERT(_condition) \
+ { \
+ ASSERT(_condition); \
+ }
+#else /*!SIM_DBG_OPTION_ENABLE*/
+#if defined(SIM_DEBUG_INFO)
+#define SIM_ASSERT(_condition) \
+ { \
+ if (!(_condition)) \
+ { \
+ sim_assert(__LINE__); \
+ } \
+ }
+#else
+#define SIM_ASSERT(_condition)
+#endif /*#if defined(SIM_DEBUG_INFO)*/
+#endif /*SIM_DBG_OPTION_ENABLE*/
+
+
+#define SIM_SetRXRetry(_RXRetry)\
+ {\
+ kal_uint16 _Retry;\
+ Data_Sync_Barrier(); \
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_RXMASK;\
+ _Retry |= _RXRetry;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_SetTXRetry(_TXRetry) \
+ {\
+ kal_uint16 _Retry;\
+ Data_Sync_Barrier(); \
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_TXMASK;\
+ _Retry |= (_TXRetry<<8);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_ObtainSW(_SW) \
+ {\
+ kal_uint16 _SW1;\
+ kal_uint16 _SW2;\
+ Data_Sync_Barrier(); \
+ _SW1 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK);\
+ _SW2 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW2_MTK);\
+ _SW = (_SW2 | (_SW1 << 8));\
+ }
+
+#define SIM_DMA_STOP(_channel) \
+ {\
+ kal_uint32 cnt = 0, ori_REG_HDMA_HDCTRR;\
+ if(_channel)\
+ {\
+ ori_REG_HDMA_HDCTRR = DRV_Reg32(REG_HDMA_HDCTRR1);\
+ SIM_SetBits32(REG_HDMA_HDCTRR1, HDCTRR_STOP);\
+ while((SIM_Reg32(REG_HDMA_HDCTRR1) & HDCTRR_STOP))\
+ {\
+ cnt++;\
+ if(cnt % 1000 == 0)\
+ {\
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC127, cnt, ori_REG_HDMA_HDCTRR, 0, 0, 0);\
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC127, hw_cb);\
+ }\
+ if(cnt % 10000 == 0) SIM_DEBUG_ASSERT(0);\
+ ust_us_busyloop(100); \
+ }\
+ } else\
+ {\
+ ori_REG_HDMA_HDCTRR = DRV_Reg32(REG_HDMA_HDCTRR0);\
+ SIM_SetBits32(REG_HDMA_HDCTRR0, HDCTRR_STOP);\
+ while((SIM_Reg32(REG_HDMA_HDCTRR0) & HDCTRR_STOP))\
+ {\
+ cnt++;\
+ if(cnt % 1000 == 0)\
+ {\
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC127, cnt, ori_REG_HDMA_HDCTRR, 0, 0, 0);\
+ sim_dump_reg(SIM_PRINT_L1SIM_CMD_TRC127, hw_cb);\
+ }\
+ if(cnt % 10000 == 0) SIM_DEBUG_ASSERT(0);\
+ ust_us_busyloop(100); \
+ }\
+ }\
+ }
+
+//#define SIM_SetIMP3(_IMP3) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), _IMP3)
+#define SIM_SetCOMDLEN(_COMDLEN) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COMDLEN_MTK), _COMDLEN)
+
+//#define SIM_SetCmdINS(_INS) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_INS_MTK), _INS)
+#define SIM_SetCmdCTRL(_INS) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK), _INS)
+#define SIM_CMDSTART() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK),SIM_INS_START)
+
+#define SIM_SetAtime(_ATIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), _ATIME)
+#define SIM_SetDtime(_DTIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DTIME_MTK), _DTIME)
+
+//#define SIM_FIFO_Flush() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), 0x01)
+//mt6290
+#if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES)|| defined(DRV_SIM_6297_SERIES)
+#define SIM_FIFO_Flush() \
+ {\
+ SIM_PRINT_DEBUG1_2; \
+ DRV_WriteReg32_NPW((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ Data_Sync_Barrier(); \
+ while(DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON); \
+ }
+#elif (defined(DRV_SIM_6290_SERIES) || defined(DRV_SIM_6291_SERIES)) && !defined(ATEST_ENABLE)
+#define SIM_FIFO_Flush() \
+ do {\
+ DRV_WriteReg32_NPW((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ ust_us_busyloop(2); \
+ } while(0)
+#else
+#define SIM_FIFO_Flush() \
+ { \
+ kal_uint32 t1 = 0; \
+ DRV_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
+ t1 = drv_get_current_time(); \
+ while(drv_get_duration_tick(t1, drv_get_current_time()) < 2); \
+ }
+#endif
+
+#if defined(SIM_DRV_PRINT_DEBUG1_2)
+#define SIM_PRINT_DEBUG1_2 \
+ { \
+ kal_uint32 dbg[2] = {0}; \
+ dbg[0] = DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DEBUG1_MTK); \
+ dbg[1] = DRV_Reg32(SIM0_BASE_ADDR_MTK + SIM_DEBUG2_MTK); \
+ if(dbg[0] != 0 || dbg[1] != 0) \
+ { \
+ DRV_ICC_print(hw_cb, SIM_PRINT_L1SIM_CMD_TRC123, dbg[0], dbg[1], 0, 0, 0); \
+ } \
+ } while (0)
+#else
+#define SIM_PRINT_DEBUG1_2
+#endif
+
+#ifdef NO_SLIM_DEF
+#define SIM_Reject_Single() \
+ {\
+ SIM_DisAllIntr();\
+ SimCard.State = SIM_PWROFF;\
+ *(volatile kal_uint16 *)SIM_IRQEN = SIM_IRQEN_SIMOFF;\
+ *(volatile kal_uint16 *)SIM_CTRL &= ~SIM_CTRL_SIMON;\
+ SIM_FIFO_Flush();\
+ }
+
+#define SIM_Reject_MT6302(hw_cb) \
+ {\
+ SIM_DisAllIntr();\
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_MT6302_addMsg(SIM_MT6302_DRIVER_DEACT, hw_cb->simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ if(KAL_FALSE == sim_MT6302_QueryNeedManualControl(hw_cb)){\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);\
+ sim_MT6302_VCCCtrl(hw_cb, 0);\
+ }\
+ else{\
+ sim_MT6302_manualDeactive(hw_cb);\
+ }\
+ }\
+ else\
+ {\
+ sim_PDNEnable_MT6302(hw_cb);\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent_MT6302(SimCard,SIM_NOREADY);\
+ }\
+ }
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+/*SIM_WaitEvent_MTK(SimCard,SIM_NOREADY,KAL_FALSE)*/
+#define SIM_Reject_MTK(hw_cb) \
+ {\
+ dbg_print("\r\n++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r\n");\
+ SIM_DisAllIntr();\
+ if(SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_addMsg(SIM_DRIVER_DEACT_SIMD, hw_cb->simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ SIM_ClearBits(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK, SIM_CTRL_SIMON);\
+ SIM_WaitEvent_MTK(SimCard,SIM_NOREADY,KAL_FALSE); \
+ } else\
+ {\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent_MTK(SimCard,SIM_NOREADY);\
+ }\
+ }
+#endif
+//#define SIM_Active() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0x0001)
+#define SIM_Active() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON)
+
+#define SIM_Deactive() do {\
+ SIM_SET_OE_BIT();\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);\
+ }while(0)
+
+#ifdef NO_SLIM_DEF
+#define SIM_WaitEvent_Single(_SIMCARD,_flag) \
+ {\
+ kal_uint32 _event_group;\
+ kal_status returnValueOfSIMWaitEvent;\
+ extern void sim_dump_error_line(void);\
+ returnValueOfSIMWaitEvent = returnValueOfSIMWaitEvent;\
+ _SIMCARD.event_state = KAL_TRUE;\
+ _SIMCARD.EvtFlag = _flag;\
+ returnValueOfSIMWaitEvent = kal_retrieve_eg_events(_SIMCARD.event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_dump_error_line();\
+ }
+
+#define SIM_SetEvent_Single(_SIMCARD,_result) \
+ {\
+ kal_status returnValueOfSIMSetEvent;\
+ returnValueOfSIMSetEvent = returnValueOfSIMSetEvent;\
+ _SIMCARD.result = _result;\
+ _SIMCARD.event_state = KAL_FALSE;\
+ returnValueOfSIMSetEvent = kal_set_eg_events(_SIMCARD.event,_SIMCARD.EvtFlag,KAL_OR);\
+ *(volatile kal_uint16 *)SIM_IRQEN = SIM_IRQEN_ALLOFF;\
+ }
+
+#define SIM_WaitEvent_MT6302(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ kal_status returnValue;\
+ extern void sim_dump_error_line(void);\
+ returnValue = returnValue;\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ switch_CB->sim_workingTaskWaiting = KAL_TRUE;\
+ if(KAL_TRUE == _unmaskSIMIntr)\
+ IRQUnmask(hw_cb->mtk_lisrCode);\
+ returnValue= kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ switch_CB->sim_workingTaskWaiting = KAL_FALSE;\
+ sim_dump_error_line();\
+ }
+
+#define SIM_SetEvent_MT6302(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,SIM_EVT_CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_MT6302_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+
+/*********************************************************************************************
+*we move this macro from sim_sw_comm.h to here, since we need a distinguish from dual controllers or MT6302.
+*In dual controllers solution, we need to enable interrupt according to simInterface, but in MT6302 solution, we only need to enable SIM's.
+**********************************************************************************************/
+#define SIM_WaitEvent_MTK(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ extern void sim_dump_error_line(void);\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ if(KAL_TRUE == _unmaskSIMIntr){\
+ IRQUnmask(hw_cb->mtk_lisrCode);\
+ }\
+ kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_dump_error_line();\
+ }
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+#define SIM_SetEvent_MTK(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,SIM_EVT_CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+#endif
+#define SIM_NotifyCARDisHALTEN() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN)
+#define SIM_T0CtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_T0CtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_FlowCtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+#define SIM_FlowCtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+
+#define SIM_DisIntr(_Intr) SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), _Intr)
+
+
+
+#define sim_PDNEnable_Single() DRVPDN_Enable(PDN_SIM)
+#define sim_PDNDisable_Single() DRVPDN_Disable(PDN_SIM)
+
+
+
+
+
+#define SIM_ActiveClk_Single() \
+ {\
+ sim_PDNDisable_Single();\
+ *(volatile kal_uint16 *)SIM_CTRL &= ~SIM_CTRL_HALT;\
+ }
+
+#define SIM_ActiveClk_MT6302(hw_cb) \
+ {\
+ sim_PDNDisable_MT6302(hw_cb);\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_ActiveClk_MT6306(hw_cb) \
+ {\
+ sim_PDNDisable_MT6306(hw_cb);\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_ActiveClk_MTK(hw_cb) \
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_Idle_Single(_level) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable_Single();\
+ }
+
+#define SIM_Idle_MT6302(_level, hw_cb) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable_MT6302(hw_cb);\
+ }
+
+#define SIM_Idle_MT6306(_level, hw_cb) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable_MT6306(hw_cb);\
+ }
+
+#define SIM_Idle_MTK(_level, hw_cb) \
+ {\
+ if(_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ } else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ }
+
+#define SIM_FIFO_GetLev() (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK) & SIM_COUNT_MASK)
+#define SIM_DisTOUTIntr() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_OpenTOUTIntr() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_DisAllIntr() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF)
+
+#ifdef NO_SLIM_DEF
+
+#endif /* End of #ifdef NO_SLIM_DEF */
+#ifdef NoT0CTRL
+#define SIMCmdInit()
+#else /*NoT0CTRL*/
+#define SIMCmdInit() \
+ {\
+ SIM_T0CtrlEnable(); /*SIM_FlowCtrlEnable()*/ \
+ }
+#endif /*NoT0CTRL*/
+
+// macros
+#define SIM_WARM_RST() SIM_SetBits((SIM0_BASE_ADDR_MTK +SIM_CTRL_MTK), SIM_CTRL_WRST)
+
+/*
+ normally, wait event will before set event, but sometimes set event will before wait event.
+ for instance, during wait event, an interrupt is generated and trigger another interrupt before
+ the corresponding wait event.
+*/
+
+#define USIM_CLR_EVENT_Single()\
+ kal_set_eg_events(usim_dcb.event,0,KAL_AND)
+
+#define USIM_CLR_EVENT_Multiple()\
+ kal_set_eg_events(usim_dcb->event,0,KAL_AND)
+
+#define USIM_POW_ON() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON)
+#define USIM_WRST() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), (SIM_CTRL_WRST|SIM_CTRL_SIMON))
+#define USIM_ENABLE_T0() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define USIM_ENABLE_T1() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T1EN)
+#define USIM_DISABLE_T0() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define USIM_DISABLE_T1() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T1EN)
+#define USIM_ENABLE_TXRX_HANSHAKE() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK|SIM_CONF_RXHSK))
+#define USIM_DISABLE_TXRX_HANSHAKE() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TXHSK|SIM_CONF_RXHSK))
+
+//#define USIM_TX_START_T1() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_INS_MTK), 1)
+#define USIM_TX_START_T1() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_COMDCTRL_MTK), SIM_INS_START)
+
+
+#define USIM_IS_IBLOCK(pcb) ((pcb&PCB_I_BIT8)==0)
+#define USIM_IS_RBLOCK(pcb) ((pcb&PCB_R_DEFAULT) == 0x80)
+#define USIM_IS_SBLOCK(pcb) ((pcb&PCB_S_DEFAULT) == PCB_S_DEFAULT)
+#define USIM_IS_RESP(pcb) (pcb&PCB_S_RESP)
+#define USIM_INV_N(n) (n = (n)?0:PCB_I_SEQ)
+
+#define USIM_CLR_FIFO() SIM_FIFO_Flush()
+
+#define USIM_RESET_T1() USIM_DISABLE_T1();USIM_ENABLE_T1();
+#define USIM_ENABLE_TOUT() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN)
+#define USIM_DISABLE_TOUT() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), (SIM_CONF_TOUTEN))
+//#define USIM_CLR_TX_TIDE() SIM_Reg(SIM_TIDE)&=(~SIM_TIDE_TXMASK)
+#define USIM_DMA_RX_TIDE() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TIDE_MTK), 0);
+
+#define SIM_SET_OE_BIT() do {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK +SIM_SIMOE_MODE_MTK), SIM_SIMOE_ENABLE);\
+ MO_Sync();\
+}while(0)
+
+#define SIM_CLR_OE_BIT() do {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK +SIM_SIMOE_MODE_MTK), SIM_SIMOE_ENABLE);\
+ MO_Sync();\
+}while(0)
+
+#define USIM_CAL_TD_COUNT(a,b) \
+ {\
+ if(a & TAMask) b++;\
+ if(a & TBMask) b++;\
+ if(a & TCMask) b++;\
+ }
+
+// generate R-block header
+#define USIM_MAKE_R_BLOCK_Single(e) \
+ {\
+ kal_uint8 pcbInMacroMakeRBlock;\
+ \
+ if(usim_dcb.nr)\
+ pcbInMacroMakeRBlock = (PCB_R_N1|e);\
+ else\
+ pcbInMacroMakeRBlock = (PCB_R_N0|e);\
+ usim_dcb.header_tx[T1_PCB_INDEX] = pcbInMacroMakeRBlock;\
+ usim_dcb.header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb.cmd_state = R_BLOCK_TX;\
+ }
+
+#define USIM_MAKE_S_RESYNC_Single()\
+ {\
+ usim_dcb.header_tx[T1_PCB_INDEX] = PCB_S_DEFAULT;\
+ usim_dcb.header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb.cmd_state = S_BlOCK_REQ_TX;\
+ }
+
+#define USIM_MAKE_R_BLOCK_Multiple(e) \
+ {\
+ kal_uint8 pcb;\
+ \
+ if(usim_dcb->nr)\
+ pcb = (PCB_R_N1|e);\
+ else\
+ pcb = (PCB_R_N0|e);\
+ usim_dcb->header_tx[T1_PCB_INDEX] = pcb;\
+ usim_dcb->header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb->cmd_state = R_BLOCK_TX;\
+ }
+
+#define USIM_MAKE_S_RESYNC_Multiple()\
+ {\
+ usim_dcb->header_tx[T1_PCB_INDEX] = PCB_S_DEFAULT;\
+ usim_dcb->header_tx[T1_LEN_INDEX] = 0;\
+ usim_dcb->cmd_state = S_BlOCK_REQ_TX;\
+ }
+
+
+////////////// temp definitions///////////////
+#define error()
+//////////////////////////////////////////////
+
+/*following is to move control block resource control code to custom files*/
+extern void *sim_get_sim_cb(kal_uint32 tasakInterface);
+extern void *sim_get_usim_cb(kal_uint32 tasakInterface);
+#define GET_USIM_CB(a) sim_get_usim_cb(a)
+#define GET_SIM_CB(a) sim_get_sim_cb(a)
+
+#define IMPLEMENTING_ASSERT ASSERT(0)
+
+#define sim_print(a,b) dbg_print(a,b)
+//#define sim_print(a,b) kal_prompt_trace(MOD_SIM,a,b)
+
+#if defined(LPWR_SLIM)
+#define usim_waitISR_with_spinlock(_spinlockid) \
+ { \
+ while(1) \
+ { \
+ kal_take_spinlock(_spinlockid, KAL_INFINITE_WAIT); \
+ Data_Sync_Barrier(); \
+ if(hw_cb->waitISR == KAL_FALSE) break; \
+ kal_give_spinlock(_spinlockid); \
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for ISR:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, (kal_uint32) hw_cb->waitISR, drv_get_current_time()); \
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr); \
+ SleepDrv_LockSleep(hw_cb->smHandler, hw_cb->sim_task_group); \
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL); \
+ } \
+ }
+#else
+#define usim_waitISR_with_spinlock(_spinlockid) \
+ { \
+ while(1) \
+ { \
+ kal_take_spinlock(_spinlockid, KAL_INFINITE_WAIT); \
+ Data_Sync_Barrier(); \
+ if(hw_cb->waitISR == KAL_FALSE) break; \
+ kal_give_spinlock(_spinlockid); \
+ kal_uint32 log_size = 0; \
+ log_size = kal_sprintf(hw_cb->dbgStr, "[SIM_DRV:%d][%s:%d]task waits for ISR:%d, %x\r\n", hw_cb->simInterface, __FUNCTION__, __LINE__, (kal_uint32) hw_cb->waitISR, drv_get_current_time()); \
+ if (log_size > 0) DRV_ICC_print_str(hw_cb->dbgStr); \
+ kal_sleep_task(KAL_MILLISECS_PER_TICK_REAL + KAL_MILLISECS_PER_TICK_REAL); \
+ } \
+ }
+#endif
+
+
+
+void sim_dump_fifo(sim_HW_cb *hw_cb);
+void sim_storeFifo(sim_HW_cb *hw_cb);
+void sim_printFifo(sim_HW_cb *hw_cb);
+void sim_dump_sim_pins(sim_HW_cb *hw_cb);
+void sim_dump_reg(kal_uint32 trc_num, sim_HW_cb *hw_cb);
+void sim_dump_gpio(sim_HW_cb *hw_cb);
+void sim_dump_eint(sim_HW_cb *hw_cb);
+
+#endif /*__SIM_DRV_SW_FUNCTION_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_drv_SW_struct.h b/mcu/driver/devdrv/usim/inc/sim_drv_SW_struct.h
new file mode 100644
index 0000000..83d9ba4
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_drv_SW_struct.h
@@ -0,0 +1,465 @@
+#ifndef __SIM_DRV_SW_STRUCT_H__
+#define __SIM_DRV_SW_STRUCT_H__
+
+#define SIM_HW_CB_HEAD 0x5A5A5A5A
+#define SIM_HW_CB_TAIL 0xA5A5A5A5
+
+/* For sim hot plug callback function */
+#include "dcl.h"
+//typedef void (*DCL_SIM_PLUG_OUT_CALLBACK)(kal_uint32 simIf);
+//typedef void (*DCL_SIM_PLUG_IN_CALLBACK)(kal_uint32 simIf);
+
+
+
+typedef struct
+{
+ kal_uint32 BURST_SIZE;
+ kal_uint32 MEM_BUS_WIDTH;
+ kal_uint32 DEV_BUS_WIDTH;
+ kal_uint32 channel; // two channels(0 or 1) are avaliable in MT6290
+ //DMA config register address
+ kal_uint32 ADDR_HDMA_HPRGA0Rx; //buf 0 : used for TX or RX
+ kal_uint32 ADDR_HDMA_HPRGA1Rx; //buf 1: used for RX in auto-switch
+ kal_uint32 ADDR_HDMA_HDCTRRx; //config for buf direction, burst size, dev bus width, and mem bus width
+ kal_uint32 ADDR_HDMA_HDC0Rx; //buf 0 config for transfer size and start
+ kal_uint32 ADDR_HDMA_HDC1Rx; //buf 1 config for transfer size and start
+} Sim_HDMA_struct;
+
+
+typedef struct
+{
+ kal_uint32 head;
+ /*
+ Here defines MTK related HW information of this logical interface, these values are defined as constant in old driver.
+ Now we make it variable.
+ */
+ kal_uint32 mtk_baseAddr;
+ kal_uint32 mtk_lisrCode;
+ /*
+ in multiple SIM drivers, simInterface is used in all most all functions, we need record this information.
+ */
+ kal_uint32 simInterface; // The logical number. This value now can be 0~n, not limted as 0~1 before. We can assume it less than 2 now
+ kal_uint32 MT6302ChipNo; // record which MT6302 switch used for this card
+ kal_uint32 MT6302PortNo; // record which port of MT6302 is used for this card
+ void *MT6302PeerInterfaceCb; // MT6302 need peer's information, so we have to maintain a way to find its peer
+ kal_uint32 simSwitchChipNo;
+ kal_uint32 simSwitchPortNo;
+ void *simSwitchPeerInterfaceCb;
+ void *simSwitchPeerInterfaceCb1;
+ void *simSwitchPeerInterfaceCb2;
+ DCL_SIM_PLUG_IN_CALLBACK simHotPlugIn;
+ DCL_SIM_PLUG_OUT_CALLBACK simHotPlugOut;
+ kal_uint32 debounceTime; // hot swap EINT debounce time
+ kal_uint32 tail;
+ kal_bool polarity; // hot swap EINT poarity
+ kal_bool IsCardRemove;
+ kal_uint8 smHandler;
+ kal_bool forceOn26M;
+ kal_char dbgStr[256];
+ kal_char hisrDbgStr[256];
+ volatile kal_bool waitISR;
+ volatile kal_bool must_not_enable_sleep;
+ volatile kal_spinlockid spinlockid;
+ volatile kal_spinlockid spinlockid_sim_hot_swap;
+ volatile kal_uint8 waitGptISR_MT6306;
+ volatile kal_bool needStopGptISR;
+ kal_bool SlowClock;
+ kal_bool doNotStopSimClock;
+ kal_uint32 issueCardStatus;
+#if defined(SIM_DRV_4_33MHZ_SCLK)
+ kal_bool canUse_4_33_SCLK;
+#endif
+ kal_bool PollTimerStart;
+ kal_bool PollTimerEnd;
+ kal_bool PollTimerPluggedOut;
+ kal_affinity_group sim_task_group;
+ kal_char l4cDbgStr[256];
+ kal_uint32 sim_detect_pin_num;
+#if defined(SIM_DRV_DYNAMIC_GET_GPIO_NUM)
+ kal_uint32 gpioCardDetPin;
+#endif
+#if defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_bool no_md_eint_settings;
+#endif
+} sim_HW_cb;
+
+typedef struct
+{
+ kal_uint32* ptr;
+ kal_uint32 size;
+} sim_nvram_param_struct;
+
+typedef struct
+{
+ sim_power_enum power;
+ sim_speed_enum speed;
+ sim_clock_stop_enum clock_stop;
+ sim_protocol_app_enum app_proto;
+ sim_protocol_phy_enum phy_proto;
+ kal_bool T0_support; // if T0 is supported
+ kal_bool T1_support; // if T1 is supported
+ kal_uint8 hist_index; // index to the historical char of ATR
+ kal_uint8 *ATR;
+ /*following information is necessary for SIM task for UICC identification*/
+ kal_bool TAiExist; //if the first TA for T=15 is existed
+ kal_uint8 ATR_length; // length to the ATR_data
+ kal_bool isSW6263; // query if status word 0x62xx 0x63xx happen
+ kal_uint8 TB15; // query if support ic usb
+ kal_bool hasPowerClass;
+ kal_uint8 PowerClass;
+ kal_bool SupportExtendedLength;
+ kal_uint8 sim_tray_status;
+ kal_uint8 sim_result;
+} sim_info_struct;
+
+#if defined SIM_DRV_IC_USB
+typedef struct
+{
+ kal_uint8 *txData;
+ kal_uint16 txSize;
+ kal_uint8 *result;
+ kal_uint16 *rcvSize;
+ kal_uint16 *sw;
+} sim_icusb_T0cmd;
+
+typedef struct
+{
+ kal_uint8 sif;
+ kal_uint8 pcb;
+ kal_uint16 cp;
+ kal_uint16 len;
+ kal_uint8 *apdubuf;
+} sim_icusb_message;
+#endif
+
+
+typedef struct
+{
+ kal_uint8 State;
+ kal_uint8 Data_format; /*SIM_direct,SIM_indirect*/
+ kal_uint8 Power; /*SIM_3V,SIM_5V*/
+ kal_uint8 recData[40]; /*PTS or ATR data*/
+ kal_bool recDataErr;
+ kal_uint8 result; /* for ATR, command, RST */
+ sim_env SIM_ENV;
+#ifndef SIM_ADDDMA
+ kal_uint8 *txbuffer; /* only used for no DMA */
+ kal_uint16 txsize; /* only used for no DMA */
+ kal_uint16 txindex; /* only used for no DMA */
+ kal_uint8 *rxbuffer; /* only used for no DMA */
+#ifdef NoT0CTRL
+ kal_uint8 INS;
+ kal_uint8 SW1;
+ kal_uint8 SW2;
+ kal_uint16 recsize;
+#endif /*NoT0CTRL*/
+#endif /*SIM_ADDDMA*/
+ /*add for clock stop mode*/
+ kal_uint8 cmdState; /* only used for no T0CTRL, and for clock stop */
+ kal_uint8 Speed; /*Speed372,Speed64,Speed32*/
+ kal_bool clkStop; /*Clok Stop Enable*/
+ kal_bool clkStopLevel; /*Clok Stop level*/
+ kal_bool reject_set_event;
+ kal_bool event_state;
+ kal_uint8 initialPower;
+ sim_card_speed_type sim_card_speed;
+ kal_hisrid hisr; /*SIM HISR*/
+ kal_eventgrpid event; /*SIM Event*/
+
+ sim_protocol_app_enum app_proto;
+ kal_bool timeout;
+ usim_cmd_case_enum cmd_case;
+ kal_bool is_err; // sim command has error once.
+ kal_bool get9000WhenSelect;
+ /*
+ following variables are get from global variables for 2 SIM projects.
+ We won't use these in single SIM driver, but we need to define the power set.
+ */
+ kal_uint8 TOUT_Factor;
+ kal_uint16 Fi;
+ kal_uint16 etu_of_1860;
+ kal_uint16 etu_of_700;
+ kal_uint8 reset_index;
+#ifdef SIM_ADDDMA
+ Sim_HDMA_struct dma_config;
+#endif
+ kal_bool TS_HSK_ENABLE;
+ kal_bool sim_ATR_fail;
+ kal_bool PTS_check; /*if false use default value: F=372, D=1*/
+ kal_uint8 PTS_data[4];
+ kal_uint8 sim_nullByteIssueNullCount;
+ kal_uint32 sim_nullByteIssuenonNullCount;
+ kal_bool keepAtrFatal;
+ kal_uint16 recDataLen; /* for command, ATR process */
+ kal_uint32 EvtFlag;
+ kal_uint32 TOUTValue;
+ kal_uint32 sim_nullByteIssueGPT;
+ /*
+ magic1 is an increasing counter, increases when 1) start new command, 2)get SIM timeout, 3)get T0 end
+ for case 2 and 3, it means that one of the ends of SIM commands has appeared.
+ */
+ volatile kal_uint32 simMagic1;
+ /*
+ magic2 is used to compared with magic1 every time GPT expires. It is set to magic1 in the start of a new command,
+ if they were compared equally in GPT timer, we know that we are still waiting for SIM controller's event.
+ */
+ volatile kal_uint32 simMagic2;
+ kal_uint32 gpt_handle;
+ kal_bool clkstoping;
+ sim_power_enum power_class; // supported power class indicated at ATR [patch from 6280 sim driver]
+ kal_bool TC2Present;
+ kal_uint32 previous_state;
+ kal_uint32 atr_count;
+#if defined(SIM_DRV_IC_USB)
+ kal_bool isIcUsb; // query if support ic usb
+ kal_bool isIcUsbRecPPS; // query if support ic usb PPS resp received
+ kal_uint32 uart_sim_ccci_handle;
+ usim_icusb_state_enum icusb_state;
+ sim_icusb_T0cmd sim_icusb_T0cmd;
+ kal_uint8 icusb_recData[40]; /*PTS or ATR data*/
+ kal_uint32 waitingTime; // waitingTime
+ kal_bool forceISO;
+#endif
+ kal_bool isPrefer3V; // prefer3v
+ kal_uint8 TB15; // query if support ic usb
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_bool poll_sim_2s;
+#endif
+ kal_uint32 t_debug[6];
+#if defined(__SIM_ACTIVATION_V2__)
+ kal_uint32 gpt_handle_for_SIM_activation;
+ kal_uint32 gpio_handle_for_SIO;
+ kal_bool activation_v2;
+#endif
+ kal_uint32 mod_id;
+ kal_uint32 mod_extq_cap;
+ kal_uint32 cmd_duration_sum;
+ kal_uint32 cmd_duration_count;
+ kal_uint32 status_duration_sum;
+ kal_uint32 status_duration_count;
+ kal_uint8 bypass6263;
+ kal_bool EF_ICCID_Selected;
+} Sim_Card;
+
+
+
+typedef struct
+{
+ usim_dir_enum dir;
+
+} ATR_struct;
+
+// specify the supported attributes of the UICC
+typedef struct
+{
+ usim_power_enum power;
+ usim_protocol_enum protocol;
+ usim_clock_stop_enum clock_stop;
+ usim_speed_enum speed;
+} usim_info_struct;
+
+typedef struct
+{
+ // before reset
+ kal_bool high_speed_en; // control if high speed is enalbed
+ usim_power_enum power_in; // expected power class input form application layer
+ // after reset
+ usim_clock_stop_enum clock_stop_type;
+} usim_config_struct;
+
+typedef struct
+{
+ kal_eventgrpid event;
+ usim_power_enum power; // power class used
+ usim_status_enum status;
+ usim_speed_enum speed; // speed selected
+ // state control
+ volatile usim_main_state_enum main_state;
+ volatile usim_status_enum ev_status;
+ // informations
+ usim_dir_enum dir; // convention of character frame
+ sim_protocol_app_enum app_proto; // application protocol (USIM, SIM)
+ sim_protocol_phy_enum phy_proto; // protocol type selected (physical layer)
+
+ // ATR info
+ kal_uint8 ATR_data[36]; // used to store all ATR data string
+ kal_uint8 ATR_index; // index to the ATR_data
+ kal_uint8 header_tx[4], header_tx_bak[4]; // header_tx_bak used to backup the previous command
+ kal_uint8 header_rx[4];
+ kal_uint8 dma_buffer[USIM_DMA_MAX_SIZE];
+ kal_uint8 retry;
+
+ sim_env sim_env; // the voltage which MS can supply
+ usim_power_enum power_in; // expected power class input form application layer
+ usim_power_enum power_class; // supported power class indicated at ATR
+ kal_bool clock_stop_en; // clock_stop is enabled or not
+ // usim_protocol_enum T;
+ usim_speed_enum card_speed; // TA1, max speed card can support
+ kal_bool high_speed_en; // control if high speed is enalbed
+ usim_clock_stop_enum clock_stop_type;
+ kal_bool present;
+ usim_reset_type_enum reset_mode; // specific or negotiable mode
+ kal_bool warm_rst; // KAL_TRUE: it's a warm reset, KAL_FALSE: a cold reset
+ kal_bool T0_support; // if T0 is supported
+ kal_bool T1_support; // if T1 is supported
+ kal_uint8 Di;
+
+ // T=1
+ kal_uint8 ns; // sequence # of sending
+ kal_uint8 nr; // sequence # of receiving
+ kal_uint8 ifsd; // information size of interface device
+ kal_uint8 ifsc; // information size of card
+ usim_cmd_state_enum cmd_state;
+ usim_cmd_state_enum cmd_state_bak;
+ kal_bool abort;
+ kal_bool wtx; // waiting time extension
+ kal_bool resync;
+ kal_bool send_prev; // send the previous block
+ kal_bool tx_chain;
+ kal_bool rx_chain;
+ kal_uint8 *tx_buf;
+ kal_uint8 *rx_buf;
+ kal_uint8 sw[2]; // used to contain SW1 and SW2
+ kal_uint8 wtx_m; // multiplier of BWT
+
+ // others
+ kal_bool ts_hsk_en; // enable handshake at TS byte (error signal and char repetition)
+
+#ifdef SIM_ADDDMA
+ Sim_HDMA_struct dma_config;
+#endif
+ kal_uint8 hist_index; // index to the historical characters
+ usim_cmd_case_enum cmd_case;
+ sim_protocol_phy_enum perfer_phy_proto; // protocol type selected (physical layer)
+ /*SIM task need following information for UICC identification*/
+ kal_bool TAiExist; //if the first TA for T=15 is existed
+#if defined(USIM_DEBUG)
+ kal_int32 sline[INDEX_COUNT]; // set event at the which line in usim_drv.c
+ kal_uint32 sindex; // index to the sline[4]
+ kal_int32 wline[INDEX_COUNT]; // wait event at the which line in usim_drv.c
+ kal_uint32 windex; // index to the wline
+#endif
+ kal_uint16 tx_size;
+ kal_uint16 rx_size;
+ kal_uint16 tx_index;
+ kal_uint16 rx_index;
+
+ kal_uint16 Fi;
+ kal_uint16 etu_of_1860;
+ kal_uint16 etu_of_700;
+ kal_uint32 gpt_handle;
+
+ // time out control
+ kal_uint32 WWT; // work waiting time (T0)
+ kal_uint32 CWT; // character waiting time in etu(T1)
+ kal_uint32 BWT; // blcok waiting time in etu(T1)
+ kal_uint32 timeout; // etu
+ kal_uint32 ev_flag;
+ kal_hisrid hisr;
+ kal_uint32 int_status;
+
+ /*
+ following variables are get from global variables for 2 SIM projects.
+ We won't use these in single SIM driver, but we need to define the power set.
+ */
+ kal_taskid ownerTask; // the task that own this control block
+
+ kal_uint32 processingState; //to to reentry check
+ kal_bool isSW6263; // query if status word 0x62xx 0x63xx happen
+ kal_uint32 previous_state;
+ kal_uint32 atr_count;
+#if defined (SIM_AUTO_TEST)
+ kal_bool auto_test; // auto test for MTK internal
+#endif
+ kal_uint32 intsta[10];
+ kal_uint32 intcnt;
+#if defined(SIM_DRV_IC_USB)
+ kal_bool isIcUsb; // query if support ic usb
+ kal_bool isIcUsbRecPPS; // query if support ic usb PPS resp received
+ kal_uint32 uart_sim_ccci_handle;
+ usim_icusb_state_enum icusb_state;
+ kal_uint8 icusb_ATR_data[36]; // used to store all ATR data string
+ kal_uint8 icusb_ATR_index; // index to the ATR_data
+ kal_uint32 waitingTime; // waitingTime
+ kal_bool forceISO;
+#endif
+ kal_bool isPrefer3V; // prefer3v
+ kal_uint8 TB15; // query if support ic usb
+ kal_uint8 TA2;
+#if defined(__SIM_HOT_SWAP_POLL_TIMER__) && defined(__SIM_HOT_SWAP_SUPPORT__)
+ kal_bool poll_sim_2s;
+#endif
+#if defined(__SIM_ACTIVATION_V2__)
+ kal_uint32 gpt_handle_for_SIM_activation;
+ kal_uint32 gpio_handle_for_SIO;
+ kal_bool activation_v2;
+#endif
+#if defined(SIM_DRV_RETRY_3V_WHEN_CMD_FAIL)
+ kal_bool retry_3v_prefer;
+#endif
+#if defined(SIM_DRV_RETRY_SPECIAL_MODE_WHEN_CMD_FAIL)
+ kal_bool retry_special_mode_prefer;
+#endif
+ kal_bool hasPowerClass;
+ kal_uint8 PowerClass;
+ kal_bool stopSimClkInEndOfAction;
+ kal_bool Support_Extended_Length;
+ kal_bool simInitialized;
+ volatile usim_status_enum error_status;
+} usim_dcb_struct;
+
+extern usim_dcb_struct usim_dcb;
+
+
+typedef struct
+{
+ sim_msgTag tag;
+ kal_uint32 event;
+ kal_uint32 data1;
+ kal_uint32 data2;
+ kal_uint32 time;
+} sim_msg;
+
+typedef usim_status_enum(*SIM_API_RESET)(sim_power_enum ExpectVolt, sim_power_enum *ResultVolt, kal_bool warm, sim_HW_cb *hw_cb);
+typedef sim_status(*SIM_API_CMD)(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_PWROFF)(sim_HW_cb *hw_cb);
+typedef void (*SIM_API_CARDINFO)(sim_info_struct *info, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_ENHANCED_SPEED)(kal_bool enable, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_ENHANCED_SELECT_PHY)(sim_protocol_phy_enum T, sim_HW_cb *hw_cb);
+typedef kal_bool(*SIM_API_SET_CLKSTOP)(sim_clock_stop_enum mode, sim_HW_cb *hw_cb);
+typedef void (*SIM_API_EOC)(sim_HW_cb *hw_cb);
+typedef void (*SIM_API_MSG)(kal_uint32 tag, kal_uint32 event, kal_uint32 data1, kal_uint32 data2);
+typedef void (*SIM_API_TOUT_TEST)(kal_uint32 toutValue, sim_HW_cb *hw_cb);
+
+
+typedef struct
+{
+ SIM_API_RESET reset;
+ SIM_API_CMD command;
+ SIM_API_PWROFF powerOff;
+ SIM_API_CARDINFO getCardInfo;
+ SIM_API_ENHANCED_SPEED enableEnhancedSpeed;
+ SIM_API_ENHANCED_SELECT_PHY selectPreferPhyLayer;
+ SIM_API_SET_CLKSTOP setClockStopMode;
+ SIM_API_EOC EOC;/*use this to hook necessary action before return to SIM task, this is called by adaption layer, not SIM task*/
+ SIM_API_MSG addMessage;
+ SIM_API_TOUT_TEST toutTest;
+} sim_ctrlDriver;
+
+#define USIM_LP_DISABLE 0x40
+#define USIM_LP_ENABLE 0x80
+#define USIM_LP_MASK_NORMAL_VSIM_CURRENT 0x01
+#define USIM_LP_MASK_REDUCE_VSIM_CURRENT 0x02
+#define USIM_LP_MASK_NORMAL_26M 0x04
+#define USIM_LP_MASK_FORCE_ON_26M 0x08
+#define USIM_LP_MASK_START_SCLK 0x10
+#define USIM_LP_MASK_STOP_SCLK 0x20
+
+#if defined(__LOCK_VSIM__)
+typedef struct
+{
+ kal_uint8 lock_vsim;
+} sim_nfc_communication;
+#endif // #if defined(__LOCK_VSIM__)
+
+#endif /*__SIM_DRV_SW_STRUCT_H__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_hw.h b/mcu/driver/devdrv/usim/inc/sim_hw.h
new file mode 100644
index 0000000..930554f
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_hw.h
@@ -0,0 +1,556 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for SIM driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+/*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/
+#include "sim_drv_HW_reg_MTK.h"
+#else
+
+/*RHR*/
+#include "reg_base.h"
+/*RHR*/
+
+#ifndef _SIM_HW_H
+#define _SIM_HW_H
+
+
+//#if ( (!defined(MT6208)) && (!defined(FPGA)) && (!defined(MT6205)) && (!defined(MT6205B)) && (!defined(MT6218)) )
+#if !defined(DRV_SIM_REG_6208_SERIES) && !defined(DRV_SIM_REG_6205B_SERIES)
+/*MT6218B || MT6219 || MT6217 || MT6226 || MT6227 || MT6228 || MT6229*/
+
+#ifdef SIM_NAMING_FROM_0_ADDRESS
+
+ #ifdef SIM_base
+ #undef SIM_base
+ #endif
+ #define SIM_base SIM0_base
+
+ #ifdef SIM2_base
+ #undef SIM2_base
+ #endif
+ #define SIM2_base SIM1_base
+
+#endif //SIM_NAMING_FROM_0_ADDRESS
+
+#ifdef SIM_DVT_ON_SIM2
+ #undef SIM_base
+ #define SIM_base SIM2_base
+#endif
+
+#define ACK_NULL_CHAR 0x60
+
+#define SIM_CTRL (SIM_base+0x0)
+#define SIM_CONF (SIM_base+0x4)
+#define SIM_BRR (SIM_base+0x8)
+#define SIM_IRQEN (SIM_base+0x10)
+#define SIM_STS (SIM_base+0x14)
+
+#define SIM_RETRY (SIM_base+0x20)
+#define SIM_TIDE (SIM_base+0x24)
+
+#define SIM_DATA (SIM_base+0x30)
+#define SIM_COUNT (SIM_base+0x34)
+
+#define SIM_ATIME (SIM_base+0x40)
+#define SIM_DTIME (SIM_base+0x44)
+#define SIM_TOUT (SIM_base+0x48)
+
+#define SIM_INS (SIM_base+0x60)
+#define SIM_IMP3 (SIM_base+0x64)
+#define SIM_SW1 (SIM_base+0x68)
+#define SIM_SW2 (SIM_base+0x6c)
+#define SIM_REG_STATUS (SIM_base+0x74)
+
+//SIM_CTRL
+#define SIM_CTRL_SIMON 0x0001
+#define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+#define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+
+//SIM_CONF
+#define SIM_CONF_RXHSK 0x0001
+#define SIM_CONF_TXHSK 0x0002
+#define SIM_CONF_CLKPO 0x0004
+#define SIM_CONF_SINV 0x0008
+#define SIM_CONF_SDIR 0x0010
+#define SIM_CONF_ODDPARITY 0x0020
+#define SIM_CONF_SIMSEL 0x0040
+#define SIM_CONF_TOUTEN 0x0080
+#define SIM_CONF_T0EN 0x0200
+#define SIM_CONF_HFEN 0x0400
+#define SIM_CONF_T1EN 0x0100
+
+#define SIM_CONF_Direct 0x0000
+#define SIM_CONF_InDirect 0x0038
+
+//SIM_BRR
+#define SIM_BRR_CLKMSK 0x0003
+#define SIM_BRR_CLK_Div2 0x0000
+#define SIM_BRR_CLK_Div4 0x0001
+#define SIM_BRR_CLK_Div8 0x0002
+#define SIM_BRR_CLK_Div12 0x0003
+
+#define SIM_BRR_ETUMSK 0x07FC
+#define SIM_BRR_BAUDMSK 0x000C
+//#if ( (defined(MT6218B)) || (defined(MT6219)))
+#if defined(DRV_SIM_REG_BAUD_6218B_SERIES)
+ #define SIM_BRR_BAUD_Div372 (0x16<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (0x03<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (0x01<<2) //F=512, D=16
+#else /*!Mt6218B,MT6219*/
+ #define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16
+ #define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32
+#endif /*MT6218B,MT6219*/
+
+//SIM_IRQEN
+#define SIM_IRQEN_TX 0x0001
+#define SIM_IRQEN_RX 0x0002
+#define SIM_IRQEN_OV 0x0004
+#define SIM_IRQEN_TOUT 0x0008
+#define SIM_IRQEN_TXERR 0x0010
+#define SIM_IRQEN_NATR 0x0020
+#define SIM_IRQEN_SIMOFF 0x0040
+#define SIM_IRQEN_T0END 0x0080
+#define SIM_IRQEN_RXERR 0x0100
+
+#define SIM_IRQEN_ALL 0x01bf
+#define SIM_IRQEN_ALLOFF 0x0000
+/* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+#define SIM_IRQEN_Normal 0x013e
+/*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/
+#define SIM_IRQEN_CMDNormal 0x019e
+/*#define SIM_IRQEN_CMDNormal 0x019c*/
+#define SIM_IRQEN_CMDDMANormal 0x019c
+#define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR)
+#define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR)
+#define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \
+ SIM_STS_OV|SIM_STS_TOUT)
+#define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX)
+#define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END)
+
+//SIM_STS
+#define SIM_STS_TX 0x0001
+#define SIM_STS_RX 0x0002
+#define SIM_STS_OV 0x0004
+#define SIM_STS_TOUT 0x0008
+#define SIM_STS_TXERR 0x0010
+#define SIM_STS_NATR 0x0020
+#define SIM_STS_SIMOFF 0x0040
+#define SIM_STS_T0END 0x0080
+#define SIM_STS_RXERR 0x0100
+#define SIM_STS_T1END 0x0200
+#define SIM_STS_EDCERR 0x0400
+
+//SIM_TOUT
+#define SIM_TOUT_MSK 0x3fff
+
+//SIM_RETRY
+#define SIM_RETRY_RXMASK 0x0007
+#define SIM_RETRY_TXMASK 0x0700
+
+//SIM_TIDE
+#define SIM_TIDE_RXMASK 0x000f
+#define SIM_TIDE_TXMASK 0x0f00
+
+//SIM_COUNT
+#define SIM_COUNT_MASK 0x000f
+
+//SIM_INS
+#define SIM_INS_MASK 0x00ff
+#define SIM_INS_INSD 0x0100
+
+//SIM_IMP3
+#define SIM_IMP3_MASK 0x01ff
+
+// SIM_STATUS
+#define SIM_STATUS_EDC 0x40
+#define SIM_STATUS_ACK 0x20
+#define SIM_STATUS_NACK 0x10
+#define SIM_STATUS_IDLE 0x01
+#define SIM_STATUS_INS 0x02
+#define SIM_STATUS_SW1 0x04
+#define SIM_STATUS_SW2 0x08
+
+#define SIM_TX_DELAY_LEN 0x4
+#define SIM_TX_DELAY_LOOP 4000
+#endif /*MT6218B*/
+
+//#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) )
+#if defined(DRV_SIM_REG_6205B_SERIES)
+ #define ACK_NULL_CHAR 0x60
+
+ #define SIM_CTRL (SIM_base+0x0)
+ #define SIM_CONF (SIM_base+0x4)
+ #define SIM_BRR (SIM_base+0x8)
+ #define SIM_IRQEN (SIM_base+0xc)
+ #define SIM_STS (SIM_base+0x10)
+ #define SIM_DATA (SIM_base+0x14)
+ #define SIM_TOUT (SIM_base+0x18)
+ #define SIM_RETRY (SIM_base+0x1c)
+ #define SIM_TIDE (SIM_base+0x20)
+ #define SIM_COUNT (SIM_base+0x24)
+ #define SIM_ATIME (SIM_base+0x28)
+ #define SIM_DTIME (SIM_base+0x2C)
+ #define SIM_INS (SIM_base+0x30)
+ #define SIM_IMP3 (SIM_base+0x34)
+ #define SIM_SW1 (SIM_base+0x38)
+ #define SIM_SW2 (SIM_base+0x3c)
+
+
+ //SIM_CTRL
+ #define SIM_CTRL_SIMON 0x0001
+ #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+ #define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+
+ //SIM_CONF
+ #define SIM_CONF_RXHSK 0x0001
+ #define SIM_CONF_TXHSK 0x0002
+ #define SIM_CONF_CLKPO 0x0004
+ #define SIM_CONF_SINV 0x0008
+ #define SIM_CONF_SDIR 0x0010
+ #define SIM_CONF_ODDPARITY 0x0020
+ #define SIM_CONF_SIMSEL 0x0040
+ #define SIM_CONF_TOUTEN 0x0080
+ #define SIM_CONF_HALTEN 0x0100
+ #define SIM_CONF_T0EN 0x0200
+ #define SIM_CONF_HFEN 0x0400
+
+ #define SIM_CONF_Direct 0x0000
+ #define SIM_CONF_InDirect 0x0038
+
+ //SIM_BRR
+ #define SIM_BRR_CLKMSK 0x0003
+ #define SIM_BRR_CLK_Div2 0x0000
+ #define SIM_BRR_CLK_Div4 0x0001
+ #define SIM_BRR_CLK_Div8 0x0002
+ #define SIM_BRR_CLK_Div12 0x0003
+
+ #define SIM_BRR_ETUMSK 0x07FC
+ #define SIM_BRR_BAUDMSK 0x000C
+ //#ifdef MT6205B
+ #if defined(DRV_SIM_REG_BAUD_6205B)
+ #define SIM_BRR_BAUD_Div372 0x000c //F=372, D=1
+ #define SIM_BRR_BAUD_Div368 0x0000 //F=368, D=1
+ #else /*!MT6205B*/
+ #define SIM_BRR_BAUD_Div372 0x0000 //F=372, D=1
+ #endif /*MT6205B*/
+ #define SIM_BRR_BAUD_Div64 0x0004 //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 0x0008 //F=512, D=16
+
+ //SIM_IRQEN
+ #define SIM_IRQEN_TX 0x0001
+ #define SIM_IRQEN_RX 0x0002
+ #define SIM_IRQEN_OV 0x0004
+ #define SIM_IRQEN_TOUT 0x0008
+ #define SIM_IRQEN_TXERR 0x0010
+ #define SIM_IRQEN_NATR 0x0020
+ #define SIM_IRQEN_SIMOFF 0x0040
+ #define SIM_IRQEN_T0END 0x0080
+ #define SIM_IRQEN_RXERR 0x0100
+
+ #define SIM_IRQEN_ALL 0x01bf
+ #define SIM_IRQEN_ALLOFF 0x0000
+ /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+ #define SIM_IRQEN_Normal 0x013e
+ /*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/
+ #define SIM_IRQEN_CMDNormal 0x019e
+ /*#define SIM_IRQEN_CMDNormal 0x019c*/
+ #define SIM_IRQEN_CMDDMANormal 0x019c
+
+ //SIM_STS
+ #define SIM_STS_TX 0x0001
+ #define SIM_STS_RX 0x0002
+ #define SIM_STS_OV 0x0004
+ #define SIM_STS_TOUT 0x0008
+ #define SIM_STS_TXERR 0x0010
+ #define SIM_STS_NATR 0x0020
+ #define SIM_STS_SIMOFF 0x0040
+ #define SIM_STS_T0END 0x0080
+ #define SIM_STS_RXERR 0x0100
+
+ //SIM_TOUT
+ #define SIM_TOUT_MSK 0x3fff
+
+ //SIM_RETRY
+ #define SIM_RETRY_RXMASK 0x0007
+ #define SIM_RETRY_TXMASK 0x0700
+
+ //SIM_TIDE
+ #define SIM_TIDE_RXMASK 0x000f
+ #define SIM_TIDE_TXMASK 0x0f00
+
+ //SIM_COUNT
+ #define SIM_COUNT_MASK 0x000f
+
+ //SIM_INS
+ #define SIM_INS_MASK 0x00ff
+ #define SIM_INS_INSD 0x0100
+
+ //SIM_IMP3
+ #define SIM_IMP3_MASK 0x01ff
+#endif /*(MT6205,MT6205B,MT6218)*/
+
+//#if ( (defined(MT6208)) || (defined(FPGA)) )
+#if defined(DRV_SIM_MT6208_SERIES)
+ #define MAX_FIFO_SIZE 31
+ #define ACK_NULL_CHAR 0x60
+
+ #define LISR_COMPLETE 0x80
+
+ #define SIM_CTRL (SIM_base+0x0)
+ #define SIM_CONF (SIM_base+0x4)
+ #define SIM_BRR (SIM_base+0x8)
+ #define SIM_IRQEN (SIM_base+0xc)
+ #define SIM_STS (SIM_base+0x10)
+ #define SIM_DATA (SIM_base+0x14)
+ #define SIM_TOUT (SIM_base+0x18)
+ #define SIM_RETRY (SIM_base+0x1c)
+ #define SIM_TIDE (SIM_base+0x20)
+ #define SIM_COUNT (SIM_base+0x24)
+ #define SIM_ATIME (SIM_base+0x28)
+ #define SIM_DTIME (SIM_base+0x2C)
+
+
+ //SIM_CTRL
+ #define SIM_CTRL_SIMON 0x0001
+ #define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+
+ //SIM_CONF
+ #define SIM_CONF_RXHSK 0x0001
+ #define SIM_CONF_TXHSK 0x0002
+ #define SIM_CONF_CLKPO 0x0004
+ #define SIM_CONF_SINV 0x0008
+ #define SIM_CONF_SDIR 0x0010
+ #define SIM_CONF_ODDPARITY 0x0020
+ #define SIM_CONF_SIMSEL 0x0040
+ #define SIM_CONF_TOUTEN 0x0080
+
+ #define SIM_CONF_Direct 0x0000
+ #define SIM_CONF_InDirect 0x0038
+
+ //SIM_BRR
+ #define SIM_BRR_CLKMSK 0x0003
+ #define SIM_BRR_CLK_Div2 0x0000
+ #define SIM_BRR_CLK_Div4 0x0001
+ #define SIM_BRR_CLK_Div8 0x0002
+ #define SIM_BRR_CLK_Div12 0x0003
+
+ #define SIM_BRR_ETUMSK 0x07FC
+ #define SIM_BRR_BAUDMSK 0x000C
+ #define SIM_BRR_BAUD_Div372 0x0000 //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 0x0004 //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 0x0008 //F=512, D=16
+
+ //SIM_IRQEN
+ #define SIM_IRQEN_TX 0x0001
+ #define SIM_IRQEN_RX 0x0002
+ #define SIM_IRQEN_OV 0x0004
+ #define SIM_IRQEN_TOUT 0x0008
+ #define SIM_IRQEN_TXERR 0x0010
+ #define SIM_IRQEN_NATR 0x0020
+ #define SIM_IRQEN_SIMOFF 0x0040
+
+ #define SIM_IRQEN_ALL 0x01bf
+ #define SIM_IRQEN_ALLOFF 0x0000
+ /* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+ #define SIM_IRQEN_Normal 0x03e
+
+ //SIM_STS
+
+ #define SIM_STS_TX 0x0001
+ #define SIM_STS_RX 0x0002
+ #define SIM_STS_OV 0x0004
+ #define SIM_STS_TOUT 0x0008
+ #define SIM_STS_TXERR 0x0010
+ #define SIM_STS_NATR 0x0020
+ #define SIM_STS_SIMOFF 0x0040
+
+ //SIM_DATA
+ #define SIM_DATA_DATAMSK 0x00ff
+ #define SIM_DATA_PARITY 0x0100
+
+ //SIM_TOUT
+ #define SIM_TOUT_MSK 0x3fff
+
+ //SIM_RETRY
+ #define SIM_RETRY_RXMASK 0x0007
+ #define SIM_RETRY_TXMASK 0x0700
+
+ //SIM_TIDE
+ #define SIM_TIDE_RXMASK 0x001f
+ #define SIM_TIDE_TXMASK 0x1f00
+
+ //SIM_TXCNT
+ #define SIM_COUNT_MASK 0x001f
+#endif /*(MT6208,FPGA)*/
+
+#endif /*_SIM_HW_H*/
+
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_hw_mtk.h b/mcu/driver/devdrv/usim/inc/sim_hw_mtk.h
new file mode 100644
index 0000000..7ed70f2
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_hw_mtk.h
@@ -0,0 +1,320 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_hw_mtk.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for MTK SIM driver in multiple sim interface solution code.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "drv_features.h"
+#include "reg_base.h"
+/*RHR*/
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+/*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/
+#include "sim_drv_HW_reg_MTK.h"
+#else
+#ifndef _SIM_HW_H
+#define _SIM_HW_H
+
+//#if ( (!defined(MT6208)) && (!defined(FPGA)) && (!defined(MT6205)) && (!defined(MT6205B)) && (!defined(MT6218)) )
+#if !defined(DRV_SIM_REG_6208_SERIES) && !defined(DRV_SIM_REG_6205B_SERIES)
+/*MT6218B || MT6219 || MT6217 || MT6226 || MT6227 || MT6228 || MT6229*/
+
+#ifdef SIM_NAMING_FROM_0_ADDRESS
+
+ #ifdef SIM_base
+ #undef SIM_base
+ #endif
+ #define SIM_base SIM0_base
+
+ #ifdef SIM2_base
+ #undef SIM2_base
+ #endif
+ #define SIM2_base SIM1_base
+
+#endif //SIM_NAMING_FROM_0_ADDRESS
+
+#define ACK_NULL_CHAR 0x60
+
+#define SIM_CTRL (SIM_base+0x0)
+#define SIM_CONF (SIM_base+0x4)
+#define SIM_BRR (SIM_base+0x8)
+#define SIM_IRQEN (SIM_base+0x10)
+#define SIM_STS (SIM_base+0x14)
+
+#define SIM_RETRY (SIM_base+0x20)
+#define SIM_TIDE (SIM_base+0x24)
+
+#define SIM_DATA (SIM_base+0x30)
+#define SIM_COUNT (SIM_base+0x34)
+
+#define SIM_ATIME (SIM_base+0x40)
+#define SIM_DTIME (SIM_base+0x44)
+#define SIM_TOUT (SIM_base+0x48)
+
+#define SIM_INS (SIM_base+0x60)
+#define SIM_IMP3 (SIM_base+0x64)
+#define SIM_SW1 (SIM_base+0x68)
+#define SIM_SW2 (SIM_base+0x6c)
+#define SIM_REG_STATUS (SIM_base+0x74)
+
+#define SIM_ADDR_OFFSET 0x90000
+
+#ifndef DRV_2_SIM_CONTROLLER
+ #define SIM0_BASE_ADDR_MTK SIM_base
+#else //DRV_2_SIM_CONTROLLER is defined
+ //SIM0_BASE_ADDR_MTK is used in Gemini project, to make code integrity, we use this in dual controller solution, too
+ //simInterface should be local variable when this MACRO called, this won't make race condition
+ #define SIM0_BASE_ADDR_MTK (SIM_base + ((SIM2_base-SIM_base)*simInterface))
+#endif
+#define SIM_CTRL_MTK 0x0
+#define SIM_CONF_MTK 0x4
+#define SIM_BRR_MTK 0x8
+#define SIM_IRQEN_MTK 0x10
+#define SIM_STS_MTK 0x14
+
+#define SIM_RETRY_MTK 0x20
+#define SIM_TIDE_MTK 0x24
+
+#define SIM_DATA_MTK 0x30
+#define SIM_COUNT_MTK 0x34
+
+#define SIM_ATIME_MTK 0x40
+#define SIM_DTIME_MTK 0x44
+#define SIM_TOUT_MTK 0x48
+
+#define SIM_INS_MTK 0x60
+#define SIM_IMP3_MTK 0x64
+#define SIM_SW1_MTK 0x68
+#define SIM_SW2_MTK 0x6c
+#define SIM_STATUS_MTK 0x74
+
+
+//SIM_CTRL
+#define SIM_CTRL_SIMON 0x0001
+#define SIM_CTRL_HALT 0x0002 /* Enable Clk stop mode or disable */
+#define SIM_CTRL_WRST 0x0004 /* Trigger a warm reset */
+
+//SIM_CONF
+#define SIM_CONF_RXHSK 0x0001
+#define SIM_CONF_TXHSK 0x0002
+#define SIM_CONF_CLKPO 0x0004
+#define SIM_CONF_SINV 0x0008
+#define SIM_CONF_SDIR 0x0010
+#define SIM_CONF_ODDPARITY 0x0020
+#define SIM_CONF_SIMSEL 0x0040
+#define SIM_CONF_TOUTEN 0x0080
+#define SIM_CONF_T0EN 0x0200
+#define SIM_CONF_HFEN 0x0400
+#define SIM_CONF_T1EN 0x0100
+
+#define SIM_CONF_Direct 0x0000
+#define SIM_CONF_InDirect 0x0038
+
+//SIM_BRR
+#define SIM_BRR_CLKMSK 0x0003
+#define SIM_BRR_CLK_Div2 0x0000
+#define SIM_BRR_CLK_Div4 0x0001
+#define SIM_BRR_CLK_Div8 0x0002
+#define SIM_BRR_CLK_Div12 0x0003
+
+#define SIM_BRR_ETUMSK 0x07FC
+#define SIM_BRR_BAUDMSK 0x000C
+//#if ( (defined(MT6218B)) || (defined(MT6219)))
+#if defined(DRV_SIM_REG_BAUD_6218B_SERIES)
+ #define SIM_BRR_BAUD_Div372 (0x16<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (0x03<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (0x01<<2) //F=512, D=16
+#else /*!Mt6218B,MT6219*/
+ #define SIM_BRR_BAUD_Div372 (372<<2) //F=372, D=1
+ #define SIM_BRR_BAUD_Div64 (64<<2) //F=512, D=8
+ #define SIM_BRR_BAUD_Div32 (32<<2) //F=512, D=16
+ #define SIM_BRR_BAUD_Div16 (16<<2) //F=512,D=32
+#endif /*MT6218B,MT6219*/
+
+//SIM_IRQEN
+#define SIM_IRQEN_TX 0x0001
+#define SIM_IRQEN_RX 0x0002
+#define SIM_IRQEN_OV 0x0004
+#define SIM_IRQEN_TOUT 0x0008
+#define SIM_IRQEN_TXERR 0x0010
+#define SIM_IRQEN_NATR 0x0020
+#define SIM_IRQEN_SIMOFF 0x0040
+#define SIM_IRQEN_T0END 0x0080
+#define SIM_IRQEN_RXERR 0x0100
+
+#define SIM_IRQEN_ALL 0x01bf
+#define SIM_IRQEN_ALLOFF 0x0000
+/* SIM_IRQEN_TXErr, SIM_IRQEN_NATR, SIM_IRQEN_TOUT,SIM_IRQEN_OV,SIM_IRQEN_RX*/
+#define SIM_IRQEN_Normal 0x013e
+/*SIM_IRQEN_T0END,SIM_IRQEN_TXErr,SIM_IRQEN_TOUT*/
+#define SIM_IRQEN_CMDNormal 0x019e
+/*#define SIM_IRQEN_CMDNormal 0x019c*/
+#define SIM_IRQEN_CMDDMANormal 0x019c
+#define USIM_IRQEN_ATR (SIM_IRQEN_RX|SIM_IRQEN_NATR)
+#define USIM_IRQEN_NORMAL (SIM_STS_RX|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_TXERR|SIM_STS_RXERR)
+#define USIM_IRQEN_CMD_T1 (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_RXERR| \
+ SIM_STS_OV|SIM_STS_TOUT)
+#define USIM_IRQEN_CMD_T1_RX (SIM_STS_EDCERR|SIM_STS_T1END|SIM_STS_OV|SIM_STS_TOUT|SIM_STS_RX)
+#define USIM_IRQEN_CMD_T1_TX (SIM_STS_T1END)
+
+//SIM_STS
+#define SIM_STS_TX 0x0001
+#define SIM_STS_RX 0x0002
+#define SIM_STS_OV 0x0004
+#define SIM_STS_TOUT 0x0008
+#define SIM_STS_TXERR 0x0010
+#define SIM_STS_NATR 0x0020
+#define SIM_STS_SIMOFF 0x0040
+#define SIM_STS_T0END 0x0080
+#define SIM_STS_RXERR 0x0100
+#define SIM_STS_T1END 0x0200
+#define SIM_STS_EDCERR 0x0400
+
+//SIM_TOUT
+#define SIM_TOUT_MSK 0x3fff
+
+//SIM_RETRY
+#define SIM_RETRY_RXMASK 0x0007
+#define SIM_RETRY_TXMASK 0x0700
+
+//SIM_TIDE
+#define SIM_TIDE_RXMASK 0x000f
+#define SIM_TIDE_TXMASK 0x0f00
+
+//SIM_COUNT
+#define SIM_COUNT_MASK 0x000f
+
+//SIM_INS
+#define SIM_INS_MASK 0x00ff
+#define SIM_INS_INSD 0x0100
+
+//SIM_IMP3
+#define SIM_IMP3_MASK 0x01ff
+
+// SIM_STATUS
+#define SIM_STATUS_EDC 0x40
+#define SIM_STATUS_ACK 0x20
+#define SIM_STATUS_NACK 0x10
+#define SIM_STATUS_IDLE 0x01
+#define SIM_STATUS_INS 0x02
+#define SIM_STATUS_SW1 0x04
+#define SIM_STATUS_SW2 0x08
+
+#define SIM_TX_DELAY_LEN 0x4
+#define SIM_TX_DELAY_LOOP 4000
+#endif /*MT6218B*/
+
+#endif /*_SIM_HW_H*/
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_mtk.h b/mcu/driver/devdrv/usim/inc/sim_mtk.h
new file mode 100644
index 0000000..e29771c
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_mtk.h
@@ -0,0 +1,221 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_mtk.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is the header file for MTK dual SIM controllers.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ *
+ * removed!
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+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "drv_features.h"
+#include "sim_sw_comm.h"
+#include "sim_hw_mtk.h"
+#include "sim_reg_adp.h"
+#include "intrCtrl.h"
+/*RHR*/
+
+#ifndef __SIM_DRV_MULTI_DRV_ARCH__
+#ifdef DRV_2_SIM_CONTROLLER
+typedef enum
+{
+ SIM_DRIVER_ACT = 0x00000001,
+ SIM_DRIVER_DEACT = 0x00000002,
+ SIM_PDNDIS = 0x00000003,
+ SIM_PDNEN = 0x00000004,
+ SIM_INT_SIM = 0x00000005,
+ SIM_INT_USIM = 0x00000006,
+ SIM_DRIVER_ACT_SIMD = 0x00000007,
+ SIM_DRIVER_DEACT_SIMD = 0x00000008,
+ SIM_CMD_TX_LOG = 0x00010001,
+ SIM_CMD_INS_LOG = 0x00010002,
+ SIM_CMD_TXDELAY = 0x00010003,
+ SIM_INIT_USIM = 0x00020001,
+ SIM_DEACTIVATE_1 = 0x00030001,
+ SIM_DEACTIVATE_2 = 0x00030002,
+ SIM_ACTION_RESET = 0x000F0001,
+ SIM_ACTION_POWOFF = 0x000F0002,
+ SIM_ACTION_COMMAND = 0x000F0003,
+ SIM_ACTION_EOC = 0x000F0004
+} sim_msgTag;
+
+typedef struct
+{
+ sim_msgTag tag;
+ kal_uint32 event;
+ kal_uint32 data1;
+ kal_uint32 data2;
+ kal_uint32 time;
+} sim_msg;
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+#define SIM_Reject_MTK(simInterface) \
+ {\
+ SIM_DisAllIntr(simInterface);\
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_addMsg(SIM_DRIVER_DEACT_SIMD, simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg(SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK, SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ SIM_ClearBits(SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK, SIM_CTRL_SIMON);\
+ }\
+ else\
+ {\
+ sim_PDNEnable(simInterface);\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent_MTK(SimCard,SIM_NOREADY);\
+ }\
+ }
+#ifdef NO_SLIM_DEF
+/*********************************************************************************************
+*we move this macro from sim_sw_comm.h to here, since we need a distinguish from dual controllers or MT6302.
+*In dual controllers solution, we need to enable interrupt according to simInterface, but in MT6302 solution, we only need to enable SIM's.
+**********************************************************************************************/
+#define SIM_WaitEvent_MTK(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ extern void sim_dump_error_line(void);\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ sim_workingTaskWaiting = KAL_TRUE;\
+ if(KAL_TRUE == _unmaskSIMIntr){\
+ if(0 == simInterface)\
+ IRQUnmask(IRQ_USIM0_CODE);\
+ else\
+ IRQUnmask(IRQ_USIM1_CODE);\
+ }\
+ kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_workingTaskWaiting = KAL_FALSE;\
+ sim_dump_error_line();\
+ }
+
+//redefine new MACRO since there is no sim_MT6302_addMsg API in MT6235, MT6238 and I don't want to change MT6302 again
+#define SIM_SetEvent_MTK(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+#endif /*#ifdef NO_SLIM_DEF*/
+#endif /*DRV_2_SIM_CONTROLLER*/
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/
diff --git a/mcu/driver/devdrv/usim/inc/sim_reg_adp.h b/mcu/driver/devdrv/usim/inc/sim_reg_adp.h
new file mode 100644
index 0000000..3a80938
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_reg_adp.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_reg_adp.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is to be an adaptation layer for all SIM related register functions.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "drv_comm.h"
+/*RHR*/
+#ifndef __SIM_REG_ADP_H__
+#define __SIM_REG_ADP_H__
+
+
+
+
+
+#ifdef __DRV_SIM_RW_DBG__
+ #define SIM_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+ #define SIM_Reg(addr) DRV_DBG_Reg(addr)
+ #define SIM_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+ #define SIM_Reg32(addr) DRV_DBG_Reg32(addr)
+ #define SIM_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+ #define SIM_Reg8(addr) DRV_DBG_Reg8(addr)
+ #define SIM_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+ #define SIM_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+ #define SIM_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+ #define SIM_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+ #define SIM_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+ #define SIM_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+ #define SIM_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+ #define SIM_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+ #define SIM_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+ #define SIM_WriteReg(addr,data) DRV_WriteReg(addr,data)
+ #define SIM_Reg(addr) DRV_Reg(addr)
+ #define SIM_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+ #define SIM_Reg32(addr) DRV_Reg32(addr)
+ #define SIM_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+ #define SIM_Reg8(addr) DRV_Reg8(addr)
+ #if defined(DRV_SIM_6292_SERIES) || defined(DRV_SIM_6293_SERIES) || defined(DRV_SIM_6295_SERIES) || defined(DRV_SIM_6297_SERIES)
+ #define SIM_ClearBits(addr,data) {MO_Sync();DRV_ClearBits(addr,data);}
+ #define SIM_SetBits(addr,data) {MO_Sync();DRV_SetBits(addr,data);}
+ #define SIM_SetData(addr, bitmask, value) {MO_Sync();DRV_SetData(addr, bitmask, value);}
+ #define SIM_ClearBits32(addr,data) {MO_Sync();DRV_ClearBits32(addr,data);}
+ #define SIM_SetBits32(addr,data) {MO_Sync();DRV_SetBits32(addr,data);}
+ #define SIM_SetData32(addr, bitmask, value) {MO_Sync();DRV_SetData32(addr, bitmask, value);}
+ #define SIM_ClearBits8(addr,data) {MO_Sync();DRV_ClearBits8(addr,data);}
+ #define SIM_SetBits8(addr,data) {MO_Sync();DRV_SetBits8(addr,data);}
+ #define SIM_SetData8(addr, bitmask, value) {MO_Sync();DRV_SetData8(addr, bitmask, value);}
+ #else
+ #define SIM_ClearBits(addr,data) DRV_ClearBits(addr,data)
+ #define SIM_SetBits(addr,data) DRV_SetBits(addr,data)
+ #define SIM_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+ #define SIM_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+ #define SIM_SetBits32(addr,data) DRV_SetBits32(addr,data)
+ #define SIM_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+ #define SIM_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+ #define SIM_SetBits8(addr,data) DRV_SetBits8(addr,data)
+ #define SIM_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+ #endif
+#endif
+
+
+
+
+
+#endif //__SIM_REG_ADP_H__
diff --git a/mcu/driver/devdrv/usim/inc/sim_sw_comm.h b/mcu/driver/devdrv/usim/inc/sim_sw_comm.h
new file mode 100644
index 0000000..893450e
--- /dev/null
+++ b/mcu/driver/devdrv/usim/inc/sim_sw_comm.h
@@ -0,0 +1,634 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sim_sw_comm.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for different SIM drivers on multiple SIM solution.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*RHR*/
+#include "sim_al.h"
+#include "kal_public_api.h"
+#include "sim_hw_mtk.h"
+#include "sim_reg_adp.h"
+#include "drv_features.h"
+/*RHR*/
+#ifdef __SIM_DRV_MULTI_DRV_ARCH__
+/*when __SIM_DRV_MULTI_DRV_ARCH__ is defined, we reorganize the header file to make all solutions built together*/
+#include "sim_drv_HW_def_MTK.h"
+#include "sim_drv_SW_struct.h"
+#include "sim_drv_SW_function.h"
+#include "sim_drv_SW_API.h"
+#include "multi_icc_custom.h"
+#else /*__SIM_DRV_MULTI_DRV_ARCH__*/
+#ifndef _SIM_SW_H
+#define _SIM_SW_H
+
+
+
+//#define __30V_ONLY_ME__
+//#define __18V_ONLY_ME__
+//#define __18V_30V_ME__
+
+//#if ( (!defined(MT6208)) && (!defined(FPGA)) )
+#if ((!defined(DRV_SIM_MT6208_SERIES)) && (!defined(DRV_SIM_MT6205B_SERIES)))
+/* SIM_ADDDMA & NoT0CTRL can't active concurrently */
+#define SIM_ADDDMA
+//#define NoT0CTRL
+
+/* SIM Format */
+#define SIM_direct 0
+#define SIM_indirect 1
+
+/* SIM Power */
+#define SIM_30V RESET_30V
+#define SIM_18V RESET_18V
+
+#define CMD_RECBUFSIZE 13
+/*DMA setting, such usb*/
+/* Size = 8bit, sinc en, dinc disable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimTxNormal 0x0074
+/* Size = 8bit, sinc disable, dinc enable, hw management, 1 trans/dma cycle, USB master,Interrupt disable */
+#define DMA_CON_SimRxNormal 0x0078
+
+/* SIM State */
+#define SIM_WAIT_FOR_ATR 0 /* reset SIM card and wait ATR */
+#define SIM_PROCESS_ATR 1 /* receiving ATR data */
+#define SIM_PROCESS_PTS 2 /* receiving PTS response data */
+#define SIM_PROCESSCMD 3
+#define SIM_SERIOUSERR 4 /* serous error due to txerr*/
+#define SIM_PWROFF 5
+#define SIM_WaitRejectDone 6
+
+
+/* SIM Miner State */
+#ifdef NoT0CTRL
+ #define SIMD_CmdIdle 0
+ #define SIM_WaitProcByte 1
+ #define SIM_AckDataState 2
+ #define SIM_NAckDataState 3
+ #define SIM_WaitSWByte 4
+#endif /*NoT0CTRL*/
+/*just for clock stop mode*/
+#define SIM_ProcessClk 5
+#define SIM_StopClk 6
+#define SIM_WaitCmdEnd 7
+
+
+/* Event */
+#define ATR_END 0x0010
+#define PTS_END 0x0008
+#define SIM_EVT_CMD_END 0x0004
+#define RST_READY 0x0002
+#define CLK_PROC 0x0020
+#define ACTIVATE_DONE 0x0040
+/*#define INIRET 0x0001*/
+
+/*ATR data define*/
+#define TAMask 0x0010
+#define TBMask 0x0020
+#define TCMask 0x0040
+#define TDMask 0x0080
+
+/* Result */
+#define SIM_SUCCESS SIM_NO_ERROR
+#define SIM_NOREADY SIM_NO_INSERT
+#define SIM_CARDERR SIM_CARD_ERROR
+#define SIM_INITXERR 5
+#define SIM_INIPTSERR 6
+#define SIM_CMDTXERR 7 /* parity error */
+#define SIM_CMDRECERR 8
+#define SIM_CMDTOUT 9
+#define SIM_CLKPROC 10
+#define SIM_NULLTIMEOUT 11
+
+#define SW1_GET_RESP_SIM 0x9f
+#define SW1_GET_RESP_USIM 0x61
+#define SW1_RESEND_USIM 0x6c
+#define LEN_INDEX 4 // index to the P3 of command header
+#define LEN_OF_CMD 5
+#define GET_RESP_CLA_SIM 0xa0
+#define GET_RESP_CLA_USIM 0x00
+#define SW1_WARN1 0x62
+#define SW1_WARN2 0x63
+#define SIM_SW_STATUS_OK 0x9000
+#define SIM_SW_STATUS_FAIL 0x00
+
+#define Speed372 0
+#define Speed64 1
+#define Speed32 2
+#define Speed16 3
+
+typedef kal_uint16 sim_status;
+
+#define MAX_SIM_ERROR_LINE 4
+
+#ifdef SIM_DBG_OPTION_ENABLE
+#define SIM_ASSERT(_condition) \
+ { \
+ ASSERT(_condition); \
+ }
+#else /*!SIM_DBG_OPTION_ENABLE*/
+#if defined(SIM_DEBUG_INFO)
+#define SIM_ASSERT(_condition) \
+ { \
+ if (!(_condition)) \
+ { \
+ sim_assert(__LINE__); \
+ } \
+ }
+#else
+#define SIM_ASSERT(_condition)
+#endif /*#if defined(SIM_DEBUG_INFO)*/
+#endif /*SIM_DBG_OPTION_ENABLE*/
+
+typedef enum
+{
+ SIM_PROTOCOL,
+ USIM_PROTOCOL
+} sim_protocol_app_enum;
+
+typedef enum
+{
+ T0_PROTOCOL,
+ T1_PROTOCOL,
+ UNKNOWN_PROTOCOL
+} sim_protocol_phy_enum;
+
+typedef enum
+{
+ UNKNOWN_POWER_CLASS = 0,
+ CLASS_A_50V = 1,
+ CLASS_B_30V = 2,
+ CLASS_AB = 3,
+ CLASS_C_18V = 4,
+ ClASS_BC = 6,
+ CLASS_ABC = 7,
+ CLASS_ALLSUPPORT = 0xff
+} sim_power_enum;
+
+typedef enum
+{
+ CLOCK_STOP_NOT_SUPPORT = 0x0,
+ CLOCK_STOP_LOW = 0x40,
+ CLOCK_STOP_HIGH = 0x80,
+ CLOCK_STOP_ANY = 0xc0,
+ CLOCK_STOP_MSK = 0xc0,
+ CLOCK_STOP_UNKONW = 0x0f
+} sim_clock_stop_enum;
+
+typedef enum
+{
+ SPEED_372,
+ SPEED_64,
+ SPEED_32,
+ SPEED_16
+} sim_speed_enum;
+
+typedef enum
+{
+ SIM_DIRECT,
+ SIM_INVERSE
+} sim_dir_enum;
+
+typedef enum
+{
+ usim_case_1 = 1,
+ usim_case_2,
+ usim_case_3,
+ usim_case_4
+} usim_cmd_case_enum;
+
+typedef struct
+{
+ kal_uint32* ptr;
+ kal_uint32 size;
+} sim_nvram_param_struct;
+
+typedef struct
+{
+ sim_power_enum power;
+ sim_speed_enum speed;
+ sim_clock_stop_enum clock_stop;
+ sim_protocol_app_enum app_proto;
+ sim_protocol_phy_enum phy_proto;
+ kal_bool T0_support; // if T0 is supported
+ kal_bool T1_support; // if T1 is supported
+ kal_uint8 hist_index; // index to the historical char of ATR
+ kal_uint8 *ATR;
+ /*following information is necessary for SIM task for UICC identification*/
+ kal_bool TAiExist; //if the first TA for T=15 is existed
+} sim_info_struct;
+
+typedef struct
+{
+ kal_uint8 State;
+ kal_uint8 Data_format; /*SIM_direct,SIM_indirect*/
+ kal_uint8 Power; /*SIM_3V,SIM_5V*/
+ kal_uint8 recData[40]; /*PTS or ATR data*/
+ kal_bool recDataErr;
+ kal_uint16 recDataLen; /* for command, ATR process */
+ kal_uint8 result; /* for ATR, command, RST */
+ kal_uint32 EvtFlag;
+ sim_env SIM_ENV;
+#ifndef SIM_ADDDMA
+ kal_uint8 *txbuffer; /* only used for no DMA */
+ kal_uint16 txsize; /* only used for no DMA */
+ kal_uint16 txindex; /* only used for no DMA */
+ kal_uint8 *rxbuffer; /* only used for no DMA */
+#ifdef NoT0CTRL
+ kal_uint16 recsize;
+ kal_uint8 INS;
+ kal_uint8 SW1;
+ kal_uint8 SW2;
+#endif /*NoT0CTRL*/
+#endif /*SIM_ADDDMA*/
+ /*add for clock stop mode*/
+ kal_uint8 cmdState; /* only used for no T0CTRL, and for clock stop */
+ kal_uint8 Speed; /*Speed372,Speed64,Speed32*/
+ kal_bool clkStop; /*Clok Stop Enable*/
+ kal_bool clkStopLevel; /*Clok Stop level*/
+ kal_bool reject_set_event;
+ kal_bool event_state;
+ kal_uint8 initialPower;
+ sim_card_speed_type sim_card_speed;
+ kal_hisrid hisr; /*SIM HISR*/
+ kal_eventgrpid event; /*SIM Event*/
+
+ sim_protocol_app_enum app_proto;
+ kal_bool timeout;
+ usim_cmd_case_enum cmd_case;
+ kal_bool is_err; // sim command has error once.
+ kal_bool get9000WhenSelect;
+
+ /*following variables are get from global variables for 2 SIM projects*/
+ kal_uint32 TOUTValue;
+ kal_uint8 TOUT_Factor;
+ kal_uint8 sim_dmaport;
+ kal_uint8 reset_index;
+ DMA_HWMENU sim_menu;
+ DMA_INPUT sim_input;
+ kal_bool TS_HSK_ENABLE;
+ kal_bool sim_ATR_fail;
+ kal_bool PTS_check;
+ kal_uint8 PTS_data[4];
+
+} Sim_Card;
+
+
+#define GET_SIM_CB(a) &SimCard_cb[a]
+
+#define SIM_SetRXRetry(_RXRetry)\
+ {\
+ kal_uint16 _Retry;\
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_RXMASK;\
+ _Retry |= _RXRetry;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_SetTXRetry(_TXRetry) \
+ {\
+ kal_uint16 _Retry;\
+ _Retry = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK);\
+ _Retry &= ~SIM_RETRY_TXMASK;\
+ _Retry |= (_TXRetry<<8);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_RETRY_MTK), _Retry);\
+ }
+
+#define SIM_ObtainSW(_SW) \
+ {\
+ kal_uint16 _SW1;\
+ kal_uint16 _SW2;\
+ _SW1 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW1_MTK);\
+ _SW2 = SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_SW2_MTK);\
+ _SW = (_SW2 | (_SW1 << 8));\
+ }
+
+#define SIM_SetIMP3(_IMP3) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IMP3_MTK), _IMP3)
+
+#define SIM_SetCmdINS(_INS) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_INS_MTK), _INS)
+
+#define SIM_SetAtime(_ATIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_ATIME_MTK), _ATIME)
+
+#define SIM_SetDtime(_DTIME) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_DTIME_MTK), _DTIME)
+
+#define SIM_FIFO_Flush() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK), 0x01)
+
+#define SIM_Reject(simInterface) \
+ {\
+ SIM_DisAllIntr(simInterface);\
+ if (SIM_Reg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK))&SIM_CTRL_SIMON)\
+ {\
+ sim_MT6302_addMsg(SIM_MT6302_DRIVER_DEACT, simInterface, 2, 0);\
+ SimCard->State = SIM_PWROFF;\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_SIMOFF);\
+ SIM_FIFO_Flush();\
+ if(KAL_FALSE == sim_MT6302_QueryNeedManualControl()){\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_SIMON);\
+ sim_MT6302_VCCCtrl(simInterface, 0);\
+ }\
+ else{\
+ sim_MT6302_manualDeactive(simInterface);\
+ }\
+ }\
+ else\
+ {\
+ sim_PDNEnable(simInterface);\
+ if(SimCard->reject_set_event)\
+ SIM_SetEvent(SimCard,SIM_NOREADY);\
+ }\
+ }
+
+
+#define SIM_Active() SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), 0x0001)
+
+
+#define SIM_WaitEvent(_SIMCARD,_flag, _unmaskSIMIntr) \
+ {\
+ kal_uint32 _event_group;\
+ extern void sim_dump_error_line(void);\
+ _SIMCARD->event_state = KAL_TRUE;\
+ _SIMCARD->EvtFlag = _flag;\
+ sim_workingTaskWaiting = KAL_TRUE;\
+ if(KAL_TRUE == _unmaskSIMIntr)\
+ IRQUnmask(IRQ_USIM0_CODE);\
+ kal_retrieve_eg_events(_SIMCARD->event,_flag,KAL_OR_CONSUME,&_event_group,KAL_SUSPEND);\
+ sim_workingTaskWaiting = KAL_FALSE;\
+ sim_dump_error_line();\
+ }
+
+#define SIM_SetEvent(_SIMCARD,_result) \
+ {\
+ _SIMCARD->result = _result;\
+ _SIMCARD->event_state = KAL_FALSE;\
+ if(0 == _SIMCARD->EvtFlag)\
+ kal_set_eg_events(_SIMCARD->event,SIM_EVT_CMD_END,KAL_OR);\
+ else\
+ kal_set_eg_events(_SIMCARD->event,_SIMCARD->EvtFlag,KAL_OR);\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF);\
+ sim_MT6302_addMsg(0x12345678, _SIMCARD->EvtFlag, __LINE__, drv_get_current_time());\
+ }
+
+
+#define SIM_NotifyCARDisHALTEN() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HALTEN)
+#define SIM_T0CtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_T0CtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_T0EN)
+#define SIM_FlowCtrlEnable() SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+#define SIM_FlowCtrlDisable() SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_HFEN)
+
+#define SIM_DisIntr(_Intr) SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), _Intr)
+#define SIM_ActiveClk(simInterface) \
+ {\
+ sim_PDNDisable(simInterface);\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }
+
+#define SIM_Idle(_level, simInterface) \
+ {\
+ if (_level == KAL_TRUE)\
+ {\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ else\
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_CLKPO);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CTRL_MTK), SIM_CTRL_HALT);\
+ }\
+ sim_PDNEnable(simInterface);\
+ }
+
+
+#define SIM_FIFO_GetLev(a) (SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_COUNT_MTK) & SIM_COUNT_MASK)
+#define SIM_DisTOUTIntr(a) SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_OpenTOUTIntr(a) SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_TOUT)
+#define SIM_DisAllIntr(a) SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF)
+#ifdef SIM_TOUT_REG_V2
+#define SIM_SetTOUT(_TOUT) \
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ if (_TOUT < 0xffffff)\
+ SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), _TOUT);\
+ else\
+ SIM_WriteReg32((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffffff);\
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ }
+#else
+#define SIM_SetTOUT(_TOUT) \
+ {\
+ SIM_ClearBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ if (_TOUT < 0xffff)\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), _TOUT);\
+ else\
+ SIM_WriteReg((SIM0_BASE_ADDR_MTK + SIM_TOUT_MTK), 0xffff);\
+ SIM_Reg(SIM0_BASE_ADDR_MTK + SIM_STS_MTK);\
+ SIM_SetBits((SIM0_BASE_ADDR_MTK + SIM_CONF_MTK), SIM_CONF_TOUTEN);\
+ }
+#endif
+
+#ifdef NoT0CTRL
+#define SIMCmdInit()
+#else /*NoT0CTRL*/
+#define SIMCmdInit() \
+ {\
+ SIM_T0CtrlEnable(); /*SIM_FlowCtrlEnable()*/ \
+ }
+#endif /*NoT0CTRL*/
+
+extern void sim_assert(kal_uint32 line);
+extern kal_uint16 SIM_CMD(kal_uint8 *txData, kal_uint16 txSize, kal_uint8 *result, kal_uint16 *rcvSize, kal_uint8 *Error, kal_uint32 simInterface);
+extern void L1sim_ChangeBaud(void);
+extern void L1sim_NormalBaud(void);
+extern sim_card_speed_type L1sim_Get_CardSpeedType(kal_uint32 simInterface);
+extern void L1sim_Enable_Enhanced_Speed(kal_bool enable, kal_uint32 simInterface);
+extern kal_uint16 L1sim_Cmd_Layer(kal_uint8 *txData, kal_uint32 *txSize, kal_uint8 *rxData, kal_uint32 *rxSize, kal_uint32 simInterface);
+
+extern void SIM1_LDO_enable(kal_bool enable);
+extern void SIM2_LDO_enable(kal_bool enable);
+
+#endif /*(MT6208,FPGA)*/
+
+#endif /*_SIM_SW_H*/
+#endif /*__SIM_DRV_MULTI_DRV_ARCH__*/