[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6325_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6325_hw.h
new file mode 100644
index 0000000..1d050a9
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6325_hw.h
@@ -0,0 +1,6822 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6325_hw.h
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6325
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6325_HW_H_STRUCT__
+#define __DCL_PMIC6325_HW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6325_REG_API
+
+#define MT6325_PMIC_REG_BASE (0x0000)
+
+#define MT6325_STRUP_CON0 (MT6325_PMIC_REG_BASE + 0x0000)
+#define MT6325_STRUP_CON2 (MT6325_PMIC_REG_BASE + 0x0002)
+#define MT6325_STRUP_CON3 (MT6325_PMIC_REG_BASE + 0x0004)
+#define MT6325_STRUP_CON4 (MT6325_PMIC_REG_BASE + 0x0006)
+#define MT6325_STRUP_CON5 (MT6325_PMIC_REG_BASE + 0x0008)
+#define MT6325_STRUP_CON6 (MT6325_PMIC_REG_BASE + 0x000A)
+#define MT6325_STRUP_CON7 (MT6325_PMIC_REG_BASE + 0x000C)
+#define MT6325_STRUP_CON8 (MT6325_PMIC_REG_BASE + 0x000E)
+#define MT6325_STRUP_CON9 (MT6325_PMIC_REG_BASE + 0x0010)
+#define MT6325_STRUP_CON10 (MT6325_PMIC_REG_BASE + 0x0012)
+#define MT6325_STRUP_CON11 (MT6325_PMIC_REG_BASE + 0x0014)
+#define MT6325_STRUP_CON12 (MT6325_PMIC_REG_BASE + 0x0016)
+#define MT6325_STRUP_CON13 (MT6325_PMIC_REG_BASE + 0x0018)
+#define MT6325_STRUP_CON14 (MT6325_PMIC_REG_BASE + 0x001A)
+#define MT6325_STRUP_CON15 (MT6325_PMIC_REG_BASE + 0x001C)
+#define MT6325_STRUP_CON16 (MT6325_PMIC_REG_BASE + 0x001E)
+#define MT6325_STRUP_CON17 (MT6325_PMIC_REG_BASE + 0x0020)
+#define MT6325_STRUP_CON18 (MT6325_PMIC_REG_BASE + 0x0022)
+#define MT6325_STRUP_CON19 (MT6325_PMIC_REG_BASE + 0x0024)
+#define MT6325_STRUP_CON20 (MT6325_PMIC_REG_BASE + 0x0026)
+#define MT6325_STRUP_CON21 (MT6325_PMIC_REG_BASE + 0x0028)
+#define MT6325_STRUP_CON22 (MT6325_PMIC_REG_BASE + 0x002A)
+#define MT6325_STRUP_CON23 (MT6325_PMIC_REG_BASE + 0x002C)
+#define MT6325_STRUP_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x002E)
+#define MT6325_HWCID (MT6325_PMIC_REG_BASE + 0x0200)
+#define MT6325_SWCID (MT6325_PMIC_REG_BASE + 0x0202)
+#define MT6325_TOP_CON (MT6325_PMIC_REG_BASE + 0x0204)
+#define MT6325_TEST_OUT (MT6325_PMIC_REG_BASE + 0x0206)
+#define MT6325_TEST_CON0 (MT6325_PMIC_REG_BASE + 0x0208)
+#define MT6325_TEST_CON1 (MT6325_PMIC_REG_BASE + 0x020A)
+#define MT6325_TESTMODE_SW (MT6325_PMIC_REG_BASE + 0x020C)
+#define MT6325_EN_STATUS0 (MT6325_PMIC_REG_BASE + 0x020E)
+#define MT6325_EN_STATUS1 (MT6325_PMIC_REG_BASE + 0x0210)
+#define MT6325_EN_STATUS2 (MT6325_PMIC_REG_BASE + 0x0212)
+#define MT6325_OCSTATUS0 (MT6325_PMIC_REG_BASE + 0x0214)
+#define MT6325_OCSTATUS1 (MT6325_PMIC_REG_BASE + 0x0216)
+#define MT6325_OCSTATUS2 (MT6325_PMIC_REG_BASE + 0x0218)
+#define MT6325_PGSTATUS (MT6325_PMIC_REG_BASE + 0x021A)
+#define MT6325_TOPSTATUS (MT6325_PMIC_REG_BASE + 0x021C)
+#define MT6325_TDSEL_CON (MT6325_PMIC_REG_BASE + 0x021E)
+#define MT6325_RDSEL_CON (MT6325_PMIC_REG_BASE + 0x0220)
+#define MT6325_SMT_CON0 (MT6325_PMIC_REG_BASE + 0x0222)
+#define MT6325_SMT_CON1 (MT6325_PMIC_REG_BASE + 0x0224)
+#define MT6325_SMT_CON2 (MT6325_PMIC_REG_BASE + 0x0226)
+#define MT6325_DRV_CON0 (MT6325_PMIC_REG_BASE + 0x0228)
+#define MT6325_DRV_CON1 (MT6325_PMIC_REG_BASE + 0x022A)
+#define MT6325_DRV_CON2 (MT6325_PMIC_REG_BASE + 0x022C)
+#define MT6325_DRV_CON3 (MT6325_PMIC_REG_BASE + 0x022E)
+#define MT6325_TOP_STATUS (MT6325_PMIC_REG_BASE + 0x0230)
+#define MT6325_TOP_STATUS_SET (MT6325_PMIC_REG_BASE + 0x0232)
+#define MT6325_TOP_STATUS_CLR (MT6325_PMIC_REG_BASE + 0x0234)
+#define MT6325_RGS_ANA_MON (MT6325_PMIC_REG_BASE + 0x0236)
+#define MT6325_TOP_CKPDN_CON0 (MT6325_PMIC_REG_BASE + 0x0238)
+#define MT6325_TOP_CKPDN_CON0_SET (MT6325_PMIC_REG_BASE + 0x023A)
+#define MT6325_TOP_CKPDN_CON0_CLR (MT6325_PMIC_REG_BASE + 0x023C)
+#define MT6325_TOP_CKPDN_CON1 (MT6325_PMIC_REG_BASE + 0x023E)
+#define MT6325_TOP_CKPDN_CON1_SET (MT6325_PMIC_REG_BASE + 0x0240)
+#define MT6325_TOP_CKPDN_CON1_CLR (MT6325_PMIC_REG_BASE + 0x0242)
+#define MT6325_TOP_CKPDN_CON2 (MT6325_PMIC_REG_BASE + 0x0244)
+#define MT6325_TOP_CKPDN_CON2_SET (MT6325_PMIC_REG_BASE + 0x0246)
+#define MT6325_TOP_CKPDN_CON2_CLR (MT6325_PMIC_REG_BASE + 0x0248)
+#define MT6325_TOP_CKPDN_CON3 (MT6325_PMIC_REG_BASE + 0x024A)
+#define MT6325_TOP_CKPDN_CON3_SET (MT6325_PMIC_REG_BASE + 0x024C)
+#define MT6325_TOP_CKPDN_CON3_CLR (MT6325_PMIC_REG_BASE + 0x024E)
+#define MT6325_TOP_CKSEL_CON0 (MT6325_PMIC_REG_BASE + 0x0250)
+#define MT6325_TOP_CKSEL_CON0_SET (MT6325_PMIC_REG_BASE + 0x0252)
+#define MT6325_TOP_CKSEL_CON0_CLR (MT6325_PMIC_REG_BASE + 0x0254)
+#define MT6325_TOP_CKSEL_CON1 (MT6325_PMIC_REG_BASE + 0x0256)
+#define MT6325_TOP_CKSEL_CON1_SET (MT6325_PMIC_REG_BASE + 0x0258)
+#define MT6325_TOP_CKSEL_CON1_CLR (MT6325_PMIC_REG_BASE + 0x025A)
+#define MT6325_TOP_CKSEL_CON2 (MT6325_PMIC_REG_BASE + 0x025C)
+#define MT6325_TOP_CKSEL_CON2_SET (MT6325_PMIC_REG_BASE + 0x025E)
+#define MT6325_TOP_CKSEL_CON2_CLR (MT6325_PMIC_REG_BASE + 0x0260)
+#define MT6325_TOP_CKDIVSEL_CON (MT6325_PMIC_REG_BASE + 0x0262)
+#define MT6325_TOP_CKDIVSEL_CON_SET (MT6325_PMIC_REG_BASE + 0x0264)
+#define MT6325_TOP_CKDIVSEL_CON_CLR (MT6325_PMIC_REG_BASE + 0x0266)
+#define MT6325_TOP_CKHWEN_CON (MT6325_PMIC_REG_BASE + 0x0268)
+#define MT6325_TOP_CKHWEN_CON_SET (MT6325_PMIC_REG_BASE + 0x026A)
+#define MT6325_TOP_CKHWEN_CON_CLR (MT6325_PMIC_REG_BASE + 0x026C)
+#define MT6325_TOP_CKTST_CON0 (MT6325_PMIC_REG_BASE + 0x026E)
+#define MT6325_TOP_CKTST_CON1 (MT6325_PMIC_REG_BASE + 0x0270)
+#define MT6325_TOP_CKTST_CON2 (MT6325_PMIC_REG_BASE + 0x0272)
+#define MT6325_TOP_CLKSQ (MT6325_PMIC_REG_BASE + 0x0274)
+#define MT6325_TOP_CLKSQ_SET (MT6325_PMIC_REG_BASE + 0x0276)
+#define MT6325_TOP_CLKSQ_CLR (MT6325_PMIC_REG_BASE + 0x0278)
+#define MT6325_TOP_CLKSQ_RTC (MT6325_PMIC_REG_BASE + 0x027A)
+#define MT6325_TOP_CLKSQ_RTC_SET (MT6325_PMIC_REG_BASE + 0x027C)
+#define MT6325_TOP_CLKSQ_RTC_CLR (MT6325_PMIC_REG_BASE + 0x027E)
+#define MT6325_TOP_CLK_TRIM (MT6325_PMIC_REG_BASE + 0x0280)
+#define MT6325_TOP_RST_CON0 (MT6325_PMIC_REG_BASE + 0x0282)
+#define MT6325_TOP_RST_CON0_SET (MT6325_PMIC_REG_BASE + 0x0284)
+#define MT6325_TOP_RST_CON0_CLR (MT6325_PMIC_REG_BASE + 0x0286)
+#define MT6325_TOP_RST_CON1 (MT6325_PMIC_REG_BASE + 0x0288)
+#define MT6325_TOP_RST_MISC (MT6325_PMIC_REG_BASE + 0x028A)
+#define MT6325_TOP_RST_MISC_SET (MT6325_PMIC_REG_BASE + 0x028C)
+#define MT6325_TOP_RST_MISC_CLR (MT6325_PMIC_REG_BASE + 0x028E)
+#define MT6325_TOP_RST_STATUS (MT6325_PMIC_REG_BASE + 0x0290)
+#define MT6325_TOP_RST_STATUS_SET (MT6325_PMIC_REG_BASE + 0x0292)
+#define MT6325_TOP_RST_STATUS_CLR (MT6325_PMIC_REG_BASE + 0x0294)
+#define MT6325_INT_CON0 (MT6325_PMIC_REG_BASE + 0x0296)
+#define MT6325_INT_CON0_SET (MT6325_PMIC_REG_BASE + 0x0298)
+#define MT6325_INT_CON0_CLR (MT6325_PMIC_REG_BASE + 0x029A)
+#define MT6325_INT_CON1 (MT6325_PMIC_REG_BASE + 0x029C)
+#define MT6325_INT_CON1_SET (MT6325_PMIC_REG_BASE + 0x029E)
+#define MT6325_INT_CON1_CLR (MT6325_PMIC_REG_BASE + 0x02A0)
+#define MT6325_INT_CON2 (MT6325_PMIC_REG_BASE + 0x02A2)
+#define MT6325_INT_CON2_SET (MT6325_PMIC_REG_BASE + 0x02A4)
+#define MT6325_INT_CON2_CLR (MT6325_PMIC_REG_BASE + 0x02A6)
+#define MT6325_INT_MISC_CON (MT6325_PMIC_REG_BASE + 0x02A8)
+#define MT6325_INT_MISC_CON_SET (MT6325_PMIC_REG_BASE + 0x02AA)
+#define MT6325_INT_MISC_CON_CLR (MT6325_PMIC_REG_BASE + 0x02AC)
+#define MT6325_INT_STATUS0 (MT6325_PMIC_REG_BASE + 0x02AE)
+#define MT6325_INT_STATUS1 (MT6325_PMIC_REG_BASE + 0x02B0)
+#define MT6325_INT_STATUS2 (MT6325_PMIC_REG_BASE + 0x02B2)
+#define MT6325_OC_GEAR_0 (MT6325_PMIC_REG_BASE + 0x02B4)
+#define MT6325_FQMTR_CON0 (MT6325_PMIC_REG_BASE + 0x02B6)
+#define MT6325_FQMTR_CON1 (MT6325_PMIC_REG_BASE + 0x02B8)
+#define MT6325_FQMTR_CON2 (MT6325_PMIC_REG_BASE + 0x02BA)
+#define MT6325_RG_SPI_CON (MT6325_PMIC_REG_BASE + 0x02BC)
+#define MT6325_DEW_DIO_EN (MT6325_PMIC_REG_BASE + 0x02BE)
+#define MT6325_DEW_READ_TEST (MT6325_PMIC_REG_BASE + 0x02C0)
+#define MT6325_DEW_WRITE_TEST (MT6325_PMIC_REG_BASE + 0x02C2)
+#define MT6325_DEW_CRC_SWRST (MT6325_PMIC_REG_BASE + 0x02C4)
+#define MT6325_DEW_CRC_EN (MT6325_PMIC_REG_BASE + 0x02C6)
+#define MT6325_DEW_CRC_VAL (MT6325_PMIC_REG_BASE + 0x02C8)
+#define MT6325_DEW_DBG_MON_SEL (MT6325_PMIC_REG_BASE + 0x02CA)
+#define MT6325_DEW_CIPHER_KEY_SEL (MT6325_PMIC_REG_BASE + 0x02CC)
+#define MT6325_DEW_CIPHER_IV_SEL (MT6325_PMIC_REG_BASE + 0x02CE)
+#define MT6325_DEW_CIPHER_EN (MT6325_PMIC_REG_BASE + 0x02D0)
+#define MT6325_DEW_CIPHER_RDY (MT6325_PMIC_REG_BASE + 0x02D2)
+#define MT6325_DEW_CIPHER_MODE (MT6325_PMIC_REG_BASE + 0x02D4)
+#define MT6325_DEW_CIPHER_SWRST (MT6325_PMIC_REG_BASE + 0x02D6)
+#define MT6325_DEW_RDDMY_NO (MT6325_PMIC_REG_BASE + 0x02D8)
+#define MT6325_INT_TYPE_CON0 (MT6325_PMIC_REG_BASE + 0x02DA)
+#define MT6325_INT_TYPE_CON0_SET (MT6325_PMIC_REG_BASE + 0x02DC)
+#define MT6325_INT_TYPE_CON0_CLR (MT6325_PMIC_REG_BASE + 0x02DE)
+#define MT6325_INT_TYPE_CON1 (MT6325_PMIC_REG_BASE + 0x02E0)
+#define MT6325_INT_TYPE_CON1_SET (MT6325_PMIC_REG_BASE + 0x02E2)
+#define MT6325_INT_TYPE_CON1_CLR (MT6325_PMIC_REG_BASE + 0x02E4)
+#define MT6325_INT_TYPE_CON2 (MT6325_PMIC_REG_BASE + 0x02E6)
+#define MT6325_INT_TYPE_CON2_SET (MT6325_PMIC_REG_BASE + 0x02E8)
+#define MT6325_INT_TYPE_CON2_CLR (MT6325_PMIC_REG_BASE + 0x02EA)
+#define MT6325_INT_STA (MT6325_PMIC_REG_BASE + 0x02EC)
+#define MT6325_BUCK_ALL_CON0 (MT6325_PMIC_REG_BASE + 0x0400)
+#define MT6325_BUCK_ALL_CON1 (MT6325_PMIC_REG_BASE + 0x0402)
+#define MT6325_BUCK_ALL_CON2 (MT6325_PMIC_REG_BASE + 0x0404)
+#define MT6325_BUCK_ALL_CON3 (MT6325_PMIC_REG_BASE + 0x0406)
+#define MT6325_BUCK_ALL_CON4 (MT6325_PMIC_REG_BASE + 0x0408)
+#define MT6325_BUCK_ALL_CON5 (MT6325_PMIC_REG_BASE + 0x040A)
+#define MT6325_BUCK_ALL_CON6 (MT6325_PMIC_REG_BASE + 0x040C)
+#define MT6325_BUCK_ALL_CON7 (MT6325_PMIC_REG_BASE + 0x040E)
+#define MT6325_BUCK_ALL_CON8 (MT6325_PMIC_REG_BASE + 0x0410)
+#define MT6325_BUCK_ALL_CON9 (MT6325_PMIC_REG_BASE + 0x0412)
+#define MT6325_BUCK_ALL_CON10 (MT6325_PMIC_REG_BASE + 0x0414)
+#define MT6325_BUCK_ALL_CON11 (MT6325_PMIC_REG_BASE + 0x0416)
+#define MT6325_BUCK_ALL_CON12 (MT6325_PMIC_REG_BASE + 0x0418)
+#define MT6325_BUCK_ALL_CON13 (MT6325_PMIC_REG_BASE + 0x041A)
+#define MT6325_BUCK_ALL_CON14 (MT6325_PMIC_REG_BASE + 0x041C)
+#define MT6325_BUCK_ALL_CON15 (MT6325_PMIC_REG_BASE + 0x041E)
+#define MT6325_BUCK_ALL_CON16 (MT6325_PMIC_REG_BASE + 0x0420)
+#define MT6325_BUCK_ALL_CON17 (MT6325_PMIC_REG_BASE + 0x0422)
+#define MT6325_BUCK_ALL_CON18 (MT6325_PMIC_REG_BASE + 0x0424)
+#define MT6325_BUCK_ALL_CON19 (MT6325_PMIC_REG_BASE + 0x0426)
+#define MT6325_BUCK_ALL_CON20 (MT6325_PMIC_REG_BASE + 0x0428)
+#define MT6325_BUCK_ALL_CON21 (MT6325_PMIC_REG_BASE + 0x042A)
+#define MT6325_BUCK_ALL_CON22 (MT6325_PMIC_REG_BASE + 0x042C)
+#define MT6325_BUCK_ALL_CON23 (MT6325_PMIC_REG_BASE + 0x042E)
+#define MT6325_BUCK_ALL_CON24 (MT6325_PMIC_REG_BASE + 0x0430)
+#define MT6325_BUCK_ALL_CON25 (MT6325_PMIC_REG_BASE + 0x0432)
+#define MT6325_BUCK_ALL_CON26 (MT6325_PMIC_REG_BASE + 0x0434)
+#define MT6325_BUCK_ALL_CON27 (MT6325_PMIC_REG_BASE + 0x0436)
+#define MT6325_BUCK_ALL_CON28 (MT6325_PMIC_REG_BASE + 0x0438)
+#define MT6325_VDRAM_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x043A)
+#define MT6325_VDRAM_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x043C)
+#define MT6325_VDRAM_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x043E)
+#define MT6325_VDRAM_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0440)
+#define MT6325_VDRAM_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0442)
+#define MT6325_VCORE1_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0444)
+#define MT6325_VCORE1_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0446)
+#define MT6325_VCORE1_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0448)
+#define MT6325_VCORE1_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x044A)
+#define MT6325_VCORE1_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x044C)
+#define MT6325_SMPS_TOP_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x044E)
+#define MT6325_SMPS_TOP_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0450)
+#define MT6325_SMPS_TOP_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0452)
+#define MT6325_SMPS_TOP_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0454)
+#define MT6325_SMPS_TOP_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0456)
+#define MT6325_SMPS_TOP_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0458)
+#define MT6325_SMPS_TOP_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x045A)
+#define MT6325_SMPS_TOP_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x045C)
+#define MT6325_SMPS_TOP_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x045E)
+#define MT6325_SMPS_TOP_ANA_CON9 (MT6325_PMIC_REG_BASE + 0x0460)
+#define MT6325_VDVFS1_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0462)
+#define MT6325_VDVFS1_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0464)
+#define MT6325_VDVFS1_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0466)
+#define MT6325_VDVFS1_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0468)
+#define MT6325_VDVFS1_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x046A)
+#define MT6325_VDVFS1_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x046C)
+#define MT6325_VDVFS1_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x046E)
+#define MT6325_VDVFS1_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0470)
+#define MT6325_VGPU_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0472)
+#define MT6325_VGPU_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0474)
+#define MT6325_VGPU_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0476)
+#define MT6325_VGPU_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0478)
+#define MT6325_VGPU_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x047A)
+#define MT6325_VPA_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x047C)
+#define MT6325_VPA_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x047E)
+#define MT6325_VPA_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0480)
+#define MT6325_VPA_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0482)
+#define MT6325_VCORE2_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0484)
+#define MT6325_VCORE2_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0486)
+#define MT6325_VCORE2_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0488)
+#define MT6325_VCORE2_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x048A)
+#define MT6325_VCORE2_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x048C)
+#define MT6325_VIO18_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x048E)
+#define MT6325_VIO18_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0490)
+#define MT6325_VIO18_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0492)
+#define MT6325_VIO18_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0494)
+#define MT6325_VIO18_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0496)
+#define MT6325_VRF18_0_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0498)
+#define MT6325_VRF18_0_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x049A)
+#define MT6325_VRF18_0_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x049C)
+#define MT6325_VRF18_0_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x049E)
+#define MT6325_VRF18_0_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x04A0)
+#define MT6325_VDVFS11_CON0 (MT6325_PMIC_REG_BASE + 0x04A2)
+#define MT6325_VDVFS11_CON7 (MT6325_PMIC_REG_BASE + 0x04B0)
+#define MT6325_VDVFS11_CON8 (MT6325_PMIC_REG_BASE + 0x04B2)
+#define MT6325_VDVFS11_CON9 (MT6325_PMIC_REG_BASE + 0x04B4)
+#define MT6325_VDVFS11_CON10 (MT6325_PMIC_REG_BASE + 0x04B6)
+#define MT6325_VDVFS11_CON11 (MT6325_PMIC_REG_BASE + 0x04B8)
+#define MT6325_VDVFS11_CON12 (MT6325_PMIC_REG_BASE + 0x04BA)
+#define MT6325_VDVFS11_CON13 (MT6325_PMIC_REG_BASE + 0x04BC)
+#define MT6325_VDVFS11_CON14 (MT6325_PMIC_REG_BASE + 0x04BE)
+#define MT6325_VDVFS11_CON18 (MT6325_PMIC_REG_BASE + 0x04C6)
+#define MT6325_VDVFS12_CON0 (MT6325_PMIC_REG_BASE + 0x04C8)
+#define MT6325_VDVFS12_CON7 (MT6325_PMIC_REG_BASE + 0x04D6)
+#define MT6325_VDVFS12_CON8 (MT6325_PMIC_REG_BASE + 0x04D8)
+#define MT6325_VDVFS12_CON9 (MT6325_PMIC_REG_BASE + 0x04DA)
+#define MT6325_VDVFS12_CON10 (MT6325_PMIC_REG_BASE + 0x04DC)
+#define MT6325_VDVFS12_CON11 (MT6325_PMIC_REG_BASE + 0x04DE)
+#define MT6325_VDVFS12_CON12 (MT6325_PMIC_REG_BASE + 0x04E0)
+#define MT6325_VDVFS12_CON13 (MT6325_PMIC_REG_BASE + 0x04E2)
+#define MT6325_VDVFS12_CON14 (MT6325_PMIC_REG_BASE + 0x04E4)
+#define MT6325_VDVFS12_CON18 (MT6325_PMIC_REG_BASE + 0x04EC)
+#define MT6325_VSRAM_DVFS1_CON0 (MT6325_PMIC_REG_BASE + 0x04EE)
+#define MT6325_VSRAM_DVFS1_CON7 (MT6325_PMIC_REG_BASE + 0x04FC)
+#define MT6325_VSRAM_DVFS1_CON8 (MT6325_PMIC_REG_BASE + 0x04FE)
+#define MT6325_VSRAM_DVFS1_CON9 (MT6325_PMIC_REG_BASE + 0x0500)
+#define MT6325_VSRAM_DVFS1_CON10 (MT6325_PMIC_REG_BASE + 0x0502)
+#define MT6325_VSRAM_DVFS1_CON11 (MT6325_PMIC_REG_BASE + 0x0504)
+#define MT6325_VSRAM_DVFS1_CON12 (MT6325_PMIC_REG_BASE + 0x0506)
+#define MT6325_VSRAM_DVFS1_CON13 (MT6325_PMIC_REG_BASE + 0x0508)
+#define MT6325_VSRAM_DVFS1_CON14 (MT6325_PMIC_REG_BASE + 0x050A)
+#define MT6325_VSRAM_DVFS1_CON18 (MT6325_PMIC_REG_BASE + 0x0512)
+#define MT6325_VDRAM_CON0 (MT6325_PMIC_REG_BASE + 0x0514)
+#define MT6325_VDRAM_CON7 (MT6325_PMIC_REG_BASE + 0x0522)
+#define MT6325_VDRAM_CON8 (MT6325_PMIC_REG_BASE + 0x0524)
+#define MT6325_VDRAM_CON9 (MT6325_PMIC_REG_BASE + 0x0526)
+#define MT6325_VDRAM_CON10 (MT6325_PMIC_REG_BASE + 0x0528)
+#define MT6325_VDRAM_CON11 (MT6325_PMIC_REG_BASE + 0x052A)
+#define MT6325_VDRAM_CON12 (MT6325_PMIC_REG_BASE + 0x052C)
+#define MT6325_VDRAM_CON13 (MT6325_PMIC_REG_BASE + 0x052E)
+#define MT6325_VDRAM_CON14 (MT6325_PMIC_REG_BASE + 0x0530)
+#define MT6325_VDRAM_CON15 (MT6325_PMIC_REG_BASE + 0x0532)
+#define MT6325_VDRAM_CON18 (MT6325_PMIC_REG_BASE + 0x0538)
+#define MT6325_VRF18_0_CON0 (MT6325_PMIC_REG_BASE + 0x053A)
+#define MT6325_VRF18_0_CON7 (MT6325_PMIC_REG_BASE + 0x0548)
+#define MT6325_VRF18_0_CON8 (MT6325_PMIC_REG_BASE + 0x054A)
+#define MT6325_VRF18_0_CON9 (MT6325_PMIC_REG_BASE + 0x054C)
+#define MT6325_VRF18_0_CON10 (MT6325_PMIC_REG_BASE + 0x054E)
+#define MT6325_VRF18_0_CON11 (MT6325_PMIC_REG_BASE + 0x0550)
+#define MT6325_VRF18_0_CON12 (MT6325_PMIC_REG_BASE + 0x0552)
+#define MT6325_VRF18_0_CON13 (MT6325_PMIC_REG_BASE + 0x0554)
+#define MT6325_VRF18_0_CON14 (MT6325_PMIC_REG_BASE + 0x0556)
+#define MT6325_VRF18_0_CON15 (MT6325_PMIC_REG_BASE + 0x0558)
+#define MT6325_VRF18_0_CON18 (MT6325_PMIC_REG_BASE + 0x055E)
+#define MT6325_VGPU_CON0 (MT6325_PMIC_REG_BASE + 0x0600)
+#define MT6325_VGPU_CON7 (MT6325_PMIC_REG_BASE + 0x060E)
+#define MT6325_VGPU_CON8 (MT6325_PMIC_REG_BASE + 0x0610)
+#define MT6325_VGPU_CON9 (MT6325_PMIC_REG_BASE + 0x0612)
+#define MT6325_VGPU_CON10 (MT6325_PMIC_REG_BASE + 0x0614)
+#define MT6325_VGPU_CON11 (MT6325_PMIC_REG_BASE + 0x0616)
+#define MT6325_VGPU_CON12 (MT6325_PMIC_REG_BASE + 0x0618)
+#define MT6325_VGPU_CON13 (MT6325_PMIC_REG_BASE + 0x061A)
+#define MT6325_VGPU_CON14 (MT6325_PMIC_REG_BASE + 0x061C)
+#define MT6325_VGPU_CON15 (MT6325_PMIC_REG_BASE + 0x061E)
+#define MT6325_VGPU_CON16 (MT6325_PMIC_REG_BASE + 0x0620)
+#define MT6325_VGPU_CON17 (MT6325_PMIC_REG_BASE + 0x0622)
+#define MT6325_VGPU_CON18 (MT6325_PMIC_REG_BASE + 0x0624)
+#define MT6325_VCORE1_CON0 (MT6325_PMIC_REG_BASE + 0x0626)
+#define MT6325_VCORE1_CON7 (MT6325_PMIC_REG_BASE + 0x0634)
+#define MT6325_VCORE1_CON8 (MT6325_PMIC_REG_BASE + 0x0636)
+#define MT6325_VCORE1_CON9 (MT6325_PMIC_REG_BASE + 0x0638)
+#define MT6325_VCORE1_CON10 (MT6325_PMIC_REG_BASE + 0x063A)
+#define MT6325_VCORE1_CON11 (MT6325_PMIC_REG_BASE + 0x063C)
+#define MT6325_VCORE1_CON12 (MT6325_PMIC_REG_BASE + 0x063E)
+#define MT6325_VCORE1_CON13 (MT6325_PMIC_REG_BASE + 0x0640)
+#define MT6325_VCORE1_CON14 (MT6325_PMIC_REG_BASE + 0x0642)
+#define MT6325_VCORE1_CON15 (MT6325_PMIC_REG_BASE + 0x0644)
+#define MT6325_VCORE1_CON16 (MT6325_PMIC_REG_BASE + 0x0646)
+#define MT6325_VCORE1_CON17 (MT6325_PMIC_REG_BASE + 0x0648)
+#define MT6325_VCORE1_CON18 (MT6325_PMIC_REG_BASE + 0x064A)
+#define MT6325_VCORE2_CON0 (MT6325_PMIC_REG_BASE + 0x064C)
+#define MT6325_VCORE2_CON7 (MT6325_PMIC_REG_BASE + 0x065A)
+#define MT6325_VCORE2_CON8 (MT6325_PMIC_REG_BASE + 0x065C)
+#define MT6325_VCORE2_CON9 (MT6325_PMIC_REG_BASE + 0x065E)
+#define MT6325_VCORE2_CON10 (MT6325_PMIC_REG_BASE + 0x0660)
+#define MT6325_VCORE2_CON11 (MT6325_PMIC_REG_BASE + 0x0662)
+#define MT6325_VCORE2_CON12 (MT6325_PMIC_REG_BASE + 0x0664)
+#define MT6325_VCORE2_CON13 (MT6325_PMIC_REG_BASE + 0x0666)
+#define MT6325_VCORE2_CON14 (MT6325_PMIC_REG_BASE + 0x0668)
+#define MT6325_VCORE2_CON15 (MT6325_PMIC_REG_BASE + 0x066A)
+#define MT6325_VCORE2_CON16 (MT6325_PMIC_REG_BASE + 0x066C)
+#define MT6325_VCORE2_CON17 (MT6325_PMIC_REG_BASE + 0x066E)
+#define MT6325_VCORE2_CON18 (MT6325_PMIC_REG_BASE + 0x0670)
+#define MT6325_VCORE2_CON19 (MT6325_PMIC_REG_BASE + 0x0672)
+#define MT6325_VCORE2_CON20 (MT6325_PMIC_REG_BASE + 0x0674)
+#define MT6325_VIO18_CON0 (MT6325_PMIC_REG_BASE + 0x0676)
+#define MT6325_VIO18_CON7 (MT6325_PMIC_REG_BASE + 0x0684)
+#define MT6325_VIO18_CON8 (MT6325_PMIC_REG_BASE + 0x0686)
+#define MT6325_VIO18_CON9 (MT6325_PMIC_REG_BASE + 0x0688)
+#define MT6325_VIO18_CON10 (MT6325_PMIC_REG_BASE + 0x068A)
+#define MT6325_VIO18_CON11 (MT6325_PMIC_REG_BASE + 0x068C)
+#define MT6325_VIO18_CON12 (MT6325_PMIC_REG_BASE + 0x068E)
+#define MT6325_VIO18_CON13 (MT6325_PMIC_REG_BASE + 0x0690)
+#define MT6325_VIO18_CON14 (MT6325_PMIC_REG_BASE + 0x0692)
+#define MT6325_VIO18_CON15 (MT6325_PMIC_REG_BASE + 0x0694)
+#define MT6325_VIO18_CON16 (MT6325_PMIC_REG_BASE + 0x0696)
+#define MT6325_VIO18_CON17 (MT6325_PMIC_REG_BASE + 0x0698)
+#define MT6325_VIO18_CON18 (MT6325_PMIC_REG_BASE + 0x069A)
+#define MT6325_VPA_CON0 (MT6325_PMIC_REG_BASE + 0x069C)
+#define MT6325_VPA_CON7 (MT6325_PMIC_REG_BASE + 0x06AA)
+#define MT6325_VPA_CON8 (MT6325_PMIC_REG_BASE + 0x06AC)
+#define MT6325_VPA_CON9 (MT6325_PMIC_REG_BASE + 0x06AE)
+#define MT6325_VPA_CON10 (MT6325_PMIC_REG_BASE + 0x06B0)
+#define MT6325_VPA_CON11 (MT6325_PMIC_REG_BASE + 0x06B2)
+#define MT6325_VPA_CON12 (MT6325_PMIC_REG_BASE + 0x06B4)
+#define MT6325_VPA_CON13 (MT6325_PMIC_REG_BASE + 0x06B6)
+#define MT6325_VPA_CON14 (MT6325_PMIC_REG_BASE + 0x06B8)
+#define MT6325_VPA_CON15 (MT6325_PMIC_REG_BASE + 0x06BA)
+#define MT6325_VPA_CON16 (MT6325_PMIC_REG_BASE + 0x06BC)
+#define MT6325_VPA_CON17 (MT6325_PMIC_REG_BASE + 0x06BE)
+#define MT6325_VPA_CON18 (MT6325_PMIC_REG_BASE + 0x06C0)
+#define MT6325_VPA_CON19 (MT6325_PMIC_REG_BASE + 0x06C2)
+#define MT6325_VPA_CON20 (MT6325_PMIC_REG_BASE + 0x06C4)
+#define MT6325_VPA_CON21 (MT6325_PMIC_REG_BASE + 0x06C6)
+#define MT6325_VPA_CON22 (MT6325_PMIC_REG_BASE + 0x06C8)
+#define MT6325_VPA_CON23 (MT6325_PMIC_REG_BASE + 0x06CA)
+#define MT6325_BUCK_K_CON0 (MT6325_PMIC_REG_BASE + 0x06CC)
+#define MT6325_BUCK_K_CON1 (MT6325_PMIC_REG_BASE + 0x06CE)
+#define MT6325_BUCK_K_CON2 (MT6325_PMIC_REG_BASE + 0x06D0)
+#define MT6325_BUCK_K_CON3 (MT6325_PMIC_REG_BASE + 0x06D2)
+#define MT6325_ZCD_CON0 (MT6325_PMIC_REG_BASE + 0x0800)
+#define MT6325_ZCD_CON1 (MT6325_PMIC_REG_BASE + 0x0802)
+#define MT6325_ZCD_CON2 (MT6325_PMIC_REG_BASE + 0x0804)
+#define MT6325_ZCD_CON3 (MT6325_PMIC_REG_BASE + 0x0806)
+#define MT6325_ZCD_CON4 (MT6325_PMIC_REG_BASE + 0x0808)
+#define MT6325_ZCD_CON5 (MT6325_PMIC_REG_BASE + 0x080A)
+#define MT6325_ISINK0_CON0 (MT6325_PMIC_REG_BASE + 0x080C)
+#define MT6325_ISINK0_CON1 (MT6325_PMIC_REG_BASE + 0x080E)
+#define MT6325_ISINK0_CON2 (MT6325_PMIC_REG_BASE + 0x0810)
+#define MT6325_ISINK0_CON3 (MT6325_PMIC_REG_BASE + 0x0812)
+#define MT6325_ISINK1_CON0 (MT6325_PMIC_REG_BASE + 0x0814)
+#define MT6325_ISINK1_CON1 (MT6325_PMIC_REG_BASE + 0x0816)
+#define MT6325_ISINK1_CON2 (MT6325_PMIC_REG_BASE + 0x0818)
+#define MT6325_ISINK1_CON3 (MT6325_PMIC_REG_BASE + 0x081A)
+#define MT6325_ISINK2_CON0 (MT6325_PMIC_REG_BASE + 0x081C)
+#define MT6325_ISINK2_CON1 (MT6325_PMIC_REG_BASE + 0x081E)
+#define MT6325_ISINK2_CON2 (MT6325_PMIC_REG_BASE + 0x0820)
+#define MT6325_ISINK2_CON3 (MT6325_PMIC_REG_BASE + 0x0822)
+#define MT6325_ISINK3_CON0 (MT6325_PMIC_REG_BASE + 0x0824)
+#define MT6325_ISINK3_CON1 (MT6325_PMIC_REG_BASE + 0x0826)
+#define MT6325_ISINK3_CON2 (MT6325_PMIC_REG_BASE + 0x0828)
+#define MT6325_ISINK3_CON3 (MT6325_PMIC_REG_BASE + 0x082A)
+#define MT6325_ISINK_ANA0 (MT6325_PMIC_REG_BASE + 0x082C)
+#define MT6325_ISINK_ANA1 (MT6325_PMIC_REG_BASE + 0x082E)
+#define MT6325_ISINK_PHASE_DLY (MT6325_PMIC_REG_BASE + 0x0830)
+#define MT6325_ISINK_SFSTR (MT6325_PMIC_REG_BASE + 0x0832)
+#define MT6325_ISINK_EN_CTRL (MT6325_PMIC_REG_BASE + 0x0834)
+#define MT6325_ISINK_MODE_CTRL (MT6325_PMIC_REG_BASE + 0x0836)
+#define MT6325_ISINK_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0838)
+#define MT6325_LDO_CON0 (MT6325_PMIC_REG_BASE + 0x0A00)
+#define MT6325_LDO_CON1 (MT6325_PMIC_REG_BASE + 0x0A02)
+#define MT6325_LDO_CON2 (MT6325_PMIC_REG_BASE + 0x0A04)
+#define MT6325_LDO_CON3 (MT6325_PMIC_REG_BASE + 0x0A06)
+#define MT6325_LDO_CON4 (MT6325_PMIC_REG_BASE + 0x0A08)
+#define MT6325_LDO_CON5 (MT6325_PMIC_REG_BASE + 0x0A0A)
+#define MT6325_LDO_CON6 (MT6325_PMIC_REG_BASE + 0x0A0C)
+#define MT6325_LDO_CON7 (MT6325_PMIC_REG_BASE + 0x0A0E)
+#define MT6325_LDO_CON8 (MT6325_PMIC_REG_BASE + 0x0A10)
+#define MT6325_LDO_CON9 (MT6325_PMIC_REG_BASE + 0x0A12)
+#define MT6325_LDO_CON10 (MT6325_PMIC_REG_BASE + 0x0A14)
+#define MT6325_LDO_CON11 (MT6325_PMIC_REG_BASE + 0x0A16)
+#define MT6325_LDO_CON12 (MT6325_PMIC_REG_BASE + 0x0A18)
+#define MT6325_LDO_CON13 (MT6325_PMIC_REG_BASE + 0x0A1A)
+#define MT6325_LDO_CON14 (MT6325_PMIC_REG_BASE + 0x0A1C)
+#define MT6325_LDO_CON15 (MT6325_PMIC_REG_BASE + 0x0A1E)
+#define MT6325_LDO_CON16 (MT6325_PMIC_REG_BASE + 0x0A20)
+#define MT6325_LDO_CON17 (MT6325_PMIC_REG_BASE + 0x0A22)
+#define MT6325_LDO_CON18 (MT6325_PMIC_REG_BASE + 0x0A24)
+#define MT6325_LDO_CON19 (MT6325_PMIC_REG_BASE + 0x0A26)
+#define MT6325_LDO_CON20 (MT6325_PMIC_REG_BASE + 0x0A28)
+#define MT6325_LDO_CON21 (MT6325_PMIC_REG_BASE + 0x0A2A)
+#define MT6325_LDO_CON22 (MT6325_PMIC_REG_BASE + 0x0A2C)
+#define MT6325_LDO_CON23 (MT6325_PMIC_REG_BASE + 0x0A2E)
+#define MT6325_LDO_CON24 (MT6325_PMIC_REG_BASE + 0x0A30)
+#define MT6325_LDO_CON25 (MT6325_PMIC_REG_BASE + 0x0A32)
+#define MT6325_LDO_CON26 (MT6325_PMIC_REG_BASE + 0x0A34)
+#define MT6325_LDO_CON27 (MT6325_PMIC_REG_BASE + 0x0A36)
+#define MT6325_LDO_CON28 (MT6325_PMIC_REG_BASE + 0x0A38)
+#define MT6325_LDO_CON29 (MT6325_PMIC_REG_BASE + 0x0A3A)
+#define MT6325_LDO_CON30 (MT6325_PMIC_REG_BASE + 0x0A3C)
+#define MT6325_LDO_VCON0 (MT6325_PMIC_REG_BASE + 0x0A3E)
+#define MT6325_LDO_VCON1 (MT6325_PMIC_REG_BASE + 0x0A40)
+#define MT6325_LDO_VCON2 (MT6325_PMIC_REG_BASE + 0x0A42)
+#define MT6325_LDO_VCON3 (MT6325_PMIC_REG_BASE + 0x0A44)
+#define MT6325_LDO_VCON4 (MT6325_PMIC_REG_BASE + 0x0A46)
+#define MT6325_LDO_VCON5 (MT6325_PMIC_REG_BASE + 0x0A48)
+#define MT6325_LDO_VCON6 (MT6325_PMIC_REG_BASE + 0x0A4A)
+#define MT6325_LDO_VCON7 (MT6325_PMIC_REG_BASE + 0x0A4C)
+#define MT6325_LDO_VCON8 (MT6325_PMIC_REG_BASE + 0x0A4E)
+#define MT6325_LDO_VCON9 (MT6325_PMIC_REG_BASE + 0x0A50)
+#define MT6325_LDO_VCON10 (MT6325_PMIC_REG_BASE + 0x0A52)
+#define MT6325_LDO_VCON11 (MT6325_PMIC_REG_BASE + 0x0A54)
+#define MT6325_LDO_VCON13 (MT6325_PMIC_REG_BASE + 0x0A56)
+#define MT6325_LDO_VCON14 (MT6325_PMIC_REG_BASE + 0x0A58)
+#define MT6325_LDO_VCON15 (MT6325_PMIC_REG_BASE + 0x0A5A)
+#define MT6325_LDO_VCON16 (MT6325_PMIC_REG_BASE + 0x0A5C)
+#define MT6325_LDO_RSV0 (MT6325_PMIC_REG_BASE + 0x0A5E)
+#define MT6325_LDO_RSV1 (MT6325_PMIC_REG_BASE + 0x0A60)
+#define MT6325_LDO_RSV2 (MT6325_PMIC_REG_BASE + 0x0A62)
+#define MT6325_LDO_RSV3 (MT6325_PMIC_REG_BASE + 0x0A64)
+#define MT6325_LDO_OCFB0 (MT6325_PMIC_REG_BASE + 0x0A66)
+#define MT6325_LDO_OCFB1 (MT6325_PMIC_REG_BASE + 0x0A68)
+#define MT6325_LDO_OCFB2 (MT6325_PMIC_REG_BASE + 0x0A6A)
+#define MT6325_LDO_OCFB3 (MT6325_PMIC_REG_BASE + 0x0A6C)
+#define MT6325_LDO_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0A6E)
+#define MT6325_BIF_CON0 (MT6325_PMIC_REG_BASE + 0x0A70)
+#define MT6325_BIF_CON1 (MT6325_PMIC_REG_BASE + 0x0A72)
+#define MT6325_BIF_CON2 (MT6325_PMIC_REG_BASE + 0x0A74)
+#define MT6325_BIF_CON3 (MT6325_PMIC_REG_BASE + 0x0A76)
+#define MT6325_BIF_CON4 (MT6325_PMIC_REG_BASE + 0x0A78)
+#define MT6325_BIF_CON5 (MT6325_PMIC_REG_BASE + 0x0A7A)
+#define MT6325_BIF_CON6 (MT6325_PMIC_REG_BASE + 0x0A7C)
+#define MT6325_BIF_CON7 (MT6325_PMIC_REG_BASE + 0x0A7E)
+#define MT6325_BIF_CON8 (MT6325_PMIC_REG_BASE + 0x0A80)
+#define MT6325_BIF_CON9 (MT6325_PMIC_REG_BASE + 0x0A82)
+#define MT6325_BIF_CON10 (MT6325_PMIC_REG_BASE + 0x0A84)
+#define MT6325_BIF_CON11 (MT6325_PMIC_REG_BASE + 0x0A86)
+#define MT6325_BIF_CON12 (MT6325_PMIC_REG_BASE + 0x0A88)
+#define MT6325_BIF_CON13 (MT6325_PMIC_REG_BASE + 0x0A8A)
+#define MT6325_BIF_CON14 (MT6325_PMIC_REG_BASE + 0x0A8C)
+#define MT6325_BIF_CON15 (MT6325_PMIC_REG_BASE + 0x0A8E)
+#define MT6325_BIF_CON16 (MT6325_PMIC_REG_BASE + 0x0A90)
+#define MT6325_BIF_CON17 (MT6325_PMIC_REG_BASE + 0x0A92)
+#define MT6325_BIF_CON18 (MT6325_PMIC_REG_BASE + 0x0A94)
+#define MT6325_BIF_CON19 (MT6325_PMIC_REG_BASE + 0x0A96)
+#define MT6325_BIF_CON20 (MT6325_PMIC_REG_BASE + 0x0A98)
+#define MT6325_BIF_CON21 (MT6325_PMIC_REG_BASE + 0x0A9A)
+#define MT6325_BIF_CON22 (MT6325_PMIC_REG_BASE + 0x0A9C)
+#define MT6325_BIF_CON23 (MT6325_PMIC_REG_BASE + 0x0A9E)
+#define MT6325_BIF_CON24 (MT6325_PMIC_REG_BASE + 0x0AA0)
+#define MT6325_BIF_CON25 (MT6325_PMIC_REG_BASE + 0x0AA2)
+#define MT6325_BIF_CON26 (MT6325_PMIC_REG_BASE + 0x0AA4)
+#define MT6325_BIF_CON27 (MT6325_PMIC_REG_BASE + 0x0AA6)
+#define MT6325_BIF_CON28 (MT6325_PMIC_REG_BASE + 0x0AA8)
+#define MT6325_BIF_CON29 (MT6325_PMIC_REG_BASE + 0x0AAA)
+#define MT6325_BIF_CON30 (MT6325_PMIC_REG_BASE + 0x0AAC)
+#define MT6325_BIF_CON31 (MT6325_PMIC_REG_BASE + 0x0AAE)
+#define MT6325_BIF_CON32 (MT6325_PMIC_REG_BASE + 0x0AB0)
+#define MT6325_BIF_CON33 (MT6325_PMIC_REG_BASE + 0x0AB2)
+#define MT6325_BIF_CON34 (MT6325_PMIC_REG_BASE + 0x0AB4)
+#define MT6325_BIF_CON35 (MT6325_PMIC_REG_BASE + 0x0AB6)
+#define MT6325_BIF_CON36 (MT6325_PMIC_REG_BASE + 0x0AB8)
+#define MT6325_BATON_CON0 (MT6325_PMIC_REG_BASE + 0x0ABA)
+#define MT6325_BIF_CON37 (MT6325_PMIC_REG_BASE + 0x0ABC)
+#define MT6325_BIF_CON38 (MT6325_PMIC_REG_BASE + 0x0ABE)
+#define MT6325_BIF_CON39 (MT6325_PMIC_REG_BASE + 0x0AC0)
+#define MT6325_SPK_CON0 (MT6325_PMIC_REG_BASE + 0x0AC2)
+#define MT6325_SPK_CON1 (MT6325_PMIC_REG_BASE + 0x0AC4)
+#define MT6325_SPK_CON2 (MT6325_PMIC_REG_BASE + 0x0AC6)
+#define MT6325_SPK_CON3 (MT6325_PMIC_REG_BASE + 0x0AC8)
+#define MT6325_SPK_CON4 (MT6325_PMIC_REG_BASE + 0x0ACA)
+#define MT6325_SPK_CON5 (MT6325_PMIC_REG_BASE + 0x0ACC)
+#define MT6325_SPK_CON6 (MT6325_PMIC_REG_BASE + 0x0ACE)
+#define MT6325_SPK_CON7 (MT6325_PMIC_REG_BASE + 0x0AD0)
+#define MT6325_SPK_CON8 (MT6325_PMIC_REG_BASE + 0x0AD2)
+#define MT6325_SPK_CON9 (MT6325_PMIC_REG_BASE + 0x0AD4)
+#define MT6325_SPK_CON10 (MT6325_PMIC_REG_BASE + 0x0AD6)
+#define MT6325_SPK_CON11 (MT6325_PMIC_REG_BASE + 0x0AD8)
+#define MT6325_SPK_CON12 (MT6325_PMIC_REG_BASE + 0x0ADA)
+#define MT6325_SPK_CON13 (MT6325_PMIC_REG_BASE + 0x0ADC)
+#define MT6325_SPK_CON14 (MT6325_PMIC_REG_BASE + 0x0ADE)
+#define MT6325_SPK_CON15 (MT6325_PMIC_REG_BASE + 0x0AE0)
+#define MT6325_SPK_CON16 (MT6325_PMIC_REG_BASE + 0x0AE2)
+#define MT6325_SPK_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0AE4)
+#define MT6325_SPK_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0AE6)
+#define MT6325_SPK_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0AE8)
+#define MT6325_OTP_CON0 (MT6325_PMIC_REG_BASE + 0x0C00)
+#define MT6325_OTP_CON1 (MT6325_PMIC_REG_BASE + 0x0C02)
+#define MT6325_OTP_CON2 (MT6325_PMIC_REG_BASE + 0x0C04)
+#define MT6325_OTP_CON3 (MT6325_PMIC_REG_BASE + 0x0C06)
+#define MT6325_OTP_CON4 (MT6325_PMIC_REG_BASE + 0x0C08)
+#define MT6325_OTP_CON5 (MT6325_PMIC_REG_BASE + 0x0C0A)
+#define MT6325_OTP_CON6 (MT6325_PMIC_REG_BASE + 0x0C0C)
+#define MT6325_OTP_CON7 (MT6325_PMIC_REG_BASE + 0x0C0E)
+#define MT6325_OTP_CON8 (MT6325_PMIC_REG_BASE + 0x0C10)
+#define MT6325_OTP_CON9 (MT6325_PMIC_REG_BASE + 0x0C12)
+#define MT6325_OTP_CON10 (MT6325_PMIC_REG_BASE + 0x0C14)
+#define MT6325_OTP_CON11 (MT6325_PMIC_REG_BASE + 0x0C16)
+#define MT6325_OTP_CON12 (MT6325_PMIC_REG_BASE + 0x0C18)
+#define MT6325_OTP_CON13 (MT6325_PMIC_REG_BASE + 0x0C1A)
+#define MT6325_OTP_CON14 (MT6325_PMIC_REG_BASE + 0x0C1C)
+#define MT6325_OTP_DOUT_0_15 (MT6325_PMIC_REG_BASE + 0x0C1E)
+#define MT6325_OTP_DOUT_16_31 (MT6325_PMIC_REG_BASE + 0x0C20)
+#define MT6325_OTP_DOUT_32_47 (MT6325_PMIC_REG_BASE + 0x0C22)
+#define MT6325_OTP_DOUT_48_63 (MT6325_PMIC_REG_BASE + 0x0C24)
+#define MT6325_OTP_DOUT_64_79 (MT6325_PMIC_REG_BASE + 0x0C26)
+#define MT6325_OTP_DOUT_80_95 (MT6325_PMIC_REG_BASE + 0x0C28)
+#define MT6325_OTP_DOUT_96_111 (MT6325_PMIC_REG_BASE + 0x0C2A)
+#define MT6325_OTP_DOUT_112_127 (MT6325_PMIC_REG_BASE + 0x0C2C)
+#define MT6325_OTP_DOUT_128_143 (MT6325_PMIC_REG_BASE + 0x0C2E)
+#define MT6325_OTP_DOUT_144_159 (MT6325_PMIC_REG_BASE + 0x0C30)
+#define MT6325_OTP_DOUT_160_175 (MT6325_PMIC_REG_BASE + 0x0C32)
+#define MT6325_OTP_DOUT_176_191 (MT6325_PMIC_REG_BASE + 0x0C34)
+#define MT6325_OTP_DOUT_192_207 (MT6325_PMIC_REG_BASE + 0x0C36)
+#define MT6325_OTP_DOUT_208_223 (MT6325_PMIC_REG_BASE + 0x0C38)
+#define MT6325_OTP_DOUT_224_239 (MT6325_PMIC_REG_BASE + 0x0C3A)
+#define MT6325_OTP_DOUT_240_255 (MT6325_PMIC_REG_BASE + 0x0C3C)
+#define MT6325_OTP_DOUT_256_271 (MT6325_PMIC_REG_BASE + 0x0C3E)
+#define MT6325_OTP_DOUT_272_287 (MT6325_PMIC_REG_BASE + 0x0C40)
+#define MT6325_OTP_DOUT_288_303 (MT6325_PMIC_REG_BASE + 0x0C42)
+#define MT6325_OTP_DOUT_304_319 (MT6325_PMIC_REG_BASE + 0x0C44)
+#define MT6325_OTP_DOUT_320_335 (MT6325_PMIC_REG_BASE + 0x0C46)
+#define MT6325_OTP_DOUT_336_351 (MT6325_PMIC_REG_BASE + 0x0C48)
+#define MT6325_OTP_DOUT_352_367 (MT6325_PMIC_REG_BASE + 0x0C4A)
+#define MT6325_OTP_DOUT_368_383 (MT6325_PMIC_REG_BASE + 0x0C4C)
+#define MT6325_OTP_DOUT_384_399 (MT6325_PMIC_REG_BASE + 0x0C4E)
+#define MT6325_OTP_DOUT_400_415 (MT6325_PMIC_REG_BASE + 0x0C50)
+#define MT6325_OTP_DOUT_416_431 (MT6325_PMIC_REG_BASE + 0x0C52)
+#define MT6325_OTP_DOUT_432_447 (MT6325_PMIC_REG_BASE + 0x0C54)
+#define MT6325_OTP_DOUT_448_463 (MT6325_PMIC_REG_BASE + 0x0C56)
+#define MT6325_OTP_DOUT_464_479 (MT6325_PMIC_REG_BASE + 0x0C58)
+#define MT6325_OTP_DOUT_480_495 (MT6325_PMIC_REG_BASE + 0x0C5A)
+#define MT6325_OTP_DOUT_496_511 (MT6325_PMIC_REG_BASE + 0x0C5C)
+#define MT6325_OTP_VAL_0_15 (MT6325_PMIC_REG_BASE + 0x0C5E)
+#define MT6325_OTP_VAL_16_31 (MT6325_PMIC_REG_BASE + 0x0C60)
+#define MT6325_OTP_VAL_32_47 (MT6325_PMIC_REG_BASE + 0x0C62)
+#define MT6325_OTP_VAL_48_63 (MT6325_PMIC_REG_BASE + 0x0C64)
+#define MT6325_OTP_VAL_64_79 (MT6325_PMIC_REG_BASE + 0x0C66)
+#define MT6325_OTP_VAL_80_95 (MT6325_PMIC_REG_BASE + 0x0C68)
+#define MT6325_OTP_VAL_96_111 (MT6325_PMIC_REG_BASE + 0x0C6A)
+#define MT6325_OTP_VAL_112_127 (MT6325_PMIC_REG_BASE + 0x0C6C)
+#define MT6325_OTP_VAL_128_143 (MT6325_PMIC_REG_BASE + 0x0C6E)
+#define MT6325_OTP_VAL_144_159 (MT6325_PMIC_REG_BASE + 0x0C70)
+#define MT6325_OTP_VAL_160_175 (MT6325_PMIC_REG_BASE + 0x0C72)
+#define MT6325_OTP_VAL_176_191 (MT6325_PMIC_REG_BASE + 0x0C74)
+#define MT6325_OTP_VAL_192_207 (MT6325_PMIC_REG_BASE + 0x0C76)
+#define MT6325_OTP_VAL_208_223 (MT6325_PMIC_REG_BASE + 0x0C78)
+#define MT6325_OTP_VAL_224_239 (MT6325_PMIC_REG_BASE + 0x0C7A)
+#define MT6325_OTP_VAL_240_255 (MT6325_PMIC_REG_BASE + 0x0C7C)
+#define MT6325_OTP_VAL_256_271 (MT6325_PMIC_REG_BASE + 0x0C7E)
+#define MT6325_OTP_VAL_272_287 (MT6325_PMIC_REG_BASE + 0x0C80)
+#define MT6325_OTP_VAL_288_303 (MT6325_PMIC_REG_BASE + 0x0C82)
+#define MT6325_OTP_VAL_304_319 (MT6325_PMIC_REG_BASE + 0x0C84)
+#define MT6325_OTP_VAL_320_335 (MT6325_PMIC_REG_BASE + 0x0C86)
+#define MT6325_OTP_VAL_336_351 (MT6325_PMIC_REG_BASE + 0x0C88)
+#define MT6325_OTP_VAL_352_367 (MT6325_PMIC_REG_BASE + 0x0C8A)
+#define MT6325_OTP_VAL_368_383 (MT6325_PMIC_REG_BASE + 0x0C8C)
+#define MT6325_OTP_VAL_384_399 (MT6325_PMIC_REG_BASE + 0x0C8E)
+#define MT6325_OTP_VAL_400_415 (MT6325_PMIC_REG_BASE + 0x0C90)
+#define MT6325_OTP_VAL_416_431 (MT6325_PMIC_REG_BASE + 0x0C92)
+#define MT6325_OTP_VAL_432_447 (MT6325_PMIC_REG_BASE + 0x0C94)
+#define MT6325_OTP_VAL_448_463 (MT6325_PMIC_REG_BASE + 0x0C96)
+#define MT6325_OTP_VAL_464_479 (MT6325_PMIC_REG_BASE + 0x0C98)
+#define MT6325_OTP_VAL_480_495 (MT6325_PMIC_REG_BASE + 0x0C9A)
+#define MT6325_OTP_VAL_496_511 (MT6325_PMIC_REG_BASE + 0x0C9C)
+#define MT6325_RTC_MIX_CON0 (MT6325_PMIC_REG_BASE + 0x0C9E)
+#define MT6325_RTC_MIX_CON1 (MT6325_PMIC_REG_BASE + 0x0CA0)
+#define MT6325_RTC_MIX_CON2 (MT6325_PMIC_REG_BASE + 0x0CA2)
+#define MT6325_FGADC_CON0 (MT6325_PMIC_REG_BASE + 0x0CA4)
+#define MT6325_FGADC_CON1 (MT6325_PMIC_REG_BASE + 0x0CA6)
+#define MT6325_FGADC_CON2 (MT6325_PMIC_REG_BASE + 0x0CA8)
+#define MT6325_FGADC_CON3 (MT6325_PMIC_REG_BASE + 0x0CAA)
+#define MT6325_FGADC_CON4 (MT6325_PMIC_REG_BASE + 0x0CAC)
+#define MT6325_FGADC_CON5 (MT6325_PMIC_REG_BASE + 0x0CAE)
+#define MT6325_FGADC_CON6 (MT6325_PMIC_REG_BASE + 0x0CB0)
+#define MT6325_FGADC_CON7 (MT6325_PMIC_REG_BASE + 0x0CB2)
+#define MT6325_FGADC_CON8 (MT6325_PMIC_REG_BASE + 0x0CB4)
+#define MT6325_FGADC_CON9 (MT6325_PMIC_REG_BASE + 0x0CB6)
+#define MT6325_FGADC_CON10 (MT6325_PMIC_REG_BASE + 0x0CB8)
+#define MT6325_FGADC_CON11 (MT6325_PMIC_REG_BASE + 0x0CBA)
+#define MT6325_FGADC_CON12 (MT6325_PMIC_REG_BASE + 0x0CBC)
+#define MT6325_FGADC_CON13 (MT6325_PMIC_REG_BASE + 0x0CBE)
+#define MT6325_FGADC_CON14 (MT6325_PMIC_REG_BASE + 0x0CC0)
+#define MT6325_FGADC_CON15 (MT6325_PMIC_REG_BASE + 0x0CC2)
+#define MT6325_FGADC_CON16 (MT6325_PMIC_REG_BASE + 0x0CC4)
+#define MT6325_FGADC_CON17 (MT6325_PMIC_REG_BASE + 0x0CC6)
+#define MT6325_FGADC_CON18 (MT6325_PMIC_REG_BASE + 0x0CC8)
+#define MT6325_FGADC_CON19 (MT6325_PMIC_REG_BASE + 0x0CCA)
+#define MT6325_FGADC_CON20 (MT6325_PMIC_REG_BASE + 0x0CCC)
+#define MT6325_FGADC_CON21 (MT6325_PMIC_REG_BASE + 0x0CCE)
+#define MT6325_FGADC_CON22 (MT6325_PMIC_REG_BASE + 0x0CD0)
+#define MT6325_FGADC_CON23 (MT6325_PMIC_REG_BASE + 0x0CD2)
+#define MT6325_FGADC_CON24 (MT6325_PMIC_REG_BASE + 0x0CD4)
+#define MT6325_FGADC_CON25 (MT6325_PMIC_REG_BASE + 0x0CD6)
+#define MT6325_FGADC_CON26 (MT6325_PMIC_REG_BASE + 0x0CD8)
+#define MT6325_FGADC_CON27 (MT6325_PMIC_REG_BASE + 0x0CDA)
+#define MT6325_FGADC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CDC)
+#define MT6325_AUDDEC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CDE)
+#define MT6325_AUDDEC_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0CE0)
+#define MT6325_AUDDEC_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0CE2)
+#define MT6325_AUDDEC_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0CE4)
+#define MT6325_AUDDEC_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0CE6)
+#define MT6325_AUDDEC_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0CE8)
+#define MT6325_AUDDEC_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x0CEA)
+#define MT6325_AUDDEC_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0CEC)
+#define MT6325_AUDDEC_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x0CEE)
+#define MT6325_AUDENC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CF0)
+#define MT6325_AUDENC_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0CF2)
+#define MT6325_AUDENC_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0CF4)
+#define MT6325_AUDENC_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0CF6)
+#define MT6325_AUDENC_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0CF8)
+#define MT6325_AUDENC_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0CFA)
+#define MT6325_AUDENC_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x0CFC)
+#define MT6325_AUDENC_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0CFE)
+#define MT6325_AUDENC_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x0D00)
+#define MT6325_AUDENC_ANA_CON9 (MT6325_PMIC_REG_BASE + 0x0D02)
+#define MT6325_AUDENC_ANA_CON11 (MT6325_PMIC_REG_BASE + 0x0D04)
+#define MT6325_AUDENC_ANA_CON12 (MT6325_PMIC_REG_BASE + 0x0D06)
+#define MT6325_AUDENC_ANA_CON13 (MT6325_PMIC_REG_BASE + 0x0D08)
+#define MT6325_AUDENC_ANA_CON14 (MT6325_PMIC_REG_BASE + 0x0D0A)
+#define MT6325_AUDENC_ANA_CON15 (MT6325_PMIC_REG_BASE + 0x0D0C)
+#define MT6325_AUDNCP_CLKDIV_CON0 (MT6325_PMIC_REG_BASE + 0x0D0E)
+#define MT6325_AUDNCP_CLKDIV_CON1 (MT6325_PMIC_REG_BASE + 0x0D10)
+#define MT6325_AUDNCP_CLKDIV_CON2 (MT6325_PMIC_REG_BASE + 0x0D12)
+#define MT6325_AUDNCP_CLKDIV_CON3 (MT6325_PMIC_REG_BASE + 0x0D14)
+#define MT6325_AUDNCP_CLKDIV_CON4 (MT6325_PMIC_REG_BASE + 0x0D16)
+#define MT6325_AUXADC_RSV0 (MT6325_PMIC_REG_BASE + 0x0E00)
+#define MT6325_AUXADC_STA0 (MT6325_PMIC_REG_BASE + 0x0E02)
+#define MT6325_AUXADC_STA1 (MT6325_PMIC_REG_BASE + 0x0E04)
+#define MT6325_AUXADC_RQST0 (MT6325_PMIC_REG_BASE + 0x0E06)
+#define MT6325_AUXADC_RQST0_SET (MT6325_PMIC_REG_BASE + 0x0E08)
+#define MT6325_AUXADC_RQST0_CLR (MT6325_PMIC_REG_BASE + 0x0E0A)
+#define MT6325_AUXADC_RQST1 (MT6325_PMIC_REG_BASE + 0x0E0C)
+#define MT6325_AUXADC_RQST1_SET (MT6325_PMIC_REG_BASE + 0x0E0E)
+#define MT6325_AUXADC_RQST1_CLR (MT6325_PMIC_REG_BASE + 0x0E10)
+#define MT6325_AUXADC_CK0 (MT6325_PMIC_REG_BASE + 0x0E12)
+#define MT6325_AUXADC_THR0 (MT6325_PMIC_REG_BASE + 0x0E14)
+#define MT6325_AUXADC_THR1 (MT6325_PMIC_REG_BASE + 0x0E16)
+#define MT6325_AUXADC_THR2 (MT6325_PMIC_REG_BASE + 0x0E18)
+#define MT6325_AUXADC_THR3 (MT6325_PMIC_REG_BASE + 0x0E1A)
+#define MT6325_AUXADC_THR4 (MT6325_PMIC_REG_BASE + 0x0E1C)
+#define MT6325_AUXADC_THR5 (MT6325_PMIC_REG_BASE + 0x0E1E)
+#define MT6325_AUXADC_THR6 (MT6325_PMIC_REG_BASE + 0x0E20)
+#define MT6325_AUXADC_THR7 (MT6325_PMIC_REG_BASE + 0x0E22)
+#define MT6325_AUXADC_DBG0 (MT6325_PMIC_REG_BASE + 0x0E24)
+#define MT6325_AUXADC_AUTORPT0 (MT6325_PMIC_REG_BASE + 0x0E26)
+#define MT6325_AUXADC_IMP0 (MT6325_PMIC_REG_BASE + 0x0E28)
+#define MT6325_AUXADC_VISMPS0_1 (MT6325_PMIC_REG_BASE + 0x0E2A)
+#define MT6325_AUXADC_VISMPS0_2 (MT6325_PMIC_REG_BASE + 0x0E2C)
+#define MT6325_AUXADC_VISMPS0_3 (MT6325_PMIC_REG_BASE + 0x0E2E)
+#define MT6325_AUXADC_VISMPS0_4 (MT6325_PMIC_REG_BASE + 0x0E30)
+#define MT6325_AUXADC_VISMPS0_5 (MT6325_PMIC_REG_BASE + 0x0E32)
+#define MT6325_AUXADC_VISMPS0_6 (MT6325_PMIC_REG_BASE + 0x0E34)
+#define MT6325_AUXADC_VISMPS0_7 (MT6325_PMIC_REG_BASE + 0x0E36)
+#define MT6325_AUXADC_LBAT2_1 (MT6325_PMIC_REG_BASE + 0x0E38)
+#define MT6325_AUXADC_LBAT2_2 (MT6325_PMIC_REG_BASE + 0x0E3A)
+#define MT6325_AUXADC_LBAT2_3 (MT6325_PMIC_REG_BASE + 0x0E3C)
+#define MT6325_AUXADC_LBAT2_4 (MT6325_PMIC_REG_BASE + 0x0E3E)
+#define MT6325_AUXADC_LBAT2_5 (MT6325_PMIC_REG_BASE + 0x0E40)
+#define MT6325_AUXADC_LBAT2_6 (MT6325_PMIC_REG_BASE + 0x0E42)
+#define MT6325_AUXADC_LBAT2_7 (MT6325_PMIC_REG_BASE + 0x0E44)
+#define MT6325_AUXADC_ADC0 (MT6325_PMIC_REG_BASE + 0x0E46)
+#define MT6325_AUXADC_ADC1 (MT6325_PMIC_REG_BASE + 0x0E48)
+#define MT6325_AUXADC_ADC2 (MT6325_PMIC_REG_BASE + 0x0E4A)
+#define MT6325_AUXADC_ADC3 (MT6325_PMIC_REG_BASE + 0x0E4C)
+#define MT6325_AUXADC_ADC4 (MT6325_PMIC_REG_BASE + 0x0E4E)
+#define MT6325_AUXADC_ADC5 (MT6325_PMIC_REG_BASE + 0x0E50)
+#define MT6325_AUXADC_ADC6 (MT6325_PMIC_REG_BASE + 0x0E52)
+#define MT6325_AUXADC_ADC7 (MT6325_PMIC_REG_BASE + 0x0E54)
+#define MT6325_AUXADC_ADC8 (MT6325_PMIC_REG_BASE + 0x0E56)
+#define MT6325_AUXADC_ADC9 (MT6325_PMIC_REG_BASE + 0x0E58)
+#define MT6325_AUXADC_ADC10 (MT6325_PMIC_REG_BASE + 0x0E5A)
+#define MT6325_AUXADC_ADC11 (MT6325_PMIC_REG_BASE + 0x0E5C)
+#define MT6325_AUXADC_ADC12 (MT6325_PMIC_REG_BASE + 0x0E5E)
+#define MT6325_AUXADC_ADC13 (MT6325_PMIC_REG_BASE + 0x0E60)
+#define MT6325_AUXADC_ADC14 (MT6325_PMIC_REG_BASE + 0x0E62)
+#define MT6325_AUXADC_ADC15 (MT6325_PMIC_REG_BASE + 0x0E64)
+#define MT6325_AUXADC_ADC16 (MT6325_PMIC_REG_BASE + 0x0E66)
+#define MT6325_AUXADC_ADC17 (MT6325_PMIC_REG_BASE + 0x0E68)
+#define MT6325_AUXADC_ADC18 (MT6325_PMIC_REG_BASE + 0x0E6A)
+#define MT6325_AUXADC_ADC19 (MT6325_PMIC_REG_BASE + 0x0E6C)
+#define MT6325_AUXADC_ADC20 (MT6325_PMIC_REG_BASE + 0x0E6E)
+#define MT6325_AUXADC_ADC21 (MT6325_PMIC_REG_BASE + 0x0E70)
+#define MT6325_AUXADC_ADC22 (MT6325_PMIC_REG_BASE + 0x0E72)
+#define MT6325_AUXADC_ADC23 (MT6325_PMIC_REG_BASE + 0x0E74)
+#define MT6325_AUXADC_ADC24 (MT6325_PMIC_REG_BASE + 0x0E76)
+#define MT6325_AUXADC_ADC25 (MT6325_PMIC_REG_BASE + 0x0E78)
+#define MT6325_AUXADC_ADC26 (MT6325_PMIC_REG_BASE + 0x0E7A)
+#define MT6325_AUXADC_ADC27 (MT6325_PMIC_REG_BASE + 0x0E7C)
+#define MT6325_AUXADC_ADC28 (MT6325_PMIC_REG_BASE + 0x0E7E)
+#define MT6325_AUXADC_ADC29 (MT6325_PMIC_REG_BASE + 0x0E80)
+#define MT6325_AUXADC_ADC30 (MT6325_PMIC_REG_BASE + 0x0E82)
+#define MT6325_AUXADC_RSV1 (MT6325_PMIC_REG_BASE + 0x0E84)
+#define MT6325_AUXADC_RSV2 (MT6325_PMIC_REG_BASE + 0x0E86)
+#define MT6325_AUXADC_CON0 (MT6325_PMIC_REG_BASE + 0x0E88)
+#define MT6325_AUXADC_CON1 (MT6325_PMIC_REG_BASE + 0x0E8A)
+#define MT6325_AUXADC_CON2 (MT6325_PMIC_REG_BASE + 0x0E8C)
+#define MT6325_AUXADC_CON3 (MT6325_PMIC_REG_BASE + 0x0E8E)
+#define MT6325_AUXADC_CON4 (MT6325_PMIC_REG_BASE + 0x0E90)
+#define MT6325_AUXADC_CON5 (MT6325_PMIC_REG_BASE + 0x0E92)
+#define MT6325_AUXADC_CON6 (MT6325_PMIC_REG_BASE + 0x0E94)
+#define MT6325_AUXADC_CON7 (MT6325_PMIC_REG_BASE + 0x0E96)
+#define MT6325_AUXADC_CON8 (MT6325_PMIC_REG_BASE + 0x0E98)
+#define MT6325_AUXADC_CON9 (MT6325_PMIC_REG_BASE + 0x0E9A)
+#define MT6325_AUXADC_CON10 (MT6325_PMIC_REG_BASE + 0x0E9C)
+#define MT6325_AUXADC_CON11 (MT6325_PMIC_REG_BASE + 0x0E9E)
+#define MT6325_AUXADC_CON12 (MT6325_PMIC_REG_BASE + 0x0EA0)
+#define MT6325_AUXADC_CON13 (MT6325_PMIC_REG_BASE + 0x0EA2)
+#define MT6325_AUXADC_CON14 (MT6325_PMIC_REG_BASE + 0x0EA4)
+#define MT6325_AUXADC_CON15 (MT6325_PMIC_REG_BASE + 0x0EA6)
+#define MT6325_AUXADC_CON16 (MT6325_PMIC_REG_BASE + 0x0EA8)
+#define MT6325_AUXADC_CON17 (MT6325_PMIC_REG_BASE + 0x0EAA)
+#define MT6325_AUXADC_CON18 (MT6325_PMIC_REG_BASE + 0x0EAC)
+#define MT6325_AUXADC_CON19 (MT6325_PMIC_REG_BASE + 0x0EAE)
+#define MT6325_AUXADC_CON20 (MT6325_PMIC_REG_BASE + 0x0EB0)
+#define MT6325_AUXADC_CON21 (MT6325_PMIC_REG_BASE + 0x0EB2)
+#define MT6325_AUXADC_CON22 (MT6325_PMIC_REG_BASE + 0x0EB4)
+#define MT6325_AUXADC_CON23 (MT6325_PMIC_REG_BASE + 0x0EB6)
+#define MT6325_AUXADC_CON24 (MT6325_PMIC_REG_BASE + 0x0EB8)
+#define MT6325_AUXADC_CON25 (MT6325_PMIC_REG_BASE + 0x0EBA)
+#define MT6325_AUXADC_CON26 (MT6325_PMIC_REG_BASE + 0x0EBC)
+#define MT6325_AUXADC_CON27 (MT6325_PMIC_REG_BASE + 0x0EBE)
+#define MT6325_ACCDET_CON0 (MT6325_PMIC_REG_BASE + 0x0EC0)
+#define MT6325_ACCDET_CON1 (MT6325_PMIC_REG_BASE + 0x0EC2)
+#define MT6325_ACCDET_CON2 (MT6325_PMIC_REG_BASE + 0x0EC4)
+#define MT6325_ACCDET_CON3 (MT6325_PMIC_REG_BASE + 0x0EC6)
+#define MT6325_ACCDET_CON4 (MT6325_PMIC_REG_BASE + 0x0EC8)
+#define MT6325_ACCDET_CON5 (MT6325_PMIC_REG_BASE + 0x0ECA)
+#define MT6325_ACCDET_CON6 (MT6325_PMIC_REG_BASE + 0x0ECC)
+#define MT6325_ACCDET_CON7 (MT6325_PMIC_REG_BASE + 0x0ECE)
+#define MT6325_ACCDET_CON8 (MT6325_PMIC_REG_BASE + 0x0ED0)
+#define MT6325_ACCDET_CON9 (MT6325_PMIC_REG_BASE + 0x0ED2)
+#define MT6325_ACCDET_CON10 (MT6325_PMIC_REG_BASE + 0x0ED4)
+#define MT6325_ACCDET_CON11 (MT6325_PMIC_REG_BASE + 0x0ED6)
+#define MT6325_ACCDET_CON12 (MT6325_PMIC_REG_BASE + 0x0ED8)
+#define MT6325_ACCDET_CON13 (MT6325_PMIC_REG_BASE + 0x0EDA)
+#define MT6325_ACCDET_CON14 (MT6325_PMIC_REG_BASE + 0x0EDC)
+#define MT6325_ACCDET_CON15 (MT6325_PMIC_REG_BASE + 0x0EDE)
+#define MT6325_ACCDET_CON16 (MT6325_PMIC_REG_BASE + 0x0EE0)
+#define MT6325_ACCDET_CON17 (MT6325_PMIC_REG_BASE + 0x0EE2)
+#define MT6325_ACCDET_CON18 (MT6325_PMIC_REG_BASE + 0x0EE4)
+#define MT6325_ACCDET_CON19 (MT6325_PMIC_REG_BASE + 0x0EE6)
+#define MT6325_ACCDET_CON20 (MT6325_PMIC_REG_BASE + 0x0EE8)
+#define MT6325_ACCDET_CON21 (MT6325_PMIC_REG_BASE + 0x0EEA)
+#define MT6325_ACCDET_CON22 (MT6325_PMIC_REG_BASE + 0x0EEC)
+#define MT6325_ACCDET_CON23 (MT6325_PMIC_REG_BASE + 0x0EEE)
+#define MT6325_ACCDET_CON24 (MT6325_PMIC_REG_BASE + 0x0EF0)
+#define MT6325_CHR_CON0 (MT6325_PMIC_REG_BASE + 0x0EF2)
+#define MT6325_CHR_CON1 (MT6325_PMIC_REG_BASE + 0x0EF4)
+#define MT6325_CHR_CON2 (MT6325_PMIC_REG_BASE + 0x0EF6)
+#define MT6325_CHR_CON3 (MT6325_PMIC_REG_BASE + 0x0EF8)
+#define MT6325_CHR_CON4 (MT6325_PMIC_REG_BASE + 0x0EFA)
+#define MT6325_CHR_CON5 (MT6325_PMIC_REG_BASE + 0x0EFC)
+#define MT6325_CHR_CON6 (MT6325_PMIC_REG_BASE + 0x0EFE)
+#define MT6325_CHR_CON7 (MT6325_PMIC_REG_BASE + 0x0F00)
+#define MT6325_CHR_CON8 (MT6325_PMIC_REG_BASE + 0x0F02)
+#define MT6325_CHR_CON9 (MT6325_PMIC_REG_BASE + 0x0F04)
+#define MT6325_CHR_CON10 (MT6325_PMIC_REG_BASE + 0x0F06)
+#define MT6325_CHR_CON11 (MT6325_PMIC_REG_BASE + 0x0F08)
+#define MT6325_CHR_CON12 (MT6325_PMIC_REG_BASE + 0x0F0A)
+#define MT6325_CHR_CON13 (MT6325_PMIC_REG_BASE + 0x0F0C)
+#define MT6325_CHR_CON14 (MT6325_PMIC_REG_BASE + 0x0F0E)
+#define MT6325_CHR_CON15 (MT6325_PMIC_REG_BASE + 0x0F10)
+#define MT6325_CHR_CON16 (MT6325_PMIC_REG_BASE + 0x0F12)
+#define MT6325_CHR_CON17 (MT6325_PMIC_REG_BASE + 0x0F14)
+#define MT6325_CHR_CON18 (MT6325_PMIC_REG_BASE + 0x0F16)
+#define MT6325_CHR_CON19 (MT6325_PMIC_REG_BASE + 0x0F18)
+#define MT6325_CHR_CON20 (MT6325_PMIC_REG_BASE + 0x0F1A)
+#define MT6325_CHR_CON21 (MT6325_PMIC_REG_BASE + 0x0F1C)
+#define MT6325_CHR_CON22 (MT6325_PMIC_REG_BASE + 0x0F1E)
+#define MT6325_CHR_CON23 (MT6325_PMIC_REG_BASE + 0x0F20)
+#define MT6325_CHR_CON24 (MT6325_PMIC_REG_BASE + 0x0F22)
+#define MT6325_CHR_CON25 (MT6325_PMIC_REG_BASE + 0x0F24)
+#define MT6325_CHR_CON26 (MT6325_PMIC_REG_BASE + 0x0F26)
+#define MT6325_CHR_CON27 (MT6325_PMIC_REG_BASE + 0x0F28)
+#define MT6325_CHR_CON28 (MT6325_PMIC_REG_BASE + 0x0F2A)
+#define MT6325_CHR_CON29 (MT6325_PMIC_REG_BASE + 0x0F2C)
+#define MT6325_CHR_CON30 (MT6325_PMIC_REG_BASE + 0x0F2E)
+#define MT6325_CHR_CON31 (MT6325_PMIC_REG_BASE + 0x0F30)
+#define MT6325_CHR_CON32 (MT6325_PMIC_REG_BASE + 0x0F32)
+#define MT6325_CHR_CON33 (MT6325_PMIC_REG_BASE + 0x0F34)
+#define MT6325_CHR_CON34 (MT6325_PMIC_REG_BASE + 0x0F36)
+#define MT6325_CHR_CON35 (MT6325_PMIC_REG_BASE + 0x0F38)
+#define MT6325_CHR_CON36 (MT6325_PMIC_REG_BASE + 0x0F3A)
+#define MT6325_CHR_CON37 (MT6325_PMIC_REG_BASE + 0x0F3C)
+#define MT6325_CHR_CON38 (MT6325_PMIC_REG_BASE + 0x0F3E)
+#define MT6325_CHR_CON39 (MT6325_PMIC_REG_BASE + 0x0F40)
+#define MT6325_CHR_CON40 (MT6325_PMIC_REG_BASE + 0x0F42)
+#define MT6325_CHR_CON41 (MT6325_PMIC_REG_BASE + 0x0F44)
+#define MT6325_EOSC_CALI_CON0 (MT6325_PMIC_REG_BASE + 0x0F46)
+#define MT6325_EOSC_CALI_CON1 (MT6325_PMIC_REG_BASE + 0x0F48)
+// mask is HEX; shift is Integer
+#define MT6325_THR_DET_DIS_MASK 0x1
+#define MT6325_THR_DET_DIS_SHIFT 0
+#define MT6325_RG_THR_TMODE_MASK 0x1
+#define MT6325_RG_THR_TMODE_SHIFT 1
+#define MT6325_RG_THR_TEMP_SEL_MASK 0x1
+#define MT6325_RG_THR_TEMP_SEL_SHIFT 2
+#define MT6325_RG_STRUP_THR_SEL_MASK 0x3
+#define MT6325_RG_STRUP_THR_SEL_SHIFT 3
+#define MT6325_THR_HWPDN_EN_MASK 0x1
+#define MT6325_THR_HWPDN_EN_SHIFT 5
+#define MT6325_RG_THRDET_SEL_MASK 0x1
+#define MT6325_RG_THRDET_SEL_SHIFT 6
+#define MT6325_RG_STRUP_IREF_TRIM_MASK 0x1F
+#define MT6325_RG_STRUP_IREF_TRIM_SHIFT 0
+#define MT6325_RG_USBDL_EN_MASK 0x1
+#define MT6325_RG_USBDL_EN_SHIFT 0
+#define MT6325_RG_FCHR_KEYDET_EN_MASK 0x1
+#define MT6325_RG_FCHR_KEYDET_EN_SHIFT 1
+#define MT6325_RG_FCHR_PU_EN_MASK 0x1
+#define MT6325_RG_FCHR_PU_EN_SHIFT 2
+#define MT6325_RG_EN_DRVSEL_MASK 0x1
+#define MT6325_RG_EN_DRVSEL_SHIFT 4
+#define MT6325_RG_RSTB_DRV_SEL_MASK 0x1
+#define MT6325_RG_RSTB_DRV_SEL_SHIFT 5
+#define MT6325_RG_VREF_BG_MASK 0x7
+#define MT6325_RG_VREF_BG_SHIFT 12
+#define MT6325_RG_PMU_RSV_MASK 0xF
+#define MT6325_RG_PMU_RSV_SHIFT 0
+#define MT6325_THR_TEST_MASK 0x3
+#define MT6325_THR_TEST_SHIFT 0
+#define MT6325_PMU_THR_DEB_MASK 0x7
+#define MT6325_PMU_THR_DEB_SHIFT 4
+#define MT6325_PMU_THR_STATUS_MASK 0x7
+#define MT6325_PMU_THR_STATUS_SHIFT 8
+#define MT6325_DDUVLO_DEB_EN_MASK 0x1
+#define MT6325_DDUVLO_DEB_EN_SHIFT 0
+#define MT6325_PWRBB_DEB_EN_MASK 0x1
+#define MT6325_PWRBB_DEB_EN_SHIFT 1
+#define MT6325_STRUP_OSC_EN_MASK 0x1
+#define MT6325_STRUP_OSC_EN_SHIFT 2
+#define MT6325_STRUP_OSC_EN_SEL_MASK 0x1
+#define MT6325_STRUP_OSC_EN_SEL_SHIFT 3
+#define MT6325_STRUP_FT_CTRL_MASK 0x3
+#define MT6325_STRUP_FT_CTRL_SHIFT 4
+#define MT6325_STRUP_PWRON_FORCE_MASK 0x1
+#define MT6325_STRUP_PWRON_FORCE_SHIFT 6
+#define MT6325_BIAS_GEN_EN_FORCE_MASK 0x1
+#define MT6325_BIAS_GEN_EN_FORCE_SHIFT 7
+#define MT6325_STRUP_PWRON_MASK 0x1
+#define MT6325_STRUP_PWRON_SHIFT 8
+#define MT6325_STRUP_PWRON_SEL_MASK 0x1
+#define MT6325_STRUP_PWRON_SEL_SHIFT 9
+#define MT6325_BIAS_GEN_EN_MASK 0x1
+#define MT6325_BIAS_GEN_EN_SHIFT 10
+#define MT6325_BIAS_GEN_EN_SEL_MASK 0x1
+#define MT6325_BIAS_GEN_EN_SEL_SHIFT 11
+#define MT6325_RTC_XOSC32_ENB_SW_MASK 0x1
+#define MT6325_RTC_XOSC32_ENB_SW_SHIFT 12
+#define MT6325_RTC_XOSC32_ENB_SEL_MASK 0x1
+#define MT6325_RTC_XOSC32_ENB_SEL_SHIFT 13
+#define MT6325_STRUP_DIG_IO_PG_FORCE_MASK 0x1
+#define MT6325_STRUP_DIG_IO_PG_FORCE_SHIFT 15
+#define MT6325_VDVFS11_PG_H2L_EN_MASK 0x1
+#define MT6325_VDVFS11_PG_H2L_EN_SHIFT 0
+#define MT6325_VDVFS12_PG_H2L_EN_MASK 0x1
+#define MT6325_VDVFS12_PG_H2L_EN_SHIFT 1
+#define MT6325_VCORE1_PG_H2L_EN_MASK 0x1
+#define MT6325_VCORE1_PG_H2L_EN_SHIFT 4
+#define MT6325_VCORE2_PG_H2L_EN_MASK 0x1
+#define MT6325_VCORE2_PG_H2L_EN_SHIFT 5
+#define MT6325_VGPU_PG_H2L_EN_MASK 0x1
+#define MT6325_VGPU_PG_H2L_EN_SHIFT 6
+#define MT6325_VIO18_PG_H2L_EN_MASK 0x1
+#define MT6325_VIO18_PG_H2L_EN_SHIFT 7
+#define MT6325_VAUD28_PG_H2L_EN_MASK 0x1
+#define MT6325_VAUD28_PG_H2L_EN_SHIFT 8
+#define MT6325_VTCXO_PG_H2L_EN_MASK 0x1
+#define MT6325_VTCXO_PG_H2L_EN_SHIFT 9
+#define MT6325_VUSB_PG_H2L_EN_MASK 0x1
+#define MT6325_VUSB_PG_H2L_EN_SHIFT 10
+#define MT6325_VSRAM_DVFS1_PG_H2L_EN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_PG_H2L_EN_SHIFT 11
+#define MT6325_VIO28_PG_H2L_EN_MASK 0x1
+#define MT6325_VIO28_PG_H2L_EN_SHIFT 12
+#define MT6325_VDRAM_PG_H2L_EN_MASK 0x1
+#define MT6325_VDRAM_PG_H2L_EN_SHIFT 13
+#define MT6325_VDVFS11_PG_ENB_MASK 0x1
+#define MT6325_VDVFS11_PG_ENB_SHIFT 0
+#define MT6325_VDVFS12_PG_ENB_MASK 0x1
+#define MT6325_VDVFS12_PG_ENB_SHIFT 1
+#define MT6325_VCORE1_PG_ENB_MASK 0x1
+#define MT6325_VCORE1_PG_ENB_SHIFT 4
+#define MT6325_VCORE2_PG_ENB_MASK 0x1
+#define MT6325_VCORE2_PG_ENB_SHIFT 5
+#define MT6325_VGPU_PG_ENB_MASK 0x1
+#define MT6325_VGPU_PG_ENB_SHIFT 6
+#define MT6325_VIO18_PG_ENB_MASK 0x1
+#define MT6325_VIO18_PG_ENB_SHIFT 7
+#define MT6325_VAUD28_PG_ENB_MASK 0x1
+#define MT6325_VAUD28_PG_ENB_SHIFT 8
+#define MT6325_VTCXO_PG_ENB_MASK 0x1
+#define MT6325_VTCXO_PG_ENB_SHIFT 9
+#define MT6325_VUSB_PG_ENB_MASK 0x1
+#define MT6325_VUSB_PG_ENB_SHIFT 10
+#define MT6325_VSRAM_DVFS1_PG_ENB_MASK 0x1
+#define MT6325_VSRAM_DVFS1_PG_ENB_SHIFT 11
+#define MT6325_VIO28_PG_ENB_MASK 0x1
+#define MT6325_VIO28_PG_ENB_SHIFT 12
+#define MT6325_VDRAM_PG_ENB_MASK 0x1
+#define MT6325_VDRAM_PG_ENB_SHIFT 13
+#define MT6325_RG_EXT_PMIC_EN_PG_ENB_MASK 0x1
+#define MT6325_RG_EXT_PMIC_EN_PG_ENB_SHIFT 14
+#define MT6325_CLR_JUST_RST_MASK 0x1
+#define MT6325_CLR_JUST_RST_SHIFT 4
+#define MT6325_UVLO_L2H_DEB_EN_MASK 0x1
+#define MT6325_UVLO_L2H_DEB_EN_SHIFT 5
+#define MT6325_JUST_PWRKEY_RST_MASK 0x1
+#define MT6325_JUST_PWRKEY_RST_SHIFT 14
+#define MT6325_QI_OSC_EN_MASK 0x1
+#define MT6325_QI_OSC_EN_SHIFT 15
+#define MT6325_STRUP_EXT_PMIC_EN_MASK 0x1
+#define MT6325_STRUP_EXT_PMIC_EN_SHIFT 0
+#define MT6325_STRUP_EXT_PMIC_SEL_MASK 0x1
+#define MT6325_STRUP_EXT_PMIC_SEL_SHIFT 1
+#define MT6325_STRUP_CON8_RSV0_MASK 0x7F
+#define MT6325_STRUP_CON8_RSV0_SHIFT 8
+#define MT6325_QI_EXT_PMIC_EN_MASK 0x1
+#define MT6325_QI_EXT_PMIC_EN_SHIFT 15
+#define MT6325_STRUP_AUXADC_START_SW_MASK 0x1
+#define MT6325_STRUP_AUXADC_START_SW_SHIFT 4
+#define MT6325_STRUP_AUXADC_RSTB_SW_MASK 0x1
+#define MT6325_STRUP_AUXADC_RSTB_SW_SHIFT 5
+#define MT6325_STRUP_AUXADC_START_SEL_MASK 0x1
+#define MT6325_STRUP_AUXADC_START_SEL_SHIFT 6
+#define MT6325_STRUP_AUXADC_RSTB_SEL_MASK 0x1
+#define MT6325_STRUP_AUXADC_RSTB_SEL_SHIFT 7
+#define MT6325_STRUP_PWROFF_SEQ_EN_MASK 0x1
+#define MT6325_STRUP_PWROFF_SEQ_EN_SHIFT 0
+#define MT6325_STRUP_PWROFF_PREOFF_EN_MASK 0x1
+#define MT6325_STRUP_PWROFF_PREOFF_EN_SHIFT 1
+#define MT6325_STRUP_PP_EN_MASK 0x1
+#define MT6325_STRUP_PP_EN_SHIFT 0
+#define MT6325_STRUP_PP_EN_SEL_MASK 0x1
+#define MT6325_STRUP_PP_EN_SEL_SHIFT 1
+#define MT6325_STRUP_DIG0_RSV0_MASK 0xF
+#define MT6325_STRUP_DIG0_RSV0_SHIFT 2
+#define MT6325_STRUP_DIG1_RSV0_MASK 0x1F
+#define MT6325_STRUP_DIG1_RSV0_SHIFT 6
+#define MT6325_RG_UVLO_VTHL_RSV0_MASK 0x1F
+#define MT6325_RG_UVLO_VTHL_RSV0_SHIFT 11
+#define MT6325_RG_BGR_RSV6_MASK 0x1
+#define MT6325_RG_BGR_RSV6_SHIFT 0
+#define MT6325_RG_BGR_RSV5_MASK 0x1
+#define MT6325_RG_BGR_RSV5_SHIFT 1
+#define MT6325_RG_BGR_RSV4_MASK 0x1F
+#define MT6325_RG_BGR_RSV4_SHIFT 5
+#define MT6325_RG_BGR_RSV3_MASK 0x1
+#define MT6325_RG_BGR_RSV3_SHIFT 10
+#define MT6325_RG_BGR_RSV2_MASK 0x7
+#define MT6325_RG_BGR_RSV2_SHIFT 11
+#define MT6325_RG_BGR_RSV1_MASK 0x1
+#define MT6325_RG_BGR_RSV1_SHIFT 14
+#define MT6325_RG_BGR_RSV0_MASK 0x1
+#define MT6325_RG_BGR_RSV0_SHIFT 15
+#define MT6325_RG_STRUP_RSV_MASK 0xFF
+#define MT6325_RG_STRUP_RSV_SHIFT 0
+#define MT6325_RG_EN_SMT_MASK 0x1
+#define MT6325_RG_EN_SMT_SHIFT 0
+#define MT6325_RG_EN_SR_MASK 0x1
+#define MT6325_RG_EN_SR_SHIFT 1
+#define MT6325_RG_EN_E8_MASK 0x1
+#define MT6325_RG_EN_E8_SHIFT 2
+#define MT6325_RG_EN_E4_MASK 0x1
+#define MT6325_RG_EN_E4_SHIFT 3
+#define MT6325_RG_TESTMODE_SWEN_MASK 0x1
+#define MT6325_RG_TESTMODE_SWEN_SHIFT 11
+#define MT6325_STRUP_DIG0_RSV1_MASK 0xF
+#define MT6325_STRUP_DIG0_RSV1_SHIFT 12
+#define MT6325_RG_RSV_SWREG_MASK 0xFFFF
+#define MT6325_RG_RSV_SWREG_SHIFT 0
+#define MT6325_STRUP_PG_STATUS_MASK 0x1
+#define MT6325_STRUP_PG_STATUS_SHIFT 0
+#define MT6325_USBDL_MASK 0x1
+#define MT6325_USBDL_SHIFT 1
+#define MT6325_STRUP_PG_STATUS_CLR_MASK 0x1
+#define MT6325_STRUP_PG_STATUS_CLR_SHIFT 15
+#define MT6325_STRUP_PP_EN_PWROFF_CNT_MASK 0x3FF
+#define MT6325_STRUP_PP_EN_PWROFF_CNT_SHIFT 0
+#define MT6325_STRUP_DIG0_RSV2_MASK 0x3F
+#define MT6325_STRUP_DIG0_RSV2_SHIFT 10
+#define MT6325_STRUP_UVLO_U1U2_SEL_MASK 0x1
+#define MT6325_STRUP_UVLO_U1U2_SEL_SHIFT 0
+#define MT6325_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK 0x1
+#define MT6325_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT 1
+#define MT6325_STRUP_LBAT_INT_SEL_CLR_MASK 0x1
+#define MT6325_STRUP_LBAT_INT_SEL_CLR_SHIFT 2
+#define MT6325_STRUP_LBAT_INT_SEL_SWCTRL_MASK 0x1
+#define MT6325_STRUP_LBAT_INT_SEL_SWCTRL_SHIFT 3
+#define MT6325_STRUP_LBAT_INT_SEL_MASK 0x1
+#define MT6325_STRUP_LBAT_INT_SEL_SHIFT 4
+#define MT6325_STRUP_LBAT_IRQ_SET_MASK 0x1
+#define MT6325_STRUP_LBAT_IRQ_SET_SHIFT 0
+#define MT6325_STRUP_LBAT_IRQ_CLR_MASK 0x1
+#define MT6325_STRUP_LBAT_IRQ_CLR_SHIFT 1
+#define MT6325_STRUP_LBAT_IRQ_SWCTRL_MASK 0x1
+#define MT6325_STRUP_LBAT_IRQ_SWCTRL_SHIFT 2
+#define MT6325_RG_UVLO_VSYS_DEB_75K_RPCNT_MAX_MASK 0xF
+#define MT6325_RG_UVLO_VSYS_DEB_75K_RPCNT_MAX_SHIFT 0
+#define MT6325_RG_UVLO_VSYS_DEB_2M_RPCNT_MAX_MASK 0xF
+#define MT6325_RG_UVLO_VSYS_DEB_2M_RPCNT_MAX_SHIFT 4
+#define MT6325_STRUP_AUXADC_RPCNT_MAX_MASK 0x7F
+#define MT6325_STRUP_AUXADC_RPCNT_MAX_SHIFT 0
+#define MT6325_RG_RST_DRVSEL_MASK 0x1
+#define MT6325_RG_RST_DRVSEL_SHIFT 12
+#define MT6325_HWCID_MASK 0xFFFF
+#define MT6325_HWCID_SHIFT 0
+#define MT6325_SWCID_MASK 0xFFFF
+#define MT6325_SWCID_SHIFT 0
+#define MT6325_RG_SRCLKEN_IN0_EN_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN0_EN_SHIFT 0
+#define MT6325_RG_SRCLKEN_IN1_EN_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN1_EN_SHIFT 1
+#define MT6325_RG_OSC_SEL_MASK 0x1
+#define MT6325_RG_OSC_SEL_SHIFT 2
+#define MT6325_RG_SRCLKEN_IN0_HW_MODE_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN0_HW_MODE_SHIFT 4
+#define MT6325_RG_SRCLKEN_IN1_HW_MODE_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN1_HW_MODE_SHIFT 5
+#define MT6325_RG_OSC_SEL_HW_MODE_MASK 0x1
+#define MT6325_RG_OSC_SEL_HW_MODE_SHIFT 6
+#define MT6325_RG_SRCLKEN_IN_SYNC_EN_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN_SYNC_EN_SHIFT 8
+#define MT6325_RG_OSC_EN_AUTO_OFF_MASK 0x1
+#define MT6325_RG_OSC_EN_AUTO_OFF_SHIFT 9
+#define MT6325_TEST_OUT_MASK 0xFF
+#define MT6325_TEST_OUT_SHIFT 0
+#define MT6325_RG_MON_FLAG_SEL_MASK 0xFF
+#define MT6325_RG_MON_FLAG_SEL_SHIFT 0
+#define MT6325_RG_MON_GRP_SEL_MASK 0x1F
+#define MT6325_RG_MON_GRP_SEL_SHIFT 8
+#define MT6325_RG_NANDTREE_MODE_MASK 0x1
+#define MT6325_RG_NANDTREE_MODE_SHIFT 0
+#define MT6325_RG_TEST_AUXADC_MASK 0x1
+#define MT6325_RG_TEST_AUXADC_SHIFT 1
+#define MT6325_RG_EFUSE_MODE_MASK 0x1
+#define MT6325_RG_EFUSE_MODE_SHIFT 2
+#define MT6325_RG_TEST_STRUP_MASK 0x1
+#define MT6325_RG_TEST_STRUP_SHIFT 3
+#define MT6325_TESTMODE_SW_MASK 0x1
+#define MT6325_TESTMODE_SW_SHIFT 0
+#define MT6325_EN_STATUS_VDVFS11_MASK 0x1
+#define MT6325_EN_STATUS_VDVFS11_SHIFT 0
+#define MT6325_EN_STATUS_VDVFS12_MASK 0x1
+#define MT6325_EN_STATUS_VDVFS12_SHIFT 1
+#define MT6325_EN_STATUS_VDRAM_MASK 0x1
+#define MT6325_EN_STATUS_VDRAM_SHIFT 2
+#define MT6325_EN_STATUS_VRF18_0_MASK 0x1
+#define MT6325_EN_STATUS_VRF18_0_SHIFT 3
+#define MT6325_EN_STATUS_VGPU_MASK 0x1
+#define MT6325_EN_STATUS_VGPU_SHIFT 4
+#define MT6325_EN_STATUS_VCORE1_MASK 0x1
+#define MT6325_EN_STATUS_VCORE1_SHIFT 5
+#define MT6325_EN_STATUS_VCORE2_MASK 0x1
+#define MT6325_EN_STATUS_VCORE2_SHIFT 6
+#define MT6325_EN_STATUS_VIO18_MASK 0x1
+#define MT6325_EN_STATUS_VIO18_SHIFT 7
+#define MT6325_EN_STATUS_VPA_MASK 0x1
+#define MT6325_EN_STATUS_VPA_SHIFT 8
+#define MT6325_EN_STATUS_VRTC_MASK 0x1
+#define MT6325_EN_STATUS_VRTC_SHIFT 9
+#define MT6325_EN_STATUS_VTCXO0_MASK 0x1
+#define MT6325_EN_STATUS_VTCXO0_SHIFT 10
+#define MT6325_EN_STATUS_VTCXO1_MASK 0x1
+#define MT6325_EN_STATUS_VTCXO1_SHIFT 11
+#define MT6325_EN_STATUS_VAUD28_MASK 0x1
+#define MT6325_EN_STATUS_VAUD28_SHIFT 12
+#define MT6325_EN_STATUS_VAUXA28_MASK 0x1
+#define MT6325_EN_STATUS_VAUXA28_SHIFT 13
+#define MT6325_EN_STATUS_VCAMA_MASK 0x1
+#define MT6325_EN_STATUS_VCAMA_SHIFT 14
+#define MT6325_EN_STATUS_VIO28_MASK 0x1
+#define MT6325_EN_STATUS_VIO28_SHIFT 15
+#define MT6325_EN_STATUS_VCAM_AF_MASK 0x1
+#define MT6325_EN_STATUS_VCAM_AF_SHIFT 0
+#define MT6325_EN_STATUS_VMC_MASK 0x1
+#define MT6325_EN_STATUS_VMC_SHIFT 1
+#define MT6325_EN_STATUS_VMCH_MASK 0x1
+#define MT6325_EN_STATUS_VMCH_SHIFT 2
+#define MT6325_EN_STATUS_VEMC33_MASK 0x1
+#define MT6325_EN_STATUS_VEMC33_SHIFT 3
+#define MT6325_EN_STATUS_VGP1_MASK 0x1
+#define MT6325_EN_STATUS_VGP1_SHIFT 4
+#define MT6325_EN_STATUS_VEFUSE_MASK 0x1
+#define MT6325_EN_STATUS_VEFUSE_SHIFT 5
+#define MT6325_EN_STATUS_VSIM1_MASK 0x1
+#define MT6325_EN_STATUS_VSIM1_SHIFT 6
+#define MT6325_EN_STATUS_VSIM2_MASK 0x1
+#define MT6325_EN_STATUS_VSIM2_SHIFT 7
+#define MT6325_EN_STATUS_VCN28_MASK 0x1
+#define MT6325_EN_STATUS_VCN28_SHIFT 8
+#define MT6325_EN_STATUS_VMIPI_MASK 0x1
+#define MT6325_EN_STATUS_VMIPI_SHIFT 9
+#define MT6325_EN_STATUS_VIBR_MASK 0x1
+#define MT6325_EN_STATUS_VIBR_SHIFT 10
+#define MT6325_EN_STATUS_VCAMD_MASK 0x1
+#define MT6325_EN_STATUS_VCAMD_SHIFT 11
+#define MT6325_EN_STATUS_VUSB33_MASK 0x1
+#define MT6325_EN_STATUS_VUSB33_SHIFT 12
+#define MT6325_EN_STATUS_VCAM_IO_MASK 0x1
+#define MT6325_EN_STATUS_VCAM_IO_SHIFT 13
+#define MT6325_EN_STATUS_VSRAM_DVFS1_MASK 0x1
+#define MT6325_EN_STATUS_VSRAM_DVFS1_SHIFT 14
+#define MT6325_EN_STATUS_VGP2_MASK 0x1
+#define MT6325_EN_STATUS_VGP2_SHIFT 15
+#define MT6325_EN_STATUS_VGP3_MASK 0x1
+#define MT6325_EN_STATUS_VGP3_SHIFT 0
+#define MT6325_EN_STATUS_VBIASN_MASK 0x1
+#define MT6325_EN_STATUS_VBIASN_SHIFT 1
+#define MT6325_EN_STATUS_VCN33_MASK 0x1
+#define MT6325_EN_STATUS_VCN33_SHIFT 2
+#define MT6325_EN_STATUS_VCN18_MASK 0x1
+#define MT6325_EN_STATUS_VCN18_SHIFT 3
+#define MT6325_EN_STATUS_VRF18_1_MASK 0x1
+#define MT6325_EN_STATUS_VRF18_1_SHIFT 4
+#define MT6325_OC_STATUS_VDVFS11_MASK 0x1
+#define MT6325_OC_STATUS_VDVFS11_SHIFT 0
+#define MT6325_OC_STATUS_VDVFS12_MASK 0x1
+#define MT6325_OC_STATUS_VDVFS12_SHIFT 1
+#define MT6325_OC_STATUS_VDRAM_MASK 0x1
+#define MT6325_OC_STATUS_VDRAM_SHIFT 2
+#define MT6325_OC_STATUS_VRF18_0_MASK 0x1
+#define MT6325_OC_STATUS_VRF18_0_SHIFT 3
+#define MT6325_OC_STATUS_VGPU_MASK 0x1
+#define MT6325_OC_STATUS_VGPU_SHIFT 4
+#define MT6325_OC_STATUS_VCORE1_MASK 0x1
+#define MT6325_OC_STATUS_VCORE1_SHIFT 5
+#define MT6325_OC_STATUS_VCORE2_MASK 0x1
+#define MT6325_OC_STATUS_VCORE2_SHIFT 6
+#define MT6325_OC_STATUS_VIO18_MASK 0x1
+#define MT6325_OC_STATUS_VIO18_SHIFT 7
+#define MT6325_OC_STATUS_VPA_MASK 0x1
+#define MT6325_OC_STATUS_VPA_SHIFT 8
+#define MT6325_OC_STATUS_VTCXO0_MASK 0x1
+#define MT6325_OC_STATUS_VTCXO0_SHIFT 9
+#define MT6325_OC_STATUS_VTCXO1_MASK 0x1
+#define MT6325_OC_STATUS_VTCXO1_SHIFT 10
+#define MT6325_OC_STATUS_VAUD28_MASK 0x1
+#define MT6325_OC_STATUS_VAUD28_SHIFT 11
+#define MT6325_OC_STATUS_VAUXA28_MASK 0x1
+#define MT6325_OC_STATUS_VAUXA28_SHIFT 12
+#define MT6325_OC_STATUS_VCAMA_MASK 0x1
+#define MT6325_OC_STATUS_VCAMA_SHIFT 13
+#define MT6325_OC_STATUS_VIO28_MASK 0x1
+#define MT6325_OC_STATUS_VIO28_SHIFT 14
+#define MT6325_OC_STATUS_VCAM_AF_MASK 0x1
+#define MT6325_OC_STATUS_VCAM_AF_SHIFT 15
+#define MT6325_OC_STATUS_VMC_MASK 0x1
+#define MT6325_OC_STATUS_VMC_SHIFT 0
+#define MT6325_OC_STATUS_VMCH_MASK 0x1
+#define MT6325_OC_STATUS_VMCH_SHIFT 1
+#define MT6325_OC_STATUS_VEMC33_MASK 0x1
+#define MT6325_OC_STATUS_VEMC33_SHIFT 2
+#define MT6325_OC_STATUS_VGP1_MASK 0x1
+#define MT6325_OC_STATUS_VGP1_SHIFT 3
+#define MT6325_OC_STATUS_VEFUSE_MASK 0x1
+#define MT6325_OC_STATUS_VEFUSE_SHIFT 4
+#define MT6325_OC_STATUS_VSIM1_MASK 0x1
+#define MT6325_OC_STATUS_VSIM1_SHIFT 5
+#define MT6325_OC_STATUS_VSIM2_MASK 0x1
+#define MT6325_OC_STATUS_VSIM2_SHIFT 6
+#define MT6325_OC_STATUS_VCN28_MASK 0x1
+#define MT6325_OC_STATUS_VCN28_SHIFT 7
+#define MT6325_OC_STATUS_VMIPI_MASK 0x1
+#define MT6325_OC_STATUS_VMIPI_SHIFT 8
+#define MT6325_OC_STATUS_VIBR_MASK 0x1
+#define MT6325_OC_STATUS_VIBR_SHIFT 10
+#define MT6325_OC_STATUS_VCAMD_MASK 0x1
+#define MT6325_OC_STATUS_VCAMD_SHIFT 11
+#define MT6325_OC_STATUS_VUSB33_MASK 0x1
+#define MT6325_OC_STATUS_VUSB33_SHIFT 12
+#define MT6325_OC_STATUS_VCAM_IO_MASK 0x1
+#define MT6325_OC_STATUS_VCAM_IO_SHIFT 13
+#define MT6325_OC_STATUS_VSRAM_DVFS1_MASK 0x1
+#define MT6325_OC_STATUS_VSRAM_DVFS1_SHIFT 14
+#define MT6325_OC_STATUS_VBIASN_MASK 0x1
+#define MT6325_OC_STATUS_VBIASN_SHIFT 15
+#define MT6325_OC_STATUS_VGP2_MASK 0x1
+#define MT6325_OC_STATUS_VGP2_SHIFT 0
+#define MT6325_OC_STATUS_VGP3_MASK 0x1
+#define MT6325_OC_STATUS_VGP3_SHIFT 1
+#define MT6325_OC_STATUS_VCN33_MASK 0x1
+#define MT6325_OC_STATUS_VCN33_SHIFT 2
+#define MT6325_OC_STATUS_VCN18_MASK 0x1
+#define MT6325_OC_STATUS_VCN18_SHIFT 3
+#define MT6325_OC_STATUS_VRF18_1_MASK 0x1
+#define MT6325_OC_STATUS_VRF18_1_SHIFT 4
+#define MT6325_VTCXO_PG_DEB_MASK 0x1
+#define MT6325_VTCXO_PG_DEB_SHIFT 3
+#define MT6325_VAUD28_PG_DEB_MASK 0x1
+#define MT6325_VAUD28_PG_DEB_SHIFT 4
+#define MT6325_VSRAM_DVFS1_PG_DEB_MASK 0x1
+#define MT6325_VSRAM_DVFS1_PG_DEB_SHIFT 5
+#define MT6325_VIO28_PG_DEB_MASK 0x1
+#define MT6325_VIO28_PG_DEB_SHIFT 6
+#define MT6325_VIO18_PG_DEB_MASK 0x1
+#define MT6325_VIO18_PG_DEB_SHIFT 8
+#define MT6325_VCORE2_PG_DEB_MASK 0x1
+#define MT6325_VCORE2_PG_DEB_SHIFT 9
+#define MT6325_VCORE1_PG_DEB_MASK 0x1
+#define MT6325_VCORE1_PG_DEB_SHIFT 10
+#define MT6325_VGPU_PG_DEB_MASK 0x1
+#define MT6325_VGPU_PG_DEB_SHIFT 11
+#define MT6325_VUSB_PG_DEB_MASK 0x1
+#define MT6325_VUSB_PG_DEB_SHIFT 12
+#define MT6325_VDRAM_PG_DEB_MASK 0x1
+#define MT6325_VDRAM_PG_DEB_SHIFT 13
+#define MT6325_VDVFS12_PG_DEB_MASK 0x1
+#define MT6325_VDVFS12_PG_DEB_SHIFT 14
+#define MT6325_VDVFS11_PG_DEB_MASK 0x1
+#define MT6325_VDVFS11_PG_DEB_SHIFT 15
+#define MT6325_PMU_TEST_MODE_SCAN_MASK 0x1
+#define MT6325_PMU_TEST_MODE_SCAN_SHIFT 0
+#define MT6325_PWRKEY_DEB_MASK 0x1
+#define MT6325_PWRKEY_DEB_SHIFT 1
+#define MT6325_HOMEKEY_DEB_MASK 0x1
+#define MT6325_HOMEKEY_DEB_SHIFT 2
+#define MT6325_RTC_XTAL_DET_DONE_MASK 0x1
+#define MT6325_RTC_XTAL_DET_DONE_SHIFT 6
+#define MT6325_XOSC32_ENB_DET_MASK 0x1
+#define MT6325_XOSC32_ENB_DET_SHIFT 7
+#define MT6325_RTC_XTAL_DET_RSV_MASK 0xF
+#define MT6325_RTC_XTAL_DET_RSV_SHIFT 8
+#define MT6325_RG_PMU_TDSEL_MASK 0x1
+#define MT6325_RG_PMU_TDSEL_SHIFT 0
+#define MT6325_RG_SPI_TDSEL_MASK 0x1
+#define MT6325_RG_SPI_TDSEL_SHIFT 1
+#define MT6325_RG_AUD_TDSEL_MASK 0x1
+#define MT6325_RG_AUD_TDSEL_SHIFT 2
+#define MT6325_RG_E32CAL_TDSEL_MASK 0x1
+#define MT6325_RG_E32CAL_TDSEL_SHIFT 3
+#define MT6325_RG_PMU_RDSEL_MASK 0x1
+#define MT6325_RG_PMU_RDSEL_SHIFT 0
+#define MT6325_RG_SPI_RDSEL_MASK 0x1
+#define MT6325_RG_SPI_RDSEL_SHIFT 1
+#define MT6325_RG_AUD_RDSEL_MASK 0x1
+#define MT6325_RG_AUD_RDSEL_SHIFT 2
+#define MT6325_RG_E32CAL_RDSEL_MASK 0x1
+#define MT6325_RG_E32CAL_RDSEL_SHIFT 3
+#define MT6325_RG_SMT_WDTRSTB_IN_MASK 0x1
+#define MT6325_RG_SMT_WDTRSTB_IN_SHIFT 0
+#define MT6325_RG_SMT_HOMEKEY_MASK 0x1
+#define MT6325_RG_SMT_HOMEKEY_SHIFT 1
+#define MT6325_RG_SMT_SRCLKEN_IN0_MASK 0x1
+#define MT6325_RG_SMT_SRCLKEN_IN0_SHIFT 2
+#define MT6325_RG_SMT_SRCLKEN_IN1_MASK 0x1
+#define MT6325_RG_SMT_SRCLKEN_IN1_SHIFT 3
+#define MT6325_RG_SMT_RTC_32K1V8_0_MASK 0x1
+#define MT6325_RG_SMT_RTC_32K1V8_0_SHIFT 4
+#define MT6325_RG_SMT_RTC_32K1V8_1_MASK 0x1
+#define MT6325_RG_SMT_RTC_32K1V8_1_SHIFT 5
+#define MT6325_RG_SMT_SPI_CLK_MASK 0x1
+#define MT6325_RG_SMT_SPI_CLK_SHIFT 0
+#define MT6325_RG_SMT_SPI_CSN_MASK 0x1
+#define MT6325_RG_SMT_SPI_CSN_SHIFT 1
+#define MT6325_RG_SMT_SPI_MOSI_MASK 0x1
+#define MT6325_RG_SMT_SPI_MOSI_SHIFT 2
+#define MT6325_RG_SMT_SPI_MISO_MASK 0x1
+#define MT6325_RG_SMT_SPI_MISO_SHIFT 3
+#define MT6325_RG_SMT_AUD_CLK_MASK 0x1
+#define MT6325_RG_SMT_AUD_CLK_SHIFT 0
+#define MT6325_RG_SMT_AUD_DAT_MOSI_MASK 0x1
+#define MT6325_RG_SMT_AUD_DAT_MOSI_SHIFT 1
+#define MT6325_RG_SMT_AUD_DAT_MISO_MASK 0x1
+#define MT6325_RG_SMT_AUD_DAT_MISO_SHIFT 2
+#define MT6325_RG_SMT_VOICE_CLK_MISO_MASK 0x1
+#define MT6325_RG_SMT_VOICE_CLK_MISO_SHIFT 3
+#define MT6325_RG_SMT_ENBB_MASK 0x1
+#define MT6325_RG_SMT_ENBB_SHIFT 4
+#define MT6325_RG_SMT_XOSC_EN_MASK 0x1
+#define MT6325_RG_SMT_XOSC_EN_SHIFT 5
+#define MT6325_RG_OCTL_SRCLKEN_IN0_MASK 0xF
+#define MT6325_RG_OCTL_SRCLKEN_IN0_SHIFT 0
+#define MT6325_RG_OCTL_SRCLKEN_IN1_MASK 0xF
+#define MT6325_RG_OCTL_SRCLKEN_IN1_SHIFT 4
+#define MT6325_RG_OCTL_RTC_32K1V8_0_MASK 0xF
+#define MT6325_RG_OCTL_RTC_32K1V8_0_SHIFT 8
+#define MT6325_RG_OCTL_RTC_32K1V8_1_MASK 0xF
+#define MT6325_RG_OCTL_RTC_32K1V8_1_SHIFT 12
+#define MT6325_RG_OCTL_SPI_CLK_MASK 0xF
+#define MT6325_RG_OCTL_SPI_CLK_SHIFT 0
+#define MT6325_RG_OCTL_SPI_CSN_MASK 0xF
+#define MT6325_RG_OCTL_SPI_CSN_SHIFT 4
+#define MT6325_RG_OCTL_SPI_MOSI_MASK 0xF
+#define MT6325_RG_OCTL_SPI_MOSI_SHIFT 8
+#define MT6325_RG_OCTL_SPI_MISO_MASK 0xF
+#define MT6325_RG_OCTL_SPI_MISO_SHIFT 12
+#define MT6325_RG_OCTL_AUD_DAT_MOSI_MASK 0xF
+#define MT6325_RG_OCTL_AUD_DAT_MOSI_SHIFT 0
+#define MT6325_RG_OCTL_AUD_DAT_MISO_MASK 0xF
+#define MT6325_RG_OCTL_AUD_DAT_MISO_SHIFT 4
+#define MT6325_RG_OCTL_AUD_CLK_MASK 0xF
+#define MT6325_RG_OCTL_AUD_CLK_SHIFT 8
+#define MT6325_RG_OCTL_VOICE_CLK_MISO_MASK 0xF
+#define MT6325_RG_OCTL_VOICE_CLK_MISO_SHIFT 12
+#define MT6325_RG_OCTL_HOMEKEY_MASK 0xF
+#define MT6325_RG_OCTL_HOMEKEY_SHIFT 0
+#define MT6325_RG_OCTL_ENBB_MASK 0xF
+#define MT6325_RG_OCTL_ENBB_SHIFT 4
+#define MT6325_RG_OCTL_XOSC_EN_MASK 0xF
+#define MT6325_RG_OCTL_XOSC_EN_SHIFT 8
+#define MT6325_TOP_STATUS_MASK 0xF
+#define MT6325_TOP_STATUS_SHIFT 0
+#define MT6325_TOP_STATUS_SET_MASK 0x3
+#define MT6325_TOP_STATUS_SET_SHIFT 0
+#define MT6325_TOP_STATUS_CLR_MASK 0x3
+#define MT6325_TOP_STATUS_CLR_SHIFT 0
+#define MT6325_RGS_VDVFS11_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VDVFS11_ENPWM_STATUS_SHIFT 0
+#define MT6325_RGS_VDVFS12_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VDVFS12_ENPWM_STATUS_SHIFT 1
+#define MT6325_RGS_VGPU_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VGPU_ENPWM_STATUS_SHIFT 2
+#define MT6325_RGS_VIO18_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VIO18_ENPWM_STATUS_SHIFT 3
+#define MT6325_RGS_VCORE1_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VCORE1_ENPWM_STATUS_SHIFT 4
+#define MT6325_RGS_VCORE2_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VCORE2_ENPWM_STATUS_SHIFT 5
+#define MT6325_RGS_VRF18_0_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VRF18_0_ENPWM_STATUS_SHIFT 6
+#define MT6325_RGS_VDRAM_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VDRAM_ENPWM_STATUS_SHIFT 7
+#define MT6325_RGS_PP_EN_MASK 0x1
+#define MT6325_RGS_PP_EN_SHIFT 8
+#define MT6325_RGS_BC11_ID_FLOAT_MASK 0x1
+#define MT6325_RGS_BC11_ID_FLOAT_SHIFT 9
+#define MT6325_RGS_BC11_ID_A_MASK 0x1
+#define MT6325_RGS_BC11_ID_A_SHIFT 10
+#define MT6325_RGS_BC11_ID_B_MASK 0x1
+#define MT6325_RGS_BC11_ID_B_SHIFT 11
+#define MT6325_RGS_BC11_ID_C_MASK 0x1
+#define MT6325_RGS_BC11_ID_C_SHIFT 12
+#define MT6325_RGS_BC11_ID_GD_MASK 0x1
+#define MT6325_RGS_BC11_ID_GD_SHIFT 13
+#define MT6325_RG_G_SMPS_PD_CK_PDN_MASK 0x1
+#define MT6325_RG_G_SMPS_PD_CK_PDN_SHIFT 0
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_MASK 0x1
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_SHIFT 1
+#define MT6325_RG_G_DRV_2M_CK_PDN_MASK 0x1
+#define MT6325_RG_G_DRV_2M_CK_PDN_SHIFT 2
+#define MT6325_RG_DRV_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_32K_CK_PDN_SHIFT 3
+#define MT6325_RG_DRV_ISINK0_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK0_CK_PDN_SHIFT 4
+#define MT6325_RG_DRV_ISINK1_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK1_CK_PDN_SHIFT 5
+#define MT6325_RG_DRV_ISINK2_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK2_CK_PDN_SHIFT 6
+#define MT6325_RG_DRV_ISINK3_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK3_CK_PDN_SHIFT 7
+#define MT6325_RG_AUXADC_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_AUXADC_1M_CK_PDN_SHIFT 8
+#define MT6325_RG_AUXADC_CK_PDN_MASK 0x1
+#define MT6325_RG_AUXADC_CK_PDN_SHIFT 9
+#define MT6325_RG_AUXADC_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_AUXADC_32K_CK_PDN_SHIFT 10
+#define MT6325_RG_AUDNCP_CK_PDN_MASK 0x1
+#define MT6325_RG_AUDNCP_CK_PDN_SHIFT 11
+#define MT6325_RG_AUDIF_CK_PDN_MASK 0x1
+#define MT6325_RG_AUDIF_CK_PDN_SHIFT 12
+#define MT6325_RG_AUD_CK_PDN_MASK 0x1
+#define MT6325_RG_AUD_CK_PDN_SHIFT 13
+#define MT6325_RG_ZCD13M_CK_PDN_MASK 0x1
+#define MT6325_RG_ZCD13M_CK_PDN_SHIFT 14
+#define MT6325_RG_VOW12M_CK_PDN_MASK 0x1
+#define MT6325_RG_VOW12M_CK_PDN_SHIFT 15
+#define MT6325_TOP_CKPDN_CON0_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON0_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON0_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON0_CLR_SHIFT 0
+#define MT6325_RG_RTC_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_32K_CK_PDN_SHIFT 0
+#define MT6325_RG_RTC_MCLK_PDN_MASK 0x1
+#define MT6325_RG_RTC_MCLK_PDN_SHIFT 1
+#define MT6325_RG_RTC_75K_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_75K_CK_PDN_SHIFT 2
+#define MT6325_RG_RTCDET_CK_PDN_MASK 0x1
+#define MT6325_RG_RTCDET_CK_PDN_SHIFT 3
+#define MT6325_RG_RTC32K_1V8_0_O_PDN_MASK 0x1
+#define MT6325_RG_RTC32K_1V8_0_O_PDN_SHIFT 4
+#define MT6325_RG_RTC32K_1V8_1_O_PDN_MASK 0x1
+#define MT6325_RG_RTC32K_1V8_1_O_PDN_SHIFT 5
+#define MT6325_RG_RTC_2SEC_OFF_DET_PDN_MASK 0x1
+#define MT6325_RG_RTC_2SEC_OFF_DET_PDN_SHIFT 6
+#define MT6325_RG_FQMTR_CK_PDN_MASK 0x1
+#define MT6325_RG_FQMTR_CK_PDN_SHIFT 7
+#define MT6325_RG_STB_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_STB_1M_CK_PDN_SHIFT 8
+#define MT6325_RG_BUCK_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_1M_CK_PDN_SHIFT 9
+#define MT6325_RG_BUCK_18M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_18M_CK_PDN_SHIFT 10
+#define MT6325_RG_PWMOC_6M_CK_PDN_MASK 0x1
+#define MT6325_RG_PWMOC_6M_CK_PDN_SHIFT 11
+#define MT6325_RG_STB_AUD_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_STB_AUD_1M_CK_PDN_SHIFT 12
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_SHIFT 13
+#define MT6325_RG_BUCK_AUD_18M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_AUD_18M_CK_PDN_SHIFT 14
+#define MT6325_RG_PWMOC_AUD_6M_CK_PDN_MASK 0x1
+#define MT6325_RG_PWMOC_AUD_6M_CK_PDN_SHIFT 15
+#define MT6325_TOP_CKPDN_CON1_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON1_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON1_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON1_CLR_SHIFT 0
+#define MT6325_RG_SPK_CK_PDN_MASK 0x1
+#define MT6325_RG_SPK_CK_PDN_SHIFT 0
+#define MT6325_RG_SPK_PWM_CK_PDN_MASK 0x1
+#define MT6325_RG_SPK_PWM_CK_PDN_SHIFT 1
+#define MT6325_RG_FGADC_ANA_CK_PDN_MASK 0x1
+#define MT6325_RG_FGADC_ANA_CK_PDN_SHIFT 2
+#define MT6325_RG_FGADC_DIG_CK_PDN_MASK 0x1
+#define MT6325_RG_FGADC_DIG_CK_PDN_SHIFT 3
+#define MT6325_RG_BIF_X72_CK_PDN_MASK 0x1
+#define MT6325_RG_BIF_X72_CK_PDN_SHIFT 4
+#define MT6325_RG_BIF_X4_CK_PDN_MASK 0x1
+#define MT6325_RG_BIF_X4_CK_PDN_SHIFT 5
+#define MT6325_RG_BIF_X1_CK_PDN_MASK 0x1
+#define MT6325_RG_BIF_X1_CK_PDN_SHIFT 6
+#define MT6325_RG_PCHR_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_PCHR_32K_CK_PDN_SHIFT 7
+#define MT6325_RG_AUD18M_CK_PDN_MASK 0x1
+#define MT6325_RG_AUD18M_CK_PDN_SHIFT 8
+#define MT6325_RG_ACCDET_CK_PDN_MASK 0x1
+#define MT6325_RG_ACCDET_CK_PDN_SHIFT 9
+#define MT6325_RG_FQMTR_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_FQMTR_32K_CK_PDN_SHIFT 10
+#define MT6325_RG_INTRP_CK_PDN_MASK 0x1
+#define MT6325_RG_INTRP_CK_PDN_SHIFT 11
+#define MT6325_RG_RTC_26M_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_26M_CK_PDN_SHIFT 12
+#define MT6325_RG_RTC_EOSC32_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_EOSC32_CK_PDN_SHIFT 13
+#define MT6325_RG_TRIM_75K_CK_PDN_MASK 0x1
+#define MT6325_RG_TRIM_75K_CK_PDN_SHIFT 14
+#define MT6325_RG_STRUP_LBAT_SEL_CK_PDN_MASK 0x1
+#define MT6325_RG_STRUP_LBAT_SEL_CK_PDN_SHIFT 15
+#define MT6325_TOP_CKPDN_CON2_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON2_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON2_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON2_CLR_SHIFT 0
+#define MT6325_RG_STRUP_75K_CK_PDN_MASK 0x1
+#define MT6325_RG_STRUP_75K_CK_PDN_SHIFT 0
+#define MT6325_RG_STRUP_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_STRUP_32K_CK_PDN_SHIFT 1
+#define MT6325_RG_EFUSE_CK_PDN_MASK 0x1
+#define MT6325_RG_EFUSE_CK_PDN_SHIFT 2
+#define MT6325_RG_SMPS_CK_DIV_PDN_MASK 0x1
+#define MT6325_RG_SMPS_CK_DIV_PDN_SHIFT 3
+#define MT6325_RG_SPI_CK_PDN_MASK 0x1
+#define MT6325_RG_SPI_CK_PDN_SHIFT 4
+#define MT6325_RG_BGR_TEST_CK_PDN_MASK 0x1
+#define MT6325_RG_BGR_TEST_CK_PDN_SHIFT 5
+#define MT6325_RG_FGADC_FT_CK_PDN_MASK 0x1
+#define MT6325_RG_FGADC_FT_CK_PDN_SHIFT 6
+#define MT6325_RG_PCHR_TEST_CK_PDN_MASK 0x1
+#define MT6325_RG_PCHR_TEST_CK_PDN_SHIFT 7
+#define MT6325_RG_BUCK_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_32K_CK_PDN_SHIFT 8
+#define MT6325_RG_BUCK_ANA_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_ANA_CK_PDN_SHIFT 9
+#define MT6325_RG_EOSC_CALI_TEST_CK_PDN_MASK 0x1
+#define MT6325_RG_EOSC_CALI_TEST_CK_PDN_SHIFT 10
+#define MT6325_TOP_CKPDN_CON3_RSV_MASK 0x1F
+#define MT6325_TOP_CKPDN_CON3_RSV_SHIFT 11
+#define MT6325_TOP_CKPDN_CON3_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON3_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON3_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON3_CLR_SHIFT 0
+#define MT6325_RG_AUDIF_CK_CKSEL_MASK 0x1
+#define MT6325_RG_AUDIF_CK_CKSEL_SHIFT 0
+#define MT6325_RG_AUD_CK_CKSEL_MASK 0x1
+#define MT6325_RG_AUD_CK_CKSEL_SHIFT 1
+#define MT6325_RG_DRV_ISINK0_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK0_CK_CKSEL_SHIFT 4
+#define MT6325_RG_DRV_ISINK1_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK1_CK_CKSEL_SHIFT 5
+#define MT6325_RG_DRV_ISINK2_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK2_CK_CKSEL_SHIFT 6
+#define MT6325_RG_DRV_ISINK3_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK3_CK_CKSEL_SHIFT 7
+#define MT6325_RG_FQMTR_CK_CKSEL_MASK 0x7
+#define MT6325_RG_FQMTR_CK_CKSEL_SHIFT 8
+#define MT6325_RG_75K_32K_SEL_MASK 0x1
+#define MT6325_RG_75K_32K_SEL_SHIFT 11
+#define MT6325_RG_AUXADC_CK_CKSEL_MASK 0x1
+#define MT6325_RG_AUXADC_CK_CKSEL_SHIFT 12
+#define MT6325_TOP_CKSEL_CON0_RSV_MASK 0x1
+#define MT6325_TOP_CKSEL_CON0_RSV_SHIFT 13
+#define MT6325_RG_OSC_SEL_HW_SRC_SEL_MASK 0x3
+#define MT6325_RG_OSC_SEL_HW_SRC_SEL_SHIFT 14
+#define MT6325_TOP_CKSEL_CON_SET_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON_SET_SHIFT 0
+#define MT6325_TOP_CKSEL_CON_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON_CLR_SHIFT 0
+#define MT6325_RG_STRUP_75K_CK_CKSEL_MASK 0x3
+#define MT6325_RG_STRUP_75K_CK_CKSEL_SHIFT 0
+#define MT6325_RG_BGR_TEST_CK_CKSEL_MASK 0x1
+#define MT6325_RG_BGR_TEST_CK_CKSEL_SHIFT 2
+#define MT6325_RG_PCHR_TEST_CK_CKSEL_MASK 0x1
+#define MT6325_RG_PCHR_TEST_CK_CKSEL_SHIFT 3
+#define MT6325_RG_FGADC_ANA_CK_CKSEL_MASK 0x1
+#define MT6325_RG_FGADC_ANA_CK_CKSEL_SHIFT 4
+#define MT6325_TOP_CKSEL_CON1_RSV_MASK 0x3
+#define MT6325_TOP_CKSEL_CON1_RSV_SHIFT 8
+#define MT6325_TOP_CKSEL_CON1_SET_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON1_SET_SHIFT 0
+#define MT6325_TOP_CKSEL_CON1_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON1_CLR_SHIFT 0
+#define MT6325_RG_SRCVOLTEN_SW_MASK 0x1
+#define MT6325_RG_SRCVOLTEN_SW_SHIFT 0
+#define MT6325_RG_VOWEN_SW_MASK 0x1
+#define MT6325_RG_VOWEN_SW_SHIFT 1
+#define MT6325_RG_BUCK_OSC_SEL_SW_MASK 0x1
+#define MT6325_RG_BUCK_OSC_SEL_SW_SHIFT 2
+#define MT6325_RG_VCORE2_OSC_SEL_SW_MASK 0x1
+#define MT6325_RG_VCORE2_OSC_SEL_SW_SHIFT 3
+#define MT6325_RG_SRCVOLTEN_MODE_MASK 0x1
+#define MT6325_RG_SRCVOLTEN_MODE_SHIFT 4
+#define MT6325_RG_VOWEN_MODE_MASK 0x1
+#define MT6325_RG_VOWEN_MODE_SHIFT 5
+#define MT6325_RG_BUCK_OSC_SEL_MODE_MASK 0x1
+#define MT6325_RG_BUCK_OSC_SEL_MODE_SHIFT 6
+#define MT6325_RG_VCORE2_OSC_SEL_MODE_MASK 0x1
+#define MT6325_RG_VCORE2_OSC_SEL_MODE_SHIFT 7
+#define MT6325_TOP_CKSEL_CON2_RSV_MASK 0x3
+#define MT6325_TOP_CKSEL_CON2_RSV_SHIFT 8
+#define MT6325_TOP_CKSEL_CON2_SET_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON2_SET_SHIFT 0
+#define MT6325_TOP_CKSEL_CON2_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON2_CLR_SHIFT 0
+#define MT6325_RG_STRUP_LBAT_SEL_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_STRUP_LBAT_SEL_CK_DIVSEL_SHIFT 0
+#define MT6325_TOP_CKDIVSEL_CON_RSV_MASK 0x3
+#define MT6325_TOP_CKDIVSEL_CON_RSV_SHIFT 2
+#define MT6325_RG_BIF_X4_CK_DIVSEL_MASK 0x7
+#define MT6325_RG_BIF_X4_CK_DIVSEL_SHIFT 4
+#define MT6325_RG_REG_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_REG_CK_DIVSEL_SHIFT 8
+#define MT6325_RG_BUCK_18M_CK_DIVSEL_MASK 0x1
+#define MT6325_RG_BUCK_18M_CK_DIVSEL_SHIFT 10
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_MASK 0x1
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_SHIFT 11
+#define MT6325_RG_SPK_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_SPK_CK_DIVSEL_SHIFT 12
+#define MT6325_RG_SPK_PWM_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_SPK_PWM_CK_DIVSEL_SHIFT 14
+#define MT6325_TOP_CKDIVSEL_CON1_SET_MASK 0xFFFF
+#define MT6325_TOP_CKDIVSEL_CON1_SET_SHIFT 0
+#define MT6325_TOP_CKDIVSEL_CON1_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKDIVSEL_CON1_CLR_SHIFT 0
+#define MT6325_RG_G_SMPS_PD_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_G_SMPS_PD_CK_PDN_HWEN_SHIFT 0
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_HWEN_SHIFT 1
+#define MT6325_RG_G_DRV_2M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_G_DRV_2M_CK_PDN_HWEN_SHIFT 2
+#define MT6325_RG_AUXADC_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_AUXADC_CK_PDN_HWEN_SHIFT 3
+#define MT6325_RG_BUCK_1M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_BUCK_1M_CK_PDN_HWEN_SHIFT 4
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_HWEN_SHIFT 5
+#define MT6325_RG_EFUSE_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_EFUSE_CK_PDN_HWEN_SHIFT 6
+#define MT6325_RG_RTC_26M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_RTC_26M_CK_PDN_HWEN_SHIFT 7
+#define MT6325_RG_AUD18M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_AUD18M_CK_PDN_HWEN_SHIFT 8
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_HWEN_MASK 0x1
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_HWEN_SHIFT 9
+#define MT6325_RG_AUXADC_CK_CKSEL_HWEN_MASK 0x1
+#define MT6325_RG_AUXADC_CK_CKSEL_HWEN_SHIFT 10
+#define MT6325_TOP_CKHWEN_CON_RSV_MASK 0x1F
+#define MT6325_TOP_CKHWEN_CON_RSV_SHIFT 11
+#define MT6325_TOP_CKHWEN_CON_SET_MASK 0xFFFF
+#define MT6325_TOP_CKHWEN_CON_SET_SHIFT 0
+#define MT6325_TOP_CKHWEN_CON_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKHWEN_CON_CLR_SHIFT 0
+#define MT6325_RG_PMU75K_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_PMU75K_CK_TST_DIS_SHIFT 0
+#define MT6325_RG_SMPS_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_SMPS_CK_TST_DIS_SHIFT 1
+#define MT6325_RG_AUD26M_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_AUD26M_CK_TST_DIS_SHIFT 2
+#define MT6325_RG_VOW12M_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_VOW12M_CK_TST_DIS_SHIFT 3
+#define MT6325_RG_RTC32K_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_RTC32K_CK_TST_DIS_SHIFT 4
+#define MT6325_RG_SPK_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_SPK_CK_TST_DIS_SHIFT 5
+#define MT6325_RG_FG_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_FG_CK_TST_DIS_SHIFT 6
+#define MT6325_RG_RTC26M_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_RTC26M_CK_TST_DIS_SHIFT 7
+#define MT6325_TOP_CKTST_CON0_RSV_MASK 0x7F
+#define MT6325_TOP_CKTST_CON0_RSV_SHIFT 8
+#define MT6325_RG_BUCK_ANA_AUTO_OFF_DIS_MASK 0x1
+#define MT6325_RG_BUCK_ANA_AUTO_OFF_DIS_SHIFT 15
+#define MT6325_RG_DRV_ISINK0_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK0_CK_TSTSEL_SHIFT 0
+#define MT6325_RG_DRV_ISINK1_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK1_CK_TSTSEL_SHIFT 1
+#define MT6325_RG_DRV_ISINK2_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK2_CK_TSTSEL_SHIFT 2
+#define MT6325_RG_DRV_ISINK3_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK3_CK_TSTSEL_SHIFT 3
+#define MT6325_RG_FQMTR_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_FQMTR_CK_TSTSEL_SHIFT 4
+#define MT6325_RG_RTCDET_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTCDET_CK_TSTSEL_SHIFT 5
+#define MT6325_RG_PMU75K_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_PMU75K_CK_TSTSEL_SHIFT 6
+#define MT6325_RG_SMPS_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_SMPS_CK_TSTSEL_SHIFT 7
+#define MT6325_RG_AUD26M_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUD26M_CK_TSTSEL_SHIFT 8
+#define MT6325_RG_VOW12M_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_VOW12M_CK_TSTSEL_SHIFT 9
+#define MT6325_RG_AUDIF_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUDIF_CK_TSTSEL_SHIFT 10
+#define MT6325_RG_AUD_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUD_CK_TSTSEL_SHIFT 11
+#define MT6325_RG_STRUP_75K_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_STRUP_75K_CK_TSTSEL_SHIFT 12
+#define MT6325_RG_RTC32K_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTC32K_CK_TSTSEL_SHIFT 13
+#define MT6325_RG_PCHR_TEST_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_PCHR_TEST_CK_TSTSEL_SHIFT 14
+#define MT6325_RG_BGR_TEST_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_BGR_TEST_CK_TSTSEL_SHIFT 15
+#define MT6325_RG_FG_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_FG_CK_TSTSEL_SHIFT 0
+#define MT6325_RG_FGADC_ANA_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_FGADC_ANA_CK_TSTSEL_SHIFT 1
+#define MT6325_RG_SPK_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_SPK_CK_TSTSEL_SHIFT 2
+#define MT6325_RG_RTC26M_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTC26M_CK_TSTSEL_SHIFT 3
+#define MT6325_RG_RTC_EOSC32_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTC_EOSC32_CK_TSTSEL_SHIFT 4
+#define MT6325_RG_EOSC_CALI_TEST_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_EOSC_CALI_TEST_CK_TSTSEL_SHIFT 5
+#define MT6325_RG_AUXADC_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUXADC_CK_TSTSEL_SHIFT 6
+#define MT6325_TOP_CKTST_CON2_RSV_MASK 0xF
+#define MT6325_TOP_CKTST_CON2_RSV_SHIFT 7
+#define MT6325_RG_CLKSQ_EN_AUD_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUD_SHIFT 0
+#define MT6325_RG_CLKSQ_EN_FQR_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_FQR_SHIFT 1
+#define MT6325_RG_CLKSQ_EN_AUX_AP_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_AP_SHIFT 2
+#define MT6325_RG_CLKSQ_EN_AUX_MD_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_MD_SHIFT 3
+#define MT6325_RG_CLKSQ_EN_AUX_GPS_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_GPS_SHIFT 4
+#define MT6325_RG_CLKSQ_EN_AUX_RSV_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_RSV_SHIFT 5
+#define MT6325_RG_CLKSQ_EN_AUX_AP_MODE_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_AP_MODE_SHIFT 8
+#define MT6325_RG_CLKSQ_EN_AUX_MD_MODE_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_MD_MODE_SHIFT 9
+#define MT6325_TOP_CLKSQ_RSV_MASK 0x1F
+#define MT6325_TOP_CLKSQ_RSV_SHIFT 10
+#define MT6325_DA_CLKSQ_EN_VA28_MASK 0x1
+#define MT6325_DA_CLKSQ_EN_VA28_SHIFT 15
+#define MT6325_TOP_CLKSQ_SET_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_SET_SHIFT 0
+#define MT6325_TOP_CLKSQ_CLR_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_CLR_SHIFT 0
+#define MT6325_RG_CLKSQ_RTC_EN_MASK 0x1
+#define MT6325_RG_CLKSQ_RTC_EN_SHIFT 0
+#define MT6325_RG_CLKSQ_RTC_EN_HW_MODE_MASK 0x1
+#define MT6325_RG_CLKSQ_RTC_EN_HW_MODE_SHIFT 1
+#define MT6325_TOP_CLKSQ_RTC_RSV0_MASK 0xF
+#define MT6325_TOP_CLKSQ_RTC_RSV0_SHIFT 2
+#define MT6325_RG_ENBB_SEL_MASK 0x1
+#define MT6325_RG_ENBB_SEL_SHIFT 8
+#define MT6325_RG_XOSC_EN_SEL_MASK 0x1
+#define MT6325_RG_XOSC_EN_SEL_SHIFT 9
+#define MT6325_TOP_CLKSQ_RTC_RSV1_MASK 0x3
+#define MT6325_TOP_CLKSQ_RTC_RSV1_SHIFT 10
+#define MT6325_DA_CLKSQ_EN_VDIG18_MASK 0x1
+#define MT6325_DA_CLKSQ_EN_VDIG18_SHIFT 15
+#define MT6325_TOP_CLKSQ_RTC_SET_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_RTC_SET_SHIFT 0
+#define MT6325_TOP_CLKSQ_RTC_CLR_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_RTC_CLR_SHIFT 0
+#define MT6325_OSC_75K_TRIM_MASK 0x1F
+#define MT6325_OSC_75K_TRIM_SHIFT 0
+#define MT6325_RG_OSC_75K_TRIM_EN_MASK 0x1
+#define MT6325_RG_OSC_75K_TRIM_EN_SHIFT 5
+#define MT6325_RG_OSC_75K_TRIM_RATE_MASK 0x3
+#define MT6325_RG_OSC_75K_TRIM_RATE_SHIFT 6
+#define MT6325_RG_OSC_75K_TRIM_MASK 0x1F
+#define MT6325_RG_OSC_75K_TRIM_SHIFT 8
+#define MT6325_RG_EFUSE_MAN_RST_MASK 0x1
+#define MT6325_RG_EFUSE_MAN_RST_SHIFT 0
+#define MT6325_RG_AUXADC_RST_MASK 0x1
+#define MT6325_RG_AUXADC_RST_SHIFT 1
+#define MT6325_RG_AUXADC_REG_RST_MASK 0x1
+#define MT6325_RG_AUXADC_REG_RST_SHIFT 2
+#define MT6325_RG_AUDIO_RST_MASK 0x1
+#define MT6325_RG_AUDIO_RST_SHIFT 3
+#define MT6325_RG_ACCDET_RST_MASK 0x1
+#define MT6325_RG_ACCDET_RST_SHIFT 4
+#define MT6325_RG_BIF_RST_MASK 0x1
+#define MT6325_RG_BIF_RST_SHIFT 5
+#define MT6325_RG_DRIVER_RST_MASK 0x1
+#define MT6325_RG_DRIVER_RST_SHIFT 6
+#define MT6325_RG_FGADC_RST_MASK 0x1
+#define MT6325_RG_FGADC_RST_SHIFT 7
+#define MT6325_RG_FQMTR_RST_MASK 0x1
+#define MT6325_RG_FQMTR_RST_SHIFT 8
+#define MT6325_RG_RTC_RST_MASK 0x1
+#define MT6325_RG_RTC_RST_SHIFT 9
+#define MT6325_RG_SPK_RST_MASK 0x1
+#define MT6325_RG_SPK_RST_SHIFT 10
+#define MT6325_RG_CHRWDT_RST_MASK 0x1
+#define MT6325_RG_CHRWDT_RST_SHIFT 11
+#define MT6325_RG_ZCD_RST_MASK 0x1
+#define MT6325_RG_ZCD_RST_SHIFT 12
+#define MT6325_RG_AUDNCP_RST_MASK 0x1
+#define MT6325_RG_AUDNCP_RST_SHIFT 13
+#define MT6325_RG_CLK_TRIM_RST_MASK 0x1
+#define MT6325_RG_CLK_TRIM_RST_SHIFT 14
+#define MT6325_TOP_RST_CON0_RSV_MASK 0x1
+#define MT6325_TOP_RST_CON0_RSV_SHIFT 15
+#define MT6325_TOP_RST_CON_SET_MASK 0xFFFF
+#define MT6325_TOP_RST_CON_SET_SHIFT 0
+#define MT6325_TOP_RST_CON_CLR_MASK 0xFFFF
+#define MT6325_TOP_RST_CON_CLR_SHIFT 0
+#define MT6325_RG_CHR_LDO_DET_MODE_MASK 0x1
+#define MT6325_RG_CHR_LDO_DET_MODE_SHIFT 0
+#define MT6325_RG_CHR_LDO_DET_SW_MASK 0x1
+#define MT6325_RG_CHR_LDO_DET_SW_SHIFT 1
+#define MT6325_RG_CHRWDT_FLAG_MODE_MASK 0x1
+#define MT6325_RG_CHRWDT_FLAG_MODE_SHIFT 2
+#define MT6325_RG_CHRWDT_FLAG_SW_MASK 0x1
+#define MT6325_RG_CHRWDT_FLAG_SW_SHIFT 3
+#define MT6325_TOP_RST_CON1_RSV_MASK 0xF
+#define MT6325_TOP_RST_CON1_RSV_SHIFT 4
+#define MT6325_RG_WDTRSTB_EN_MASK 0x1
+#define MT6325_RG_WDTRSTB_EN_SHIFT 0
+#define MT6325_RG_WDTRSTB_MODE_MASK 0x1
+#define MT6325_RG_WDTRSTB_MODE_SHIFT 1
+#define MT6325_WDTRSTB_STATUS_MASK 0x1
+#define MT6325_WDTRSTB_STATUS_SHIFT 2
+#define MT6325_WDTRSTB_STATUS_CLR_MASK 0x1
+#define MT6325_WDTRSTB_STATUS_CLR_SHIFT 3
+#define MT6325_RG_WDTRSTB_FB_EN_MASK 0x1
+#define MT6325_RG_WDTRSTB_FB_EN_SHIFT 4
+#define MT6325_RG_HOMEKEY_RST_EN_MASK 0x1
+#define MT6325_RG_HOMEKEY_RST_EN_SHIFT 8
+#define MT6325_RG_PWRKEY_RST_EN_MASK 0x1
+#define MT6325_RG_PWRKEY_RST_EN_SHIFT 9
+#define MT6325_RG_PWRRST_TMR_DIS_MASK 0x1
+#define MT6325_RG_PWRRST_TMR_DIS_SHIFT 10
+#define MT6325_RG_PWRKEY_RST_TD_MASK 0x3
+#define MT6325_RG_PWRKEY_RST_TD_SHIFT 12
+#define MT6325_TOP_RST_MISC_SET_MASK 0xFFFF
+#define MT6325_TOP_RST_MISC_SET_SHIFT 0
+#define MT6325_TOP_RST_MISC_CLR_MASK 0xFFFF
+#define MT6325_TOP_RST_MISC_CLR_SHIFT 0
+#define MT6325_VPWRIN_RSTB_STATUS_MASK 0x1
+#define MT6325_VPWRIN_RSTB_STATUS_SHIFT 0
+#define MT6325_DDLO_RSTB_STATUS_MASK 0x1
+#define MT6325_DDLO_RSTB_STATUS_SHIFT 1
+#define MT6325_UVLO_RSTB_STATUS_MASK 0x1
+#define MT6325_UVLO_RSTB_STATUS_SHIFT 2
+#define MT6325_RTC_DDLO_RSTB_STATUS_MASK 0x1
+#define MT6325_RTC_DDLO_RSTB_STATUS_SHIFT 3
+#define MT6325_CHRWDT_REG_RSTB_STATUS_MASK 0x1
+#define MT6325_CHRWDT_REG_RSTB_STATUS_SHIFT 4
+#define MT6325_CHRDET_REG_RSTB_STATUS_MASK 0x1
+#define MT6325_CHRDET_REG_RSTB_STATUS_SHIFT 5
+#define MT6325_TOP_RST_STATUS_RSV_MASK 0x3
+#define MT6325_TOP_RST_STATUS_RSV_SHIFT 6
+#define MT6325_TOP_RST_STATUS_SET_MASK 0xFFFF
+#define MT6325_TOP_RST_STATUS_SET_SHIFT 0
+#define MT6325_TOP_RST_STATUS_CLR_MASK 0xFFFF
+#define MT6325_TOP_RST_STATUS_CLR_SHIFT 0
+#define MT6325_RG_INT_EN_PWRKEY_MASK 0x1
+#define MT6325_RG_INT_EN_PWRKEY_SHIFT 0
+#define MT6325_RG_INT_EN_HOMEKEY_MASK 0x1
+#define MT6325_RG_INT_EN_HOMEKEY_SHIFT 1
+#define MT6325_RG_INT_EN_PWRKEY_R_MASK 0x1
+#define MT6325_RG_INT_EN_PWRKEY_R_SHIFT 2
+#define MT6325_RG_INT_EN_HOMEKEY_R_MASK 0x1
+#define MT6325_RG_INT_EN_HOMEKEY_R_SHIFT 3
+#define MT6325_RG_INT_EN_THR_H_MASK 0x1
+#define MT6325_RG_INT_EN_THR_H_SHIFT 4
+#define MT6325_RG_INT_EN_THR_L_MASK 0x1
+#define MT6325_RG_INT_EN_THR_L_SHIFT 5
+#define MT6325_RG_INT_EN_BAT_H_MASK 0x1
+#define MT6325_RG_INT_EN_BAT_H_SHIFT 6
+#define MT6325_RG_INT_EN_BAT_L_MASK 0x1
+#define MT6325_RG_INT_EN_BAT_L_SHIFT 7
+#define MT6325_RG_INT_EN_BIF_MASK 0x1
+#define MT6325_RG_INT_EN_BIF_SHIFT 8
+#define MT6325_RG_INT_EN_RTC_MASK 0x1
+#define MT6325_RG_INT_EN_RTC_SHIFT 9
+#define MT6325_RG_INT_EN_AUDIO_MASK 0x1
+#define MT6325_RG_INT_EN_AUDIO_SHIFT 10
+#define MT6325_RG_INT_EN_VOW_MASK 0x1
+#define MT6325_RG_INT_EN_VOW_SHIFT 11
+#define MT6325_RG_INT_EN_ACCDET_MASK 0x1
+#define MT6325_RG_INT_EN_ACCDET_SHIFT 12
+#define MT6325_RG_INT_EN_ACCDET_EINT_MASK 0x1
+#define MT6325_RG_INT_EN_ACCDET_EINT_SHIFT 13
+#define MT6325_RG_INT_EN_ACCDET_NEGV_MASK 0x1
+#define MT6325_RG_INT_EN_ACCDET_NEGV_SHIFT 14
+#define MT6325_RG_INT_EN_NI_LBAT_INT_MASK 0x1
+#define MT6325_RG_INT_EN_NI_LBAT_INT_SHIFT 15
+#define MT6325_INT_CON0_SET_MASK 0xFFFF
+#define MT6325_INT_CON0_SET_SHIFT 0
+#define MT6325_INT_CON0_CLR_MASK 0xFFFF
+#define MT6325_INT_CON0_CLR_SHIFT 0
+#define MT6325_RG_INT_EN_VDVFS11_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VDVFS11_OC_SHIFT 0
+#define MT6325_RG_INT_EN_VDVFS12_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VDVFS12_OC_SHIFT 1
+#define MT6325_RG_INT_EN_VRF18_0_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VRF18_0_OC_SHIFT 2
+#define MT6325_RG_INT_EN_VDRAM_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VDRAM_OC_SHIFT 3
+#define MT6325_RG_INT_EN_VGPU_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VGPU_OC_SHIFT 4
+#define MT6325_RG_INT_EN_VCORE1_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VCORE1_OC_SHIFT 5
+#define MT6325_RG_INT_EN_VCORE2_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VCORE2_OC_SHIFT 6
+#define MT6325_RG_INT_EN_VIO18_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VIO18_OC_SHIFT 7
+#define MT6325_RG_INT_EN_VPA_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VPA_OC_SHIFT 8
+#define MT6325_RG_INT_EN_LDO_OC_MASK 0x1
+#define MT6325_RG_INT_EN_LDO_OC_SHIFT 9
+#define MT6325_RG_INT_EN_BAT2_H_MASK 0x1
+#define MT6325_RG_INT_EN_BAT2_H_SHIFT 10
+#define MT6325_RG_INT_EN_BAT2_L_MASK 0x1
+#define MT6325_RG_INT_EN_BAT2_L_SHIFT 11
+#define MT6325_RG_INT_EN_VISMPS0_H_MASK 0x1
+#define MT6325_RG_INT_EN_VISMPS0_H_SHIFT 12
+#define MT6325_RG_INT_EN_VISMPS0_L_MASK 0x1
+#define MT6325_RG_INT_EN_VISMPS0_L_SHIFT 13
+#define MT6325_RG_INT_EN_AUXADC_IMP_MASK 0x1
+#define MT6325_RG_INT_EN_AUXADC_IMP_SHIFT 14
+#define MT6325_INT_CON1_SET_MASK 0xFFFF
+#define MT6325_INT_CON1_SET_SHIFT 0
+#define MT6325_INT_CON1_CLR_MASK 0xFFFF
+#define MT6325_INT_CON1_CLR_SHIFT 0
+#define MT6325_RG_INT_EN_OV_MASK 0x1
+#define MT6325_RG_INT_EN_OV_SHIFT 0
+#define MT6325_RG_INT_EN_BVALID_DET_MASK 0x1
+#define MT6325_RG_INT_EN_BVALID_DET_SHIFT 1
+#define MT6325_RG_INT_EN_VBATON_UNDET_MASK 0x1
+#define MT6325_RG_INT_EN_VBATON_UNDET_SHIFT 2
+#define MT6325_RG_INT_EN_WATCHDOG_MASK 0x1
+#define MT6325_RG_INT_EN_WATCHDOG_SHIFT 3
+#define MT6325_RG_INT_EN_PCHR_CM_VDEC_MASK 0x1
+#define MT6325_RG_INT_EN_PCHR_CM_VDEC_SHIFT 4
+#define MT6325_RG_INT_EN_CHRDET_MASK 0x1
+#define MT6325_RG_INT_EN_CHRDET_SHIFT 5
+#define MT6325_RG_INT_EN_PCHR_CM_VINC_MASK 0x1
+#define MT6325_RG_INT_EN_PCHR_CM_VINC_SHIFT 6
+#define MT6325_RG_INT_EN_FG_BAT_H_MASK 0x1
+#define MT6325_RG_INT_EN_FG_BAT_H_SHIFT 7
+#define MT6325_RG_INT_EN_FG_BAT_L_MASK 0x1
+#define MT6325_RG_INT_EN_FG_BAT_L_SHIFT 8
+#define MT6325_RG_INT_EN_FG_CUR_H_MASK 0x1
+#define MT6325_RG_INT_EN_FG_CUR_H_SHIFT 9
+#define MT6325_RG_INT_EN_FG_CUR_L_MASK 0x1
+#define MT6325_RG_INT_EN_FG_CUR_L_SHIFT 10
+#define MT6325_RG_INT_EN_FG_ZCV_MASK 0x1
+#define MT6325_RG_INT_EN_FG_ZCV_SHIFT 11
+#define MT6325_RG_INT_EN_SPKL_D_MASK 0x1
+#define MT6325_RG_INT_EN_SPKL_D_SHIFT 12
+#define MT6325_RG_INT_EN_SPKL_AB_MASK 0x1
+#define MT6325_RG_INT_EN_SPKL_AB_SHIFT 13
+#define MT6325_INT_CON2_SET_MASK 0xFFFF
+#define MT6325_INT_CON2_SET_SHIFT 0
+#define MT6325_INT_CON2_CLR_MASK 0xFFFF
+#define MT6325_INT_CON2_CLR_SHIFT 0
+#define MT6325_POLARITY_MASK 0x1
+#define MT6325_POLARITY_SHIFT 0
+#define MT6325_RG_HOMEKEY_INT_SEL_MASK 0x1
+#define MT6325_RG_HOMEKEY_INT_SEL_SHIFT 1
+#define MT6325_RG_PWRKEY_INT_SEL_MASK 0x1
+#define MT6325_RG_PWRKEY_INT_SEL_SHIFT 2
+#define MT6325_RG_CHRDET_INT_SEL_MASK 0x1
+#define MT6325_RG_CHRDET_INT_SEL_SHIFT 3
+#define MT6325_RG_PCHR_CM_VINC_POLARITY_RSV_MASK 0x1
+#define MT6325_RG_PCHR_CM_VINC_POLARITY_RSV_SHIFT 4
+#define MT6325_RG_PCHR_CM_VDEC_POLARITY_RSV_MASK 0x1
+#define MT6325_RG_PCHR_CM_VDEC_POLARITY_RSV_SHIFT 5
+#define MT6325_INT_MISC_CON_SET_MASK 0xFFFF
+#define MT6325_INT_MISC_CON_SET_SHIFT 0
+#define MT6325_INT_MISC_CON_CLR_MASK 0xFFFF
+#define MT6325_INT_MISC_CON_CLR_SHIFT 0
+#define MT6325_RG_INT_STATUS_PWRKEY_MASK 0x1
+#define MT6325_RG_INT_STATUS_PWRKEY_SHIFT 0
+#define MT6325_RG_INT_STATUS_HOMEKEY_MASK 0x1
+#define MT6325_RG_INT_STATUS_HOMEKEY_SHIFT 1
+#define MT6325_RG_INT_STATUS_PWRKEY_R_MASK 0x1
+#define MT6325_RG_INT_STATUS_PWRKEY_R_SHIFT 2
+#define MT6325_RG_INT_STATUS_HOMEKEY_R_MASK 0x1
+#define MT6325_RG_INT_STATUS_HOMEKEY_R_SHIFT 3
+#define MT6325_RG_INT_STATUS_THR_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_THR_H_SHIFT 4
+#define MT6325_RG_INT_STATUS_THR_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_THR_L_SHIFT 5
+#define MT6325_RG_INT_STATUS_BAT_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT_H_SHIFT 6
+#define MT6325_RG_INT_STATUS_BAT_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT_L_SHIFT 7
+#define MT6325_RG_INT_STATUS_BIF_MASK 0x1
+#define MT6325_RG_INT_STATUS_BIF_SHIFT 8
+#define MT6325_RG_INT_STATUS_RTC_MASK 0x1
+#define MT6325_RG_INT_STATUS_RTC_SHIFT 9
+#define MT6325_RG_INT_STATUS_AUDIO_MASK 0x1
+#define MT6325_RG_INT_STATUS_AUDIO_SHIFT 10
+#define MT6325_RG_INT_STATUS_VOW_MASK 0x1
+#define MT6325_RG_INT_STATUS_VOW_SHIFT 11
+#define MT6325_RG_INT_STATUS_ACCDET_MASK 0x1
+#define MT6325_RG_INT_STATUS_ACCDET_SHIFT 12
+#define MT6325_RG_INT_STATUS_ACCDET_EINT_MASK 0x1
+#define MT6325_RG_INT_STATUS_ACCDET_EINT_SHIFT 13
+#define MT6325_RG_INT_STATUS_ACCDET_NEGV_MASK 0x1
+#define MT6325_RG_INT_STATUS_ACCDET_NEGV_SHIFT 14
+#define MT6325_RG_INT_STATUS_NI_LBAT_INT_MASK 0x1
+#define MT6325_RG_INT_STATUS_NI_LBAT_INT_SHIFT 15
+#define MT6325_RG_INT_STATUS_VDVFS11_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VDVFS11_OC_SHIFT 0
+#define MT6325_RG_INT_STATUS_VDVFS12_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VDVFS12_OC_SHIFT 1
+#define MT6325_RG_INT_STATUS_VRF18_0_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VRF18_0_OC_SHIFT 2
+#define MT6325_RG_INT_STATUS_VDRAM_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VDRAM_OC_SHIFT 3
+#define MT6325_RG_INT_STATUS_VGPU_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VGPU_OC_SHIFT 4
+#define MT6325_RG_INT_STATUS_VCORE1_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VCORE1_OC_SHIFT 5
+#define MT6325_RG_INT_STATUS_VCORE2_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VCORE2_OC_SHIFT 6
+#define MT6325_RG_INT_STATUS_VIO18_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VIO18_OC_SHIFT 7
+#define MT6325_RG_INT_STATUS_VPA_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VPA_OC_SHIFT 8
+#define MT6325_RG_INT_STATUS_LDO_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_LDO_OC_SHIFT 9
+#define MT6325_RG_INT_STATUS_BAT2_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT2_H_SHIFT 10
+#define MT6325_RG_INT_STATUS_BAT2_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT2_L_SHIFT 11
+#define MT6325_RG_INT_STATUS_VISMPS0_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_VISMPS0_H_SHIFT 12
+#define MT6325_RG_INT_STATUS_VISMPS0_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_VISMPS0_L_SHIFT 13
+#define MT6325_RG_INT_STATUS_AUXADC_IMP_MASK 0x1
+#define MT6325_RG_INT_STATUS_AUXADC_IMP_SHIFT 14
+#define MT6325_RG_INT_STATUS_OV_MASK 0x1
+#define MT6325_RG_INT_STATUS_OV_SHIFT 0
+#define MT6325_RG_INT_STATUS_BVALID_DET_MASK 0x1
+#define MT6325_RG_INT_STATUS_BVALID_DET_SHIFT 1
+#define MT6325_RG_INT_STATUS_VBATON_UNDET_MASK 0x1
+#define MT6325_RG_INT_STATUS_VBATON_UNDET_SHIFT 2
+#define MT6325_RG_INT_STATUS_WATCHDOG_MASK 0x1
+#define MT6325_RG_INT_STATUS_WATCHDOG_SHIFT 3
+#define MT6325_RG_INT_STATUS_PCHR_CM_VDEC_MASK 0x1
+#define MT6325_RG_INT_STATUS_PCHR_CM_VDEC_SHIFT 4
+#define MT6325_RG_INT_STATUS_CHRDET_MASK 0x1
+#define MT6325_RG_INT_STATUS_CHRDET_SHIFT 5
+#define MT6325_RG_INT_STATUS_PCHR_CM_VINC_MASK 0x1
+#define MT6325_RG_INT_STATUS_PCHR_CM_VINC_SHIFT 6
+#define MT6325_RG_INT_STATUS_FG_BAT_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_BAT_H_SHIFT 7
+#define MT6325_RG_INT_STATUS_FG_BAT_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_BAT_L_SHIFT 8
+#define MT6325_RG_INT_STATUS_FG_CUR_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_CUR_H_SHIFT 9
+#define MT6325_RG_INT_STATUS_FG_CUR_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_CUR_L_SHIFT 10
+#define MT6325_RG_INT_STATUS_FG_ZCV_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_ZCV_SHIFT 11
+#define MT6325_RG_INT_STATUS_SPKL_D_MASK 0x1
+#define MT6325_RG_INT_STATUS_SPKL_D_SHIFT 12
+#define MT6325_RG_INT_STATUS_SPKL_AB_MASK 0x1
+#define MT6325_RG_INT_STATUS_SPKL_AB_SHIFT 13
+#define MT6325_OC_GEAR_LDO_MASK 0x3
+#define MT6325_OC_GEAR_LDO_SHIFT 0
+#define MT6325_FQMTR_TCKSEL_MASK 0x7
+#define MT6325_FQMTR_TCKSEL_SHIFT 0
+#define MT6325_FQMTR_BUSY_MASK 0x1
+#define MT6325_FQMTR_BUSY_SHIFT 3
+#define MT6325_FQMTR_EN_MASK 0x1
+#define MT6325_FQMTR_EN_SHIFT 15
+#define MT6325_FQMTR_WINSET_MASK 0xFFFF
+#define MT6325_FQMTR_WINSET_SHIFT 0
+#define MT6325_FQMTR_DATA_MASK 0xFFFF
+#define MT6325_FQMTR_DATA_SHIFT 0
+#define MT6325_RG_SLP_RW_EN_MASK 0x1
+#define MT6325_RG_SLP_RW_EN_SHIFT 0
+#define MT6325_RG_SPI_RSV_MASK 0x7FFF
+#define MT6325_RG_SPI_RSV_SHIFT 1
+#define MT6325_DEW_DIO_EN_MASK 0x1
+#define MT6325_DEW_DIO_EN_SHIFT 0
+#define MT6325_DEW_READ_TEST_MASK 0xFFFF
+#define MT6325_DEW_READ_TEST_SHIFT 0
+#define MT6325_DEW_WRITE_TEST_MASK 0xFFFF
+#define MT6325_DEW_WRITE_TEST_SHIFT 0
+#define MT6325_DEW_CRC_SWRST_MASK 0x1
+#define MT6325_DEW_CRC_SWRST_SHIFT 0
+#define MT6325_DEW_CRC_EN_MASK 0x1
+#define MT6325_DEW_CRC_EN_SHIFT 0
+#define MT6325_DEW_CRC_VAL_MASK 0xFF
+#define MT6325_DEW_CRC_VAL_SHIFT 0
+#define MT6325_DEW_DBG_MON_SEL_MASK 0xF
+#define MT6325_DEW_DBG_MON_SEL_SHIFT 0
+#define MT6325_DEW_CIPHER_KEY_SEL_MASK 0x3
+#define MT6325_DEW_CIPHER_KEY_SEL_SHIFT 0
+#define MT6325_DEW_CIPHER_IV_SEL_MASK 0x3
+#define MT6325_DEW_CIPHER_IV_SEL_SHIFT 0
+#define MT6325_DEW_CIPHER_EN_MASK 0x1
+#define MT6325_DEW_CIPHER_EN_SHIFT 0
+#define MT6325_DEW_CIPHER_RDY_MASK 0x1
+#define MT6325_DEW_CIPHER_RDY_SHIFT 0
+#define MT6325_DEW_CIPHER_MODE_MASK 0x1
+#define MT6325_DEW_CIPHER_MODE_SHIFT 0
+#define MT6325_DEW_CIPHER_SWRST_MASK 0x1
+#define MT6325_DEW_CIPHER_SWRST_SHIFT 0
+#define MT6325_DEW_RDDMY_NO_MASK 0xF
+#define MT6325_DEW_RDDMY_NO_SHIFT 0
+#define MT6325_INT_TYPE_CON0_MASK 0xFFFF
+#define MT6325_INT_TYPE_CON0_SHIFT 0
+#define MT6325_INT_TYPE_CON0_SET_MASK 0xFFFF
+#define MT6325_INT_TYPE_CON0_SET_SHIFT 0
+#define MT6325_INT_TYPE_CON0_CLR_MASK 0xFFFF
+#define MT6325_INT_TYPE_CON0_CLR_SHIFT 0
+#define MT6325_INT_TYPE_CON1_MASK 0x7FFF
+#define MT6325_INT_TYPE_CON1_SHIFT 0
+#define MT6325_INT_TYPE_CON1_SET_MASK 0x7FFF
+#define MT6325_INT_TYPE_CON1_SET_SHIFT 0
+#define MT6325_INT_TYPE_CON1_CLR_MASK 0x7FFF
+#define MT6325_INT_TYPE_CON1_CLR_SHIFT 0
+#define MT6325_INT_TYPE_CON2_MASK 0x3FFF
+#define MT6325_INT_TYPE_CON2_SHIFT 0
+#define MT6325_INT_TYPE_CON2_SET_MASK 0x3FFF
+#define MT6325_INT_TYPE_CON2_SET_SHIFT 0
+#define MT6325_INT_TYPE_CON2_CLR_MASK 0x3FFF
+#define MT6325_INT_TYPE_CON2_CLR_SHIFT 0
+#define MT6325_CPU_INT_STA_MASK 0x1
+#define MT6325_CPU_INT_STA_SHIFT 0
+#define MT6325_MD32_INT_STA_MASK 0x1
+#define MT6325_MD32_INT_STA_SHIFT 1
+#define MT6325_BUCK_ALL_RSV0_MASK 0xFF
+#define MT6325_BUCK_ALL_RSV0_SHIFT 8
+#define MT6325_VSLEEP_SRC0_MASK 0x1FF
+#define MT6325_VSLEEP_SRC0_SHIFT 0
+#define MT6325_VSLEEP_SRC1_MASK 0xF
+#define MT6325_VSLEEP_SRC1_SHIFT 12
+#define MT6325_R2R_SRC0_MASK 0x1FF
+#define MT6325_R2R_SRC0_SHIFT 0
+#define MT6325_R2R_SRC1_MASK 0xF
+#define MT6325_R2R_SRC1_SHIFT 12
+#define MT6325_BUCK_OSC_SEL_SRC0_MASK 0x1FF
+#define MT6325_BUCK_OSC_SEL_SRC0_SHIFT 0
+#define MT6325_SRCLKEN_DLY_SRC1_MASK 0xF
+#define MT6325_SRCLKEN_DLY_SRC1_SHIFT 12
+#define MT6325_BUCK_CON5_RSV0_MASK 0xFFFF
+#define MT6325_BUCK_CON5_RSV0_SHIFT 0
+#define MT6325_QI_VGPU_DIG_MON_MASK 0xF
+#define MT6325_QI_VGPU_DIG_MON_SHIFT 0
+#define MT6325_QI_VIO18_DIG_MON_MASK 0xF
+#define MT6325_QI_VIO18_DIG_MON_SHIFT 4
+#define MT6325_QI_VCORE1_DIG_MON_MASK 0xF
+#define MT6325_QI_VCORE1_DIG_MON_SHIFT 0
+#define MT6325_QI_VCORE2_DIG_MON_MASK 0xF
+#define MT6325_QI_VCORE2_DIG_MON_SHIFT 4
+#define MT6325_QI_VRF18_0_DIG_MON_MASK 0xF
+#define MT6325_QI_VRF18_0_DIG_MON_SHIFT 0
+#define MT6325_QI_VPA_DIG_MON_MASK 0xFF
+#define MT6325_QI_VPA_DIG_MON_SHIFT 8
+#define MT6325_QI_VDVFS11_DIG_MON_MASK 0xFF
+#define MT6325_QI_VDVFS11_DIG_MON_SHIFT 0
+#define MT6325_QI_VDVFS12_DIG_MON_MASK 0xFF
+#define MT6325_QI_VDVFS12_DIG_MON_SHIFT 8
+#define MT6325_VDVFS11_OC_EN_MASK 0x1
+#define MT6325_VDVFS11_OC_EN_SHIFT 0
+#define MT6325_VDVFS11_OC_DEG_EN_MASK 0x1
+#define MT6325_VDVFS11_OC_DEG_EN_SHIFT 1
+#define MT6325_VDVFS11_OC_WND_MASK 0x3
+#define MT6325_VDVFS11_OC_WND_SHIFT 2
+#define MT6325_VDVFS11_OC_THD_MASK 0x3
+#define MT6325_VDVFS11_OC_THD_SHIFT 6
+#define MT6325_VDVFS12_OC_EN_MASK 0x1
+#define MT6325_VDVFS12_OC_EN_SHIFT 0
+#define MT6325_VDVFS12_OC_DEG_EN_MASK 0x1
+#define MT6325_VDVFS12_OC_DEG_EN_SHIFT 1
+#define MT6325_VDVFS12_OC_WND_MASK 0x3
+#define MT6325_VDVFS12_OC_WND_SHIFT 2
+#define MT6325_VDVFS12_OC_THD_MASK 0x3
+#define MT6325_VDVFS12_OC_THD_SHIFT 6
+#define MT6325_VRF18_0_OC_EN_MASK 0x1
+#define MT6325_VRF18_0_OC_EN_SHIFT 0
+#define MT6325_VRF18_0_OC_DEG_EN_MASK 0x1
+#define MT6325_VRF18_0_OC_DEG_EN_SHIFT 1
+#define MT6325_VRF18_0_OC_WND_MASK 0x3
+#define MT6325_VRF18_0_OC_WND_SHIFT 2
+#define MT6325_VRF18_0_OC_THD_MASK 0x3
+#define MT6325_VRF18_0_OC_THD_SHIFT 6
+#define MT6325_VPA_OC_EN_MASK 0x1
+#define MT6325_VPA_OC_EN_SHIFT 0
+#define MT6325_VPA_OC_DEG_EN_MASK 0x1
+#define MT6325_VPA_OC_DEG_EN_SHIFT 1
+#define MT6325_VPA_OC_WND_MASK 0x3
+#define MT6325_VPA_OC_WND_SHIFT 2
+#define MT6325_VPA_OC_THD_MASK 0x3
+#define MT6325_VPA_OC_THD_SHIFT 6
+#define MT6325_VGPU_OC_EN_MASK 0x1
+#define MT6325_VGPU_OC_EN_SHIFT 0
+#define MT6325_VGPU_OC_DEG_EN_MASK 0x1
+#define MT6325_VGPU_OC_DEG_EN_SHIFT 1
+#define MT6325_VGPU_OC_WND_MASK 0x3
+#define MT6325_VGPU_OC_WND_SHIFT 2
+#define MT6325_VGPU_OC_THD_MASK 0x3
+#define MT6325_VGPU_OC_THD_SHIFT 6
+#define MT6325_VCORE1_OC_EN_MASK 0x1
+#define MT6325_VCORE1_OC_EN_SHIFT 0
+#define MT6325_VCORE1_OC_DEG_EN_MASK 0x1
+#define MT6325_VCORE1_OC_DEG_EN_SHIFT 1
+#define MT6325_VCORE1_OC_WND_MASK 0x3
+#define MT6325_VCORE1_OC_WND_SHIFT 2
+#define MT6325_VCORE1_OC_THD_MASK 0x3
+#define MT6325_VCORE1_OC_THD_SHIFT 6
+#define MT6325_VCORE2_OC_EN_MASK 0x1
+#define MT6325_VCORE2_OC_EN_SHIFT 0
+#define MT6325_VCORE2_OC_DEG_EN_MASK 0x1
+#define MT6325_VCORE2_OC_DEG_EN_SHIFT 1
+#define MT6325_VCORE2_OC_WND_MASK 0x3
+#define MT6325_VCORE2_OC_WND_SHIFT 2
+#define MT6325_VCORE2_OC_THD_MASK 0x3
+#define MT6325_VCORE2_OC_THD_SHIFT 6
+#define MT6325_VIO18_OC_EN_MASK 0x1
+#define MT6325_VIO18_OC_EN_SHIFT 0
+#define MT6325_VIO18_OC_DEG_EN_MASK 0x1
+#define MT6325_VIO18_OC_DEG_EN_SHIFT 1
+#define MT6325_VIO18_OC_WND_MASK 0x3
+#define MT6325_VIO18_OC_WND_SHIFT 2
+#define MT6325_VIO18_OC_THD_MASK 0x3
+#define MT6325_VIO18_OC_THD_SHIFT 6
+#define MT6325_VDRAM_OC_EN_MASK 0x1
+#define MT6325_VDRAM_OC_EN_SHIFT 0
+#define MT6325_VDRAM_OC_DEG_EN_MASK 0x1
+#define MT6325_VDRAM_OC_DEG_EN_SHIFT 1
+#define MT6325_VDRAM_OC_WND_MASK 0x3
+#define MT6325_VDRAM_OC_WND_SHIFT 2
+#define MT6325_VDRAM_OC_THD_MASK 0x3
+#define MT6325_VDRAM_OC_THD_SHIFT 6
+#define MT6325_VDVFS11_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VDVFS11_OC_FLAG_CLR_SHIFT 0
+#define MT6325_VDVFS12_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VDVFS12_OC_FLAG_CLR_SHIFT 1
+#define MT6325_VRF18_0_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VRF18_0_OC_FLAG_CLR_SHIFT 2
+#define MT6325_VPA_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VPA_OC_FLAG_CLR_SHIFT 3
+#define MT6325_VGPU_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VGPU_OC_FLAG_CLR_SHIFT 4
+#define MT6325_VCORE1_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VCORE1_OC_FLAG_CLR_SHIFT 5
+#define MT6325_VCORE2_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VCORE2_OC_FLAG_CLR_SHIFT 6
+#define MT6325_VIO18_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VIO18_OC_FLAG_CLR_SHIFT 7
+#define MT6325_VDRAM_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VDRAM_OC_FLAG_CLR_SHIFT 8
+#define MT6325_VDVFS11_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VDVFS11_OC_FLAG_CLR_SEL_SHIFT 0
+#define MT6325_VDVFS12_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VDVFS12_OC_FLAG_CLR_SEL_SHIFT 1
+#define MT6325_VRF18_0_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VRF18_0_OC_FLAG_CLR_SEL_SHIFT 2
+#define MT6325_VPA_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VPA_OC_FLAG_CLR_SEL_SHIFT 3
+#define MT6325_VGPU_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VGPU_OC_FLAG_CLR_SEL_SHIFT 4
+#define MT6325_VCORE1_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VCORE1_OC_FLAG_CLR_SEL_SHIFT 5
+#define MT6325_VCORE2_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VCORE2_OC_FLAG_CLR_SEL_SHIFT 6
+#define MT6325_VIO18_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VIO18_OC_FLAG_CLR_SEL_SHIFT 7
+#define MT6325_VDRAM_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VDRAM_OC_FLAG_CLR_SEL_SHIFT 8
+#define MT6325_VDVFS11_OC_STATUS_MASK 0x1
+#define MT6325_VDVFS11_OC_STATUS_SHIFT 0
+#define MT6325_VDVFS12_OC_STATUS_MASK 0x1
+#define MT6325_VDVFS12_OC_STATUS_SHIFT 1
+#define MT6325_VRF18_0_OC_STATUS_MASK 0x1
+#define MT6325_VRF18_0_OC_STATUS_SHIFT 2
+#define MT6325_VPA_OC_STATUS_MASK 0x1
+#define MT6325_VPA_OC_STATUS_SHIFT 3
+#define MT6325_VGPU_OC_STATUS_MASK 0x1
+#define MT6325_VGPU_OC_STATUS_SHIFT 4
+#define MT6325_VCORE1_OC_STATUS_MASK 0x1
+#define MT6325_VCORE1_OC_STATUS_SHIFT 5
+#define MT6325_VCORE2_OC_STATUS_MASK 0x1
+#define MT6325_VCORE2_OC_STATUS_SHIFT 6
+#define MT6325_VIO18_OC_STATUS_MASK 0x1
+#define MT6325_VIO18_OC_STATUS_SHIFT 7
+#define MT6325_VDRAM_OC_STATUS_MASK 0x1
+#define MT6325_VDRAM_OC_STATUS_SHIFT 8
+#define MT6325_VDVFS11_OC_INT_EN_MASK 0x1
+#define MT6325_VDVFS11_OC_INT_EN_SHIFT 0
+#define MT6325_VDVFS12_OC_INT_EN_MASK 0x1
+#define MT6325_VDVFS12_OC_INT_EN_SHIFT 1
+#define MT6325_VRF18_0_OC_INT_EN_MASK 0x1
+#define MT6325_VRF18_0_OC_INT_EN_SHIFT 2
+#define MT6325_VPA_OC_INT_EN_MASK 0x1
+#define MT6325_VPA_OC_INT_EN_SHIFT 3
+#define MT6325_VGPU_OC_INT_EN_MASK 0x1
+#define MT6325_VGPU_OC_INT_EN_SHIFT 4
+#define MT6325_VCORE1_OC_INT_EN_MASK 0x1
+#define MT6325_VCORE1_OC_INT_EN_SHIFT 5
+#define MT6325_VCORE2_OC_INT_EN_MASK 0x1
+#define MT6325_VCORE2_OC_INT_EN_SHIFT 6
+#define MT6325_VIO18_OC_INT_EN_MASK 0x1
+#define MT6325_VIO18_OC_INT_EN_SHIFT 7
+#define MT6325_VDRAM_OC_INT_EN_MASK 0x1
+#define MT6325_VDRAM_OC_INT_EN_SHIFT 8
+#define MT6325_VDVFS11_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VDVFS11_EN_OC_SDN_SEL_SHIFT 0
+#define MT6325_VDVFS12_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VDVFS12_EN_OC_SDN_SEL_SHIFT 1
+#define MT6325_VRF18_0_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VRF18_0_EN_OC_SDN_SEL_SHIFT 2
+#define MT6325_VPA_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VPA_EN_OC_SDN_SEL_SHIFT 3
+#define MT6325_VGPU_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VGPU_EN_OC_SDN_SEL_SHIFT 4
+#define MT6325_VCORE1_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VCORE1_EN_OC_SDN_SEL_SHIFT 5
+#define MT6325_VCORE2_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VCORE2_EN_OC_SDN_SEL_SHIFT 6
+#define MT6325_VIO18_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VIO18_EN_OC_SDN_SEL_SHIFT 7
+#define MT6325_VDRAM_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VDRAM_EN_OC_SDN_SEL_SHIFT 8
+#define MT6325_VSRAM_DVFS1_TRACK_SLEEP_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_TRACK_SLEEP_CTRL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_TRACK_ON_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_TRACK_ON_CTRL_SHIFT 1
+#define MT6325_VDVFS1_TRACK_ON_CTRL_MASK 0x1
+#define MT6325_VDVFS1_TRACK_ON_CTRL_SHIFT 2
+#define MT6325_VSRAM_DVFS1_VOSEL_DELTA_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_DELTA_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_OFFSET_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_OFFSET_SHIFT 8
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_LB_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_LB_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_HB_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_HB_SHIFT 8
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_LB_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_LB_SHIFT 0
+#define MT6325_QI_VDVFS11_VSLEEP_MASK 0x3
+#define MT6325_QI_VDVFS11_VSLEEP_SHIFT 0
+#define MT6325_QI_VDVFS12_VSLEEP_MASK 0x3
+#define MT6325_QI_VDVFS12_VSLEEP_SHIFT 2
+#define MT6325_QI_VGPU_VSLEEP_MASK 0x3
+#define MT6325_QI_VGPU_VSLEEP_SHIFT 4
+#define MT6325_QI_VCORE1_VSLEEP_MASK 0x3
+#define MT6325_QI_VCORE1_VSLEEP_SHIFT 6
+#define MT6325_QI_VCORE2_VSLEEP_MASK 0x3
+#define MT6325_QI_VCORE2_VSLEEP_SHIFT 8
+#define MT6325_QI_VDRAM_VSLEEP_MASK 0x3
+#define MT6325_QI_VDRAM_VSLEEP_SHIFT 10
+#define MT6325_QI_VSRAM_DVFS1_VSLEEP_MASK 0x3
+#define MT6325_QI_VSRAM_DVFS1_VSLEEP_SHIFT 12
+#define MT6325_QI_VDVFS11_VSLEEP_RSV0_MASK 0x1
+#define MT6325_QI_VDVFS11_VSLEEP_RSV0_SHIFT 0
+#define MT6325_QI_VDVFS12_VSLEEP_RSV0_MASK 0x1
+#define MT6325_QI_VDVFS12_VSLEEP_RSV0_SHIFT 1
+#define MT6325_QI_VGPU_MODE_MASK 0x1
+#define MT6325_QI_VGPU_MODE_SHIFT 2
+#define MT6325_QI_VCORE1_MODE_MASK 0x1
+#define MT6325_QI_VCORE1_MODE_SHIFT 3
+#define MT6325_QI_VCORE2_MODE_MASK 0x1
+#define MT6325_QI_VCORE2_MODE_SHIFT 4
+#define MT6325_QI_VDRAM_MODE_MASK 0x1
+#define MT6325_QI_VDRAM_MODE_SHIFT 5
+#define MT6325_QI_VRF18_0_MODE_MASK 0x1
+#define MT6325_QI_VRF18_0_MODE_SHIFT 6
+#define MT6325_QI_VIO18_MODE_MASK 0x1
+#define MT6325_QI_VIO18_MODE_SHIFT 7
+#define MT6325_RG_VDRAM_MIN_OFF_MASK 0x3
+#define MT6325_RG_VDRAM_MIN_OFF_SHIFT 0
+#define MT6325_RG_VDRAM_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VDRAM_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VDRAM_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VDRAM_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VDRAM_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VDRAM_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VDRAM_RZSEL_MASK 0x7
+#define MT6325_RG_VDRAM_RZSEL_SHIFT 5
+#define MT6325_RG_VDRAM_CC_MASK 0x3
+#define MT6325_RG_VDRAM_CC_SHIFT 8
+#define MT6325_RG_VDRAM_CSR_MASK 0x7
+#define MT6325_RG_VDRAM_CSR_SHIFT 10
+#define MT6325_RG_VDRAM_CSL_MASK 0xF
+#define MT6325_RG_VDRAM_CSL_SHIFT 0
+#define MT6325_RG_VDRAM_SLP_MASK 0x7
+#define MT6325_RG_VDRAM_SLP_SHIFT 4
+#define MT6325_RG_VDRAM_ZX_OS_MASK 0x3
+#define MT6325_RG_VDRAM_ZX_OS_SHIFT 7
+#define MT6325_RG_VDRAM_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VDRAM_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VDRAM_MODESET_MASK 0x1
+#define MT6325_RG_VDRAM_MODESET_SHIFT 15
+#define MT6325_RG_VDRAM_NDIS_EN_MASK 0x1
+#define MT6325_RG_VDRAM_NDIS_EN_SHIFT 0
+#define MT6325_RG_VDRAM_CSM_MASK 0x3F
+#define MT6325_RG_VDRAM_CSM_SHIFT 1
+#define MT6325_RG_VDRAM_RSV_MASK 0xFF
+#define MT6325_RG_VDRAM_RSV_SHIFT 7
+#define MT6325_RG_VDRAM_PFM_RIP_MASK 0x7
+#define MT6325_RG_VDRAM_PFM_RIP_SHIFT 0
+#define MT6325_RG_VDRAM_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VDRAM_TRAN_BST_SHIFT 3
+#define MT6325_RG_VDRAM_DTS_ENB_MASK 0x1
+#define MT6325_RG_VDRAM_DTS_ENB_SHIFT 9
+#define MT6325_RG_VDRAM_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VDRAM_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VDRAM_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VDRAM_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VDRAM_C2_RSV_MASK 0x1
+#define MT6325_RG_VDRAM_C2_RSV_SHIFT 0
+#define MT6325_RG_VCORE1_MIN_OFF_MASK 0x3
+#define MT6325_RG_VCORE1_MIN_OFF_SHIFT 0
+#define MT6325_RG_VCORE1_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VCORE1_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VCORE1_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VCORE1_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VCORE1_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VCORE1_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VCORE1_RZSEL_MASK 0x7
+#define MT6325_RG_VCORE1_RZSEL_SHIFT 5
+#define MT6325_RG_VCORE1_CC_MASK 0x3
+#define MT6325_RG_VCORE1_CC_SHIFT 8
+#define MT6325_RG_VCORE1_CSR_MASK 0x7
+#define MT6325_RG_VCORE1_CSR_SHIFT 10
+#define MT6325_RG_VCORE1_CSL_MASK 0xF
+#define MT6325_RG_VCORE1_CSL_SHIFT 0
+#define MT6325_RG_VCORE1_SLP_MASK 0x7
+#define MT6325_RG_VCORE1_SLP_SHIFT 4
+#define MT6325_RG_VCORE1_ZX_OS_MASK 0x3
+#define MT6325_RG_VCORE1_ZX_OS_SHIFT 7
+#define MT6325_RG_VCORE1_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VCORE1_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VCORE1_MODESET_MASK 0x1
+#define MT6325_RG_VCORE1_MODESET_SHIFT 15
+#define MT6325_RG_VCORE1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCORE1_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCORE1_CSM_MASK 0x3F
+#define MT6325_RG_VCORE1_CSM_SHIFT 1
+#define MT6325_RG_VCORE1_RSV_MASK 0xFF
+#define MT6325_RG_VCORE1_RSV_SHIFT 7
+#define MT6325_RG_VCORE1_PFM_RIP_MASK 0x7
+#define MT6325_RG_VCORE1_PFM_RIP_SHIFT 0
+#define MT6325_RG_VCORE1_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VCORE1_TRAN_BST_SHIFT 3
+#define MT6325_RG_VCORE1_DTS_ENB_MASK 0x1
+#define MT6325_RG_VCORE1_DTS_ENB_SHIFT 9
+#define MT6325_RG_VCORE1_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VCORE1_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VCORE1_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VCORE1_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VCORE1_C2_RSV_MASK 0x1
+#define MT6325_RG_VCORE1_C2_RSV_SHIFT 0
+#define MT6325_RG_SMPS_TESTMODE_B_MASK 0x1FF
+#define MT6325_RG_SMPS_TESTMODE_B_SHIFT 0
+#define MT6325_RG_VSRAM_DVFS1_TRIMH_MASK 0x1F
+#define MT6325_RG_VSRAM_DVFS1_TRIMH_SHIFT 9
+#define MT6325_RG_VSRAM_DVFS1_TRIML_MASK 0x1F
+#define MT6325_RG_VSRAM_DVFS1_TRIML_SHIFT 0
+#define MT6325_RG_VDVFS11_TRIMH_MASK 0x1F
+#define MT6325_RG_VDVFS11_TRIMH_SHIFT 5
+#define MT6325_RG_VDVFS11_TRIML_MASK 0x1F
+#define MT6325_RG_VDVFS11_TRIML_SHIFT 10
+#define MT6325_RG_VDVFS12_TRIMH_MASK 0x1F
+#define MT6325_RG_VDVFS12_TRIMH_SHIFT 0
+#define MT6325_RG_VDVFS12_TRIML_MASK 0x1F
+#define MT6325_RG_VDVFS12_TRIML_SHIFT 5
+#define MT6325_RG_VGPU_TRIMH_MASK 0x1F
+#define MT6325_RG_VGPU_TRIMH_SHIFT 10
+#define MT6325_RG_VGPU_TRIML_MASK 0x1F
+#define MT6325_RG_VGPU_TRIML_SHIFT 0
+#define MT6325_RG_VCORE1_TRIMH_MASK 0x1F
+#define MT6325_RG_VCORE1_TRIMH_SHIFT 5
+#define MT6325_RG_VCORE1_TRIML_MASK 0x1F
+#define MT6325_RG_VCORE1_TRIML_SHIFT 10
+#define MT6325_RG_VCORE2_TRIMH_MASK 0x1F
+#define MT6325_RG_VCORE2_TRIMH_SHIFT 0
+#define MT6325_RG_VCORE2_TRIML_MASK 0x1F
+#define MT6325_RG_VCORE2_TRIML_SHIFT 5
+#define MT6325_RG_VIO18_TRIMH_MASK 0xF
+#define MT6325_RG_VIO18_TRIMH_SHIFT 10
+#define MT6325_RG_VIO18_TRIML_MASK 0xF
+#define MT6325_RG_VIO18_TRIML_SHIFT 0
+#define MT6325_RG_VPA_TRIMH_MASK 0x1F
+#define MT6325_RG_VPA_TRIMH_SHIFT 4
+#define MT6325_RG_VPA_TRIML_MASK 0x1F
+#define MT6325_RG_VPA_TRIML_SHIFT 9
+#define MT6325_RG_VPA_TRIM_REF_MASK 0x1F
+#define MT6325_RG_VPA_TRIM_REF_SHIFT 0
+#define MT6325_RG_VRF18_0_TRIMH_MASK 0xF
+#define MT6325_RG_VRF18_0_TRIMH_SHIFT 5
+#define MT6325_RG_VRF18_0_TRIML_MASK 0xF
+#define MT6325_RG_VRF18_0_TRIML_SHIFT 9
+#define MT6325_RG_VDRAM_TRIMH_MASK 0xF
+#define MT6325_RG_VDRAM_TRIMH_SHIFT 0
+#define MT6325_RG_VDRAM_TRIML_MASK 0xF
+#define MT6325_RG_VDRAM_TRIML_SHIFT 4
+#define MT6325_RG_VSRAM_DVFS1_VSLEEP_MASK 0x7
+#define MT6325_RG_VSRAM_DVFS1_VSLEEP_SHIFT 8
+#define MT6325_RG_VDVFS11_VSLEEP_MASK 0x7
+#define MT6325_RG_VDVFS11_VSLEEP_SHIFT 11
+#define MT6325_RG_VDVFS12_VSLEEP_MASK 0x7
+#define MT6325_RG_VDVFS12_VSLEEP_SHIFT 0
+#define MT6325_RG_VGPU_VSLEEP_MASK 0x7
+#define MT6325_RG_VGPU_VSLEEP_SHIFT 3
+#define MT6325_RG_VCORE1_VSLEEP_MASK 0x7
+#define MT6325_RG_VCORE1_VSLEEP_SHIFT 6
+#define MT6325_RG_VCORE2_VSLEEP_MASK 0x7
+#define MT6325_RG_VCORE2_VSLEEP_SHIFT 9
+#define MT6325_RG_VPA_BURSTH_MASK 0x3
+#define MT6325_RG_VPA_BURSTH_SHIFT 12
+#define MT6325_RG_VPA_BURSTL_MASK 0x3
+#define MT6325_RG_VPA_BURSTL_SHIFT 14
+#define MT6325_RG_VDRAM_VSLEEP_MASK 0x7
+#define MT6325_RG_VDRAM_VSLEEP_SHIFT 0
+#define MT6325_RG_DMY100MA_EN_MASK 0x1
+#define MT6325_RG_DMY100MA_EN_SHIFT 3
+#define MT6325_RG_DMY100MA_SEL_MASK 0x3
+#define MT6325_RG_DMY100MA_SEL_SHIFT 4
+#define MT6325_RG_VDVFS1_MIN_OFF_MASK 0x3
+#define MT6325_RG_VDVFS1_MIN_OFF_SHIFT 0
+#define MT6325_RG_VDVFS1_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VDVFS1_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VDVFS1_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VDVFS1_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VDVFS1_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VDVFS1_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VDVFS11_RZSEL_MASK 0xF
+#define MT6325_RG_VDVFS11_RZSEL_SHIFT 5
+#define MT6325_RG_VDVFS12_RZSEL_MASK 0xF
+#define MT6325_RG_VDVFS12_RZSEL_SHIFT 9
+#define MT6325_RG_VDVFS11_PFM_RIP_MASK 0x7
+#define MT6325_RG_VDVFS11_PFM_RIP_SHIFT 13
+#define MT6325_RG_VDVFS11_CSR_MASK 0x7
+#define MT6325_RG_VDVFS11_CSR_SHIFT 0
+#define MT6325_RG_VDVFS12_CSR_MASK 0x7
+#define MT6325_RG_VDVFS12_CSR_SHIFT 3
+#define MT6325_RG_VDVFS11_PFM_CSR_MASK 0x7
+#define MT6325_RG_VDVFS11_PFM_CSR_SHIFT 6
+#define MT6325_RG_VDVFS12_PFM_CSR_MASK 0x7
+#define MT6325_RG_VDVFS12_PFM_CSR_SHIFT 9
+#define MT6325_RG_VDVFS11_CSL_MASK 0xF
+#define MT6325_RG_VDVFS11_CSL_SHIFT 12
+#define MT6325_RG_VDVFS12_CSL_MASK 0xF
+#define MT6325_RG_VDVFS12_CSL_SHIFT 0
+#define MT6325_RG_VDVFS11_SLP_MASK 0x7
+#define MT6325_RG_VDVFS11_SLP_SHIFT 4
+#define MT6325_RG_VDVFS12_SLP_MASK 0x7
+#define MT6325_RG_VDVFS12_SLP_SHIFT 7
+#define MT6325_RG_VDVFS11_ZX_OS_MASK 0x3
+#define MT6325_RG_VDVFS11_ZX_OS_SHIFT 10
+#define MT6325_RG_VDVFS12_ZX_OS_MASK 0x3
+#define MT6325_RG_VDVFS12_ZX_OS_SHIFT 12
+#define MT6325_RG_VDVFS11_MODESET_MASK 0x1
+#define MT6325_RG_VDVFS11_MODESET_SHIFT 14
+#define MT6325_RG_VDVFS12_MODESET_MASK 0x1
+#define MT6325_RG_VDVFS12_MODESET_SHIFT 15
+#define MT6325_RG_VDVFS11_NDIS_EN_MASK 0x1
+#define MT6325_RG_VDVFS11_NDIS_EN_SHIFT 0
+#define MT6325_RG_VDVFS12_NDIS_EN_MASK 0x1
+#define MT6325_RG_VDVFS12_NDIS_EN_SHIFT 1
+#define MT6325_RG_VDVFS11_TRANS_BST_MASK 0xFF
+#define MT6325_RG_VDVFS11_TRANS_BST_SHIFT 2
+#define MT6325_RG_VDVFS12_TRANS_BST_MASK 0xFF
+#define MT6325_RG_VDVFS12_TRANS_BST_SHIFT 0
+#define MT6325_RG_VDVFS11_UVP_EN_MASK 0x1
+#define MT6325_RG_VDVFS11_UVP_EN_SHIFT 8
+#define MT6325_RG_VDVFS12_UVP_EN_MASK 0x1
+#define MT6325_RG_VDVFS12_UVP_EN_SHIFT 9
+#define MT6325_RG_VDVFS11_CSM_MASK 0x3F
+#define MT6325_RG_VDVFS11_CSM_SHIFT 10
+#define MT6325_RG_VDVFS12_CSM_MASK 0x3F
+#define MT6325_RG_VDVFS12_CSM_SHIFT 0
+#define MT6325_RG_VDVFS11_PKMODE_MASK 0x1
+#define MT6325_RG_VDVFS11_PKMODE_SHIFT 6
+#define MT6325_RG_VDVFS12_PKMODE_MASK 0x1
+#define MT6325_RG_VDVFS12_PKMODE_SHIFT 7
+#define MT6325_RG_VDVFS11_RSV_MASK 0xFF
+#define MT6325_RG_VDVFS11_RSV_SHIFT 8
+#define MT6325_RG_VDVFS12_RSV_MASK 0xFF
+#define MT6325_RG_VDVFS12_RSV_SHIFT 0
+#define MT6325_RG_VDVFS11_ZXOS_TRIM_MASK 0xFF
+#define MT6325_RG_VDVFS11_ZXOS_TRIM_SHIFT 8
+#define MT6325_RG_VDVFS12_ZXOS_TRIM_MASK 0xFF
+#define MT6325_RG_VDVFS12_ZXOS_TRIM_SHIFT 0
+#define MT6325_RG_VDVFS11_OC_OFF_MASK 0x1
+#define MT6325_RG_VDVFS11_OC_OFF_SHIFT 8
+#define MT6325_RG_VDVFS12_OC_OFF_MASK 0x1
+#define MT6325_RG_VDVFS12_OC_OFF_SHIFT 9
+#define MT6325_RG_VDVFS11_PHS_SHED_TRIM_MASK 0xF
+#define MT6325_RG_VDVFS11_PHS_SHED_TRIM_SHIFT 10
+#define MT6325_RG_VGPU_MIN_OFF_MASK 0x3
+#define MT6325_RG_VGPU_MIN_OFF_SHIFT 0
+#define MT6325_RG_VGPU_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VGPU_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VGPU_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VGPU_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VGPU_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VGPU_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VGPU_RZSEL_MASK 0x7
+#define MT6325_RG_VGPU_RZSEL_SHIFT 5
+#define MT6325_RG_VGPU_CC_MASK 0x3
+#define MT6325_RG_VGPU_CC_SHIFT 8
+#define MT6325_RG_VGPU_CSR_MASK 0x7
+#define MT6325_RG_VGPU_CSR_SHIFT 10
+#define MT6325_RG_VGPU_CSL_MASK 0xF
+#define MT6325_RG_VGPU_CSL_SHIFT 0
+#define MT6325_RG_VGPU_SLP_MASK 0x7
+#define MT6325_RG_VGPU_SLP_SHIFT 4
+#define MT6325_RG_VGPU_ZX_OS_MASK 0x3
+#define MT6325_RG_VGPU_ZX_OS_SHIFT 7
+#define MT6325_RG_VGPU_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VGPU_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VGPU_MODESET_MASK 0x1
+#define MT6325_RG_VGPU_MODESET_SHIFT 15
+#define MT6325_RG_VGPU_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGPU_NDIS_EN_SHIFT 0
+#define MT6325_RG_VGPU_CSM_MASK 0x3F
+#define MT6325_RG_VGPU_CSM_SHIFT 1
+#define MT6325_RG_VGPU_RSV_MASK 0xFF
+#define MT6325_RG_VGPU_RSV_SHIFT 7
+#define MT6325_RG_VGPU_PFM_RIP_MASK 0x7
+#define MT6325_RG_VGPU_PFM_RIP_SHIFT 0
+#define MT6325_RG_VGPU_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VGPU_TRAN_BST_SHIFT 3
+#define MT6325_RG_VGPU_DTS_ENB_MASK 0x1
+#define MT6325_RG_VGPU_DTS_ENB_SHIFT 9
+#define MT6325_RG_VGPU_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VGPU_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VGPU_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VGPU_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VGPU_C2_RSV_MASK 0x1
+#define MT6325_RG_VGPU_C2_RSV_SHIFT 0
+#define MT6325_RG_VPA_RZSEL_MASK 0x3
+#define MT6325_RG_VPA_RZSEL_SHIFT 0
+#define MT6325_RG_VPA_CC_MASK 0x3
+#define MT6325_RG_VPA_CC_SHIFT 2
+#define MT6325_RG_VPA_CSR_MASK 0x3
+#define MT6325_RG_VPA_CSR_SHIFT 4
+#define MT6325_RG_VPA_CSMIR_MASK 0x3
+#define MT6325_RG_VPA_CSMIR_SHIFT 6
+#define MT6325_RG_VPA_CSL_MASK 0x3
+#define MT6325_RG_VPA_CSL_SHIFT 8
+#define MT6325_RG_VPA_SLP_MASK 0x3
+#define MT6325_RG_VPA_SLP_SHIFT 10
+#define MT6325_RG_VPA_ZX_OS_TRIM_MASK 0x3F
+#define MT6325_RG_VPA_ZX_OS_TRIM_SHIFT 0
+#define MT6325_RG_VPA_ZX_OS_MASK 0x3
+#define MT6325_RG_VPA_ZX_OS_SHIFT 6
+#define MT6325_RG_VPA_HZP_MASK 0x1
+#define MT6325_RG_VPA_HZP_SHIFT 8
+#define MT6325_RG_VPA_BWEX_GAT_MASK 0x1
+#define MT6325_RG_VPA_BWEX_GAT_SHIFT 9
+#define MT6325_RG_VPA_MODESET_MASK 0x1
+#define MT6325_RG_VPA_MODESET_SHIFT 10
+#define MT6325_RG_VPA_SLEW_MASK 0x3
+#define MT6325_RG_VPA_SLEW_SHIFT 11
+#define MT6325_RG_VPA_SLEW_NMOS_MASK 0x3
+#define MT6325_RG_VPA_SLEW_NMOS_SHIFT 13
+#define MT6325_RG_VPA_NDIS_EN_MASK 0x1
+#define MT6325_RG_VPA_NDIS_EN_SHIFT 15
+#define MT6325_RG_VPA_MIN_ON_MASK 0x3
+#define MT6325_RG_VPA_MIN_ON_SHIFT 0
+#define MT6325_RG_VPA_VBAT_DEL_MASK 0x3
+#define MT6325_RG_VPA_VBAT_DEL_SHIFT 2
+#define MT6325_RG_VPA_EN_MASK 0x1
+#define MT6325_RG_VPA_EN_SHIFT 4
+#define MT6325_RG_VPA_RSV1_MASK 0xFF
+#define MT6325_RG_VPA_RSV1_SHIFT 5
+#define MT6325_RG_VPA_RSV2_MASK 0xFF
+#define MT6325_RG_VPA_RSV2_SHIFT 0
+#define MT6325_RG_VCORE2_MIN_OFF_MASK 0x3
+#define MT6325_RG_VCORE2_MIN_OFF_SHIFT 0
+#define MT6325_RG_VCORE2_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VCORE2_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VCORE2_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VCORE2_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VCORE2_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VCORE2_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VCORE2_RZSEL_MASK 0x7
+#define MT6325_RG_VCORE2_RZSEL_SHIFT 5
+#define MT6325_RG_VCORE2_CC_MASK 0x3
+#define MT6325_RG_VCORE2_CC_SHIFT 8
+#define MT6325_RG_VCORE2_CSR_MASK 0x7
+#define MT6325_RG_VCORE2_CSR_SHIFT 10
+#define MT6325_RG_VCORE2_CSL_MASK 0xF
+#define MT6325_RG_VCORE2_CSL_SHIFT 0
+#define MT6325_RG_VCORE2_SLP_MASK 0x7
+#define MT6325_RG_VCORE2_SLP_SHIFT 4
+#define MT6325_RG_VCORE2_ZX_OS_MASK 0x3
+#define MT6325_RG_VCORE2_ZX_OS_SHIFT 7
+#define MT6325_RG_VCORE2_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VCORE2_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VCORE2_MODESET_MASK 0x1
+#define MT6325_RG_VCORE2_MODESET_SHIFT 15
+#define MT6325_RG_VCORE2_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCORE2_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCORE2_CSM_MASK 0x3F
+#define MT6325_RG_VCORE2_CSM_SHIFT 1
+#define MT6325_RG_VCORE2_RSV_MASK 0xFF
+#define MT6325_RG_VCORE2_RSV_SHIFT 7
+#define MT6325_RG_VCORE2_PFM_RIP_MASK 0x7
+#define MT6325_RG_VCORE2_PFM_RIP_SHIFT 0
+#define MT6325_RG_VCORE2_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VCORE2_TRAN_BST_SHIFT 3
+#define MT6325_RG_VCORE2_DTS_ENB_MASK 0x1
+#define MT6325_RG_VCORE2_DTS_ENB_SHIFT 9
+#define MT6325_RG_VCORE2_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VCORE2_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VCORE2_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VCORE2_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VCORE2_C2_RSV_MASK 0x1
+#define MT6325_RG_VCORE2_C2_RSV_SHIFT 0
+#define MT6325_RG_VIO18_MIN_OFF_MASK 0x3
+#define MT6325_RG_VIO18_MIN_OFF_SHIFT 0
+#define MT6325_RG_VIO18_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VIO18_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VIO18_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VIO18_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VIO18_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VIO18_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VIO18_RZSEL_MASK 0x7
+#define MT6325_RG_VIO18_RZSEL_SHIFT 5
+#define MT6325_RG_VIO18_CC_MASK 0x3
+#define MT6325_RG_VIO18_CC_SHIFT 8
+#define MT6325_RG_VIO18_CSR_MASK 0x7
+#define MT6325_RG_VIO18_CSR_SHIFT 10
+#define MT6325_RG_VIO18_CSL_MASK 0xF
+#define MT6325_RG_VIO18_CSL_SHIFT 0
+#define MT6325_RG_VIO18_SLP_MASK 0x7
+#define MT6325_RG_VIO18_SLP_SHIFT 4
+#define MT6325_RG_VIO18_ZX_OS_MASK 0x3
+#define MT6325_RG_VIO18_ZX_OS_SHIFT 7
+#define MT6325_RG_VIO18_MODESET_MASK 0x1
+#define MT6325_RG_VIO18_MODESET_SHIFT 9
+#define MT6325_RG_VIO18_NDIS_EN_MASK 0x1
+#define MT6325_RG_VIO18_NDIS_EN_SHIFT 10
+#define MT6325_RG_VIO18_CSM_MASK 0x3F
+#define MT6325_RG_VIO18_CSM_SHIFT 0
+#define MT6325_RG_VIO18_RSV_MASK 0xFF
+#define MT6325_RG_VIO18_RSV_SHIFT 6
+#define MT6325_RG_VIO18_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VIO18_ZXOS_TRIM_SHIFT 0
+#define MT6325_RG_VIO18_PFM_RIP_MASK 0x7
+#define MT6325_RG_VIO18_PFM_RIP_SHIFT 6
+#define MT6325_RG_VIO18_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VIO18_TRAN_BST_SHIFT 9
+#define MT6325_RG_VIO18_DTS_ENB_MASK 0x1
+#define MT6325_RG_VIO18_DTS_ENB_SHIFT 15
+#define MT6325_RG_VIO18_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VIO18_RCL_TRIM_SHIFT 0
+#define MT6325_RG_VIO18_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VIO18_RCL_TRIM_EN_SHIFT 5
+#define MT6325_RG_VIO18_C2_RSV_MASK 0x1
+#define MT6325_RG_VIO18_C2_RSV_SHIFT 6
+#define MT6325_RG_VRF1_MIN_OFF_MASK 0x3
+#define MT6325_RG_VRF1_MIN_OFF_SHIFT 0
+#define MT6325_RG_VRF18_0_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VRF18_0_SSTART_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_SSTART_EN_SHIFT 3
+#define MT6325_RG_VRF18_0_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VRF18_0_RZSEL_MASK 0x7
+#define MT6325_RG_VRF18_0_RZSEL_SHIFT 5
+#define MT6325_RG_VRF18_0_CC_MASK 0x3
+#define MT6325_RG_VRF18_0_CC_SHIFT 8
+#define MT6325_RG_VRF18_0_CSR_MASK 0x7
+#define MT6325_RG_VRF18_0_CSR_SHIFT 10
+#define MT6325_RG_VRF18_0_CSL_MASK 0xF
+#define MT6325_RG_VRF18_0_CSL_SHIFT 0
+#define MT6325_RG_VRF18_0_SLP_MASK 0x7
+#define MT6325_RG_VRF18_0_SLP_SHIFT 4
+#define MT6325_RG_VRF18_0_ZX_OS_MASK 0x3
+#define MT6325_RG_VRF18_0_ZX_OS_SHIFT 7
+#define MT6325_RG_VRF18_0_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VRF18_0_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VRF18_0_MODESET_MASK 0x1
+#define MT6325_RG_VRF18_0_MODESET_SHIFT 15
+#define MT6325_RG_VRF18_0_NDIS_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_NDIS_EN_SHIFT 0
+#define MT6325_RG_VRF18_0_CSM_MASK 0x3F
+#define MT6325_RG_VRF18_0_CSM_SHIFT 1
+#define MT6325_RG_VRF18_0_RSV_MASK 0xFF
+#define MT6325_RG_VRF18_0_RSV_SHIFT 7
+#define MT6325_RG_VRF18_0_PFM_RIP_MASK 0x7
+#define MT6325_RG_VRF18_0_PFM_RIP_SHIFT 0
+#define MT6325_RG_VRF18_0_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VRF18_0_TRAN_BST_SHIFT 3
+#define MT6325_RG_VRF18_0_DTS_ENB_MASK 0x1
+#define MT6325_RG_VRF18_0_DTS_ENB_SHIFT 9
+#define MT6325_RG_VRF18_0_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VRF18_0_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VRF18_0_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VRF18_0_C2_RSV_MASK 0x1
+#define MT6325_RG_VRF18_0_C2_RSV_SHIFT 0
+#define MT6325_VDVFS11_DIG0_RSV0_MASK 0xFF
+#define MT6325_VDVFS11_DIG0_RSV0_SHIFT 8
+#define MT6325_VDVFS11_EN_CTRL_MASK 0x1
+#define MT6325_VDVFS11_EN_CTRL_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_CTRL_MASK 0x1
+#define MT6325_VDVFS11_VOSEL_CTRL_SHIFT 1
+#define MT6325_VDVFS11_DIG0_RSV1_MASK 0x1
+#define MT6325_VDVFS11_DIG0_RSV1_SHIFT 2
+#define MT6325_VDVFS11_DIG1_RSV1_MASK 0x1
+#define MT6325_VDVFS11_DIG1_RSV1_SHIFT 3
+#define MT6325_VDVFS11_EN_SEL_MASK 0x3
+#define MT6325_VDVFS11_EN_SEL_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_SEL_MASK 0x3
+#define MT6325_VDVFS11_VOSEL_SEL_SHIFT 4
+#define MT6325_VDVFS11_DIG0_RSV2_MASK 0x3
+#define MT6325_VDVFS11_DIG0_RSV2_SHIFT 8
+#define MT6325_VDVFS11_DIG1_RSV2_MASK 0x3
+#define MT6325_VDVFS11_DIG1_RSV2_SHIFT 12
+#define MT6325_VDVFS11_EN_MASK 0x1
+#define MT6325_VDVFS11_EN_SHIFT 0
+#define MT6325_VDVFS11_STBTD_MASK 0x3
+#define MT6325_VDVFS11_STBTD_SHIFT 4
+#define MT6325_QI_VDVFS11_STB_MASK 0x1
+#define MT6325_QI_VDVFS11_STB_SHIFT 12
+#define MT6325_QI_VDVFS11_EN_MASK 0x1
+#define MT6325_QI_VDVFS11_EN_SHIFT 13
+#define MT6325_QI_VDVFS11_OC_STATUS_MASK 0x1
+#define MT6325_QI_VDVFS11_OC_STATUS_SHIFT 15
+#define MT6325_VDVFS11_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VDVFS11_SFCHG_FRATE_SHIFT 0
+#define MT6325_VDVFS11_SFCHG_FEN_MASK 0x1
+#define MT6325_VDVFS11_SFCHG_FEN_SHIFT 7
+#define MT6325_VDVFS11_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VDVFS11_SFCHG_RRATE_SHIFT 8
+#define MT6325_VDVFS11_SFCHG_REN_MASK 0x1
+#define MT6325_VDVFS11_SFCHG_REN_SHIFT 15
+#define MT6325_VDVFS11_VOSEL_MASK 0x7F
+#define MT6325_VDVFS11_VOSEL_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_ON_MASK 0x7F
+#define MT6325_VDVFS11_VOSEL_ON_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VDVFS11_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VDVFS11_VOSEL_MASK 0x7F
+#define MT6325_NI_VDVFS11_VOSEL_SHIFT 0
+#define MT6325_VDVFS11_TRANS_TD_MASK 0x3
+#define MT6325_VDVFS11_TRANS_TD_SHIFT 0
+#define MT6325_VDVFS11_TRANS_CTRL_MASK 0x3
+#define MT6325_VDVFS11_TRANS_CTRL_SHIFT 4
+#define MT6325_VDVFS11_TRANS_ONCE_MASK 0x1
+#define MT6325_VDVFS11_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VDVFS11_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VDVFS11_VOSEL_TRANS_SHIFT 7
+#define MT6325_VDVFS11_VSLEEP_EN_MASK 0x1
+#define MT6325_VDVFS11_VSLEEP_EN_SHIFT 8
+#define MT6325_VDVFS11_R2R_PDN_MASK 0x1
+#define MT6325_VDVFS11_R2R_PDN_SHIFT 10
+#define MT6325_VDVFS11_VSLEEP_SEL_MASK 0x1
+#define MT6325_VDVFS11_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VDVFS11_R2R_PDN_MASK 0x1
+#define MT6325_NI_VDVFS11_R2R_PDN_SHIFT 14
+#define MT6325_NI_VDVFS11_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VDVFS11_VSLEEP_SEL_SHIFT 15
+#define MT6325_VDVFS12_DIG0_RSV0_MASK 0xFF
+#define MT6325_VDVFS12_DIG0_RSV0_SHIFT 8
+#define MT6325_VDVFS12_EN_CTRL_MASK 0x1
+#define MT6325_VDVFS12_EN_CTRL_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_CTRL_MASK 0x1
+#define MT6325_VDVFS12_VOSEL_CTRL_SHIFT 1
+#define MT6325_VDVFS12_DIG0_RSV1_MASK 0x1
+#define MT6325_VDVFS12_DIG0_RSV1_SHIFT 2
+#define MT6325_VDVFS12_DIG1_RSV1_MASK 0x1
+#define MT6325_VDVFS12_DIG1_RSV1_SHIFT 3
+#define MT6325_VDVFS12_EN_SEL_MASK 0x3
+#define MT6325_VDVFS12_EN_SEL_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_SEL_MASK 0x3
+#define MT6325_VDVFS12_VOSEL_SEL_SHIFT 4
+#define MT6325_VDVFS12_DIG0_RSV2_MASK 0x3
+#define MT6325_VDVFS12_DIG0_RSV2_SHIFT 8
+#define MT6325_VDVFS12_DIG1_RSV2_MASK 0x3
+#define MT6325_VDVFS12_DIG1_RSV2_SHIFT 12
+#define MT6325_VDVFS12_EN_MASK 0x1
+#define MT6325_VDVFS12_EN_SHIFT 0
+#define MT6325_VDVFS12_STBTD_MASK 0x3
+#define MT6325_VDVFS12_STBTD_SHIFT 4
+#define MT6325_QI_VDVFS12_STB_MASK 0x1
+#define MT6325_QI_VDVFS12_STB_SHIFT 12
+#define MT6325_QI_VDVFS12_EN_MASK 0x1
+#define MT6325_QI_VDVFS12_EN_SHIFT 13
+#define MT6325_QI_VDVFS12_OC_STATUS_MASK 0x1
+#define MT6325_QI_VDVFS12_OC_STATUS_SHIFT 15
+#define MT6325_VDVFS12_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VDVFS12_SFCHG_FRATE_SHIFT 0
+#define MT6325_VDVFS12_SFCHG_FEN_MASK 0x1
+#define MT6325_VDVFS12_SFCHG_FEN_SHIFT 7
+#define MT6325_VDVFS12_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VDVFS12_SFCHG_RRATE_SHIFT 8
+#define MT6325_VDVFS12_SFCHG_REN_MASK 0x1
+#define MT6325_VDVFS12_SFCHG_REN_SHIFT 15
+#define MT6325_VDVFS12_VOSEL_MASK 0x7F
+#define MT6325_VDVFS12_VOSEL_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_ON_MASK 0x7F
+#define MT6325_VDVFS12_VOSEL_ON_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VDVFS12_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VDVFS12_VOSEL_MASK 0x7F
+#define MT6325_NI_VDVFS12_VOSEL_SHIFT 0
+#define MT6325_VDVFS12_TRANS_TD_MASK 0x3
+#define MT6325_VDVFS12_TRANS_TD_SHIFT 0
+#define MT6325_VDVFS12_TRANS_CTRL_MASK 0x3
+#define MT6325_VDVFS12_TRANS_CTRL_SHIFT 4
+#define MT6325_VDVFS12_TRANS_ONCE_MASK 0x1
+#define MT6325_VDVFS12_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VDVFS12_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VDVFS12_VOSEL_TRANS_SHIFT 7
+#define MT6325_VDVFS12_VSLEEP_EN_MASK 0x1
+#define MT6325_VDVFS12_VSLEEP_EN_SHIFT 8
+#define MT6325_VDVFS12_R2R_PDN_MASK 0x1
+#define MT6325_VDVFS12_R2R_PDN_SHIFT 10
+#define MT6325_VDVFS12_VSLEEP_SEL_MASK 0x1
+#define MT6325_VDVFS12_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VDVFS12_R2R_PDN_MASK 0x1
+#define MT6325_NI_VDVFS12_R2R_PDN_SHIFT 14
+#define MT6325_NI_VDVFS12_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VDVFS12_VSLEEP_SEL_SHIFT 15
+#define MT6325_VSRAM_DVFS1_DIG0_RSV0_MASK 0xFF
+#define MT6325_VSRAM_DVFS1_DIG0_RSV0_SHIFT 8
+#define MT6325_VSRAM_DVFS1_EN_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_EN_CTRL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_VOSEL_CTRL_SHIFT 1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV1_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV1_SHIFT 2
+#define MT6325_VSRAM_DVFS1_DIG1_RSV1_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG1_RSV1_SHIFT 3
+#define MT6325_VSRAM_DVFS1_EN_SEL_MASK 0x3
+#define MT6325_VSRAM_DVFS1_EN_SEL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_SEL_MASK 0x3
+#define MT6325_VSRAM_DVFS1_VOSEL_SEL_SHIFT 4
+#define MT6325_VSRAM_DVFS1_DIG0_RSV2_MASK 0x3
+#define MT6325_VSRAM_DVFS1_DIG0_RSV2_SHIFT 8
+#define MT6325_VSRAM_DVFS1_DIG1_RSV2_MASK 0x3
+#define MT6325_VSRAM_DVFS1_DIG1_RSV2_SHIFT 12
+#define MT6325_VSRAM_DVFS1_EN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_EN_SHIFT 0
+#define MT6325_VSRAM_DVFS1_STBTD_MASK 0x3
+#define MT6325_VSRAM_DVFS1_STBTD_SHIFT 4
+#define MT6325_VSRAM_DVFS1_DIG0_RSV4_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV4_SHIFT 12
+#define MT6325_VSRAM_DVFS1_DIG0_RSV3_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV3_SHIFT 13
+#define MT6325_QI_VSRAM_DVFS1_OC_STATUS_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_OC_STATUS_SHIFT 15
+#define MT6325_VSRAM_DVFS1_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_SFCHG_FRATE_SHIFT 0
+#define MT6325_VSRAM_DVFS1_SFCHG_FEN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_SFCHG_FEN_SHIFT 7
+#define MT6325_VSRAM_DVFS1_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_SFCHG_RRATE_SHIFT 8
+#define MT6325_VSRAM_DVFS1_SFCHG_REN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_SFCHG_REN_SHIFT 15
+#define MT6325_VSRAM_DVFS1_VOSEL_RSV_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_RSV_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_MASK 0x7F
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_TRANS_TD_MASK 0x3
+#define MT6325_VSRAM_DVFS1_TRANS_TD_SHIFT 0
+#define MT6325_VSRAM_DVFS1_TRANS_CTRL_MASK 0x3
+#define MT6325_VSRAM_DVFS1_TRANS_CTRL_SHIFT 4
+#define MT6325_VSRAM_DVFS1_TRANS_ONCE_MASK 0x1
+#define MT6325_VSRAM_DVFS1_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_TRANS_SHIFT 7
+#define MT6325_VSRAM_DVFS1_VSLEEP_EN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_VSLEEP_EN_SHIFT 8
+#define MT6325_VSRAM_DVFS1_R2R_PDN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_R2R_PDN_SHIFT 10
+#define MT6325_VSRAM_DVFS1_VSLEEP_SEL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VSRAM_DVFS1_R2R_PDN_MASK 0x1
+#define MT6325_NI_VSRAM_DVFS1_R2R_PDN_SHIFT 14
+#define MT6325_NI_VSRAM_DVFS1_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VSRAM_DVFS1_VSLEEP_SEL_SHIFT 15
+#define MT6325_VDRAM_DIG0_RSV0_MASK 0xFF
+#define MT6325_VDRAM_DIG0_RSV0_SHIFT 8
+#define MT6325_VDRAM_EN_CTRL_MASK 0x1
+#define MT6325_VDRAM_EN_CTRL_SHIFT 0
+#define MT6325_VDRAM_VOSEL_CTRL_MASK 0x1
+#define MT6325_VDRAM_VOSEL_CTRL_SHIFT 1
+#define MT6325_VDRAM_DIG0_RSV1_MASK 0x1
+#define MT6325_VDRAM_DIG0_RSV1_SHIFT 2
+#define MT6325_VDRAM_BURST_CTRL_MASK 0x1
+#define MT6325_VDRAM_BURST_CTRL_SHIFT 3
+#define MT6325_VDRAM_EN_SEL_MASK 0x3
+#define MT6325_VDRAM_EN_SEL_SHIFT 0
+#define MT6325_VDRAM_VOSEL_SEL_MASK 0x3
+#define MT6325_VDRAM_VOSEL_SEL_SHIFT 4
+#define MT6325_VDRAM_DIG0_RSV2_MASK 0x3
+#define MT6325_VDRAM_DIG0_RSV2_SHIFT 8
+#define MT6325_VDRAM_BURST_SEL_MASK 0x3
+#define MT6325_VDRAM_BURST_SEL_SHIFT 12
+#define MT6325_VDRAM_EN_MASK 0x1
+#define MT6325_VDRAM_EN_SHIFT 0
+#define MT6325_VDRAM_STBTD_MASK 0x3
+#define MT6325_VDRAM_STBTD_SHIFT 4
+#define MT6325_QI_VDRAM_STB_MASK 0x1
+#define MT6325_QI_VDRAM_STB_SHIFT 12
+#define MT6325_QI_VDRAM_EN_MASK 0x1
+#define MT6325_QI_VDRAM_EN_SHIFT 13
+#define MT6325_QI_VDRAM_OC_STATUS_MASK 0x1
+#define MT6325_QI_VDRAM_OC_STATUS_SHIFT 15
+#define MT6325_VDRAM_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VDRAM_SFCHG_FRATE_SHIFT 0
+#define MT6325_VDRAM_SFCHG_FEN_MASK 0x1
+#define MT6325_VDRAM_SFCHG_FEN_SHIFT 7
+#define MT6325_VDRAM_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VDRAM_SFCHG_RRATE_SHIFT 8
+#define MT6325_VDRAM_SFCHG_REN_MASK 0x1
+#define MT6325_VDRAM_SFCHG_REN_SHIFT 15
+#define MT6325_VDRAM_VOSEL_MASK 0x7F
+#define MT6325_VDRAM_VOSEL_SHIFT 0
+#define MT6325_VDRAM_VOSEL_ON_MASK 0x7F
+#define MT6325_VDRAM_VOSEL_ON_SHIFT 0
+#define MT6325_VDRAM_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VDRAM_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VDRAM_VOSEL_MASK 0x7F
+#define MT6325_NI_VDRAM_VOSEL_SHIFT 0
+#define MT6325_VDRAM_BURST_MASK 0x7
+#define MT6325_VDRAM_BURST_SHIFT 0
+#define MT6325_VDRAM_BURST_ON_MASK 0x7
+#define MT6325_VDRAM_BURST_ON_SHIFT 4
+#define MT6325_VDRAM_BURST_SLEEP_MASK 0x7
+#define MT6325_VDRAM_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VDRAM_BURST_MASK 0x7
+#define MT6325_QI_VDRAM_BURST_SHIFT 12
+#define MT6325_VDRAM_TRANS_TD_MASK 0x3
+#define MT6325_VDRAM_TRANS_TD_SHIFT 0
+#define MT6325_VDRAM_TRANS_CTRL_MASK 0x3
+#define MT6325_VDRAM_TRANS_CTRL_SHIFT 4
+#define MT6325_VDRAM_TRANS_ONCE_MASK 0x1
+#define MT6325_VDRAM_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VDRAM_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VDRAM_VOSEL_TRANS_SHIFT 7
+#define MT6325_VDRAM_VSLEEP_EN_MASK 0x1
+#define MT6325_VDRAM_VSLEEP_EN_SHIFT 8
+#define MT6325_VDRAM_R2R_PDN_MASK 0x1
+#define MT6325_VDRAM_R2R_PDN_SHIFT 10
+#define MT6325_VDRAM_VSLEEP_SEL_MASK 0x1
+#define MT6325_VDRAM_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VDRAM_R2R_PDN_MASK 0x1
+#define MT6325_NI_VDRAM_R2R_PDN_SHIFT 14
+#define MT6325_NI_VDRAM_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VDRAM_VSLEEP_SEL_SHIFT 15
+#define MT6325_VRF18_0_DIG0_RSV0_MASK 0xFF
+#define MT6325_VRF18_0_DIG0_RSV0_SHIFT 8
+#define MT6325_VRF18_0_EN_CTRL_MASK 0x1
+#define MT6325_VRF18_0_EN_CTRL_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_CTRL_MASK 0x1
+#define MT6325_VRF18_0_VOSEL_CTRL_SHIFT 1
+#define MT6325_VRF18_0_DIG0_RSV1_MASK 0x1
+#define MT6325_VRF18_0_DIG0_RSV1_SHIFT 2
+#define MT6325_VRF18_0_BURST_CTRL_MASK 0x1
+#define MT6325_VRF18_0_BURST_CTRL_SHIFT 3
+#define MT6325_VRF18_0_EN_SEL_MASK 0x3
+#define MT6325_VRF18_0_EN_SEL_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_SEL_MASK 0x3
+#define MT6325_VRF18_0_VOSEL_SEL_SHIFT 4
+#define MT6325_VRF18_0_DIG0_RSV2_MASK 0x3
+#define MT6325_VRF18_0_DIG0_RSV2_SHIFT 8
+#define MT6325_VRF18_0_BURST_SEL_MASK 0x3
+#define MT6325_VRF18_0_BURST_SEL_SHIFT 12
+#define MT6325_VRF18_0_EN_MASK 0x1
+#define MT6325_VRF18_0_EN_SHIFT 0
+#define MT6325_VRF18_0_STBTD_MASK 0x3
+#define MT6325_VRF18_0_STBTD_SHIFT 4
+#define MT6325_QI_VRF18_0_STB_MASK 0x1
+#define MT6325_QI_VRF18_0_STB_SHIFT 12
+#define MT6325_QI_VRF18_0_EN_MASK 0x1
+#define MT6325_QI_VRF18_0_EN_SHIFT 13
+#define MT6325_QI_VRF18_0_OC_STATUS_MASK 0x1
+#define MT6325_QI_VRF18_0_OC_STATUS_SHIFT 15
+#define MT6325_VRF18_0_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VRF18_0_SFCHG_FRATE_SHIFT 0
+#define MT6325_VRF18_0_SFCHG_FEN_MASK 0x1
+#define MT6325_VRF18_0_SFCHG_FEN_SHIFT 7
+#define MT6325_VRF18_0_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VRF18_0_SFCHG_RRATE_SHIFT 8
+#define MT6325_VRF18_0_SFCHG_REN_MASK 0x1
+#define MT6325_VRF18_0_SFCHG_REN_SHIFT 15
+#define MT6325_VRF18_0_VOSEL_MASK 0x7F
+#define MT6325_VRF18_0_VOSEL_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_ON_MASK 0x7F
+#define MT6325_VRF18_0_VOSEL_ON_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VRF18_0_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VRF18_0_VOSEL_MASK 0x7F
+#define MT6325_NI_VRF18_0_VOSEL_SHIFT 0
+#define MT6325_VRF18_0_BURST_MASK 0x7
+#define MT6325_VRF18_0_BURST_SHIFT 0
+#define MT6325_VRF18_0_BURST_ON_MASK 0x7
+#define MT6325_VRF18_0_BURST_ON_SHIFT 4
+#define MT6325_VRF18_0_BURST_SLEEP_MASK 0x7
+#define MT6325_VRF18_0_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VRF18_0_BURST_MASK 0x7
+#define MT6325_QI_VRF18_0_BURST_SHIFT 12
+#define MT6325_VRF18_0_TRANS_TD_MASK 0x3
+#define MT6325_VRF18_0_TRANS_TD_SHIFT 0
+#define MT6325_VRF18_0_TRANS_CTRL_MASK 0x3
+#define MT6325_VRF18_0_TRANS_CTRL_SHIFT 4
+#define MT6325_VRF18_0_TRANS_ONCE_MASK 0x1
+#define MT6325_VRF18_0_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VRF18_0_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VRF18_0_VOSEL_TRANS_SHIFT 7
+#define MT6325_VRF18_0_VSLEEP_EN_MASK 0x1
+#define MT6325_VRF18_0_VSLEEP_EN_SHIFT 8
+#define MT6325_VRF18_0_R2R_PDN_MASK 0x1
+#define MT6325_VRF18_0_R2R_PDN_SHIFT 10
+#define MT6325_VRF18_0_VSLEEP_SEL_MASK 0x1
+#define MT6325_VRF18_0_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VRF18_0_R2R_PDN_MASK 0x1
+#define MT6325_NI_VRF18_0_R2R_PDN_SHIFT 14
+#define MT6325_NI_VRF18_0_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VRF18_0_VSLEEP_SEL_SHIFT 15
+#define MT6325_VGPU_DIG0_RSV0_MASK 0xFF
+#define MT6325_VGPU_DIG0_RSV0_SHIFT 8
+#define MT6325_VGPU_EN_CTRL_MASK 0x1
+#define MT6325_VGPU_EN_CTRL_SHIFT 0
+#define MT6325_VGPU_VOSEL_CTRL_MASK 0x1
+#define MT6325_VGPU_VOSEL_CTRL_SHIFT 1
+#define MT6325_VGPU_DLC_CTRL_MASK 0x1
+#define MT6325_VGPU_DLC_CTRL_SHIFT 2
+#define MT6325_VGPU_BURST_CTRL_MASK 0x1
+#define MT6325_VGPU_BURST_CTRL_SHIFT 3
+#define MT6325_VGPU_EN_SEL_MASK 0x3
+#define MT6325_VGPU_EN_SEL_SHIFT 0
+#define MT6325_VGPU_VOSEL_SEL_MASK 0x3
+#define MT6325_VGPU_VOSEL_SEL_SHIFT 4
+#define MT6325_VGPU_DLC_SEL_MASK 0x3
+#define MT6325_VGPU_DLC_SEL_SHIFT 8
+#define MT6325_VGPU_BURST_SEL_MASK 0x3
+#define MT6325_VGPU_BURST_SEL_SHIFT 12
+#define MT6325_VGPU_EN_MASK 0x1
+#define MT6325_VGPU_EN_SHIFT 0
+#define MT6325_VGPU_STBTD_MASK 0x3
+#define MT6325_VGPU_STBTD_SHIFT 4
+#define MT6325_QI_VGPU_STB_MASK 0x1
+#define MT6325_QI_VGPU_STB_SHIFT 12
+#define MT6325_QI_VGPU_EN_MASK 0x1
+#define MT6325_QI_VGPU_EN_SHIFT 13
+#define MT6325_QI_VGPU_OC_STATUS_MASK 0x1
+#define MT6325_QI_VGPU_OC_STATUS_SHIFT 15
+#define MT6325_VGPU_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VGPU_SFCHG_FRATE_SHIFT 0
+#define MT6325_VGPU_SFCHG_FEN_MASK 0x1
+#define MT6325_VGPU_SFCHG_FEN_SHIFT 7
+#define MT6325_VGPU_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VGPU_SFCHG_RRATE_SHIFT 8
+#define MT6325_VGPU_SFCHG_REN_MASK 0x1
+#define MT6325_VGPU_SFCHG_REN_SHIFT 15
+#define MT6325_VGPU_VOSEL_MASK 0x7F
+#define MT6325_VGPU_VOSEL_SHIFT 0
+#define MT6325_VGPU_VOSEL_ON_MASK 0x7F
+#define MT6325_VGPU_VOSEL_ON_SHIFT 0
+#define MT6325_VGPU_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VGPU_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VGPU_VOSEL_MASK 0x7F
+#define MT6325_NI_VGPU_VOSEL_SHIFT 0
+#define MT6325_VGPU_BURST_MASK 0x7
+#define MT6325_VGPU_BURST_SHIFT 0
+#define MT6325_VGPU_BURST_ON_MASK 0x7
+#define MT6325_VGPU_BURST_ON_SHIFT 4
+#define MT6325_VGPU_BURST_SLEEP_MASK 0x7
+#define MT6325_VGPU_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VGPU_BURST_MASK 0x7
+#define MT6325_QI_VGPU_BURST_SHIFT 12
+#define MT6325_VGPU_DLC_MASK 0x3
+#define MT6325_VGPU_DLC_SHIFT 0
+#define MT6325_VGPU_DLC_ON_MASK 0x3
+#define MT6325_VGPU_DLC_ON_SHIFT 4
+#define MT6325_VGPU_DLC_SLEEP_MASK 0x3
+#define MT6325_VGPU_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VGPU_DLC_MASK 0x3
+#define MT6325_QI_VGPU_DLC_SHIFT 12
+#define MT6325_VGPU_DLC_N_MASK 0x3
+#define MT6325_VGPU_DLC_N_SHIFT 0
+#define MT6325_VGPU_DLC_N_ON_MASK 0x3
+#define MT6325_VGPU_DLC_N_ON_SHIFT 4
+#define MT6325_VGPU_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VGPU_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VGPU_DLC_N_MASK 0x3
+#define MT6325_QI_VGPU_DLC_N_SHIFT 12
+#define MT6325_VGPU_TRANS_TD_MASK 0x3
+#define MT6325_VGPU_TRANS_TD_SHIFT 0
+#define MT6325_VGPU_TRANS_CTRL_MASK 0x3
+#define MT6325_VGPU_TRANS_CTRL_SHIFT 4
+#define MT6325_VGPU_TRANS_ONCE_MASK 0x1
+#define MT6325_VGPU_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VGPU_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VGPU_VOSEL_TRANS_SHIFT 7
+#define MT6325_VGPU_VSLEEP_EN_MASK 0x1
+#define MT6325_VGPU_VSLEEP_EN_SHIFT 8
+#define MT6325_VGPU_R2R_PDN_MASK 0x1
+#define MT6325_VGPU_R2R_PDN_SHIFT 10
+#define MT6325_VGPU_VSLEEP_SEL_MASK 0x1
+#define MT6325_VGPU_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VGPU_R2R_PDN_MASK 0x1
+#define MT6325_NI_VGPU_R2R_PDN_SHIFT 14
+#define MT6325_NI_VGPU_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VGPU_VSLEEP_SEL_SHIFT 15
+#define MT6325_VCORE1_DIG0_RSV0_MASK 0xFF
+#define MT6325_VCORE1_DIG0_RSV0_SHIFT 8
+#define MT6325_VCORE1_EN_CTRL_MASK 0x1
+#define MT6325_VCORE1_EN_CTRL_SHIFT 0
+#define MT6325_VCORE1_VOSEL_CTRL_MASK 0x1
+#define MT6325_VCORE1_VOSEL_CTRL_SHIFT 1
+#define MT6325_VCORE1_DLC_CTRL_MASK 0x1
+#define MT6325_VCORE1_DLC_CTRL_SHIFT 2
+#define MT6325_VCORE1_BURST_CTRL_MASK 0x1
+#define MT6325_VCORE1_BURST_CTRL_SHIFT 3
+#define MT6325_VCORE1_EN_SEL_MASK 0x3
+#define MT6325_VCORE1_EN_SEL_SHIFT 0
+#define MT6325_VCORE1_VOSEL_SEL_MASK 0x3
+#define MT6325_VCORE1_VOSEL_SEL_SHIFT 4
+#define MT6325_VCORE1_DLC_SEL_MASK 0x3
+#define MT6325_VCORE1_DLC_SEL_SHIFT 8
+#define MT6325_VCORE1_BURST_SEL_MASK 0x3
+#define MT6325_VCORE1_BURST_SEL_SHIFT 12
+#define MT6325_VCORE1_EN_MASK 0x1
+#define MT6325_VCORE1_EN_SHIFT 0
+#define MT6325_VCORE1_STBTD_MASK 0x3
+#define MT6325_VCORE1_STBTD_SHIFT 4
+#define MT6325_QI_VCORE1_STB_MASK 0x1
+#define MT6325_QI_VCORE1_STB_SHIFT 12
+#define MT6325_QI_VCORE1_EN_MASK 0x1
+#define MT6325_QI_VCORE1_EN_SHIFT 13
+#define MT6325_QI_VCORE1_OC_STATUS_MASK 0x1
+#define MT6325_QI_VCORE1_OC_STATUS_SHIFT 15
+#define MT6325_VCORE1_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VCORE1_SFCHG_FRATE_SHIFT 0
+#define MT6325_VCORE1_SFCHG_FEN_MASK 0x1
+#define MT6325_VCORE1_SFCHG_FEN_SHIFT 7
+#define MT6325_VCORE1_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VCORE1_SFCHG_RRATE_SHIFT 8
+#define MT6325_VCORE1_SFCHG_REN_MASK 0x1
+#define MT6325_VCORE1_SFCHG_REN_SHIFT 15
+#define MT6325_VCORE1_VOSEL_MASK 0x7F
+#define MT6325_VCORE1_VOSEL_SHIFT 0
+#define MT6325_VCORE1_VOSEL_ON_MASK 0x7F
+#define MT6325_VCORE1_VOSEL_ON_SHIFT 0
+#define MT6325_VCORE1_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VCORE1_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VCORE1_VOSEL_MASK 0x7F
+#define MT6325_NI_VCORE1_VOSEL_SHIFT 0
+#define MT6325_VCORE1_BURST_MASK 0x7
+#define MT6325_VCORE1_BURST_SHIFT 0
+#define MT6325_VCORE1_BURST_ON_MASK 0x7
+#define MT6325_VCORE1_BURST_ON_SHIFT 4
+#define MT6325_VCORE1_BURST_SLEEP_MASK 0x7
+#define MT6325_VCORE1_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE1_BURST_MASK 0x7
+#define MT6325_QI_VCORE1_BURST_SHIFT 12
+#define MT6325_VCORE1_DLC_MASK 0x3
+#define MT6325_VCORE1_DLC_SHIFT 0
+#define MT6325_VCORE1_DLC_ON_MASK 0x3
+#define MT6325_VCORE1_DLC_ON_SHIFT 4
+#define MT6325_VCORE1_DLC_SLEEP_MASK 0x3
+#define MT6325_VCORE1_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE1_DLC_MASK 0x3
+#define MT6325_QI_VCORE1_DLC_SHIFT 12
+#define MT6325_VCORE1_DLC_N_MASK 0x3
+#define MT6325_VCORE1_DLC_N_SHIFT 0
+#define MT6325_VCORE1_DLC_N_ON_MASK 0x3
+#define MT6325_VCORE1_DLC_N_ON_SHIFT 4
+#define MT6325_VCORE1_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VCORE1_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE1_DLC_N_MASK 0x3
+#define MT6325_QI_VCORE1_DLC_N_SHIFT 12
+#define MT6325_VCORE1_TRANS_TD_MASK 0x3
+#define MT6325_VCORE1_TRANS_TD_SHIFT 0
+#define MT6325_VCORE1_TRANS_CTRL_MASK 0x3
+#define MT6325_VCORE1_TRANS_CTRL_SHIFT 4
+#define MT6325_VCORE1_TRANS_ONCE_MASK 0x1
+#define MT6325_VCORE1_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VCORE1_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VCORE1_VOSEL_TRANS_SHIFT 7
+#define MT6325_VCORE1_VSLEEP_EN_MASK 0x1
+#define MT6325_VCORE1_VSLEEP_EN_SHIFT 8
+#define MT6325_VCORE1_R2R_PDN_MASK 0x1
+#define MT6325_VCORE1_R2R_PDN_SHIFT 10
+#define MT6325_VCORE1_VSLEEP_SEL_MASK 0x1
+#define MT6325_VCORE1_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VCORE1_R2R_PDN_MASK 0x1
+#define MT6325_NI_VCORE1_R2R_PDN_SHIFT 14
+#define MT6325_NI_VCORE1_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VCORE1_VSLEEP_SEL_SHIFT 15
+#define MT6325_VCORE2_DIG0_RSV0_MASK 0xFF
+#define MT6325_VCORE2_DIG0_RSV0_SHIFT 8
+#define MT6325_VCORE2_EN_CTRL_MASK 0x1
+#define MT6325_VCORE2_EN_CTRL_SHIFT 0
+#define MT6325_VCORE2_VOSEL_CTRL_MASK 0x1
+#define MT6325_VCORE2_VOSEL_CTRL_SHIFT 1
+#define MT6325_VCORE2_DLC_CTRL_MASK 0x1
+#define MT6325_VCORE2_DLC_CTRL_SHIFT 2
+#define MT6325_VCORE2_BURST_CTRL_MASK 0x1
+#define MT6325_VCORE2_BURST_CTRL_SHIFT 3
+#define MT6325_VCORE2_EN_SEL_MASK 0x3
+#define MT6325_VCORE2_EN_SEL_SHIFT 0
+#define MT6325_VCORE2_VOSEL_SEL_MASK 0x3
+#define MT6325_VCORE2_VOSEL_SEL_SHIFT 4
+#define MT6325_VCORE2_DLC_SEL_MASK 0x3
+#define MT6325_VCORE2_DLC_SEL_SHIFT 8
+#define MT6325_VCORE2_BURST_SEL_MASK 0x3
+#define MT6325_VCORE2_BURST_SEL_SHIFT 12
+#define MT6325_VCORE2_EN_MASK 0x1
+#define MT6325_VCORE2_EN_SHIFT 0
+#define MT6325_VCORE2_STBTD_MASK 0x3
+#define MT6325_VCORE2_STBTD_SHIFT 4
+#define MT6325_QI_VCORE2_STB_MASK 0x1
+#define MT6325_QI_VCORE2_STB_SHIFT 12
+#define MT6325_QI_VCORE2_EN_MASK 0x1
+#define MT6325_QI_VCORE2_EN_SHIFT 13
+#define MT6325_QI_VCORE2_OC_STATUS_MASK 0x1
+#define MT6325_QI_VCORE2_OC_STATUS_SHIFT 15
+#define MT6325_VCORE2_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VCORE2_SFCHG_FRATE_SHIFT 0
+#define MT6325_VCORE2_SFCHG_FEN_MASK 0x1
+#define MT6325_VCORE2_SFCHG_FEN_SHIFT 7
+#define MT6325_VCORE2_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VCORE2_SFCHG_RRATE_SHIFT 8
+#define MT6325_VCORE2_SFCHG_REN_MASK 0x1
+#define MT6325_VCORE2_SFCHG_REN_SHIFT 15
+#define MT6325_VCORE2_VOSEL_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_SHIFT 0
+#define MT6325_VCORE2_VOSEL_ON_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_ON_SHIFT 0
+#define MT6325_VCORE2_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VCORE2_VOSEL_MASK 0x7F
+#define MT6325_NI_VCORE2_VOSEL_SHIFT 0
+#define MT6325_VCORE2_BURST_MASK 0x7
+#define MT6325_VCORE2_BURST_SHIFT 0
+#define MT6325_VCORE2_BURST_ON_MASK 0x7
+#define MT6325_VCORE2_BURST_ON_SHIFT 4
+#define MT6325_VCORE2_BURST_SLEEP_MASK 0x7
+#define MT6325_VCORE2_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE2_BURST_MASK 0x7
+#define MT6325_QI_VCORE2_BURST_SHIFT 12
+#define MT6325_VCORE2_DLC_MASK 0x3
+#define MT6325_VCORE2_DLC_SHIFT 0
+#define MT6325_VCORE2_DLC_ON_MASK 0x3
+#define MT6325_VCORE2_DLC_ON_SHIFT 4
+#define MT6325_VCORE2_DLC_SLEEP_MASK 0x3
+#define MT6325_VCORE2_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE2_DLC_MASK 0x3
+#define MT6325_QI_VCORE2_DLC_SHIFT 12
+#define MT6325_VCORE2_DLC_N_MASK 0x3
+#define MT6325_VCORE2_DLC_N_SHIFT 0
+#define MT6325_VCORE2_DLC_N_ON_MASK 0x3
+#define MT6325_VCORE2_DLC_N_ON_SHIFT 4
+#define MT6325_VCORE2_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VCORE2_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE2_DLC_N_MASK 0x3
+#define MT6325_QI_VCORE2_DLC_N_SHIFT 12
+#define MT6325_VCORE2_TRANS_TD_MASK 0x3
+#define MT6325_VCORE2_TRANS_TD_SHIFT 0
+#define MT6325_VCORE2_TRANS_CTRL_MASK 0x3
+#define MT6325_VCORE2_TRANS_CTRL_SHIFT 4
+#define MT6325_VCORE2_TRANS_ONCE_MASK 0x1
+#define MT6325_VCORE2_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VCORE2_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VCORE2_VOSEL_TRANS_SHIFT 7
+#define MT6325_VCORE2_VSLEEP_EN_MASK 0x1
+#define MT6325_VCORE2_VSLEEP_EN_SHIFT 8
+#define MT6325_VCORE2_R2R_PDN_MASK 0x1
+#define MT6325_VCORE2_R2R_PDN_SHIFT 10
+#define MT6325_VCORE2_VSLEEP_SEL_MASK 0x1
+#define MT6325_VCORE2_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VCORE2_R2R_PDN_MASK 0x1
+#define MT6325_NI_VCORE2_R2R_PDN_SHIFT 14
+#define MT6325_NI_VCORE2_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VCORE2_VSLEEP_SEL_SHIFT 15
+#define MT6325_VCORE2_VOSEL_AUD_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_AUD_SHIFT 0
+#define MT6325_BUCK_DVFS_DONE_MASK 0x1
+#define MT6325_BUCK_DVFS_DONE_SHIFT 0
+#define MT6325_BUCK_DVFS_DONE_SW_MASK 0x1
+#define MT6325_BUCK_DVFS_DONE_SW_SHIFT 1
+#define MT6325_VCORE_DVFS_DONE_STA_MASK 0x1
+#define MT6325_VCORE_DVFS_DONE_STA_SHIFT 2
+#define MT6325_VIO18_DIG0_RSV0_MASK 0xFF
+#define MT6325_VIO18_DIG0_RSV0_SHIFT 8
+#define MT6325_VIO18_EN_CTRL_MASK 0x1
+#define MT6325_VIO18_EN_CTRL_SHIFT 0
+#define MT6325_VIO18_VOSEL_CTRL_MASK 0x1
+#define MT6325_VIO18_VOSEL_CTRL_SHIFT 1
+#define MT6325_VIO18_DLC_CTRL_MASK 0x1
+#define MT6325_VIO18_DLC_CTRL_SHIFT 2
+#define MT6325_VIO18_BURST_CTRL_MASK 0x1
+#define MT6325_VIO18_BURST_CTRL_SHIFT 3
+#define MT6325_VIO18_EN_SEL_MASK 0x3
+#define MT6325_VIO18_EN_SEL_SHIFT 0
+#define MT6325_VIO18_VOSEL_SEL_MASK 0x3
+#define MT6325_VIO18_VOSEL_SEL_SHIFT 4
+#define MT6325_VIO18_DLC_SEL_MASK 0x3
+#define MT6325_VIO18_DLC_SEL_SHIFT 8
+#define MT6325_VIO18_BURST_SEL_MASK 0x3
+#define MT6325_VIO18_BURST_SEL_SHIFT 12
+#define MT6325_VIO18_EN_MASK 0x1
+#define MT6325_VIO18_EN_SHIFT 0
+#define MT6325_VIO18_STBTD_MASK 0x3
+#define MT6325_VIO18_STBTD_SHIFT 4
+#define MT6325_QI_VIO18_STB_MASK 0x1
+#define MT6325_QI_VIO18_STB_SHIFT 12
+#define MT6325_QI_VIO18_EN_MASK 0x1
+#define MT6325_QI_VIO18_EN_SHIFT 13
+#define MT6325_QI_VIO18_OC_STATUS_MASK 0x1
+#define MT6325_QI_VIO18_OC_STATUS_SHIFT 15
+#define MT6325_VIO18_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VIO18_SFCHG_FRATE_SHIFT 0
+#define MT6325_VIO18_SFCHG_FEN_MASK 0x1
+#define MT6325_VIO18_SFCHG_FEN_SHIFT 7
+#define MT6325_VIO18_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VIO18_SFCHG_RRATE_SHIFT 8
+#define MT6325_VIO18_SFCHG_REN_MASK 0x1
+#define MT6325_VIO18_SFCHG_REN_SHIFT 15
+#define MT6325_VIO18_VOSEL_MASK 0x7F
+#define MT6325_VIO18_VOSEL_SHIFT 0
+#define MT6325_VIO18_VOSEL_ON_MASK 0x7F
+#define MT6325_VIO18_VOSEL_ON_SHIFT 0
+#define MT6325_VIO18_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VIO18_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VIO18_VOSEL_MASK 0x7F
+#define MT6325_NI_VIO18_VOSEL_SHIFT 0
+#define MT6325_VIO18_BURST_MASK 0x7
+#define MT6325_VIO18_BURST_SHIFT 0
+#define MT6325_VIO18_BURST_ON_MASK 0x7
+#define MT6325_VIO18_BURST_ON_SHIFT 4
+#define MT6325_VIO18_BURST_SLEEP_MASK 0x7
+#define MT6325_VIO18_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VIO18_BURST_MASK 0x7
+#define MT6325_QI_VIO18_BURST_SHIFT 12
+#define MT6325_VIO18_DLC_MASK 0x3
+#define MT6325_VIO18_DLC_SHIFT 0
+#define MT6325_VIO18_DLC_ON_MASK 0x3
+#define MT6325_VIO18_DLC_ON_SHIFT 4
+#define MT6325_VIO18_DLC_SLEEP_MASK 0x3
+#define MT6325_VIO18_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VIO18_DLC_MASK 0x3
+#define MT6325_QI_VIO18_DLC_SHIFT 12
+#define MT6325_VIO18_DLC_N_MASK 0x3
+#define MT6325_VIO18_DLC_N_SHIFT 0
+#define MT6325_VIO18_DLC_N_ON_MASK 0x3
+#define MT6325_VIO18_DLC_N_ON_SHIFT 4
+#define MT6325_VIO18_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VIO18_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VIO18_DLC_N_MASK 0x3
+#define MT6325_QI_VIO18_DLC_N_SHIFT 12
+#define MT6325_VIO18_TRANS_TD_MASK 0x3
+#define MT6325_VIO18_TRANS_TD_SHIFT 0
+#define MT6325_VIO18_TRANS_CTRL_MASK 0x3
+#define MT6325_VIO18_TRANS_CTRL_SHIFT 4
+#define MT6325_VIO18_TRANS_ONCE_MASK 0x1
+#define MT6325_VIO18_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VIO18_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VIO18_VOSEL_TRANS_SHIFT 7
+#define MT6325_VIO18_VSLEEP_EN_MASK 0x1
+#define MT6325_VIO18_VSLEEP_EN_SHIFT 8
+#define MT6325_VIO18_R2R_PDN_MASK 0x1
+#define MT6325_VIO18_R2R_PDN_SHIFT 10
+#define MT6325_VIO18_VSLEEP_SEL_MASK 0x1
+#define MT6325_VIO18_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VIO18_R2R_PDN_MASK 0x1
+#define MT6325_NI_VIO18_R2R_PDN_SHIFT 14
+#define MT6325_NI_VIO18_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VIO18_VSLEEP_SEL_SHIFT 15
+#define MT6325_VPA_DIG0_RSV0_MASK 0xFF
+#define MT6325_VPA_DIG0_RSV0_SHIFT 8
+#define MT6325_VPA_EN_CTRL_MASK 0x1
+#define MT6325_VPA_EN_CTRL_SHIFT 0
+#define MT6325_VPA_VOSEL_CTRL_MASK 0x1
+#define MT6325_VPA_VOSEL_CTRL_SHIFT 1
+#define MT6325_VPA_DLC_CTRL_MASK 0x1
+#define MT6325_VPA_DLC_CTRL_SHIFT 2
+#define MT6325_VPA_BURST_CTRL_MASK 0x1
+#define MT6325_VPA_BURST_CTRL_SHIFT 3
+#define MT6325_VPA_EN_SEL_MASK 0x3
+#define MT6325_VPA_EN_SEL_SHIFT 0
+#define MT6325_VPA_VOSEL_SEL_MASK 0x3
+#define MT6325_VPA_VOSEL_SEL_SHIFT 4
+#define MT6325_VPA_DLC_SEL_MASK 0x3
+#define MT6325_VPA_DLC_SEL_SHIFT 8
+#define MT6325_VPA_BURST_SEL_MASK 0x3
+#define MT6325_VPA_BURST_SEL_SHIFT 12
+#define MT6325_VPA_EN_MASK 0x1
+#define MT6325_VPA_EN_SHIFT 0
+#define MT6325_VPA_STBTD_MASK 0x3
+#define MT6325_VPA_STBTD_SHIFT 4
+#define MT6325_QI_VPA_STB_MASK 0x1
+#define MT6325_QI_VPA_STB_SHIFT 12
+#define MT6325_QI_VPA_EN_MASK 0x1
+#define MT6325_QI_VPA_EN_SHIFT 13
+#define MT6325_QI_VPA_OC_STATUS_MASK 0x1
+#define MT6325_QI_VPA_OC_STATUS_SHIFT 15
+#define MT6325_VPA_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VPA_SFCHG_FRATE_SHIFT 0
+#define MT6325_VPA_SFCHG_FEN_MASK 0x1
+#define MT6325_VPA_SFCHG_FEN_SHIFT 7
+#define MT6325_VPA_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VPA_SFCHG_RRATE_SHIFT 8
+#define MT6325_VPA_SFCHG_REN_MASK 0x1
+#define MT6325_VPA_SFCHG_REN_SHIFT 15
+#define MT6325_VPA_VOSEL_MASK 0x3F
+#define MT6325_VPA_VOSEL_SHIFT 0
+#define MT6325_VPA_VOSEL_ON_MASK 0x3F
+#define MT6325_VPA_VOSEL_ON_SHIFT 0
+#define MT6325_VPA_VOSEL_SLEEP_MASK 0x3F
+#define MT6325_VPA_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VPA_VOSEL_MASK 0x3F
+#define MT6325_NI_VPA_VOSEL_SHIFT 0
+#define MT6325_VPA_DIG0_RSV3_MASK 0x7
+#define MT6325_VPA_DIG0_RSV3_SHIFT 11
+#define MT6325_VPA_DLC_MASK 0x7
+#define MT6325_VPA_DLC_SHIFT 0
+#define MT6325_VPA_DLC_ON_MASK 0x7
+#define MT6325_VPA_DLC_ON_SHIFT 4
+#define MT6325_VPA_DLC_SLEEP_MASK 0x7
+#define MT6325_VPA_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VPA_DLC_MASK 0x7
+#define MT6325_QI_VPA_DLC_SHIFT 12
+#define MT6325_VPA_DIG0_RSV1_MASK 0xFF
+#define MT6325_VPA_DIG0_RSV1_SHIFT 0
+#define MT6325_VPA_DIG1_RSV1_MASK 0xFF
+#define MT6325_VPA_DIG1_RSV1_SHIFT 8
+#define MT6325_VPA_TRANS_TD_MASK 0x3
+#define MT6325_VPA_TRANS_TD_SHIFT 0
+#define MT6325_VPA_TRANS_CTRL_MASK 0x3
+#define MT6325_VPA_TRANS_CTRL_SHIFT 4
+#define MT6325_VPA_TRANS_ONCE_MASK 0x1
+#define MT6325_VPA_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VPA_DVS_BW_MASK 0x1
+#define MT6325_NI_VPA_DVS_BW_SHIFT 7
+#define MT6325_VPA_DIG1_RSV4_MASK 0x3
+#define MT6325_VPA_DIG1_RSV4_SHIFT 10
+#define MT6325_VPA_DIG1_RSV3_MASK 0x3
+#define MT6325_VPA_DIG1_RSV3_SHIFT 14
+#define MT6325_VPA_BURSTH_MASK 0x3
+#define MT6325_VPA_BURSTH_SHIFT 0
+#define MT6325_VPA_BURSTH_ON_MASK 0x3
+#define MT6325_VPA_BURSTH_ON_SHIFT 4
+#define MT6325_VPA_BURSTH_SLEEP_MASK 0x3
+#define MT6325_VPA_BURSTH_SLEEP_SHIFT 8
+#define MT6325_QI_VPA_BURSTH_MASK 0x3
+#define MT6325_QI_VPA_BURSTH_SHIFT 12
+#define MT6325_VPA_BURSTL_MASK 0x3
+#define MT6325_VPA_BURSTL_SHIFT 0
+#define MT6325_VPA_BURSTL_ON_MASK 0x3
+#define MT6325_VPA_BURSTL_ON_SHIFT 4
+#define MT6325_VPA_BURSTL_SLEEP_MASK 0x3
+#define MT6325_VPA_BURSTL_SLEEP_SHIFT 8
+#define MT6325_QI_VPA_BURSTL_MASK 0x3
+#define MT6325_QI_VPA_BURSTL_SHIFT 12
+#define MT6325_VPA_VOSEL_DLC011_MASK 0x3F
+#define MT6325_VPA_VOSEL_DLC011_SHIFT 0
+#define MT6325_VPA_VOSEL_DLC111_MASK 0x3F
+#define MT6325_VPA_VOSEL_DLC111_SHIFT 8
+#define MT6325_VPA_DLC_MAP_EN_MASK 0x1
+#define MT6325_VPA_DLC_MAP_EN_SHIFT 0
+#define MT6325_VPA_VOSEL_DLC001_MASK 0x3F
+#define MT6325_VPA_VOSEL_DLC001_SHIFT 8
+#define MT6325_VPA_DVS_TRANS_TD_MASK 0x3
+#define MT6325_VPA_DVS_TRANS_TD_SHIFT 0
+#define MT6325_VPA_DVS_TRANS_CTRL_MASK 0x3
+#define MT6325_VPA_DVS_TRANS_CTRL_SHIFT 4
+#define MT6325_VPA_DVS_TRANS_ONCE_MASK 0x1
+#define MT6325_VPA_DVS_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VPA_DVS_TRANST_MASK 0x1
+#define MT6325_NI_VPA_DVS_TRANST_SHIFT 7
+#define MT6325_VPA_DIG0_RSV4_MASK 0xF
+#define MT6325_VPA_DIG0_RSV4_SHIFT 8
+#define MT6325_VPA_DIG1_RSV2_MASK 0xF
+#define MT6325_VPA_DIG1_RSV2_SHIFT 12
+#define MT6325_K_RST_DONE_MASK 0x1
+#define MT6325_K_RST_DONE_SHIFT 0
+#define MT6325_K_MAP_SEL_MASK 0x1
+#define MT6325_K_MAP_SEL_SHIFT 1
+#define MT6325_K_ONCE_EN_MASK 0x1
+#define MT6325_K_ONCE_EN_SHIFT 2
+#define MT6325_K_ONCE_MASK 0x1
+#define MT6325_K_ONCE_SHIFT 3
+#define MT6325_K_START_MANUAL_MASK 0x1
+#define MT6325_K_START_MANUAL_SHIFT 4
+#define MT6325_K_SRC_SEL_MASK 0x1
+#define MT6325_K_SRC_SEL_SHIFT 5
+#define MT6325_K_AUTO_EN_MASK 0x1
+#define MT6325_K_AUTO_EN_SHIFT 6
+#define MT6325_K_INV_MASK 0x1
+#define MT6325_K_INV_SHIFT 7
+#define MT6325_K_CONTROL_SMPS_MASK 0x3F
+#define MT6325_K_CONTROL_SMPS_SHIFT 8
+#define MT6325_K_RESULT_MASK 0x1
+#define MT6325_K_RESULT_SHIFT 0
+#define MT6325_K_DONE_MASK 0x1
+#define MT6325_K_DONE_SHIFT 1
+#define MT6325_K_CONTROL_MASK 0x3F
+#define MT6325_K_CONTROL_SHIFT 2
+#define MT6325_QI_SMPS_OSC_CAL_MASK 0x3F
+#define MT6325_QI_SMPS_OSC_CAL_SHIFT 8
+#define MT6325_K_BUCK_CK_CNT_MASK 0x3FF
+#define MT6325_K_BUCK_CK_CNT_SHIFT 0
+#define MT6325_RG_AUDZCDENABLE_MASK 0x1
+#define MT6325_RG_AUDZCDENABLE_SHIFT 0
+#define MT6325_RG_AUDZCDGAINSTEPTIME_MASK 0x7
+#define MT6325_RG_AUDZCDGAINSTEPTIME_SHIFT 1
+#define MT6325_RG_AUDZCDGAINSTEPSIZE_MASK 0x3
+#define MT6325_RG_AUDZCDGAINSTEPSIZE_SHIFT 4
+#define MT6325_RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
+#define MT6325_RG_AUDZCDTIMEOUTMODESEL_SHIFT 6
+#define MT6325_RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDZCDCLKSEL_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7
+#define MT6325_RG_AUDZCDMUXSEL_VAUDP15_SHIFT 8
+#define MT6325_RG_AUDLOLGAIN_MASK 0x1F
+#define MT6325_RG_AUDLOLGAIN_SHIFT 0
+#define MT6325_RG_AUDLORGAIN_MASK 0x1F
+#define MT6325_RG_AUDLORGAIN_SHIFT 7
+#define MT6325_RG_AUDHPLGAIN_MASK 0x1F
+#define MT6325_RG_AUDHPLGAIN_SHIFT 0
+#define MT6325_RG_AUDHPRGAIN_MASK 0x1F
+#define MT6325_RG_AUDHPRGAIN_SHIFT 7
+#define MT6325_RG_AUDHSGAIN_MASK 0x1F
+#define MT6325_RG_AUDHSGAIN_SHIFT 0
+#define MT6325_RG_AUDIVLGAIN_MASK 0x7
+#define MT6325_RG_AUDIVLGAIN_SHIFT 0
+#define MT6325_RG_AUDIVRGAIN_MASK 0x7
+#define MT6325_RG_AUDIVRGAIN_SHIFT 8
+#define MT6325_RG_AUDINTGAIN1_MASK 0x3F
+#define MT6325_RG_AUDINTGAIN1_SHIFT 0
+#define MT6325_RG_AUDINTGAIN2_MASK 0x3F
+#define MT6325_RG_AUDINTGAIN2_SHIFT 8
+#define MT6325_ISINK_DIM0_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM0_FSEL_SHIFT 0
+#define MT6325_ISINK0_RSV1_MASK 0xF
+#define MT6325_ISINK0_RSV1_SHIFT 0
+#define MT6325_ISINK0_RSV0_MASK 0x7
+#define MT6325_ISINK0_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM0_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM0_DUTY_SHIFT 7
+#define MT6325_ISINK_CH0_STEP_MASK 0x7
+#define MT6325_ISINK_CH0_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH0_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH0_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH0_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH0_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH0_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH0_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TON_SEL_SHIFT 8
+#define MT6325_ISINK_DIM1_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM1_FSEL_SHIFT 0
+#define MT6325_ISINK1_RSV1_MASK 0xF
+#define MT6325_ISINK1_RSV1_SHIFT 0
+#define MT6325_ISINK1_RSV0_MASK 0x7
+#define MT6325_ISINK1_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM1_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM1_DUTY_SHIFT 7
+#define MT6325_ISINK_CH1_STEP_MASK 0x7
+#define MT6325_ISINK_CH1_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH1_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH1_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH1_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH1_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH1_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH1_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TON_SEL_SHIFT 8
+#define MT6325_ISINK_DIM2_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM2_FSEL_SHIFT 0
+#define MT6325_ISINK2_RSV1_MASK 0xF
+#define MT6325_ISINK2_RSV1_SHIFT 0
+#define MT6325_ISINK2_RSV0_MASK 0x7
+#define MT6325_ISINK2_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM2_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM2_DUTY_SHIFT 7
+#define MT6325_ISINK_CH2_STEP_MASK 0x7
+#define MT6325_ISINK_CH2_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH2_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH2_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH2_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH2_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH2_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH2_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TON_SEL_SHIFT 8
+#define MT6325_ISINK_DIM3_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM3_FSEL_SHIFT 0
+#define MT6325_ISINK3_RSV1_MASK 0xF
+#define MT6325_ISINK3_RSV1_SHIFT 0
+#define MT6325_ISINK3_RSV0_MASK 0x7
+#define MT6325_ISINK3_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM3_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM3_DUTY_SHIFT 7
+#define MT6325_ISINK_CH3_STEP_MASK 0x7
+#define MT6325_ISINK_CH3_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH3_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH3_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH3_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH3_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH3_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH3_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TON_SEL_SHIFT 8
+#define MT6325_RG_ISINKS_RSV_MASK 0xFF
+#define MT6325_RG_ISINKS_RSV_SHIFT 0
+#define MT6325_RG_ISINK3_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK3_DOUBLE_EN_SHIFT 8
+#define MT6325_RG_ISINK2_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK2_DOUBLE_EN_SHIFT 9
+#define MT6325_RG_ISINK1_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK1_DOUBLE_EN_SHIFT 10
+#define MT6325_RG_ISINK0_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK0_DOUBLE_EN_SHIFT 11
+#define MT6325_RG_TRIM_SEL_MASK 0x7
+#define MT6325_RG_TRIM_SEL_SHIFT 12
+#define MT6325_RG_TRIM_EN_MASK 0x1
+#define MT6325_RG_TRIM_EN_SHIFT 15
+#define MT6325_NI_ISINK3_STATUS_MASK 0x1
+#define MT6325_NI_ISINK3_STATUS_SHIFT 0
+#define MT6325_NI_ISINK2_STATUS_MASK 0x1
+#define MT6325_NI_ISINK2_STATUS_SHIFT 1
+#define MT6325_NI_ISINK1_STATUS_MASK 0x1
+#define MT6325_NI_ISINK1_STATUS_SHIFT 2
+#define MT6325_NI_ISINK0_STATUS_MASK 0x1
+#define MT6325_NI_ISINK0_STATUS_SHIFT 3
+#define MT6325_ISINK_PHASE0_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE0_DLY_EN_SHIFT 0
+#define MT6325_ISINK_PHASE1_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE1_DLY_EN_SHIFT 1
+#define MT6325_ISINK_PHASE2_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE2_DLY_EN_SHIFT 2
+#define MT6325_ISINK_PHASE3_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE3_DLY_EN_SHIFT 3
+#define MT6325_ISINK_PHASE_DLY_TC_MASK 0x3
+#define MT6325_ISINK_PHASE_DLY_TC_SHIFT 4
+#define MT6325_ISINK_CHOP0_SW_MASK 0x1
+#define MT6325_ISINK_CHOP0_SW_SHIFT 12
+#define MT6325_ISINK_CHOP1_SW_MASK 0x1
+#define MT6325_ISINK_CHOP1_SW_SHIFT 13
+#define MT6325_ISINK_CHOP2_SW_MASK 0x1
+#define MT6325_ISINK_CHOP2_SW_SHIFT 14
+#define MT6325_ISINK_CHOP3_SW_MASK 0x1
+#define MT6325_ISINK_CHOP3_SW_SHIFT 15
+#define MT6325_ISINK_SFSTR3_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR3_EN_SHIFT 0
+#define MT6325_ISINK_SFSTR3_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR3_TC_SHIFT 1
+#define MT6325_ISINK_SFSTR2_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR2_EN_SHIFT 4
+#define MT6325_ISINK_SFSTR2_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR2_TC_SHIFT 5
+#define MT6325_ISINK_SFSTR1_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR1_EN_SHIFT 8
+#define MT6325_ISINK_SFSTR1_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR1_TC_SHIFT 9
+#define MT6325_ISINK_SFSTR0_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR0_EN_SHIFT 12
+#define MT6325_ISINK_SFSTR0_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR0_TC_SHIFT 13
+#define MT6325_ISINK_CH0_EN_MASK 0x1
+#define MT6325_ISINK_CH0_EN_SHIFT 0
+#define MT6325_ISINK_CH1_EN_MASK 0x1
+#define MT6325_ISINK_CH1_EN_SHIFT 1
+#define MT6325_ISINK_CH2_EN_MASK 0x1
+#define MT6325_ISINK_CH2_EN_SHIFT 2
+#define MT6325_ISINK_CH3_EN_MASK 0x1
+#define MT6325_ISINK_CH3_EN_SHIFT 3
+#define MT6325_ISINK_CHOP0_EN_MASK 0x1
+#define MT6325_ISINK_CHOP0_EN_SHIFT 4
+#define MT6325_ISINK_CHOP1_EN_MASK 0x1
+#define MT6325_ISINK_CHOP1_EN_SHIFT 5
+#define MT6325_ISINK_CHOP2_EN_MASK 0x1
+#define MT6325_ISINK_CHOP2_EN_SHIFT 6
+#define MT6325_ISINK_CHOP3_EN_MASK 0x1
+#define MT6325_ISINK_CHOP3_EN_SHIFT 7
+#define MT6325_ISINK_CH0_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH0_BIAS_EN_SHIFT 8
+#define MT6325_ISINK_CH1_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH1_BIAS_EN_SHIFT 9
+#define MT6325_ISINK_CH2_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH2_BIAS_EN_SHIFT 10
+#define MT6325_ISINK_CH3_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH3_BIAS_EN_SHIFT 11
+#define MT6325_ISINK_RSV_MASK 0xF
+#define MT6325_ISINK_RSV_SHIFT 0
+#define MT6325_ISINK_CH3_MODE_MASK 0x3
+#define MT6325_ISINK_CH3_MODE_SHIFT 8
+#define MT6325_ISINK_CH2_MODE_MASK 0x3
+#define MT6325_ISINK_CH2_MODE_SHIFT 10
+#define MT6325_ISINK_CH1_MODE_MASK 0x3
+#define MT6325_ISINK_CH1_MODE_SHIFT 12
+#define MT6325_ISINK_CH0_MODE_MASK 0x3
+#define MT6325_ISINK_CH0_MODE_SHIFT 14
+#define MT6325_RG_ISINKS_CH0_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH0_STEP_SHIFT 0
+#define MT6325_RG_ISINKS_CH1_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH1_STEP_SHIFT 3
+#define MT6325_RG_ISINKS_CH2_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH2_STEP_SHIFT 6
+#define MT6325_RG_ISINKS_CH3_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH3_STEP_SHIFT 9
+#define MT6325_RG_VTCXO0_MODE_SET_MASK 0x1
+#define MT6325_RG_VTCXO0_MODE_SET_SHIFT 0
+#define MT6325_RG_VTCXO0_EN_MASK 0x1
+#define MT6325_RG_VTCXO0_EN_SHIFT 1
+#define MT6325_RG_VTCXO0_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO0_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VTCXO0_ON_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO0_ON_CTRL_SHIFT 3
+#define MT6325_RG_VTCXO0_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VTCXO0_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VTCXO0_MODE_MASK 0x1
+#define MT6325_QI_VTCXO0_MODE_SHIFT 7
+#define MT6325_RG_VTCXO0_STBTD_MASK 0x3
+#define MT6325_RG_VTCXO0_STBTD_SHIFT 8
+#define MT6325_RG_VTCXO0_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VTCXO0_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VTCXO0_STB_MASK 0x1
+#define MT6325_QI_VTCXO0_STB_SHIFT 14
+#define MT6325_QI_VTCXO0_EN_MASK 0x1
+#define MT6325_QI_VTCXO0_EN_SHIFT 15
+#define MT6325_RG_VTCXO1_MODE_SET_MASK 0x1
+#define MT6325_RG_VTCXO1_MODE_SET_SHIFT 0
+#define MT6325_RG_VTCXO1_EN_MASK 0x1
+#define MT6325_RG_VTCXO1_EN_SHIFT 1
+#define MT6325_RG_VTCXO1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VTCXO1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VTCXO1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VTCXO1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VTCXO1_MODE_MASK 0x1
+#define MT6325_QI_VTCXO1_MODE_SHIFT 7
+#define MT6325_RG_VTCXO1_STBTD_MASK 0x3
+#define MT6325_RG_VTCXO1_STBTD_SHIFT 8
+#define MT6325_RG_VTCXO1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VTCXO1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VTCXO1_STB_MASK 0x1
+#define MT6325_QI_VTCXO1_STB_SHIFT 14
+#define MT6325_QI_VTCXO1_EN_MASK 0x1
+#define MT6325_QI_VTCXO1_EN_SHIFT 15
+#define MT6325_RG_VAUD28_MODE_SET_MASK 0x1
+#define MT6325_RG_VAUD28_MODE_SET_SHIFT 0
+#define MT6325_RG_VAUD28_EN_MASK 0x1
+#define MT6325_RG_VAUD28_EN_SHIFT 1
+#define MT6325_RG_VAUD28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VAUD28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VAUD28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VAUD28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VAUD28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VAUD28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VAUD28_MODE_MASK 0x1
+#define MT6325_QI_VAUD28_MODE_SHIFT 7
+#define MT6325_RG_VAUD28_STBTD_MASK 0x3
+#define MT6325_RG_VAUD28_STBTD_SHIFT 8
+#define MT6325_RG_VAUD28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VAUD28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VAUD28_STB_MASK 0x1
+#define MT6325_QI_VAUD28_STB_SHIFT 14
+#define MT6325_QI_VAUD28_EN_MASK 0x1
+#define MT6325_QI_VAUD28_EN_SHIFT 15
+#define MT6325_RG_VAUXA28_MODE_SET_MASK 0x1
+#define MT6325_RG_VAUXA28_MODE_SET_SHIFT 0
+#define MT6325_RG_VAUXA28_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_EN_SHIFT 1
+#define MT6325_RG_VAUXA28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VAUXA28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VAUXA28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VAUXA28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VAUXA28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VAUXA28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VAUXA28_MODE_MASK 0x1
+#define MT6325_QI_VAUXA28_MODE_SHIFT 7
+#define MT6325_RG_VAUXA28_STBTD_MASK 0x3
+#define MT6325_RG_VAUXA28_STBTD_SHIFT 8
+#define MT6325_RG_VAUXA28_AUXADC_PWDB_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_AUXADC_PWDB_EN_SHIFT 11
+#define MT6325_RG_VAUXA28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VAUXA28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VAUXA28_STB_MASK 0x1
+#define MT6325_QI_VAUXA28_STB_SHIFT 14
+#define MT6325_QI_VAUXA28_EN_MASK 0x1
+#define MT6325_QI_VAUXA28_EN_SHIFT 15
+#define MT6325_RG_VBIF28_MODE_SET_MASK 0x1
+#define MT6325_RG_VBIF28_MODE_SET_SHIFT 0
+#define MT6325_RG_VBIF28_EN_MASK 0x1
+#define MT6325_RG_VBIF28_EN_SHIFT 1
+#define MT6325_RG_VBIF28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VBIF28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VBIF28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VBIF28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VBIF28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VBIF28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VBIF28_MODE_MASK 0x1
+#define MT6325_QI_VBIF28_MODE_SHIFT 7
+#define MT6325_RG_VBIF28_STBTD_MASK 0x3
+#define MT6325_RG_VBIF28_STBTD_SHIFT 8
+#define MT6325_RG_VBIF28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VBIF28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VBIF28_STB_MASK 0x1
+#define MT6325_QI_VBIF28_STB_SHIFT 14
+#define MT6325_QI_VBIF28_EN_MASK 0x1
+#define MT6325_QI_VBIF28_EN_SHIFT 15
+#define MT6325_RG_VCAMA_EN_MASK 0x1
+#define MT6325_RG_VCAMA_EN_SHIFT 1
+#define MT6325_RG_VCAMA_STBTD_MASK 0x3
+#define MT6325_RG_VCAMA_STBTD_SHIFT 8
+#define MT6325_QI_VCAMA_STB_MASK 0x1
+#define MT6325_QI_VCAMA_STB_SHIFT 14
+#define MT6325_QI_VCAMA_EN_MASK 0x1
+#define MT6325_QI_VCAMA_EN_SHIFT 15
+#define MT6325_RG_VCN28_MODE_SET_MASK 0x1
+#define MT6325_RG_VCN28_MODE_SET_SHIFT 0
+#define MT6325_RG_VCN28_EN_MASK 0x1
+#define MT6325_RG_VCN28_EN_SHIFT 1
+#define MT6325_RG_VCN28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCN28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCN28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCN28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCN28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCN28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCN28_MODE_MASK 0x1
+#define MT6325_QI_VCN28_MODE_SHIFT 7
+#define MT6325_RG_VCN28_STBTD_MASK 0x3
+#define MT6325_RG_VCN28_STBTD_SHIFT 8
+#define MT6325_RG_VCN28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCN28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCN28_STB_MASK 0x1
+#define MT6325_QI_VCN28_STB_SHIFT 14
+#define MT6325_QI_VCN28_EN_MASK 0x1
+#define MT6325_QI_VCN28_EN_SHIFT 15
+#define MT6325_RG_VCN33_MODE_SET_MASK 0x1
+#define MT6325_RG_VCN33_MODE_SET_SHIFT 0
+#define MT6325_RG_VCN33_EN_MASK 0x1
+#define MT6325_RG_VCN33_EN_SHIFT 1
+#define MT6325_RG_VCN33_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCN33_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCN33_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCN33_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCN33_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCN33_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCN33_MODE_MASK 0x1
+#define MT6325_QI_VCN33_MODE_SHIFT 7
+#define MT6325_RG_VCN33_STBTD_MASK 0x3
+#define MT6325_RG_VCN33_STBTD_SHIFT 8
+#define MT6325_RG_VCN33_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCN33_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCN33_STB_MASK 0x1
+#define MT6325_QI_VCN33_STB_SHIFT 14
+#define MT6325_QI_VCN33_EN_MASK 0x1
+#define MT6325_QI_VCN33_EN_SHIFT 15
+#define MT6325_RG_VRF18_1_MODE_SET_MASK 0x1
+#define MT6325_RG_VRF18_1_MODE_SET_SHIFT 0
+#define MT6325_RG_VRF18_1_EN_MASK 0x1
+#define MT6325_RG_VRF18_1_EN_SHIFT 1
+#define MT6325_RG_VRF18_1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VRF18_1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VRF18_1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VRF18_1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VRF18_1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VRF18_1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VRF18_1_MODE_MASK 0x1
+#define MT6325_QI_VRF18_1_MODE_SHIFT 7
+#define MT6325_RG_VRF18_1_STBTD_MASK 0x3
+#define MT6325_RG_VRF18_1_STBTD_SHIFT 8
+#define MT6325_RG_VRF18_1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VRF18_1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VRF18_1_STB_MASK 0x1
+#define MT6325_QI_VRF18_1_STB_SHIFT 14
+#define MT6325_QI_VRF18_1_EN_MASK 0x1
+#define MT6325_QI_VRF18_1_EN_SHIFT 15
+#define MT6325_RG_VUSB33_MODE_SET_MASK 0x1
+#define MT6325_RG_VUSB33_MODE_SET_SHIFT 0
+#define MT6325_RG_VUSB33_EN_MASK 0x1
+#define MT6325_RG_VUSB33_EN_SHIFT 1
+#define MT6325_RG_VUSB33_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VUSB33_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VUSB33_ON_CTRL_MASK 0x1
+#define MT6325_RG_VUSB33_ON_CTRL_SHIFT 3
+#define MT6325_RG_VUSB33_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VUSB33_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VUSB33_MODE_MASK 0x1
+#define MT6325_QI_VUSB33_MODE_SHIFT 7
+#define MT6325_RG_VUSB33_STBTD_MASK 0x3
+#define MT6325_RG_VUSB33_STBTD_SHIFT 8
+#define MT6325_RG_VUSB33_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VUSB33_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VUSB33_STB_MASK 0x1
+#define MT6325_QI_VUSB33_STB_SHIFT 14
+#define MT6325_QI_VUSB33_EN_MASK 0x1
+#define MT6325_QI_VUSB33_EN_SHIFT 15
+#define MT6325_RG_VMCH_MODE_SET_MASK 0x1
+#define MT6325_RG_VMCH_MODE_SET_SHIFT 0
+#define MT6325_RG_VMCH_EN_MASK 0x1
+#define MT6325_RG_VMCH_EN_SHIFT 1
+#define MT6325_RG_VMCH_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VMCH_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VMCH_ON_CTRL_MASK 0x1
+#define MT6325_RG_VMCH_ON_CTRL_SHIFT 3
+#define MT6325_RG_VMCH_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VMCH_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VMCH_MODE_MASK 0x1
+#define MT6325_QI_VMCH_MODE_SHIFT 7
+#define MT6325_RG_VMCH_STBTD_MASK 0x3
+#define MT6325_RG_VMCH_STBTD_SHIFT 8
+#define MT6325_RG_VMCH_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VMCH_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VMCH_STB_MASK 0x1
+#define MT6325_QI_VMCH_STB_SHIFT 14
+#define MT6325_QI_VMCH_EN_MASK 0x1
+#define MT6325_QI_VMCH_EN_SHIFT 15
+#define MT6325_RG_VMC_MODE_SET_MASK 0x1
+#define MT6325_RG_VMC_MODE_SET_SHIFT 0
+#define MT6325_RG_VMC_EN_MASK 0x1
+#define MT6325_RG_VMC_EN_SHIFT 1
+#define MT6325_RG_VMC_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VMC_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VMC_ON_CTRL_MASK 0x1
+#define MT6325_RG_VMC_ON_CTRL_SHIFT 3
+#define MT6325_RG_VMC_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VMC_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VMC_INT_DIS_MASK 0x1
+#define MT6325_QI_VMC_INT_DIS_SHIFT 6
+#define MT6325_QI_VMC_MODE_MASK 0x1
+#define MT6325_QI_VMC_MODE_SHIFT 7
+#define MT6325_RG_VMC_STBTD_MASK 0x3
+#define MT6325_RG_VMC_STBTD_SHIFT 8
+#define MT6325_RG_VMC_INT_DIS_SEL_MASK 0x3
+#define MT6325_RG_VMC_INT_DIS_SEL_SHIFT 10
+#define MT6325_RG_VMC_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VMC_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VMC_STB_MASK 0x1
+#define MT6325_QI_VMC_STB_SHIFT 14
+#define MT6325_QI_VMC_EN_MASK 0x1
+#define MT6325_QI_VMC_EN_SHIFT 15
+#define MT6325_RG_VEMC33_MODE_SET_MASK 0x1
+#define MT6325_RG_VEMC33_MODE_SET_SHIFT 0
+#define MT6325_RG_VEMC33_EN_MASK 0x1
+#define MT6325_RG_VEMC33_EN_SHIFT 1
+#define MT6325_RG_VEMC33_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VEMC33_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VEMC33_ON_CTRL_MASK 0x1
+#define MT6325_RG_VEMC33_ON_CTRL_SHIFT 3
+#define MT6325_RG_VEMC33_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VEMC33_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VEMC_3V3_MODE_MASK 0x1
+#define MT6325_QI_VEMC_3V3_MODE_SHIFT 7
+#define MT6325_RG_VEMC33_STBTD_MASK 0x3
+#define MT6325_RG_VEMC33_STBTD_SHIFT 8
+#define MT6325_RG_VEMC33_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VEMC33_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VEMC_3V3_STB_MASK 0x1
+#define MT6325_QI_VEMC_3V3_STB_SHIFT 14
+#define MT6325_QI_VEMC_3V3_EN_MASK 0x1
+#define MT6325_QI_VEMC_3V3_EN_SHIFT 15
+#define MT6325_RG_VIO28_MODE_SET_MASK 0x1
+#define MT6325_RG_VIO28_MODE_SET_SHIFT 0
+#define MT6325_RG_VIO28_EN_MASK 0x1
+#define MT6325_RG_VIO28_EN_SHIFT 1
+#define MT6325_RG_VIO28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VIO28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VIO28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VIO28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VIO28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VIO28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VIO28_MODE_MASK 0x1
+#define MT6325_QI_VIO28_MODE_SHIFT 7
+#define MT6325_RG_VIO28_STBTD_MASK 0x3
+#define MT6325_RG_VIO28_STBTD_SHIFT 8
+#define MT6325_RG_VIO28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VIO28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VIO28_STB_MASK 0x1
+#define MT6325_QI_VIO28_STB_SHIFT 14
+#define MT6325_QI_VIO28_EN_MASK 0x1
+#define MT6325_QI_VIO28_EN_SHIFT 15
+#define MT6325_RG_VCAM_AF_MODE_SET_MASK 0x1
+#define MT6325_RG_VCAM_AF_MODE_SET_SHIFT 0
+#define MT6325_RG_VCAM_AF_EN_MASK 0x1
+#define MT6325_RG_VCAM_AF_EN_SHIFT 1
+#define MT6325_RG_VCAM_AF_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_AF_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCAM_AF_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_AF_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCAM_AF_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCAM_AF_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCAMAF_MODE_MASK 0x1
+#define MT6325_QI_VCAMAF_MODE_SHIFT 7
+#define MT6325_RG_VCAM_AF_STBTD_MASK 0x3
+#define MT6325_RG_VCAM_AF_STBTD_SHIFT 8
+#define MT6325_RG_VCAM_AF_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCAM_AF_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCAMAF_STB_MASK 0x1
+#define MT6325_QI_VCAMAF_STB_SHIFT 14
+#define MT6325_QI_VCAMAF_EN_MASK 0x1
+#define MT6325_QI_VCAMAF_EN_SHIFT 15
+#define MT6325_RG_VGP1_MODE_SET_MASK 0x1
+#define MT6325_RG_VGP1_MODE_SET_SHIFT 0
+#define MT6325_RG_VGP1_EN_MASK 0x1
+#define MT6325_RG_VGP1_EN_SHIFT 1
+#define MT6325_RG_VGP1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VGP1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VGP1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VGP1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VGP1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VGP1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VGP1_MODE_MASK 0x1
+#define MT6325_QI_VGP1_MODE_SHIFT 7
+#define MT6325_RG_VGP1_STBTD_MASK 0x3
+#define MT6325_RG_VGP1_STBTD_SHIFT 8
+#define MT6325_RG_VGP1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VGP1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VGP1_STB_MASK 0x1
+#define MT6325_QI_VGP1_STB_SHIFT 14
+#define MT6325_QI_VGP1_EN_MASK 0x1
+#define MT6325_QI_VGP1_EN_SHIFT 15
+#define MT6325_RG_VEFUSE_MODE_SET_MASK 0x1
+#define MT6325_RG_VEFUSE_MODE_SET_SHIFT 0
+#define MT6325_RG_VEFUSE_EN_MASK 0x1
+#define MT6325_RG_VEFUSE_EN_SHIFT 1
+#define MT6325_RG_VEFUSE_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VEFUSE_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VEFUSE_ON_CTRL_MASK 0x1
+#define MT6325_RG_VEFUSE_ON_CTRL_SHIFT 3
+#define MT6325_RG_VEFUSE_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VEFUSE_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VEFUSE_MODE_MASK 0x1
+#define MT6325_QI_VEFUSE_MODE_SHIFT 7
+#define MT6325_RG_VEFUSE_STBTD_MASK 0x3
+#define MT6325_RG_VEFUSE_STBTD_SHIFT 8
+#define MT6325_RG_VEFUSE_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VEFUSE_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VEFUSE_STB_MASK 0x1
+#define MT6325_QI_VEFUSE_STB_SHIFT 14
+#define MT6325_QI_VEFUSE_EN_MASK 0x1
+#define MT6325_QI_VEFUSE_EN_SHIFT 15
+#define MT6325_RG_VSIM1_MODE_SET_MASK 0x1
+#define MT6325_RG_VSIM1_MODE_SET_SHIFT 0
+#define MT6325_RG_VSIM1_EN_MASK 0x1
+#define MT6325_RG_VSIM1_EN_SHIFT 1
+#define MT6325_RG_VSIM1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VSIM1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VSIM1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VSIM1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VSIM1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VSIM1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VSIM1_MODE_MASK 0x1
+#define MT6325_QI_VSIM1_MODE_SHIFT 7
+#define MT6325_RG_VSIM1_STBTD_MASK 0x3
+#define MT6325_RG_VSIM1_STBTD_SHIFT 8
+#define MT6325_RG_VSIM1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VSIM1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VSIM1_STB_MASK 0x1
+#define MT6325_QI_VSIM1_STB_SHIFT 14
+#define MT6325_QI_VSIM1_EN_MASK 0x1
+#define MT6325_QI_VSIM1_EN_SHIFT 15
+#define MT6325_RG_VSIM2_MODE_SET_MASK 0x1
+#define MT6325_RG_VSIM2_MODE_SET_SHIFT 0
+#define MT6325_RG_VSIM2_EN_MASK 0x1
+#define MT6325_RG_VSIM2_EN_SHIFT 1
+#define MT6325_RG_VSIM2_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VSIM2_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VSIM2_ON_CTRL_MASK 0x1
+#define MT6325_RG_VSIM2_ON_CTRL_SHIFT 3
+#define MT6325_RG_VSIM2_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VSIM2_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VSIM2_MODE_MASK 0x1
+#define MT6325_QI_VSIM2_MODE_SHIFT 7
+#define MT6325_RG_VSIM2_STBTD_MASK 0x3
+#define MT6325_RG_VSIM2_STBTD_SHIFT 8
+#define MT6325_RG_VSIM2_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VSIM2_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VSIM2_STB_MASK 0x1
+#define MT6325_QI_VSIM2_STB_SHIFT 14
+#define MT6325_QI_VSIM2_EN_MASK 0x1
+#define MT6325_QI_VSIM2_EN_SHIFT 15
+#define MT6325_RG_VMIPI_MODE_SET_MASK 0x1
+#define MT6325_RG_VMIPI_MODE_SET_SHIFT 0
+#define MT6325_RG_VMIPI_EN_MASK 0x1
+#define MT6325_RG_VMIPI_EN_SHIFT 1
+#define MT6325_RG_VMIPI_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VMIPI_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VMIPI_ON_CTRL_MASK 0x1
+#define MT6325_RG_VMIPI_ON_CTRL_SHIFT 3
+#define MT6325_RG_VMIPI_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VMIPI_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VMIPI_MODE_MASK 0x1
+#define MT6325_QI_VMIPI_MODE_SHIFT 7
+#define MT6325_RG_VMIPI_STBTD_MASK 0x3
+#define MT6325_RG_VMIPI_STBTD_SHIFT 8
+#define MT6325_RG_VMIPI_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VMIPI_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VMIPI_STB_MASK 0x1
+#define MT6325_QI_VMIPI_STB_SHIFT 14
+#define MT6325_QI_VMIPI_EN_MASK 0x1
+#define MT6325_QI_VMIPI_EN_SHIFT 15
+#define MT6325_RG_VIBR_THER_SHEN_EN_MASK 0x1
+#define MT6325_RG_VIBR_THER_SHEN_EN_SHIFT 0
+#define MT6325_RG_VIBR_EN_MASK 0x1
+#define MT6325_RG_VIBR_EN_SHIFT 1
+#define MT6325_RG_VIBR_SW_MODE_MASK 0x1
+#define MT6325_RG_VIBR_SW_MODE_SHIFT 3
+#define MT6325_RG_VIBR_FR_ORI_MASK 0x3
+#define MT6325_RG_VIBR_FR_ORI_SHIFT 4
+#define MT6325_RG_VIBR_MST_TIME_MASK 0x3
+#define MT6325_RG_VIBR_MST_TIME_SHIFT 8
+#define MT6325_RG_VIBR_MID_STATE_MASK 0x3
+#define MT6325_RG_VIBR_MID_STATE_SHIFT 10
+#define MT6325_QI_VIBR_FR_MASK 0x3
+#define MT6325_QI_VIBR_FR_SHIFT 12
+#define MT6325_RG_VIBR_PWDB_MASK 0x1
+#define MT6325_RG_VIBR_PWDB_SHIFT 15
+#define MT6325_RG_VCN18_MODE_SET_MASK 0x1
+#define MT6325_RG_VCN18_MODE_SET_SHIFT 0
+#define MT6325_RG_VCN18_EN_MASK 0x1
+#define MT6325_RG_VCN18_EN_SHIFT 1
+#define MT6325_RG_VCN18_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCN18_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCN18_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCN18_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCN18_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCN18_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCN18_MODE_MASK 0x1
+#define MT6325_QI_VCN18_MODE_SHIFT 7
+#define MT6325_RG_VCN18_STBTD_MASK 0x3
+#define MT6325_RG_VCN18_STBTD_SHIFT 8
+#define MT6325_RG_VCN18_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCN18_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCN18_STB_MASK 0x1
+#define MT6325_QI_VCN18_STB_SHIFT 14
+#define MT6325_QI_VCN18_EN_MASK 0x1
+#define MT6325_QI_VCN18_EN_SHIFT 15
+#define MT6325_NI_VDIG18_VOSEL_MASK 0x7
+#define MT6325_NI_VDIG18_VOSEL_SHIFT 0
+#define MT6325_RG_VDIG18_SRCLKEN_SEL_MASK 0x3
+#define MT6325_RG_VDIG18_SRCLKEN_SEL_SHIFT 7
+#define MT6325_RG_VDIG18_SLEEP_VOSEL_MASK 0x7
+#define MT6325_RG_VDIG18_SLEEP_VOSEL_SHIFT 9
+#define MT6325_RG_VDIG18_VOSEL_MASK 0x7
+#define MT6325_RG_VDIG18_VOSEL_SHIFT 12
+#define MT6325_RG_VDIG18_VOSEL_CTRL_MASK 0x1
+#define MT6325_RG_VDIG18_VOSEL_CTRL_SHIFT 15
+#define MT6325_RG_VGP2_MODE_SET_MASK 0x1
+#define MT6325_RG_VGP2_MODE_SET_SHIFT 0
+#define MT6325_RG_VGP2_EN_MASK 0x1
+#define MT6325_RG_VGP2_EN_SHIFT 1
+#define MT6325_RG_VGP2_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VGP2_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VGP2_ON_CTRL_MASK 0x1
+#define MT6325_RG_VGP2_ON_CTRL_SHIFT 3
+#define MT6325_RG_VGP2_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VGP2_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VGP2_MODE_MASK 0x1
+#define MT6325_QI_VGP2_MODE_SHIFT 7
+#define MT6325_RG_VGP2_STBTD_MASK 0x3
+#define MT6325_RG_VGP2_STBTD_SHIFT 8
+#define MT6325_RG_VGP2_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VGP2_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VGP2_STB_MASK 0x1
+#define MT6325_QI_VGP2_STB_SHIFT 14
+#define MT6325_QI_VGP2_EN_MASK 0x1
+#define MT6325_QI_VGP2_EN_SHIFT 15
+#define MT6325_RG_VCAMD_MODE_SET_MASK 0x1
+#define MT6325_RG_VCAMD_MODE_SET_SHIFT 0
+#define MT6325_RG_VCAMD_EN_MASK 0x1
+#define MT6325_RG_VCAMD_EN_SHIFT 1
+#define MT6325_RG_VCAMD_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCAMD_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCAMD_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCAMD_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCAMD_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCAMD_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCAMD_MODE_MASK 0x1
+#define MT6325_QI_VCAMD_MODE_SHIFT 7
+#define MT6325_RG_VCAMD_STBTD_MASK 0x3
+#define MT6325_RG_VCAMD_STBTD_SHIFT 8
+#define MT6325_RG_VCAMD_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCAMD_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCAMD_STB_MASK 0x1
+#define MT6325_QI_VCAMD_STB_SHIFT 14
+#define MT6325_QI_VCAMD_EN_MASK 0x1
+#define MT6325_QI_VCAMD_EN_SHIFT 15
+#define MT6325_RG_VCAM_IO_MODE_SET_MASK 0x1
+#define MT6325_RG_VCAM_IO_MODE_SET_SHIFT 0
+#define MT6325_RG_VCAM_IO_EN_MASK 0x1
+#define MT6325_RG_VCAM_IO_EN_SHIFT 1
+#define MT6325_RG_VCAM_IO_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_IO_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCAM_IO_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_IO_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCAM_IO_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCAM_IO_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCAMIO_MODE_MASK 0x1
+#define MT6325_QI_VCAMIO_MODE_SHIFT 7
+#define MT6325_RG_VCAM_IO_STBTD_MASK 0x3
+#define MT6325_RG_VCAM_IO_STBTD_SHIFT 8
+#define MT6325_RG_VCAM_IO_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCAM_IO_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCAMIO_STB_MASK 0x1
+#define MT6325_QI_VCAMIO_STB_SHIFT 14
+#define MT6325_QI_VCAMIO_EN_MASK 0x1
+#define MT6325_QI_VCAMIO_EN_SHIFT 15
+#define MT6325_RG_VSRAM_DVFS1_MODE_SET_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_MODE_SET_SHIFT 0
+#define MT6325_RG_VSRAM_DVFS1_EN_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_EN_SHIFT 1
+#define MT6325_RG_VSRAM_DVFS1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VSRAM_DVFS1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VSRAM_DVFS1_MODE_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_MODE_SHIFT 7
+#define MT6325_RG_VSRAM_DVFS1_STBTD_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_STBTD_SHIFT 8
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VSRAM_DVFS1_STB_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_STB_SHIFT 14
+#define MT6325_QI_VSRAM_DVFS1_EN_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_EN_SHIFT 15
+#define MT6325_RG_VGP3_MODE_SET_MASK 0x1
+#define MT6325_RG_VGP3_MODE_SET_SHIFT 0
+#define MT6325_RG_VGP3_EN_MASK 0x1
+#define MT6325_RG_VGP3_EN_SHIFT 1
+#define MT6325_RG_VGP3_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VGP3_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VGP3_ON_CTRL_MASK 0x1
+#define MT6325_RG_VGP3_ON_CTRL_SHIFT 3
+#define MT6325_RG_VGP3_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VGP3_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VGP3_MODE_MASK 0x1
+#define MT6325_QI_VGP3_MODE_SHIFT 7
+#define MT6325_RG_VGP3_STBTD_MASK 0x3
+#define MT6325_RG_VGP3_STBTD_SHIFT 8
+#define MT6325_RG_VGP3_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VGP3_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VGP3_STB_MASK 0x1
+#define MT6325_QI_VGP3_STB_SHIFT 14
+#define MT6325_QI_VGP3_EN_MASK 0x1
+#define MT6325_QI_VGP3_EN_SHIFT 15
+#define MT6325_RG_VBIASN_MODE_SET_MASK 0x1
+#define MT6325_RG_VBIASN_MODE_SET_SHIFT 0
+#define MT6325_RG_VBIASN_EN_MASK 0x1
+#define MT6325_RG_VBIASN_EN_SHIFT 1
+#define MT6325_RG_VBIASN_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VBIASN_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VBIASN_ON_CTRL_MASK 0x1
+#define MT6325_RG_VBIASN_ON_CTRL_SHIFT 3
+#define MT6325_RG_VBIASN_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VBIASN_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VBIASN_MODE_MASK 0x1
+#define MT6325_QI_VBIASN_MODE_SHIFT 7
+#define MT6325_RG_VBIASN_STBTD_MASK 0x3
+#define MT6325_RG_VBIASN_STBTD_SHIFT 8
+#define MT6325_RG_VBIASN_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VBIASN_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VBIASN_STB_MASK 0x1
+#define MT6325_QI_VBIASN_STB_SHIFT 14
+#define MT6325_QI_VBIASN_EN_MASK 0x1
+#define MT6325_QI_VBIASN_EN_SHIFT 15
+#define MT6325_RG_VRTC_EN_MASK 0x1
+#define MT6325_RG_VRTC_EN_SHIFT 1
+#define MT6325_QI_VRTC_EN_MASK 0x1
+#define MT6325_QI_VRTC_EN_SHIFT 15
+#define MT6325_RG_VBIASN_DIS_SEL_MASK 0x3
+#define MT6325_RG_VBIASN_DIS_SEL_SHIFT 0
+#define MT6325_RG_VBIASN_TRANS_EN_MASK 0x1
+#define MT6325_RG_VBIASN_TRANS_EN_SHIFT 2
+#define MT6325_RG_VBIASN_TRANS_CTRL_MASK 0x3
+#define MT6325_RG_VBIASN_TRANS_CTRL_SHIFT 4
+#define MT6325_RG_VBIASN_TRANS_ONCE_MASK 0x1
+#define MT6325_RG_VBIASN_TRANS_ONCE_SHIFT 6
+#define MT6325_QI_VBIASN_CHR_MASK 0x1
+#define MT6325_QI_VBIASN_CHR_SHIFT 7
+#define MT6325_RG_VTCXO1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VTCXO1_NDIS_EN_SHIFT 0
+#define MT6325_RG_VTCXO1_CAL_MASK 0xF
+#define MT6325_RG_VTCXO1_CAL_SHIFT 4
+#define MT6325_RG_VTCXO0_NDIS_EN_MASK 0x1
+#define MT6325_RG_VTCXO0_NDIS_EN_SHIFT 8
+#define MT6325_RG_VTCXO0_CAL_MASK 0xF
+#define MT6325_RG_VTCXO0_CAL_SHIFT 12
+#define MT6325_RG_VBIF28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VBIF28_NDIS_EN_SHIFT 0
+#define MT6325_RG_VBIF28_CAL_MASK 0xF
+#define MT6325_RG_VBIF28_CAL_SHIFT 4
+#define MT6325_RG_VAUD28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VAUD28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VAUD28_SENSE_SEL_MASK 0x1
+#define MT6325_RG_VAUD28_SENSE_SEL_SHIFT 9
+#define MT6325_RG_VAUD28_CAL_MASK 0xF
+#define MT6325_RG_VAUD28_CAL_SHIFT 12
+#define MT6325_RG_VCAMA_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMA_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCAMA_VOSEL_MASK 0x3
+#define MT6325_RG_VCAMA_VOSEL_SHIFT 1
+#define MT6325_RG_VCAMA_CAL_MASK 0xF
+#define MT6325_RG_VCAMA_CAL_SHIFT 4
+#define MT6325_RG_VAUXA28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VAUXA28_SENSE_SEL_MASK 0x1
+#define MT6325_RG_VAUXA28_SENSE_SEL_SHIFT 9
+#define MT6325_RG_VAUXA28_CAL_MASK 0xF
+#define MT6325_RG_VAUXA28_CAL_SHIFT 12
+#define MT6325_RG_VCN33_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCN33_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCN33_VOSEL_MASK 0x3
+#define MT6325_RG_VCN33_VOSEL_SHIFT 1
+#define MT6325_RG_VCN33_CAL_MASK 0xF
+#define MT6325_RG_VCN33_CAL_SHIFT 4
+#define MT6325_RG_VCN28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCN28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VCN28_CAL_MASK 0xF
+#define MT6325_RG_VCN28_CAL_SHIFT 12
+#define MT6325_RG_VUSB33_NDIS_EN_MASK 0x1
+#define MT6325_RG_VUSB33_NDIS_EN_SHIFT 0
+#define MT6325_RG_VUSB33_CAL_MASK 0xF
+#define MT6325_RG_VUSB33_CAL_SHIFT 4
+#define MT6325_RG_VRF18_1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VRF18_1_NDIS_EN_SHIFT 8
+#define MT6325_RG_VRF18_1_VOSEL_MASK 0x3
+#define MT6325_RG_VRF18_1_VOSEL_SHIFT 9
+#define MT6325_RG_VRF18_1_CAL_MASK 0xF
+#define MT6325_RG_VRF18_1_CAL_SHIFT 12
+#define MT6325_RG_VMC_NDIS_EN_MASK 0x1
+#define MT6325_RG_VMC_NDIS_EN_SHIFT 0
+#define MT6325_RG_VMC_VOSEL_MASK 0x1
+#define MT6325_RG_VMC_VOSEL_SHIFT 1
+#define MT6325_RG_VMC_STB_CAL_MASK 0x1
+#define MT6325_RG_VMC_STB_CAL_SHIFT 2
+#define MT6325_RG_VMC_CAL_MASK 0xF
+#define MT6325_RG_VMC_CAL_SHIFT 4
+#define MT6325_RG_VMCH_NDIS_EN_MASK 0x1
+#define MT6325_RG_VMCH_NDIS_EN_SHIFT 8
+#define MT6325_RG_VMCH_VOSEL_MASK 0x1
+#define MT6325_RG_VMCH_VOSEL_SHIFT 9
+#define MT6325_RG_VMCH_DB_EN_MASK 0x1
+#define MT6325_RG_VMCH_DB_EN_SHIFT 10
+#define MT6325_RG_VMCH_STB_SEL_MASK 0x1
+#define MT6325_RG_VMCH_STB_SEL_SHIFT 11
+#define MT6325_RG_VMCH_CAL_MASK 0xF
+#define MT6325_RG_VMCH_CAL_SHIFT 12
+#define MT6325_RG_VEMC_3V3_STB_CAL_MASK 0x3
+#define MT6325_RG_VEMC_3V3_STB_CAL_SHIFT 4
+#define MT6325_RG_VEMC_3V3_NDIS_EN_MASK 0x1
+#define MT6325_RG_VEMC_3V3_NDIS_EN_SHIFT 8
+#define MT6325_RG_VEMC_3V3_VOSEL_MASK 0x1
+#define MT6325_RG_VEMC_3V3_VOSEL_SHIFT 9
+#define MT6325_RG_VEMC_3V3_DL_EN_MASK 0x1
+#define MT6325_RG_VEMC_3V3_DL_EN_SHIFT 10
+#define MT6325_RG_VEMC_3V3_CAL_MASK 0xF
+#define MT6325_RG_VEMC_3V3_CAL_SHIFT 12
+#define MT6325_RG_VCAMAF_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMAF_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCAMAF_VOSEL_MASK 0x7
+#define MT6325_RG_VCAMAF_VOSEL_SHIFT 1
+#define MT6325_RG_VCAMAF_CAL_MASK 0xF
+#define MT6325_RG_VCAMAF_CAL_SHIFT 4
+#define MT6325_RG_VIO28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VIO28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VIO28_CAL_MASK 0xF
+#define MT6325_RG_VIO28_CAL_SHIFT 12
+#define MT6325_RG_VGP2_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGP2_NDIS_EN_SHIFT 0
+#define MT6325_RG_VGP2_VOSEL_MASK 0x3
+#define MT6325_RG_VGP2_VOSEL_SHIFT 1
+#define MT6325_RG_VGP2_CAL_MASK 0xF
+#define MT6325_RG_VGP2_CAL_SHIFT 4
+#define MT6325_RG_VGP1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGP1_NDIS_EN_SHIFT 8
+#define MT6325_RG_VGP1_VOSEL_MASK 0x7
+#define MT6325_RG_VGP1_VOSEL_SHIFT 9
+#define MT6325_RG_VGP1_CAL_MASK 0xF
+#define MT6325_RG_VGP1_CAL_SHIFT 12
+#define MT6325_RG_VSIM2_NDIS_EN_MASK 0x1
+#define MT6325_RG_VSIM2_NDIS_EN_SHIFT 0
+#define MT6325_RG_VSIM2_VOSEL_MASK 0x7
+#define MT6325_RG_VSIM2_VOSEL_SHIFT 1
+#define MT6325_RG_VSIM2_CAL_MASK 0xF
+#define MT6325_RG_VSIM2_CAL_SHIFT 4
+#define MT6325_RG_VSIM1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VSIM1_NDIS_EN_SHIFT 8
+#define MT6325_RG_VSIM1_VOSEL_MASK 0x7
+#define MT6325_RG_VSIM1_VOSEL_SHIFT 9
+#define MT6325_RG_VSIM1_CAL_MASK 0xF
+#define MT6325_RG_VSIM1_CAL_SHIFT 12
+#define MT6325_RG_VIBR_VOSEL_MASK 0x7
+#define MT6325_RG_VIBR_VOSEL_SHIFT 1
+#define MT6325_RG_VIBR_VOCAL_MASK 0xF
+#define MT6325_RG_VIBR_VOCAL_SHIFT 4
+#define MT6325_RG_VMIPI_NDIS_EN_MASK 0x1
+#define MT6325_RG_VMIPI_NDIS_EN_SHIFT 8
+#define MT6325_RG_VMIPI_VOSEL_MASK 0x3
+#define MT6325_RG_VMIPI_VOSEL_SHIFT 9
+#define MT6325_RG_VMIPI_CAL_MASK 0xF
+#define MT6325_RG_VMIPI_CAL_SHIFT 12
+#define MT6325_RG_VEFUSE_NDIS_EN_MASK 0x1
+#define MT6325_RG_VEFUSE_NDIS_EN_SHIFT 0
+#define MT6325_RG_VEFUSE_VOSEL_MASK 0x7
+#define MT6325_RG_VEFUSE_VOSEL_SHIFT 1
+#define MT6325_RG_VEFUSE_CAL_MASK 0xF
+#define MT6325_RG_VEFUSE_CAL_SHIFT 4
+#define MT6325_RG_VCN18_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCN18_NDIS_EN_SHIFT 8
+#define MT6325_RG_VCN18_VOSEL_MASK 0x7
+#define MT6325_RG_VCN18_VOSEL_SHIFT 9
+#define MT6325_RG_VCN18_CAL_MASK 0xF
+#define MT6325_RG_VCN18_CAL_SHIFT 12
+#define MT6325_RG_VCAMD_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMD_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCAMD_VOSEL_MASK 0x7
+#define MT6325_RG_VCAMD_VOSEL_SHIFT 1
+#define MT6325_RG_VCAMD_CAL_MASK 0xF
+#define MT6325_RG_VCAMD_CAL_SHIFT 4
+#define MT6325_RG_VCAMIO_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMIO_NDIS_EN_SHIFT 8
+#define MT6325_RG_VCAMIO_VOSEL_MASK 0x7
+#define MT6325_RG_VCAMIO_VOSEL_SHIFT 9
+#define MT6325_RG_VCAMIO_CAL_MASK 0xF
+#define MT6325_RG_VCAMIO_CAL_SHIFT 12
+#define MT6325_RG_VSRAM_DVFS1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_NDIS_EN_SHIFT 0
+#define MT6325_RG_VSRAM_DVFS1_NDIS_PLCUR_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_NDIS_PLCUR_SHIFT 4
+#define MT6325_RG_VSRAM_DVFS1_VOSEL_MASK 0x7F
+#define MT6325_RG_VSRAM_DVFS1_VOSEL_SHIFT 9
+#define MT6325_RG_VBIASN_NDIS_EN_MASK 0x1
+#define MT6325_RG_VBIASN_NDIS_EN_SHIFT 0
+#define MT6325_RG_VBIASN_CAL_MASK 0xF
+#define MT6325_RG_VBIASN_CAL_SHIFT 4
+#define MT6325_RG_VGP3_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGP3_NDIS_EN_SHIFT 8
+#define MT6325_RG_VGP3_VOSEL_MASK 0x7
+#define MT6325_RG_VGP3_VOSEL_SHIFT 9
+#define MT6325_RG_VGP3_CAL_MASK 0xF
+#define MT6325_RG_VGP3_CAL_SHIFT 12
+#define MT6325_RG_VBIASN_VOSEL_MASK 0x1F
+#define MT6325_RG_VBIASN_VOSEL_SHIFT 11
+#define MT6325_RG_DLDO_1_RSV_L_MASK 0x1F
+#define MT6325_RG_DLDO_1_RSV_L_SHIFT 0
+#define MT6325_RG_LDO_RSV0_MASK 0x3F
+#define MT6325_RG_LDO_RSV0_SHIFT 5
+#define MT6325_RG_DLDO_1_RSV_H_MASK 0x1F
+#define MT6325_RG_DLDO_1_RSV_H_SHIFT 11
+#define MT6325_RG_DLDO_2_RSV_L_MASK 0x1F
+#define MT6325_RG_DLDO_2_RSV_L_SHIFT 0
+#define MT6325_RG_LDO_RSV1_MASK 0x3F
+#define MT6325_RG_LDO_RSV1_SHIFT 5
+#define MT6325_RG_DLDO_2_RSV_H_MASK 0x1F
+#define MT6325_RG_DLDO_2_RSV_H_SHIFT 11
+#define MT6325_RG_LDO_RSV3_MASK 0xFF
+#define MT6325_RG_LDO_RSV3_SHIFT 0
+#define MT6325_RG_SYSLDO_RSVL_MASK 0x7
+#define MT6325_RG_SYSLDO_RSVL_SHIFT 8
+#define MT6325_RG_SYSLDO_RSV_H_MASK 0x7
+#define MT6325_RG_SYSLDO_RSV_H_SHIFT 12
+#define MT6325_RG_ADLDO_RSV_L_MASK 0x1F
+#define MT6325_RG_ADLDO_RSV_L_SHIFT 0
+#define MT6325_RG_LDO_RSV2_MASK 0x3F
+#define MT6325_RG_LDO_RSV2_SHIFT 5
+#define MT6325_RG_ADLDO_RSV_H_MASK 0x1F
+#define MT6325_RG_ADLDO_RSV_H_SHIFT 11
+#define MT6325_RG_VMC_OCFB_EN_MASK 0x1
+#define MT6325_RG_VMC_OCFB_EN_SHIFT 0
+#define MT6325_RG_VIO28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VIO28_OCFB_EN_SHIFT 1
+#define MT6325_RG_VEMC33_OCFB_EN_MASK 0x1
+#define MT6325_RG_VEMC33_OCFB_EN_SHIFT 2
+#define MT6325_RG_VMCH_OCFB_EN_MASK 0x1
+#define MT6325_RG_VMCH_OCFB_EN_SHIFT 3
+#define MT6325_RG_VUSB33_OCFB_EN_MASK 0x1
+#define MT6325_RG_VUSB33_OCFB_EN_SHIFT 4
+#define MT6325_RG_VRF18_1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VRF18_1_OCFB_EN_SHIFT 5
+#define MT6325_RG_VCN33_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCN33_OCFB_EN_SHIFT 6
+#define MT6325_RG_VCN28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCN28_OCFB_EN_SHIFT 7
+#define MT6325_RG_VCAMA_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAMA_OCFB_EN_SHIFT 8
+#define MT6325_RG_VAUXA28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_OCFB_EN_SHIFT 9
+#define MT6325_RG_VBIF28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VBIF28_OCFB_EN_SHIFT 10
+#define MT6325_RG_VAUD28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VAUD28_OCFB_EN_SHIFT 11
+#define MT6325_RG_VTCXO1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VTCXO1_OCFB_EN_SHIFT 12
+#define MT6325_RG_VTCXO0_OCFB_EN_MASK 0x1
+#define MT6325_RG_VTCXO0_OCFB_EN_SHIFT 13
+#define MT6325_LDO_DEGTD_SEL_MASK 0x3
+#define MT6325_LDO_DEGTD_SEL_SHIFT 14
+#define MT6325_RG_VBIASN_OCFB_EN_MASK 0x1
+#define MT6325_RG_VBIASN_OCFB_EN_SHIFT 1
+#define MT6325_RG_VGP3_OCFB_EN_MASK 0x1
+#define MT6325_RG_VGP3_OCFB_EN_SHIFT 2
+#define MT6325_RG_VSRAM_DVFS1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_OCFB_EN_SHIFT 3
+#define MT6325_RG_VCAM_IO_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAM_IO_OCFB_EN_SHIFT 4
+#define MT6325_RG_VCAMD_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAMD_OCFB_EN_SHIFT 5
+#define MT6325_RG_VGP2_OCFB_EN_MASK 0x1
+#define MT6325_RG_VGP2_OCFB_EN_SHIFT 6
+#define MT6325_RG_VCN18_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCN18_OCFB_EN_SHIFT 7
+#define MT6325_RG_VMIPI_OCFB_EN_MASK 0x1
+#define MT6325_RG_VMIPI_OCFB_EN_SHIFT 8
+#define MT6325_RG_VSIM2_OCFB_EN_MASK 0x1
+#define MT6325_RG_VSIM2_OCFB_EN_SHIFT 9
+#define MT6325_RG_VSIM1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VSIM1_OCFB_EN_SHIFT 10
+#define MT6325_RG_VEFUSE_OCFB_EN_MASK 0x1
+#define MT6325_RG_VEFUSE_OCFB_EN_SHIFT 11
+#define MT6325_RG_VGP1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VGP1_OCFB_EN_SHIFT 12
+#define MT6325_RG_VCAM_AF_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAM_AF_OCFB_EN_SHIFT 13
+#define MT6325_QI_VMC_OCFB_EN_MASK 0x1
+#define MT6325_QI_VMC_OCFB_EN_SHIFT 0
+#define MT6325_QI_VIO28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VIO28_OCFB_EN_SHIFT 1
+#define MT6325_QI_VEMC_3V3_OCFB_EN_MASK 0x1
+#define MT6325_QI_VEMC_3V3_OCFB_EN_SHIFT 2
+#define MT6325_QI_VMCH_OCFB_EN_MASK 0x1
+#define MT6325_QI_VMCH_OCFB_EN_SHIFT 3
+#define MT6325_QI_VUSB33_OCFB_EN_MASK 0x1
+#define MT6325_QI_VUSB33_OCFB_EN_SHIFT 4
+#define MT6325_QI_VRF18_1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VRF18_1_OCFB_EN_SHIFT 5
+#define MT6325_QI_VCN33_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCN33_OCFB_EN_SHIFT 6
+#define MT6325_QI_VCN28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCN28_OCFB_EN_SHIFT 7
+#define MT6325_QI_VCAMA_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMA_OCFB_EN_SHIFT 8
+#define MT6325_QI_VAUXA28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VAUXA28_OCFB_EN_SHIFT 9
+#define MT6325_QI_VBIF28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VBIF28_OCFB_EN_SHIFT 10
+#define MT6325_QI_VAUD28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VAUD28_OCFB_EN_SHIFT 11
+#define MT6325_QI_VTCXO1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VTCXO1_OCFB_EN_SHIFT 12
+#define MT6325_QI_VTCXO0_OCFB_EN_MASK 0x1
+#define MT6325_QI_VTCXO0_OCFB_EN_SHIFT 13
+#define MT6325_QI_VBIASN_OCFB_EN_MASK 0x1
+#define MT6325_QI_VBIASN_OCFB_EN_SHIFT 1
+#define MT6325_QI_VGP3_OCFB_EN_MASK 0x1
+#define MT6325_QI_VGP3_OCFB_EN_SHIFT 2
+#define MT6325_QI_VSRAM_DVFS1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_OCFB_EN_SHIFT 3
+#define MT6325_QI_VCAMIO_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMIO_OCFB_EN_SHIFT 4
+#define MT6325_QI_VCAMD_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMD_OCFB_EN_SHIFT 5
+#define MT6325_QI_VGP2_OCFB_EN_MASK 0x1
+#define MT6325_QI_VGP2_OCFB_EN_SHIFT 6
+#define MT6325_QI_VCN18_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCN18_OCFB_EN_SHIFT 7
+#define MT6325_QI_VMIPI_OCFB_EN_MASK 0x1
+#define MT6325_QI_VMIPI_OCFB_EN_SHIFT 8
+#define MT6325_QI_VSIM2_OCFB_EN_MASK 0x1
+#define MT6325_QI_VSIM2_OCFB_EN_SHIFT 9
+#define MT6325_QI_VSIM1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VSIM1_OCFB_EN_SHIFT 10
+#define MT6325_QI_VEFUSE_OCFB_EN_MASK 0x1
+#define MT6325_QI_VEFUSE_OCFB_EN_SHIFT 11
+#define MT6325_QI_VGP1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VGP1_OCFB_EN_SHIFT 12
+#define MT6325_QI_VCAMAF_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMAF_OCFB_EN_SHIFT 13
+#define MT6325_RG_VCAMIO_EN_MASK 0x1
+#define MT6325_RG_VCAMIO_EN_SHIFT 0
+#define MT6325_RG_VCAMAF_EN_MASK 0x1
+#define MT6325_RG_VCAMAF_EN_SHIFT 1
+#define MT6325_BIF_COMMAND_0_MASK 0x7FF
+#define MT6325_BIF_COMMAND_0_SHIFT 0
+#define MT6325_BIF_COMMAND_1_MASK 0x7FF
+#define MT6325_BIF_COMMAND_1_SHIFT 0
+#define MT6325_BIF_COMMAND_2_MASK 0x7FF
+#define MT6325_BIF_COMMAND_2_SHIFT 0
+#define MT6325_BIF_COMMAND_3_MASK 0x7FF
+#define MT6325_BIF_COMMAND_3_SHIFT 0
+#define MT6325_BIF_COMMAND_4_MASK 0x7FF
+#define MT6325_BIF_COMMAND_4_SHIFT 0
+#define MT6325_BIF_COMMAND_5_MASK 0x7FF
+#define MT6325_BIF_COMMAND_5_SHIFT 0
+#define MT6325_BIF_COMMAND_6_MASK 0x7FF
+#define MT6325_BIF_COMMAND_6_SHIFT 0
+#define MT6325_BIF_COMMAND_7_MASK 0x7FF
+#define MT6325_BIF_COMMAND_7_SHIFT 0
+#define MT6325_BIF_COMMAND_8_MASK 0x7FF
+#define MT6325_BIF_COMMAND_8_SHIFT 0
+#define MT6325_BIF_COMMAND_9_MASK 0x7FF
+#define MT6325_BIF_COMMAND_9_SHIFT 0
+#define MT6325_BIF_COMMAND_10_MASK 0x7FF
+#define MT6325_BIF_COMMAND_10_SHIFT 0
+#define MT6325_BIF_COMMAND_11_MASK 0x7FF
+#define MT6325_BIF_COMMAND_11_SHIFT 0
+#define MT6325_BIF_COMMAND_12_MASK 0x7FF
+#define MT6325_BIF_COMMAND_12_SHIFT 0
+#define MT6325_BIF_COMMAND_13_MASK 0x7FF
+#define MT6325_BIF_COMMAND_13_SHIFT 0
+#define MT6325_BIF_COMMAND_14_MASK 0x7FF
+#define MT6325_BIF_COMMAND_14_SHIFT 0
+#define MT6325_BIF_RSV_MASK 0x7F
+#define MT6325_BIF_RSV_SHIFT 0
+#define MT6325_BIF_COMMAND_TYPE_MASK 0x3
+#define MT6325_BIF_COMMAND_TYPE_SHIFT 8
+#define MT6325_BIF_TRASFER_NUM_MASK 0xF
+#define MT6325_BIF_TRASFER_NUM_SHIFT 12
+#define MT6325_BIF_LOGIC_0_SET_MASK 0xF
+#define MT6325_BIF_LOGIC_0_SET_SHIFT 0
+#define MT6325_BIF_LOGIC_1_SET_MASK 0x1F
+#define MT6325_BIF_LOGIC_1_SET_SHIFT 4
+#define MT6325_BIF_STOP_SET_MASK 0x3F
+#define MT6325_BIF_STOP_SET_SHIFT 10
+#define MT6325_BIF_DEBOUNCE_WND_MASK 0x3
+#define MT6325_BIF_DEBOUNCE_WND_SHIFT 0
+#define MT6325_BIF_DEBOUNCE_THD_MASK 0x3
+#define MT6325_BIF_DEBOUNCE_THD_SHIFT 2
+#define MT6325_BIF_DEBOUNCE_EN_MASK 0x1
+#define MT6325_BIF_DEBOUNCE_EN_SHIFT 4
+#define MT6325_BIF_READ_EXPECT_NUM_MASK 0xF
+#define MT6325_BIF_READ_EXPECT_NUM_SHIFT 12
+#define MT6325_BIF_TRASACT_TRIGGER_MASK 0x1
+#define MT6325_BIF_TRASACT_TRIGGER_SHIFT 0
+#define MT6325_BIF_DATA_NUM_MASK 0xF
+#define MT6325_BIF_DATA_NUM_SHIFT 0
+#define MT6325_BIF_RESPONSE_MASK 0x1
+#define MT6325_BIF_RESPONSE_SHIFT 12
+#define MT6325_BIF_DATA_0_MASK 0xFF
+#define MT6325_BIF_DATA_0_SHIFT 0
+#define MT6325_BIF_ACK_0_MASK 0x1
+#define MT6325_BIF_ACK_0_SHIFT 8
+#define MT6325_BIF_ERROR_0_MASK 0x1
+#define MT6325_BIF_ERROR_0_SHIFT 15
+#define MT6325_BIF_DATA_1_MASK 0xFF
+#define MT6325_BIF_DATA_1_SHIFT 0
+#define MT6325_BIF_ACK_1_MASK 0x1
+#define MT6325_BIF_ACK_1_SHIFT 8
+#define MT6325_BIF_ERROR_1_MASK 0x1
+#define MT6325_BIF_ERROR_1_SHIFT 15
+#define MT6325_BIF_DATA_2_MASK 0xFF
+#define MT6325_BIF_DATA_2_SHIFT 0
+#define MT6325_BIF_ACK_2_MASK 0x1
+#define MT6325_BIF_ACK_2_SHIFT 8
+#define MT6325_BIF_ERROR_2_MASK 0x1
+#define MT6325_BIF_ERROR_2_SHIFT 15
+#define MT6325_BIF_DATA_3_MASK 0xFF
+#define MT6325_BIF_DATA_3_SHIFT 0
+#define MT6325_BIF_ACK_3_MASK 0x1
+#define MT6325_BIF_ACK_3_SHIFT 8
+#define MT6325_BIF_ERROR_3_MASK 0x1
+#define MT6325_BIF_ERROR_3_SHIFT 15
+#define MT6325_BIF_DATA_4_MASK 0xFF
+#define MT6325_BIF_DATA_4_SHIFT 0
+#define MT6325_BIF_ACK_4_MASK 0x1
+#define MT6325_BIF_ACK_4_SHIFT 8
+#define MT6325_BIF_ERROR_4_MASK 0x1
+#define MT6325_BIF_ERROR_4_SHIFT 15
+#define MT6325_BIF_DATA_5_MASK 0xFF
+#define MT6325_BIF_DATA_5_SHIFT 0
+#define MT6325_BIF_ACK_5_MASK 0x1
+#define MT6325_BIF_ACK_5_SHIFT 8
+#define MT6325_BIF_ERROR_5_MASK 0x1
+#define MT6325_BIF_ERROR_5_SHIFT 15
+#define MT6325_BIF_DATA_6_MASK 0xFF
+#define MT6325_BIF_DATA_6_SHIFT 0
+#define MT6325_BIF_ACK_6_MASK 0x1
+#define MT6325_BIF_ACK_6_SHIFT 8
+#define MT6325_BIF_ERROR_6_MASK 0x1
+#define MT6325_BIF_ERROR_6_SHIFT 15
+#define MT6325_BIF_DATA_7_MASK 0xFF
+#define MT6325_BIF_DATA_7_SHIFT 0
+#define MT6325_BIF_ACK_7_MASK 0x1
+#define MT6325_BIF_ACK_7_SHIFT 8
+#define MT6325_BIF_ERROR_7_MASK 0x1
+#define MT6325_BIF_ERROR_7_SHIFT 15
+#define MT6325_BIF_DATA_8_MASK 0xFF
+#define MT6325_BIF_DATA_8_SHIFT 0
+#define MT6325_BIF_ACK_8_MASK 0x1
+#define MT6325_BIF_ACK_8_SHIFT 8
+#define MT6325_BIF_ERROR_8_MASK 0x1
+#define MT6325_BIF_ERROR_8_SHIFT 15
+#define MT6325_BIF_DATA_9_MASK 0xFF
+#define MT6325_BIF_DATA_9_SHIFT 0
+#define MT6325_BIF_ACK_9_MASK 0x1
+#define MT6325_BIF_ACK_9_SHIFT 8
+#define MT6325_BIF_ERROR_9_MASK 0x1
+#define MT6325_BIF_ERROR_9_SHIFT 15
+#define MT6325_BIF_TEST_MODE0_MASK 0x1
+#define MT6325_BIF_TEST_MODE0_SHIFT 0
+#define MT6325_BIF_TEST_MODE1_MASK 0x1
+#define MT6325_BIF_TEST_MODE1_SHIFT 1
+#define MT6325_BIF_TEST_MODE2_MASK 0x1
+#define MT6325_BIF_TEST_MODE2_SHIFT 2
+#define MT6325_BIF_TEST_MODE3_MASK 0x1
+#define MT6325_BIF_TEST_MODE3_SHIFT 3
+#define MT6325_BIF_TEST_MODE4_MASK 0x1
+#define MT6325_BIF_TEST_MODE4_SHIFT 4
+#define MT6325_BIF_TEST_MODE5_MASK 0x1
+#define MT6325_BIF_TEST_MODE5_SHIFT 5
+#define MT6325_BIF_TEST_MODE6_MASK 0x1
+#define MT6325_BIF_TEST_MODE6_SHIFT 6
+#define MT6325_BIF_TEST_MODE7_MASK 0x1
+#define MT6325_BIF_TEST_MODE7_SHIFT 7
+#define MT6325_BIF_TEST_MODE8_MASK 0x1
+#define MT6325_BIF_TEST_MODE8_SHIFT 8
+#define MT6325_BIF_BAT_LOST_SW_MASK 0x1
+#define MT6325_BIF_BAT_LOST_SW_SHIFT 11
+#define MT6325_BIF_RX_DATA_SW_MASK 0x1
+#define MT6325_BIF_RX_DATA_SW_SHIFT 12
+#define MT6325_BIF_TX_DATA_SW_MASK 0x1
+#define MT6325_BIF_TX_DATA_SW_SHIFT 13
+#define MT6325_BIF_RX_EN_SW_MASK 0x1
+#define MT6325_BIF_RX_EN_SW_SHIFT 14
+#define MT6325_BIF_TX_EN_SW_MASK 0x1
+#define MT6325_BIF_TX_EN_SW_SHIFT 15
+#define MT6325_BIF_BACK_NORMAL_MASK 0x1
+#define MT6325_BIF_BACK_NORMAL_SHIFT 0
+#define MT6325_BIF_IRQ_CLR_MASK 0x1
+#define MT6325_BIF_IRQ_CLR_SHIFT 1
+#define MT6325_BIF_BAT_LOST_GATED_MASK 0x1
+#define MT6325_BIF_BAT_LOST_GATED_SHIFT 10
+#define MT6325_BIF_IRQ_MASK 0x1
+#define MT6325_BIF_IRQ_SHIFT 11
+#define MT6325_BIF_TIMEOUT_MASK 0x1
+#define MT6325_BIF_TIMEOUT_SHIFT 12
+#define MT6325_BIF_BAT_LOST_MASK 0x1
+#define MT6325_BIF_BAT_LOST_SHIFT 13
+#define MT6325_BIF_TOTAL_VALID_MASK 0x1
+#define MT6325_BIF_TOTAL_VALID_SHIFT 14
+#define MT6325_BIF_BUS_STATUS_MASK 0x1
+#define MT6325_BIF_BUS_STATUS_SHIFT 15
+#define MT6325_BIF_POWER_UP_COUNT_MASK 0x1F
+#define MT6325_BIF_POWER_UP_COUNT_SHIFT 0
+#define MT6325_BIF_POWER_UP_MASK 0x1
+#define MT6325_BIF_POWER_UP_SHIFT 15
+#define MT6325_BIF_RX_ERROR_UNKNOW_MASK 0x1
+#define MT6325_BIF_RX_ERROR_UNKNOW_SHIFT 2
+#define MT6325_BIF_RX_ERROR_INSUFF_MASK 0x1
+#define MT6325_BIF_RX_ERROR_INSUFF_SHIFT 3
+#define MT6325_BIF_RX_ERROR_LOWPHASE_MASK 0x1
+#define MT6325_BIF_RX_ERROR_LOWPHASE_SHIFT 4
+#define MT6325_BIF_RX_STATE_MASK 0x7
+#define MT6325_BIF_RX_STATE_SHIFT 5
+#define MT6325_BIF_FLOW_CTL_STATE_MASK 0x3
+#define MT6325_BIF_FLOW_CTL_STATE_SHIFT 8
+#define MT6325_BIF_TX_STATE_MASK 0x3
+#define MT6325_BIF_TX_STATE_SHIFT 10
+#define MT6325_QI_BIF_RX_DATA_MASK 0x1
+#define MT6325_QI_BIF_RX_DATA_SHIFT 12
+#define MT6325_QI_BIF_RX_EN_MASK 0x1
+#define MT6325_QI_BIF_RX_EN_SHIFT 13
+#define MT6325_QI_BIF_TX_DATA_MASK 0x1
+#define MT6325_QI_BIF_TX_DATA_SHIFT 14
+#define MT6325_QI_BIF_TX_EN_MASK 0x1
+#define MT6325_QI_BIF_TX_EN_SHIFT 15
+#define MT6325_BIF_TX_DATA_FIANL_MASK 0xFFFF
+#define MT6325_BIF_TX_DATA_FIANL_SHIFT 0
+#define MT6325_BIF_RX_DATA_SAMPLING_MASK 0xFFFF
+#define MT6325_BIF_RX_DATA_SAMPLING_SHIFT 0
+#define MT6325_BIF_RX_DATA_RECOVERY_MASK 0x3FFF
+#define MT6325_BIF_RX_DATA_RECOVERY_SHIFT 0
+#define MT6325_RG_BATON_HT_EN_MASK 0x1
+#define MT6325_RG_BATON_HT_EN_SHIFT 0
+#define MT6325_RG_BATON_TDET_EN_MASK 0x1
+#define MT6325_RG_BATON_TDET_EN_SHIFT 2
+#define MT6325_RG_VBIF28_AUXADC_EN_MASK 0x1
+#define MT6325_RG_VBIF28_AUXADC_EN_SHIFT 3
+#define MT6325_RG_BATON_HT_EN_DLY_TIME_MASK 0x1
+#define MT6325_RG_BATON_HT_EN_DLY_TIME_SHIFT 4
+#define MT6325_QI_BATON_HT_EN_MASK 0x1
+#define MT6325_QI_BATON_HT_EN_SHIFT 5
+#define MT6325_RGS_BATON_HV_MASK 0x1
+#define MT6325_RGS_BATON_HV_SHIFT 6
+#define MT6325_RG_BATON_HT_TRIM_RSV0_MASK 0x7
+#define MT6325_RG_BATON_HT_TRIM_RSV0_SHIFT 8
+#define MT6325_RG_HW_VTH_CTRL_MASK 0x1
+#define MT6325_RG_HW_VTH_CTRL_SHIFT 11
+#define MT6325_RG_HW_VTH2_MASK 0x3
+#define MT6325_RG_HW_VTH2_SHIFT 12
+#define MT6325_RG_HW_VTH1_MASK 0x3
+#define MT6325_RG_HW_VTH1_SHIFT 14
+#define MT6325_BIF_TIMEOUT_SET_MASK 0xFFFF
+#define MT6325_BIF_TIMEOUT_SET_SHIFT 0
+#define MT6325_BIF_RX_DEG_WND_MASK 0x3FF
+#define MT6325_BIF_RX_DEG_WND_SHIFT 0
+#define MT6325_BIF_RX_DEG_EN_MASK 0x1
+#define MT6325_BIF_RX_DEG_EN_SHIFT 15
+#define MT6325_BIF_RSV1_MASK 0xFF
+#define MT6325_BIF_RSV1_SHIFT 0
+#define MT6325_BIF_RSV0_MASK 0xFF
+#define MT6325_BIF_RSV0_SHIFT 8
+#define MT6325_SPK_EN_L_MASK 0x1
+#define MT6325_SPK_EN_L_SHIFT 0
+#define MT6325_SPKMODE_L_MASK 0x1
+#define MT6325_SPKMODE_L_SHIFT 2
+#define MT6325_SPK_TRIM_EN_L_MASK 0x1
+#define MT6325_SPK_TRIM_EN_L_SHIFT 3
+#define MT6325_SPK_OC_SHDN_DL_MASK 0x1
+#define MT6325_SPK_OC_SHDN_DL_SHIFT 8
+#define MT6325_SPK_THER_SHDN_L_EN_MASK 0x1
+#define MT6325_SPK_THER_SHDN_L_EN_SHIFT 9
+#define MT6325_SPK_OUT_STAGE_SEL_MASK 0x1
+#define MT6325_SPK_OUT_STAGE_SEL_SHIFT 10
+#define MT6325_RG_SPK_GAINL_MASK 0x3
+#define MT6325_RG_SPK_GAINL_SHIFT 12
+#define MT6325_DA_SPK_OFFSET_L_MASK 0x1F
+#define MT6325_DA_SPK_OFFSET_L_SHIFT 0
+#define MT6325_DA_SPK_LEAD_DGLH_L_MASK 0x1
+#define MT6325_DA_SPK_LEAD_DGLH_L_SHIFT 5
+#define MT6325_NI_SPK_LEAD_L_MASK 0x1
+#define MT6325_NI_SPK_LEAD_L_SHIFT 6
+#define MT6325_SPK_OFFSET_L_OV_MASK 0x1
+#define MT6325_SPK_OFFSET_L_OV_SHIFT 7
+#define MT6325_SPK_OFFSET_L_SW_MASK 0x1F
+#define MT6325_SPK_OFFSET_L_SW_SHIFT 8
+#define MT6325_SPK_LEAD_L_SW_MASK 0x1
+#define MT6325_SPK_LEAD_L_SW_SHIFT 13
+#define MT6325_SPK_OFFSET_L_MODE_MASK 0x1
+#define MT6325_SPK_OFFSET_L_MODE_SHIFT 14
+#define MT6325_SPK_TRIM_DONE_L_MASK 0x1
+#define MT6325_SPK_TRIM_DONE_L_SHIFT 15
+#define MT6325_RG_SPK_INTG_RST_L_MASK 0x1
+#define MT6325_RG_SPK_INTG_RST_L_SHIFT 0
+#define MT6325_RG_SPK_FORCE_EN_L_MASK 0x1
+#define MT6325_RG_SPK_FORCE_EN_L_SHIFT 1
+#define MT6325_RG_SPK_SLEW_L_MASK 0x3
+#define MT6325_RG_SPK_SLEW_L_SHIFT 2
+#define MT6325_RG_SPKAB_OBIAS_L_MASK 0x3
+#define MT6325_RG_SPKAB_OBIAS_L_SHIFT 4
+#define MT6325_RG_SPKRCV_EN_L_MASK 0x1
+#define MT6325_RG_SPKRCV_EN_L_SHIFT 6
+#define MT6325_RG_SPK_DRC_EN_L_MASK 0x1
+#define MT6325_RG_SPK_DRC_EN_L_SHIFT 7
+#define MT6325_RG_SPK_TEST_EN_L_MASK 0x1
+#define MT6325_RG_SPK_TEST_EN_L_SHIFT 8
+#define MT6325_RG_SPKAB_OC_EN_L_MASK 0x1
+#define MT6325_RG_SPKAB_OC_EN_L_SHIFT 9
+#define MT6325_RG_SPK_OC_EN_L_MASK 0x1
+#define MT6325_RG_SPK_OC_EN_L_SHIFT 10
+#define MT6325_SPK_EN_R_MASK 0x1
+#define MT6325_SPK_EN_R_SHIFT 0
+#define MT6325_SPKMODE_R_MASK 0x1
+#define MT6325_SPKMODE_R_SHIFT 2
+#define MT6325_SPK_TRIM_EN_R_MASK 0x1
+#define MT6325_SPK_TRIM_EN_R_SHIFT 3
+#define MT6325_SPK_OC_SHDN_DR_MASK 0x1
+#define MT6325_SPK_OC_SHDN_DR_SHIFT 8
+#define MT6325_SPK_THER_SHDN_R_EN_MASK 0x1
+#define MT6325_SPK_THER_SHDN_R_EN_SHIFT 9
+#define MT6325_RG_SPK_GAINR_MASK 0x3
+#define MT6325_RG_SPK_GAINR_SHIFT 12
+#define MT6325_DA_SPK_OFFSET_R_MASK 0x1F
+#define MT6325_DA_SPK_OFFSET_R_SHIFT 0
+#define MT6325_DA_SPK_LEAD_DGLH_R_MASK 0x1
+#define MT6325_DA_SPK_LEAD_DGLH_R_SHIFT 5
+#define MT6325_NI_SPK_LEAD_R_MASK 0x1
+#define MT6325_NI_SPK_LEAD_R_SHIFT 6
+#define MT6325_SPK_OFFSET_R_OV_MASK 0x1
+#define MT6325_SPK_OFFSET_R_OV_SHIFT 7
+#define MT6325_SPK_OFFSET_R_SW_MASK 0x1F
+#define MT6325_SPK_OFFSET_R_SW_SHIFT 8
+#define MT6325_SPK_LEAD_R_SW_MASK 0x1
+#define MT6325_SPK_LEAD_R_SW_SHIFT 13
+#define MT6325_SPK_OFFSET_R_MODE_MASK 0x1
+#define MT6325_SPK_OFFSET_R_MODE_SHIFT 14
+#define MT6325_SPK_TRIM_DONE_R_MASK 0x1
+#define MT6325_SPK_TRIM_DONE_R_SHIFT 15
+#define MT6325_RG_SPK_INTG_RST_R_MASK 0x1
+#define MT6325_RG_SPK_INTG_RST_R_SHIFT 0
+#define MT6325_RG_SPK_FORCE_EN_R_MASK 0x1
+#define MT6325_RG_SPK_FORCE_EN_R_SHIFT 1
+#define MT6325_RG_SPK_SLEW_R_MASK 0x3
+#define MT6325_RG_SPK_SLEW_R_SHIFT 2
+#define MT6325_RG_SPKAB_OBIAS_R_MASK 0x3
+#define MT6325_RG_SPKAB_OBIAS_R_SHIFT 4
+#define MT6325_RG_SPKRCV_EN_R_MASK 0x1
+#define MT6325_RG_SPKRCV_EN_R_SHIFT 6
+#define MT6325_RG_SPK_DRC_EN_R_MASK 0x1
+#define MT6325_RG_SPK_DRC_EN_R_SHIFT 7
+#define MT6325_RG_SPK_TEST_EN_R_MASK 0x1
+#define MT6325_RG_SPK_TEST_EN_R_SHIFT 8
+#define MT6325_RG_SPKAB_OC_EN_R_MASK 0x1
+#define MT6325_RG_SPKAB_OC_EN_R_SHIFT 9
+#define MT6325_RG_SPK_OC_EN_R_MASK 0x1
+#define MT6325_RG_SPK_OC_EN_R_SHIFT 10
+#define MT6325_RG_SPKPGA_GAINR_MASK 0xF
+#define MT6325_RG_SPKPGA_GAINR_SHIFT 11
+#define MT6325_SPK_TRIM_WND_MASK 0x7
+#define MT6325_SPK_TRIM_WND_SHIFT 0
+#define MT6325_SPK_TRIM_THD_MASK 0x3
+#define MT6325_SPK_TRIM_THD_SHIFT 4
+#define MT6325_SPK_OC_WND_MASK 0x3
+#define MT6325_SPK_OC_WND_SHIFT 8
+#define MT6325_SPK_OC_THD_MASK 0x3
+#define MT6325_SPK_OC_THD_SHIFT 10
+#define MT6325_SPK_D_OC_R_DEG_MASK 0x1
+#define MT6325_SPK_D_OC_R_DEG_SHIFT 12
+#define MT6325_SPK_AB_OC_R_DEG_MASK 0x1
+#define MT6325_SPK_AB_OC_R_DEG_SHIFT 13
+#define MT6325_SPK_D_OC_L_DEG_MASK 0x1
+#define MT6325_SPK_D_OC_L_DEG_SHIFT 14
+#define MT6325_SPK_AB_OC_L_DEG_MASK 0x1
+#define MT6325_SPK_AB_OC_L_DEG_SHIFT 15
+#define MT6325_SPK_TD1_MASK 0xF
+#define MT6325_SPK_TD1_SHIFT 0
+#define MT6325_SPK_TD2_MASK 0xF
+#define MT6325_SPK_TD2_SHIFT 4
+#define MT6325_SPK_TD3_MASK 0xF
+#define MT6325_SPK_TD3_SHIFT 8
+#define MT6325_SPK_TRIM_DIV_MASK 0x7
+#define MT6325_SPK_TRIM_DIV_SHIFT 12
+#define MT6325_RG_BTL_SET_MASK 0x3
+#define MT6325_RG_BTL_SET_SHIFT 0
+#define MT6325_RG_SPK_IBIAS_SEL_MASK 0x3
+#define MT6325_RG_SPK_IBIAS_SEL_SHIFT 2
+#define MT6325_RG_SPK_CCODE_MASK 0xF
+#define MT6325_RG_SPK_CCODE_SHIFT 4
+#define MT6325_RG_SPK_EN_VIEW_VCM_MASK 0x1
+#define MT6325_RG_SPK_EN_VIEW_VCM_SHIFT 8
+#define MT6325_RG_SPK_EN_VIEW_CLK_MASK 0x1
+#define MT6325_RG_SPK_EN_VIEW_CLK_SHIFT 9
+#define MT6325_RG_SPK_VCM_SEL_MASK 0x1
+#define MT6325_RG_SPK_VCM_SEL_SHIFT 10
+#define MT6325_RG_SPK_VCM_IBSEL_MASK 0x1
+#define MT6325_RG_SPK_VCM_IBSEL_SHIFT 11
+#define MT6325_RG_SPK_FBRC_EN_MASK 0x1
+#define MT6325_RG_SPK_FBRC_EN_SHIFT 12
+#define MT6325_RG_SPKAB_OVDRV_MASK 0x1
+#define MT6325_RG_SPKAB_OVDRV_SHIFT 13
+#define MT6325_RG_SPK_OCTH_D_MASK 0x1
+#define MT6325_RG_SPK_OCTH_D_SHIFT 14
+#define MT6325_RG_SPKPGA_GAINL_MASK 0xF
+#define MT6325_RG_SPKPGA_GAINL_SHIFT 8
+#define MT6325_SPK_RSV0_MASK 0x1
+#define MT6325_SPK_RSV0_SHIFT 12
+#define MT6325_SPK_VCM_FAST_EN_MASK 0x1
+#define MT6325_SPK_VCM_FAST_EN_SHIFT 13
+#define MT6325_SPK_TEST_MODE0_MASK 0x1
+#define MT6325_SPK_TEST_MODE0_SHIFT 14
+#define MT6325_SPK_TEST_MODE1_MASK 0x1
+#define MT6325_SPK_TEST_MODE1_SHIFT 15
+#define MT6325_SPK_TD_WAIT_MASK 0x7
+#define MT6325_SPK_TD_WAIT_SHIFT 0
+#define MT6325_SPK_TD_DONE_MASK 0x7
+#define MT6325_SPK_TD_DONE_SHIFT 4
+#define MT6325_SPK_EN_MODE_MASK 0x1
+#define MT6325_SPK_EN_MODE_SHIFT 0
+#define MT6325_SPK_VCM_FAST_SW_MASK 0x1
+#define MT6325_SPK_VCM_FAST_SW_SHIFT 1
+#define MT6325_SPK_RST_R_SW_MASK 0x1
+#define MT6325_SPK_RST_R_SW_SHIFT 2
+#define MT6325_SPK_RST_L_SW_MASK 0x1
+#define MT6325_SPK_RST_L_SW_SHIFT 3
+#define MT6325_SPKMODE_R_SW_MASK 0x1
+#define MT6325_SPKMODE_R_SW_SHIFT 4
+#define MT6325_SPKMODE_L_SW_MASK 0x1
+#define MT6325_SPKMODE_L_SW_SHIFT 5
+#define MT6325_SPK_DEPOP_EN_R_SW_MASK 0x1
+#define MT6325_SPK_DEPOP_EN_R_SW_SHIFT 6
+#define MT6325_SPK_DEPOP_EN_L_SW_MASK 0x1
+#define MT6325_SPK_DEPOP_EN_L_SW_SHIFT 7
+#define MT6325_SPK_EN_R_SW_MASK 0x1
+#define MT6325_SPK_EN_R_SW_SHIFT 8
+#define MT6325_SPK_EN_L_SW_MASK 0x1
+#define MT6325_SPK_EN_L_SW_SHIFT 9
+#define MT6325_SPK_OUTSTG_EN_R_SW_MASK 0x1
+#define MT6325_SPK_OUTSTG_EN_R_SW_SHIFT 10
+#define MT6325_SPK_OUTSTG_EN_L_SW_MASK 0x1
+#define MT6325_SPK_OUTSTG_EN_L_SW_SHIFT 11
+#define MT6325_SPK_TRIM_EN_R_SW_MASK 0x1
+#define MT6325_SPK_TRIM_EN_R_SW_SHIFT 12
+#define MT6325_SPK_TRIM_EN_L_SW_MASK 0x1
+#define MT6325_SPK_TRIM_EN_L_SW_SHIFT 13
+#define MT6325_SPK_TRIM_STOP_R_SW_MASK 0x1
+#define MT6325_SPK_TRIM_STOP_R_SW_SHIFT 14
+#define MT6325_SPK_TRIM_STOP_L_SW_MASK 0x1
+#define MT6325_SPK_TRIM_STOP_L_SW_SHIFT 15
+#define MT6325_RG_SPK_ISENSE_TEST_EN_MASK 0x1
+#define MT6325_RG_SPK_ISENSE_TEST_EN_SHIFT 7
+#define MT6325_RG_SPK_ISENSE_REFSEL_MASK 0x7
+#define MT6325_RG_SPK_ISENSE_REFSEL_SHIFT 8
+#define MT6325_RG_SPK_ISENSE_GAINSEL_MASK 0x7
+#define MT6325_RG_SPK_ISENSE_GAINSEL_SHIFT 11
+#define MT6325_RG_SPK_ISENSE_PDRESET_MASK 0x1
+#define MT6325_RG_SPK_ISENSE_PDRESET_SHIFT 14
+#define MT6325_RG_SPK_ISENSE_EN_MASK 0x1
+#define MT6325_RG_SPK_ISENSE_EN_SHIFT 15
+#define MT6325_RG_SPK_RSV1_MASK 0xFF
+#define MT6325_RG_SPK_RSV1_SHIFT 0
+#define MT6325_RG_SPK_RSV0_MASK 0xFF
+#define MT6325_RG_SPK_RSV0_SHIFT 8
+#define MT6325_RG_SPK_ABD_VOLSEN_GAIN_MASK 0x3
+#define MT6325_RG_SPK_ABD_VOLSEN_GAIN_SHIFT 4
+#define MT6325_RG_SPK_ABD_VOLSEN_EN_MASK 0x1
+#define MT6325_RG_SPK_ABD_VOLSEN_EN_SHIFT 6
+#define MT6325_RG_SPK_ABD_CURSEN_SEL_MASK 0x1
+#define MT6325_RG_SPK_ABD_CURSEN_SEL_SHIFT 7
+#define MT6325_RG_SPK_RSV2_MASK 0xFF
+#define MT6325_RG_SPK_RSV2_SHIFT 8
+#define MT6325_RG_SPK_TRIM2_MASK 0xFF
+#define MT6325_RG_SPK_TRIM2_SHIFT 0
+#define MT6325_RG_SPK_TRIM1_MASK 0xFF
+#define MT6325_RG_SPK_TRIM1_SHIFT 8
+#define MT6325_RG_SPK_D_CURSEN_RSETSEL_MASK 0x1F
+#define MT6325_RG_SPK_D_CURSEN_RSETSEL_SHIFT 0
+#define MT6325_RG_SPK_D_CURSEN_GAIN_MASK 0x3
+#define MT6325_RG_SPK_D_CURSEN_GAIN_SHIFT 5
+#define MT6325_RG_SPK_D_CURSEN_EN_MASK 0x1
+#define MT6325_RG_SPK_D_CURSEN_EN_SHIFT 7
+#define MT6325_RG_SPK_AB_CURSEN_RSETSEL_MASK 0x1F
+#define MT6325_RG_SPK_AB_CURSEN_RSETSEL_SHIFT 8
+#define MT6325_RG_SPK_AB_CURSEN_GAIN_MASK 0x3
+#define MT6325_RG_SPK_AB_CURSEN_GAIN_SHIFT 13
+#define MT6325_RG_SPK_AB_CURSEN_EN_MASK 0x1
+#define MT6325_RG_SPK_AB_CURSEN_EN_SHIFT 15
+#define MT6325_RG_SPKPGA_GAIN_MASK 0xF
+#define MT6325_RG_SPKPGA_GAIN_SHIFT 11
+#define MT6325_RG_SPK_RSV_MASK 0xFF
+#define MT6325_RG_SPK_RSV_SHIFT 0
+#define MT6325_RG_ISENSE_PD_RESET_MASK 0x1
+#define MT6325_RG_ISENSE_PD_RESET_SHIFT 11
+#define MT6325_RG_AUDIVLPWRUP_VAUDP12_MASK 0x1
+#define MT6325_RG_AUDIVLPWRUP_VAUDP12_SHIFT 4
+#define MT6325_RG_AUDIVLSTARTUP_VAUDP12_MASK 0x1
+#define MT6325_RG_AUDIVLSTARTUP_VAUDP12_SHIFT 5
+#define MT6325_RG_AUDIVLMUXSEL_VAUDP12_MASK 0x7
+#define MT6325_RG_AUDIVLMUXSEL_VAUDP12_SHIFT 6
+#define MT6325_RG_AUDIVLMUTE_VAUDP12_MASK 0x1
+#define MT6325_RG_AUDIVLMUTE_VAUDP12_SHIFT 9
+#define MT6325_RG_OTP_PA_MASK 0x3F
+#define MT6325_RG_OTP_PA_SHIFT 0
+#define MT6325_RG_OTP_PDIN_MASK 0xFF
+#define MT6325_RG_OTP_PDIN_SHIFT 0
+#define MT6325_RG_OTP_PTM_MASK 0x3
+#define MT6325_RG_OTP_PTM_SHIFT 0
+#define MT6325_RG_OTP_PWE_MASK 0x3
+#define MT6325_RG_OTP_PWE_SHIFT 0
+#define MT6325_RG_OTP_PPROG_MASK 0x1
+#define MT6325_RG_OTP_PPROG_SHIFT 0
+#define MT6325_RG_OTP_PWE_SRC_MASK 0x1
+#define MT6325_RG_OTP_PWE_SRC_SHIFT 0
+#define MT6325_RG_OTP_PROG_PKEY_MASK 0xFFFF
+#define MT6325_RG_OTP_PROG_PKEY_SHIFT 0
+#define MT6325_RG_OTP_RD_PKEY_MASK 0xFFFF
+#define MT6325_RG_OTP_RD_PKEY_SHIFT 0
+#define MT6325_RG_OTP_RD_TRIG_MASK 0x1
+#define MT6325_RG_OTP_RD_TRIG_SHIFT 0
+#define MT6325_RG_RD_RDY_BYPASS_MASK 0x1
+#define MT6325_RG_RD_RDY_BYPASS_SHIFT 0
+#define MT6325_RG_SKIP_OTP_OUT_MASK 0x1
+#define MT6325_RG_SKIP_OTP_OUT_SHIFT 0
+#define MT6325_RG_OTP_RD_SW_MASK 0x1
+#define MT6325_RG_OTP_RD_SW_SHIFT 0
+#define MT6325_RG_OTP_DOUT_SW_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_SW_SHIFT 0
+#define MT6325_RG_OTP_RD_BUSY_MASK 0x1
+#define MT6325_RG_OTP_RD_BUSY_SHIFT 0
+#define MT6325_RG_OTP_RD_ACK_MASK 0x1
+#define MT6325_RG_OTP_RD_ACK_SHIFT 2
+#define MT6325_RG_OTP_PA_SW_MASK 0x1F
+#define MT6325_RG_OTP_PA_SW_SHIFT 0
+#define MT6325_RG_OTP_DOUT_0_15_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_0_15_SHIFT 0
+#define MT6325_RG_OTP_DOUT_16_31_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_16_31_SHIFT 0
+#define MT6325_RG_OTP_DOUT_32_47_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_32_47_SHIFT 0
+#define MT6325_RG_OTP_DOUT_48_63_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_48_63_SHIFT 0
+#define MT6325_RG_OTP_DOUT_64_79_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_64_79_SHIFT 0
+#define MT6325_RG_OTP_DOUT_80_95_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_80_95_SHIFT 0
+#define MT6325_RG_OTP_DOUT_96_111_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_96_111_SHIFT 0
+#define MT6325_RG_OTP_DOUT_112_127_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_112_127_SHIFT 0
+#define MT6325_RG_OTP_DOUT_128_143_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_128_143_SHIFT 0
+#define MT6325_RG_OTP_DOUT_144_159_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_144_159_SHIFT 0
+#define MT6325_RG_OTP_DOUT_160_175_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_160_175_SHIFT 0
+#define MT6325_RG_OTP_DOUT_176_191_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_176_191_SHIFT 0
+#define MT6325_RG_OTP_DOUT_192_207_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_192_207_SHIFT 0
+#define MT6325_RG_OTP_DOUT_208_223_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_208_223_SHIFT 0
+#define MT6325_RG_OTP_DOUT_224_239_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_224_239_SHIFT 0
+#define MT6325_RG_OTP_DOUT_240_255_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_240_255_SHIFT 0
+#define MT6325_RG_OTP_DOUT_256_271_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_256_271_SHIFT 0
+#define MT6325_RG_OTP_DOUT_272_287_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_272_287_SHIFT 0
+#define MT6325_RG_OTP_DOUT_288_303_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_288_303_SHIFT 0
+#define MT6325_RG_OTP_DOUT_304_319_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_304_319_SHIFT 0
+#define MT6325_RG_OTP_DOUT_320_335_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_320_335_SHIFT 0
+#define MT6325_RG_OTP_DOUT_336_351_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_336_351_SHIFT 0
+#define MT6325_RG_OTP_DOUT_352_367_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_352_367_SHIFT 0
+#define MT6325_RG_OTP_DOUT_368_383_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_368_383_SHIFT 0
+#define MT6325_RG_OTP_DOUT_384_399_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_384_399_SHIFT 0
+#define MT6325_RG_OTP_DOUT_400_415_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_400_415_SHIFT 0
+#define MT6325_RG_OTP_DOUT_416_431_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_416_431_SHIFT 0
+#define MT6325_RG_OTP_DOUT_432_447_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_432_447_SHIFT 0
+#define MT6325_RG_OTP_DOUT_448_463_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_448_463_SHIFT 0
+#define MT6325_RG_OTP_DOUT_464_479_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_464_479_SHIFT 0
+#define MT6325_RG_OTP_DOUT_480_495_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_480_495_SHIFT 0
+#define MT6325_RG_OTP_DOUT_496_511_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_496_511_SHIFT 0
+#define MT6325_RG_OTP_VAL_0_15_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_0_15_SHIFT 0
+#define MT6325_RG_OTP_VAL_16_31_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_16_31_SHIFT 0
+#define MT6325_RG_OTP_VAL_32_47_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_32_47_SHIFT 0
+#define MT6325_RG_OTP_VAL_48_63_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_48_63_SHIFT 0
+#define MT6325_RG_OTP_VAL_64_79_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_64_79_SHIFT 0
+#define MT6325_RG_OTP_VAL_80_95_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_80_95_SHIFT 0
+#define MT6325_RG_OTP_VAL_96_111_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_96_111_SHIFT 0
+#define MT6325_RG_OTP_VAL_112_127_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_112_127_SHIFT 0
+#define MT6325_RG_OTP_VAL_128_143_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_128_143_SHIFT 0
+#define MT6325_RG_OTP_VAL_144_159_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_144_159_SHIFT 0
+#define MT6325_RG_OTP_VAL_160_175_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_160_175_SHIFT 0
+#define MT6325_RG_OTP_VAL_176_191_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_176_191_SHIFT 0
+#define MT6325_RG_OTP_VAL_192_207_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_192_207_SHIFT 0
+#define MT6325_RG_OTP_VAL_208_223_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_208_223_SHIFT 0
+#define MT6325_RG_OTP_VAL_224_239_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_224_239_SHIFT 0
+#define MT6325_RG_OTP_VAL_240_255_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_240_255_SHIFT 0
+#define MT6325_RG_OTP_VAL_256_271_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_256_271_SHIFT 0
+#define MT6325_RG_OTP_VAL_272_287_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_272_287_SHIFT 0
+#define MT6325_RG_OTP_VAL_288_303_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_288_303_SHIFT 0
+#define MT6325_RG_OTP_VAL_304_319_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_304_319_SHIFT 0
+#define MT6325_RG_OTP_VAL_320_335_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_320_335_SHIFT 0
+#define MT6325_RG_OTP_VAL_336_351_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_336_351_SHIFT 0
+#define MT6325_RG_OTP_VAL_352_367_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_352_367_SHIFT 0
+#define MT6325_RG_OTP_VAL_368_383_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_368_383_SHIFT 0
+#define MT6325_RG_OTP_VAL_384_399_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_384_399_SHIFT 0
+#define MT6325_RG_OTP_VAL_400_415_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_400_415_SHIFT 0
+#define MT6325_RG_OTP_VAL_416_431_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_416_431_SHIFT 0
+#define MT6325_RG_OTP_VAL_432_447_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_432_447_SHIFT 0
+#define MT6325_RG_OTP_VAL_448_463_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_448_463_SHIFT 0
+#define MT6325_RG_OTP_VAL_464_479_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_464_479_SHIFT 0
+#define MT6325_RG_OTP_VAL_480_495_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_480_495_SHIFT 0
+#define MT6325_RG_OTP_VAL_496_511_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_496_511_SHIFT 0
+#define MT6325_MIX_EOSC32_STP_LPDTB_MASK 0x1
+#define MT6325_MIX_EOSC32_STP_LPDTB_SHIFT 1
+#define MT6325_MIX_EOSC32_STP_LPDEN_MASK 0x1
+#define MT6325_MIX_EOSC32_STP_LPDEN_SHIFT 2
+#define MT6325_MIX_XOSC32_STP_PWDB_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_PWDB_SHIFT 3
+#define MT6325_MIX_XOSC32_STP_LPDTB_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_LPDTB_SHIFT 4
+#define MT6325_MIX_XOSC32_STP_LPDEN_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_LPDEN_SHIFT 5
+#define MT6325_MIX_XOSC32_STP_LPDRST_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_LPDRST_SHIFT 6
+#define MT6325_MIX_XOSC32_STP_CALI_MASK 0x1F
+#define MT6325_MIX_XOSC32_STP_CALI_SHIFT 7
+#define MT6325_STMP_MODE_MASK 0x1
+#define MT6325_STMP_MODE_SHIFT 12
+#define MT6325_MIX_EOSC32_STP_CHOP_EN_MASK 0x1
+#define MT6325_MIX_EOSC32_STP_CHOP_EN_SHIFT 0
+#define MT6325_MIX_DCXO_STP_LVSH_EN_MASK 0x1
+#define MT6325_MIX_DCXO_STP_LVSH_EN_SHIFT 1
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_MASK 0x1
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_SHIFT 2
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_EN_MASK 0x1
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3
+#define MT6325_MIX_RTC_STP_XOSC32_ENB_MASK 0x1
+#define MT6325_MIX_RTC_STP_XOSC32_ENB_SHIFT 4
+#define MT6325_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1
+#define MT6325_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT 5
+#define MT6325_MIX_EOSC32_STP_RSV_MASK 0x3
+#define MT6325_MIX_EOSC32_STP_RSV_SHIFT 6
+#define MT6325_MIX_EOSC32_VCT_EN_MASK 0x1
+#define MT6325_MIX_EOSC32_VCT_EN_SHIFT 8
+#define MT6325_MIX_EOSC32_OPT_MASK 0x3
+#define MT6325_MIX_EOSC32_OPT_SHIFT 9
+#define MT6325_MIX_RTC_STP_DEBUG_OUT_MASK 0x3
+#define MT6325_MIX_RTC_STP_DEBUG_OUT_SHIFT 0
+#define MT6325_MIX_RTC_STP_DEBUG_SEL_MASK 0x3
+#define MT6325_MIX_RTC_STP_DEBUG_SEL_SHIFT 4
+#define MT6325_MIX_RTC_STP_K_EOSC32_EN_MASK 0x1
+#define MT6325_MIX_RTC_STP_K_EOSC32_EN_SHIFT 7
+#define MT6325_MIX_RTC_STP_EMBCK_SEL_MASK 0x1
+#define MT6325_MIX_RTC_STP_EMBCK_SEL_SHIFT 8
+#define MT6325_MIX_STP_BBWAKEUP_MASK 0x1
+#define MT6325_MIX_STP_BBWAKEUP_SHIFT 9
+#define MT6325_MIX_STP_RTC_DDLO_MASK 0x1
+#define MT6325_MIX_STP_RTC_DDLO_SHIFT 10
+#define MT6325_MIX_RTC_XOSC32_ENB_MASK 0x1
+#define MT6325_MIX_RTC_XOSC32_ENB_SHIFT 11
+#define MT6325_MIX_EFUSE_XOSC32_ENB_OPT_MASK 0x1
+#define MT6325_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT 12
+#define MT6325_FG_ON_MASK 0x1
+#define MT6325_FG_ON_SHIFT 0
+#define MT6325_FG_CAL_MASK 0x3
+#define MT6325_FG_CAL_SHIFT 2
+#define MT6325_FG_AUTOCALRATE_MASK 0x7
+#define MT6325_FG_AUTOCALRATE_SHIFT 4
+#define MT6325_FG_SW_CR_MASK 0x1
+#define MT6325_FG_SW_CR_SHIFT 8
+#define MT6325_FG_SW_READ_PRE_MASK 0x1
+#define MT6325_FG_SW_READ_PRE_SHIFT 9
+#define MT6325_FG_LATCHDATA_ST_MASK 0x1
+#define MT6325_FG_LATCHDATA_ST_SHIFT 10
+#define MT6325_FG_SW_CLEAR_MASK 0x1
+#define MT6325_FG_SW_CLEAR_SHIFT 11
+#define MT6325_FG_OFFSET_RST_MASK 0x1
+#define MT6325_FG_OFFSET_RST_SHIFT 12
+#define MT6325_FG_TIME_RST_MASK 0x1
+#define MT6325_FG_TIME_RST_SHIFT 13
+#define MT6325_FG_CHARGE_RST_MASK 0x1
+#define MT6325_FG_CHARGE_RST_SHIFT 14
+#define MT6325_FG_SW_RSTCLR_MASK 0x1
+#define MT6325_FG_SW_RSTCLR_SHIFT 15
+#define MT6325_FG_CAR_31_16_MASK 0xFFFF
+#define MT6325_FG_CAR_31_16_SHIFT 0
+#define MT6325_FG_CAR_15_00_MASK 0xFFFF
+#define MT6325_FG_CAR_15_00_SHIFT 0
+#define MT6325_FG_NTER_29_16_MASK 0x3FFF
+#define MT6325_FG_NTER_29_16_SHIFT 0
+#define MT6325_FG_NTER_15_00_MASK 0xFFFF
+#define MT6325_FG_NTER_15_00_SHIFT 0
+#define MT6325_FG_BLTR_MASK 0xFFFF
+#define MT6325_FG_BLTR_SHIFT 0
+#define MT6325_FG_BFTR_MASK 0xFFFF
+#define MT6325_FG_BFTR_SHIFT 0
+#define MT6325_FG_CURRENT_OUT_MASK 0xFFFF
+#define MT6325_FG_CURRENT_OUT_SHIFT 0
+#define MT6325_FG_ADJUST_OFFSET_VALUE_MASK 0xFFFF
+#define MT6325_FG_ADJUST_OFFSET_VALUE_SHIFT 0
+#define MT6325_FG_OFFSET_MASK 0xFFFF
+#define MT6325_FG_OFFSET_SHIFT 0
+#define MT6325_RG_FGRINTMODE_MASK 0x1
+#define MT6325_RG_FGRINTMODE_SHIFT 0
+#define MT6325_RG_FGANALOGTEST_MASK 0xF
+#define MT6325_RG_FGANALOGTEST_SHIFT 4
+#define MT6325_RG_SPARE_MASK 0xFF
+#define MT6325_RG_SPARE_SHIFT 8
+#define MT6325_FG_OSR_MASK 0xF
+#define MT6325_FG_OSR_SHIFT 0
+#define MT6325_FG_ADJ_OFFSET_EN_MASK 0x1
+#define MT6325_FG_ADJ_OFFSET_EN_SHIFT 8
+#define MT6325_FG_ADC_AUTORST_MASK 0x1
+#define MT6325_FG_ADC_AUTORST_SHIFT 9
+#define MT6325_FG_FIR1BYPASS_MASK 0x1
+#define MT6325_FG_FIR1BYPASS_SHIFT 0
+#define MT6325_FG_FIR2BYPASS_MASK 0x1
+#define MT6325_FG_FIR2BYPASS_SHIFT 1
+#define MT6325_FG_L_CUR_INT_STS_MASK 0x1
+#define MT6325_FG_L_CUR_INT_STS_SHIFT 2
+#define MT6325_FG_H_CUR_INT_STS_MASK 0x1
+#define MT6325_FG_H_CUR_INT_STS_SHIFT 3
+#define MT6325_FG_L_INT_STS_MASK 0x1
+#define MT6325_FG_L_INT_STS_SHIFT 4
+#define MT6325_FG_H_INT_STS_MASK 0x1
+#define MT6325_FG_H_INT_STS_SHIFT 5
+#define MT6325_FG_ADC_RSTDETECT_MASK 0x1
+#define MT6325_FG_ADC_RSTDETECT_SHIFT 7
+#define MT6325_FG_SLP_EN_MASK 0x1
+#define MT6325_FG_SLP_EN_SHIFT 8
+#define MT6325_FG_ZCV_DET_EN_MASK 0x1
+#define MT6325_FG_ZCV_DET_EN_SHIFT 9
+#define MT6325_RG_FG_AUXADC_R_MASK 0x1
+#define MT6325_RG_FG_AUXADC_R_SHIFT 10
+#define MT6325_FGADC_EN_MASK 0x1
+#define MT6325_FGADC_EN_SHIFT 12
+#define MT6325_FGCAL_EN_MASK 0x1
+#define MT6325_FGCAL_EN_SHIFT 13
+#define MT6325_FG_RST_MASK 0x1
+#define MT6325_FG_RST_SHIFT 14
+#define MT6325_FG_CIC2_MASK 0xFFFF
+#define MT6325_FG_CIC2_SHIFT 0
+#define MT6325_FG_SLP_CUR_TH_MASK 0xFFFF
+#define MT6325_FG_SLP_CUR_TH_SHIFT 0
+#define MT6325_FG_SLP_TIME_MASK 0xFF
+#define MT6325_FG_SLP_TIME_SHIFT 0
+#define MT6325_FG_SRCVOLTEN_FTIME_MASK 0xFF
+#define MT6325_FG_SRCVOLTEN_FTIME_SHIFT 0
+#define MT6325_FG_DET_TIME_MASK 0xFF
+#define MT6325_FG_DET_TIME_SHIFT 8
+#define MT6325_FG_ZCV_CAR_31_16_MASK 0xFFFF
+#define MT6325_FG_ZCV_CAR_31_16_SHIFT 0
+#define MT6325_FG_ZCV_CAR_15_00_MASK 0xFFFF
+#define MT6325_FG_ZCV_CAR_15_00_SHIFT 0
+#define MT6325_FG_ZCV_CURR_MASK 0xFFFF
+#define MT6325_FG_ZCV_CURR_SHIFT 0
+#define MT6325_FG_R_CURR_MASK 0xFFFF
+#define MT6325_FG_R_CURR_SHIFT 0
+#define MT6325_FG_MODE_MASK 0x1
+#define MT6325_FG_MODE_SHIFT 0
+#define MT6325_FG_RST_SW_MASK 0x1
+#define MT6325_FG_RST_SW_SHIFT 1
+#define MT6325_FG_FGCAL_EN_SW_MASK 0x1
+#define MT6325_FG_FGCAL_EN_SW_SHIFT 2
+#define MT6325_FG_FGADC_EN_SW_MASK 0x1
+#define MT6325_FG_FGADC_EN_SW_SHIFT 3
+#define MT6325_FG_RSV1_MASK 0xF
+#define MT6325_FG_RSV1_SHIFT 4
+#define MT6325_FG_TEST_MODE0_MASK 0x1
+#define MT6325_FG_TEST_MODE0_SHIFT 14
+#define MT6325_FG_TEST_MODE1_MASK 0x1
+#define MT6325_FG_TEST_MODE1_SHIFT 15
+#define MT6325_FG_GAIN_MASK 0x1FFF
+#define MT6325_FG_GAIN_SHIFT 0
+#define MT6325_FG_CUR_HTH_MASK 0xFFFF
+#define MT6325_FG_CUR_HTH_SHIFT 0
+#define MT6325_FG_CUR_LTH_MASK 0xFFFF
+#define MT6325_FG_CUR_LTH_SHIFT 0
+#define MT6325_FG_ZCV_DET_TIME_MASK 0x3F
+#define MT6325_FG_ZCV_DET_TIME_SHIFT 0
+#define MT6325_FG_ZCV_CAR_TH_30_16_MASK 0x7FFF
+#define MT6325_FG_ZCV_CAR_TH_30_16_SHIFT 0
+#define MT6325_FG_ZCV_CAR_TH_15_00_MASK 0xFFFF
+#define MT6325_FG_ZCV_CAR_TH_15_00_SHIFT 0
+#define MT6325_RG_FGINTMODE_MASK 0x1
+#define MT6325_RG_FGINTMODE_SHIFT 4
+#define MT6325_RG_AUDDACLPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDDACLPWRUP_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDDACRPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDDACRPWRUP_VAUDP15_SHIFT 1
+#define MT6325_RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
+#define MT6325_RG_AUD_DAC_PWR_UP_VA28_SHIFT 2
+#define MT6325_RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
+#define MT6325_RG_AUD_DAC_PWL_UP_VA28_SHIFT 3
+#define MT6325_RG_AUDHSPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSPWRUP_VAUDP15_SHIFT 4
+#define MT6325_RG_AUDHPLPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPLPWRUP_VAUDP15_SHIFT 5
+#define MT6325_RG_AUDHPRPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPRPWRUP_VAUDP15_SHIFT 6
+#define MT6325_RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHSMUXINPUTSEL_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPLMUXINPUTSEL_VAUDP15_SHIFT 9
+#define MT6325_RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPRMUXINPUTSEL_VAUDP15_SHIFT 11
+#define MT6325_RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSSCDISABLE_VAUDP15_SHIFT 13
+#define MT6325_RG_AUDHPLSCDISABLE_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPLSCDISABLE_VAUDP15_SHIFT 14
+#define MT6325_RG_AUDHPRSCDISABLE_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPRSCDISABLE_VAUDP15_SHIFT 15
+#define MT6325_RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPLBSCCURRENT_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPRBSCCURRENT_VAUDP15_SHIFT 1
+#define MT6325_RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSBSCCURRENT_VAUDP15_SHIFT 2
+#define MT6325_RG_AUDHPSTARTUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPSTARTUP_VAUDP15_SHIFT 3
+#define MT6325_RG_AUDHSSTARTUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSSTARTUP_VAUDP15_SHIFT 4
+#define MT6325_RG_PRECHARGEBUF_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_PRECHARGEBUF_EN_VAUDP15_SHIFT 5
+#define MT6325_RG_HPINPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HPINPUTSTBENH_VAUDP15_SHIFT 6
+#define MT6325_RG_HPOUTPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HPOUTPUTSTBENH_VAUDP15_SHIFT 7
+#define MT6325_RG_HPINPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HPINPUTRESET0_VAUDP15_SHIFT 8
+#define MT6325_RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HPOUTPUTRESET0_VAUDP15_SHIFT 9
+#define MT6325_RG_HPOUT_SHORTVCM_VAUDP15_MASK 0x1
+#define MT6325_RG_HPOUT_SHORTVCM_VAUDP15_SHIFT 10
+#define MT6325_RG_HSINPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HSINPUTSTBENH_VAUDP15_SHIFT 11
+#define MT6325_RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HSOUTPUTSTBENH_VAUDP15_SHIFT 12
+#define MT6325_RG_HSINPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HSINPUTRESET0_VAUDP15_SHIFT 13
+#define MT6325_RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HSOUTPUTRESET0_VAUDP15_SHIFT 14
+#define MT6325_RG_HPOUTSTB_RSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_HPOUTSTB_RSEL_VAUDP15_SHIFT 0
+#define MT6325_RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
+#define MT6325_RG_HSOUT_SHORTVCM_VAUDP15_SHIFT 2
+#define MT6325_RG_AUDHPLTRIM_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDHPLTRIM_VAUDP15_SHIFT 3
+#define MT6325_RG_AUDHPRTRIM_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDHPRTRIM_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDHPTRIM_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPTRIM_EN_VAUDP15_SHIFT 11
+#define MT6325_RG_AUDHPLFINETRIM_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPLFINETRIM_VAUDP15_SHIFT 12
+#define MT6325_RG_AUDHPRFINETRIM_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPRFINETRIM_VAUDP15_SHIFT 14
+#define MT6325_RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDTRIMBUF_EN_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SHIFT 1
+#define MT6325_RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDTRIMBUF_GAINSEL_VAUDP15_SHIFT 5
+#define MT6325_RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPSPKDET_EN_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SHIFT 8
+#define MT6325_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SHIFT 10
+#define MT6325_RG_ABIDEC_RESERVED_VA28_MASK 0xFF
+#define MT6325_RG_ABIDEC_RESERVED_VA28_SHIFT 0
+#define MT6325_RG_ABIDEC_RESERVED_VAUDP15_MASK 0xFF
+#define MT6325_RG_ABIDEC_RESERVED_VAUDP15_SHIFT 8
+#define MT6325_RG_AUDBIASADJ_0_VAUDP15_MASK 0x3F
+#define MT6325_RG_AUDBIASADJ_0_VAUDP15_SHIFT 4
+#define MT6325_RG_AUDBIASADJ_1_VAUDP15_MASK 0x3F
+#define MT6325_RG_AUDBIASADJ_1_VAUDP15_SHIFT 10
+#define MT6325_RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDIBIASPWRDN_VAUDP15_SHIFT 0
+#define MT6325_RG_RSTB_DECODER_VA28_MASK 0x1
+#define MT6325_RG_RSTB_DECODER_VA28_SHIFT 1
+#define MT6325_RG_RSTB_ENCODER_VA28_MASK 0x1
+#define MT6325_RG_RSTB_ENCODER_VA28_SHIFT 2
+#define MT6325_RG_SEL_DECODER_96K_VA28_MASK 0x1
+#define MT6325_RG_SEL_DECODER_96K_VA28_SHIFT 3
+#define MT6325_RG_SEL_ENCODER_96K_VA28_MASK 0x1
+#define MT6325_RG_SEL_ENCODER_96K_VA28_SHIFT 4
+#define MT6325_RG_SEL_DELAY_VCORE_MASK 0x1
+#define MT6325_RG_SEL_DELAY_VCORE_SHIFT 5
+#define MT6325_RG_HCLDO_EN_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_EN_VA18_SHIFT 6
+#define MT6325_RG_LCLDO_EN_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_EN_VA18_SHIFT 7
+#define MT6325_RG_LCLDO_ENC_EN_VA28_MASK 0x1
+#define MT6325_RG_LCLDO_ENC_EN_VA28_SHIFT 8
+#define MT6325_RG_VA33REFGEN_EN_VA18_MASK 0x1
+#define MT6325_RG_VA33REFGEN_EN_VA18_SHIFT 9
+#define MT6325_RG_HCLDO_PDDIS_EN_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_PDDIS_EN_VA18_SHIFT 10
+#define MT6325_RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_REMOTE_SENSE_VA18_SHIFT 11
+#define MT6325_RG_LCLDO_PDDIS_EN_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_PDDIS_EN_VA18_SHIFT 12
+#define MT6325_RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_REMOTE_SENSE_VA18_SHIFT 13
+#define MT6325_RG_LCLDO_VOSEL_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_VOSEL_VA18_SHIFT 14
+#define MT6325_RG_HCLDO_VOSEL_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_VOSEL_VA18_SHIFT 15
+#define MT6325_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
+#define MT6325_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT 0
+#define MT6325_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
+#define MT6325_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT 1
+#define MT6325_RG_VA28REFGEN_EN_VA28_MASK 0x1
+#define MT6325_RG_VA28REFGEN_EN_VA28_SHIFT 2
+#define MT6325_RG_AUDPMU_RESERVED_VA28_MASK 0xF
+#define MT6325_RG_AUDPMU_RESERVED_VA28_SHIFT 3
+#define MT6325_RG_AUDPMU_RESERVED_VA18_MASK 0xF
+#define MT6325_RG_AUDPMU_RESERVED_VA18_SHIFT 7
+#define MT6325_RG_AUDPMU_RESERVED_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDPMU_RESERVED_VAUDP15_SHIFT 11
+#define MT6325_RG_NVREG_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_NVREG_EN_VAUDP15_SHIFT 15
+#define MT6325_RG_NVREG_PULL0V_VAUDP15_MASK 0x1
+#define MT6325_RG_NVREG_PULL0V_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDGLB_PWRDN_VA28_MASK 0x1
+#define MT6325_RG_AUDGLB_PWRDN_VA28_SHIFT 1
+#define MT6325_RG_AUDPREAMPLON_MASK 0x1
+#define MT6325_RG_AUDPREAMPLON_SHIFT 0
+#define MT6325_RG_AUDPREAMPLDCCEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPLDCCEN_SHIFT 1
+#define MT6325_RG_AUDPREAMPLDCRPECHARGE_MASK 0x1
+#define MT6325_RG_AUDPREAMPLDCRPECHARGE_SHIFT 2
+#define MT6325_RG_AUDPREAMPLPGATEST_MASK 0x1
+#define MT6325_RG_AUDPREAMPLPGATEST_SHIFT 3
+#define MT6325_RG_AUDPREAMPLVSCALE_MASK 0x3
+#define MT6325_RG_AUDPREAMPLVSCALE_SHIFT 4
+#define MT6325_RG_AUDPREAMPLINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDPREAMPLINPUTSEL_SHIFT 6
+#define MT6325_RG_AUDADCLPWRUP_MASK 0x1
+#define MT6325_RG_AUDADCLPWRUP_SHIFT 8
+#define MT6325_RG_AUDADCLINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDADCLINPUTSEL_SHIFT 9
+#define MT6325_RG_AUDPREAMPRON_MASK 0x1
+#define MT6325_RG_AUDPREAMPRON_SHIFT 0
+#define MT6325_RG_AUDPREAMPRDCCEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPRDCCEN_SHIFT 1
+#define MT6325_RG_AUDPREAMPRDCRPECHARGE_MASK 0x1
+#define MT6325_RG_AUDPREAMPRDCRPECHARGE_SHIFT 2
+#define MT6325_RG_AUDPREAMPRPGATEST_MASK 0x1
+#define MT6325_RG_AUDPREAMPRPGATEST_SHIFT 3
+#define MT6325_RG_AUDPREAMPRVSCALE_MASK 0x3
+#define MT6325_RG_AUDPREAMPRVSCALE_SHIFT 4
+#define MT6325_RG_AUDPREAMPRINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDPREAMPRINPUTSEL_SHIFT 6
+#define MT6325_RG_AUDADCRPWRUP_MASK 0x1
+#define MT6325_RG_AUDADCRPWRUP_SHIFT 8
+#define MT6325_RG_AUDADCRINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDADCRINPUTSEL_SHIFT 9
+#define MT6325_RG_AUDULHALFBIAS_MASK 0x1
+#define MT6325_RG_AUDULHALFBIAS_SHIFT 0
+#define MT6325_RG_AUDGLBVOWLPWEN_MASK 0x1
+#define MT6325_RG_AUDGLBVOWLPWEN_SHIFT 1
+#define MT6325_RG_AUDPREAMPLPEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPLPEN_SHIFT 2
+#define MT6325_RG_AUDADC1STSTAGELPEN_MASK 0x1
+#define MT6325_RG_AUDADC1STSTAGELPEN_SHIFT 3
+#define MT6325_RG_AUDADC2NDSTAGELPEN_MASK 0x1
+#define MT6325_RG_AUDADC2NDSTAGELPEN_SHIFT 4
+#define MT6325_RG_AUDADCFLASHLPEN_MASK 0x1
+#define MT6325_RG_AUDADCFLASHLPEN_SHIFT 5
+#define MT6325_RG_AUDPREAMPIDDTEST_MASK 0x3
+#define MT6325_RG_AUDPREAMPIDDTEST_SHIFT 6
+#define MT6325_RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADC1STSTAGEIDDTEST_SHIFT 8
+#define MT6325_RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 10
+#define MT6325_RG_AUDADCREFBUFIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADCREFBUFIDDTEST_SHIFT 12
+#define MT6325_RG_AUDADCFLASHIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADCFLASHIDDTEST_SHIFT 14
+#define MT6325_RG_AUDADCDAC0P25FS_MASK 0x1
+#define MT6325_RG_AUDADCDAC0P25FS_SHIFT 0
+#define MT6325_RG_AUDADCCLKSEL_MASK 0x1
+#define MT6325_RG_AUDADCCLKSEL_SHIFT 1
+#define MT6325_RG_AUDADCCLKSOURCE_MASK 0x3
+#define MT6325_RG_AUDADCCLKSOURCE_SHIFT 2
+#define MT6325_RG_AUDADCCLKGENMODE_MASK 0x3
+#define MT6325_RG_AUDADCCLKGENMODE_SHIFT 4
+#define MT6325_RG_AUDPREAMPAAFEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPAAFEN_SHIFT 8
+#define MT6325_RG_DCCVCMBUFLPMODSEL_MASK 0x1
+#define MT6325_RG_DCCVCMBUFLPMODSEL_SHIFT 9
+#define MT6325_RG_DCCVCMBUFLPSWEN_MASK 0x1
+#define MT6325_RG_DCCVCMBUFLPSWEN_SHIFT 10
+#define MT6325_RG_AUDSPAREPGA_MASK 0x1F
+#define MT6325_RG_AUDSPAREPGA_SHIFT 11
+#define MT6325_RG_AUDADC1STSTAGESDENB_MASK 0x1
+#define MT6325_RG_AUDADC1STSTAGESDENB_SHIFT 0
+#define MT6325_RG_AUDADC2NDSTAGERESET_MASK 0x1
+#define MT6325_RG_AUDADC2NDSTAGERESET_SHIFT 1
+#define MT6325_RG_AUDADC3RDSTAGERESET_MASK 0x1
+#define MT6325_RG_AUDADC3RDSTAGERESET_SHIFT 2
+#define MT6325_RG_AUDADCFSRESET_MASK 0x1
+#define MT6325_RG_AUDADCFSRESET_SHIFT 3
+#define MT6325_RG_AUDADCWIDECM_MASK 0x1
+#define MT6325_RG_AUDADCWIDECM_SHIFT 4
+#define MT6325_RG_AUDADCNOPATEST_MASK 0x1
+#define MT6325_RG_AUDADCNOPATEST_SHIFT 5
+#define MT6325_RG_AUDADCBYPASS_MASK 0x1
+#define MT6325_RG_AUDADCBYPASS_SHIFT 6
+#define MT6325_RG_AUDADCFFBYPASS_MASK 0x1
+#define MT6325_RG_AUDADCFFBYPASS_SHIFT 7
+#define MT6325_RG_AUDADCDACFBCURRENT_MASK 0x1
+#define MT6325_RG_AUDADCDACFBCURRENT_SHIFT 8
+#define MT6325_RG_AUDADCDACIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADCDACIDDTEST_SHIFT 9
+#define MT6325_RG_AUDADCDACNRZ_MASK 0x1
+#define MT6325_RG_AUDADCDACNRZ_SHIFT 11
+#define MT6325_RG_AUDADCNODEM_MASK 0x1
+#define MT6325_RG_AUDADCNODEM_SHIFT 12
+#define MT6325_RG_AUDADCDACTEST_MASK 0x1
+#define MT6325_RG_AUDADCDACTEST_SHIFT 13
+#define MT6325_RG_AUDADCTESTDATA_MASK 0xFFFF
+#define MT6325_RG_AUDADCTESTDATA_SHIFT 0
+#define MT6325_RG_AUDRCTUNEL_MASK 0x1F
+#define MT6325_RG_AUDRCTUNEL_SHIFT 0
+#define MT6325_RG_AUDRCTUNELSEL_MASK 0x1
+#define MT6325_RG_AUDRCTUNELSEL_SHIFT 5
+#define MT6325_RG_AUDRCTUNER_MASK 0x1F
+#define MT6325_RG_AUDRCTUNER_SHIFT 8
+#define MT6325_RG_AUDRCTUNERSEL_MASK 0x1
+#define MT6325_RG_AUDRCTUNERSEL_SHIFT 13
+#define MT6325_RG_AUDSPAREVA28_MASK 0xFF
+#define MT6325_RG_AUDSPAREVA28_SHIFT 0
+#define MT6325_RG_AUDSPAREVA18_MASK 0xFF
+#define MT6325_RG_AUDSPAREVA18_SHIFT 8
+#define MT6325_RG_AUDDIGMICEN_MASK 0x1
+#define MT6325_RG_AUDDIGMICEN_SHIFT 0
+#define MT6325_RG_AUDDIGMICBIAS_MASK 0x3
+#define MT6325_RG_AUDDIGMICBIAS_SHIFT 1
+#define MT6325_RG_DMICHPCLKEN_MASK 0x1
+#define MT6325_RG_DMICHPCLKEN_SHIFT 3
+#define MT6325_RG_AUDDIGMICPDUTY_MASK 0x3
+#define MT6325_RG_AUDDIGMICPDUTY_SHIFT 4
+#define MT6325_RG_AUDDIGMICNDUTY_MASK 0x3
+#define MT6325_RG_AUDDIGMICNDUTY_SHIFT 6
+#define MT6325_RG_DMICMONEN_MASK 0x1
+#define MT6325_RG_DMICMONEN_SHIFT 8
+#define MT6325_RG_DMICMONSEL_MASK 0x7
+#define MT6325_RG_DMICMONSEL_SHIFT 9
+#define MT6325_RG_AUDSPAREVMIC_MASK 0xF
+#define MT6325_RG_AUDSPAREVMIC_SHIFT 12
+#define MT6325_RG_AUDPWDBMICBIAS0_MASK 0x1
+#define MT6325_RG_AUDPWDBMICBIAS0_SHIFT 0
+#define MT6325_RG_AUDMICBIAS0DCSWPEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS0DCSWPEN_SHIFT 1
+#define MT6325_RG_AUDMICBIAS0DCSWNEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS0DCSWNEN_SHIFT 2
+#define MT6325_RG_AUDMICBIAS0BYPASSEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS0BYPASSEN_SHIFT 3
+#define MT6325_RG_AUDPWDBMICBIAS1_MASK 0x1
+#define MT6325_RG_AUDPWDBMICBIAS1_SHIFT 4
+#define MT6325_RG_AUDMICBIAS1DCSWPEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS1DCSWPEN_SHIFT 5
+#define MT6325_RG_AUDMICBIAS1DCSWNEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS1DCSWNEN_SHIFT 6
+#define MT6325_RG_AUDMICBIAS1BYPASSEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS1BYPASSEN_SHIFT 7
+#define MT6325_RG_AUDMICBIASVREF_MASK 0x7
+#define MT6325_RG_AUDMICBIASVREF_SHIFT 8
+#define MT6325_RG_AUDMICBIASLOWPEN_MASK 0x1
+#define MT6325_RG_AUDMICBIASLOWPEN_SHIFT 11
+#define MT6325_RG_BANDGAPGEN_MASK 0x1
+#define MT6325_RG_BANDGAPGEN_SHIFT 12
+#define MT6325_RG_AUDENCSPAREVA28_MASK 0xFF
+#define MT6325_RG_AUDENCSPAREVA28_SHIFT 0
+#define MT6325_RG_AUDENCSPAREVA18_MASK 0xFF
+#define MT6325_RG_AUDENCSPAREVA18_SHIFT 8
+#define MT6325_RG_PLL_EN_MASK 0x1
+#define MT6325_RG_PLL_EN_SHIFT 0
+#define MT6325_RG_PLLBS_RST_MASK 0x1
+#define MT6325_RG_PLLBS_RST_SHIFT 1
+#define MT6325_RG_PLL_DCKO_SEL_MASK 0x3
+#define MT6325_RG_PLL_DCKO_SEL_SHIFT 2
+#define MT6325_RG_PLL_DIV1_MASK 0x3F
+#define MT6325_RG_PLL_DIV1_SHIFT 4
+#define MT6325_RG_PLL_RLATCH_EN_MASK 0x1
+#define MT6325_RG_PLL_RLATCH_EN_SHIFT 10
+#define MT6325_RG_PLL_PDIV1_EN_MASK 0x1
+#define MT6325_RG_PLL_PDIV1_EN_SHIFT 11
+#define MT6325_RG_PLL_PDIV1_MASK 0xF
+#define MT6325_RG_PLL_PDIV1_SHIFT 12
+#define MT6325_RG_PLL_BC_MASK 0x3
+#define MT6325_RG_PLL_BC_SHIFT 0
+#define MT6325_RG_PLL_BP_MASK 0x3
+#define MT6325_RG_PLL_BP_SHIFT 2
+#define MT6325_RG_PLL_BR_MASK 0x3
+#define MT6325_RG_PLL_BR_SHIFT 4
+#define MT6325_RG_CKO_SEL_MASK 0x3
+#define MT6325_RG_CKO_SEL_SHIFT 6
+#define MT6325_RG_PLL_IBSEL_MASK 0x3
+#define MT6325_RG_PLL_IBSEL_SHIFT 8
+#define MT6325_RG_PLL_CKT_SEL_MASK 0x3
+#define MT6325_RG_PLL_CKT_SEL_SHIFT 10
+#define MT6325_RG_PLL_VCT_EN_MASK 0x1
+#define MT6325_RG_PLL_VCT_EN_SHIFT 12
+#define MT6325_RG_PLL_CKT_EN_MASK 0x1
+#define MT6325_RG_PLL_CKT_EN_SHIFT 13
+#define MT6325_RG_PLL_HPM_EN_MASK 0x1
+#define MT6325_RG_PLL_HPM_EN_SHIFT 14
+#define MT6325_RG_PLL_DCHP_EN_MASK 0x1
+#define MT6325_RG_PLL_DCHP_EN_SHIFT 15
+#define MT6325_RG_PLL_CDIV_MASK 0x7
+#define MT6325_RG_PLL_CDIV_SHIFT 0
+#define MT6325_RG_VCOBAND_MASK 0x7
+#define MT6325_RG_VCOBAND_SHIFT 3
+#define MT6325_RG_CKDRV_EN_MASK 0x1
+#define MT6325_RG_CKDRV_EN_SHIFT 6
+#define MT6325_RG_PLL_DCHP_AEN_MASK 0x1
+#define MT6325_RG_PLL_DCHP_AEN_SHIFT 7
+#define MT6325_RG_PLL_RSVA_MASK 0xFF
+#define MT6325_RG_PLL_RSVA_SHIFT 8
+#define MT6325_RG_AUDPREAMPLGAIN_MASK 0x7
+#define MT6325_RG_AUDPREAMPLGAIN_SHIFT 0
+#define MT6325_RG_AUDPREAMPRGAIN_MASK 0x7
+#define MT6325_RG_AUDPREAMPRGAIN_SHIFT 4
+#define MT6325_RG_DIVCKS_CHG_MASK 0x1
+#define MT6325_RG_DIVCKS_CHG_SHIFT 0
+#define MT6325_RG_DIVCKS_ON_MASK 0x1
+#define MT6325_RG_DIVCKS_ON_SHIFT 0
+#define MT6325_RG_DIVCKS_PRG_MASK 0x1FF
+#define MT6325_RG_DIVCKS_PRG_SHIFT 0
+#define MT6325_RG_DIVCKS_PWD_NCP_MASK 0x1
+#define MT6325_RG_DIVCKS_PWD_NCP_SHIFT 0
+#define MT6325_RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3
+#define MT6325_RG_DIVCKS_PWD_NCP_ST_SEL_SHIFT 0
+#define MT6325_AUXADC_DIG0_RSV0_MASK 0xFFFF
+#define MT6325_AUXADC_DIG0_RSV0_SHIFT 0
+#define MT6325_AUXADC_ADC_BUSY_IN_MASK 0x1FFF
+#define MT6325_AUXADC_ADC_BUSY_IN_SHIFT 0
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_PCHR_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_PCHR_SHIFT 13
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_SWCHR_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_SWCHR_SHIFT 14
+#define MT6325_AUXADC_RO_RSV0_MASK 0x1
+#define MT6325_AUXADC_RO_RSV0_SHIFT 15
+#define MT6325_AUXADC_ADC_BUSY_IN_VISMPS0_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_VISMPS0_SHIFT 11
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT_SHIFT 12
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT2_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT 13
+#define MT6325_AUXADC_ADC_BUSY_IN_THR1_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_THR1_SHIFT 14
+#define MT6325_AUXADC_ADC_BUSY_IN_THR2_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_THR2_SHIFT 15
+#define MT6325_AUXADC_RQST0_RSV1_MASK 0xFF
+#define MT6325_AUXADC_RQST0_RSV1_SHIFT 0
+#define MT6325_AUXADC_RQST0_RSV0_MASK 0xFF
+#define MT6325_AUXADC_RQST0_RSV0_SHIFT 8
+#define MT6325_AUXADC_RQST0_SET_MASK 0xFFFF
+#define MT6325_AUXADC_RQST0_SET_SHIFT 0
+#define MT6325_AUXADC_RQST0_CLR_MASK 0xFFFF
+#define MT6325_AUXADC_RQST0_CLR_SHIFT 0
+#define MT6325_AUXADC_RQST_RSV0_MASK 0xF
+#define MT6325_AUXADC_RQST_RSV0_SHIFT 0
+#define MT6325_AUXADC_RQST_CH4_BY_MD_MASK 0x1
+#define MT6325_AUXADC_RQST_CH4_BY_MD_SHIFT 4
+#define MT6325_AUXADC_RQST_CH7_BY_MD_MASK 0x1
+#define MT6325_AUXADC_RQST_CH7_BY_MD_SHIFT 7
+#define MT6325_AUXADC_RQST_CH7_BY_GPS_MASK 0x1
+#define MT6325_AUXADC_RQST_CH7_BY_GPS_SHIFT 8
+#define MT6325_AUXADC_RQST_RSV1_MASK 0x7F
+#define MT6325_AUXADC_RQST_RSV1_SHIFT 9
+#define MT6325_AUXADC_RQST1_SET_MASK 0xFFFF
+#define MT6325_AUXADC_RQST1_SET_SHIFT 0
+#define MT6325_AUXADC_RQST1_CLR_MASK 0xFFFF
+#define MT6325_AUXADC_RQST1_CLR_SHIFT 0
+#define MT6325_AUXADC_CK_ON_EXTD_MASK 0x3F
+#define MT6325_AUXADC_CK_ON_EXTD_SHIFT 0
+#define MT6325_AUXADC_STRUP_CK_ON_ENB_MASK 0x1
+#define MT6325_AUXADC_STRUP_CK_ON_ENB_SHIFT 10
+#define MT6325_AUXADC_ADC_RDY_WAKEUP_CLR_MASK 0x1
+#define MT6325_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT 11
+#define MT6325_AUXADC_SRCLKEN_CK_EN_MASK 0x1
+#define MT6325_AUXADC_SRCLKEN_CK_EN_SHIFT 12
+#define MT6325_AUXADC_CK_AON_GPS_MASK 0x1
+#define MT6325_AUXADC_CK_AON_GPS_SHIFT 13
+#define MT6325_AUXADC_CK_AON_MD_MASK 0x1
+#define MT6325_AUXADC_CK_AON_MD_SHIFT 14
+#define MT6325_AUXADC_CK_AON_MASK 0x1
+#define MT6325_AUXADC_CK_AON_SHIFT 15
+#define MT6325_AUXADC_PMU_THR_PDN_SW_MASK 0x1
+#define MT6325_AUXADC_PMU_THR_PDN_SW_SHIFT 0
+#define MT6325_AUXADC_PMU_THR_PDN_SEL_MASK 0x1
+#define MT6325_AUXADC_PMU_THR_PDN_SEL_SHIFT 1
+#define MT6325_AUXADC_PMU_THR_PDN_STATUS_MASK 0x1
+#define MT6325_AUXADC_PMU_THR_PDN_STATUS_SHIFT 2
+#define MT6325_AUXADC_RO_RSV1_MASK 0x7F
+#define MT6325_AUXADC_RO_RSV1_SHIFT 3
+#define MT6325_AUXADC_DIG1_RSV0_MASK 0x3F
+#define MT6325_AUXADC_DIG1_RSV0_SHIFT 10
+#define MT6325_AUXADC_THR_DEBT_MAX_MASK 0xFF
+#define MT6325_AUXADC_THR_DEBT_MAX_SHIFT 0
+#define MT6325_AUXADC_THR_DEBT_MIN_MASK 0xFF
+#define MT6325_AUXADC_THR_DEBT_MIN_SHIFT 8
+#define MT6325_AUXADC_THR_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_AUXADC_THR_DET_PRD_15_0_SHIFT 0
+#define MT6325_AUXADC_THR_DET_PRD_19_16_MASK 0xF
+#define MT6325_AUXADC_THR_DET_PRD_19_16_SHIFT 0
+#define MT6325_AUXADC_THR_VOLT_MAX_MASK 0xFFF
+#define MT6325_AUXADC_THR_VOLT_MAX_SHIFT 0
+#define MT6325_AUXADC_THR_IRQ_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_THR_IRQ_EN_MAX_SHIFT 12
+#define MT6325_AUXADC_THR_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_THR_EN_MAX_SHIFT 13
+#define MT6325_AUXADC_THR_MAX_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_THR_MAX_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_THR_VOLT_MIN_MASK 0xFFF
+#define MT6325_AUXADC_THR_VOLT_MIN_SHIFT 0
+#define MT6325_AUXADC_THR_IRQ_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_THR_IRQ_EN_MIN_SHIFT 12
+#define MT6325_AUXADC_THR_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_THR_EN_MIN_SHIFT 13
+#define MT6325_AUXADC_THR_MIN_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_THR_MIN_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_RG_AUXADC_FGADC_START_SW_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_START_SW_SHIFT 0
+#define MT6325_RG_AUXADC_FGADC_START_SEL_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_START_SEL_SHIFT 1
+#define MT6325_RG_AUXADC_FGADC_R_SW_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_R_SW_SHIFT 2
+#define MT6325_RG_AUXADC_FGADC_R_SEL_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_R_SEL_SHIFT 3
+#define MT6325_AUXADC_DIG0_RSV2_MASK 0x1
+#define MT6325_AUXADC_DIG0_RSV2_SHIFT 4
+#define MT6325_AUXADC_DIG1_RSV2_MASK 0xF
+#define MT6325_AUXADC_DIG1_RSV2_SHIFT 5
+#define MT6325_AUXADC_ACCDET_AUTO_SPL_MASK 0x1
+#define MT6325_AUXADC_ACCDET_AUTO_SPL_SHIFT 9
+#define MT6325_AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
+#define MT6325_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT 10
+#define MT6325_AUXADC_AUTORPT_PRD_MASK 0x3FF
+#define MT6325_AUXADC_AUTORPT_PRD_SHIFT 0
+#define MT6325_AUXADC_AUTORPT_EN_MASK 0x1
+#define MT6325_AUXADC_AUTORPT_EN_SHIFT 15
+#define MT6325_AUXADC_IMPEDANCE_CNT_MASK 0x3F
+#define MT6325_AUXADC_IMPEDANCE_CNT_SHIFT 0
+#define MT6325_AUXADC_IMPEDANCE_CHSEL_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_CHSEL_SHIFT 6
+#define MT6325_AUXADC_IMPEDANCE_IRQ_CLR_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_IRQ_CLR_SHIFT 7
+#define MT6325_AUXADC_IMPEDANCE_IRQ_STATUS_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT 8
+#define MT6325_AUXADC_CLR_IMP_CNT_STOP_MASK 0x1
+#define MT6325_AUXADC_CLR_IMP_CNT_STOP_SHIFT 14
+#define MT6325_AUXADC_IMPEDANCE_MODE_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_MODE_SHIFT 15
+#define MT6325_AUXADC_VISMPS0_DEBT_MAX_MASK 0xFF
+#define MT6325_AUXADC_VISMPS0_DEBT_MAX_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_DEBT_MIN_MASK 0xFF
+#define MT6325_AUXADC_VISMPS0_DEBT_MIN_SHIFT 8
+#define MT6325_AUXADC_VISMPS0_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_AUXADC_VISMPS0_DET_PRD_15_0_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_DET_PRD_19_16_MASK 0xF
+#define MT6325_AUXADC_VISMPS0_DET_PRD_19_16_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_VOLT_MAX_MASK 0xFFF
+#define MT6325_AUXADC_VISMPS0_VOLT_MAX_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MAX_SHIFT 12
+#define MT6325_AUXADC_VISMPS0_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_EN_MAX_SHIFT 13
+#define MT6325_AUXADC_VISMPS0_MAX_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_MAX_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_VISMPS0_VOLT_MIN_MASK 0xFFF
+#define MT6325_AUXADC_VISMPS0_VOLT_MIN_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MIN_SHIFT 12
+#define MT6325_AUXADC_VISMPS0_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_EN_MIN_SHIFT 13
+#define MT6325_AUXADC_VISMPS0_MIN_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_MIN_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DEBT_MAX_MASK 0xFF
+#define MT6325_AUXADC_LBAT2_DEBT_MAX_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DEBT_MIN_MASK 0xFF
+#define MT6325_AUXADC_LBAT2_DEBT_MIN_SHIFT 8
+#define MT6325_AUXADC_LBAT2_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_AUXADC_LBAT2_DET_PRD_15_0_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DET_PRD_19_16_MASK 0xF
+#define MT6325_AUXADC_LBAT2_DET_PRD_19_16_SHIFT 0
+#define MT6325_AUXADC_LBAT2_VOLT_MAX_MASK 0xFFF
+#define MT6325_AUXADC_LBAT2_VOLT_MAX_SHIFT 0
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT 12
+#define MT6325_AUXADC_LBAT2_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_LBAT2_EN_MAX_SHIFT 13
+#define MT6325_AUXADC_LBAT2_MAX_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_LBAT2_MAX_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_LBAT2_VOLT_MIN_MASK 0xFFF
+#define MT6325_AUXADC_LBAT2_VOLT_MIN_SHIFT 0
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT 12
+#define MT6325_AUXADC_LBAT2_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_LBAT2_EN_MIN_SHIFT 13
+#define MT6325_AUXADC_LBAT2_MIN_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_LBAT2_MIN_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_RG_ADC_OUT_BATSNS_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_BATSNS_SHIFT 0
+#define MT6325_RG_ADC_RDY_BATSNS_MASK 0x1
+#define MT6325_RG_ADC_RDY_BATSNS_SHIFT 15
+#define MT6325_RG_ADC_OUT_ISENSE_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_ISENSE_SHIFT 0
+#define MT6325_RG_ADC_RDY_ISENSE_MASK 0x1
+#define MT6325_RG_ADC_RDY_ISENSE_SHIFT 15
+#define MT6325_RG_ADC_OUT_VCDT_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_VCDT_SHIFT 0
+#define MT6325_RG_ADC_RDY_VCDT_MASK 0x1
+#define MT6325_RG_ADC_RDY_VCDT_SHIFT 15
+#define MT6325_RG_ADC_OUT_BATON1_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_BATON1_SHIFT 0
+#define MT6325_RG_ADC_RDY_BATON1_MASK 0x1
+#define MT6325_RG_ADC_RDY_BATON1_SHIFT 15
+#define MT6325_RG_ADC_OUT_THR_SENSE1_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_THR_SENSE1_SHIFT 0
+#define MT6325_RG_ADC_RDY_THR_SENSE1_MASK 0x1
+#define MT6325_RG_ADC_RDY_THR_SENSE1_SHIFT 15
+#define MT6325_RG_ADC_OUT_THR_MD_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_THR_MD_SHIFT 0
+#define MT6325_RG_ADC_RDY_THR_MD_MASK 0x1
+#define MT6325_RG_ADC_RDY_THR_MD_SHIFT 15
+#define MT6325_RG_ADC_OUT_BATON2_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_BATON2_SHIFT 0
+#define MT6325_RG_ADC_RDY_BATON2_MASK 0x1
+#define MT6325_RG_ADC_RDY_BATON2_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH5_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH5_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH5_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH5_SHIFT 15
+#define MT6325_RG_ADC_OUT_WAKEUP_PCHR_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_WAKEUP_PCHR_SHIFT 0
+#define MT6325_RG_ADC_RDY_WAKEUP_PCHR_MASK 0x1
+#define MT6325_RG_ADC_RDY_WAKEUP_PCHR_SHIFT 15
+#define MT6325_RG_ADC_OUT_WAKEUP_SWCHR_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_WAKEUP_SWCHR_SHIFT 0
+#define MT6325_RG_ADC_RDY_WAKEUP_SWCHR_MASK 0x1
+#define MT6325_RG_ADC_RDY_WAKEUP_SWCHR_SHIFT 15
+#define MT6325_RG_ADC_OUT_LBAT_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_LBAT_SHIFT 0
+#define MT6325_RG_ADC_RDY_LBAT_MASK 0x1
+#define MT6325_RG_ADC_RDY_LBAT_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH6_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH6_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH6_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH6_SHIFT 15
+#define MT6325_RG_ADC_RDY_GPS_MASK 0x1
+#define MT6325_RG_ADC_RDY_GPS_SHIFT 15
+#define MT6325_RG_ADC_OUT_GPS_MASK 0xFFFF
+#define MT6325_RG_ADC_OUT_GPS_SHIFT 0
+#define MT6325_RG_ADC_OUT_GPS_LSB_MASK 0x1
+#define MT6325_RG_ADC_OUT_GPS_LSB_SHIFT 15
+#define MT6325_RG_ADC_OUT_MD_MASK 0xFFFF
+#define MT6325_RG_ADC_OUT_MD_SHIFT 0
+#define MT6325_RG_ADC_OUT_MD_LSB_MASK 0x1
+#define MT6325_RG_ADC_OUT_MD_LSB_SHIFT 0
+#define MT6325_RG_ADC_RDY_MD_MASK 0x1
+#define MT6325_RG_ADC_RDY_MD_SHIFT 15
+#define MT6325_RG_ADC_OUT_INT_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_INT_SHIFT 0
+#define MT6325_RG_ADC_RDY_INT_MASK 0x1
+#define MT6325_RG_ADC_RDY_INT_SHIFT 15
+#define MT6325_RG_ADC_OUT_CIC_RAW_16_1_MASK 0xFFFF
+#define MT6325_RG_ADC_OUT_CIC_RAW_16_1_SHIFT 0
+#define MT6325_RG_ADC_OUT_CIC_RAW_0_MASK 0x1
+#define MT6325_RG_ADC_OUT_CIC_RAW_0_SHIFT 0
+#define MT6325_RG_ADC_BUSY_MASK 0x7FFF
+#define MT6325_RG_ADC_BUSY_SHIFT 1
+#define MT6325_RG_ADC_OUT_LBAT2_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_LBAT2_SHIFT 0
+#define MT6325_RG_ADC_RDY_LBAT2_MASK 0x1
+#define MT6325_RG_ADC_RDY_LBAT2_SHIFT 15
+#define MT6325_RG_ADC_OUT_THR_HW_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_THR_HW_SHIFT 0
+#define MT6325_RG_ADC_RDY_THR_HW_MASK 0x1
+#define MT6325_RG_ADC_RDY_THR_HW_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH8_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH8_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH8_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH8_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH9_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH9_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH9_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH9_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH10_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH10_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH10_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH10_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH11_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH11_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH11_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH11_SHIFT 15
+#define MT6325_RG_ADC_OUT_VISMPS0_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_VISMPS0_SHIFT 0
+#define MT6325_RG_ADC_RDY_VISMPS0_MASK 0x1
+#define MT6325_RG_ADC_RDY_VISMPS0_SHIFT 15
+#define MT6325_RG_ADC_OUT_FGADC_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_FGADC_SHIFT 0
+#define MT6325_RG_ADC_RDY_FGADC_MASK 0x1
+#define MT6325_RG_ADC_RDY_FGADC_SHIFT 15
+#define MT6325_RG_ADC_OUT_IMP_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_IMP_SHIFT 0
+#define MT6325_RG_ADC_RDY_IMP_MASK 0x1
+#define MT6325_RG_ADC_RDY_IMP_SHIFT 15
+#define MT6325_RG_ADC_OUT_IMP_AVG_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_IMP_AVG_SHIFT 0
+#define MT6325_RG_ADC_RDY_IMP_AVG_MASK 0x1
+#define MT6325_RG_ADC_RDY_IMP_AVG_SHIFT 15
+#define MT6325_RG_ADC_OUT_FGADC2_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_FGADC2_SHIFT 0
+#define MT6325_RG_ADC_RDY_FGADC2_MASK 0x1
+#define MT6325_RG_ADC_RDY_FGADC2_SHIFT 15
+#define MT6325_RG_SW_GAIN_TRIM_MASK 0xFFFF
+#define MT6325_RG_SW_GAIN_TRIM_SHIFT 0
+#define MT6325_RG_SW_OFFSET_TRIM_MASK 0xFFFF
+#define MT6325_RG_SW_OFFSET_TRIM_SHIFT 0
+#define MT6325_RG_ADC_PWDB_MASK 0x1
+#define MT6325_RG_ADC_PWDB_SHIFT 0
+#define MT6325_RG_ADC_PWDB_SWCTRL_MASK 0x1
+#define MT6325_RG_ADC_PWDB_SWCTRL_SHIFT 2
+#define MT6325_RG_ADC_CALI_RATE_MASK 0x3
+#define MT6325_RG_ADC_CALI_RATE_SHIFT 4
+#define MT6325_RG_ADC_CALI_EN_MASK 0x1
+#define MT6325_RG_ADC_CALI_EN_SHIFT 6
+#define MT6325_RG_ADC_CALI_FORCE_MASK 0x1
+#define MT6325_RG_ADC_CALI_FORCE_SHIFT 7
+#define MT6325_RG_ADC_AUTORST_RANGE_MASK 0x3
+#define MT6325_RG_ADC_AUTORST_RANGE_SHIFT 8
+#define MT6325_RG_ADC_AUTORST_EN_MASK 0x1
+#define MT6325_RG_ADC_AUTORST_EN_SHIFT 10
+#define MT6325_RG_ADC_LATCH_EDGE_MASK 0x1
+#define MT6325_RG_ADC_LATCH_EDGE_SHIFT 11
+#define MT6325_RG_ADC_FILTER_ORDER_MASK 0x1
+#define MT6325_RG_ADC_FILTER_ORDER_SHIFT 12
+#define MT6325_RG_ADC_SWCTRL_EN_MASK 0x1
+#define MT6325_RG_ADC_SWCTRL_EN_SHIFT 0
+#define MT6325_AUXADC_ADCIN_VSEN_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_VSEN_EN_SHIFT 1
+#define MT6325_AUXADC_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT 2
+#define MT6325_AUXADC_ADCIN_VBAT_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_VBAT_EN_SHIFT 4
+#define MT6325_AUXADC_ADCIN_CHR_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_CHR_EN_SHIFT 5
+#define MT6325_RG_AUXADC_CHSEL_MASK 0xF
+#define MT6325_RG_AUXADC_CHSEL_SHIFT 12
+#define MT6325_RG_LBAT_DEBT_MAX_MASK 0xFF
+#define MT6325_RG_LBAT_DEBT_MAX_SHIFT 0
+#define MT6325_RG_LBAT_DEBT_MIN_MASK 0xFF
+#define MT6325_RG_LBAT_DEBT_MIN_SHIFT 8
+#define MT6325_RG_LBAT_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_RG_LBAT_DET_PRD_15_0_SHIFT 0
+#define MT6325_RG_LBAT_DET_PRD_19_16_MASK 0xF
+#define MT6325_RG_LBAT_DET_PRD_19_16_SHIFT 0
+#define MT6325_RG_LBAT_VOLT_MAX_MASK 0xFFF
+#define MT6325_RG_LBAT_VOLT_MAX_SHIFT 0
+#define MT6325_RG_LBAT_IRQ_EN_MAX_MASK 0x1
+#define MT6325_RG_LBAT_IRQ_EN_MAX_SHIFT 12
+#define MT6325_RG_LBAT_EN_MAX_MASK 0x1
+#define MT6325_RG_LBAT_EN_MAX_SHIFT 13
+#define MT6325_RG_LBAT_MAX_IRQ_B_MASK 0x1
+#define MT6325_RG_LBAT_MAX_IRQ_B_SHIFT 15
+#define MT6325_RG_LBAT_VOLT_MIN_MASK 0xFFF
+#define MT6325_RG_LBAT_VOLT_MIN_SHIFT 0
+#define MT6325_RG_LBAT_IRQ_EN_MIN_MASK 0x1
+#define MT6325_RG_LBAT_IRQ_EN_MIN_SHIFT 12
+#define MT6325_RG_LBAT_EN_MIN_MASK 0x1
+#define MT6325_RG_LBAT_EN_MIN_SHIFT 13
+#define MT6325_RG_LBAT_MIN_IRQ_B_MASK 0x1
+#define MT6325_RG_LBAT_MIN_IRQ_B_SHIFT 15
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_RG_DATA_REUSE_SEL_MASK 0x3
+#define MT6325_RG_DATA_REUSE_SEL_SHIFT 3
+#define MT6325_RG_AUXADC_BIST_ENB_MASK 0x1
+#define MT6325_RG_AUXADC_BIST_ENB_SHIFT 5
+#define MT6325_RG_OSR_MASK 0x7
+#define MT6325_RG_OSR_SHIFT 10
+#define MT6325_RG_OSR_GPS_MASK 0x7
+#define MT6325_RG_OSR_GPS_SHIFT 13
+#define MT6325_RG_ADC_TRIM_CH7_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH7_SEL_SHIFT 0
+#define MT6325_RG_ADC_TRIM_CH6_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH6_SEL_SHIFT 2
+#define MT6325_RG_ADC_TRIM_CH5_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH5_SEL_SHIFT 4
+#define MT6325_RG_ADC_TRIM_CH4_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH4_SEL_SHIFT 6
+#define MT6325_RG_ADC_TRIM_CH3_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH3_SEL_SHIFT 8
+#define MT6325_RG_ADC_TRIM_CH2_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH2_SEL_SHIFT 10
+#define MT6325_RG_ADC_TRIM_CH0_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH0_SEL_SHIFT 14
+#define MT6325_RG_VBUF_CALEN_MASK 0x1
+#define MT6325_RG_VBUF_CALEN_SHIFT 0
+#define MT6325_RG_VBUF_EXTEN_MASK 0x1
+#define MT6325_RG_VBUF_EXTEN_SHIFT 1
+#define MT6325_RG_VBUF_BYP_MASK 0x1
+#define MT6325_RG_VBUF_BYP_SHIFT 2
+#define MT6325_RG_VBUF_EN_MASK 0x1
+#define MT6325_RG_VBUF_EN_SHIFT 4
+#define MT6325_RG_SOURCE_LBAT_SEL_MASK 0x1
+#define MT6325_RG_SOURCE_LBAT_SEL_SHIFT 15
+#define MT6325_EFUSE_GAIN_CH0_TRIM_MASK 0x1FF
+#define MT6325_EFUSE_GAIN_CH0_TRIM_SHIFT 0
+#define MT6325_EFUSE_OFFSET_CH0_TRIM_MASK 0xFF
+#define MT6325_EFUSE_OFFSET_CH0_TRIM_SHIFT 0
+#define MT6325_EFUSE_GAIN_CH4_TRIM_MASK 0x1FF
+#define MT6325_EFUSE_GAIN_CH4_TRIM_SHIFT 0
+#define MT6325_EFUSE_OFFSET_CH4_TRIM_MASK 0xFF
+#define MT6325_EFUSE_OFFSET_CH4_TRIM_SHIFT 0
+#define MT6325_EFUSE_GAIN_CH7_TRIM_MASK 0xFFFF
+#define MT6325_EFUSE_GAIN_CH7_TRIM_SHIFT 0
+#define MT6325_EFUSE_OFFSET_CH7_TRIM_MASK 0xFFFF
+#define MT6325_EFUSE_OFFSET_CH7_TRIM_SHIFT 0
+#define MT6325_RG_ADC_IBIAS_MASK 0x3
+#define MT6325_RG_ADC_IBIAS_SHIFT 0
+#define MT6325_RG_ADC_RST_MASK 0x1
+#define MT6325_RG_ADC_RST_SHIFT 2
+#define MT6325_RG_ADC_LP_EN_MASK 0x1
+#define MT6325_RG_ADC_LP_EN_SHIFT 3
+#define MT6325_RG_ADC_INPUT_SHORT_MASK 0x1
+#define MT6325_RG_ADC_INPUT_SHORT_SHIFT 4
+#define MT6325_RG_ADC_CHOPPER_EN_MASK 0x1
+#define MT6325_RG_ADC_CHOPPER_EN_SHIFT 5
+#define MT6325_RG_VPWDB_ADC_MASK 0x1
+#define MT6325_RG_VPWDB_ADC_SHIFT 6
+#define MT6325_RG_VREF18_EN_MASK 0x1
+#define MT6325_RG_VREF18_EN_SHIFT 7
+#define MT6325_RG_ADC_CHS_SEL_MASK 0x3
+#define MT6325_RG_ADC_CHS_SEL_SHIFT 8
+#define MT6325_RG_ADC_DVREF_CAL_MASK 0x1
+#define MT6325_RG_ADC_DVREF_CAL_SHIFT 14
+#define MT6325_RG_ADC_DENB_MASK 0x1
+#define MT6325_RG_ADC_DENB_SHIFT 15
+#define MT6325_RG_ADC_SLEEP_MODE_EN_MASK 0x1
+#define MT6325_RG_ADC_SLEEP_MODE_EN_SHIFT 0
+#define MT6325_RG_ADC_GPS_STATUS_MASK 0x1
+#define MT6325_RG_ADC_GPS_STATUS_SHIFT 1
+#define MT6325_RG_ADC_RSV_BIT_MASK 0x1
+#define MT6325_RG_ADC_RSV_BIT_SHIFT 2
+#define MT6325_RG_ADC_TEST_MODE_EN_MASK 0x1
+#define MT6325_RG_ADC_TEST_MODE_EN_SHIFT 3
+#define MT6325_RG_ADC_TEST_OUT_SEL_MASK 0x1
+#define MT6325_RG_ADC_TEST_OUT_SEL_SHIFT 4
+#define MT6325_RG_DECI_BYPASS_EN_MASK 0x1
+#define MT6325_RG_DECI_BYPASS_EN_SHIFT 5
+#define MT6325_RG_ADC_CLK_AON_MASK 0x1
+#define MT6325_RG_ADC_CLK_AON_SHIFT 7
+#define MT6325_RG_ADC_DECI_FORCE_MASK 0x1
+#define MT6325_RG_ADC_DECI_FORCE_SHIFT 12
+#define MT6325_RG_ADC_DECI_GDLY_MASK 0x3
+#define MT6325_RG_ADC_DECI_GDLY_SHIFT 14
+#define MT6325_RG_MD_RQST_MASK 0x1
+#define MT6325_RG_MD_RQST_SHIFT 15
+#define MT6325_RG_GPS_RQST_MASK 0x1
+#define MT6325_RG_GPS_RQST_SHIFT 15
+#define MT6325_RG_AP_RQST_LIST_MASK 0x1FF
+#define MT6325_RG_AP_RQST_LIST_SHIFT 0
+#define MT6325_RG_AP_RQST_MASK 0x1
+#define MT6325_RG_AP_RQST_SHIFT 15
+#define MT6325_RG_AP_RQST_LIST_RSV_MASK 0xFF
+#define MT6325_RG_AP_RQST_LIST_RSV_SHIFT 0
+#define MT6325_RG_ADC_OUT_TRIM_ENB_MASK 0x1
+#define MT6325_RG_ADC_OUT_TRIM_ENB_SHIFT 1
+#define MT6325_RG_ADC_TRIM_COMP_MASK 0x1
+#define MT6325_RG_ADC_TRIM_COMP_SHIFT 2
+#define MT6325_RG_ADC_2S_COMP_ENB_MASK 0x1
+#define MT6325_RG_ADC_2S_COMP_ENB_SHIFT 3
+#define MT6325_RG_CIC_OUT_RAW_MASK 0x1
+#define MT6325_RG_CIC_OUT_RAW_SHIFT 4
+#define MT6325_RG_DATA_SKIP_ENB_MASK 0x1
+#define MT6325_RG_DATA_SKIP_ENB_SHIFT 5
+#define MT6325_RG_DATA_SKIP_NUM_MASK 0x3
+#define MT6325_RG_DATA_SKIP_NUM_SHIFT 6
+#define MT6325_RG_ADC_REV_MASK 0xFF
+#define MT6325_RG_ADC_REV_SHIFT 0
+#define MT6325_RG_DECI_GDLY_SEL_MODE_MASK 0x1
+#define MT6325_RG_DECI_GDLY_SEL_MODE_SHIFT 0
+#define MT6325_RG_DECI_GDLY_VREF18_SELB_MASK 0x1
+#define MT6325_RG_DECI_GDLY_VREF18_SELB_SHIFT 1
+#define MT6325_RG_ADC_RSV1_MASK 0x1FFF
+#define MT6325_RG_ADC_RSV1_SHIFT 2
+#define MT6325_RG_VREF18_ENB_MASK 0x1
+#define MT6325_RG_VREF18_ENB_SHIFT 15
+#define MT6325_RG_ADC_MD_STATUS_MASK 0x1
+#define MT6325_RG_ADC_MD_STATUS_SHIFT 0
+#define MT6325_RG_ADC_RSV2_MASK 0x3FFF
+#define MT6325_RG_ADC_RSV2_SHIFT 1
+#define MT6325_RG_VREF18_ENB_MD_MASK 0x1
+#define MT6325_RG_VREF18_ENB_MD_SHIFT 15
+#define MT6325_RG_AUDACCDETVTHBCAL_MASK 0x1
+#define MT6325_RG_AUDACCDETVTHBCAL_SHIFT 0
+#define MT6325_RG_AUDACCDETVTHACAL_MASK 0x1
+#define MT6325_RG_AUDACCDETVTHACAL_SHIFT 1
+#define MT6325_RG_AUDACCDETANASWCTRLENB_MASK 0x1
+#define MT6325_RG_AUDACCDETANASWCTRLENB_SHIFT 2
+#define MT6325_RG_ACCDETSEL_MASK 0x1
+#define MT6325_RG_ACCDETSEL_SHIFT 3
+#define MT6325_RG_AUDACCDETSWCTRL_MASK 0x7
+#define MT6325_RG_AUDACCDETSWCTRL_SHIFT 4
+#define MT6325_RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
+#define MT6325_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT 7
+#define MT6325_RG_AUDACCDETTVDET_MASK 0x1
+#define MT6325_RG_AUDACCDETTVDET_SHIFT 8
+#define MT6325_RG_AUDACCDETVIN1PULLLOW_MASK 0x1
+#define MT6325_RG_AUDACCDETVIN1PULLLOW_SHIFT 9
+#define MT6325_AUDACCDETAUXADCSWCTRL_MASK 0x1
+#define MT6325_AUDACCDETAUXADCSWCTRL_SHIFT 10
+#define MT6325_AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
+#define MT6325_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 11
+#define MT6325_RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
+#define MT6325_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT 12
+#define MT6325_RG_AUDACCDETRSV_MASK 0x3
+#define MT6325_RG_AUDACCDETRSV_SHIFT 13
+#define MT6325_ACCDET_EN_MASK 0x1
+#define MT6325_ACCDET_EN_SHIFT 0
+#define MT6325_ACCDET_SEQ_INIT_MASK 0x1
+#define MT6325_ACCDET_SEQ_INIT_SHIFT 1
+#define MT6325_ACCDET_EINTDET_EN_MASK 0x1
+#define MT6325_ACCDET_EINTDET_EN_SHIFT 2
+#define MT6325_ACCDET_EINT_SEQ_INIT_MASK 0x1
+#define MT6325_ACCDET_EINT_SEQ_INIT_SHIFT 3
+#define MT6325_ACCDET_NEGVDET_EN_MASK 0x1
+#define MT6325_ACCDET_NEGVDET_EN_SHIFT 4
+#define MT6325_ACCDET_NEGVDET_EN_CTRL_MASK 0x1
+#define MT6325_ACCDET_NEGVDET_EN_CTRL_SHIFT 5
+#define MT6325_ACCDET_CMP_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_CMP_PWM_EN_SHIFT 0
+#define MT6325_ACCDET_VTH_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_VTH_PWM_EN_SHIFT 1
+#define MT6325_ACCDET_MBIAS_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_MBIAS_PWM_EN_SHIFT 2
+#define MT6325_ACCDET_EINT_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_EINT_PWM_EN_SHIFT 3
+#define MT6325_ACCDET_CMP_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_CMP_PWM_IDLE_SHIFT 4
+#define MT6325_ACCDET_VTH_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_VTH_PWM_IDLE_SHIFT 5
+#define MT6325_ACCDET_MBIAS_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_MBIAS_PWM_IDLE_SHIFT 6
+#define MT6325_ACCDET_EINT_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_EINT_PWM_IDLE_SHIFT 7
+#define MT6325_ACCDET_PWM_WIDTH_MASK 0xFFFF
+#define MT6325_ACCDET_PWM_WIDTH_SHIFT 0
+#define MT6325_ACCDET_PWM_THRESH_MASK 0xFFFF
+#define MT6325_ACCDET_PWM_THRESH_SHIFT 0
+#define MT6325_ACCDET_RISE_DELAY_MASK 0x7FFF
+#define MT6325_ACCDET_RISE_DELAY_SHIFT 0
+#define MT6325_ACCDET_FALL_DELAY_MASK 0x1
+#define MT6325_ACCDET_FALL_DELAY_SHIFT 15
+#define MT6325_ACCDET_DEBOUNCE0_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE0_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE1_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE1_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE2_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE2_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE3_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE3_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE4_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE4_SHIFT 0
+#define MT6325_ACCDET_IVAL_CUR_IN_MASK 0x3
+#define MT6325_ACCDET_IVAL_CUR_IN_SHIFT 0
+#define MT6325_ACCDET_EINT_IVAL_CUR_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_CUR_IN_SHIFT 2
+#define MT6325_ACCDET_IVAL_SAM_IN_MASK 0x3
+#define MT6325_ACCDET_IVAL_SAM_IN_SHIFT 4
+#define MT6325_ACCDET_EINT_IVAL_SAM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_SAM_IN_SHIFT 6
+#define MT6325_ACCDET_IVAL_MEM_IN_MASK 0x3
+#define MT6325_ACCDET_IVAL_MEM_IN_SHIFT 8
+#define MT6325_ACCDET_EINT_IVAL_MEM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_MEM_IN_SHIFT 10
+#define MT6325_ACCDET_EINT_IVAL_SEL_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_SEL_SHIFT 14
+#define MT6325_ACCDET_IVAL_SEL_MASK 0x1
+#define MT6325_ACCDET_IVAL_SEL_SHIFT 15
+#define MT6325_ACCDET_IRQ_MASK 0x1
+#define MT6325_ACCDET_IRQ_SHIFT 0
+#define MT6325_ACCDET_NEGV_IRQ_MASK 0x1
+#define MT6325_ACCDET_NEGV_IRQ_SHIFT 1
+#define MT6325_ACCDET_EINT_IRQ_MASK 0x1
+#define MT6325_ACCDET_EINT_IRQ_SHIFT 2
+#define MT6325_ACCDET_IRQ_CLR_MASK 0x1
+#define MT6325_ACCDET_IRQ_CLR_SHIFT 8
+#define MT6325_ACCDET_NEGV_IRQ_CLR_MASK 0x1
+#define MT6325_ACCDET_NEGV_IRQ_CLR_SHIFT 9
+#define MT6325_ACCDET_EINT_IRQ_CLR_MASK 0x1
+#define MT6325_ACCDET_EINT_IRQ_CLR_SHIFT 10
+#define MT6325_ACCDET_EINT_IRQ_POLARITY_MASK 0x1
+#define MT6325_ACCDET_EINT_IRQ_POLARITY_SHIFT 15
+#define MT6325_ACCDET_TEST_MODE0_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE0_SHIFT 0
+#define MT6325_ACCDET_TEST_MODE1_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE1_SHIFT 1
+#define MT6325_ACCDET_TEST_MODE2_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE2_SHIFT 2
+#define MT6325_ACCDET_TEST_MODE3_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE3_SHIFT 3
+#define MT6325_ACCDET_TEST_MODE4_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE4_SHIFT 4
+#define MT6325_ACCDET_TEST_MODE5_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE5_SHIFT 5
+#define MT6325_ACCDET_PWM_SEL_MASK 0x3
+#define MT6325_ACCDET_PWM_SEL_SHIFT 6
+#define MT6325_ACCDET_IN_SW_MASK 0x3
+#define MT6325_ACCDET_IN_SW_SHIFT 8
+#define MT6325_ACCDET_CMP_EN_SW_MASK 0x1
+#define MT6325_ACCDET_CMP_EN_SW_SHIFT 12
+#define MT6325_ACCDET_VTH_EN_SW_MASK 0x1
+#define MT6325_ACCDET_VTH_EN_SW_SHIFT 13
+#define MT6325_ACCDET_MBIAS_EN_SW_MASK 0x1
+#define MT6325_ACCDET_MBIAS_EN_SW_SHIFT 14
+#define MT6325_ACCDET_PWM_EN_SW_MASK 0x1
+#define MT6325_ACCDET_PWM_EN_SW_SHIFT 15
+#define MT6325_ACCDET_IN_MASK 0x3
+#define MT6325_ACCDET_IN_SHIFT 0
+#define MT6325_ACCDET_CUR_IN_MASK 0x3
+#define MT6325_ACCDET_CUR_IN_SHIFT 2
+#define MT6325_ACCDET_SAM_IN_MASK 0x3
+#define MT6325_ACCDET_SAM_IN_SHIFT 4
+#define MT6325_ACCDET_MEM_IN_MASK 0x3
+#define MT6325_ACCDET_MEM_IN_SHIFT 6
+#define MT6325_ACCDET_STATE_MASK 0x7
+#define MT6325_ACCDET_STATE_SHIFT 8
+#define MT6325_ACCDET_MBIAS_CLK_MASK 0x1
+#define MT6325_ACCDET_MBIAS_CLK_SHIFT 12
+#define MT6325_ACCDET_VTH_CLK_MASK 0x1
+#define MT6325_ACCDET_VTH_CLK_SHIFT 13
+#define MT6325_ACCDET_CMP_CLK_MASK 0x1
+#define MT6325_ACCDET_CMP_CLK_SHIFT 14
+#define MT6325_DA_AUDACCDETAUXADCSWCTRL_MASK 0x1
+#define MT6325_DA_AUDACCDETAUXADCSWCTRL_SHIFT 15
+#define MT6325_ACCDET_EINT_DEB_SEL_MASK 0x1
+#define MT6325_ACCDET_EINT_DEB_SEL_SHIFT 0
+#define MT6325_ACCDET_EINT_DEBOUNCE_MASK 0x7
+#define MT6325_ACCDET_EINT_DEBOUNCE_SHIFT 4
+#define MT6325_ACCDET_EINT_PWM_THRESH_MASK 0x7
+#define MT6325_ACCDET_EINT_PWM_THRESH_SHIFT 8
+#define MT6325_ACCDET_EINT_PWM_WIDTH_MASK 0x3
+#define MT6325_ACCDET_EINT_PWM_WIDTH_SHIFT 12
+#define MT6325_ACCDET_NEGV_THRESH_MASK 0x1F
+#define MT6325_ACCDET_NEGV_THRESH_SHIFT 0
+#define MT6325_ACCDET_EINT_PWM_FALL_DELAY_MASK 0x1
+#define MT6325_ACCDET_EINT_PWM_FALL_DELAY_SHIFT 5
+#define MT6325_ACCDET_EINT_PWM_RISE_DELAY_MASK 0x3FF
+#define MT6325_ACCDET_EINT_PWM_RISE_DELAY_SHIFT 6
+#define MT6325_ACCDET_TEST_MODE13_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE13_SHIFT 1
+#define MT6325_ACCDET_TEST_MODE12_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE12_SHIFT 2
+#define MT6325_ACCDET_NVDETECTOUT_SW_MASK 0x1
+#define MT6325_ACCDET_NVDETECTOUT_SW_SHIFT 3
+#define MT6325_ACCDET_TEST_MODE11_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE11_SHIFT 5
+#define MT6325_ACCDET_TEST_MODE10_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE10_SHIFT 6
+#define MT6325_ACCDET_EINTCMPOUT_SW_MASK 0x1
+#define MT6325_ACCDET_EINTCMPOUT_SW_SHIFT 7
+#define MT6325_ACCDET_TEST_MODE9_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE9_SHIFT 9
+#define MT6325_ACCDET_TEST_MODE8_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE8_SHIFT 10
+#define MT6325_ACCDET_AUXADC_CTRL_SW_MASK 0x1
+#define MT6325_ACCDET_AUXADC_CTRL_SW_SHIFT 11
+#define MT6325_ACCDET_TEST_MODE7_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE7_SHIFT 13
+#define MT6325_ACCDET_TEST_MODE6_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE6_SHIFT 14
+#define MT6325_ACCDET_EINTCMP_EN_SW_MASK 0x1
+#define MT6325_ACCDET_EINTCMP_EN_SW_SHIFT 15
+#define MT6325_RG_NVCMPSWEN_MASK 0x1
+#define MT6325_RG_NVCMPSWEN_SHIFT 8
+#define MT6325_RG_NVMODSEL_MASK 0x1
+#define MT6325_RG_NVMODSEL_SHIFT 9
+#define MT6325_RG_SWBUFSWEN_MASK 0x1
+#define MT6325_RG_SWBUFSWEN_SHIFT 10
+#define MT6325_RG_SWBUFMODSEL_MASK 0x1
+#define MT6325_RG_SWBUFMODSEL_SHIFT 11
+#define MT6325_RG_NVDETVTH_MASK 0x1
+#define MT6325_RG_NVDETVTH_SHIFT 12
+#define MT6325_RG_NVDETCMPEN_MASK 0x1
+#define MT6325_RG_NVDETCMPEN_SHIFT 13
+#define MT6325_RG_EINTCONFIGACCDET_MASK 0x1
+#define MT6325_RG_EINTCONFIGACCDET_SHIFT 14
+#define MT6325_RG_EINTCOMPVTH_MASK 0x1
+#define MT6325_RG_EINTCOMPVTH_SHIFT 15
+#define MT6325_ACCDET_EINT_STATE_MASK 0x7
+#define MT6325_ACCDET_EINT_STATE_SHIFT 0
+#define MT6325_ACCDET_EINT_CUR_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_CUR_IN_SHIFT 8
+#define MT6325_ACCDET_EINT_SAM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_SAM_IN_SHIFT 9
+#define MT6325_ACCDET_EINT_MEM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_MEM_IN_SHIFT 10
+#define MT6325_NVDETECTOUT_MASK 0x1
+#define MT6325_NVDETECTOUT_SHIFT 13
+#define MT6325_EINTCMPOUT_MASK 0x1
+#define MT6325_EINTCMPOUT_SHIFT 14
+#define MT6325_NI_EINTCMPEN_MASK 0x1
+#define MT6325_NI_EINTCMPEN_SHIFT 15
+#define MT6325_ACCDET_NEGV_COUNT_IN_MASK 0x3F
+#define MT6325_ACCDET_NEGV_COUNT_IN_SHIFT 0
+#define MT6325_ACCDET_NEGV_EN_FINAL_MASK 0x1
+#define MT6325_ACCDET_NEGV_EN_FINAL_SHIFT 6
+#define MT6325_ACCDET_NEGV_COUNT_END_MASK 0x1
+#define MT6325_ACCDET_NEGV_COUNT_END_SHIFT 12
+#define MT6325_ACCDET_NEGV_MINU_MASK 0x1
+#define MT6325_ACCDET_NEGV_MINU_SHIFT 13
+#define MT6325_ACCDET_NEGV_ADD_MASK 0x1
+#define MT6325_ACCDET_NEGV_ADD_SHIFT 14
+#define MT6325_ACCDET_NEGV_CMP_MASK 0x1
+#define MT6325_ACCDET_NEGV_CMP_SHIFT 15
+#define MT6325_ACCDET_CUR_DEB_MASK 0xFFFF
+#define MT6325_ACCDET_CUR_DEB_SHIFT 0
+#define MT6325_ACCDET_EINT_CUR_DEB_MASK 0x7FFF
+#define MT6325_ACCDET_EINT_CUR_DEB_SHIFT 0
+#define MT6325_ACCDET_RSV_CON0_MASK 0xFFFF
+#define MT6325_ACCDET_RSV_CON0_SHIFT 0
+#define MT6325_ACCDET_RSV_CON1_MASK 0xFFFF
+#define MT6325_ACCDET_RSV_CON1_SHIFT 0
+#define MT6325_RG_VCDT_HV_EN_MASK 0x1
+#define MT6325_RG_VCDT_HV_EN_SHIFT 0
+#define MT6325_RGS_CHR_LDO_DET_MASK 0x1
+#define MT6325_RGS_CHR_LDO_DET_SHIFT 1
+#define MT6325_RG_PCHR_AUTOMODE_MASK 0x1
+#define MT6325_RG_PCHR_AUTOMODE_SHIFT 2
+#define MT6325_RG_CSDAC_EN_MASK 0x1
+#define MT6325_RG_CSDAC_EN_SHIFT 3
+#define MT6325_RG_CHR_EN_MASK 0x1
+#define MT6325_RG_CHR_EN_SHIFT 4
+#define MT6325_RGS_CHRDET_MASK 0x1
+#define MT6325_RGS_CHRDET_SHIFT 5
+#define MT6325_RGS_VCDT_LV_DET_MASK 0x1
+#define MT6325_RGS_VCDT_LV_DET_SHIFT 6
+#define MT6325_RGS_VCDT_HV_DET_MASK 0x1
+#define MT6325_RGS_VCDT_HV_DET_SHIFT 7
+#define MT6325_RG_VCDT_LV_VTH_MASK 0xF
+#define MT6325_RG_VCDT_LV_VTH_SHIFT 0
+#define MT6325_RG_VCDT_HV_VTH_MASK 0xF
+#define MT6325_RG_VCDT_HV_VTH_SHIFT 4
+#define MT6325_RG_VBAT_CV_EN_MASK 0x1
+#define MT6325_RG_VBAT_CV_EN_SHIFT 1
+#define MT6325_RG_VBAT_CC_EN_MASK 0x1
+#define MT6325_RG_VBAT_CC_EN_SHIFT 2
+#define MT6325_RG_CS_EN_MASK 0x1
+#define MT6325_RG_CS_EN_SHIFT 3
+#define MT6325_RGS_CS_DET_MASK 0x1
+#define MT6325_RGS_CS_DET_SHIFT 5
+#define MT6325_RGS_VBAT_CV_DET_MASK 0x1
+#define MT6325_RGS_VBAT_CV_DET_SHIFT 6
+#define MT6325_RGS_VBAT_CC_DET_MASK 0x1
+#define MT6325_RGS_VBAT_CC_DET_SHIFT 7
+#define MT6325_RG_VBAT_CV_VTH_MASK 0x3F
+#define MT6325_RG_VBAT_CV_VTH_SHIFT 0
+#define MT6325_RG_VBAT_CC_VTH_MASK 0x3
+#define MT6325_RG_VBAT_CC_VTH_SHIFT 6
+#define MT6325_RG_CS_VTH_MASK 0xF
+#define MT6325_RG_CS_VTH_SHIFT 0
+#define MT6325_RG_PCHR_TOHTC_MASK 0x7
+#define MT6325_RG_PCHR_TOHTC_SHIFT 0
+#define MT6325_RG_PCHR_TOLTC_MASK 0x7
+#define MT6325_RG_PCHR_TOLTC_SHIFT 4
+#define MT6325_RG_VBAT_OV_EN_MASK 0x1
+#define MT6325_RG_VBAT_OV_EN_SHIFT 0
+#define MT6325_RG_VBAT_OV_VTH_MASK 0xF
+#define MT6325_RG_VBAT_OV_VTH_SHIFT 1
+#define MT6325_RG_VBAT_OV_DEG_MASK 0x1
+#define MT6325_RG_VBAT_OV_DEG_SHIFT 5
+#define MT6325_RGS_VBAT_OV_DET_MASK 0x1
+#define MT6325_RGS_VBAT_OV_DET_SHIFT 6
+#define MT6325_RG_BATON_EN_MASK 0x1
+#define MT6325_RG_BATON_EN_SHIFT 0
+#define MT6325_RG_BATON_HT_EN_RSV0_MASK 0x1
+#define MT6325_RG_BATON_HT_EN_RSV0_SHIFT 1
+#define MT6325_BATON_TDET_EN_MASK 0x1
+#define MT6325_BATON_TDET_EN_SHIFT 2
+#define MT6325_RG_BATON_HT_TRIM_MASK 0x7
+#define MT6325_RG_BATON_HT_TRIM_SHIFT 4
+#define MT6325_RG_BATON_HT_TRIM_SET_MASK 0x1
+#define MT6325_RG_BATON_HT_TRIM_SET_SHIFT 7
+#define MT6325_RGS_BATON_UNDET_MASK 0x1
+#define MT6325_RGS_BATON_UNDET_SHIFT 12
+#define MT6325_RG_CSDAC_DATA_MASK 0x3FF
+#define MT6325_RG_CSDAC_DATA_SHIFT 0
+#define MT6325_RG_FRC_CSVTH_USBDL_MASK 0x1
+#define MT6325_RG_FRC_CSVTH_USBDL_SHIFT 0
+#define MT6325_RGS_PCHR_FLAG_OUT_MASK 0xF
+#define MT6325_RGS_PCHR_FLAG_OUT_SHIFT 0
+#define MT6325_RG_PCHR_FLAG_EN_MASK 0x1
+#define MT6325_RG_PCHR_FLAG_EN_SHIFT 4
+#define MT6325_RG_OTG_BVALID_EN_MASK 0x1
+#define MT6325_RG_OTG_BVALID_EN_SHIFT 5
+#define MT6325_RGS_OTG_BVALID_DET_MASK 0x1
+#define MT6325_RGS_OTG_BVALID_DET_SHIFT 6
+#define MT6325_RG_PCHR_FLAG_SEL_MASK 0x3F
+#define MT6325_RG_PCHR_FLAG_SEL_SHIFT 0
+#define MT6325_RG_PCHR_TESTMODE_MASK 0x1
+#define MT6325_RG_PCHR_TESTMODE_SHIFT 0
+#define MT6325_RG_CSDAC_TESTMODE_MASK 0x1
+#define MT6325_RG_CSDAC_TESTMODE_SHIFT 1
+#define MT6325_RG_PCHR_RST_MASK 0x1
+#define MT6325_RG_PCHR_RST_SHIFT 2
+#define MT6325_RG_PCHR_FT_CTRL_MASK 0x7
+#define MT6325_RG_PCHR_FT_CTRL_SHIFT 4
+#define MT6325_RG_CHRWDT_TD_MASK 0xF
+#define MT6325_RG_CHRWDT_TD_SHIFT 0
+#define MT6325_RG_CHRWDT_EN_MASK 0x1
+#define MT6325_RG_CHRWDT_EN_SHIFT 4
+#define MT6325_RG_CHRWDT_WR_MASK 0x1
+#define MT6325_RG_CHRWDT_WR_SHIFT 8
+#define MT6325_RG_PCHR_RV_MASK 0xFF
+#define MT6325_RG_PCHR_RV_SHIFT 0
+#define MT6325_RG_CHRWDT_INT_EN_MASK 0x1
+#define MT6325_RG_CHRWDT_INT_EN_SHIFT 0
+#define MT6325_RG_CHRWDT_FLAG_WR_MASK 0x1
+#define MT6325_RG_CHRWDT_FLAG_WR_SHIFT 1
+#define MT6325_RGS_CHRWDT_OUT_MASK 0x1
+#define MT6325_RGS_CHRWDT_OUT_SHIFT 2
+#define MT6325_RG_USBDL_RST_MASK 0x1
+#define MT6325_RG_USBDL_RST_SHIFT 2
+#define MT6325_RG_USBDL_SET_MASK 0x1
+#define MT6325_RG_USBDL_SET_SHIFT 3
+#define MT6325_RG_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VSEN_MUX_EN_SHIFT 8
+#define MT6325_RG_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 9
+#define MT6325_RG_ADCIN_VBAT_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VBAT_EN_SHIFT 10
+#define MT6325_RG_ADCIN_VSEN_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VSEN_EN_SHIFT 11
+#define MT6325_RG_ADCIN_CHR_EN_MASK 0x1
+#define MT6325_RG_ADCIN_CHR_EN_SHIFT 12
+#define MT6325_RG_UVLO_VTHL_MASK 0x1F
+#define MT6325_RG_UVLO_VTHL_SHIFT 0
+#define MT6325_RG_UVLO_VH_LAT_MASK 0x1
+#define MT6325_RG_UVLO_VH_LAT_SHIFT 7
+#define MT6325_RG_LBAT_INT_VTH_MASK 0x1F
+#define MT6325_RG_LBAT_INT_VTH_SHIFT 0
+#define MT6325_RG_BGR_RSEL_MASK 0x7
+#define MT6325_RG_BGR_RSEL_SHIFT 0
+#define MT6325_RG_BGR_UNCHOP_PH_MASK 0x1
+#define MT6325_RG_BGR_UNCHOP_PH_SHIFT 4
+#define MT6325_RG_BGR_UNCHOP_MASK 0x1
+#define MT6325_RG_BGR_UNCHOP_SHIFT 5
+#define MT6325_RG_BC11_BB_CTRL_MASK 0x1
+#define MT6325_RG_BC11_BB_CTRL_SHIFT 0
+#define MT6325_RG_BC11_RST_MASK 0x1
+#define MT6325_RG_BC11_RST_SHIFT 1
+#define MT6325_RG_BC11_VSRC_EN_MASK 0x3
+#define MT6325_RG_BC11_VSRC_EN_SHIFT 2
+#define MT6325_RG_BC11_ACA_EN_MASK 0x1
+#define MT6325_RG_BC11_ACA_EN_SHIFT 4
+#define MT6325_RGS_BC11_CMP_OUT_MASK 0x1
+#define MT6325_RGS_BC11_CMP_OUT_SHIFT 7
+#define MT6325_RG_BC11_VREF_VTH_MASK 0x3
+#define MT6325_RG_BC11_VREF_VTH_SHIFT 0
+#define MT6325_RG_BC11_CMP_EN_MASK 0x3
+#define MT6325_RG_BC11_CMP_EN_SHIFT 2
+#define MT6325_RG_BC11_IPD_EN_MASK 0x3
+#define MT6325_RG_BC11_IPD_EN_SHIFT 4
+#define MT6325_RG_BC11_IPU_EN_MASK 0x3
+#define MT6325_RG_BC11_IPU_EN_SHIFT 6
+#define MT6325_RG_BC11_BIAS_EN_MASK 0x1
+#define MT6325_RG_BC11_BIAS_EN_SHIFT 8
+#define MT6325_RG_CSDAC_STP_INC_MASK 0x7
+#define MT6325_RG_CSDAC_STP_INC_SHIFT 0
+#define MT6325_RG_CSDAC_STP_DEC_MASK 0x7
+#define MT6325_RG_CSDAC_STP_DEC_SHIFT 4
+#define MT6325_RG_CSDAC_DLY_MASK 0x7
+#define MT6325_RG_CSDAC_DLY_SHIFT 0
+#define MT6325_RG_CSDAC_STP_MASK 0x7
+#define MT6325_RG_CSDAC_STP_SHIFT 4
+#define MT6325_RG_LOW_ICH_DB_MASK 0x3F
+#define MT6325_RG_LOW_ICH_DB_SHIFT 0
+#define MT6325_RG_CHRIND_ON_MASK 0x1
+#define MT6325_RG_CHRIND_ON_SHIFT 6
+#define MT6325_RG_CHRIND_DIMMING_MASK 0x1
+#define MT6325_RG_CHRIND_DIMMING_SHIFT 7
+#define MT6325_RG_CV_MODE_MASK 0x1
+#define MT6325_RG_CV_MODE_SHIFT 0
+#define MT6325_RG_VCDT_MODE_MASK 0x1
+#define MT6325_RG_VCDT_MODE_SHIFT 1
+#define MT6325_RG_CSDAC_MODE_MASK 0x1
+#define MT6325_RG_CSDAC_MODE_SHIFT 2
+#define MT6325_RG_TRACKING_EN_MASK 0x1
+#define MT6325_RG_TRACKING_EN_SHIFT 4
+#define MT6325_RG_HWCV_EN_MASK 0x1
+#define MT6325_RG_HWCV_EN_SHIFT 6
+#define MT6325_RG_ULC_DET_EN_MASK 0x1
+#define MT6325_RG_ULC_DET_EN_SHIFT 7
+#define MT6325_RG_BGR_TRIM_EN_MASK 0x1
+#define MT6325_RG_BGR_TRIM_EN_SHIFT 0
+#define MT6325_RG_ICHRG_TRIM_MASK 0xF
+#define MT6325_RG_ICHRG_TRIM_SHIFT 4
+#define MT6325_RG_BGR_TRIM_MASK 0x1F
+#define MT6325_RG_BGR_TRIM_SHIFT 0
+#define MT6325_RG_OVP_TRIM_MASK 0xF
+#define MT6325_RG_OVP_TRIM_SHIFT 0
+#define MT6325_RG_CHR_OSC_TRIM_MASK 0x1F
+#define MT6325_RG_CHR_OSC_TRIM_SHIFT 0
+#define MT6325_QI_BGR_EXT_BUF_EN_MASK 0x1
+#define MT6325_QI_BGR_EXT_BUF_EN_SHIFT 5
+#define MT6325_RG_BGR_TEST_EN_MASK 0x1
+#define MT6325_RG_BGR_TEST_EN_SHIFT 6
+#define MT6325_RG_BGR_TEST_RSTB_MASK 0x1
+#define MT6325_RG_BGR_TEST_RSTB_SHIFT 7
+#define MT6325_RG_DAC_USBDL_MAX_MASK 0x3FF
+#define MT6325_RG_DAC_USBDL_MAX_SHIFT 0
+#define MT6325_RG_CM_VDEC_TRIG_MASK 0x1
+#define MT6325_RG_CM_VDEC_TRIG_SHIFT 0
+#define MT6325_PCHR_CM_VDEC_STATUS_MASK 0x3
+#define MT6325_PCHR_CM_VDEC_STATUS_SHIFT 4
+#define MT6325_RG_CM_VINC_TRIG_MASK 0x1
+#define MT6325_RG_CM_VINC_TRIG_SHIFT 0
+#define MT6325_PCHR_CM_VINC_STATUS_MASK 0x3
+#define MT6325_PCHR_CM_VINC_STATUS_SHIFT 4
+#define MT6325_RG_CM_VDEC_HPRD1_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD1_SHIFT 0
+#define MT6325_RG_CM_VDEC_HPRD2_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD2_SHIFT 8
+#define MT6325_RG_CM_VDEC_HPRD3_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD3_SHIFT 0
+#define MT6325_RG_CM_VDEC_HPRD4_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD4_SHIFT 8
+#define MT6325_RG_CM_VDEC_HPRD5_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD5_SHIFT 0
+#define MT6325_RG_CM_VDEC_HPRD6_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD6_SHIFT 8
+#define MT6325_RG_CM_VINC_HPRD1_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD1_SHIFT 0
+#define MT6325_RG_CM_VINC_HPRD2_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD2_SHIFT 8
+#define MT6325_RG_CM_VINC_HPRD3_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD3_SHIFT 0
+#define MT6325_RG_CM_VINC_HPRD4_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD4_SHIFT 8
+#define MT6325_RG_CM_VINC_HPRD5_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD5_SHIFT 0
+#define MT6325_RG_CM_VINC_HPRD6_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD6_SHIFT 8
+#define MT6325_RG_CM_LPRD_MASK 0x3F
+#define MT6325_RG_CM_LPRD_SHIFT 0
+#define MT6325_RG_CM_CS_VTHL_MASK 0xF
+#define MT6325_RG_CM_CS_VTHL_SHIFT 0
+#define MT6325_RG_CM_CS_VTHH_MASK 0xF
+#define MT6325_RG_CM_CS_VTHH_SHIFT 4
+#define MT6325_RG_PCHR_RSV_MASK 0xFF
+#define MT6325_RG_PCHR_RSV_SHIFT 0
+#define MT6325_EOSC_CALI_START_MASK 0x1
+#define MT6325_EOSC_CALI_START_SHIFT 0
+#define MT6325_EOSC_CALI_START_SET_MASK 0x1
+#define MT6325_EOSC_CALI_START_SET_SHIFT 1
+#define MT6325_EOSC_CALI_TD_MASK 0x7
+#define MT6325_EOSC_CALI_TD_SHIFT 5
+#define MT6325_EOSC_CALI_TD_SET_MASK 0x1
+#define MT6325_EOSC_CALI_TD_SET_SHIFT 8
+#define MT6325_EOSC_CALI_TEST_MASK 0xF
+#define MT6325_EOSC_CALI_TEST_SHIFT 9
+#define MT6325_EOSC_CALI_FLAG_SEL_MASK 0xF
+#define MT6325_EOSC_CALI_FLAG_SEL_SHIFT 0
+#define MT6325_EOSC_CALI_FLAG_EN_MASK 0x1
+#define MT6325_EOSC_CALI_FLAG_EN_SHIFT 4
+#define MT6325_FRC_VTCXO0_ON_MASK 0x1
+#define MT6325_FRC_VTCXO0_ON_SHIFT 8
+#define MT6325_FRC_VTCXO0_ON_SET_MASK 0x1
+#define MT6325_FRC_VTCXO0_ON_SET_SHIFT 9
+#define MT6325_EOSC_CALI_RSV_SET_MASK 0x1
+#define MT6325_EOSC_CALI_RSV_SET_SHIFT 10
+#define MT6325_EOSC_CALI_RSV_MASK 0xF
+#define MT6325_EOSC_CALI_RSV_SHIFT 11
+
+#endif // #ifdef PMIC_6325_REG_API
+#endif // #ifndef __DCL_PMIC6325_HW_H_STRUCT__
+