[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/peripheral/inc/hif_v2_internal.h b/mcu/driver/peripheral/inc/hif_v2_internal.h
new file mode 100644
index 0000000..938fb51
--- /dev/null
+++ b/mcu/driver/peripheral/inc/hif_v2_internal.h
@@ -0,0 +1,195 @@
+#ifndef __HIF_V2_INTERNAL_H__
+#define __HIF_V2_INTERNAL_H__
+
+//#include "drv_features.h"
+//#include "kal_release.h"
+#include "reg_base.h"
+#if defined(DRV_HIF_SUPPORT) && defined(DRV_HIF_V2)
+
+
+//#define HIF0_base 0x81180000
+
+// Default: HIF0 is connected to LPCE1. HIF1 is connected to LPCE2.
+#error
+
+//define ECO solution for MT6256E4,MT6575E2 or MTK later chips
+//#if (defined(MT6256_S03) || defined(MT6575_S01) || defined(MT6577)) && defined(__AST_TL1_TDD__)
+//#if (defined(MT6256_S03)) && defined(__AST_TL1_TDD__)
+//#define HIF_ECO_SOLUTION_SUPPORT
+//#endif
+/****************************************************************************
+** Define HIF registers and Macro
+*****************************************************************************/
+#define HIF_MAX_PORT_NUM 4
+#define HIF_ENGINE_COUNT 2
+
+#define HIF_PORT_MCU_A0_LOW_ADDR(n) (HIF0_base+0x0300+n*base_add_increase)
+#define HIF_PORT_MCU_A0_HIGH_ADDR(n) (HIF0_base+0x0310+n*base_add_increase)
+#define HIF_PORT_PDMA_ADDR(n) (HIF0_base+0x0200+n*base_add_increase)
+
+#define HIF_TIMING_CONFIG_WRITE_WAIT_STATE_MASK 0x3F
+#define HIF_TIMING_CONFIG_WRITE_SETUP_TIME_MASK 0xF00
+#define HIF_TIMING_CONFIG_WRITE_HOLD_TIME_MASK 0xF000
+#define HIF_TIMING_CONFIG_READ_LATENCY_TIME_MASK 0x3F0000
+#define HIF_TIMING_CONFIG_READ_SETUP_TIME_MASK 0xF000000
+#define HIF_TIMING_CONFIG_READ_HOLD_TIME_MASK 0xF0000000
+#define HIF_TIMING_CONFIG_CHW_MASK 0xF
+#define HIF_TIMING_CONFIG_WRITE_WAIT_STATE_OFFSET 0
+#define HIF_TIMING_CONFIG_WRITE_SETUP_TIME_OFFSET 8
+#define HIF_TIMING_CONFIG_WRITE_HOLD_TIME_OFFSET 12
+#define HIF_TIMING_CONFIG_READ_LATENCY_TIME_OFFSET 16
+#define HIF_TIMING_CONFIG_READ_SETUP_TIME_OFFSET 24
+#define HIF_TIMING_CONFIG_READ_HOLD_TIME_OFFSET 28
+#define HIF_TIMING_CONFIG_CHW_OFFSET 0
+
+
+#define HIF_STA_REG(n) (HIF0_base+n*base_add_increase+0x0)
+#define HIF_INTEN_REG(n) (HIF0_base+n*base_add_increase+0x4)
+#define HIF_INTSTA_REG(n) (HIF0_base+n*base_add_increase+0x8)
+#define HIF_START_REG(n) (HIF0_base+n*base_add_increase+0xC)
+#define HIF_SWRST_REG(n) (HIF0_base+n*base_add_increase+0x10)
+#define HIF_TIME0_REG(n) (HIF0_base+n*base_add_increase+0x14)
+#define HIF_TIME1_REG(n) (HIF0_base+n*base_add_increase+0x18)
+#define HIF_CON_REG(n) (HIF0_base+n*base_add_increase+0x20)
+#define HIF_DAMOUNT_REG(n) (HIF0_base+n*base_add_increase+0x24)
+//#if defined (HIF_ECO_SOLUTION_SUPPORT)
+#define HIF_ACS_ARB_REG(n) (HIF0_base+n*base_add_increase+0x30)
+
+#define PIF_BUSY_MASK 0x2
+
+#define MCU_ACS_REQ_OFFSET 0
+#define MCU_ACS_STR_OFFSET 2
+//#endif
+
+#define HIF_BUSY_MASK 0x00000001
+#define HIF_CPL_MASK 0x00000001
+#define HIF_START_MASK 0x00000001
+#define HIF_RST_MASK 0x00000001
+#define HIF_HIFW_MASK 0x00000003
+#define HIF_WRITE_MASK 0x00000004
+#define HIF_A0_MASK 0x00000008
+#define HIF_ULTRA_MASK 0x00000010
+
+#define HIF_HIFW_OFFSET 0
+#define HIF_WRITE_OFFSET 2
+#define HIF_A0_OFFSET 3
+#define HIF_ULTRA_OFFSET 4
+
+#define SET_HIF_CE2WR_SETUP_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_SETUP_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_SETUP_TIME_OFFSET;
+#define SET_HIF_CE2WR_HOLD_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_HOLD_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_HOLD_TIME_OFFSET;
+#define SET_HIF_CE2RD_SETUP_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_SETUP_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_SETUP_TIME_OFFSET;
+#define SET_HIF_CE2RD_HOLD_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_HOLD_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_HOLD_TIME_OFFSET;
+#define SET_HIF_WRITE_WAIT_STATE(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_WAIT_STATE_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_WAIT_STATE_OFFSET;
+#define SET_HIF_READ_LATENCY_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_LATENCY_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_LATENCY_TIME_OFFSET;
+#define SET_HIF_CS_HIGH_WIDTH_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME1_REG(n)) &= ~HIF_TIMING_CONFIG_CHW_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME1_REG(n)) |= (val)<<HIF_TIMING_CONFIG_CHW_OFFSET;
+#define SET_HIF_BUS_WIDTH(n, val) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_HIFW_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= (val/8-1)<<HIF_HIFW_OFFSET;
+#define SET_HIF_WRITE(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_WRITE_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 1<<HIF_WRITE_OFFSET;
+#define SET_HIF_READ(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_WRITE_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 0<<HIF_WRITE_OFFSET;
+#define SET_HIF_A0_HIGH(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_A0_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 1<<HIF_A0_OFFSET;
+#define SET_HIF_A0_LOW(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_A0_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 0<<HIF_A0_OFFSET;
+#define SET_HIF_ULTRA(n, val) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_ULTRA_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= (val)<<HIF_ULTRA_OFFSET;
+#define GET_HIF_ULTRA(n) (((*(volatile kal_uint32*)HIF_CON_REG(n))>> HIF_ULTRA_OFFSET) & 0x1);
+#define SET_HIF_DAMOUNT(n, val) (*(volatile kal_uint32*)HIF_DAMOUNT_REG(n)) = (val) - 1;
+
+#define ENABLE_HIF_INTR(n) (*(volatile kal_uint32*)HIF_INTEN_REG(n)) = 1;
+#define DISABLE_HIF_INTR(n) (*(volatile kal_uint32*)HIF_INTEN_REG(n)) = 0;
+
+#define START_HIF(n) (*(volatile kal_uint32*)HIF_START_REG(n)) = 0;\
+ (*(volatile kal_uint32*)HIF_START_REG(n)) = 1;
+#define HIF_BUSY(n) ((*(volatile kal_uint32*)HIF_STA_REG(n)) & HIF_BUSY_MASK)
+#define HIF_INT_CLEAR(n) do {volatile kal_uint32 hif_intsta = (*(volatile kal_uint32*)HIF_INTSTA_REG(n)));} while(0);
+//#if defined (HIF_ECO_SOLUTION_SUPPORT)
+#define SET_HIF_MCU_ACS_REQ(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) |= 1<<MCU_ACS_REQ_OFFSET
+#define SET_HIF_MCU_ACS_STA(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) |= 1<<MCU_ACS_STR_OFFSET
+#define CLEAR_HIF_MCU_ACS_REQ_STA(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) = 0
+#define PIF_BUSY(n) ((*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) & PIF_BUSY_MASK)
+//#endif
+
+// power gating definitions
+#error
+// End of power gating definitions
+/****************************************************************************
+** NLI arbiter definitions
+*****************************************************************************/
+#define REG_NLI_ARB_CS *((volatile unsigned int *) (NLI_ARB_base + 0x0014))
+#define REG_NLI_ARB_CONT_GRANT *((volatile unsigned int *) (NLI_ARB_base + 0x0018))
+#define REG_NLI_ARB_HANDOVER *((volatile unsigned int *) (NLI_ARB_base + 0x001C))
+
+
+#define NLI_ARB_CE0B_SEL_OFS 0
+#define NLI_ARB_CE1B_SEL_OFS 4
+#define NLI_ARB_CE2B_SEL_OFS 8
+#define NLI_ARB_CE3B_SEL_OFS 12
+#define NLI_ARB_CEB_SEL_OFS(n) (4 * n)
+
+#define NLI_ARB_CE0B_SEL_MASK 0x7
+#define NLI_ARB_CE1B_SEL_MASK 0x70
+#define NLI_ARB_CE2B_SEL_MASK 0x700
+#define NLI_ARB_CE3B_SEL_MASK 0x7000
+#define NLI_ARB_CEB_SEL_MASK(n) (0x7 << (NLI_ARB_CEB_SEL_OFS(n)))
+#define NLI_ARB_SET_LPCE_SEL(lpce_num, hif_id) \
+{ \
+ volatile unsigned int temp_REG_NLI_ARB_CS; \
+ temp_REG_NLI_ARB_CS = REG_NLI_ARB_CS; \
+ temp_REG_NLI_ARB_CS &= (~(NLI_ARB_CEB_SEL_MASK(lpce_num))); \
+ temp_REG_NLI_ARB_CS |= ((hif_id+3) << (NLI_ARB_CEB_SEL_OFS(lpce_num))); \
+ REG_NLI_ARB_CS = temp_REG_NLI_ARB_CS; \
+}
+/****************************************************************************
+** PDMA definitions
+*****************************************************************************/
+#define PDMA_OFS 0x80
+// PDMA definitions
+
+
+/****************************************************************************
+** PDMA Control Register Macros
+*****************************************************************************/
+
+#define PDMA_SET_BUF_ADDR(if_num, val) REG_PDMA_HIF_MEM_ADDR(if_num) = val;
+#define PDMA_RD_BIT 0x1
+#define PDMA_SET_RW_DIRECTION(if_num, R) REG_PDMA_HIF_CON(if_num) &= (~(PDMA_RD_BIT));\
+ REG_PDMA_HIF_CON(if_num) |= (R & 0x1);
+#define PDMA_BURST_LEN_MASK 0x70000
+#define PDMA_BURST_LEN_OFS 16
+#define PDMA_SET_BURST_LEN(if_num, len) REG_PDMA_HIF_CON(if_num) &= (~(PDMA_BURST_LEN_MASK));\
+ REG_PDMA_HIF_CON(if_num) |= ((len & 0x7) << PDMA_BURST_LEN_OFS);
+#define PDMA_SET_BUF_LEN(if_num, len) REG_PDMA_HIF_LEN(if_num) = len
+#define PDMA_START(if_num) REG_PDMA_HIF_EN(if_num) = 1;
+#define PDMA_SW_RST(if_num) REG_PDMA_HIF_RST(if_num) = 1;
+
+// End of PDMA definitions
+
+typedef struct
+{
+ kal_bool realtime_callback;
+ kal_uint32 port;
+ kal_uint32 engine_id;
+ kal_uint32 user;
+ HIF_CONFIG_T config;
+ kal_bool A0H_CPU_BUSY;
+ kal_bool A0L_CPU_BUSY;
+} HIF_INTERNAL_HANDLE_T;
+
+// HIF internal functions
+void hif0_lisr(void);
+void hif0_hisr(void);
+void hif1_lisr(void);
+void hif1_hisr(void);
+void hif_wait_for_idle(kal_uint32 engine_id);
+
+#endif
+#endif