[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/sleep_drv/internal/inc/AP_RM_private.h b/mcu/driver/sleep_drv/internal/inc/AP_RM_private.h
new file mode 100644
index 0000000..d48a3f7
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/AP_RM_private.h
@@ -0,0 +1,157 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * AP_RM_private.h
+ *
+ * Project:
+ * --------
+ * MT6280
+ *
+ * Description:
+ * ------------
+ * AP Resource Management (AP TOPSM) configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef AP_RM_PRIVATE_H
+#define AP_RM_PRIVATE_H
+
+#include "md2g_drv.h"
+#include "MD_TOPSM_private.h"
+
+#ifdef __CENTRALIZED_SLEEP_MANAGER_V2__
+#ifdef __AP_SLEEP_MANAGER_SUPPORT__
+
+/******************** Register Definition ********************/
+
+/* Registers for Top-level Sleep Mode Manager. */
+/************************************************************/
+/* Settle time */
+#define AP_TOPSM_RM_CLK_SETTLE ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x00))
+/************************************************************/
+/* Timer control */
+#define AP_TOPSM_RM_TMR_TRG0 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x10))
+#define AP_TOPSM_RM_TMR_PWR0 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x18))
+#define AP_TOPSM_RM_PERI_CON ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x30))
+#define AP_TOPSM_RM_PERI_CON1 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x34))
+#define AP_TOPSM_RM_TMR_SSTA ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x40))
+#define AP_TOPSM_TOPSM_DBG ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x50))
+/* Debug */
+#define AP_TOPSM_CCF_CLK_CON ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x200))
+/************************************************************/
+/* Power on/off control(MTCMOS) */
+#define AP_TOPSM_RM_PWR_CON0 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x800))
+#define AP_TOPSM_RM_PWR_CON1 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x804))
+#define AP_TOPSM_RM_PWR_PER ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x824))
+/************************************************************/
+/* Clock on/off control */
+#define AP_TOPSM_RM_PLL_MASK0 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x830))
+#define AP_TOPSM_RM_PLL_MASK1 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x834))
+/************************************************************/
+/* Cross sleep manager */
+#define AP_TOPSM_RM_SM_PLL_MASK ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x840))
+#define AP_TOPSM_RM_SM_PWR ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x850))
+#define AP_TOPSM_RM_SM_TRG_MASK ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x860))
+#define AP_TOPSM_RM_SM_MASK ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x890))
+#define AP_TOPSM_SM_REQ_MASK ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x8B0))
+#define AP_TOPSM_SM_SLV_REQ_IRQ ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x8C0))
+#define AP_TOPSM_SM_MAS_RDY_IRQ ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x8D0))
+#define AP_TOPSM_SM_TRIG_SETTLE0 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x900))
+/************************************************************/
+/* Others */
+#define AP_TOPSM_SW_CLK_FORCE_ON_CON ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0xA00))
+#define AP_TOPSM_SW_CLK_FORCE_ON_SET ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0xA04))
+#define AP_TOPSM_SW_CLK_FORCE_ON_CLR ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0xA08))
+#define AP_TOPSM_SW_CLK_STA ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0xA20))
+#define AP_TOPSM_SW_PWR_STA ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0xA24))
+#define AP_TOPSM_PROTECT_ACK_MASK ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0xA38))
+#endif /* _AP_SLEEP_MANAGER_SUPPORT__ */
+#endif /* __CENTRALIZED_SLEEP_MANAGER_V2__ */
+#endif /* !AP_RM_PRIVATE_H*/
diff --git a/mcu/driver/sleep_drv/internal/inc/MD_TOPSM_private.h b/mcu/driver/sleep_drv/internal/inc/MD_TOPSM_private.h
new file mode 100644
index 0000000..3588c77
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/MD_TOPSM_private.h
@@ -0,0 +1,6654 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MD_TOPSM_private.h
+ *
+ * Project:
+ * --------
+ * MT6293
+ *
+ * Description:
+ * ------------
+ * MCU Resource Management (MCU TOPSM) configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef MD_TOPSM_PRIVATE_H
+#define MD_TOPSM_PRIVATE_H
+
+#if defined(__ASSEMBLER__)
+#define FRC_REG 0xA00D0800
+#define ENABLE_KEY 0xF2CC0001
+#if defined(__MD93__) || defined(__MD95__) || (defined(__MD97__) && defined(__MIPS_IA__))
+.macro ENABLE_FRC
+.set push
+.set nomips16
+ li a0, FRC_REG
+ li a1, ENABLE_KEY
+ sw a1, 0x0(a0)
+.set pop
+.endm
+#elif defined(__MD97__) || defined(__MD97P__)
+.macro ENABLE_FRC
+.set push
+ li $a0, FRC_REG
+ li $a1, ENABLE_KEY
+ sw $a1, 0x0($a0)
+.set pop
+.endm
+#else
+ #error "no chip match"
+#endif
+#else
+
+#include "ostd_private.h" // for OST_ISR and IS_SW_LOAD_L1_EXIST
+#include "sleepdrv_interface.h"
+#if defined(L1_SIM)
+#include "simul_public.h"
+#endif
+
+/******************** Register Definition ********************/
+#define MD_TOPSM_BASE BASE_MADDR_MDTOPSM /* MCU_TOP_SleepMode_base: 0xFF830000(Strongly order) is used for 6290 */
+#define MDSM_CORE_PWR_CTRL_BASE BASE_MADDR_MDPERI_MDSM_CORE_PWR_CTRL
+#define MDGLOBAL_DCM_BASE BASE_MADDR_MDTOP_GLBCON /* BASE_MADDR_MD_GLBCON_TOP_DCM */
+#define MDPERIMISC_BASE BASE_MADDR_MDPERIMISC
+#define MDCORESYSMISC_BASE BASE_MADDR_MCUSYS_MISC_REG
+#if !defined(__MD97__) && !defined(__MD97P__)
+#define MDSMICFG_BASE BASE_MADDR_MDSMICFG
+#endif
+#if defined(__MD97P__)
+#define MDCORESYSIAIADELSELCFG_BASE
+#else
+#define MDCORESYSIAIADELSELCFG_BASE BASE_MADDR_MCUSYS_IA_DEL_CFG
+#endif
+#define MDTOP_PLLMIXED_BASE BASE_MADDR_MDTOP_PLLMIXED
+
+#if defined(__MD93__)
+/*===========================================================================================================================
+** MD TOPSM
+**===========================================================================================================================*/
+
+
+/*=========================================
+** Power Control Register0:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+**
+** [15:15] PWR_CTRL
+** Enable SW MTCMOS control sequence mode or not
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0000))
+/*=========================================
+** Power Control Register1:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+**
+** [15:15] PWR_CTRL
+** Enable SW MTCMOS control sequence mode or not
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0004))
+/*=========================================
+** Power Control Register2:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+**
+** [15:15] PWR_CTRL
+** Enable SW MTCMOS control sequence mode or not
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0008))
+/*=========================================
+** Power Control Register3:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+**
+** [15:15] PWR_CTRL
+** Enable SW MTCMOS control sequence mode or not
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x000C))
+/*=========================================
+** Power Control Register4:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+**
+** [15:15] PWR_CTRL
+** Enable SW MTCMOS control sequence mode or not
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0010))
+/*=========================================
+** Power Control Register5:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+**
+** [15:15] PWR_CTRL
+** Enable SW MTCMOS control sequence mode or not
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0014))
+/*=========================================
+** Power Control Register6:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+** Enable SW MTCMOS control sequence mode or not
+** [15:15] PWR_CTRL
+** SW MTCMOS control sequence mode: Subsys bus protection request
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0018))
+/*=========================================
+** Power Control Register7:
+** 1. Specify each MTCMOS domain power settle time (32K based) & reset deassertion contrl type
+** 2. Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by bit[15] (this feature is for backup solution)
+** 3. Specify each MTCMOS domain is always on or off
+** 4. Sepcify the starting period for memory power on
+** 5. Write 0xb2 << 24 to update this register
+** [4:0] PWRON_SETTLE
+** Subsys power on settling period (32KHz clock based), Min = 2
+** [5:5] PWR_ON_1_MODE
+** 2th power on channel control mode
+** 0: trigger 2th power on after 4 cycles of 26m of 1th power on
+** 1: trigger 2th power on after 1 cycle of 32k of 1th power on
+** [6:6] RST_EN_MODE
+** Subsys reset deassetion control
+** 0: reset will not be triggered when power off
+** 1: reset will be triggered when power off
+** [7:7] PWR_FORCE_ON
+** PWR force on bit:
+** If the mtcmos domain is default on, this bit will be 1. For the default on mtcmos domain, SW must manually assigns this bit as 0
+** if necessary to disable force on function
+** [13:8] PWR_MEMUP_ST
+** specify the starting period for memory power on.
+** To reduce in-ruch current, it's necessary to configure different starting period for each mtcmos domain in hw mode.
+** The unit is 26m cycle * (mcf_cnt_base +1)
+** [14:14] PWR_RESERVED
+** Enable SW MTCMOS control sequence mode or not
+** [15:15] PWR_CTRL
+** SW MTCMOS control sequence mode: Subsys bus protection request
+**=========================================*/
+#define MD_TOPSM_SM_PWR_CON7 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x001C))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode,
+** mtcmos domain pwr on procedure:
+** a. write 1 at corresponding register
+** b. waiting 33us
+** c. polling SM_PWR_RDY register
+** [0:0] PWR0_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos0 by SW process0
+** [1:1] PWR1_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos1 by SW process0
+** [2:2] PWR2_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos2 by SW process0
+** [3:3] PWR3_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos3 by SW process0
+** [4:4] PWR4_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos4 by SW process0
+** [5:5] PWR5_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos5 by SW process0
+** [6:6] PWR6_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos6 by SW process0
+** [7:7] PWR7_ON_SW_CTRL0
+** SW PWR control mode: write 1 to power on mtcmos7 by SW process0
+**=========================================*/
+#define MD_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0080))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode,
+** mtcmos domain pwr on procedure:
+** a. write 1 at corresponding register
+** b. waiting 33us
+** c. polling SM_PWR_RDY register
+** [0:0] PWR0_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos0 by SW process1
+** [1:1] PWR1_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos1 by SW process1
+** [2:2] PWR2_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos2 by SW process1
+** [3:3] PWR3_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos3 by SW process1
+** [4:4] PWR4_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos4 by SW process1
+** [5:5] PWR5_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos5 by SW process1
+** [6:6] PWR6_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos6 by SW process1
+** [7:7] PWR7_ON_SW_CTRL1
+** SW PWR control mode: write 1 to power on mtcmos7 by SW process1
+**=========================================*/
+#define MD_TOPSM_SM_PWR_ON_SW_CTRL1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0084))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode,
+** mtcmos domain pwr on procedure:
+** a. write 1 at corresponding register
+** b. waiting 33us
+** c. polling SM_PWR_RDY register
+** [0:0] PWR0_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos0 by SW process2
+** [1:1] PWR1_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos1 by SW process2
+** [2:2] PWR2_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos2 by SW process2
+** [3:3] PWR3_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos3 by SW process2
+** [4:4] PWR4_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos4 by SW process2
+** [5:5] PWR5_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos5 by SW process2
+** [6:6] PWR6_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos6 by SW process2
+** [7:7] PWR7_ON_SW_CTRL2
+** SW PWR control mode: write 1 to power on mtcmos7 by SW process2
+**=========================================*/
+#define MD_TOPSM_SM_PWR_ON_SW_CTRL2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0088))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode,
+** mtcmos domain pwr on procedure:
+** a. write 1 at corresponding register
+** b. waiting 33us
+** c. polling SM_PWR_RDY register
+** [0:0] PWR0_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos0 by SW process3
+** [1:1] PWR1_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos1 by SW process3
+** [2:2] PWR2_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos2 by SW process3
+** [3:3] PWR3_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos3 by SW process3
+** [4:4] PWR4_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos4 by SW process3
+** [5:5] PWR5_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos5 by SW process3
+** [6:6] PWR6_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos6 by SW process3
+** [7:7] PWR7_ON_SW_CTRL3
+** SW PWR control mode: write 1 to power on mtcmos7 by SW process3
+**=========================================*/
+#define MD_TOPSM_SM_PWR_ON_SW_CTRL3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x008C))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode
+** When to trigger power off: must confirm power is on & ready bit is on
+** [0:0] PWR0_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos0 by SW process0
+** [1:1] PWR1_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos1 by SW process0
+** [2:2] PWR2_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos2 by SW process0
+** [3:3] PWR3_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos3 by SW process0
+** [4:4] PWR4_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos4 by SW process0
+** [5:5] PWR5_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos5 by SW process0
+** [6:6] PWR6_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos6 by SW process0
+** [7:7] PWR7_OFF_SW_CTRL0
+** SW PWR control mode: write 1 to power off mtcmos7 by SW process0
+**=========================================*/
+#define MD_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00A0))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode
+** When to trigger power off: must confirm power is on & ready bit is on
+** [0:0] PWR0_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos0 by SW process1
+** [1:1] PWR1_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos1 by SW process1
+** [2:2] PWR2_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos2 by SW process1
+** [3:3] PWR3_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos3 by SW process1
+** [4:4] PWR4_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos4 by SW process1
+** [5:5] PWR5_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos5 by SW process1
+** [6:6] PWR6_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos6 by SW process1
+** [7:7] PWR7_OFF_SW_CTRL1
+** SW PWR control mode: write 1 to power off mtcmos7 by SW process1
+**=========================================*/
+#define MD_TOPSM_SM_PWR_OFF_SW_CTRL1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00A4))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode
+** When to trigger power off: must confirm power is on & ready bit is on
+** [0:0] PWR0_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos0 by SW process2
+** [1:1] PWR1_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos1 by SW process2
+** [2:2] PWR2_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos2 by SW process2
+** [3:3] PWR3_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos3 by SW process2
+** [4:4] PWR4_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos4 by SW process2
+** [5:5] PWR5_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos5 by SW process2
+** [6:6] PWR6_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos6 by SW process2
+** [7:7] PWR7_OFF_SW_CTRL2
+** SW PWR control mode: write 1 to power off mtcmos7 by SW process2
+**=========================================*/
+#define MD_TOPSM_SM_PWR_OFF_SW_CTRL2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00A8))
+/*=========================================
+** SW PWR control:
+** Specify the MTCMOS domain on/off for SW PWR control mode
+** When to trigger power off: must confirm power is on & ready bit is on
+** [0:0] PWR0_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos0 by SW process3
+** [1:1] PWR1_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos1 by SW process3
+** [2:2] PWR2_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos2 by SW process3
+** [3:3] PWR3_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos3 by SW process3
+** [4:4] PWR4_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos4 by SW process3
+** [5:5] PWR5_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos5 by SW process3
+** [6:6] PWR6_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos6 by SW process3
+** [7:7] PWR7_OFF_SW_CTRL3
+** SW PWR control mode: write 1 to power off mtcmos7 by SW process3
+**=========================================*/
+#define MD_TOPSM_SM_PWR_OFF_SW_CTRL3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00AC))
+/*=========================================
+** power settle timer parameter 0:
+** Specify the timing relationship for power control sequence
+** [3:0] BUSPROT_SETTLE
+** Bus Protion Settling Time (26MHz clock based)
+** [7:4] MEMPROT_SETTLE
+** Memory protect Settling Time (26MHz clock based)
+** [11:8] ISOEN_SETTLE
+** Isolation Enable Settling Time (26MHz clock based)
+** [17:12] RESET_SETTLE
+** Reset Settling Time (26MHz clock based)
+** [25:20] MEMUP_SETTLE
+** Memory Power on Settling Time (26MHz clock based)
+** [31:28] MEMISO_SETTLE
+** Memory Isolation Enable Settling Time (26MHz clock based)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C0))
+/*=========================================
+** power settle timer parameter 1:
+** Specify the timing relationship for power control sequence
+** [3:0] CLKEN_SETTLE
+** Clock Enable Settling Time (26MHz clock based)
+** [7:4] ISOOFF_SETTLE
+** Isolation Disable Settling Time (26MHz clock based)
+** [11:8] CLKOFF_SETTLE
+** Clock Disable Settling Time (26MHz clock based)
+** [15:12] DISRST_SETTLE
+** Disable Reset Settling Time (26MHz clock based)
+** [19:16] WAIT_ON_SETTLE
+** Wait On Settling Time (26MHz clock based)
+** [28:24] MAX_PWR_SETTLE_TIME
+** Maximun Power Settling Time (among each PWRON_SETTLE in SM_PWR_CONx) (32KHz clock based) for MTCMOS domain in HW mode
+**=========================================*/
+#define MD_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C4))
+/*=========================================
+** power settle timer parameter 1:
+** Specify the protect ready is ignored or not when MTCMOS is in off flow
+** [0:0] PWR0_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR0
+** [1:1] PWR1_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR1
+** [2:2] PWR2_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR2
+** [3:3] PWR3_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR3
+** [4:4] PWR4_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR4
+** [5:5] PWR5_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR5
+** [6:6] PWR6_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR6
+** [7:7] PWR7_BYPASS_PROTECT_RDY
+** Bus protect ready is ignored or not for PWR7
+**=========================================*/
+#define MD_TOPSM_SM_PWR_BYPASS_PROTECT_RDY ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C8))
+/*=========================================
+** Power Ready Register:
+** power ready bit
+** [0:0] PWR0_RDY_TRG
+** triggered by power0 ready from low to high
+** [1:1] PWR1_RDY_TRG
+** triggered by power1 ready from low to high
+** [2:2] PWR2_RDY_TRG
+** triggered by power2 ready from low to high
+** [3:3] PWR3_RDY_TRG
+** triggered by power3 ready from low to high
+** [4:4] PWR4_RDY_TRG
+** triggered by power4 ready from low to high
+** [5:5] PWR5_RDY_TRG
+** triggered by power5 ready from low to high
+** [6:6] PWR6_RDY_TRG
+** triggered by power6 ready from low to high
+** [7:7] PWR7_RDY_TRG
+** triggered by power7 ready from low to high
+**=========================================*/
+#define MD_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00D0))
+/*=========================================
+** Power Ready Register:
+** power ready bit
+** [0:0] PWR0_RDY
+** power0 ready
+** [1:1] PWR1_RDY
+** power1 ready
+** [2:2] PWR2_RDY
+** power2 ready
+** [3:3] PWR3_RDY
+** power3 ready
+** [4:4] PWR4_RDY
+** power4 ready
+** [5:5] PWR5_RDY
+** power5 ready
+** [6:6] PWR6_RDY
+** power6 ready
+** [7:7] PWR7_RDY
+** power7 ready
+**=========================================*/
+#define MD_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00D4))
+/*=========================================
+** MTCMOS signal that SW control:
+** Specify MTCMOS SUBSYS Power Control Sequence for SW MTCMOS control sequence mode by the bit[15] in SM_PWR_CONx (this feature is for backup solution)
+** [0:0] PWR_PROTECT_REQ
+** SW MTCMOS control sequence mode: Subsys protect req
+** [1:1] PWR_ON_0
+** SW MTCMOS control sequence mode: Subsys power on
+** [2:2] PWR_ON_1
+** SW MTCMOS control sequence mode: Subsys power on
+** [3:3] PWR_CLK_DIS
+** SW MTCMOS control sequence mode: Subsys clock disable
+** [4:4] PWR_ISO
+** SW MTCMOS control sequence mode: Subsys isolation enable
+** [5:5] PWR_RST_B
+** SW MTCMOS control sequence mode: Subsys power on reset
+** [6:6] PWR_MEM_PROT
+** SW MTCMOS control sequence mode: Subsys memory protection
+** [7:7] PWR_MEM_ISOINTB
+** SW MTCMOS control sequence mode: Power memory isolation
+** [8:8] PWR_MEM_OFF
+** SW MTCMOS control sequence mode: Subsys memory power off
+** [9:9] PWR_RESERVED
+**
+**=========================================*/
+#define MD_TOPSM_SW_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00E0))
+/*=========================================
+** TIMER channel request mask bit:
+** TIMER channel request mask bit
+** [0:0] SM_TMR0_REQ_MASK
+** TIMER0 channel request mask bit
+** [1:1] SM_TMR1_REQ_MASK
+** TIMER1 channel request mask bit
+** [2:2] SM_TMR2_REQ_MASK
+** TIMER2 channel request mask bit
+** [3:3] SM_TMR3_REQ_MASK
+** TIMER3 channel request mask bit
+** [4:4] SM_TMR4_REQ_MASK
+** TIMER4 channel request mask bit
+** [5:5] SM_TMR5_REQ_MASK
+** TIMER5 channel request mask bit
+** [6:6] SM_TMR6_REQ_MASK
+** TIMER6 channel request mask bit
+** [7:7] SM_TMR7_REQ_MASK
+** TIMER7 channel request mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0100))
+/*=========================================
+** TIMER channel sysclk ctrl mask bit:
+** TIMER channel sysclk ctrl mask bit
+** [0:0] SM_TMR0_SYSCLK_MASK
+** TIMER0 channel sysclk ctrl mask bit
+** [1:1] SM_TMR1_SYSCLK_MASK
+** TIMER1 channel sysclk ctrl mask bit
+** [2:2] SM_TMR2_SYSCLK_MASK
+** TIMER2 channel sysclk ctrl mask bit
+** [3:3] SM_TMR3_SYSCLK_MASK
+** TIMER3 channel sysclk ctrl mask bit
+** [4:4] SM_TMR4_SYSCLK_MASK
+** TIMER4 channel sysclk ctrl mask bit
+** [5:5] SM_TMR5_SYSCLK_MASK
+** TIMER5 channel sysclk ctrl mask bit
+** [6:6] SM_TMR6_SYSCLK_MASK
+** TIMER6 channel sysclk ctrl mask bit
+** [7:7] SM_TMR7_SYSCLK_MASK
+** TIMER7 channel sysclk ctrl mask bit
+** [8:8] SM_TMR0_SYSCLK1_MASK
+** TIMER0 channel sysclk1 ctrl mask bit
+** [9:9] SM_TMR1_SYSCLK1_MASK
+** TIMER1 channel sysclk1 ctrl mask bit
+** [10:10] SM_TMR2_SYSCLK1_MASK
+** TIMER2 channel sysclk1 ctrl mask bit
+** [11:11] SM_TMR3_SYSCLK1_MASK
+** TIMER3 channel sysclk1 ctrl mask bit
+** [12:12] SM_TMR4_SYSCLK1_MASK
+** TIMER4 channel sysclk1 ctrl mask bit
+** [13:13] SM_TMR5_SYSCLK1_MASK
+** TIMER5 channel sysclk1 ctrl mask bit
+** [14:14] SM_TMR6_SYSCLK1_MASK
+** TIMER6 channel sysclk1 ctrl mask bit
+** [15:15] SM_TMR7_SYSCLK1_MASK
+** TIMER7 channel sysclk1 ctrl mask bit
+** [16:16] SM_TMR0_SYSCLK2_MASK
+** TIMER0 channel sysclk2 ctrl mask bit
+** [17:17] SM_TMR1_SYSCLK2_MASK
+** TIMER1 channel sysclk2 ctrl mask bit
+** [18:18] SM_TMR2_SYSCLK2_MASK
+** TIMER2 channel sysclk2 ctrl mask bit
+** [19:19] SM_TMR3_SYSCLK2_MASK
+** TIMER3 channel sysclk2 ctrl mask bit
+** [20:20] SM_TMR4_SYSCLK2_MASK
+** TIMER4 channel sysclk2 ctrl mask bit
+** [21:21] SM_TMR5_SYSCLK2_MASK
+** TIMER5 channel sysclk2 ctrl mask bit
+** [22:22] SM_TMR6_SYSCLK2_MASK
+** TIMER6 channel sysclk2 ctrl mask bit
+** [23:23] SM_TMR7_SYSCLK2_MASK
+** TIMER7 channel sysclk2 ctrl mask bit
+** [24:24] SM_TMR0_SYSCLK3_MASK
+** TIMER0 channel sysclk3 ctrl mask bit
+** [25:25] SM_TMR1_SYSCLK3_MASK
+** TIMER1 channel sysclk3 ctrl mask bit
+** [26:26] SM_TMR2_SYSCLK3_MASK
+** TIMER2 channel sysclk3 ctrl mask bit
+** [27:27] SM_TMR3_SYSCLK3_MASK
+** TIMER3 channel sysclk3 ctrl mask bit
+** [28:28] SM_TMR4_SYSCLK3_MASK
+** TIMER4 channel sysclk3 ctrl mask bit
+** [29:29] SM_TMR5_SYSCLK3_MASK
+** TIMER5 channel sysclk3 ctrl mask bit
+** [30:30] SM_TMR6_SYSCLK3_MASK
+** TIMER6 channel sysclk3 ctrl mask bit
+** [31:31] SM_TMR7_SYSCLK3_MASK
+** TIMER7 channel sysclk3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0108))
+/*=========================================
+** TIMER channel pll ctrl mask bit:
+** TIMER channel pll ctrl mask bit
+** [0:0] SM_TMR0_PLL0_MASK
+** TIMER0 channel pll0 ctrl mask bit
+** [1:1] SM_TMR1_PLL0_MASK
+** TIMER1 channel pll0 ctrl mask bit
+** [2:2] SM_TMR2_PLL0_MASK
+** TIMER2 channel pll0 ctrl mask bit
+** [3:3] SM_TMR3_PLL0_MASK
+** TIMER3 channel pll0 ctrl mask bit
+** [4:4] SM_TMR4_PLL0_MASK
+** TIMER4 channel pll0 ctrl mask bit
+** [5:5] SM_TMR5_PLL0_MASK
+** TIMER5 channel pll0 ctrl mask bit
+** [6:6] SM_TMR6_PLL0_MASK
+** TIMER6 channel pll0 ctrl mask bit
+** [7:7] SM_TMR7_PLL0_MASK
+** TIMER7 channel pll0 ctrl mask bit
+** [8:8] SM_TMR0_PLL1_MASK
+** TIMER0 channel pll1 ctrl mask bit
+** [9:9] SM_TMR1_PLL1_MASK
+** TIMER1 channel pll1 ctrl mask bit
+** [10:10] SM_TMR2_PLL1_MASK
+** TIMER2 channel pll1 ctrl mask bit
+** [11:11] SM_TMR3_PLL1_MASK
+** TIMER3 channel pll1 ctrl mask bit
+** [12:12] SM_TMR4_PLL1_MASK
+** TIMER4 channel pll1 ctrl mask bit
+** [13:13] SM_TMR5_PLL1_MASK
+** TIMER5 channel pll1 ctrl mask bit
+** [14:14] SM_TMR6_PLL1_MASK
+** TIMER6 channel pll1 ctrl mask bit
+** [15:15] SM_TMR7_PLL1_MASK
+** TIMER7 channel pll1 ctrl mask bit
+** [16:16] SM_TMR0_PLL2_MASK
+** TIMER0 channel pll2 ctrl mask bit
+** [17:17] SM_TMR1_PLL2_MASK
+** TIMER1 channel pll2 ctrl mask bit
+** [18:18] SM_TMR2_PLL2_MASK
+** TIMER2 channel pll2 ctrl mask bit
+** [19:19] SM_TMR3_PLL2_MASK
+** TIMER3 channel pll2 ctrl mask bit
+** [20:20] SM_TMR4_PLL2_MASK
+** TIMER4 channel pll2 ctrl mask bit
+** [21:21] SM_TMR5_PLL2_MASK
+** TIMER5 channel pll2 ctrl mask bit
+** [22:22] SM_TMR6_PLL2_MASK
+** TIMER6 channel pll2 ctrl mask bit
+** [23:23] SM_TMR7_PLL2_MASK
+** TIMER7 channel pll2 ctrl mask bit
+** [24:24] SM_TMR0_PLL3_MASK
+** TIMER0 channel pll3 ctrl mask bit
+** [25:25] SM_TMR1_PLL3_MASK
+** TIMER1 channel pll3 ctrl mask bit
+** [26:26] SM_TMR2_PLL3_MASK
+** TIMER2 channel pll3 ctrl mask bit
+** [27:27] SM_TMR3_PLL3_MASK
+** TIMER3 channel pll3 ctrl mask bit
+** [28:28] SM_TMR4_PLL3_MASK
+** TIMER4 channel pll3 ctrl mask bit
+** [29:29] SM_TMR5_PLL3_MASK
+** TIMER5 channel pll3 ctrl mask bit
+** [30:30] SM_TMR6_PLL3_MASK
+** TIMER6 channel pll3 ctrl mask bit
+** [31:31] SM_TMR7_PLL3_MASK
+** TIMER7 channel pll3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0120))
+/*=========================================
+** TIMER channel pll ctrl mask bit:
+** TIMER channel pll ctrl mask bit
+** [0:0] SM_TMR0_PLL4_MASK
+** TIMER0 channel pll4 ctrl mask bit
+** [1:1] SM_TMR1_PLL4_MASK
+** TIMER1 channel pll4 ctrl mask bit
+** [2:2] SM_TMR2_PLL4_MASK
+** TIMER2 channel pll4 ctrl mask bit
+** [3:3] SM_TMR3_PLL4_MASK
+** TIMER3 channel pll4 ctrl mask bit
+** [4:4] SM_TMR4_PLL4_MASK
+** TIMER4 channel pll4 ctrl mask bit
+** [5:5] SM_TMR5_PLL4_MASK
+** TIMER5 channel pll4 ctrl mask bit
+** [6:6] SM_TMR6_PLL4_MASK
+** TIMER6 channel pll4 ctrl mask bit
+** [7:7] SM_TMR7_PLL4_MASK
+** TIMER7 channel pll4 ctrl mask bit
+** [8:8] SM_TMR0_PLL5_MASK
+** TIMER0 channel pll5 ctrl mask bit
+** [9:9] SM_TMR1_PLL5_MASK
+** TIMER1 channel pll5 ctrl mask bit
+** [10:10] SM_TMR2_PLL5_MASK
+** TIMER2 channel pll5 ctrl mask bit
+** [11:11] SM_TMR3_PLL5_MASK
+** TIMER3 channel pll5 ctrl mask bit
+** [12:12] SM_TMR4_PLL5_MASK
+** TIMER4 channel pll5 ctrl mask bit
+** [13:13] SM_TMR5_PLL5_MASK
+** TIMER5 channel pll5 ctrl mask bit
+** [14:14] SM_TMR6_PLL5_MASK
+** TIMER6 channel pll5 ctrl mask bit
+** [15:15] SM_TMR7_PLL5_MASK
+** TIMER7 channel pll5 ctrl mask bit
+** [16:16] SM_TMR0_PLL6_MASK
+** TIMER0 channel pll6 ctrl mask bit
+** [17:17] SM_TMR1_PLL6_MASK
+** TIMER1 channel pll6 ctrl mask bit
+** [18:18] SM_TMR2_PLL6_MASK
+** TIMER2 channel pll6 ctrl mask bit
+** [19:19] SM_TMR3_PLL6_MASK
+** TIMER3 channel pll6 ctrl mask bit
+** [20:20] SM_TMR4_PLL6_MASK
+** TIMER4 channel pll6 ctrl mask bit
+** [21:21] SM_TMR5_PLL6_MASK
+** TIMER5 channel pll6 ctrl mask bit
+** [22:22] SM_TMR6_PLL6_MASK
+** TIMER6 channel pll6 ctrl mask bit
+** [23:23] SM_TMR7_PLL6_MASK
+** TIMER7 channel pll6 ctrl mask bit
+** [24:24] SM_TMR0_PLL7_MASK
+** TIMER0 channel pll7 ctrl mask bit
+** [25:25] SM_TMR1_PLL7_MASK
+** TIMER1 channel pll7 ctrl mask bit
+** [26:26] SM_TMR2_PLL7_MASK
+** TIMER2 channel pll7 ctrl mask bit
+** [27:27] SM_TMR3_PLL7_MASK
+** TIMER3 channel pll7 ctrl mask bit
+** [28:28] SM_TMR4_PLL7_MASK
+** TIMER4 channel pll7 ctrl mask bit
+** [29:29] SM_TMR5_PLL7_MASK
+** TIMER5 channel pll7 ctrl mask bit
+** [30:30] SM_TMR6_PLL7_MASK
+** TIMER6 channel pll7 ctrl mask bit
+** [31:31] SM_TMR7_PLL7_MASK
+** TIMER7 channel pll7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0124))
+/*=========================================
+** TIMER channel pll ctrl mask bit:
+** TIMER channel pll ctrl mask bit
+** [0:0] SM_TMR0_PLL8_MASK
+** TIMER0 channel pll8 ctrl mask bit
+** [1:1] SM_TMR1_PLL8_MASK
+** TIMER1 channel pll8 ctrl mask bit
+** [2:2] SM_TMR2_PLL8_MASK
+** TIMER2 channel pll8 ctrl mask bit
+** [3:3] SM_TMR3_PLL8_MASK
+** TIMER3 channel pll8 ctrl mask bit
+** [4:4] SM_TMR4_PLL8_MASK
+** TIMER4 channel pll8 ctrl mask bit
+** [5:5] SM_TMR5_PLL8_MASK
+** TIMER5 channel pll8 ctrl mask bit
+** [6:6] SM_TMR6_PLL8_MASK
+** TIMER6 channel pll8 ctrl mask bit
+** [7:7] SM_TMR7_PLL8_MASK
+** TIMER7 channel pll8 ctrl mask bit
+** [8:8] SM_TMR0_PLL9_MASK
+** TIMER0 channel pll9 ctrl mask bit
+** [9:9] SM_TMR1_PLL9_MASK
+** TIMER1 channel pll9 ctrl mask bit
+** [10:10] SM_TMR2_PLL9_MASK
+** TIMER2 channel pll9 ctrl mask bit
+** [11:11] SM_TMR3_PLL9_MASK
+** TIMER3 channel pll9 ctrl mask bit
+** [12:12] SM_TMR4_PLL9_MASK
+** TIMER4 channel pll9 ctrl mask bit
+** [13:13] SM_TMR5_PLL9_MASK
+** TIMER5 channel pll9 ctrl mask bit
+** [14:14] SM_TMR6_PLL9_MASK
+** TIMER6 channel pll9 ctrl mask bit
+** [15:15] SM_TMR7_PLL9_MASK
+** TIMER7 channel pll9 ctrl mask bit
+** [16:16] SM_TMR0_PLL10_MASK
+** TIMER0 channel pll10 ctrl mask bit
+** [17:17] SM_TMR1_PLL10_MASK
+** TIMER1 channel pll10 ctrl mask bit
+** [18:18] SM_TMR2_PLL10_MASK
+** TIMER2 channel pll10 ctrl mask bit
+** [19:19] SM_TMR3_PLL10_MASK
+** TIMER3 channel pll10 ctrl mask bit
+** [20:20] SM_TMR4_PLL10_MASK
+** TIMER4 channel pll10 ctrl mask bit
+** [21:21] SM_TMR5_PLL10_MASK
+** TIMER5 channel pll10 ctrl mask bit
+** [22:22] SM_TMR6_PLL10_MASK
+** TIMER6 channel pll10 ctrl mask bit
+** [23:23] SM_TMR7_PLL10_MASK
+** TIMER7 channel pll10 ctrl mask bit
+** [24:24] SM_TMR0_PLL11_MASK
+** TIMER0 channel pll11 ctrl mask bit
+** [25:25] SM_TMR1_PLL11_MASK
+** TIMER1 channel pll11 ctrl mask bit
+** [26:26] SM_TMR2_PLL11_MASK
+** TIMER2 channel pll11 ctrl mask bit
+** [27:27] SM_TMR3_PLL11_MASK
+** TIMER3 channel pll11 ctrl mask bit
+** [28:28] SM_TMR4_PLL11_MASK
+** TIMER4 channel pll11 ctrl mask bit
+** [29:29] SM_TMR5_PLL11_MASK
+** TIMER5 channel pll11 ctrl mask bit
+** [30:30] SM_TMR6_PLL11_MASK
+** TIMER6 channel pll11 ctrl mask bit
+** [31:31] SM_TMR7_PLL11_MASK
+** TIMER7 channel pll11 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PLL_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0128))
+/*=========================================
+** TIMER channel pll ctrl mask bit:
+** TIMER channel pll ctrl mask bit
+** [0:0] SM_TMR0_PLL12_MASK
+** TIMER0 channel pll12 ctrl mask bit
+** [1:1] SM_TMR1_PLL12_MASK
+** TIMER1 channel pll12 ctrl mask bit
+** [2:2] SM_TMR2_PLL12_MASK
+** TIMER2 channel pll12 ctrl mask bit
+** [3:3] SM_TMR3_PLL12_MASK
+** TIMER3 channel pll12 ctrl mask bit
+** [4:4] SM_TMR4_PLL12_MASK
+** TIMER4 channel pll12 ctrl mask bit
+** [5:5] SM_TMR5_PLL12_MASK
+** TIMER5 channel pll12 ctrl mask bit
+** [6:6] SM_TMR6_PLL12_MASK
+** TIMER6 channel pll12 ctrl mask bit
+** [7:7] SM_TMR7_PLL12_MASK
+** TIMER7 channel pll12 ctrl mask bit
+** [8:8] SM_TMR0_PLL13_MASK
+** TIMER0 channel pll13 ctrl mask bit
+** [9:9] SM_TMR1_PLL13_MASK
+** TIMER1 channel pll13 ctrl mask bit
+** [10:10] SM_TMR2_PLL13_MASK
+** TIMER2 channel pll13 ctrl mask bit
+** [11:11] SM_TMR3_PLL13_MASK
+** TIMER3 channel pll13 ctrl mask bit
+** [12:12] SM_TMR4_PLL13_MASK
+** TIMER4 channel pll13 ctrl mask bit
+** [13:13] SM_TMR5_PLL13_MASK
+** TIMER5 channel pll13 ctrl mask bit
+** [14:14] SM_TMR6_PLL13_MASK
+** TIMER6 channel pll13 ctrl mask bit
+** [15:15] SM_TMR7_PLL13_MASK
+** TIMER7 channel pll13 ctrl mask bit
+** [16:16] SM_TMR0_PLL14_MASK
+** TIMER0 channel pll14 ctrl mask bit
+** [17:17] SM_TMR1_PLL14_MASK
+** TIMER1 channel pll14 ctrl mask bit
+** [18:18] SM_TMR2_PLL14_MASK
+** TIMER2 channel pll14 ctrl mask bit
+** [19:19] SM_TMR3_PLL14_MASK
+** TIMER3 channel pll14 ctrl mask bit
+** [20:20] SM_TMR4_PLL14_MASK
+** TIMER4 channel pll14 ctrl mask bit
+** [21:21] SM_TMR5_PLL14_MASK
+** TIMER5 channel pll14 ctrl mask bit
+** [22:22] SM_TMR6_PLL14_MASK
+** TIMER6 channel pll14 ctrl mask bit
+** [23:23] SM_TMR7_PLL14_MASK
+** TIMER7 channel pll14 ctrl mask bit
+** [24:24] SM_TMR0_PLL15_MASK
+** TIMER0 channel pll15 ctrl mask bit
+** [25:25] SM_TMR1_PLL15_MASK
+** TIMER1 channel pll15 ctrl mask bit
+** [26:26] SM_TMR2_PLL15_MASK
+** TIMER2 channel pll15 ctrl mask bit
+** [27:27] SM_TMR3_PLL15_MASK
+** TIMER3 channel pll15 ctrl mask bit
+** [28:28] SM_TMR4_PLL15_MASK
+** TIMER4 channel pll15 ctrl mask bit
+** [29:29] SM_TMR5_PLL15_MASK
+** TIMER5 channel pll15 ctrl mask bit
+** [30:30] SM_TMR6_PLL15_MASK
+** TIMER6 channel pll15 ctrl mask bit
+** [31:31] SM_TMR7_PLL15_MASK
+** TIMER7 channel pll15 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PLL_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x012C))
+/*=========================================
+** TIMER channel pwr ctrl mask bit:
+** TIMER channel pwr ctrl mask bit
+** [0:0] SM_TMR0_PWR0_MASK
+** TIMER0 channel pwr0 ctrl mask bit
+** [1:1] SM_TMR1_PWR0_MASK
+** TIMER1 channel pwr0 ctrl mask bit
+** [2:2] SM_TMR2_PWR0_MASK
+** TIMER2 channel pwr0 ctrl mask bit
+** [3:3] SM_TMR3_PWR0_MASK
+** TIMER3 channel pwr0 ctrl mask bit
+** [4:4] SM_TMR4_PWR0_MASK
+** TIMER4 channel pwr0 ctrl mask bit
+** [5:5] SM_TMR5_PWR0_MASK
+** TIMER5 channel pwr0 ctrl mask bit
+** [6:6] SM_TMR6_PWR0_MASK
+** TIMER6 channel pwr0 ctrl mask bit
+** [7:7] SM_TMR7_PWR0_MASK
+** TIMER7 channel pwr0 ctrl mask bit
+** [8:8] SM_TMR0_PWR1_MASK
+** TIMER0 channel pwr1 ctrl mask bit
+** [9:9] SM_TMR1_PWR1_MASK
+** TIMER1 channel pwr1 ctrl mask bit
+** [10:10] SM_TMR2_PWR1_MASK
+** TIMER2 channel pwr1 ctrl mask bit
+** [11:11] SM_TMR3_PWR1_MASK
+** TIMER3 channel pwr1 ctrl mask bit
+** [12:12] SM_TMR4_PWR1_MASK
+** TIMER4 channel pwr1 ctrl mask bit
+** [13:13] SM_TMR5_PWR1_MASK
+** TIMER5 channel pwr1 ctrl mask bit
+** [14:14] SM_TMR6_PWR1_MASK
+** TIMER6 channel pwr1 ctrl mask bit
+** [15:15] SM_TMR7_PWR1_MASK
+** TIMER7 channel pwr1 ctrl mask bit
+** [16:16] SM_TMR0_PWR2_MASK
+** TIMER0 channel pwr2 ctrl mask bit
+** [17:17] SM_TMR1_PWR2_MASK
+** TIMER1 channel pwr2 ctrl mask bit
+** [18:18] SM_TMR2_PWR2_MASK
+** TIMER2 channel pwr2 ctrl mask bit
+** [19:19] SM_TMR3_PWR2_MASK
+** TIMER3 channel pwr2 ctrl mask bit
+** [20:20] SM_TMR4_PWR2_MASK
+** TIMER4 channel pwr2 ctrl mask bit
+** [21:21] SM_TMR5_PWR2_MASK
+** TIMER5 channel pwr2 ctrl mask bit
+** [22:22] SM_TMR6_PWR2_MASK
+** TIMER6 channel pwr2 ctrl mask bit
+** [23:23] SM_TMR7_PWR2_MASK
+** TIMER7 channel pwr2 ctrl mask bit
+** [24:24] SM_TMR0_PWR3_MASK
+** TIMER0 channel pwr3 ctrl mask bit
+** [25:25] SM_TMR1_PWR3_MASK
+** TIMER1 channel pwr3 ctrl mask bit
+** [26:26] SM_TMR2_PWR3_MASK
+** TIMER2 channel pwr3 ctrl mask bit
+** [27:27] SM_TMR3_PWR3_MASK
+** TIMER3 channel pwr3 ctrl mask bit
+** [28:28] SM_TMR4_PWR3_MASK
+** TIMER4 channel pwr3 ctrl mask bit
+** [29:29] SM_TMR5_PWR3_MASK
+** TIMER5 channel pwr3 ctrl mask bit
+** [30:30] SM_TMR6_PWR3_MASK
+** TIMER6 channel pwr3 ctrl mask bit
+** [31:31] SM_TMR7_PWR3_MASK
+** TIMER7 channel pwr3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0140))
+/*=========================================
+** TIMER channel pwr ctrl mask bit:
+** TIMER channel pwr ctrl mask bit
+** [0:0] SM_TMR0_PWR4_MASK
+** TIMER0 channel pwr4 ctrl mask bit
+** [1:1] SM_TMR1_PWR4_MASK
+** TIMER1 channel pwr4 ctrl mask bit
+** [2:2] SM_TMR2_PWR4_MASK
+** TIMER2 channel pwr4 ctrl mask bit
+** [3:3] SM_TMR3_PWR4_MASK
+** TIMER3 channel pwr4 ctrl mask bit
+** [4:4] SM_TMR4_PWR4_MASK
+** TIMER4 channel pwr4 ctrl mask bit
+** [5:5] SM_TMR5_PWR4_MASK
+** TIMER5 channel pwr4 ctrl mask bit
+** [6:6] SM_TMR6_PWR4_MASK
+** TIMER6 channel pwr4 ctrl mask bit
+** [7:7] SM_TMR7_PWR4_MASK
+** TIMER7 channel pwr4 ctrl mask bit
+** [8:8] SM_TMR0_PWR5_MASK
+** TIMER0 channel pwr5 ctrl mask bit
+** [9:9] SM_TMR1_PWR5_MASK
+** TIMER1 channel pwr5 ctrl mask bit
+** [10:10] SM_TMR2_PWR5_MASK
+** TIMER2 channel pwr5 ctrl mask bit
+** [11:11] SM_TMR3_PWR5_MASK
+** TIMER3 channel pwr5 ctrl mask bit
+** [12:12] SM_TMR4_PWR5_MASK
+** TIMER4 channel pwr5 ctrl mask bit
+** [13:13] SM_TMR5_PWR5_MASK
+** TIMER5 channel pwr5 ctrl mask bit
+** [14:14] SM_TMR6_PWR5_MASK
+** TIMER6 channel pwr5 ctrl mask bit
+** [15:15] SM_TMR7_PWR5_MASK
+** TIMER7 channel pwr5 ctrl mask bit
+** [16:16] SM_TMR0_PWR6_MASK
+** TIMER0 channel pwr6 ctrl mask bit
+** [17:17] SM_TMR1_PWR6_MASK
+** TIMER1 channel pwr6 ctrl mask bit
+** [18:18] SM_TMR2_PWR6_MASK
+** TIMER2 channel pwr6 ctrl mask bit
+** [19:19] SM_TMR3_PWR6_MASK
+** TIMER3 channel pwr6 ctrl mask bit
+** [20:20] SM_TMR4_PWR6_MASK
+** TIMER4 channel pwr6 ctrl mask bit
+** [21:21] SM_TMR5_PWR6_MASK
+** TIMER5 channel pwr6 ctrl mask bit
+** [22:22] SM_TMR6_PWR6_MASK
+** TIMER6 channel pwr6 ctrl mask bit
+** [23:23] SM_TMR7_PWR6_MASK
+** TIMER7 channel pwr6 ctrl mask bit
+** [24:24] SM_TMR0_PWR7_MASK
+** TIMER0 channel pwr7 ctrl mask bit
+** [25:25] SM_TMR1_PWR7_MASK
+** TIMER1 channel pwr7 ctrl mask bit
+** [26:26] SM_TMR2_PWR7_MASK
+** TIMER2 channel pwr7 ctrl mask bit
+** [27:27] SM_TMR3_PWR7_MASK
+** TIMER3 channel pwr7 ctrl mask bit
+** [28:28] SM_TMR4_PWR7_MASK
+** TIMER4 channel pwr7 ctrl mask bit
+** [29:29] SM_TMR5_PWR7_MASK
+** TIMER5 channel pwr7 ctrl mask bit
+** [30:30] SM_TMR6_PWR7_MASK
+** TIMER6 channel pwr7 ctrl mask bit
+** [31:31] SM_TMR7_PWR7_MASK
+** TIMER7 channel pwr7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0144))
+/*=========================================
+** TIMER channel pwr ctrl mask bit:
+** TIMER channel pwr ctrl mask bit
+** [0:0] SM_TMR0_PWR8_MASK
+** TIMER0 channel pwr8 ctrl mask bit
+** [1:1] SM_TMR1_PWR8_MASK
+** TIMER1 channel pwr8 ctrl mask bit
+** [2:2] SM_TMR2_PWR8_MASK
+** TIMER2 channel pwr8 ctrl mask bit
+** [3:3] SM_TMR3_PWR8_MASK
+** TIMER3 channel pwr8 ctrl mask bit
+** [4:4] SM_TMR4_PWR8_MASK
+** TIMER4 channel pwr8 ctrl mask bit
+** [5:5] SM_TMR5_PWR8_MASK
+** TIMER5 channel pwr8 ctrl mask bit
+** [6:6] SM_TMR6_PWR8_MASK
+** TIMER6 channel pwr8 ctrl mask bit
+** [7:7] SM_TMR7_PWR8_MASK
+** TIMER7 channel pwr8 ctrl mask bit
+** [8:8] SM_TMR0_PWR9_MASK
+** TIMER0 channel pwr9 ctrl mask bit
+** [9:9] SM_TMR1_PWR9_MASK
+** TIMER1 channel pwr9 ctrl mask bit
+** [10:10] SM_TMR2_PWR9_MASK
+** TIMER2 channel pwr9 ctrl mask bit
+** [11:11] SM_TMR3_PWR9_MASK
+** TIMER3 channel pwr9 ctrl mask bit
+** [12:12] SM_TMR4_PWR9_MASK
+** TIMER4 channel pwr9 ctrl mask bit
+** [13:13] SM_TMR5_PWR9_MASK
+** TIMER5 channel pwr9 ctrl mask bit
+** [14:14] SM_TMR6_PWR9_MASK
+** TIMER6 channel pwr9 ctrl mask bit
+** [15:15] SM_TMR7_PWR9_MASK
+** TIMER7 channel pwr9 ctrl mask bit
+** [16:16] SM_TMR0_PWR10_MASK
+** TIMER0 channel pwr10 ctrl mask bit
+** [17:17] SM_TMR1_PWR10_MASK
+** TIMER1 channel pwr10 ctrl mask bit
+** [18:18] SM_TMR2_PWR10_MASK
+** TIMER2 channel pwr10 ctrl mask bit
+** [19:19] SM_TMR3_PWR10_MASK
+** TIMER3 channel pwr10 ctrl mask bit
+** [20:20] SM_TMR4_PWR10_MASK
+** TIMER4 channel pwr10 ctrl mask bit
+** [21:21] SM_TMR5_PWR10_MASK
+** TIMER5 channel pwr10 ctrl mask bit
+** [22:22] SM_TMR6_PWR10_MASK
+** TIMER6 channel pwr10 ctrl mask bit
+** [23:23] SM_TMR7_PWR10_MASK
+** TIMER7 channel pwr10 ctrl mask bit
+** [24:24] SM_TMR0_PWR11_MASK
+** TIMER0 channel pwr11 ctrl mask bit
+** [25:25] SM_TMR1_PWR11_MASK
+** TIMER1 channel pwr11 ctrl mask bit
+** [26:26] SM_TMR2_PWR11_MASK
+** TIMER2 channel pwr11 ctrl mask bit
+** [27:27] SM_TMR3_PWR11_MASK
+** TIMER3 channel pwr11 ctrl mask bit
+** [28:28] SM_TMR4_PWR11_MASK
+** TIMER4 channel pwr11 ctrl mask bit
+** [29:29] SM_TMR5_PWR11_MASK
+** TIMER5 channel pwr11 ctrl mask bit
+** [30:30] SM_TMR6_PWR11_MASK
+** TIMER6 channel pwr11 ctrl mask bit
+** [31:31] SM_TMR7_PWR11_MASK
+** TIMER7 channel pwr11 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PWR_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0148))
+/*=========================================
+** TIMER channel pwr ctrl mask bit:
+** TIMER channel pwr ctrl mask bit
+** [0:0] SM_TMR0_PWR12_MASK
+** TIMER0 channel pwr12 ctrl mask bit
+** [1:1] SM_TMR1_PWR12_MASK
+** TIMER1 channel pwr12 ctrl mask bit
+** [2:2] SM_TMR2_PWR12_MASK
+** TIMER2 channel pwr12 ctrl mask bit
+** [3:3] SM_TMR3_PWR12_MASK
+** TIMER3 channel pwr12 ctrl mask bit
+** [4:4] SM_TMR4_PWR12_MASK
+** TIMER4 channel pwr12 ctrl mask bit
+** [5:5] SM_TMR5_PWR12_MASK
+** TIMER5 channel pwr12 ctrl mask bit
+** [6:6] SM_TMR6_PWR12_MASK
+** TIMER6 channel pwr12 ctrl mask bit
+** [7:7] SM_TMR7_PWR12_MASK
+** TIMER7 channel pwr12 ctrl mask bit
+** [8:8] SM_TMR0_PWR13_MASK
+** TIMER0 channel pwr13 ctrl mask bit
+** [9:9] SM_TMR1_PWR13_MASK
+** TIMER1 channel pwr13 ctrl mask bit
+** [10:10] SM_TMR2_PWR13_MASK
+** TIMER2 channel pwr13 ctrl mask bit
+** [11:11] SM_TMR3_PWR13_MASK
+** TIMER3 channel pwr13 ctrl mask bit
+** [12:12] SM_TMR4_PWR13_MASK
+** TIMER4 channel pwr13 ctrl mask bit
+** [13:13] SM_TMR5_PWR13_MASK
+** TIMER5 channel pwr13 ctrl mask bit
+** [14:14] SM_TMR6_PWR13_MASK
+** TIMER6 channel pwr13 ctrl mask bit
+** [15:15] SM_TMR7_PWR13_MASK
+** TIMER7 channel pwr13 ctrl mask bit
+** [16:16] SM_TMR0_PWR14_MASK
+** TIMER0 channel pwr14 ctrl mask bit
+** [17:17] SM_TMR1_PWR14_MASK
+** TIMER1 channel pwr14 ctrl mask bit
+** [18:18] SM_TMR2_PWR14_MASK
+** TIMER2 channel pwr14 ctrl mask bit
+** [19:19] SM_TMR3_PWR14_MASK
+** TIMER3 channel pwr14 ctrl mask bit
+** [20:20] SM_TMR4_PWR14_MASK
+** TIMER4 channel pwr14 ctrl mask bit
+** [21:21] SM_TMR5_PWR14_MASK
+** TIMER5 channel pwr14 ctrl mask bit
+** [22:22] SM_TMR6_PWR14_MASK
+** TIMER6 channel pwr14 ctrl mask bit
+** [23:23] SM_TMR7_PWR14_MASK
+** TIMER7 channel pwr14 ctrl mask bit
+** [24:24] SM_TMR0_PWR15_MASK
+** TIMER0 channel pwr15 ctrl mask bit
+** [25:25] SM_TMR1_PWR15_MASK
+** TIMER1 channel pwr15 ctrl mask bit
+** [26:26] SM_TMR2_PWR15_MASK
+** TIMER2 channel pwr15 ctrl mask bit
+** [27:27] SM_TMR3_PWR15_MASK
+** TIMER3 channel pwr15 ctrl mask bit
+** [28:28] SM_TMR4_PWR15_MASK
+** TIMER4 channel pwr15 ctrl mask bit
+** [29:29] SM_TMR5_PWR15_MASK
+** TIMER5 channel pwr15 ctrl mask bit
+** [30:30] SM_TMR6_PWR15_MASK
+** TIMER6 channel pwr15 ctrl mask bit
+** [31:31] SM_TMR7_PWR15_MASK
+** TIMER7 channel pwr15 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PWR_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x014C))
+/*=========================================
+** TIMER channel pwr ctrl mask bit:
+** TIMER channel pwr ctrl mask bit
+** [0:0] SM_TMR0_PWR16_MASK
+** TIMER0 channel pwr16 ctrl mask bit
+** [1:1] SM_TMR1_PWR16_MASK
+** TIMER1 channel pwr16 ctrl mask bit
+** [2:2] SM_TMR2_PWR16_MASK
+** TIMER2 channel pwr16 ctrl mask bit
+** [3:3] SM_TMR3_PWR16_MASK
+** TIMER3 channel pwr16 ctrl mask bit
+** [4:4] SM_TMR4_PWR16_MASK
+** TIMER4 channel pwr16 ctrl mask bit
+** [5:5] SM_TMR5_PWR16_MASK
+** TIMER5 channel pwr16 ctrl mask bit
+** [6:6] SM_TMR6_PWR16_MASK
+** TIMER6 channel pwr16 ctrl mask bit
+** [7:7] SM_TMR7_PWR16_MASK
+** TIMER7 channel pwr16 ctrl mask bit
+** [8:8] SM_TMR0_PWR17_MASK
+** TIMER0 channel pwr17 ctrl mask bit
+** [9:9] SM_TMR1_PWR17_MASK
+** TIMER1 channel pwr17 ctrl mask bit
+** [10:10] SM_TMR2_PWR17_MASK
+** TIMER2 channel pwr17 ctrl mask bit
+** [11:11] SM_TMR3_PWR17_MASK
+** TIMER3 channel pwr17 ctrl mask bit
+** [12:12] SM_TMR4_PWR17_MASK
+** TIMER4 channel pwr17 ctrl mask bit
+** [13:13] SM_TMR5_PWR17_MASK
+** TIMER5 channel pwr17 ctrl mask bit
+** [14:14] SM_TMR6_PWR17_MASK
+** TIMER6 channel pwr17 ctrl mask bit
+** [15:15] SM_TMR7_PWR17_MASK
+** TIMER7 channel pwr17 ctrl mask bit
+** [16:16] SM_TMR0_PWR18_MASK
+** TIMER0 channel pwr18 ctrl mask bit
+** [17:17] SM_TMR1_PWR18_MASK
+** TIMER1 channel pwr18 ctrl mask bit
+** [18:18] SM_TMR2_PWR18_MASK
+** TIMER2 channel pwr18 ctrl mask bit
+** [19:19] SM_TMR3_PWR18_MASK
+** TIMER3 channel pwr18 ctrl mask bit
+** [20:20] SM_TMR4_PWR18_MASK
+** TIMER4 channel pwr18 ctrl mask bit
+** [21:21] SM_TMR5_PWR18_MASK
+** TIMER5 channel pwr18 ctrl mask bit
+** [22:22] SM_TMR6_PWR18_MASK
+** TIMER6 channel pwr18 ctrl mask bit
+** [23:23] SM_TMR7_PWR18_MASK
+** TIMER7 channel pwr18 ctrl mask bit
+** [24:24] SM_TMR0_PWR19_MASK
+** TIMER0 channel pwr19 ctrl mask bit
+** [25:25] SM_TMR1_PWR19_MASK
+** TIMER1 channel pwr19 ctrl mask bit
+** [26:26] SM_TMR2_PWR19_MASK
+** TIMER2 channel pwr19 ctrl mask bit
+** [27:27] SM_TMR3_PWR19_MASK
+** TIMER3 channel pwr19 ctrl mask bit
+** [28:28] SM_TMR4_PWR19_MASK
+** TIMER4 channel pwr19 ctrl mask bit
+** [29:29] SM_TMR5_PWR19_MASK
+** TIMER5 channel pwr19 ctrl mask bit
+** [30:30] SM_TMR6_PWR19_MASK
+** TIMER6 channel pwr19 ctrl mask bit
+** [31:31] SM_TMR7_PWR19_MASK
+** TIMER7 channel pwr19 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PWR_MASK4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0150))
+/*=========================================
+** TIMER channel pwr ctrl mask bit:
+** TIMER channel pwr ctrl mask bit
+** [0:0] SM_TMR0_PWR20_MASK
+** TIMER0 channel pwr20 ctrl mask bit
+** [1:1] SM_TMR1_PWR20_MASK
+** TIMER1 channel pwr20 ctrl mask bit
+** [2:2] SM_TMR2_PWR20_MASK
+** TIMER2 channel pwr20 ctrl mask bit
+** [3:3] SM_TMR3_PWR20_MASK
+** TIMER3 channel pwr20 ctrl mask bit
+** [4:4] SM_TMR4_PWR20_MASK
+** TIMER4 channel pwr20 ctrl mask bit
+** [5:5] SM_TMR5_PWR20_MASK
+** TIMER5 channel pwr20 ctrl mask bit
+** [6:6] SM_TMR6_PWR20_MASK
+** TIMER6 channel pwr20 ctrl mask bit
+** [7:7] SM_TMR7_PWR20_MASK
+** TIMER7 channel pwr20 ctrl mask bit
+** [8:8] SM_TMR0_PWR21_MASK
+** TIMER0 channel pwr21 ctrl mask bit
+** [9:9] SM_TMR1_PWR21_MASK
+** TIMER1 channel pwr21 ctrl mask bit
+** [10:10] SM_TMR2_PWR21_MASK
+** TIMER2 channel pwr21 ctrl mask bit
+** [11:11] SM_TMR3_PWR21_MASK
+** TIMER3 channel pwr21 ctrl mask bit
+** [12:12] SM_TMR4_PWR21_MASK
+** TIMER4 channel pwr21 ctrl mask bit
+** [13:13] SM_TMR5_PWR21_MASK
+** TIMER5 channel pwr21 ctrl mask bit
+** [14:14] SM_TMR6_PWR21_MASK
+** TIMER6 channel pwr21 ctrl mask bit
+** [15:15] SM_TMR7_PWR21_MASK
+** TIMER7 channel pwr21 ctrl mask bit
+** [16:16] SM_TMR0_PWR22_MASK
+** TIMER0 channel pwr22 ctrl mask bit
+** [17:17] SM_TMR1_PWR22_MASK
+** TIMER1 channel pwr22 ctrl mask bit
+** [18:18] SM_TMR2_PWR22_MASK
+** TIMER2 channel pwr22 ctrl mask bit
+** [19:19] SM_TMR3_PWR22_MASK
+** TIMER3 channel pwr22 ctrl mask bit
+** [20:20] SM_TMR4_PWR22_MASK
+** TIMER4 channel pwr22 ctrl mask bit
+** [21:21] SM_TMR5_PWR22_MASK
+** TIMER5 channel pwr22 ctrl mask bit
+** [22:22] SM_TMR6_PWR22_MASK
+** TIMER6 channel pwr22 ctrl mask bit
+** [23:23] SM_TMR7_PWR22_MASK
+** TIMER7 channel pwr22 ctrl mask bit
+** [24:24] SM_TMR0_PWR23_MASK
+** TIMER0 channel pwr23 ctrl mask bit
+** [25:25] SM_TMR1_PWR23_MASK
+** TIMER1 channel pwr23 ctrl mask bit
+** [26:26] SM_TMR2_PWR23_MASK
+** TIMER2 channel pwr23 ctrl mask bit
+** [27:27] SM_TMR3_PWR23_MASK
+** TIMER3 channel pwr23 ctrl mask bit
+** [28:28] SM_TMR4_PWR23_MASK
+** TIMER4 channel pwr23 ctrl mask bit
+** [29:29] SM_TMR5_PWR23_MASK
+** TIMER5 channel pwr23 ctrl mask bit
+** [30:30] SM_TMR6_PWR23_MASK
+** TIMER6 channel pwr23 ctrl mask bit
+** [31:31] SM_TMR7_PWR23_MASK
+** TIMER7 channel pwr23 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PWR_MASK5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0154))
+/*=========================================
+** TIMER channel mas trigger ctrl mask bit:
+** TIMER channel mas trigger ctrl mask bit
+** [0:0] SM_TMR0_MAS_TRIG0_MASK
+** TIMER0 channel mas trigger channel0 ctrl mask bit
+** [1:1] SM_TMR1_MAS_TRIG0_MASK
+** TIMER1 channel mas trigger channel0 ctrl mask bit
+** [2:2] SM_TMR2_MAS_TRIG0_MASK
+** TIMER2 channel mas trigger channel0 ctrl mask bit
+** [3:3] SM_TMR3_MAS_TRIG0_MASK
+** TIMER3 channel mas trigger channel0 ctrl mask bit
+** [4:4] SM_TMR4_MAS_TRIG0_MASK
+** TIMER4 channel mas trigger channel0 ctrl mask bit
+** [5:5] SM_TMR5_MAS_TRIG0_MASK
+** TIMER5 channel mas trigger channel0 ctrl mask bit
+** [6:6] SM_TMR6_MAS_TRIG0_MASK
+** TIMER6 channel mas trigger channel0 ctrl mask bit
+** [7:7] SM_TMR7_MAS_TRIG0_MASK
+** TIMER7 channel mas trigger channel0 ctrl mask bit
+** [8:8] SM_TMR0_MAS_TRIG1_MASK
+** TIMER0 channel mas trigger channel1 ctrl mask bit
+** [9:9] SM_TMR1_MAS_TRIG1_MASK
+** TIMER1 channel mas trigger channel1 ctrl mask bit
+** [10:10] SM_TMR2_MAS_TRIG1_MASK
+** TIMER2 channel mas trigger channel1 ctrl mask bit
+** [11:11] SM_TMR3_MAS_TRIG1_MASK
+** TIMER3 channel mas trigger channel1 ctrl mask bit
+** [12:12] SM_TMR4_MAS_TRIG1_MASK
+** TIMER4 channel mas trigger channel1 ctrl mask bit
+** [13:13] SM_TMR5_MAS_TRIG1_MASK
+** TIMER5 channel mas trigger channel1 ctrl mask bit
+** [14:14] SM_TMR6_MAS_TRIG1_MASK
+** TIMER6 channel mas trigger channel1 ctrl mask bit
+** [15:15] SM_TMR7_MAS_TRIG1_MASK
+** TIMER7 channel mas trigger channel1 ctrl mask bit
+** [16:16] SM_TMR0_MAS_TRIG2_MASK
+** TIMER0 channel mas trigger channel2 ctrl mask bit
+** [17:17] SM_TMR1_MAS_TRIG2_MASK
+** TIMER1 channel mas trigger channel2 ctrl mask bit
+** [18:18] SM_TMR2_MAS_TRIG2_MASK
+** TIMER2 channel mas trigger channel2 ctrl mask bit
+** [19:19] SM_TMR3_MAS_TRIG2_MASK
+** TIMER3 channel mas trigger channel2 ctrl mask bit
+** [20:20] SM_TMR4_MAS_TRIG2_MASK
+** TIMER4 channel mas trigger channel2 ctrl mask bit
+** [21:21] SM_TMR5_MAS_TRIG2_MASK
+** TIMER5 channel mas trigger channel2 ctrl mask bit
+** [22:22] SM_TMR6_MAS_TRIG2_MASK
+** TIMER6 channel mas trigger channel2 ctrl mask bit
+** [23:23] SM_TMR7_MAS_TRIG2_MASK
+** TIMER7 channel mas trigger channel2 ctrl mask bit
+** [24:24] SM_TMR0_MAS_TRIG3_MASK
+** TIMER0 channel mas trigger channel3 ctrl mask bit
+** [25:25] SM_TMR1_MAS_TRIG3_MASK
+** TIMER1 channel mas trigger channel3 ctrl mask bit
+** [26:26] SM_TMR2_MAS_TRIG3_MASK
+** TIMER2 channel mas trigger channel3 ctrl mask bit
+** [27:27] SM_TMR3_MAS_TRIG3_MASK
+** TIMER3 channel mas trigger channel3 ctrl mask bit
+** [28:28] SM_TMR4_MAS_TRIG3_MASK
+** TIMER4 channel mas trigger channel3 ctrl mask bit
+** [29:29] SM_TMR5_MAS_TRIG3_MASK
+** TIMER5 channel mas trigger channel3 ctrl mask bit
+** [30:30] SM_TMR6_MAS_TRIG3_MASK
+** TIMER6 channel mas trigger channel3 ctrl mask bit
+** [31:31] SM_TMR7_MAS_TRIG3_MASK
+** TIMER7 channel mas trigger channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0160))
+/*=========================================
+** TIMER channel mas trigger ctrl mask bit:
+** TIMER channel mas trigger ctrl mask bit
+** [0:0] SM_TMR0_MAS_TRIG4_MASK
+** TIMER0 channel mas trigger channel4 ctrl mask bit
+** [1:1] SM_TMR1_MAS_TRIG4_MASK
+** TIMER1 channel mas trigger channel4 ctrl mask bit
+** [2:2] SM_TMR2_MAS_TRIG4_MASK
+** TIMER2 channel mas trigger channel4 ctrl mask bit
+** [3:3] SM_TMR3_MAS_TRIG4_MASK
+** TIMER3 channel mas trigger channel4 ctrl mask bit
+** [4:4] SM_TMR4_MAS_TRIG4_MASK
+** TIMER4 channel mas trigger channel4 ctrl mask bit
+** [5:5] SM_TMR5_MAS_TRIG4_MASK
+** TIMER5 channel mas trigger channel4 ctrl mask bit
+** [6:6] SM_TMR6_MAS_TRIG4_MASK
+** TIMER6 channel mas trigger channel4 ctrl mask bit
+** [7:7] SM_TMR7_MAS_TRIG4_MASK
+** TIMER7 channel mas trigger channel4 ctrl mask bit
+** [8:8] SM_TMR0_MAS_TRIG5_MASK
+** TIMER0 channel mas trigger channel5 ctrl mask bit
+** [9:9] SM_TMR1_MAS_TRIG5_MASK
+** TIMER1 channel mas trigger channel5 ctrl mask bit
+** [10:10] SM_TMR2_MAS_TRIG5_MASK
+** TIMER2 channel mas trigger channel5 ctrl mask bit
+** [11:11] SM_TMR3_MAS_TRIG5_MASK
+** TIMER3 channel mas trigger channel5 ctrl mask bit
+** [12:12] SM_TMR4_MAS_TRIG5_MASK
+** TIMER4 channel mas trigger channel5 ctrl mask bit
+** [13:13] SM_TMR5_MAS_TRIG5_MASK
+** TIMER5 channel mas trigger channel5 ctrl mask bit
+** [14:14] SM_TMR6_MAS_TRIG5_MASK
+** TIMER6 channel mas trigger channel5 ctrl mask bit
+** [15:15] SM_TMR7_MAS_TRIG5_MASK
+** TIMER7 channel mas trigger channel5 ctrl mask bit
+** [16:16] SM_TMR0_MAS_TRIG6_MASK
+** TIMER0 channel mas trigger channel6 ctrl mask bit
+** [17:17] SM_TMR1_MAS_TRIG6_MASK
+** TIMER1 channel mas trigger channel6 ctrl mask bit
+** [18:18] SM_TMR2_MAS_TRIG6_MASK
+** TIMER2 channel mas trigger channel6 ctrl mask bit
+** [19:19] SM_TMR3_MAS_TRIG6_MASK
+** TIMER3 channel mas trigger channel6 ctrl mask bit
+** [20:20] SM_TMR4_MAS_TRIG6_MASK
+** TIMER4 channel mas trigger channel6 ctrl mask bit
+** [21:21] SM_TMR5_MAS_TRIG6_MASK
+** TIMER5 channel mas trigger channel6 ctrl mask bit
+** [22:22] SM_TMR6_MAS_TRIG6_MASK
+** TIMER6 channel mas trigger channel6 ctrl mask bit
+** [23:23] SM_TMR7_MAS_TRIG6_MASK
+** TIMER7 channel mas trigger channel6 ctrl mask bit
+** [24:24] SM_TMR0_MAS_TRIG7_MASK
+** TIMER0 channel mas trigger channel7 ctrl mask bit
+** [25:25] SM_TMR1_MAS_TRIG7_MASK
+** TIMER1 channel mas trigger channel7 ctrl mask bit
+** [26:26] SM_TMR2_MAS_TRIG7_MASK
+** TIMER2 channel mas trigger channel7 ctrl mask bit
+** [27:27] SM_TMR3_MAS_TRIG7_MASK
+** TIMER3 channel mas trigger channel7 ctrl mask bit
+** [28:28] SM_TMR4_MAS_TRIG7_MASK
+** TIMER4 channel mas trigger channel7 ctrl mask bit
+** [29:29] SM_TMR5_MAS_TRIG7_MASK
+** TIMER5 channel mas trigger channel7 ctrl mask bit
+** [30:30] SM_TMR6_MAS_TRIG7_MASK
+** TIMER6 channel mas trigger channel7 ctrl mask bit
+** [31:31] SM_TMR7_MAS_TRIG7_MASK
+** TIMER7 channel mas trigger channel7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0164))
+/*=========================================
+** TIMER channel timer trigger ctrl mask bit:
+** TIMER channel timer trigger ctrl mask bit
+** [0:0] SM_TMR0_TIMER_TRIG0_MASK
+** TIMER0 channel timer trigger channel0 ctrl mask bit
+** [1:1] SM_TMR1_TIMER_TRIG0_MASK
+** TIMER1 channel timer trigger channel0 ctrl mask bit
+** [2:2] SM_TMR2_TIMER_TRIG0_MASK
+** TIMER2 channel timer trigger channel0 ctrl mask bit
+** [3:3] SM_TMR3_TIMER_TRIG0_MASK
+** TIMER3 channel timer trigger channel0 ctrl mask bit
+** [4:4] SM_TMR4_TIMER_TRIG0_MASK
+** TIMER4 channel timer trigger channel0 ctrl mask bit
+** [5:5] SM_TMR5_TIMER_TRIG0_MASK
+** TIMER5 channel timer trigger channel0 ctrl mask bit
+** [6:6] SM_TMR6_TIMER_TRIG0_MASK
+** TIMER6 channel timer trigger channel0 ctrl mask bit
+** [7:7] SM_TMR7_TIMER_TRIG0_MASK
+** TIMER7 channel timer trigger channel0 ctrl mask bit
+** [8:8] SM_TMR0_TIMER_TRIG1_MASK
+** TIMER0 channel timer trigger channel1 ctrl mask bit
+** [9:9] SM_TMR1_TIMER_TRIG1_MASK
+** TIMER1 channel timer trigger channel1 ctrl mask bit
+** [10:10] SM_TMR2_TIMER_TRIG1_MASK
+** TIMER2 channel timer trigger channel1 ctrl mask bit
+** [11:11] SM_TMR3_TIMER_TRIG1_MASK
+** TIMER3 channel timer trigger channel1 ctrl mask bit
+** [12:12] SM_TMR4_TIMER_TRIG1_MASK
+** TIMER4 channel timer trigger channel1 ctrl mask bit
+** [13:13] SM_TMR5_TIMER_TRIG1_MASK
+** TIMER5 channel timer trigger channel1 ctrl mask bit
+** [14:14] SM_TMR6_TIMER_TRIG1_MASK
+** TIMER6 channel timer trigger channel1 ctrl mask bit
+** [15:15] SM_TMR7_TIMER_TRIG1_MASK
+** TIMER7 channel timer trigger channel1 ctrl mask bit
+** [16:16] SM_TMR0_TIMER_TRIG2_MASK
+** TIMER0 channel timer trigger channel2 ctrl mask bit
+** [17:17] SM_TMR1_TIMER_TRIG2_MASK
+** TIMER1 channel timer trigger channel2 ctrl mask bit
+** [18:18] SM_TMR2_TIMER_TRIG2_MASK
+** TIMER2 channel timer trigger channel2 ctrl mask bit
+** [19:19] SM_TMR3_TIMER_TRIG2_MASK
+** TIMER3 channel timer trigger channel2 ctrl mask bit
+** [20:20] SM_TMR4_TIMER_TRIG2_MASK
+** TIMER4 channel timer trigger channel2 ctrl mask bit
+** [21:21] SM_TMR5_TIMER_TRIG2_MASK
+** TIMER5 channel timer trigger channel2 ctrl mask bit
+** [22:22] SM_TMR6_TIMER_TRIG2_MASK
+** TIMER6 channel timer trigger channel2 ctrl mask bit
+** [23:23] SM_TMR7_TIMER_TRIG2_MASK
+** TIMER7 channel timer trigger channel2 ctrl mask bit
+** [24:24] SM_TMR0_TIMER_TRIG3_MASK
+** TIMER0 channel timer trigger channel3 ctrl mask bit
+** [25:25] SM_TMR1_TIMER_TRIG3_MASK
+** TIMER1 channel timer trigger channel3 ctrl mask bit
+** [26:26] SM_TMR2_TIMER_TRIG3_MASK
+** TIMER2 channel timer trigger channel3 ctrl mask bit
+** [27:27] SM_TMR3_TIMER_TRIG3_MASK
+** TIMER3 channel timer trigger channel3 ctrl mask bit
+** [28:28] SM_TMR4_TIMER_TRIG3_MASK
+** TIMER4 channel timer trigger channel3 ctrl mask bit
+** [29:29] SM_TMR5_TIMER_TRIG3_MASK
+** TIMER5 channel timer trigger channel3 ctrl mask bit
+** [30:30] SM_TMR6_TIMER_TRIG3_MASK
+** TIMER6 channel timer trigger channel3 ctrl mask bit
+** [31:31] SM_TMR7_TIMER_TRIG3_MASK
+** TIMER7 channel timer trigger channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0170))
+/*=========================================
+** TIMER channel timer trigger ctrl mask bit:
+** TIMER channel timer trigger ctrl mask bit
+** [0:0] SM_TMR0_TIMER_TRIG4_MASK
+** TIMER0 channel timer trigger channel4 ctrl mask bit
+** [1:1] SM_TMR1_TIMER_TRIG4_MASK
+** TIMER1 channel timer trigger channel4 ctrl mask bit
+** [2:2] SM_TMR2_TIMER_TRIG4_MASK
+** TIMER2 channel timer trigger channel4 ctrl mask bit
+** [3:3] SM_TMR3_TIMER_TRIG4_MASK
+** TIMER3 channel timer trigger channel4 ctrl mask bit
+** [4:4] SM_TMR4_TIMER_TRIG4_MASK
+** TIMER4 channel timer trigger channel4 ctrl mask bit
+** [5:5] SM_TMR5_TIMER_TRIG4_MASK
+** TIMER5 channel timer trigger channel4 ctrl mask bit
+** [6:6] SM_TMR6_TIMER_TRIG4_MASK
+** TIMER6 channel timer trigger channel4 ctrl mask bit
+** [7:7] SM_TMR7_TIMER_TRIG4_MASK
+** TIMER7 channel timer trigger channel4 ctrl mask bit
+** [8:8] SM_TMR0_TIMER_TRIG5_MASK
+** TIMER0 channel timer trigger channel5 ctrl mask bit
+** [9:9] SM_TMR1_TIMER_TRIG5_MASK
+** TIMER1 channel timer trigger channel5 ctrl mask bit
+** [10:10] SM_TMR2_TIMER_TRIG5_MASK
+** TIMER2 channel timer trigger channel5 ctrl mask bit
+** [11:11] SM_TMR3_TIMER_TRIG5_MASK
+** TIMER3 channel timer trigger channel5 ctrl mask bit
+** [12:12] SM_TMR4_TIMER_TRIG5_MASK
+** TIMER4 channel timer trigger channel5 ctrl mask bit
+** [13:13] SM_TMR5_TIMER_TRIG5_MASK
+** TIMER5 channel timer trigger channel5 ctrl mask bit
+** [14:14] SM_TMR6_TIMER_TRIG5_MASK
+** TIMER6 channel timer trigger channel5 ctrl mask bit
+** [15:15] SM_TMR7_TIMER_TRIG5_MASK
+** TIMER7 channel timer trigger channel5 ctrl mask bit
+** [16:16] SM_TMR0_TIMER_TRIG6_MASK
+** TIMER0 channel timer trigger channel6 ctrl mask bit
+** [17:17] SM_TMR1_TIMER_TRIG6_MASK
+** TIMER1 channel timer trigger channel6 ctrl mask bit
+** [18:18] SM_TMR2_TIMER_TRIG6_MASK
+** TIMER2 channel timer trigger channel6 ctrl mask bit
+** [19:19] SM_TMR3_TIMER_TRIG6_MASK
+** TIMER3 channel timer trigger channel6 ctrl mask bit
+** [20:20] SM_TMR4_TIMER_TRIG6_MASK
+** TIMER4 channel timer trigger channel6 ctrl mask bit
+** [21:21] SM_TMR5_TIMER_TRIG6_MASK
+** TIMER5 channel timer trigger channel6 ctrl mask bit
+** [22:22] SM_TMR6_TIMER_TRIG6_MASK
+** TIMER6 channel timer trigger channel6 ctrl mask bit
+** [23:23] SM_TMR7_TIMER_TRIG6_MASK
+** TIMER7 channel timer trigger channel6 ctrl mask bit
+** [24:24] SM_TMR0_TIMER_TRIG7_MASK
+** TIMER0 channel timer trigger channel7 ctrl mask bit
+** [25:25] SM_TMR1_TIMER_TRIG7_MASK
+** TIMER1 channel timer trigger channel7 ctrl mask bit
+** [26:26] SM_TMR2_TIMER_TRIG7_MASK
+** TIMER2 channel timer trigger channel7 ctrl mask bit
+** [27:27] SM_TMR3_TIMER_TRIG7_MASK
+** TIMER3 channel timer trigger channel7 ctrl mask bit
+** [28:28] SM_TMR4_TIMER_TRIG7_MASK
+** TIMER4 channel timer trigger channel7 ctrl mask bit
+** [29:29] SM_TMR5_TIMER_TRIG7_MASK
+** TIMER5 channel timer trigger channel7 ctrl mask bit
+** [30:30] SM_TMR6_TIMER_TRIG7_MASK
+** TIMER6 channel timer trigger channel7 ctrl mask bit
+** [31:31] SM_TMR7_TIMER_TRIG7_MASK
+** TIMER7 channel timer trigger channel7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0174))
+/*=========================================
+** TIMER channel client active ctrl mask bit:
+** TIMER channel client active ctrl mask bit
+** [0:0] SM_TMR0_CLIENT_ACT0_MASK
+** TIMER0 channel client active channel0 ctrl mask bit
+** [1:1] SM_TMR1_CLIENT_ACT0_MASK
+** TIMER1 channel client active channel0 ctrl mask bit
+** [2:2] SM_TMR2_CLIENT_ACT0_MASK
+** TIMER2 channel client active channel0 ctrl mask bit
+** [3:3] SM_TMR3_CLIENT_ACT0_MASK
+** TIMER3 channel client active channel0 ctrl mask bit
+** [4:4] SM_TMR4_CLIENT_ACT0_MASK
+** TIMER4 channel client active channel0 ctrl mask bit
+** [5:5] SM_TMR5_CLIENT_ACT0_MASK
+** TIMER5 channel client active channel0 ctrl mask bit
+** [6:6] SM_TMR6_CLIENT_ACT0_MASK
+** TIMER6 channel client active channel0 ctrl mask bit
+** [7:7] SM_TMR7_CLIENT_ACT0_MASK
+** TIMER7 channel client active channel0 ctrl mask bit
+** [8:8] SM_TMR0_CLIENT_ACT1_MASK
+** TIMER0 channel client active channel1 ctrl mask bit
+** [9:9] SM_TMR1_CLIENT_ACT1_MASK
+** TIMER1 channel client active channel1 ctrl mask bit
+** [10:10] SM_TMR2_CLIENT_ACT1_MASK
+** TIMER2 channel client active channel1 ctrl mask bit
+** [11:11] SM_TMR3_CLIENT_ACT1_MASK
+** TIMER3 channel client active channel1 ctrl mask bit
+** [12:12] SM_TMR4_CLIENT_ACT1_MASK
+** TIMER4 channel client active channel1 ctrl mask bit
+** [13:13] SM_TMR5_CLIENT_ACT1_MASK
+** TIMER5 channel client active channel1 ctrl mask bit
+** [14:14] SM_TMR6_CLIENT_ACT1_MASK
+** TIMER6 channel client active channel1 ctrl mask bit
+** [15:15] SM_TMR7_CLIENT_ACT1_MASK
+** TIMER7 channel client active channel1 ctrl mask bit
+** [16:16] SM_TMR0_CLIENT_ACT2_MASK
+** TIMER0 channel client active channel2 ctrl mask bit
+** [17:17] SM_TMR1_CLIENT_ACT2_MASK
+** TIMER1 channel client active channel2 ctrl mask bit
+** [18:18] SM_TMR2_CLIENT_ACT2_MASK
+** TIMER2 channel client active channel2 ctrl mask bit
+** [19:19] SM_TMR3_CLIENT_ACT2_MASK
+** TIMER3 channel client active channel2 ctrl mask bit
+** [20:20] SM_TMR4_CLIENT_ACT2_MASK
+** TIMER4 channel client active channel2 ctrl mask bit
+** [21:21] SM_TMR5_CLIENT_ACT2_MASK
+** TIMER5 channel client active channel2 ctrl mask bit
+** [22:22] SM_TMR6_CLIENT_ACT2_MASK
+** TIMER6 channel client active channel2 ctrl mask bit
+** [23:23] SM_TMR7_CLIENT_ACT2_MASK
+** TIMER7 channel client active channel2 ctrl mask bit
+** [24:24] SM_TMR0_CLIENT_ACT3_MASK
+** TIMER0 channel client active channel3 ctrl mask bit
+** [25:25] SM_TMR1_CLIENT_ACT3_MASK
+** TIMER1 channel client active channel3 ctrl mask bit
+** [26:26] SM_TMR2_CLIENT_ACT3_MASK
+** TIMER2 channel client active channel3 ctrl mask bit
+** [27:27] SM_TMR3_CLIENT_ACT3_MASK
+** TIMER3 channel client active channel3 ctrl mask bit
+** [28:28] SM_TMR4_CLIENT_ACT3_MASK
+** TIMER4 channel client active channel3 ctrl mask bit
+** [29:29] SM_TMR5_CLIENT_ACT3_MASK
+** TIMER5 channel client active channel3 ctrl mask bit
+** [30:30] SM_TMR6_CLIENT_ACT3_MASK
+** TIMER6 channel client active channel3 ctrl mask bit
+** [31:31] SM_TMR7_CLIENT_ACT3_MASK
+** TIMER7 channel client active channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0180))
+/*=========================================
+** TIMER channel FSM status:
+** TIMER channel FSM status
+** 0000001: Normal stage
+** 0000010: MTOFF stage
+** 0000100: PAUSE stage
+** 0001000: PRE_PAUSE stage
+** 0010000: SYSCLK_SETTLE stage
+** 0100000: CCP_SETTLE stage
+** 1000000: MTON stage
+** [6:0] SM_TMR0_SSTA
+** TIMER0 channel FSM status
+** [14:8] SM_TMR1_SSTA
+** TIMER1 channel FSM status
+** [22:16] SM_TMR2_SSTA
+** TIMER2 channel FSM status
+** [30:24] SM_TMR3_SSTA
+** TIMER3 channel FSM status
+**=========================================*/
+#define MD_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x01A0))
+/*=========================================
+** TIMER channel FSM status:
+** TIMER channel FSM status
+** 0000001: Normal stage
+** 0000010: MTOFF stage
+** 0000100: PAUSE stage
+** 0001000: PRE_PAUSE stage
+** 0010000: SYSCLK_SETTLE stage
+** 0100000: CCP_SETTLE stage
+** 1000000: MTON stage
+** [6:0] SM_TMR4_SSTA
+** TIMER4 channel FSM status
+** [14:8] SM_TMR5_SSTA
+** TIMER5 channel FSM status
+** [22:16] SM_TMR6_SSTA
+** TIMER6 channel FSM status
+** [30:24] SM_TMR7_SSTA
+** TIMER7 channel FSM status
+**=========================================*/
+#define MD_TOPSM_SM_TMR_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x01A4))
+/*=========================================
+** SLV channel request mask bit:
+** SLV channel request mask bit
+** [0:0] SM_SLV0_REQ_MASK
+** SLV0 channel request mask bit
+** [1:1] SM_SLV1_REQ_MASK
+** SLV1 channel request mask bit
+** [2:2] SM_SLV2_REQ_MASK
+** SLV2 channel request mask bit
+** [3:3] SM_SLV3_REQ_MASK
+** SLV3 channel request mask bit
+** [4:4] SM_SLV4_REQ_MASK
+** SLV4 channel request mask bit
+** [5:5] SM_SLV5_REQ_MASK
+** SLV5 channel request mask bit
+** [6:6] SM_SLV6_REQ_MASK
+** SLV6 channel request mask bit
+** [7:7] SM_SLV7_REQ_MASK
+** SLV7 channel request mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0200))
+/*=========================================
+** SLV channel sysclk ctrl mask bit:
+** SLV channel sysclk ctrl mask bit
+** [0:0] SM_SLV0_SYSCLK_MASK
+** SLV0 channel sysclk ctrl mask bit
+** [1:1] SM_SLV1_SYSCLK_MASK
+** SLV1 channel sysclk ctrl mask bit
+** [2:2] SM_SLV2_SYSCLK_MASK
+** SLV2 channel sysclk ctrl mask bit
+** [3:3] SM_SLV3_SYSCLK_MASK
+** SLV3 channel sysclk ctrl mask bit
+** [4:4] SM_SLV4_SYSCLK_MASK
+** SLV4 channel sysclk ctrl mask bit
+** [5:5] SM_SLV5_SYSCLK_MASK
+** SLV5 channel sysclk ctrl mask bit
+** [6:6] SM_SLV6_SYSCLK_MASK
+** SLV6 channel sysclk ctrl mask bit
+** [7:7] SM_SLV7_SYSCLK_MASK
+** SLV7 channel sysclk ctrl mask bit
+** [8:8] SM_SLV0_SYSCLK1_MASK
+** SLV0 channel sysclk1 ctrl mask bit
+** [9:9] SM_SLV1_SYSCLK1_MASK
+** SLV1 channel sysclk1 ctrl mask bit
+** [10:10] SM_SLV2_SYSCLK1_MASK
+** SLV2 channel sysclk1 ctrl mask bit
+** [11:11] SM_SLV3_SYSCLK1_MASK
+** SLV3 channel sysclk1 ctrl mask bit
+** [12:12] SM_SLV4_SYSCLK1_MASK
+** SLV4 channel sysclk1 ctrl mask bit
+** [13:13] SM_SLV5_SYSCLK1_MASK
+** SLV5 channel sysclk1 ctrl mask bit
+** [14:14] SM_SLV6_SYSCLK1_MASK
+** SLV6 channel sysclk1 ctrl mask bit
+** [15:15] SM_SLV7_SYSCLK1_MASK
+** SLV7 channel sysclk1 ctrl mask bit
+** [16:16] SM_SLV0_SYSCLK2_MASK
+** SLV0 channel sysclk2 ctrl mask bit
+** [17:17] SM_SLV1_SYSCLK2_MASK
+** SLV1 channel sysclk2 ctrl mask bit
+** [18:18] SM_SLV2_SYSCLK2_MASK
+** SLV2 channel sysclk2 ctrl mask bit
+** [19:19] SM_SLV3_SYSCLK2_MASK
+** SLV3 channel sysclk2 ctrl mask bit
+** [20:20] SM_SLV4_SYSCLK2_MASK
+** SLV4 channel sysclk2 ctrl mask bit
+** [21:21] SM_SLV5_SYSCLK2_MASK
+** SLV5 channel sysclk2 ctrl mask bit
+** [22:22] SM_SLV6_SYSCLK2_MASK
+** SLV6 channel sysclk2 ctrl mask bit
+** [23:23] SM_SLV7_SYSCLK2_MASK
+** SLV7 channel sysclk2 ctrl mask bit
+** [24:24] SM_SLV0_SYSCLK3_MASK
+** SLV0 channel sysclk3 ctrl mask bit
+** [25:25] SM_SLV1_SYSCLK3_MASK
+** SLV1 channel sysclk3 ctrl mask bit
+** [26:26] SM_SLV2_SYSCLK3_MASK
+** SLV2 channel sysclk3 ctrl mask bit
+** [27:27] SM_SLV3_SYSCLK3_MASK
+** SLV3 channel sysclk3 ctrl mask bit
+** [28:28] SM_SLV4_SYSCLK3_MASK
+** SLV4 channel sysclk3 ctrl mask bit
+** [29:29] SM_SLV5_SYSCLK3_MASK
+** SLV5 channel sysclk3 ctrl mask bit
+** [30:30] SM_SLV6_SYSCLK3_MASK
+** SLV6 channel sysclk3 ctrl mask bit
+** [31:31] SM_SLV7_SYSCLK3_MASK
+** SLV7 channel sysclk3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0208))
+/*=========================================
+** SLV channel pll ctrl mask bit:
+** SLV channel pll ctrl mask bit
+** [0:0] SM_SLV0_PLL0_MASK
+** SLV0 channel pll0 ctrl mask bit
+** [1:1] SM_SLV1_PLL0_MASK
+** SLV1 channel pll0 ctrl mask bit
+** [2:2] SM_SLV2_PLL0_MASK
+** SLV2 channel pll0 ctrl mask bit
+** [3:3] SM_SLV3_PLL0_MASK
+** SLV3 channel pll0 ctrl mask bit
+** [4:4] SM_SLV4_PLL0_MASK
+** SLV4 channel pll0 ctrl mask bit
+** [5:5] SM_SLV5_PLL0_MASK
+** SLV5 channel pll0 ctrl mask bit
+** [6:6] SM_SLV6_PLL0_MASK
+** SLV6 channel pll0 ctrl mask bit
+** [7:7] SM_SLV7_PLL0_MASK
+** SLV7 channel pll0 ctrl mask bit
+** [8:8] SM_SLV0_PLL1_MASK
+** SLV0 channel pll1 ctrl mask bit
+** [9:9] SM_SLV1_PLL1_MASK
+** SLV1 channel pll1 ctrl mask bit
+** [10:10] SM_SLV2_PLL1_MASK
+** SLV2 channel pll1 ctrl mask bit
+** [11:11] SM_SLV3_PLL1_MASK
+** SLV3 channel pll1 ctrl mask bit
+** [12:12] SM_SLV4_PLL1_MASK
+** SLV4 channel pll1 ctrl mask bit
+** [13:13] SM_SLV5_PLL1_MASK
+** SLV5 channel pll1 ctrl mask bit
+** [14:14] SM_SLV6_PLL1_MASK
+** SLV6 channel pll1 ctrl mask bit
+** [15:15] SM_SLV7_PLL1_MASK
+** SLV7 channel pll1 ctrl mask bit
+** [16:16] SM_SLV0_PLL2_MASK
+** SLV0 channel pll2 ctrl mask bit
+** [17:17] SM_SLV1_PLL2_MASK
+** SLV1 channel pll2 ctrl mask bit
+** [18:18] SM_SLV2_PLL2_MASK
+** SLV2 channel pll2 ctrl mask bit
+** [19:19] SM_SLV3_PLL2_MASK
+** SLV3 channel pll2 ctrl mask bit
+** [20:20] SM_SLV4_PLL2_MASK
+** SLV4 channel pll2 ctrl mask bit
+** [21:21] SM_SLV5_PLL2_MASK
+** SLV5 channel pll2 ctrl mask bit
+** [22:22] SM_SLV6_PLL2_MASK
+** SLV6 channel pll2 ctrl mask bit
+** [23:23] SM_SLV7_PLL2_MASK
+** SLV7 channel pll2 ctrl mask bit
+** [24:24] SM_SLV0_PLL3_MASK
+** SLV0 channel pll3 ctrl mask bit
+** [25:25] SM_SLV1_PLL3_MASK
+** SLV1 channel pll3 ctrl mask bit
+** [26:26] SM_SLV2_PLL3_MASK
+** SLV2 channel pll3 ctrl mask bit
+** [27:27] SM_SLV3_PLL3_MASK
+** SLV3 channel pll3 ctrl mask bit
+** [28:28] SM_SLV4_PLL3_MASK
+** SLV4 channel pll3 ctrl mask bit
+** [29:29] SM_SLV5_PLL3_MASK
+** SLV5 channel pll3 ctrl mask bit
+** [30:30] SM_SLV6_PLL3_MASK
+** SLV6 channel pll3 ctrl mask bit
+** [31:31] SM_SLV7_PLL3_MASK
+** SLV7 channel pll3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0220))
+/*=========================================
+** SLV channel pll ctrl mask bit:
+** SLV channel pll ctrl mask bit
+** [0:0] SM_SLV0_PLL4_MASK
+** SLV0 channel pll4 ctrl mask bit
+** [1:1] SM_SLV1_PLL4_MASK
+** SLV1 channel pll4 ctrl mask bit
+** [2:2] SM_SLV2_PLL4_MASK
+** SLV2 channel pll4 ctrl mask bit
+** [3:3] SM_SLV3_PLL4_MASK
+** SLV3 channel pll4 ctrl mask bit
+** [4:4] SM_SLV4_PLL4_MASK
+** SLV4 channel pll4 ctrl mask bit
+** [5:5] SM_SLV5_PLL4_MASK
+** SLV5 channel pll4 ctrl mask bit
+** [6:6] SM_SLV6_PLL4_MASK
+** SLV6 channel pll4 ctrl mask bit
+** [7:7] SM_SLV7_PLL4_MASK
+** SLV7 channel pll4 ctrl mask bit
+** [8:8] SM_SLV0_PLL5_MASK
+** SLV0 channel pll5 ctrl mask bit
+** [9:9] SM_SLV1_PLL5_MASK
+** SLV1 channel pll5 ctrl mask bit
+** [10:10] SM_SLV2_PLL5_MASK
+** SLV2 channel pll5 ctrl mask bit
+** [11:11] SM_SLV3_PLL5_MASK
+** SLV3 channel pll5 ctrl mask bit
+** [12:12] SM_SLV4_PLL5_MASK
+** SLV4 channel pll5 ctrl mask bit
+** [13:13] SM_SLV5_PLL5_MASK
+** SLV5 channel pll5 ctrl mask bit
+** [14:14] SM_SLV6_PLL5_MASK
+** SLV6 channel pll5 ctrl mask bit
+** [15:15] SM_SLV7_PLL5_MASK
+** SLV7 channel pll5 ctrl mask bit
+** [16:16] SM_SLV0_PLL6_MASK
+** SLV0 channel pll6 ctrl mask bit
+** [17:17] SM_SLV1_PLL6_MASK
+** SLV1 channel pll6 ctrl mask bit
+** [18:18] SM_SLV2_PLL6_MASK
+** SLV2 channel pll6 ctrl mask bit
+** [19:19] SM_SLV3_PLL6_MASK
+** SLV3 channel pll6 ctrl mask bit
+** [20:20] SM_SLV4_PLL6_MASK
+** SLV4 channel pll6 ctrl mask bit
+** [21:21] SM_SLV5_PLL6_MASK
+** SLV5 channel pll6 ctrl mask bit
+** [22:22] SM_SLV6_PLL6_MASK
+** SLV6 channel pll6 ctrl mask bit
+** [23:23] SM_SLV7_PLL6_MASK
+** SLV7 channel pll6 ctrl mask bit
+** [24:24] SM_SLV0_PLL7_MASK
+** SLV0 channel pll7 ctrl mask bit
+** [25:25] SM_SLV1_PLL7_MASK
+** SLV1 channel pll7 ctrl mask bit
+** [26:26] SM_SLV2_PLL7_MASK
+** SLV2 channel pll7 ctrl mask bit
+** [27:27] SM_SLV3_PLL7_MASK
+** SLV3 channel pll7 ctrl mask bit
+** [28:28] SM_SLV4_PLL7_MASK
+** SLV4 channel pll7 ctrl mask bit
+** [29:29] SM_SLV5_PLL7_MASK
+** SLV5 channel pll7 ctrl mask bit
+** [30:30] SM_SLV6_PLL7_MASK
+** SLV6 channel pll7 ctrl mask bit
+** [31:31] SM_SLV7_PLL7_MASK
+** SLV7 channel pll7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0224))
+/*=========================================
+** SLV channel pll ctrl mask bit:
+** SLV channel pll ctrl mask bit
+** [0:0] SM_SLV0_PLL8_MASK
+** SLV0 channel pll8 ctrl mask bit
+** [1:1] SM_SLV1_PLL8_MASK
+** SLV1 channel pll8 ctrl mask bit
+** [2:2] SM_SLV2_PLL8_MASK
+** SLV2 channel pll8 ctrl mask bit
+** [3:3] SM_SLV3_PLL8_MASK
+** SLV3 channel pll8 ctrl mask bit
+** [4:4] SM_SLV4_PLL8_MASK
+** SLV4 channel pll8 ctrl mask bit
+** [5:5] SM_SLV5_PLL8_MASK
+** SLV5 channel pll8 ctrl mask bit
+** [6:6] SM_SLV6_PLL8_MASK
+** SLV6 channel pll8 ctrl mask bit
+** [7:7] SM_SLV7_PLL8_MASK
+** SLV7 channel pll8 ctrl mask bit
+** [8:8] SM_SLV0_PLL9_MASK
+** SLV0 channel pll9 ctrl mask bit
+** [9:9] SM_SLV1_PLL9_MASK
+** SLV1 channel pll9 ctrl mask bit
+** [10:10] SM_SLV2_PLL9_MASK
+** SLV2 channel pll9 ctrl mask bit
+** [11:11] SM_SLV3_PLL9_MASK
+** SLV3 channel pll9 ctrl mask bit
+** [12:12] SM_SLV4_PLL9_MASK
+** SLV4 channel pll9 ctrl mask bit
+** [13:13] SM_SLV5_PLL9_MASK
+** SLV5 channel pll9 ctrl mask bit
+** [14:14] SM_SLV6_PLL9_MASK
+** SLV6 channel pll9 ctrl mask bit
+** [15:15] SM_SLV7_PLL9_MASK
+** SLV7 channel pll9 ctrl mask bit
+** [16:16] SM_SLV0_PLL10_MASK
+** SLV0 channel pll10 ctrl mask bit
+** [17:17] SM_SLV1_PLL10_MASK
+** SLV1 channel pll10 ctrl mask bit
+** [18:18] SM_SLV2_PLL10_MASK
+** SLV2 channel pll10 ctrl mask bit
+** [19:19] SM_SLV3_PLL10_MASK
+** SLV3 channel pll10 ctrl mask bit
+** [20:20] SM_SLV4_PLL10_MASK
+** SLV4 channel pll10 ctrl mask bit
+** [21:21] SM_SLV5_PLL10_MASK
+** SLV5 channel pll10 ctrl mask bit
+** [22:22] SM_SLV6_PLL10_MASK
+** SLV6 channel pll10 ctrl mask bit
+** [23:23] SM_SLV7_PLL10_MASK
+** SLV7 channel pll10 ctrl mask bit
+** [24:24] SM_SLV0_PLL11_MASK
+** SLV0 channel pll11 ctrl mask bit
+** [25:25] SM_SLV1_PLL11_MASK
+** SLV1 channel pll11 ctrl mask bit
+** [26:26] SM_SLV2_PLL11_MASK
+** SLV2 channel pll11 ctrl mask bit
+** [27:27] SM_SLV3_PLL11_MASK
+** SLV3 channel pll11 ctrl mask bit
+** [28:28] SM_SLV4_PLL11_MASK
+** SLV4 channel pll11 ctrl mask bit
+** [29:29] SM_SLV5_PLL11_MASK
+** SLV5 channel pll11 ctrl mask bit
+** [30:30] SM_SLV6_PLL11_MASK
+** SLV6 channel pll11 ctrl mask bit
+** [31:31] SM_SLV7_PLL11_MASK
+** SLV7 channel pll11 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PLL_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0228))
+/*=========================================
+** SLV channel pll ctrl mask bit:
+** SLV channel pll ctrl mask bit
+** [0:0] SM_SLV0_PLL12_MASK
+** SLV0 channel pll12 ctrl mask bit
+** [1:1] SM_SLV1_PLL12_MASK
+** SLV1 channel pll12 ctrl mask bit
+** [2:2] SM_SLV2_PLL12_MASK
+** SLV2 channel pll12 ctrl mask bit
+** [3:3] SM_SLV3_PLL12_MASK
+** SLV3 channel pll12 ctrl mask bit
+** [4:4] SM_SLV4_PLL12_MASK
+** SLV4 channel pll12 ctrl mask bit
+** [5:5] SM_SLV5_PLL12_MASK
+** SLV5 channel pll12 ctrl mask bit
+** [6:6] SM_SLV6_PLL12_MASK
+** SLV6 channel pll12 ctrl mask bit
+** [7:7] SM_SLV7_PLL12_MASK
+** SLV7 channel pll12 ctrl mask bit
+** [8:8] SM_SLV0_PLL13_MASK
+** SLV0 channel pll13 ctrl mask bit
+** [9:9] SM_SLV1_PLL13_MASK
+** SLV1 channel pll13 ctrl mask bit
+** [10:10] SM_SLV2_PLL13_MASK
+** SLV2 channel pll13 ctrl mask bit
+** [11:11] SM_SLV3_PLL13_MASK
+** SLV3 channel pll13 ctrl mask bit
+** [12:12] SM_SLV4_PLL13_MASK
+** SLV4 channel pll13 ctrl mask bit
+** [13:13] SM_SLV5_PLL13_MASK
+** SLV5 channel pll13 ctrl mask bit
+** [14:14] SM_SLV6_PLL13_MASK
+** SLV6 channel pll13 ctrl mask bit
+** [15:15] SM_SLV7_PLL13_MASK
+** SLV7 channel pll13 ctrl mask bit
+** [16:16] SM_SLV0_PLL14_MASK
+** SLV0 channel pll14 ctrl mask bit
+** [17:17] SM_SLV1_PLL14_MASK
+** SLV1 channel pll14 ctrl mask bit
+** [18:18] SM_SLV2_PLL14_MASK
+** SLV2 channel pll14 ctrl mask bit
+** [19:19] SM_SLV3_PLL14_MASK
+** SLV3 channel pll14 ctrl mask bit
+** [20:20] SM_SLV4_PLL14_MASK
+** SLV4 channel pll14 ctrl mask bit
+** [21:21] SM_SLV5_PLL14_MASK
+** SLV5 channel pll14 ctrl mask bit
+** [22:22] SM_SLV6_PLL14_MASK
+** SLV6 channel pll14 ctrl mask bit
+** [23:23] SM_SLV7_PLL14_MASK
+** SLV7 channel pll14 ctrl mask bit
+** [24:24] SM_SLV0_PLL15_MASK
+** SLV0 channel pll15 ctrl mask bit
+** [25:25] SM_SLV1_PLL15_MASK
+** SLV1 channel pll15 ctrl mask bit
+** [26:26] SM_SLV2_PLL15_MASK
+** SLV2 channel pll15 ctrl mask bit
+** [27:27] SM_SLV3_PLL15_MASK
+** SLV3 channel pll15 ctrl mask bit
+** [28:28] SM_SLV4_PLL15_MASK
+** SLV4 channel pll15 ctrl mask bit
+** [29:29] SM_SLV5_PLL15_MASK
+** SLV5 channel pll15 ctrl mask bit
+** [30:30] SM_SLV6_PLL15_MASK
+** SLV6 channel pll15 ctrl mask bit
+** [31:31] SM_SLV7_PLL15_MASK
+** SLV7 channel pll15 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PLL_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x022C))
+/*=========================================
+** SLV channel pwr ctrl mask bit:
+** SLV channel pwr ctrl mask bit
+** [0:0] SM_SLV0_PWR0_MASK
+** SLV0 channel pwr0 ctrl mask bit
+** [1:1] SM_SLV1_PWR0_MASK
+** SLV1 channel pwr0 ctrl mask bit
+** [2:2] SM_SLV2_PWR0_MASK
+** SLV2 channel pwr0 ctrl mask bit
+** [3:3] SM_SLV3_PWR0_MASK
+** SLV3 channel pwr0 ctrl mask bit
+** [4:4] SM_SLV4_PWR0_MASK
+** SLV4 channel pwr0 ctrl mask bit
+** [5:5] SM_SLV5_PWR0_MASK
+** SLV5 channel pwr0 ctrl mask bit
+** [6:6] SM_SLV6_PWR0_MASK
+** SLV6 channel pwr0 ctrl mask bit
+** [7:7] SM_SLV7_PWR0_MASK
+** SLV7 channel pwr0 ctrl mask bit
+** [8:8] SM_SLV0_PWR1_MASK
+** SLV0 channel pwr1 ctrl mask bit
+** [9:9] SM_SLV1_PWR1_MASK
+** SLV1 channel pwr1 ctrl mask bit
+** [10:10] SM_SLV2_PWR1_MASK
+** SLV2 channel pwr1 ctrl mask bit
+** [11:11] SM_SLV3_PWR1_MASK
+** SLV3 channel pwr1 ctrl mask bit
+** [12:12] SM_SLV4_PWR1_MASK
+** SLV4 channel pwr1 ctrl mask bit
+** [13:13] SM_SLV5_PWR1_MASK
+** SLV5 channel pwr1 ctrl mask bit
+** [14:14] SM_SLV6_PWR1_MASK
+** SLV6 channel pwr1 ctrl mask bit
+** [15:15] SM_SLV7_PWR1_MASK
+** SLV7 channel pwr1 ctrl mask bit
+** [16:16] SM_SLV0_PWR2_MASK
+** SLV0 channel pwr2 ctrl mask bit
+** [17:17] SM_SLV1_PWR2_MASK
+** SLV1 channel pwr2 ctrl mask bit
+** [18:18] SM_SLV2_PWR2_MASK
+** SLV2 channel pwr2 ctrl mask bit
+** [19:19] SM_SLV3_PWR2_MASK
+** SLV3 channel pwr2 ctrl mask bit
+** [20:20] SM_SLV4_PWR2_MASK
+** SLV4 channel pwr2 ctrl mask bit
+** [21:21] SM_SLV5_PWR2_MASK
+** SLV5 channel pwr2 ctrl mask bit
+** [22:22] SM_SLV6_PWR2_MASK
+** SLV6 channel pwr2 ctrl mask bit
+** [23:23] SM_SLV7_PWR2_MASK
+** SLV7 channel pwr2 ctrl mask bit
+** [24:24] SM_SLV0_PWR3_MASK
+** SLV0 channel pwr3 ctrl mask bit
+** [25:25] SM_SLV1_PWR3_MASK
+** SLV1 channel pwr3 ctrl mask bit
+** [26:26] SM_SLV2_PWR3_MASK
+** SLV2 channel pwr3 ctrl mask bit
+** [27:27] SM_SLV3_PWR3_MASK
+** SLV3 channel pwr3 ctrl mask bit
+** [28:28] SM_SLV4_PWR3_MASK
+** SLV4 channel pwr3 ctrl mask bit
+** [29:29] SM_SLV5_PWR3_MASK
+** SLV5 channel pwr3 ctrl mask bit
+** [30:30] SM_SLV6_PWR3_MASK
+** SLV6 channel pwr3 ctrl mask bit
+** [31:31] SM_SLV7_PWR3_MASK
+** SLV7 channel pwr3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0240))
+/*=========================================
+** SLV channel pwr ctrl mask bit:
+** SLV channel pwr ctrl mask bit
+** [0:0] SM_SLV0_PWR4_MASK
+** SLV0 channel pwr4 ctrl mask bit
+** [1:1] SM_SLV1_PWR4_MASK
+** SLV1 channel pwr4 ctrl mask bit
+** [2:2] SM_SLV2_PWR4_MASK
+** SLV2 channel pwr4 ctrl mask bit
+** [3:3] SM_SLV3_PWR4_MASK
+** SLV3 channel pwr4 ctrl mask bit
+** [4:4] SM_SLV4_PWR4_MASK
+** SLV4 channel pwr4 ctrl mask bit
+** [5:5] SM_SLV5_PWR4_MASK
+** SLV5 channel pwr4 ctrl mask bit
+** [6:6] SM_SLV6_PWR4_MASK
+** SLV6 channel pwr4 ctrl mask bit
+** [7:7] SM_SLV7_PWR4_MASK
+** SLV7 channel pwr4 ctrl mask bit
+** [8:8] SM_SLV0_PWR5_MASK
+** SLV0 channel pwr5 ctrl mask bit
+** [9:9] SM_SLV1_PWR5_MASK
+** SLV1 channel pwr5 ctrl mask bit
+** [10:10] SM_SLV2_PWR5_MASK
+** SLV2 channel pwr5 ctrl mask bit
+** [11:11] SM_SLV3_PWR5_MASK
+** SLV3 channel pwr5 ctrl mask bit
+** [12:12] SM_SLV4_PWR5_MASK
+** SLV4 channel pwr5 ctrl mask bit
+** [13:13] SM_SLV5_PWR5_MASK
+** SLV5 channel pwr5 ctrl mask bit
+** [14:14] SM_SLV6_PWR5_MASK
+** SLV6 channel pwr5 ctrl mask bit
+** [15:15] SM_SLV7_PWR5_MASK
+** SLV7 channel pwr5 ctrl mask bit
+** [16:16] SM_SLV0_PWR6_MASK
+** SLV0 channel pwr6 ctrl mask bit
+** [17:17] SM_SLV1_PWR6_MASK
+** SLV1 channel pwr6 ctrl mask bit
+** [18:18] SM_SLV2_PWR6_MASK
+** SLV2 channel pwr6 ctrl mask bit
+** [19:19] SM_SLV3_PWR6_MASK
+** SLV3 channel pwr6 ctrl mask bit
+** [20:20] SM_SLV4_PWR6_MASK
+** SLV4 channel pwr6 ctrl mask bit
+** [21:21] SM_SLV5_PWR6_MASK
+** SLV5 channel pwr6 ctrl mask bit
+** [22:22] SM_SLV6_PWR6_MASK
+** SLV6 channel pwr6 ctrl mask bit
+** [23:23] SM_SLV7_PWR6_MASK
+** SLV7 channel pwr6 ctrl mask bit
+** [24:24] SM_SLV0_PWR7_MASK
+** SLV0 channel pwr7 ctrl mask bit
+** [25:25] SM_SLV1_PWR7_MASK
+** SLV1 channel pwr7 ctrl mask bit
+** [26:26] SM_SLV2_PWR7_MASK
+** SLV2 channel pwr7 ctrl mask bit
+** [27:27] SM_SLV3_PWR7_MASK
+** SLV3 channel pwr7 ctrl mask bit
+** [28:28] SM_SLV4_PWR7_MASK
+** SLV4 channel pwr7 ctrl mask bit
+** [29:29] SM_SLV5_PWR7_MASK
+** SLV5 channel pwr7 ctrl mask bit
+** [30:30] SM_SLV6_PWR7_MASK
+** SLV6 channel pwr7 ctrl mask bit
+** [31:31] SM_SLV7_PWR7_MASK
+** SLV7 channel pwr7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0244))
+/*=========================================
+** SLV channel pwr ctrl mask bit:
+** SLV channel pwr ctrl mask bit
+** [0:0] SM_SLV0_PWR8_MASK
+** SLV0 channel pwr8 ctrl mask bit
+** [1:1] SM_SLV1_PWR8_MASK
+** SLV1 channel pwr8 ctrl mask bit
+** [2:2] SM_SLV2_PWR8_MASK
+** SLV2 channel pwr8 ctrl mask bit
+** [3:3] SM_SLV3_PWR8_MASK
+** SLV3 channel pwr8 ctrl mask bit
+** [4:4] SM_SLV4_PWR8_MASK
+** SLV4 channel pwr8 ctrl mask bit
+** [5:5] SM_SLV5_PWR8_MASK
+** SLV5 channel pwr8 ctrl mask bit
+** [6:6] SM_SLV6_PWR8_MASK
+** SLV6 channel pwr8 ctrl mask bit
+** [7:7] SM_SLV7_PWR8_MASK
+** SLV7 channel pwr8 ctrl mask bit
+** [8:8] SM_SLV0_PWR9_MASK
+** SLV0 channel pwr9 ctrl mask bit
+** [9:9] SM_SLV1_PWR9_MASK
+** SLV1 channel pwr9 ctrl mask bit
+** [10:10] SM_SLV2_PWR9_MASK
+** SLV2 channel pwr9 ctrl mask bit
+** [11:11] SM_SLV3_PWR9_MASK
+** SLV3 channel pwr9 ctrl mask bit
+** [12:12] SM_SLV4_PWR9_MASK
+** SLV4 channel pwr9 ctrl mask bit
+** [13:13] SM_SLV5_PWR9_MASK
+** SLV5 channel pwr9 ctrl mask bit
+** [14:14] SM_SLV6_PWR9_MASK
+** SLV6 channel pwr9 ctrl mask bit
+** [15:15] SM_SLV7_PWR9_MASK
+** SLV7 channel pwr9 ctrl mask bit
+** [16:16] SM_SLV0_PWR10_MASK
+** SLV0 channel pwr10 ctrl mask bit
+** [17:17] SM_SLV1_PWR10_MASK
+** SLV1 channel pwr10 ctrl mask bit
+** [18:18] SM_SLV2_PWR10_MASK
+** SLV2 channel pwr10 ctrl mask bit
+** [19:19] SM_SLV3_PWR10_MASK
+** SLV3 channel pwr10 ctrl mask bit
+** [20:20] SM_SLV4_PWR10_MASK
+** SLV4 channel pwr10 ctrl mask bit
+** [21:21] SM_SLV5_PWR10_MASK
+** SLV5 channel pwr10 ctrl mask bit
+** [22:22] SM_SLV6_PWR10_MASK
+** SLV6 channel pwr10 ctrl mask bit
+** [23:23] SM_SLV7_PWR10_MASK
+** SLV7 channel pwr10 ctrl mask bit
+** [24:24] SM_SLV0_PWR11_MASK
+** SLV0 channel pwr11 ctrl mask bit
+** [25:25] SM_SLV1_PWR11_MASK
+** SLV1 channel pwr11 ctrl mask bit
+** [26:26] SM_SLV2_PWR11_MASK
+** SLV2 channel pwr11 ctrl mask bit
+** [27:27] SM_SLV3_PWR11_MASK
+** SLV3 channel pwr11 ctrl mask bit
+** [28:28] SM_SLV4_PWR11_MASK
+** SLV4 channel pwr11 ctrl mask bit
+** [29:29] SM_SLV5_PWR11_MASK
+** SLV5 channel pwr11 ctrl mask bit
+** [30:30] SM_SLV6_PWR11_MASK
+** SLV6 channel pwr11 ctrl mask bit
+** [31:31] SM_SLV7_PWR11_MASK
+** SLV7 channel pwr11 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PWR_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0248))
+/*=========================================
+** SLV channel pwr ctrl mask bit:
+** SLV channel pwr ctrl mask bit
+** [0:0] SM_SLV0_PWR12_MASK
+** SLV0 channel pwr12 ctrl mask bit
+** [1:1] SM_SLV1_PWR12_MASK
+** SLV1 channel pwr12 ctrl mask bit
+** [2:2] SM_SLV2_PWR12_MASK
+** SLV2 channel pwr12 ctrl mask bit
+** [3:3] SM_SLV3_PWR12_MASK
+** SLV3 channel pwr12 ctrl mask bit
+** [4:4] SM_SLV4_PWR12_MASK
+** SLV4 channel pwr12 ctrl mask bit
+** [5:5] SM_SLV5_PWR12_MASK
+** SLV5 channel pwr12 ctrl mask bit
+** [6:6] SM_SLV6_PWR12_MASK
+** SLV6 channel pwr12 ctrl mask bit
+** [7:7] SM_SLV7_PWR12_MASK
+** SLV7 channel pwr12 ctrl mask bit
+** [8:8] SM_SLV0_PWR13_MASK
+** SLV0 channel pwr13 ctrl mask bit
+** [9:9] SM_SLV1_PWR13_MASK
+** SLV1 channel pwr13 ctrl mask bit
+** [10:10] SM_SLV2_PWR13_MASK
+** SLV2 channel pwr13 ctrl mask bit
+** [11:11] SM_SLV3_PWR13_MASK
+** SLV3 channel pwr13 ctrl mask bit
+** [12:12] SM_SLV4_PWR13_MASK
+** SLV4 channel pwr13 ctrl mask bit
+** [13:13] SM_SLV5_PWR13_MASK
+** SLV5 channel pwr13 ctrl mask bit
+** [14:14] SM_SLV6_PWR13_MASK
+** SLV6 channel pwr13 ctrl mask bit
+** [15:15] SM_SLV7_PWR13_MASK
+** SLV7 channel pwr13 ctrl mask bit
+** [16:16] SM_SLV0_PWR14_MASK
+** SLV0 channel pwr14 ctrl mask bit
+** [17:17] SM_SLV1_PWR14_MASK
+** SLV1 channel pwr14 ctrl mask bit
+** [18:18] SM_SLV2_PWR14_MASK
+** SLV2 channel pwr14 ctrl mask bit
+** [19:19] SM_SLV3_PWR14_MASK
+** SLV3 channel pwr14 ctrl mask bit
+** [20:20] SM_SLV4_PWR14_MASK
+** SLV4 channel pwr14 ctrl mask bit
+** [21:21] SM_SLV5_PWR14_MASK
+** SLV5 channel pwr14 ctrl mask bit
+** [22:22] SM_SLV6_PWR14_MASK
+** SLV6 channel pwr14 ctrl mask bit
+** [23:23] SM_SLV7_PWR14_MASK
+** SLV7 channel pwr14 ctrl mask bit
+** [24:24] SM_SLV0_PWR15_MASK
+** SLV0 channel pwr15 ctrl mask bit
+** [25:25] SM_SLV1_PWR15_MASK
+** SLV1 channel pwr15 ctrl mask bit
+** [26:26] SM_SLV2_PWR15_MASK
+** SLV2 channel pwr15 ctrl mask bit
+** [27:27] SM_SLV3_PWR15_MASK
+** SLV3 channel pwr15 ctrl mask bit
+** [28:28] SM_SLV4_PWR15_MASK
+** SLV4 channel pwr15 ctrl mask bit
+** [29:29] SM_SLV5_PWR15_MASK
+** SLV5 channel pwr15 ctrl mask bit
+** [30:30] SM_SLV6_PWR15_MASK
+** SLV6 channel pwr15 ctrl mask bit
+** [31:31] SM_SLV7_PWR15_MASK
+** SLV7 channel pwr15 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PWR_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x024C))
+/*=========================================
+** SLV channel pwr ctrl mask bit:
+** SLV channel pwr ctrl mask bit
+** [0:0] SM_SLV0_PWR16_MASK
+** SLV0 channel pwr16 ctrl mask bit
+** [1:1] SM_SLV1_PWR16_MASK
+** SLV1 channel pwr16 ctrl mask bit
+** [2:2] SM_SLV2_PWR16_MASK
+** SLV2 channel pwr16 ctrl mask bit
+** [3:3] SM_SLV3_PWR16_MASK
+** SLV3 channel pwr16 ctrl mask bit
+** [4:4] SM_SLV4_PWR16_MASK
+** SLV4 channel pwr16 ctrl mask bit
+** [5:5] SM_SLV5_PWR16_MASK
+** SLV5 channel pwr16 ctrl mask bit
+** [6:6] SM_SLV6_PWR16_MASK
+** SLV6 channel pwr16 ctrl mask bit
+** [7:7] SM_SLV7_PWR16_MASK
+** SLV7 channel pwr16 ctrl mask bit
+** [8:8] SM_SLV0_PWR17_MASK
+** SLV0 channel pwr17 ctrl mask bit
+** [9:9] SM_SLV1_PWR17_MASK
+** SLV1 channel pwr17 ctrl mask bit
+** [10:10] SM_SLV2_PWR17_MASK
+** SLV2 channel pwr17 ctrl mask bit
+** [11:11] SM_SLV3_PWR17_MASK
+** SLV3 channel pwr17 ctrl mask bit
+** [12:12] SM_SLV4_PWR17_MASK
+** SLV4 channel pwr17 ctrl mask bit
+** [13:13] SM_SLV5_PWR17_MASK
+** SLV5 channel pwr17 ctrl mask bit
+** [14:14] SM_SLV6_PWR17_MASK
+** SLV6 channel pwr17 ctrl mask bit
+** [15:15] SM_SLV7_PWR17_MASK
+** SLV7 channel pwr17 ctrl mask bit
+** [16:16] SM_SLV0_PWR18_MASK
+** SLV0 channel pwr18 ctrl mask bit
+** [17:17] SM_SLV1_PWR18_MASK
+** SLV1 channel pwr18 ctrl mask bit
+** [18:18] SM_SLV2_PWR18_MASK
+** SLV2 channel pwr18 ctrl mask bit
+** [19:19] SM_SLV3_PWR18_MASK
+** SLV3 channel pwr18 ctrl mask bit
+** [20:20] SM_SLV4_PWR18_MASK
+** SLV4 channel pwr18 ctrl mask bit
+** [21:21] SM_SLV5_PWR18_MASK
+** SLV5 channel pwr18 ctrl mask bit
+** [22:22] SM_SLV6_PWR18_MASK
+** SLV6 channel pwr18 ctrl mask bit
+** [23:23] SM_SLV7_PWR18_MASK
+** SLV7 channel pwr18 ctrl mask bit
+** [24:24] SM_SLV0_PWR19_MASK
+** SLV0 channel pwr19 ctrl mask bit
+** [25:25] SM_SLV1_PWR19_MASK
+** SLV1 channel pwr19 ctrl mask bit
+** [26:26] SM_SLV2_PWR19_MASK
+** SLV2 channel pwr19 ctrl mask bit
+** [27:27] SM_SLV3_PWR19_MASK
+** SLV3 channel pwr19 ctrl mask bit
+** [28:28] SM_SLV4_PWR19_MASK
+** SLV4 channel pwr19 ctrl mask bit
+** [29:29] SM_SLV5_PWR19_MASK
+** SLV5 channel pwr19 ctrl mask bit
+** [30:30] SM_SLV6_PWR19_MASK
+** SLV6 channel pwr19 ctrl mask bit
+** [31:31] SM_SLV7_PWR19_MASK
+** SLV7 channel pwr19 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PWR_MASK4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0250))
+/*=========================================
+** SLV channel pwr ctrl mask bit:
+** SLV channel pwr ctrl mask bit
+** [0:0] SM_SLV0_PWR20_MASK
+** SLV0 channel pwr20 ctrl mask bit
+** [1:1] SM_SLV1_PWR20_MASK
+** SLV1 channel pwr20 ctrl mask bit
+** [2:2] SM_SLV2_PWR20_MASK
+** SLV2 channel pwr20 ctrl mask bit
+** [3:3] SM_SLV3_PWR20_MASK
+** SLV3 channel pwr20 ctrl mask bit
+** [4:4] SM_SLV4_PWR20_MASK
+** SLV4 channel pwr20 ctrl mask bit
+** [5:5] SM_SLV5_PWR20_MASK
+** SLV5 channel pwr20 ctrl mask bit
+** [6:6] SM_SLV6_PWR20_MASK
+** SLV6 channel pwr20 ctrl mask bit
+** [7:7] SM_SLV7_PWR20_MASK
+** SLV7 channel pwr20 ctrl mask bit
+** [8:8] SM_SLV0_PWR21_MASK
+** SLV0 channel pwr21 ctrl mask bit
+** [9:9] SM_SLV1_PWR21_MASK
+** SLV1 channel pwr21 ctrl mask bit
+** [10:10] SM_SLV2_PWR21_MASK
+** SLV2 channel pwr21 ctrl mask bit
+** [11:11] SM_SLV3_PWR21_MASK
+** SLV3 channel pwr21 ctrl mask bit
+** [12:12] SM_SLV4_PWR21_MASK
+** SLV4 channel pwr21 ctrl mask bit
+** [13:13] SM_SLV5_PWR21_MASK
+** SLV5 channel pwr21 ctrl mask bit
+** [14:14] SM_SLV6_PWR21_MASK
+** SLV6 channel pwr21 ctrl mask bit
+** [15:15] SM_SLV7_PWR21_MASK
+** SLV7 channel pwr21 ctrl mask bit
+** [16:16] SM_SLV0_PWR22_MASK
+** SLV0 channel pwr22 ctrl mask bit
+** [17:17] SM_SLV1_PWR22_MASK
+** SLV1 channel pwr22 ctrl mask bit
+** [18:18] SM_SLV2_PWR22_MASK
+** SLV2 channel pwr22 ctrl mask bit
+** [19:19] SM_SLV3_PWR22_MASK
+** SLV3 channel pwr22 ctrl mask bit
+** [20:20] SM_SLV4_PWR22_MASK
+** SLV4 channel pwr22 ctrl mask bit
+** [21:21] SM_SLV5_PWR22_MASK
+** SLV5 channel pwr22 ctrl mask bit
+** [22:22] SM_SLV6_PWR22_MASK
+** SLV6 channel pwr22 ctrl mask bit
+** [23:23] SM_SLV7_PWR22_MASK
+** SLV7 channel pwr22 ctrl mask bit
+** [24:24] SM_SLV0_PWR23_MASK
+** SLV0 channel pwr23 ctrl mask bit
+** [25:25] SM_SLV1_PWR23_MASK
+** SLV1 channel pwr23 ctrl mask bit
+** [26:26] SM_SLV2_PWR23_MASK
+** SLV2 channel pwr23 ctrl mask bit
+** [27:27] SM_SLV3_PWR23_MASK
+** SLV3 channel pwr23 ctrl mask bit
+** [28:28] SM_SLV4_PWR23_MASK
+** SLV4 channel pwr23 ctrl mask bit
+** [29:29] SM_SLV5_PWR23_MASK
+** SLV5 channel pwr23 ctrl mask bit
+** [30:30] SM_SLV6_PWR23_MASK
+** SLV6 channel pwr23 ctrl mask bit
+** [31:31] SM_SLV7_PWR23_MASK
+** SLV7 channel pwr23 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PWR_MASK5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0254))
+/*=========================================
+** SLV channel mas trigger ctrl mask bit:
+** SLV channel mas trigger ctrl mask bit
+** [0:0] SM_SLV0_MAS_TRIG0_MASK
+** SLV0 channel mas trigger channel0 ctrl mask bit
+** [1:1] SM_SLV1_MAS_TRIG0_MASK
+** SLV1 channel mas trigger channel0 ctrl mask bit
+** [2:2] SM_SLV2_MAS_TRIG0_MASK
+** SLV2 channel mas trigger channel0 ctrl mask bit
+** [3:3] SM_SLV3_MAS_TRIG0_MASK
+** SLV3 channel mas trigger channel0 ctrl mask bit
+** [4:4] SM_SLV4_MAS_TRIG0_MASK
+** SLV4 channel mas trigger channel0 ctrl mask bit
+** [5:5] SM_SLV5_MAS_TRIG0_MASK
+** SLV5 channel mas trigger channel0 ctrl mask bit
+** [6:6] SM_SLV6_MAS_TRIG0_MASK
+** SLV6 channel mas trigger channel0 ctrl mask bit
+** [7:7] SM_SLV7_MAS_TRIG0_MASK
+** SLV7 channel mas trigger channel0 ctrl mask bit
+** [8:8] SM_SLV0_MAS_TRIG1_MASK
+** SLV0 channel mas trigger channel1 ctrl mask bit
+** [9:9] SM_SLV1_MAS_TRIG1_MASK
+** SLV1 channel mas trigger channel1 ctrl mask bit
+** [10:10] SM_SLV2_MAS_TRIG1_MASK
+** SLV2 channel mas trigger channel1 ctrl mask bit
+** [11:11] SM_SLV3_MAS_TRIG1_MASK
+** SLV3 channel mas trigger channel1 ctrl mask bit
+** [12:12] SM_SLV4_MAS_TRIG1_MASK
+** SLV4 channel mas trigger channel1 ctrl mask bit
+** [13:13] SM_SLV5_MAS_TRIG1_MASK
+** SLV5 channel mas trigger channel1 ctrl mask bit
+** [14:14] SM_SLV6_MAS_TRIG1_MASK
+** SLV6 channel mas trigger channel1 ctrl mask bit
+** [15:15] SM_SLV7_MAS_TRIG1_MASK
+** SLV7 channel mas trigger channel1 ctrl mask bit
+** [16:16] SM_SLV0_MAS_TRIG2_MASK
+** SLV0 channel mas trigger channel2 ctrl mask bit
+** [17:17] SM_SLV1_MAS_TRIG2_MASK
+** SLV1 channel mas trigger channel2 ctrl mask bit
+** [18:18] SM_SLV2_MAS_TRIG2_MASK
+** SLV2 channel mas trigger channel2 ctrl mask bit
+** [19:19] SM_SLV3_MAS_TRIG2_MASK
+** SLV3 channel mas trigger channel2 ctrl mask bit
+** [20:20] SM_SLV4_MAS_TRIG2_MASK
+** SLV4 channel mas trigger channel2 ctrl mask bit
+** [21:21] SM_SLV5_MAS_TRIG2_MASK
+** SLV5 channel mas trigger channel2 ctrl mask bit
+** [22:22] SM_SLV6_MAS_TRIG2_MASK
+** SLV6 channel mas trigger channel2 ctrl mask bit
+** [23:23] SM_SLV7_MAS_TRIG2_MASK
+** SLV7 channel mas trigger channel2 ctrl mask bit
+** [24:24] SM_SLV0_MAS_TRIG3_MASK
+** SLV0 channel mas trigger channel3 ctrl mask bit
+** [25:25] SM_SLV1_MAS_TRIG3_MASK
+** SLV1 channel mas trigger channel3 ctrl mask bit
+** [26:26] SM_SLV2_MAS_TRIG3_MASK
+** SLV2 channel mas trigger channel3 ctrl mask bit
+** [27:27] SM_SLV3_MAS_TRIG3_MASK
+** SLV3 channel mas trigger channel3 ctrl mask bit
+** [28:28] SM_SLV4_MAS_TRIG3_MASK
+** SLV4 channel mas trigger channel3 ctrl mask bit
+** [29:29] SM_SLV5_MAS_TRIG3_MASK
+** SLV5 channel mas trigger channel3 ctrl mask bit
+** [30:30] SM_SLV6_MAS_TRIG3_MASK
+** SLV6 channel mas trigger channel3 ctrl mask bit
+** [31:31] SM_SLV7_MAS_TRIG3_MASK
+** SLV7 channel mas trigger channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0260))
+/*=========================================
+** SLV channel mas trigger ctrl mask bit:
+** SLV channel mas trigger ctrl mask bit
+** [0:0] SM_SLV0_MAS_TRIG4_MASK
+** SLV0 channel mas trigger channel4 ctrl mask bit
+** [1:1] SM_SLV1_MAS_TRIG4_MASK
+** SLV1 channel mas trigger channel4 ctrl mask bit
+** [2:2] SM_SLV2_MAS_TRIG4_MASK
+** SLV2 channel mas trigger channel4 ctrl mask bit
+** [3:3] SM_SLV3_MAS_TRIG4_MASK
+** SLV3 channel mas trigger channel4 ctrl mask bit
+** [4:4] SM_SLV4_MAS_TRIG4_MASK
+** SLV4 channel mas trigger channel4 ctrl mask bit
+** [5:5] SM_SLV5_MAS_TRIG4_MASK
+** SLV5 channel mas trigger channel4 ctrl mask bit
+** [6:6] SM_SLV6_MAS_TRIG4_MASK
+** SLV6 channel mas trigger channel4 ctrl mask bit
+** [7:7] SM_SLV7_MAS_TRIG4_MASK
+** SLV7 channel mas trigger channel4 ctrl mask bit
+** [8:8] SM_SLV0_MAS_TRIG5_MASK
+** SLV0 channel mas trigger channel1 ctrl mask bit
+** [9:9] SM_SLV1_MAS_TRIG5_MASK
+** SLV1 channel mas trigger channel5 ctrl mask bit
+** [10:10] SM_SLV2_MAS_TRIG5_MASK
+** SLV2 channel mas trigger channel5 ctrl mask bit
+** [11:11] SM_SLV3_MAS_TRIG5_MASK
+** SLV3 channel mas trigger channel5 ctrl mask bit
+** [12:12] SM_SLV4_MAS_TRIG5_MASK
+** SLV4 channel mas trigger channel5 ctrl mask bit
+** [13:13] SM_SLV5_MAS_TRIG5_MASK
+** SLV5 channel mas trigger channel5 ctrl mask bit
+** [14:14] SM_SLV6_MAS_TRIG5_MASK
+** SLV6 channel mas trigger channel5 ctrl mask bit
+** [15:15] SM_SLV7_MAS_TRIG5_MASK
+** SLV7 channel mas trigger channel5 ctrl mask bit
+** [16:16] SM_SLV0_MAS_TRIG6_MASK
+** SLV0 channel mas trigger channel6 ctrl mask bit
+** [17:17] SM_SLV1_MAS_TRIG6_MASK
+** SLV1 channel mas trigger channel6 ctrl mask bit
+** [18:18] SM_SLV2_MAS_TRIG6_MASK
+** SLV2 channel mas trigger channel6 ctrl mask bit
+** [19:19] SM_SLV3_MAS_TRIG6_MASK
+** SLV3 channel mas trigger channel6 ctrl mask bit
+** [20:20] SM_SLV4_MAS_TRIG6_MASK
+** SLV4 channel mas trigger channel6 ctrl mask bit
+** [21:21] SM_SLV5_MAS_TRIG6_MASK
+** SLV5 channel mas trigger channel6 ctrl mask bit
+** [22:22] SM_SLV6_MAS_TRIG6_MASK
+** SLV6 channel mas trigger channel6 ctrl mask bit
+** [23:23] SM_SLV7_MAS_TRIG6_MASK
+** SLV7 channel mas trigger channel6 ctrl mask bit
+** [24:24] SM_SLV0_MAS_TRIG7_MASK
+** SLV0 channel mas trigger channel7 ctrl mask bit
+** [25:25] SM_SLV1_MAS_TRIG7_MASK
+** SLV1 channel mas trigger channel7 ctrl mask bit
+** [26:26] SM_SLV2_MAS_TRIG7_MASK
+** SLV2 channel mas trigger channel7 ctrl mask bit
+** [27:27] SM_SLV3_MAS_TRIG7_MASK
+** SLV3 channel mas trigger channel7 ctrl mask bit
+** [28:28] SM_SLV4_MAS_TRIG7_MASK
+** SLV4 channel mas trigger channel7 ctrl mask bit
+** [29:29] SM_SLV5_MAS_TRIG7_MASK
+** SLV5 channel mas trigger channel7 ctrl mask bit
+** [30:30] SM_SLV6_MAS_TRIG7_MASK
+** SLV6 channel mas trigger channel7 ctrl mask bit
+** [31:31] SM_SLV7_MAS_TRIG7_MASK
+** SLV7 channel mas trigger channel7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0264))
+/*=========================================
+** SLV channel timer trigger ctrl mask bit:
+** SLV channel timer trigger ctrl mask bit
+** [0:0] SM_SLV0_TIMER_TRIG0_MASK
+** SLV0 channel timer trigger channel0 ctrl mask bit
+** [1:1] SM_SLV1_TIMER_TRIG0_MASK
+** SLV1 channel timer trigger channel0 ctrl mask bit
+** [2:2] SM_SLV2_TIMER_TRIG0_MASK
+** SLV2 channel timer trigger channel0 ctrl mask bit
+** [3:3] SM_SLV3_TIMER_TRIG0_MASK
+** SLV3 channel timer trigger channel0 ctrl mask bit
+** [4:4] SM_SLV4_TIMER_TRIG0_MASK
+** SLV4 channel timer trigger channel0 ctrl mask bit
+** [5:5] SM_SLV5_TIMER_TRIG0_MASK
+** SLV5 channel timer trigger channel0 ctrl mask bit
+** [6:6] SM_SLV6_TIMER_TRIG0_MASK
+** SLV6 channel timer trigger channel0 ctrl mask bit
+** [7:7] SM_SLV7_TIMER_TRIG0_MASK
+** SLV7 channel timer trigger channel0 ctrl mask bit
+** [8:8] SM_SLV0_TIMER_TRIG1_MASK
+** SLV0 channel timer trigger channel1 ctrl mask bit
+** [9:9] SM_SLV1_TIMER_TRIG1_MASK
+** SLV1 channel timer trigger channel1 ctrl mask bit
+** [10:10] SM_SLV2_TIMER_TRIG1_MASK
+** SLV2 channel timer trigger channel1 ctrl mask bit
+** [11:11] SM_SLV3_TIMER_TRIG1_MASK
+** SLV3 channel timer trigger channel1 ctrl mask bit
+** [12:12] SM_SLV4_TIMER_TRIG1_MASK
+** SLV4 channel timer trigger channel1 ctrl mask bit
+** [13:13] SM_SLV5_TIMER_TRIG1_MASK
+** SLV5 channel timer trigger channel1 ctrl mask bit
+** [14:14] SM_SLV6_TIMER_TRIG1_MASK
+** SLV6 channel timer trigger channel1 ctrl mask bit
+** [15:15] SM_SLV7_TIMER_TRIG1_MASK
+** SLV7 channel timer trigger channel1 ctrl mask bit
+** [16:16] SM_SLV0_TIMER_TRIG2_MASK
+** SLV0 channel timer trigger channel2 ctrl mask bit
+** [17:17] SM_SLV1_TIMER_TRIG2_MASK
+** SLV1 channel timer trigger channel2 ctrl mask bit
+** [18:18] SM_SLV2_TIMER_TRIG2_MASK
+** SLV2 channel timer trigger channel2 ctrl mask bit
+** [19:19] SM_SLV3_TIMER_TRIG2_MASK
+** SLV3 channel timer trigger channel2 ctrl mask bit
+** [20:20] SM_SLV4_TIMER_TRIG2_MASK
+** SLV4 channel timer trigger channel2 ctrl mask bit
+** [21:21] SM_SLV5_TIMER_TRIG2_MASK
+** SLV5 channel timer trigger channel2 ctrl mask bit
+** [22:22] SM_SLV6_TIMER_TRIG2_MASK
+** SLV6 channel timer trigger channel2 ctrl mask bit
+** [23:23] SM_SLV7_TIMER_TRIG2_MASK
+** SLV7 channel timer trigger channel2 ctrl mask bit
+** [24:24] SM_SLV0_TIMER_TRIG3_MASK
+** SLV0 channel timer trigger channel3 ctrl mask bit
+** [25:25] SM_SLV1_TIMER_TRIG3_MASK
+** SLV1 channel timer trigger channel3 ctrl mask bit
+** [26:26] SM_SLV2_TIMER_TRIG3_MASK
+** SLV2 channel timer trigger channel3 ctrl mask bit
+** [27:27] SM_SLV3_TIMER_TRIG3_MASK
+** SLV3 channel timer trigger channel3 ctrl mask bit
+** [28:28] SM_SLV4_TIMER_TRIG3_MASK
+** SLV4 channel timer trigger channel3 ctrl mask bit
+** [29:29] SM_SLV5_TIMER_TRIG3_MASK
+** SLV5 channel timer trigger channel3 ctrl mask bit
+** [30:30] SM_SLV6_TIMER_TRIG3_MASK
+** SLV6 channel timer trigger channel3 ctrl mask bit
+** [31:31] SM_SLV7_TIMER_TRIG3_MASK
+** SLV7 channel timer trigger channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0270))
+/*=========================================
+** SLV channel timer trigger ctrl mask bit:
+** SLV channel timer trigger ctrl mask bit
+** [0:0] SM_SLV0_TIMER_TRIG4_MASK
+** SLV0 channel timer trigger channel4 ctrl mask bit
+** [1:1] SM_SLV1_TIMER_TRIG4_MASK
+** SLV1 channel timer trigger channel4 ctrl mask bit
+** [2:2] SM_SLV2_TIMER_TRIG4_MASK
+** SLV2 channel timer trigger channel4 ctrl mask bit
+** [3:3] SM_SLV3_TIMER_TRIG4_MASK
+** SLV3 channel timer trigger channel4 ctrl mask bit
+** [4:4] SM_SLV4_TIMER_TRIG4_MASK
+** SLV4 channel timer trigger channel4 ctrl mask bit
+** [5:5] SM_SLV5_TIMER_TRIG4_MASK
+** SLV5 channel timer trigger channel4 ctrl mask bit
+** [6:6] SM_SLV6_TIMER_TRIG4_MASK
+** SLV6 channel timer trigger channel4 ctrl mask bit
+** [7:7] SM_SLV7_TIMER_TRIG4_MASK
+** SLV7 channel timer trigger channel4 ctrl mask bit
+** [8:8] SM_SLV0_TIMER_TRIG5_MASK
+** SLV0 channel timer trigger channel5 ctrl mask bit
+** [9:9] SM_SLV1_TIMER_TRIG5_MASK
+** SLV1 channel timer trigger channel5 ctrl mask bit
+** [10:10] SM_SLV2_TIMER_TRIG5_MASK
+** SLV2 channel timer trigger channel5 ctrl mask bit
+** [11:11] SM_SLV3_TIMER_TRIG5_MASK
+** SLV3 channel timer trigger channel5 ctrl mask bit
+** [12:12] SM_SLV4_TIMER_TRIG5_MASK
+** SLV4 channel timer trigger channel5 ctrl mask bit
+** [13:13] SM_SLV5_TIMER_TRIG5_MASK
+** SLV5 channel timer trigger channel5 ctrl mask bit
+** [14:14] SM_SLV6_TIMER_TRIG5_MASK
+** SLV6 channel timer trigger channel5 ctrl mask bit
+** [15:15] SM_SLV7_TIMER_TRIG5_MASK
+** SLV7 channel timer trigger channel5 ctrl mask bit
+** [16:16] SM_SLV0_TIMER_TRIG6_MASK
+** SLV0 channel timer trigger channel6 ctrl mask bit
+** [17:17] SM_SLV1_TIMER_TRIG6_MASK
+** SLV1 channel timer trigger channel6 ctrl mask bit
+** [18:18] SM_SLV2_TIMER_TRIG6_MASK
+** SLV2 channel timer trigger channel6 ctrl mask bit
+** [19:19] SM_SLV3_TIMER_TRIG6_MASK
+** SLV3 channel timer trigger channel6 ctrl mask bit
+** [20:20] SM_SLV4_TIMER_TRIG6_MASK
+** SLV4 channel timer trigger channel6 ctrl mask bit
+** [21:21] SM_SLV5_TIMER_TRIG6_MASK
+** SLV5 channel timer trigger channel6 ctrl mask bit
+** [22:22] SM_SLV6_TIMER_TRIG6_MASK
+** SLV6 channel timer trigger channel6 ctrl mask bit
+** [23:23] SM_SLV7_TIMER_TRIG6_MASK
+** SLV7 channel timer trigger channel6 ctrl mask bit
+** [24:24] SM_SLV0_TIMER_TRIG7_MASK
+** SLV0 channel timer trigger channel7 ctrl mask bit
+** [25:25] SM_SLV1_TIMER_TRIG7_MASK
+** SLV1 channel timer trigger channel7 ctrl mask bit
+** [26:26] SM_SLV2_TIMER_TRIG7_MASK
+** SLV2 channel timer trigger channel7 ctrl mask bit
+** [27:27] SM_SLV3_TIMER_TRIG7_MASK
+** SLV3 channel timer trigger channel7 ctrl mask bit
+** [28:28] SM_SLV4_TIMER_TRIG7_MASK
+** SLV4 channel timer trigger channel7 ctrl mask bit
+** [29:29] SM_SLV5_TIMER_TRIG7_MASK
+** SLV5 channel timer trigger channel7 ctrl mask bit
+** [30:30] SM_SLV6_TIMER_TRIG7_MASK
+** SLV6 channel timer trigger channel7 ctrl mask bit
+** [31:31] SM_SLV7_TIMER_TRIG7_MASK
+** SLV7 channel timer trigger channel7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0274))
+/*=========================================
+** SLV channel client active ctrl mask bit:
+** SLV channel client active ctrl mask bit
+** [0:0] SM_SLV0_CLIENT_ACT0_MASK
+** SLV0 channel client active channel0 ctrl mask bit
+** [1:1] SM_SLV1_CLIENT_ACT0_MASK
+** SLV1 channel client active channel0 ctrl mask bit
+** [2:2] SM_SLV2_CLIENT_ACT0_MASK
+** SLV2 channel client active channel0 ctrl mask bit
+** [3:3] SM_SLV3_CLIENT_ACT0_MASK
+** SLV3 channel client active channel0 ctrl mask bit
+** [4:4] SM_SLV4_CLIENT_ACT0_MASK
+** SLV4 channel client active channel0 ctrl mask bit
+** [5:5] SM_SLV5_CLIENT_ACT0_MASK
+** SLV5 channel client active channel0 ctrl mask bit
+** [6:6] SM_SLV6_CLIENT_ACT0_MASK
+** SLV6 channel client active channel0 ctrl mask bit
+** [7:7] SM_SLV7_CLIENT_ACT0_MASK
+** SLV7 channel client active channel0 ctrl mask bit
+** [8:8] SM_SLV0_CLIENT_ACT1_MASK
+** SLV0 channel client active channel1 ctrl mask bit
+** [9:9] SM_SLV1_CLIENT_ACT1_MASK
+** SLV1 channel client active channel1 ctrl mask bit
+** [10:10] SM_SLV2_CLIENT_ACT1_MASK
+** SLV2 channel client active channel1 ctrl mask bit
+** [11:11] SM_SLV3_CLIENT_ACT1_MASK
+** SLV3 channel client active channel1 ctrl mask bit
+** [12:12] SM_SLV4_CLIENT_ACT1_MASK
+** SLV4 channel client active channel1 ctrl mask bit
+** [13:13] SM_SLV5_CLIENT_ACT1_MASK
+** SLV5 channel client active channel1 ctrl mask bit
+** [14:14] SM_SLV6_CLIENT_ACT1_MASK
+** SLV6 channel client active channel1 ctrl mask bit
+** [15:15] SM_SLV7_CLIENT_ACT1_MASK
+** SLV7 channel client active channel1 ctrl mask bit
+** [16:16] SM_SLV0_CLIENT_ACT2_MASK
+** SLV0 channel client active channel2 ctrl mask bit
+** [17:17] SM_SLV1_CLIENT_ACT2_MASK
+** SLV1 channel client active channel2 ctrl mask bit
+** [18:18] SM_SLV2_CLIENT_ACT2_MASK
+** SLV2 channel client active channel2 ctrl mask bit
+** [19:19] SM_SLV3_CLIENT_ACT2_MASK
+** SLV3 channel client active channel2 ctrl mask bit
+** [20:20] SM_SLV4_CLIENT_ACT2_MASK
+** SLV4 channel client active channel2 ctrl mask bit
+** [21:21] SM_SLV5_CLIENT_ACT2_MASK
+** SLV5 channel client active channel2 ctrl mask bit
+** [22:22] SM_SLV6_CLIENT_ACT2_MASK
+** SLV6 channel client active channel2 ctrl mask bit
+** [23:23] SM_SLV7_CLIENT_ACT2_MASK
+** SLV7 channel client active channel2 ctrl mask bit
+** [24:24] SM_SLV0_CLIENT_ACT3_MASK
+** SLV0 channel client active channel3 ctrl mask bit
+** [25:25] SM_SLV1_CLIENT_ACT3_MASK
+** SLV1 channel client active channel3 ctrl mask bit
+** [26:26] SM_SLV2_CLIENT_ACT3_MASK
+** SLV2 channel client active channel3 ctrl mask bit
+** [27:27] SM_SLV3_CLIENT_ACT3_MASK
+** SLV3 channel client active channel3 ctrl mask bit
+** [28:28] SM_SLV4_CLIENT_ACT3_MASK
+** SLV4 channel client active channel3 ctrl mask bit
+** [29:29] SM_SLV5_CLIENT_ACT3_MASK
+** SLV5 channel client active channel3 ctrl mask bit
+** [30:30] SM_SLV6_CLIENT_ACT3_MASK
+** SLV6 channel client active channel3 ctrl mask bit
+** [31:31] SM_SLV7_CLIENT_ACT3_MASK
+** SLV7 channel client active channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0280))
+/*=========================================
+** SLV channel FSM status:
+** SLV channel FSM status
+** 0000001: Normal stage
+** 0000010: MTOFF stage
+** 0000100: PAUSE stage
+** 0001000: PRE_PAUSE stage
+** 0010000: SYSCLK_SETTLE stage
+** 0100000: CCP_SETTLE stage
+** 1000000: MTON stage
+** [6:0] SM_SLV0_SSTA
+** SLV0 channel FSM status
+** [14:8] SM_SLV1_SSTA
+** SLV1 channel FSM status
+** [22:16] SM_SLV2_SSTA
+** SLV2 channel FSM status
+** [30:24] SM_SLV3_SSTA
+** SLV3 channel FSM status
+**=========================================*/
+#define MD_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x02A0))
+/*=========================================
+** SLV channel FSM status:
+** SLV channel FSM status
+** 0000001: Normal stage
+** 0000010: MTOFF stage
+** 0000100: PAUSE stage
+** 0001000: PRE_PAUSE stage
+** 0010000: SYSCLK_SETTLE stage
+** 0100000: CCP_SETTLE stage
+** 1000000: MTON stage
+** [6:0] SM_SLV4_SSTA
+** SLV4 channel FSM status
+** [14:8] SM_SLV5_SSTA
+** SLV5 channel FSM status
+** [22:16] SM_SLV6_SSTA
+** SLV6 channel FSM status
+** [30:24] SM_SLV7_SSTA
+** SLV7 channel FSM status
+**=========================================*/
+#define MD_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x02A4))
+/*=========================================
+** DBG channel request mask bit:
+** DBG channel request mask bit
+** [0:0] SM_DBG0_REQ_MASK
+** DBG0 channel request mask bit
+** [1:1] SM_DBG1_REQ_MASK
+** DBG1 channel request mask bit
+** [2:2] SM_DBG2_REQ_MASK
+** DBG2 channel request mask bit
+** [3:3] SM_DBG3_REQ_MASK
+** DBG3 channel request mask bit
+** [4:4] SM_DBG4_REQ_MASK
+** DBG4 channel request mask bit
+** [5:5] SM_DBG5_REQ_MASK
+** DBG5 channel request mask bit
+** [6:6] SM_DBG6_REQ_MASK
+** DBG6 channel request mask bit
+** [7:7] SM_DBG7_REQ_MASK
+** DBG7 channel request mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0300))
+/*=========================================
+** DBG channel sysclk ctrl mask bit:
+** DBG channel sysclk ctrl mask bit
+** [0:0] SM_DBG0_SYSCLK_MASK
+** DBG0 channel sysclk ctrl mask bit
+** [1:1] SM_DBG1_SYSCLK_MASK
+** DBG1 channel sysclk ctrl mask bit
+** [2:2] SM_DBG2_SYSCLK_MASK
+** DBG2 channel sysclk ctrl mask bit
+** [3:3] SM_DBG3_SYSCLK_MASK
+** DBG3 channel sysclk ctrl mask bit
+** [4:4] SM_DBG4_SYSCLK_MASK
+** DBG4 channel sysclk ctrl mask bit
+** [5:5] SM_DBG5_SYSCLK_MASK
+** DBG5 channel sysclk ctrl mask bit
+** [6:6] SM_DBG6_SYSCLK_MASK
+** DBG6 channel sysclk ctrl mask bit
+** [7:7] SM_DBG7_SYSCLK_MASK
+** DBG7 channel sysclk ctrl mask bit
+** [8:8] SM_DBG0_SYSCLK1_MASK
+** DBG0 channel sysclk1 ctrl mask bit
+** [9:9] SM_DBG1_SYSCLK1_MASK
+** DBG1 channel sysclk1 ctrl mask bit
+** [10:10] SM_DBG2_SYSCLK1_MASK
+** DBG2 channel sysclk1 ctrl mask bit
+** [11:11] SM_DBG3_SYSCLK1_MASK
+** DBG3 channel sysclk1 ctrl mask bit
+** [12:12] SM_DBG4_SYSCLK1_MASK
+** DBG4 channel sysclk1 ctrl mask bit
+** [13:13] SM_DBG5_SYSCLK1_MASK
+** DBG5 channel sysclk1 ctrl mask bit
+** [14:14] SM_DBG6_SYSCLK1_MASK
+** DBG6 channel sysclk1 ctrl mask bit
+** [15:15] SM_DBG7_SYSCLK1_MASK
+** DBG7 channel sysclk1 ctrl mask bit
+** [16:16] SM_DBG0_SYSCLK2_MASK
+** DBG0 channel sysclk2 ctrl mask bit
+** [17:17] SM_DBG1_SYSCLK2_MASK
+** DBG1 channel sysclk2 ctrl mask bit
+** [18:18] SM_DBG2_SYSCLK2_MASK
+** DBG2 channel sysclk2 ctrl mask bit
+** [19:19] SM_DBG3_SYSCLK2_MASK
+** DBG3 channel sysclk2 ctrl mask bit
+** [20:20] SM_DBG4_SYSCLK2_MASK
+** DBG4 channel sysclk2 ctrl mask bit
+** [21:21] SM_DBG5_SYSCLK2_MASK
+** DBG5 channel sysclk2 ctrl mask bit
+** [22:22] SM_DBG6_SYSCLK2_MASK
+** DBG6 channel sysclk2 ctrl mask bit
+** [23:23] SM_DBG7_SYSCLK2_MASK
+** DBG7 channel sysclk2 ctrl mask bit
+** [24:24] SM_DBG0_SYSCLK3_MASK
+** DBG0 channel sysclk3 ctrl mask bit
+** [25:25] SM_DBG1_SYSCLK3_MASK
+** DBG1 channel sysclk3 ctrl mask bit
+** [26:26] SM_DBG2_SYSCLK3_MASK
+** DBG2 channel sysclk3 ctrl mask bit
+** [27:27] SM_DBG3_SYSCLK3_MASK
+** DBG3 channel sysclk3 ctrl mask bit
+** [28:28] SM_DBG4_SYSCLK3_MASK
+** DBG4 channel sysclk3 ctrl mask bit
+** [29:29] SM_DBG5_SYSCLK3_MASK
+** DBG5 channel sysclk3 ctrl mask bit
+** [30:30] SM_DBG6_SYSCLK3_MASK
+** DBG6 channel sysclk3 ctrl mask bit
+** [31:31] SM_DBG7_SYSCLK3_MASK
+** DBG7 channel sysclk3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0308))
+/*=========================================
+** DBG channel pll ctrl mask bit:
+** DBG channel pll ctrl mask bit
+** [0:0] SM_DBG0_PLL0_MASK
+** DBG0 channel pll0 ctrl mask bit
+** [1:1] SM_DBG1_PLL0_MASK
+** DBG1 channel pll0 ctrl mask bit
+** [2:2] SM_DBG2_PLL0_MASK
+** DBG2 channel pll0 ctrl mask bit
+** [3:3] SM_DBG3_PLL0_MASK
+** DBG3 channel pll0 ctrl mask bit
+** [4:4] SM_DBG4_PLL0_MASK
+** DBG4 channel pll0 ctrl mask bit
+** [5:5] SM_DBG5_PLL0_MASK
+** DBG5 channel pll0 ctrl mask bit
+** [6:6] SM_DBG6_PLL0_MASK
+** DBG6 channel pll0 ctrl mask bit
+** [7:7] SM_DBG7_PLL0_MASK
+** DBG7 channel pll0 ctrl mask bit
+** [8:8] SM_DBG0_PLL1_MASK
+** DBG0 channel pll1 ctrl mask bit
+** [9:9] SM_DBG1_PLL1_MASK
+** DBG1 channel pll1 ctrl mask bit
+** [10:10] SM_DBG2_PLL1_MASK
+** DBG2 channel pll1 ctrl mask bit
+** [11:11] SM_DBG3_PLL1_MASK
+** DBG3 channel pll1 ctrl mask bit
+** [12:12] SM_DBG4_PLL1_MASK
+** DBG4 channel pll1 ctrl mask bit
+** [13:13] SM_DBG5_PLL1_MASK
+** DBG5 channel pll1 ctrl mask bit
+** [14:14] SM_DBG6_PLL1_MASK
+** DBG6 channel pll1 ctrl mask bit
+** [15:15] SM_DBG7_PLL1_MASK
+** DBG7 channel pll1 ctrl mask bit
+** [16:16] SM_DBG0_PLL2_MASK
+** DBG0 channel pll2 ctrl mask bit
+** [17:17] SM_DBG1_PLL2_MASK
+** DBG1 channel pll2 ctrl mask bit
+** [18:18] SM_DBG2_PLL2_MASK
+** DBG2 channel pll2 ctrl mask bit
+** [19:19] SM_DBG3_PLL2_MASK
+** DBG3 channel pll2 ctrl mask bit
+** [20:20] SM_DBG4_PLL2_MASK
+** DBG4 channel pll2 ctrl mask bit
+** [21:21] SM_DBG5_PLL2_MASK
+** DBG5 channel pll2 ctrl mask bit
+** [22:22] SM_DBG6_PLL2_MASK
+** DBG6 channel pll2 ctrl mask bit
+** [23:23] SM_DBG7_PLL2_MASK
+** DBG7 channel pll2 ctrl mask bit
+** [24:24] SM_DBG0_PLL3_MASK
+** DBG0 channel pll3 ctrl mask bit
+** [25:25] SM_DBG1_PLL3_MASK
+** DBG1 channel pll3 ctrl mask bit
+** [26:26] SM_DBG2_PLL3_MASK
+** DBG2 channel pll3 ctrl mask bit
+** [27:27] SM_DBG3_PLL3_MASK
+** DBG3 channel pll3 ctrl mask bit
+** [28:28] SM_DBG4_PLL3_MASK
+** DBG4 channel pll3 ctrl mask bit
+** [29:29] SM_DBG5_PLL3_MASK
+** DBG5 channel pll3 ctrl mask bit
+** [30:30] SM_DBG6_PLL3_MASK
+** DBG6 channel pll3 ctrl mask bit
+** [31:31] SM_DBG7_PLL3_MASK
+** DBG7 channel pll3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0320))
+/*=========================================
+** DBG channel pll ctrl mask bit:
+** DBG channel pll ctrl mask bit
+** [0:0] SM_DBG0_PLL4_MASK
+** DBG0 channel pll4 ctrl mask bit
+** [1:1] SM_DBG1_PLL4_MASK
+** DBG1 channel pll4 ctrl mask bit
+** [2:2] SM_DBG2_PLL4_MASK
+** DBG2 channel pll4 ctrl mask bit
+** [3:3] SM_DBG3_PLL4_MASK
+** DBG3 channel pll4 ctrl mask bit
+** [4:4] SM_DBG4_PLL4_MASK
+** DBG4 channel pll4 ctrl mask bit
+** [5:5] SM_DBG5_PLL4_MASK
+** DBG5 channel pll4 ctrl mask bit
+** [6:6] SM_DBG6_PLL4_MASK
+** DBG6 channel pll4 ctrl mask bit
+** [7:7] SM_DBG7_PLL4_MASK
+** DBG7 channel pll4 ctrl mask bit
+** [8:8] SM_DBG0_PLL5_MASK
+** DBG0 channel pll5 ctrl mask bit
+** [9:9] SM_DBG1_PLL5_MASK
+** DBG1 channel pll5 ctrl mask bit
+** [10:10] SM_DBG2_PLL5_MASK
+** DBG2 channel pll5 ctrl mask bit
+** [11:11] SM_DBG3_PLL5_MASK
+** DBG3 channel pll5 ctrl mask bit
+** [12:12] SM_DBG4_PLL5_MASK
+** DBG4 channel pll5 ctrl mask bit
+** [13:13] SM_DBG5_PLL5_MASK
+** DBG5 channel pll5 ctrl mask bit
+** [14:14] SM_DBG6_PLL5_MASK
+** DBG6 channel pll5 ctrl mask bit
+** [15:15] SM_DBG7_PLL5_MASK
+** DBG7 channel pll5 ctrl mask bit
+** [16:16] SM_DBG0_PLL6_MASK
+** DBG0 channel pll6 ctrl mask bit
+** [17:17] SM_DBG1_PLL6_MASK
+** DBG1 channel pll6 ctrl mask bit
+** [18:18] SM_DBG2_PLL6_MASK
+** DBG2 channel pll6 ctrl mask bit
+** [19:19] SM_DBG3_PLL6_MASK
+** DBG3 channel pll6 ctrl mask bit
+** [20:20] SM_DBG4_PLL6_MASK
+** DBG4 channel pll6 ctrl mask bit
+** [21:21] SM_DBG5_PLL6_MASK
+** DBG5 channel pll6 ctrl mask bit
+** [22:22] SM_DBG6_PLL6_MASK
+** DBG6 channel pll6 ctrl mask bit
+** [23:23] SM_DBG7_PLL6_MASK
+** DBG7 channel pll6 ctrl mask bit
+** [24:24] SM_DBG0_PLL7_MASK
+** DBG0 channel pll7 ctrl mask bit
+** [25:25] SM_DBG1_PLL7_MASK
+** DBG1 channel pll7 ctrl mask bit
+** [26:26] SM_DBG2_PLL7_MASK
+** DBG2 channel pll7 ctrl mask bit
+** [27:27] SM_DBG3_PLL7_MASK
+** DBG3 channel pll7 ctrl mask bit
+** [28:28] SM_DBG4_PLL7_MASK
+** DBG4 channel pll7 ctrl mask bit
+** [29:29] SM_DBG5_PLL7_MASK
+** DBG5 channel pll7 ctrl mask bit
+** [30:30] SM_DBG6_PLL7_MASK
+** DBG6 channel pll7 ctrl mask bit
+** [31:31] SM_DBG7_PLL7_MASK
+** DBG7 channel pll7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0324))
+/*=========================================
+** DBG channel pll ctrl mask bit:
+** DBG channel pll ctrl mask bit
+** [0:0] SM_DBG0_PLL8_MASK
+** DBG0 channel pll8 ctrl mask bit
+** [1:1] SM_DBG1_PLL8_MASK
+** DBG1 channel pll8 ctrl mask bit
+** [2:2] SM_DBG2_PLL8_MASK
+** DBG2 channel pll8 ctrl mask bit
+** [3:3] SM_DBG3_PLL8_MASK
+** DBG3 channel pll8 ctrl mask bit
+** [4:4] SM_DBG4_PLL8_MASK
+** DBG4 channel pll8 ctrl mask bit
+** [5:5] SM_DBG5_PLL8_MASK
+** DBG5 channel pll8 ctrl mask bit
+** [6:6] SM_DBG6_PLL8_MASK
+** DBG6 channel pll8 ctrl mask bit
+** [7:7] SM_DBG7_PLL8_MASK
+** DBG7 channel pll8 ctrl mask bit
+** [8:8] SM_DBG0_PLL9_MASK
+** DBG0 channel pll9 ctrl mask bit
+** [9:9] SM_DBG1_PLL9_MASK
+** DBG1 channel pll9 ctrl mask bit
+** [10:10] SM_DBG2_PLL9_MASK
+** DBG2 channel pll9 ctrl mask bit
+** [11:11] SM_DBG3_PLL9_MASK
+** DBG3 channel pll9 ctrl mask bit
+** [12:12] SM_DBG4_PLL9_MASK
+** DBG4 channel pll9 ctrl mask bit
+** [13:13] SM_DBG5_PLL9_MASK
+** DBG5 channel pll9 ctrl mask bit
+** [14:14] SM_DBG6_PLL9_MASK
+** DBG6 channel pll9 ctrl mask bit
+** [15:15] SM_DBG7_PLL9_MASK
+** DBG7 channel pll9 ctrl mask bit
+** [16:16] SM_DBG0_PLL10_MASK
+** DBG0 channel pll10 ctrl mask bit
+** [17:17] SM_DBG1_PLL10_MASK
+** DBG1 channel pll10 ctrl mask bit
+** [18:18] SM_DBG2_PLL10_MASK
+** DBG2 channel pll10 ctrl mask bit
+** [19:19] SM_DBG3_PLL10_MASK
+** DBG3 channel pll10 ctrl mask bit
+** [20:20] SM_DBG4_PLL10_MASK
+** DBG4 channel pll10 ctrl mask bit
+** [21:21] SM_DBG5_PLL10_MASK
+** DBG5 channel pll10 ctrl mask bit
+** [22:22] SM_DBG6_PLL10_MASK
+** DBG6 channel pll10 ctrl mask bit
+** [23:23] SM_DBG7_PLL10_MASK
+** DBG7 channel pll10 ctrl mask bit
+** [24:24] SM_DBG0_PLL11_MASK
+** DBG0 channel pll11 ctrl mask bit
+** [25:25] SM_DBG1_PLL11_MASK
+** DBG1 channel pll11 ctrl mask bit
+** [26:26] SM_DBG2_PLL11_MASK
+** DBG2 channel pll11 ctrl mask bit
+** [27:27] SM_DBG3_PLL11_MASK
+** DBG3 channel pll11 ctrl mask bit
+** [28:28] SM_DBG4_PLL11_MASK
+** DBG4 channel pll11 ctrl mask bit
+** [29:29] SM_DBG5_PLL11_MASK
+** DBG5 channel pll11 ctrl mask bit
+** [30:30] SM_DBG6_PLL11_MASK
+** DBG6 channel pll11 ctrl mask bit
+** [31:31] SM_DBG7_PLL11_MASK
+** DBG7 channel pll11 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PLL_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0328))
+/*=========================================
+** DBG channel pll ctrl mask bit:
+** DBG channel pll ctrl mask bit
+** [0:0] SM_DBG0_PLL12_MASK
+** DBG0 channel pll12 ctrl mask bit
+** [1:1] SM_DBG1_PLL12_MASK
+** DBG1 channel pll12 ctrl mask bit
+** [2:2] SM_DBG2_PLL12_MASK
+** DBG2 channel pll12 ctrl mask bit
+** [3:3] SM_DBG3_PLL12_MASK
+** DBG3 channel pll12 ctrl mask bit
+** [4:4] SM_DBG4_PLL12_MASK
+** DBG4 channel pll12 ctrl mask bit
+** [5:5] SM_DBG5_PLL12_MASK
+** DBG5 channel pll12 ctrl mask bit
+** [6:6] SM_DBG6_PLL12_MASK
+** DBG6 channel pll12 ctrl mask bit
+** [7:7] SM_DBG7_PLL12_MASK
+** DBG7 channel pll12 ctrl mask bit
+** [8:8] SM_DBG0_PLL13_MASK
+** DBG0 channel pll13 ctrl mask bit
+** [9:9] SM_DBG1_PLL13_MASK
+** DBG1 channel pll13 ctrl mask bit
+** [10:10] SM_DBG2_PLL13_MASK
+** DBG2 channel pll13 ctrl mask bit
+** [11:11] SM_DBG3_PLL13_MASK
+** DBG3 channel pll13 ctrl mask bit
+** [12:12] SM_DBG4_PLL13_MASK
+** DBG4 channel pll13 ctrl mask bit
+** [13:13] SM_DBG5_PLL13_MASK
+** DBG5 channel pll13 ctrl mask bit
+** [14:14] SM_DBG6_PLL13_MASK
+** DBG6 channel pll13 ctrl mask bit
+** [15:15] SM_DBG7_PLL13_MASK
+** DBG7 channel pll13 ctrl mask bit
+** [16:16] SM_DBG0_PLL14_MASK
+** DBG0 channel pll14 ctrl mask bit
+** [17:17] SM_DBG1_PLL14_MASK
+** DBG1 channel pll14 ctrl mask bit
+** [18:18] SM_DBG2_PLL14_MASK
+** DBG2 channel pll14 ctrl mask bit
+** [19:19] SM_DBG3_PLL14_MASK
+** DBG3 channel pll14 ctrl mask bit
+** [20:20] SM_DBG4_PLL14_MASK
+** DBG4 channel pll14 ctrl mask bit
+** [21:21] SM_DBG5_PLL14_MASK
+** DBG5 channel pll14 ctrl mask bit
+** [22:22] SM_DBG6_PLL14_MASK
+** DBG6 channel pll14 ctrl mask bit
+** [23:23] SM_DBG7_PLL14_MASK
+** DBG7 channel pll14 ctrl mask bit
+** [24:24] SM_DBG0_PLL15_MASK
+** DBG0 channel pll15 ctrl mask bit
+** [25:25] SM_DBG1_PLL15_MASK
+** DBG1 channel pll15 ctrl mask bit
+** [26:26] SM_DBG2_PLL15_MASK
+** DBG2 channel pll15 ctrl mask bit
+** [27:27] SM_DBG3_PLL15_MASK
+** DBG3 channel pll15 ctrl mask bit
+** [28:28] SM_DBG4_PLL15_MASK
+** DBG4 channel pll15 ctrl mask bit
+** [29:29] SM_DBG5_PLL15_MASK
+** DBG5 channel pll15 ctrl mask bit
+** [30:30] SM_DBG6_PLL15_MASK
+** DBG6 channel pll15 ctrl mask bit
+** [31:31] SM_DBG7_PLL15_MASK
+** DBG7 channel pll15 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PLL_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x032C))
+/*=========================================
+** DBG channel pwr ctrl mask bit:
+** DBG channel pwr ctrl mask bit
+** [0:0] SM_DBG0_PWR0_MASK
+** DBG0 channel pwr0 ctrl mask bit
+** [1:1] SM_DBG1_PWR0_MASK
+** DBG1 channel pwr0 ctrl mask bit
+** [2:2] SM_DBG2_PWR0_MASK
+** DBG2 channel pwr0 ctrl mask bit
+** [3:3] SM_DBG3_PWR0_MASK
+** DBG3 channel pwr0 ctrl mask bit
+** [4:4] SM_DBG4_PWR0_MASK
+** DBG4 channel pwr0 ctrl mask bit
+** [5:5] SM_DBG5_PWR0_MASK
+** DBG5 channel pwr0 ctrl mask bit
+** [6:6] SM_DBG6_PWR0_MASK
+** DBG6 channel pwr0 ctrl mask bit
+** [7:7] SM_DBG7_PWR0_MASK
+** DBG7 channel pwr0 ctrl mask bit
+** [8:8] SM_DBG0_PWR1_MASK
+** DBG0 channel pwr1 ctrl mask bit
+** [9:9] SM_DBG1_PWR1_MASK
+** DBG1 channel pwr1 ctrl mask bit
+** [10:10] SM_DBG2_PWR1_MASK
+** DBG2 channel pwr1 ctrl mask bit
+** [11:11] SM_DBG3_PWR1_MASK
+** DBG3 channel pwr1 ctrl mask bit
+** [12:12] SM_DBG4_PWR1_MASK
+** DBG4 channel pwr1 ctrl mask bit
+** [13:13] SM_DBG5_PWR1_MASK
+** DBG5 channel pwr1 ctrl mask bit
+** [14:14] SM_DBG6_PWR1_MASK
+** DBG6 channel pwr1 ctrl mask bit
+** [15:15] SM_DBG7_PWR1_MASK
+** DBG7 channel pwr1 ctrl mask bit
+** [16:16] SM_DBG0_PWR2_MASK
+** DBG0 channel pwr2 ctrl mask bit
+** [17:17] SM_DBG1_PWR2_MASK
+** DBG1 channel pwr2 ctrl mask bit
+** [18:18] SM_DBG2_PWR2_MASK
+** DBG2 channel pwr2 ctrl mask bit
+** [19:19] SM_DBG3_PWR2_MASK
+** DBG3 channel pwr2 ctrl mask bit
+** [20:20] SM_DBG4_PWR2_MASK
+** DBG4 channel pwr2 ctrl mask bit
+** [21:21] SM_DBG5_PWR2_MASK
+** DBG5 channel pwr2 ctrl mask bit
+** [22:22] SM_DBG6_PWR2_MASK
+** DBG6 channel pwr2 ctrl mask bit
+** [23:23] SM_DBG7_PWR2_MASK
+** DBG7 channel pwr2 ctrl mask bit
+** [24:24] SM_DBG0_PWR3_MASK
+** DBG0 channel pwr3 ctrl mask bit
+** [25:25] SM_DBG1_PWR3_MASK
+** DBG1 channel pwr3 ctrl mask bit
+** [26:26] SM_DBG2_PWR3_MASK
+** DBG2 channel pwr3 ctrl mask bit
+** [27:27] SM_DBG3_PWR3_MASK
+** DBG3 channel pwr3 ctrl mask bit
+** [28:28] SM_DBG4_PWR3_MASK
+** DBG4 channel pwr3 ctrl mask bit
+** [29:29] SM_DBG5_PWR3_MASK
+** DBG5 channel pwr3 ctrl mask bit
+** [30:30] SM_DBG6_PWR3_MASK
+** DBG6 channel pwr3 ctrl mask bit
+** [31:31] SM_DBG7_PWR3_MASK
+** DBG7 channel pwr3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0340))
+/*=========================================
+** DBG channel pwr ctrl mask bit:
+** DBG channel pwr ctrl mask bit
+** [0:0] SM_DBG0_PWR4_MASK
+** DBG0 channel pwr4 ctrl mask bit
+** [1:1] SM_DBG1_PWR4_MASK
+** DBG1 channel pwr4 ctrl mask bit
+** [2:2] SM_DBG2_PWR4_MASK
+** DBG2 channel pwr4 ctrl mask bit
+** [3:3] SM_DBG3_PWR4_MASK
+** DBG3 channel pwr4 ctrl mask bit
+** [4:4] SM_DBG4_PWR4_MASK
+** DBG4 channel pwr4 ctrl mask bit
+** [5:5] SM_DBG5_PWR4_MASK
+** DBG5 channel pwr4 ctrl mask bit
+** [6:6] SM_DBG6_PWR4_MASK
+** DBG6 channel pwr4 ctrl mask bit
+** [7:7] SM_DBG7_PWR4_MASK
+** DBG7 channel pwr4 ctrl mask bit
+** [8:8] SM_DBG0_PWR5_MASK
+** DBG0 channel pwr5 ctrl mask bit
+** [9:9] SM_DBG1_PWR5_MASK
+** DBG1 channel pwr5 ctrl mask bit
+** [10:10] SM_DBG2_PWR5_MASK
+** DBG2 channel pwr5 ctrl mask bit
+** [11:11] SM_DBG3_PWR5_MASK
+** DBG3 channel pwr5 ctrl mask bit
+** [12:12] SM_DBG4_PWR5_MASK
+** DBG4 channel pwr5 ctrl mask bit
+** [13:13] SM_DBG5_PWR5_MASK
+** DBG5 channel pwr5 ctrl mask bit
+** [14:14] SM_DBG6_PWR5_MASK
+** DBG6 channel pwr5 ctrl mask bit
+** [15:15] SM_DBG7_PWR5_MASK
+** DBG7 channel pwr5 ctrl mask bit
+** [16:16] SM_DBG0_PWR6_MASK
+** DBG0 channel pwr6 ctrl mask bit
+** [17:17] SM_DBG1_PWR6_MASK
+** DBG1 channel pwr6 ctrl mask bit
+** [18:18] SM_DBG2_PWR6_MASK
+** DBG2 channel pwr6 ctrl mask bit
+** [19:19] SM_DBG3_PWR6_MASK
+** DBG3 channel pwr6 ctrl mask bit
+** [20:20] SM_DBG4_PWR6_MASK
+** DBG4 channel pwr6 ctrl mask bit
+** [21:21] SM_DBG5_PWR6_MASK
+** DBG5 channel pwr6 ctrl mask bit
+** [22:22] SM_DBG6_PWR6_MASK
+** DBG6 channel pwr6 ctrl mask bit
+** [23:23] SM_DBG7_PWR6_MASK
+** DBG7 channel pwr6 ctrl mask bit
+** [24:24] SM_DBG0_PWR7_MASK
+** DBG0 channel pwr7 ctrl mask bit
+** [25:25] SM_DBG1_PWR7_MASK
+** DBG1 channel pwr7 ctrl mask bit
+** [26:26] SM_DBG2_PWR7_MASK
+** DBG2 channel pwr7 ctrl mask bit
+** [27:27] SM_DBG3_PWR7_MASK
+** DBG3 channel pwr7 ctrl mask bit
+** [28:28] SM_DBG4_PWR7_MASK
+** DBG4 channel pwr7 ctrl mask bit
+** [29:29] SM_DBG5_PWR7_MASK
+** DBG5 channel pwr7 ctrl mask bit
+** [30:30] SM_DBG6_PWR7_MASK
+** DBG6 channel pwr7 ctrl mask bit
+** [31:31] SM_DBG7_PWR7_MASK
+** DBG7 channel pwr7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0344))
+/*=========================================
+** DBG channel pwr ctrl mask bit:
+** DBG channel pwr ctrl mask bit
+** [0:0] SM_DBG0_PWR8_MASK
+** DBG0 channel pwr8 ctrl mask bit
+** [1:1] SM_DBG1_PWR8_MASK
+** DBG1 channel pwr8 ctrl mask bit
+** [2:2] SM_DBG2_PWR8_MASK
+** DBG2 channel pwr8 ctrl mask bit
+** [3:3] SM_DBG3_PWR8_MASK
+** DBG3 channel pwr8 ctrl mask bit
+** [4:4] SM_DBG4_PWR8_MASK
+** DBG4 channel pwr8 ctrl mask bit
+** [5:5] SM_DBG5_PWR8_MASK
+** DBG5 channel pwr8 ctrl mask bit
+** [6:6] SM_DBG6_PWR8_MASK
+** DBG6 channel pwr8 ctrl mask bit
+** [7:7] SM_DBG7_PWR8_MASK
+** DBG7 channel pwr8 ctrl mask bit
+** [8:8] SM_DBG0_PWR9_MASK
+** DBG0 channel pwr9 ctrl mask bit
+** [9:9] SM_DBG1_PWR9_MASK
+** DBG1 channel pwr9 ctrl mask bit
+** [10:10] SM_DBG2_PWR9_MASK
+** DBG2 channel pwr9 ctrl mask bit
+** [11:11] SM_DBG3_PWR9_MASK
+** DBG3 channel pwr9 ctrl mask bit
+** [12:12] SM_DBG4_PWR9_MASK
+** DBG4 channel pwr9 ctrl mask bit
+** [13:13] SM_DBG5_PWR9_MASK
+** DBG5 channel pwr9 ctrl mask bit
+** [14:14] SM_DBG6_PWR9_MASK
+** DBG6 channel pwr9 ctrl mask bit
+** [15:15] SM_DBG7_PWR9_MASK
+** DBG7 channel pwr9 ctrl mask bit
+** [16:16] SM_DBG0_PWR10_MASK
+** DBG0 channel pwr10 ctrl mask bit
+** [17:17] SM_DBG1_PWR10_MASK
+** DBG1 channel pwr10 ctrl mask bit
+** [18:18] SM_DBG2_PWR10_MASK
+** DBG2 channel pwr10 ctrl mask bit
+** [19:19] SM_DBG3_PWR10_MASK
+** DBG3 channel pwr10 ctrl mask bit
+** [20:20] SM_DBG4_PWR10_MASK
+** DBG4 channel pwr10 ctrl mask bit
+** [21:21] SM_DBG5_PWR10_MASK
+** DBG5 channel pwr10 ctrl mask bit
+** [22:22] SM_DBG6_PWR10_MASK
+** DBG6 channel pwr10 ctrl mask bit
+** [23:23] SM_DBG7_PWR10_MASK
+** DBG7 channel pwr10 ctrl mask bit
+** [24:24] SM_DBG0_PWR11_MASK
+** DBG0 channel pwr11 ctrl mask bit
+** [25:25] SM_DBG1_PWR11_MASK
+** DBG1 channel pwr11 ctrl mask bit
+** [26:26] SM_DBG2_PWR11_MASK
+** DBG2 channel pwr11 ctrl mask bit
+** [27:27] SM_DBG3_PWR11_MASK
+** DBG3 channel pwr11 ctrl mask bit
+** [28:28] SM_DBG4_PWR11_MASK
+** DBG4 channel pwr11 ctrl mask bit
+** [29:29] SM_DBG5_PWR11_MASK
+** DBG5 channel pwr11 ctrl mask bit
+** [30:30] SM_DBG6_PWR11_MASK
+** DBG6 channel pwr11 ctrl mask bit
+** [31:31] SM_DBG7_PWR11_MASK
+** DBG7 channel pwr11 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PWR_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0348))
+/*=========================================
+** DBG channel pwr ctrl mask bit:
+** DBG channel pwr ctrl mask bit
+** [0:0] SM_DBG0_PWR12_MASK
+** DBG0 channel pwr12 ctrl mask bit
+** [1:1] SM_DBG1_PWR12_MASK
+** DBG1 channel pwr12 ctrl mask bit
+** [2:2] SM_DBG2_PWR12_MASK
+** DBG2 channel pwr12 ctrl mask bit
+** [3:3] SM_DBG3_PWR12_MASK
+** DBG3 channel pwr12 ctrl mask bit
+** [4:4] SM_DBG4_PWR12_MASK
+** DBG4 channel pwr12 ctrl mask bit
+** [5:5] SM_DBG5_PWR12_MASK
+** DBG5 channel pwr12 ctrl mask bit
+** [6:6] SM_DBG6_PWR12_MASK
+** DBG6 channel pwr12 ctrl mask bit
+** [7:7] SM_DBG7_PWR12_MASK
+** DBG7 channel pwr12 ctrl mask bit
+** [8:8] SM_DBG0_PWR13_MASK
+** DBG0 channel pwr13 ctrl mask bit
+** [9:9] SM_DBG1_PWR13_MASK
+** DBG1 channel pwr13 ctrl mask bit
+** [10:10] SM_DBG2_PWR13_MASK
+** DBG2 channel pwr13 ctrl mask bit
+** [11:11] SM_DBG3_PWR13_MASK
+** DBG3 channel pwr13 ctrl mask bit
+** [12:12] SM_DBG4_PWR13_MASK
+** DBG4 channel pwr13 ctrl mask bit
+** [13:13] SM_DBG5_PWR13_MASK
+** DBG5 channel pwr13 ctrl mask bit
+** [14:14] SM_DBG6_PWR13_MASK
+** DBG6 channel pwr13 ctrl mask bit
+** [15:15] SM_DBG7_PWR13_MASK
+** DBG7 channel pwr13 ctrl mask bit
+** [16:16] SM_DBG0_PWR14_MASK
+** DBG0 channel pwr14 ctrl mask bit
+** [17:17] SM_DBG1_PWR14_MASK
+** DBG1 channel pwr14 ctrl mask bit
+** [18:18] SM_DBG2_PWR14_MASK
+** DBG2 channel pwr14 ctrl mask bit
+** [19:19] SM_DBG3_PWR14_MASK
+** DBG3 channel pwr14 ctrl mask bit
+** [20:20] SM_DBG4_PWR14_MASK
+** DBG4 channel pwr14 ctrl mask bit
+** [21:21] SM_DBG5_PWR14_MASK
+** DBG5 channel pwr14 ctrl mask bit
+** [22:22] SM_DBG6_PWR14_MASK
+** DBG6 channel pwr14 ctrl mask bit
+** [23:23] SM_DBG7_PWR14_MASK
+** DBG7 channel pwr14 ctrl mask bit
+** [24:24] SM_DBG0_PWR15_MASK
+** DBG0 channel pwr15 ctrl mask bit
+** [25:25] SM_DBG1_PWR15_MASK
+** DBG1 channel pwr15 ctrl mask bit
+** [26:26] SM_DBG2_PWR15_MASK
+** DBG2 channel pwr15 ctrl mask bit
+** [27:27] SM_DBG3_PWR15_MASK
+** DBG3 channel pwr15 ctrl mask bit
+** [28:28] SM_DBG4_PWR15_MASK
+** DBG4 channel pwr15 ctrl mask bit
+** [29:29] SM_DBG5_PWR15_MASK
+** DBG5 channel pwr15 ctrl mask bit
+** [30:30] SM_DBG6_PWR15_MASK
+** DBG6 channel pwr15 ctrl mask bit
+** [31:31] SM_DBG7_PWR15_MASK
+** DBG7 channel pwr15 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PWR_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x034C))
+/*=========================================
+** DBG channel pwr ctrl mask bit:
+** DBG channel pwr ctrl mask bit
+** [0:0] SM_DBG0_PWR16_MASK
+** DBG0 channel pwr16 ctrl mask bit
+** [1:1] SM_DBG1_PWR16_MASK
+** DBG1 channel pwr16 ctrl mask bit
+** [2:2] SM_DBG2_PWR16_MASK
+** DBG2 channel pwr16 ctrl mask bit
+** [3:3] SM_DBG3_PWR16_MASK
+** DBG3 channel pwr16 ctrl mask bit
+** [4:4] SM_DBG4_PWR16_MASK
+** DBG4 channel pwr16 ctrl mask bit
+** [5:5] SM_DBG5_PWR16_MASK
+** DBG5 channel pwr16 ctrl mask bit
+** [6:6] SM_DBG6_PWR16_MASK
+** DBG6 channel pwr16 ctrl mask bit
+** [7:7] SM_DBG7_PWR16_MASK
+** DBG7 channel pwr16 ctrl mask bit
+** [8:8] SM_DBG0_PWR17_MASK
+** DBG0 channel pwr17 ctrl mask bit
+** [9:9] SM_DBG1_PWR17_MASK
+** DBG1 channel pwr17 ctrl mask bit
+** [10:10] SM_DBG2_PWR17_MASK
+** DBG2 channel pwr17 ctrl mask bit
+** [11:11] SM_DBG3_PWR17_MASK
+** DBG3 channel pwr17 ctrl mask bit
+** [12:12] SM_DBG4_PWR17_MASK
+** DBG4 channel pwr17 ctrl mask bit
+** [13:13] SM_DBG5_PWR17_MASK
+** DBG5 channel pwr17 ctrl mask bit
+** [14:14] SM_DBG6_PWR17_MASK
+** DBG6 channel pwr17 ctrl mask bit
+** [15:15] SM_DBG7_PWR17_MASK
+** DBG7 channel pwr17 ctrl mask bit
+** [16:16] SM_DBG0_PWR18_MASK
+** DBG0 channel pwr18 ctrl mask bit
+** [17:17] SM_DBG1_PWR18_MASK
+** DBG1 channel pwr18 ctrl mask bit
+** [18:18] SM_DBG2_PWR18_MASK
+** DBG2 channel pwr18 ctrl mask bit
+** [19:19] SM_DBG3_PWR18_MASK
+** DBG3 channel pwr18 ctrl mask bit
+** [20:20] SM_DBG4_PWR18_MASK
+** DBG4 channel pwr18 ctrl mask bit
+** [21:21] SM_DBG5_PWR18_MASK
+** DBG5 channel pwr18 ctrl mask bit
+** [22:22] SM_DBG6_PWR18_MASK
+** DBG6 channel pwr18 ctrl mask bit
+** [23:23] SM_DBG7_PWR18_MASK
+** DBG7 channel pwr18 ctrl mask bit
+** [24:24] SM_DBG0_PWR19_MASK
+** DBG0 channel pwr19 ctrl mask bit
+** [25:25] SM_DBG1_PWR19_MASK
+** DBG1 channel pwr19 ctrl mask bit
+** [26:26] SM_DBG2_PWR19_MASK
+** DBG2 channel pwr19 ctrl mask bit
+** [27:27] SM_DBG3_PWR19_MASK
+** DBG3 channel pwr19 ctrl mask bit
+** [28:28] SM_DBG4_PWR19_MASK
+** DBG4 channel pwr19 ctrl mask bit
+** [29:29] SM_DBG5_PWR19_MASK
+** DBG5 channel pwr19 ctrl mask bit
+** [30:30] SM_DBG6_PWR19_MASK
+** DBG6 channel pwr19 ctrl mask bit
+** [31:31] SM_DBG7_PWR19_MASK
+** DBG7 channel pwr19 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PWR_MASK4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0350))
+/*=========================================
+** DBG channel pwr ctrl mask bit:
+** DBG channel pwr ctrl mask bit
+** [0:0] SM_DBG0_PWR20_MASK
+** DBG0 channel pwr20 ctrl mask bit
+** [1:1] SM_DBG1_PWR20_MASK
+** DBG1 channel pwr20 ctrl mask bit
+** [2:2] SM_DBG2_PWR20_MASK
+** DBG2 channel pwr20 ctrl mask bit
+** [3:3] SM_DBG3_PWR20_MASK
+** DBG3 channel pwr20 ctrl mask bit
+** [4:4] SM_DBG4_PWR20_MASK
+** DBG4 channel pwr20 ctrl mask bit
+** [5:5] SM_DBG5_PWR20_MASK
+** DBG5 channel pwr20 ctrl mask bit
+** [6:6] SM_DBG6_PWR20_MASK
+** DBG6 channel pwr20 ctrl mask bit
+** [7:7] SM_DBG7_PWR20_MASK
+** DBG7 channel pwr20 ctrl mask bit
+** [8:8] SM_DBG0_PWR21_MASK
+** DBG0 channel pwr21 ctrl mask bit
+** [9:9] SM_DBG1_PWR21_MASK
+** DBG1 channel pwr21 ctrl mask bit
+** [10:10] SM_DBG2_PWR21_MASK
+** DBG2 channel pwr21 ctrl mask bit
+** [11:11] SM_DBG3_PWR21_MASK
+** DBG3 channel pwr21 ctrl mask bit
+** [12:12] SM_DBG4_PWR21_MASK
+** DBG4 channel pwr21 ctrl mask bit
+** [13:13] SM_DBG5_PWR21_MASK
+** DBG5 channel pwr21 ctrl mask bit
+** [14:14] SM_DBG6_PWR21_MASK
+** DBG6 channel pwr21 ctrl mask bit
+** [15:15] SM_DBG7_PWR21_MASK
+** DBG7 channel pwr21 ctrl mask bit
+** [16:16] SM_DBG0_PWR22_MASK
+** DBG0 channel pwr22 ctrl mask bit
+** [17:17] SM_DBG1_PWR22_MASK
+** DBG1 channel pwr22 ctrl mask bit
+** [18:18] SM_DBG2_PWR22_MASK
+** DBG2 channel pwr22 ctrl mask bit
+** [19:19] SM_DBG3_PWR22_MASK
+** DBG3 channel pwr22 ctrl mask bit
+** [20:20] SM_DBG4_PWR22_MASK
+** DBG4 channel pwr22 ctrl mask bit
+** [21:21] SM_DBG5_PWR22_MASK
+** DBG5 channel pwr22 ctrl mask bit
+** [22:22] SM_DBG6_PWR22_MASK
+** DBG6 channel pwr22 ctrl mask bit
+** [23:23] SM_DBG7_PWR22_MASK
+** DBG7 channel pwr22 ctrl mask bit
+** [24:24] SM_DBG0_PWR23_MASK
+** DBG0 channel pwr23 ctrl mask bit
+** [25:25] SM_DBG1_PWR23_MASK
+** DBG1 channel pwr23 ctrl mask bit
+** [26:26] SM_DBG2_PWR23_MASK
+** DBG2 channel pwr23 ctrl mask bit
+** [27:27] SM_DBG3_PWR23_MASK
+** DBG3 channel pwr23 ctrl mask bit
+** [28:28] SM_DBG4_PWR23_MASK
+** DBG4 channel pwr23 ctrl mask bit
+** [29:29] SM_DBG5_PWR23_MASK
+** DBG5 channel pwr23 ctrl mask bit
+** [30:30] SM_DBG6_PWR23_MASK
+** DBG6 channel pwr23 ctrl mask bit
+** [31:31] SM_DBG7_PWR23_MASK
+** DBG7 channel pwr23 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PWR_MASK5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0354))
+/*=========================================
+** DBG channel mas trigger ctrl mask bit:
+** DBG channel mas trigger ctrl mask bit
+** [0:0] SM_DBG0_MAS_TRIG0_MASK
+** DBG0 channel mas trigger channel0 ctrl mask bit
+** [1:1] SM_DBG1_MAS_TRIG0_MASK
+** DBG1 channel mas trigger channel0 ctrl mask bit
+** [2:2] SM_DBG2_MAS_TRIG0_MASK
+** DBG2 channel mas trigger channel0 ctrl mask bit
+** [3:3] SM_DBG3_MAS_TRIG0_MASK
+** DBG3 channel mas trigger channel0 ctrl mask bit
+** [4:4] SM_DBG4_MAS_TRIG0_MASK
+** DBG4 channel mas trigger channel0 ctrl mask bit
+** [5:5] SM_DBG5_MAS_TRIG0_MASK
+** DBG5 channel mas trigger channel0 ctrl mask bit
+** [6:6] SM_DBG6_MAS_TRIG0_MASK
+** DBG6 channel mas trigger channel0 ctrl mask bit
+** [7:7] SM_DBG7_MAS_TRIG0_MASK
+** DBG7 channel mas trigger channel0 ctrl mask bit
+** [8:8] SM_DBG0_MAS_TRIG1_MASK
+** DBG0 channel mas trigger channel1 ctrl mask bit
+** [9:9] SM_DBG1_MAS_TRIG1_MASK
+** DBG1 channel mas trigger channel1 ctrl mask bit
+** [10:10] SM_DBG2_MAS_TRIG1_MASK
+** DBG2 channel mas trigger channel1 ctrl mask bit
+** [11:11] SM_DBG3_MAS_TRIG1_MASK
+** DBG3 channel mas trigger channel1 ctrl mask bit
+** [12:12] SM_DBG4_MAS_TRIG1_MASK
+** DBG4 channel mas trigger channel1 ctrl mask bit
+** [13:13] SM_DBG5_MAS_TRIG1_MASK
+** DBG5 channel mas trigger channel1 ctrl mask bit
+** [14:14] SM_DBG6_MAS_TRIG1_MASK
+** DBG6 channel mas trigger channel1 ctrl mask bit
+** [15:15] SM_DBG7_MAS_TRIG1_MASK
+** DBG7 channel mas trigger channel1 ctrl mask bit
+** [16:16] SM_DBG0_MAS_TRIG2_MASK
+** DBG0 channel mas trigger channel2 ctrl mask bit
+** [17:17] SM_DBG1_MAS_TRIG2_MASK
+** DBG1 channel mas trigger channel2 ctrl mask bit
+** [18:18] SM_DBG2_MAS_TRIG2_MASK
+** DBG2 channel mas trigger channel2 ctrl mask bit
+** [19:19] SM_DBG3_MAS_TRIG2_MASK
+** DBG3 channel mas trigger channel2 ctrl mask bit
+** [20:20] SM_DBG4_MAS_TRIG2_MASK
+** DBG4 channel mas trigger channel2 ctrl mask bit
+** [21:21] SM_DBG5_MAS_TRIG2_MASK
+** DBG5 channel mas trigger channel2 ctrl mask bit
+** [22:22] SM_DBG6_MAS_TRIG2_MASK
+** DBG6 channel mas trigger channel2 ctrl mask bit
+** [23:23] SM_DBG7_MAS_TRIG2_MASK
+** DBG7 channel mas trigger channel2 ctrl mask bit
+** [24:24] SM_DBG0_MAS_TRIG3_MASK
+** DBG0 channel mas trigger channel3 ctrl mask bit
+** [25:25] SM_DBG1_MAS_TRIG3_MASK
+** DBG1 channel mas trigger channel3 ctrl mask bit
+** [26:26] SM_DBG2_MAS_TRIG3_MASK
+** DBG2 channel mas trigger channel3 ctrl mask bit
+** [27:27] SM_DBG3_MAS_TRIG3_MASK
+** DBG3 channel mas trigger channel3 ctrl mask bit
+** [28:28] SM_DBG4_MAS_TRIG3_MASK
+** DBG4 channel mas trigger channel3 ctrl mask bit
+** [29:29] SM_DBG5_MAS_TRIG3_MASK
+** DBG5 channel mas trigger channel3 ctrl mask bit
+** [30:30] SM_DBG6_MAS_TRIG3_MASK
+** DBG6 channel mas trigger channel3 ctrl mask bit
+** [31:31] SM_DBG7_MAS_TRIG3_MASK
+** DBG7 channel mas trigger channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0360))
+/*=========================================
+** DBG channel mas trigger ctrl mask bit:
+** DBG channel mas trigger ctrl mask bit
+** [0:0] SM_DBG0_MAS_TRIG4_MASK
+** DBG0 channel mas trigger channel4 ctrl mask bit
+** [1:1] SM_DBG1_MAS_TRIG4_MASK
+** DBG1 channel mas trigger channel4 ctrl mask bit
+** [2:2] SM_DBG2_MAS_TRIG4_MASK
+** DBG2 channel mas trigger channel4 ctrl mask bit
+** [3:3] SM_DBG3_MAS_TRIG4_MASK
+** DBG3 channel mas trigger channel4 ctrl mask bit
+** [4:4] SM_DBG4_MAS_TRIG4_MASK
+** DBG4 channel mas trigger channel4 ctrl mask bit
+** [5:5] SM_DBG5_MAS_TRIG4_MASK
+** DBG5 channel mas trigger channel4 ctrl mask bit
+** [6:6] SM_DBG6_MAS_TRIG4_MASK
+** DBG6 channel mas trigger channel4 ctrl mask bit
+** [7:7] SM_DBG7_MAS_TRIG4_MASK
+** DBG7 channel mas trigger channel4 ctrl mask bit
+** [8:8] SM_DBG0_MAS_TRIG5_MASK
+** DBG0 channel mas trigger channel5 ctrl mask bit
+** [9:9] SM_DBG1_MAS_TRIG5_MASK
+** DBG1 channel mas trigger channel5 ctrl mask bit
+** [10:10] SM_DBG2_MAS_TRIG5_MASK
+** DBG2 channel mas trigger channel5 ctrl mask bit
+** [11:11] SM_DBG3_MAS_TRIG5_MASK
+** DBG3 channel mas trigger channel5 ctrl mask bit
+** [12:12] SM_DBG4_MAS_TRIG5_MASK
+** DBG4 channel mas trigger channel5 ctrl mask bit
+** [13:13] SM_DBG5_MAS_TRIG5_MASK
+** DBG5 channel mas trigger channel5 ctrl mask bit
+** [14:14] SM_DBG6_MAS_TRIG5_MASK
+** DBG6 channel mas trigger channel5 ctrl mask bit
+** [15:15] SM_DBG7_MAS_TRIG5_MASK
+** DBG7 channel mas trigger channel5 ctrl mask bit
+** [16:16] SM_DBG0_MAS_TRIG6_MASK
+** DBG0 channel mas trigger channel6 ctrl mask bit
+** [17:17] SM_DBG1_MAS_TRIG6_MASK
+** DBG1 channel mas trigger channel6 ctrl mask bit
+** [18:18] SM_DBG2_MAS_TRIG6_MASK
+** DBG2 channel mas trigger channel6 ctrl mask bit
+** [19:19] SM_DBG3_MAS_TRIG6_MASK
+** DBG3 channel mas trigger channel6 ctrl mask bit
+** [20:20] SM_DBG4_MAS_TRIG6_MASK
+** DBG4 channel mas trigger channel6 ctrl mask bit
+** [21:21] SM_DBG5_MAS_TRIG6_MASK
+** DBG5 channel mas trigger channel6 ctrl mask bit
+** [22:22] SM_DBG6_MAS_TRIG6_MASK
+** DBG6 channel mas trigger channel6 ctrl mask bit
+** [23:23] SM_DBG7_MAS_TRIG6_MASK
+** DBG7 channel mas trigger channel6 ctrl mask bit
+** [24:24] SM_DBG0_MAS_TRIG7_MASK
+** DBG0 channel mas trigger channel7 ctrl mask bit
+** [25:25] SM_DBG1_MAS_TRIG7_MASK
+** DBG1 channel mas trigger channel7 ctrl mask bit
+** [26:26] SM_DBG2_MAS_TRIG7_MASK
+** DBG2 channel mas trigger channel7 ctrl mask bit
+** [27:27] SM_DBG3_MAS_TRIG7_MASK
+** DBG3 channel mas trigger channel7 ctrl mask bit
+** [28:28] SM_DBG4_MAS_TRIG7_MASK
+** DBG4 channel mas trigger channel7 ctrl mask bit
+** [29:29] SM_DBG5_MAS_TRIG7_MASK
+** DBG5 channel mas trigger channel7 ctrl mask bit
+** [30:30] SM_DBG6_MAS_TRIG7_MASK
+** DBG6 channel mas trigger channel7 ctrl mask bit
+** [31:31] SM_DBG7_MAS_TRIG7_MASK
+** DBG7 channel mas trigger channel7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0364))
+/*=========================================
+** DBG channel timer trigger ctrl mask bit:
+** DBG channel timer trigger ctrl mask bit
+** [0:0] SM_DBG0_TIMER_TRIG0_MASK
+** DBG0 channel timer trigger channel0 ctrl mask bit
+** [1:1] SM_DBG1_TIMER_TRIG0_MASK
+** DBG1 channel timer trigger channel0 ctrl mask bit
+** [2:2] SM_DBG2_TIMER_TRIG0_MASK
+** DBG2 channel timer trigger channel0 ctrl mask bit
+** [3:3] SM_DBG3_TIMER_TRIG0_MASK
+** DBG3 channel timer trigger channel0 ctrl mask bit
+** [4:4] SM_DBG4_TIMER_TRIG0_MASK
+** DBG4 channel timer trigger channel0 ctrl mask bit
+** [5:5] SM_DBG5_TIMER_TRIG0_MASK
+** DBG5 channel timer trigger channel0 ctrl mask bit
+** [6:6] SM_DBG6_TIMER_TRIG0_MASK
+** DBG6 channel timer trigger channel0 ctrl mask bit
+** [7:7] SM_DBG7_TIMER_TRIG0_MASK
+** DBG7 channel timer trigger channel0 ctrl mask bit
+** [8:8] SM_DBG0_TIMER_TRIG1_MASK
+** DBG0 channel timer trigger channel1 ctrl mask bit
+** [9:9] SM_DBG1_TIMER_TRIG1_MASK
+** DBG1 channel timer trigger channel1 ctrl mask bit
+** [10:10] SM_DBG2_TIMER_TRIG1_MASK
+** DBG2 channel timer trigger channel1 ctrl mask bit
+** [11:11] SM_DBG3_TIMER_TRIG1_MASK
+** DBG3 channel timer trigger channel1 ctrl mask bit
+** [12:12] SM_DBG4_TIMER_TRIG1_MASK
+** DBG4 channel timer trigger channel1 ctrl mask bit
+** [13:13] SM_DBG5_TIMER_TRIG1_MASK
+** DBG5 channel timer trigger channel1 ctrl mask bit
+** [14:14] SM_DBG6_TIMER_TRIG1_MASK
+** DBG6 channel timer trigger channel1 ctrl mask bit
+** [15:15] SM_DBG7_TIMER_TRIG1_MASK
+** DBG7 channel timer trigger channel1 ctrl mask bit
+** [16:16] SM_DBG0_TIMER_TRIG2_MASK
+** DBG0 channel timer trigger channel2 ctrl mask bit
+** [17:17] SM_DBG1_TIMER_TRIG2_MASK
+** DBG1 channel timer trigger channel2 ctrl mask bit
+** [18:18] SM_DBG2_TIMER_TRIG2_MASK
+** DBG2 channel timer trigger channel2 ctrl mask bit
+** [19:19] SM_DBG3_TIMER_TRIG2_MASK
+** DBG3 channel timer trigger channel2 ctrl mask bit
+** [20:20] SM_DBG4_TIMER_TRIG2_MASK
+** DBG4 channel timer trigger channel2 ctrl mask bit
+** [21:21] SM_DBG5_TIMER_TRIG2_MASK
+** DBG5 channel timer trigger channel2 ctrl mask bit
+** [22:22] SM_DBG6_TIMER_TRIG2_MASK
+** DBG6 channel timer trigger channel2 ctrl mask bit
+** [23:23] SM_DBG7_TIMER_TRIG2_MASK
+** DBG7 channel timer trigger channel2 ctrl mask bit
+** [24:24] SM_DBG0_TIMER_TRIG3_MASK
+** DBG0 channel timer trigger channel3 ctrl mask bit
+** [25:25] SM_DBG1_TIMER_TRIG3_MASK
+** DBG1 channel timer trigger channel3 ctrl mask bit
+** [26:26] SM_DBG2_TIMER_TRIG3_MASK
+** DBG2 channel timer trigger channel3 ctrl mask bit
+** [27:27] SM_DBG3_TIMER_TRIG3_MASK
+** DBG3 channel timer trigger channel3 ctrl mask bit
+** [28:28] SM_DBG4_TIMER_TRIG3_MASK
+** DBG4 channel timer trigger channel3 ctrl mask bit
+** [29:29] SM_DBG5_TIMER_TRIG3_MASK
+** DBG5 channel timer trigger channel3 ctrl mask bit
+** [30:30] SM_DBG6_TIMER_TRIG3_MASK
+** DBG6 channel timer trigger channel3 ctrl mask bit
+** [31:31] SM_DBG7_TIMER_TRIG3_MASK
+** DBG7 channel timer trigger channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0370))
+/*=========================================
+** DBG channel timer trigger ctrl mask bit:
+** DBG channel timer trigger ctrl mask bit
+** [0:0] SM_DBG0_TIMER_TRIG4_MASK
+** DBG0 channel timer trigger channel4 ctrl mask bit
+** [1:1] SM_DBG1_TIMER_TRIG4_MASK
+** DBG1 channel timer trigger channel4 ctrl mask bit
+** [2:2] SM_DBG2_TIMER_TRIG4_MASK
+** DBG2 channel timer trigger channel4 ctrl mask bit
+** [3:3] SM_DBG3_TIMER_TRIG4_MASK
+** DBG3 channel timer trigger channel4 ctrl mask bit
+** [4:4] SM_DBG4_TIMER_TRIG4_MASK
+** DBG4 channel timer trigger channel4 ctrl mask bit
+** [5:5] SM_DBG5_TIMER_TRIG4_MASK
+** DBG5 channel timer trigger channel4 ctrl mask bit
+** [6:6] SM_DBG6_TIMER_TRIG4_MASK
+** DBG6 channel timer trigger channel4 ctrl mask bit
+** [7:7] SM_DBG7_TIMER_TRIG4_MASK
+** DBG7 channel timer trigger channel4 ctrl mask bit
+** [8:8] SM_DBG0_TIMER_TRIG5_MASK
+** DBG0 channel timer trigger channel5 ctrl mask bit
+** [9:9] SM_DBG1_TIMER_TRIG5_MASK
+** DBG1 channel timer trigger channel5 ctrl mask bit
+** [10:10] SM_DBG2_TIMER_TRIG5_MASK
+** DBG2 channel timer trigger channel5 ctrl mask bit
+** [11:11] SM_DBG3_TIMER_TRIG5_MASK
+** DBG3 channel timer trigger channel5 ctrl mask bit
+** [12:12] SM_DBG4_TIMER_TRIG5_MASK
+** DBG4 channel timer trigger channel5 ctrl mask bit
+** [13:13] SM_DBG5_TIMER_TRIG5_MASK
+** DBG5 channel timer trigger channel5 ctrl mask bit
+** [14:14] SM_DBG6_TIMER_TRIG5_MASK
+** DBG6 channel timer trigger channel5 ctrl mask bit
+** [15:15] SM_DBG7_TIMER_TRIG5_MASK
+** DBG7 channel timer trigger channel5 ctrl mask bit
+** [16:16] SM_DBG0_TIMER_TRIG2_MASK
+** DBG0 channel timer trigger channel6 ctrl mask bit
+** [17:17] SM_DBG1_TIMER_TRIG6_MASK
+** DBG1 channel timer trigger channel6 ctrl mask bit
+** [18:18] SM_DBG2_TIMER_TRIG6_MASK
+** DBG2 channel timer trigger channel6 ctrl mask bit
+** [19:19] SM_DBG3_TIMER_TRIG6_MASK
+** DBG3 channel timer trigger channel6 ctrl mask bit
+** [20:20] SM_DBG4_TIMER_TRIG6_MASK
+** DBG4 channel timer trigger channel6 ctrl mask bit
+** [21:21] SM_DBG5_TIMER_TRIG6_MASK
+** DBG5 channel timer trigger channel6 ctrl mask bit
+** [22:22] SM_DBG6_TIMER_TRIG6_MASK
+** DBG6 channel timer trigger channel6 ctrl mask bit
+** [23:23] SM_DBG7_TIMER_TRIG6_MASK
+** DBG7 channel timer trigger channel6 ctrl mask bit
+** [24:24] SM_DBG0_TIMER_TRIG7_MASK
+** DBG0 channel timer trigger channel7 ctrl mask bit
+** [25:25] SM_DBG1_TIMER_TRIG7_MASK
+** DBG1 channel timer trigger channel7 ctrl mask bit
+** [26:26] SM_DBG2_TIMER_TRIG7_MASK
+** DBG2 channel timer trigger channel7 ctrl mask bit
+** [27:27] SM_DBG3_TIMER_TRIG7_MASK
+** DBG3 channel timer trigger channel7 ctrl mask bit
+** [28:28] SM_DBG4_TIMER_TRIG7_MASK
+** DBG4 channel timer trigger channel7 ctrl mask bit
+** [29:29] SM_DBG5_TIMER_TRIG7_MASK
+** DBG5 channel timer trigger channel7 ctrl mask bit
+** [30:30] SM_DBG6_TIMER_TRIG7_MASK
+** DBG6 channel timer trigger channel7 ctrl mask bit
+** [31:31] SM_DBG7_TIMER_TRIG7_MASK
+** DBG7 channel timer trigger channel7 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0374))
+/*=========================================
+** DBG channel client active ctrl mask bit:
+** DBG channel client active ctrl mask bit
+** [0:0] SM_DBG0_CLIENT_ACT0_MASK
+** DBG0 channel client active channel0 ctrl mask bit
+** [1:1] SM_DBG1_CLIENT_ACT0_MASK
+** DBG1 channel client active channel0 ctrl mask bit
+** [2:2] SM_DBG2_CLIENT_ACT0_MASK
+** DBG2 channel client active channel0 ctrl mask bit
+** [3:3] SM_DBG3_CLIENT_ACT0_MASK
+** DBG3 channel client active channel0 ctrl mask bit
+** [4:4] SM_DBG4_CLIENT_ACT0_MASK
+** DBG4 channel client active channel0 ctrl mask bit
+** [5:5] SM_DBG5_CLIENT_ACT0_MASK
+** DBG5 channel client active channel0 ctrl mask bit
+** [6:6] SM_DBG6_CLIENT_ACT0_MASK
+** DBG6 channel client active channel0 ctrl mask bit
+** [7:7] SM_DBG7_CLIENT_ACT0_MASK
+** DBG7 channel client active channel0 ctrl mask bit
+** [8:8] SM_DBG0_CLIENT_ACT1_MASK
+** DBG0 channel client active channel1 ctrl mask bit
+** [9:9] SM_DBG1_CLIENT_ACT1_MASK
+** DBG1 channel client active channel1 ctrl mask bit
+** [10:10] SM_DBG2_CLIENT_ACT1_MASK
+** DBG2 channel client active channel1 ctrl mask bit
+** [11:11] SM_DBG3_CLIENT_ACT1_MASK
+** DBG3 channel client active channel1 ctrl mask bit
+** [12:12] SM_DBG4_CLIENT_ACT1_MASK
+** DBG4 channel client active channel1 ctrl mask bit
+** [13:13] SM_DBG5_CLIENT_ACT1_MASK
+** DBG5 channel client active channel1 ctrl mask bit
+** [14:14] SM_DBG6_CLIENT_ACT1_MASK
+** DBG6 channel client active channel1 ctrl mask bit
+** [15:15] SM_DBG7_CLIENT_ACT1_MASK
+** DBG7 channel client active channel1 ctrl mask bit
+** [16:16] SM_DBG0_CLIENT_ACT2_MASK
+** DBG0 channel client active channel2 ctrl mask bit
+** [17:17] SM_DBG1_CLIENT_ACT2_MASK
+** DBG1 channel client active channel2 ctrl mask bit
+** [18:18] SM_DBG2_CLIENT_ACT2_MASK
+** DBG2 channel client active channel2 ctrl mask bit
+** [19:19] SM_DBG3_CLIENT_ACT2_MASK
+** DBG3 channel client active channel2 ctrl mask bit
+** [20:20] SM_DBG4_CLIENT_ACT2_MASK
+** DBG4 channel client active channel2 ctrl mask bit
+** [21:21] SM_DBG5_CLIENT_ACT2_MASK
+** DBG5 channel client active channel2 ctrl mask bit
+** [22:22] SM_DBG6_CLIENT_ACT2_MASK
+** DBG6 channel client active channel2 ctrl mask bit
+** [23:23] SM_DBG7_CLIENT_ACT2_MASK
+** DBG7 channel client active channel2 ctrl mask bit
+** [24:24] SM_DBG0_CLIENT_ACT3_MASK
+** DBG0 channel client active channel3 ctrl mask bit
+** [25:25] SM_DBG1_CLIENT_ACT3_MASK
+** DBG1 channel client active channel3 ctrl mask bit
+** [26:26] SM_DBG2_CLIENT_ACT3_MASK
+** DBG2 channel client active channel3 ctrl mask bit
+** [27:27] SM_DBG3_CLIENT_ACT3_MASK
+** DBG3 channel client active channel3 ctrl mask bit
+** [28:28] SM_DBG4_CLIENT_ACT3_MASK
+** DBG4 channel client active channel3 ctrl mask bit
+** [29:29] SM_DBG5_CLIENT_ACT3_MASK
+** DBG5 channel client active channel3 ctrl mask bit
+** [30:30] SM_DBG6_CLIENT_ACT3_MASK
+** DBG6 channel client active channel3 ctrl mask bit
+** [31:31] SM_DBG7_CLIENT_ACT3_MASK
+** DBG7 channel client active channel3 ctrl mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0380))
+/*=========================================
+** DBG channel FSM status:
+** DBG channel FSM status
+** 0000001: Normal stage
+** 0000010: MTOFF stage
+** 0000100: PAUSE stage
+** 0001000: PRE_PAUSE stage
+** 0010000: SYSCLK_SETTLE stage
+** 0100000: CCP_SETTLE stage
+** 1000000: MTON stage
+** [6:0] SM_DBG0_SSTA
+** DBG0 channel FSM status
+** [14:8] SM_DBG1_SSTA
+** DBG1 channel FSM status
+** [22:16] SM_DBG2_SSTA
+** DBG2 channel FSM status
+** [30:24] SM_DBG3_SSTA
+** DBG3 channel FSM status
+**=========================================*/
+#define MD_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x03A0))
+/*=========================================
+** DBG channel FSM status:
+** DBG channel FSM status
+** 0000001: Normal stage
+** 0000010: MTOFF stage
+** 0000100: PAUSE stage
+** 0001000: PRE_PAUSE stage
+** 0010000: SYSCLK_SETTLE stage
+** 0100000: CCP_SETTLE stage
+** 1000000: MTON stage
+** [6:0] SM_DBG4_SSTA
+** DBG4 channel FSM status
+** [14:8] SM_DBG5_SSTA
+** DBG5 channel FSM status
+** [22:16] SM_DBG6_SSTA
+** DBG6 channel FSM status
+** [30:24] SM_DBG7_SSTA
+** DBG7 channel FSM status
+**=========================================*/
+#define MD_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x03A4))
+/*=========================================
+** Clock Settling Setting:
+** Notes:
+** If there is no two stage PLL, SM_PLL_SETTLE = max(each pll settle time)
+** Otherewise, SM_PLL_SETTLE = max of 1th + max of 2th stage pll settle time
+** [8:0] SM_SYSCLK_SETTLE
+** System clock settling time by F32K_CK cycles. Max = 508 cycles
+** All topsm sysclk settling time must be the same.
+** [20:16] SM_PLL_SETTLE
+** PLL settling time by F32k_CK cycles.
+**=========================================*/
+#define MD_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0400))
+/*=========================================
+** Timer trigger settle time:
+** Application: TIMER channel do pause complete and trigger another timer to wakeup during wakeup time
+** [7:0] SM_TIMER_TRIG_SETTLE
+** Timer trigger settle time
+**=========================================*/
+#define MD_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0410))
+/*=========================================
+** The maximum of mas trigger settle time:
+** Specify the maximum value among each mas trigger settle time (in SM_MAS_TRIG_GRP_SETTLE)
+** [7:0] SM_MAS_TRIG_MAX_SETTLE
+** The maximum of mas trigger settle time
+**=========================================*/
+#define MD_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0418))
+/*=========================================
+** mas trigger settle time for each channel:
+** Specify mas trigger settle time for each channel
+** [7:0] SM_MAS_TRIG0_SETTLE
+** mas trigger settle time for channel0
+** [15:8] SM_MAS_TRIG1_SETTLE
+** mas trigger settle time for channel1
+** [23:16] SM_MAS_TRIG2_SETTLE
+** mas trigger settle time for channel2
+** [31:24] SM_MAS_TRIG3_SETTLE
+** mas trigger settle time for channel3
+**=========================================*/
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0420))
+/*=========================================
+** mas trigger settle time for each channel:
+** Specify mas trigger settle time for each channel
+** [7:0] SM_MAS_TRIG4_SETTLE
+** mas trigger settle time for channel0
+** [15:8] SM_MAS_TRIG5_SETTLE
+** mas trigger settle time for channel1
+** [23:16] SM_MAS_TRIG6_SETTLE
+** mas trigger settle time for channel2
+** [31:24] SM_MAS_TRIG7_SETTLE
+** mas trigger settle time for channel3
+**=========================================*/
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0424))
+/*=========================================
+** mas trigger SAL value for each channel:
+** Specify Sampling ack latency for each channel
+** [7:0] SM_MAS_TRIG0_SAL
+** mas trigger SAL value for channel0, Min = 1
+** [15:8] SM_MAS_TRIG1_SAL
+** mas trigger SAL value for channel1, Min = 1
+** [23:16] SM_MAS_TRIG2_SAL
+** mas trigger SAL value for channel2, Min = 1
+** [31:24] SM_MAS_TRIG3_SAL
+** mas trigger SAL value for channel3, Min = 1
+**=========================================*/
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0430))
+/*=========================================
+** mas trigger SAL value for each channel:
+** Specify Sampling ack latency for each channel
+** [7:0] SM_MAS_TRIG4_SAL
+** mas trigger SAL value for channel0, Min = 1
+** [15:8] SM_MAS_TRIG5_SAL
+** mas trigger SAL value for channel1, Min = 1
+** [23:16] SM_MAS_TRIG6_SAL
+** mas trigger SAL value for channel2, Min = 1
+** [31:24] SM_MAS_TRIG7_SAL
+** mas trigger SAL value for channel3, Min = 1
+**=========================================*/
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0434))
+/*=========================================
+** mas trigger channel selection:
+** Application: If the corresponding bit is set 1, mas trigger channel settle time is ignored when pause interrupt happen
+** [0:0] SM_TMR0_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER0 channel , the settle time of mas trigger channels are all ignored
+** [1:1] SM_TMR1_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER1 channel , the settle time of mas trigger channels are all ignored
+** [2:2] SM_TMR2_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER2 channel , the settle time of mas trigger channels are all ignored
+** [3:3] SM_TMR3_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER3 channel , the settle time of mas trigger channels are all ignored
+** [4:4] SM_TMR4_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER4 channel , the settle time of mas trigger channels are all ignored
+** [5:5] SM_TMR5_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER5 channel , the settle time of mas trigger channels are all ignored
+** [6:6] SM_TMR6_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER6 channel , the settle time of mas trigger channels are all ignored
+** [7:7] SM_TMR7_MAS_TRIG_SEL
+** When pause interrupt happening @TIMER7 channel , the settle time of mas trigger channels are all ignored
+** [8:8] SM_SLV0_MAS_TRIG_SEL
+** When pause interrupt happening @SLV0 channel , the settle time of mas trigger channels are all ignored
+** [9:9] SM_SLV1_MAS_TRIG_SEL
+** When pause interrupt happening @SLV1 channel , the settle time of mas trigger channels are all ignored
+** [10:10] SM_SLV2_MAS_TRIG_SEL
+** When pause interrupt happening @SLV2 channel , the settle time of mas trigger channels are all ignored
+** [11:11] SM_SLV3_MAS_TRIG_SEL
+** When pause interrupt happening @SLV3 channel , the settle time of mas trigger channels are all ignored
+** [12:12] SM_SLV4_MAS_TRIG_SEL
+** When pause interrupt happening @SLV4 channel , the settle time of mas trigger channels are all ignored
+** [13:13] SM_SLV5_MAS_TRIG_SEL
+** When pause interrupt happening @SLV5 channel , the settle time of mas trigger channels are all ignored
+** [14:14] SM_SLV6_MAS_TRIG_SEL
+** When pause interrupt happening @SLV6 channel , the settle time of mas trigger channels are all ignored
+** [15:15] SM_SLV7_MAS_TRIG_SEL
+** When pause interrupt happening @SLV7 channel , the settle time of mas trigger channels are all ignored
+** [16:16] SM_DBG0_MAS_TRIG_SEL
+** When pause interrupt happening @DBG0 channel , the settle time of mas trigger channels are all ignored
+** [17:17] SM_DBG1_MAS_TRIG_SEL
+** When pause interrupt happening @DBG1 channel , the settle time of mas trigger channels are all ignored
+** [18:18] SM_DBG2_MAS_TRIG_SEL
+** When pause interrupt happening @DBG2 channel , the settle time of mas trigger channels are all ignored
+** [19:19] SM_DBG3_MAS_TRIG_SEL
+** When pause interrupt happening @DBG3 channel , the settle time of mas trigger channels are all ignored
+** [20:20] SM_DBG4_MAS_TRIG_SEL
+** When pause interrupt happening @DBG4 channel , the settle time of mas trigger channels are all ignored
+** [21:21] SM_DBG5_MAS_TRIG_SEL
+** When pause interrupt happening @DBG5 channel , the settle time of mas trigger channels are all ignored
+** [22:22] SM_DBG6_MAS_TRIG_SEL
+** When pause interrupt happening @DBG6 channel , the settle time of mas trigger channels are all ignored
+** [23:23] SM_DBG7_MAS_TRIG_SEL
+** When pause interrupt happening @DBG7 channel , the settle time of mas trigger channels are all ignored
+**=========================================*/
+#define MD_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0440))
+/*=========================================
+** TMR channel for sw trigger mode:
+** TMR channel for SW trigger mode.
+** This application is only active when corresponding mask bit in SM_TMR_REQ_MASK is tie 1
+** 0: enter sleep,
+** 1: trigger wakeup
+** It's not available to dynamiccally trigger this register 0->1 or 1->0.
+** [0:0] TMR0_SW_TRIG
+** TMR0 channel triggered by SW is only available when SM_TMR_REQ_MASK[0] is 1
+** [1:1] TMR1_SW_TRIG
+** TMR1 channel triggered by SW is only available when SM_TMR_REQ_MASK[1] is 1
+** [2:2] TMR2_SW_TRIG
+** TMR2 channel triggered by SW is only available when SM_TMR_REQ_MASK[2] is 1
+** [3:3] TMR3_SW_TRIG
+** TMR3 channel triggered by SW is only available when SM_TMR_REQ_MASK[3] is 1
+** [4:4] TMR4_SW_TRIG
+** TMR4 channel triggered by SW is only available when SM_TMR_REQ_MASK[4] is 1
+** [5:5] TMR5_SW_TRIG
+** TMR5 channel triggered by SW is only available when SM_TMR_REQ_MASK[5] is 1
+** [6:6] TMR6_SW_TRIG
+** TMR6 channel triggered by SW is only available when SM_TMR_REQ_MASK[6] is 1
+** [7:7] TMR7_SW_TRIG
+** TMR7 channel triggered by SW is only available when SM_TMR_REQ_MASK[7] is 1
+**=========================================*/
+#define MD_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0450))
+/*=========================================
+** SLV channel for sw trigger mode:
+** SLV channel for SW trigger mode.
+** This application is only active when corresponding mask bit in SM_SLV_REQ_MASK is tie 1
+** 0: enter sleep,
+** 1: trigger wakeup
+** when to check ready bit:
+** When trigger 0->1, after waiging 33us to check ready bit
+** (When to trigger turn off: must confirm the req is on & ready bit is on)
+** [0:0] SLV0_SW_TRIG
+** SLV0 channel triggered by SW is only available when SM_SLV_REQ_MASK[0] is 1
+** [1:1] SLV1_SW_TRIG
+** SLV1 channel triggered by SW is only available when SM_SLV_REQ_MASK[1] is 1
+** [2:2] SLV2_SW_TRIG
+** SLV2 channel triggered by SW is only available when SM_SLV_REQ_MASK[2] is 1
+** [3:3] SLV3_SW_TRIG
+** SLV3 channel triggered by SW is only available when SM_SLV_REQ_MASK[3] is 1
+** [4:4] SLV4_SW_TRIG
+** SLV4 channel triggered by SW is only available when SM_SLV_REQ_MASK[4] is 1
+** [5:5] SLV5_SW_TRIG
+** SLV5 channel triggered by SW is only available when SM_SLV_REQ_MASK[5] is 1
+** [6:6] SLV6_SW_TRIG
+** SLV6 channel triggered by SW is only available when SM_SLV_REQ_MASK[6] is 1
+** [7:7] SLV7_SW_TRIG
+** SLV7 channel triggered by SW is only available when SM_SLV_REQ_MASK[7] is 1
+**=========================================*/
+#define MD_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0454))
+/*=========================================
+** DBG channel for sw trigger mode:
+** SLV channel for SW trigger mode.
+** This application is only active when corresponding mask bit in SM_SLV_REQ_MASK is tie 1
+** 0: enter sleep,
+** 1: trigger wakeup
+** when to check ready bit:
+** When trigger 0->1, after waiging 33us to check ready bit
+** (When to trigger turn off: must confirm the req is on & ready bit is on)
+** [0:0] DBG0_SW_TRIG
+** DBG0 channel triggered by SW is only available when SM_DBG_REQ_MASK[0] is 1
+** [1:1] DBG1_SW_TRIG
+** DBG1 channel triggered by SW is only available when SM_DBG_REQ_MASK[1] is 1
+** [2:2] DBG2_SW_TRIG
+** DBG2 channel triggered by SW is only available when SM_DBG_REQ_MASK[2] is 1
+** [3:3] DBG3_SW_TRIG
+** DBG3 channel triggered by SW is only available when SM_DBG_REQ_MASK[3] is 1
+** [4:4] DBG4_SW_TRIG
+** DBG4 channel triggered by SW is only available when SM_DBG_REQ_MASK[4] is 1
+** [5:5] DBG5_SW_TRIG
+** DBG5 channel triggered by SW is only available when SM_DBG_REQ_MASK[5] is 1
+** [6:6] DBG6_SW_TRIG
+** DBG6 channel triggered by SW is only available when SM_DBG_REQ_MASK[6] is 1
+** [7:7] DBG7_SW_TRIG
+** DBG7 channel triggered by SW is only available when SM_DBG_REQ_MASK[7] is 1
+**=========================================*/
+#define MD_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0458))
+/*=========================================
+** mas trigger channel for sw trigger mode:
+** mas trigger channel for SW trigger mode.
+** Mas trigger channel[0~3] are triggered by HW path OR SW path. (together trigger is ok)
+** Mas trigger channel[4~7] are triggered by SW path only.
+** [0:0] MAS0_SW_TRIG
+** mas trigger channel0 is also controlled by SW
+** [1:1] MAS1_SW_TRIG
+** mas trigger channel1 is also controlled by SW
+** [2:2] MAS2_SW_TRIG
+** mas trigger channel2 is also controlled by SW
+** [3:3] MAS3_SW_TRIG
+** mas trigger channel3 is also controlled by SW
+** [4:4] MAS4_SW_TRIG
+** mas trigger channel4 is only controlled by SW
+** [5:5] MAS5_SW_TRIG
+** mas trigger channel5 is only controlled by SW
+** [6:6] MAS6_SW_TRIG
+** mas trigger channel6 is only controlled by SW
+** [7:7] MAS7_SW_TRIG
+** mas trigger channel7 is only controlled by SW
+**=========================================*/
+#define MD_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x045C))
+/*=========================================
+** mas trigger channel for sw trigger mode:
+** ignore sysclk settle time for TIMER channel. It's used if TIMER channel trigger pause command but total pause duration is not necessary to includ sysclk settle time
+** [0:0] TMR0_BYPASS_SYSCLK
+** TMR channel0 bypass sysclk
+** [1:1] TMR1_BYPASS_SYSCLK
+** TMR channel1 bypass sysclk
+** [2:2] TMR2_BYPASS_SYSCLK
+** TMR channel2 bypass sysclk
+** [3:3] TMR3_BYPASS_SYSCLK
+** TMR channel3 bypass sysclk
+** [4:4] TMR4_BYPASS_SYSCLK
+** TMR channel4 bypass sysclk
+** [5:5] TMR5_BYPASS_SYSCLK
+** TMR channel5 bypass sysclk
+** [6:6] TMR6_BYPASS_SYSCLK
+** TMR channel6 bypass sysclk
+** [7:7] TMR7_BYPASS_SYSCLK
+** TMR channel7 bypass sysclk
+**=========================================*/
+#define MD_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0468))
+/*=========================================
+** SLV channel Interrupt:
+** SLV channel irq flag and irq mask bit
+** [0:0] SLV0_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV0 channel ready from low to high
+** [1:1] SLV1_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV1 channel ready from low to high
+** [2:2] SLV2_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV2 channel ready from low to high
+** [3:3] SLV3_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV3 channel ready from low to high
+** [4:4] SLV4_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV4 channel ready from low to high
+** [5:5] SLV5_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV5 channel ready from low to high
+** [6:6] SLV6_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV6 channel ready from low to high
+** [7:7] SLV7_INT_STA
+** 0: No interrupt
+** 1: Trigger SLV7 channel ready from low to high
+** [8:8] SLV0_INT_MASK
+** SLV0 channel interrupt mask bit
+** [9:9] SLV1_INT_MASK
+** SLV1 channel interrupt mask bit
+** [10:10] SLV2_INT_MASK
+** SLV2 channel interrupt mask bit
+** [11:11] SLV3_INT_MASK
+** SLV3 channel interrupt mask bit
+** [12:12] SLV4_INT_MASK
+** SLV4 channel interrupt mask bit
+** [13:13] SLV5_INT_MASK
+** SLV5 channel interrupt mask bit
+** [14:14] SLV6_INT_MASK
+** SLV6 channel interrupt mask bit
+** [15:15] SLV7_INT_MASK
+** SLV7 channel interrupt mask bit
+**=========================================*/
+#define MD_TOPSM_SM_SLV_REQ_IRQ ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0470))
+/*=========================================
+** DBG channel Interrupt:
+** DBG channel irq flag and irq mask bit
+** [0:0] DBG0_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG0 channel ready from low to high
+** [1:1] DBG1_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG1 channel ready from low to high
+** [2:2] DBG2_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG2 channel ready from low to high
+** [3:3] DBG3_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG3 channel ready from low to high
+** [4:4] DBG4_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG4 channel ready from low to high
+** [5:5] DBG5_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG5 channel ready from low to high
+** [6:6] DBG6_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG6 channel ready from low to high
+** [7:7] DBG7_INT_STA
+** 0: No interrupt
+** 1: Trigger DBG7 channel ready from low to high
+** [8:8] DBG0_INT_MASK
+** DBG0 channel interrupt mask bit
+** [9:9] DBG1_INT_MASK
+** DBG1 channel interrupt mask bit
+** [10:10] DBG2_INT_MASK
+** DBG2 channel interrupt mask bit
+** [11:11] DBG3_INT_MASK
+** DBG3 channel interrupt mask bit
+** [12:12] DBG4_INT_MASK
+** DBG4 channel interrupt mask bit
+** [13:13] DBG5_INT_MASK
+** DBG5 channel interrupt mask bit
+** [14:14] DBG6_INT_MASK
+** DBG6 channel interrupt mask bit
+** [15:15] DBG7_INT_MASK
+** DBG7 channel interrupt mask bit
+**=========================================*/
+#define MD_TOPSM_SM_DBG_REQ_IRQ ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0478))
+/*=========================================
+** mas trigger channel Interrupt:
+** mas_trig channel irq flag and irq mask bit
+** [0:0] MAS0_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel0 ready from low to high
+** [1:1] MAS1_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel1 ready from low to high
+** [2:2] MAS2_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel2 ready from low to high
+** [3:3] MAS3_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel3 ready from low to high
+** [4:4] MAS4_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel4 ready from low to high
+** [5:5] MAS5_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel5 ready from low to high
+** [6:6] MAS6_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel6 ready from low to high
+** [7:7] MAS7_INT_STA
+** 0: No interrupt
+** 1: Trigger mas trigger channel7 ready from low to high
+** [8:8] MAS0_INT_MASK
+** mas trigger channel0 interrupt mask bit
+** [9:9] MAS1_INT_MASK
+** mas trigger channel1 interrupt mask bit
+** [10:10] MAS2_INT_MASK
+** mas trigger channel2 interrupt mask bit
+** [11:11] MAS3_INT_MASK
+** mas trigger channel3 interrupt mask bit
+** [12:12] MAS4_INT_MASK
+** mas trigger channel4 interrupt mask bit
+** [13:13] MAS5_INT_MASK
+** mas trigger channel5 interrupt mask bit
+** [14:14] MAS6_INT_MASK
+** mas trigger channel6 interrupt mask bit
+** [15:15] MAS7_INT_MASK
+** mas trigger channel7 interrupt mask bit
+**=========================================*/
+#define MD_TOPSM_SM_MAS_REQ_IRQ ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0480))
+/*=========================================
+** sysclk force on:
+** sysclk force on
+** [0:0] SYSCLK_FORCE_ON
+** sysclk force on
+** [1:1] SYSCLK1_FORCE_ON
+** sysclk1 force on
+** [2:2] SYSCLK2_FORCE_ON
+** sysclk2 force on
+** [3:3] SYSCLK3_FORCE_ON
+** sysclk3 force on
+**=========================================*/
+#define MD_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04A0))
+/*=========================================
+** pll force on:
+** pll force on
+** [0:0] PLL0_FORCE_ON
+** pll0 force on
+** [1:1] PLL1_FORCE_ON
+** pll1 force on
+** [2:2] PLL2_FORCE_ON
+** pll2 force on
+** [3:3] PLL3_FORCE_ON
+** pll3 force on
+** [4:4] PLL4_FORCE_ON
+** pll4 force on
+** [5:5] PLL5_FORCE_ON
+** pll5 force on
+** [6:6] PLL6_FORCE_ON
+** pll6 force on
+** [7:7] PLL7_FORCE_ON
+** pll7 force on
+** [8:8] PLL8_FORCE_ON
+** pll8 force on
+** [9:9] PLL9_FORCE_ON
+** pll9 force on
+** [10:10] PLL10_FORCE_ON
+** pll10 force on
+** [11:11] PLL11_FORCE_ON
+** pll11 force on
+** [12:12] PLL12_FORCE_ON
+** pll12 force on
+** [13:13] PLL13_FORCE_ON
+** pll13 force on
+** [14:14] PLL14_FORCE_ON
+** pll14 force on
+** [15:15] PLL15_FORCE_ON
+** pll15 force on
+**=========================================*/
+#define MD_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04B0))
+/*=========================================
+** timer trigger channel force on:
+** timer trigger channel force on
+** [0:0] TIMER_TRIG0_FORCE_ON
+** timer tirgger channel0 force on
+** [1:1] TIMER_TRIG1_FORCE_ON
+** timer tirgger channel1 force on
+** [2:2] TIMER_TRIG2_FORCE_ON
+** timer tirgger channel2 force on
+** [3:3] TIMER_TRIG3_FORCE_ON
+** timer tirgger channel3 force on
+**=========================================*/
+#define MD_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04D0))
+/*=========================================
+** timer trigger channel force on:
+** client active channel force on
+** [0:0] CLIENT_ACT0_FORCE_ON
+** client active channel0 force on
+** [1:1] CLIENT_ACT1_FORCE_ON
+** client active channel1 force on
+** [2:2] CLIENT_ACT2_FORCE_ON
+** client active channel2 force on
+** [3:3] CLIENT_ACT3_FORCE_ON
+** client active channel3 force on
+**=========================================*/
+#define MD_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04E0))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR0_STATUS
+** pwr0 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0500))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR1_STATUS
+** pwr1 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0504))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR2_STATUS
+** pwr2 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0508))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR3_STATUS
+** pwr3 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x050C))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR4_STATUS
+** pwr4 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0510))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR5_STATUS
+** pwr5 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0514))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR6_STATUS
+** pwr6 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS6 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0518))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR7_STATUS
+** pwr7 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS7 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x051C))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR8_STATUS
+** pwr8 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS8 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0520))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR9_STATUS
+** pwr9 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS9 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0524))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR10_STATUS
+** pwr10 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS10 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0528))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR11_STATUS
+** pwr11 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS11 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x052C))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR12_STATUS
+** pwr12 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS12 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0530))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR13_STATUS
+** pwr13 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS13 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0534))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR14_STATUS
+** pwr14 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS14 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0538))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR15_STATUS
+** pwr15 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS15 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x053C))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR16_STATUS
+** pwr16 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS16 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0540))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR17_STATUS
+** pwr17 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS17 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0544))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR18_STATUS
+** pwr18 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS18 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0548))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR19_STATUS
+** pwr19 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS19 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x054C))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR20_STATUS
+** pwr20 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS20 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0550))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR21_STATUS
+** pwr21 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS21 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0554))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR22_STATUS
+** pwr22 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS22 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0558))
+/*=========================================
+** pwr status:
+** pwr status
+** [14:0] PWR23_STATUS
+** pwr23 status (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_STATUS23 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x055C))
+/*=========================================
+** sysclk status:
+** sysclk status
+** [0:0] SYSCLK_RDY
+** sysclk ready (usually for debug purpose)
+** [1:1] SYSCLK1_RDY
+** sysclk1 ready (usually for debug purpose)
+** [2:2] SYSCLK2_RDY
+** sysclk2 ready (usually for debug purpose)
+** [3:3] SYSCLK3_RDY
+** sysclk3 ready (usually for debug purpose)
+** [16:16] SYSCLK_REQ
+** sysclk request (usually for debug purpose)
+** [17:17] SYSCLK1_REQ
+** sysclk1 request (usually for debug purpose)
+** [18:18] SYSCLK2_REQ
+** sysclk2 request (usually for debug purpose)
+** [19:19] SYSCLK3_REQ
+** sysclk3 request (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0580))
+/*=========================================
+** pll status:
+** pll status
+** [0:0] PLL0_RDY
+** pll0 ready (usually for debug purpose)
+** [1:1] PLL1_RDY
+** pll1 ready (usually for debug purpose)
+** [2:2] PLL2_RDY
+** pll2 ready (usually for debug purpose)
+** [3:3] PLL3_RDY
+** pll3 ready (usually for debug purpose)
+** [4:4] PLL4_RDY
+** pll4 ready (usually for debug purpose)
+** [5:5] PLL5_RDY
+** pll5 ready (usually for debug purpose)
+** [6:6] PLL6_RDY
+** pll6 ready (usually for debug purpose)
+** [7:7] PLL7_RDY
+** pll7 ready (usually for debug purpose)
+** [8:8] PLL8_RDY
+** pll8 ready (usually for debug purpose)
+** [9:9] PLL9_RDY
+** pll9 ready (usually for debug purpose)
+** [10:10] PLL10_RDY
+** pll10 ready (usually for debug purpose)
+** [11:11] PLL11_RDY
+** pll11 ready (usually for debug purpose)
+** [12:12] PLL12_RDY
+** pll12 ready (usually for debug purpose)
+** [13:13] PLL13_RDY
+** pll13 ready (usually for debug purpose)
+** [14:14] PLL14_RDY
+** pll14 ready (usually for debug purpose)
+** [15:15] PLL15_RDY
+** pll15 ready (usually for debug purpose)
+** [16:16] PLL0_REQ
+** pll0 request (usually for debug purpose)
+** [17:17] PLL1_REQ
+** pll1 request (usually for debug purpose)
+** [18:18] PLL2_REQ
+** pll2 request (usually for debug purpose)
+** [19:19] PLL3_REQ
+** pll3 request (usually for debug purpose)
+** [20:20] PLL4_REQ
+** pll4 request (usually for debug purpose)
+** [21:21] PLL5_REQ
+** pll5 request (usually for debug purpose)
+** [22:22] PLL6_REQ
+** pll6 request (usually for debug purpose)
+** [23:23] PLL7_REQ
+** pll7 request (usually for debug purpose)
+** [24:24] PLL8_REQ
+** pll8 request (usually for debug purpose)
+** [25:25] PLL9_REQ
+** pll9 request (usually for debug purpose)
+** [26:26] PLL10_REQ
+** pll10 request (usually for debug purpose)
+** [27:27] PLL11_REQ
+** pll11 request (usually for debug purpose)
+** [28:28] PLL12_REQ
+** pll12 request (usually for debug purpose)
+** [29:29] PLL13_REQ
+** pll13 request (usually for debug purpose)
+** [30:30] PLL14_REQ
+** pll14 request (usually for debug purpose)
+** [31:31] PLL15_REQ
+** pll15 request (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0590))
+/*=========================================
+** pwr_req status:
+** pwr_req status
+** [0:0] PWR0_REQ
+** hw pwr0 request (usually for debug purpose)
+** [1:1] PWR1_REQ
+** hw pwr1 request (usually for debug purpose)
+** [2:2] PWR2_REQ
+** hw pwr2 request (usually for debug purpose)
+** [3:3] PWR3_REQ
+** hw pwr3 request (usually for debug purpose)
+** [4:4] PWR4_REQ
+** hw pwr4 request (usually for debug purpose)
+** [5:5] PWR5_REQ
+** hw pwr5 request (usually for debug purpose)
+** [6:6] PWR6_REQ
+** hw pwr6 request (usually for debug purpose)
+** [7:7] PWR7_REQ
+** hw pwr7 request (usually for debug purpose)
+** [8:8] PWR8_REQ
+** hw pwr8 request (usually for debug purpose)
+** [9:9] PWR9_REQ
+** hw pwr9 request (usually for debug purpose)
+** [10:10] PWR10_REQ
+** hw pwr10 request (usually for debug purpose)
+** [11:11] PWR11_REQ
+** hw pwr11 request (usually for debug purpose)
+** [12:12] PWR12_REQ
+** hw pwr12 request (usually for debug purpose)
+** [13:13] PWR13_REQ
+** hw pwr13 request (usually for debug purpose)
+** [14:14] PWR14_REQ
+** hw pwr14 request (usually for debug purpose)
+** [15:15] PWR15_REQ
+** hw pwr15 request (usually for debug purpose)
+** [16:16] PWR16_REQ
+** hw pwr16 request (usually for debug purpose)
+** [17:17] PWR17_REQ
+** hw pwr17 request (usually for debug purpose)
+** [18:18] PWR18_REQ
+** hw pwr18 request (usually for debug purpose)
+** [19:19] PWR19_REQ
+** hw pwr19 request (usually for debug purpose)
+** [20:20] PWR20_REQ
+** hw pwr20 request (usually for debug purpose)
+** [21:21] PWR21_REQ
+** hw pwr21 request (usually for debug purpose)
+** [22:22] PWR22_REQ
+** hw pwr22 request (usually for debug purpose)
+** [23:23] PWR23_REQ
+** hw pwr23 request (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05A0))
+/*=========================================
+** pwr_ack status:
+** pwr_ack status
+** [0:0] PWR0_ACK
+** pwr0 ack (usually for debug purpose)
+** [1:1] PWR1_ACK
+** pwr1 ack (usually for debug purpose)
+** [2:2] PWR2_ACK
+** pwr2 ack (usually for debug purpose)
+** [3:3] PWR3_ACK
+** pwr3 ack (usually for debug purpose)
+** [4:4] PWR4_ACK
+** pwr4 ack (usually for debug purpose)
+** [5:5] PWR5_ACK
+** pwr5 ack (usually for debug purpose)
+** [6:6] PWR6_ACK
+** pwr6 ack (usually for debug purpose)
+** [7:7] PWR7_ACK
+** pwr7 ack (usually for debug purpose)
+** [8:8] PWR8_ACK
+** pwr8 ack (usually for debug purpose)
+** [9:9] PWR9_ACK
+** pwr9 ack (usually for debug purpose)
+** [10:10] PWR10_ACK
+** pwr10 ack (usually for debug purpose)
+** [11:11] PWR11_ACK
+** pwr11 ack (usually for debug purpose)
+** [12:12] PWR12_ACK
+** pwr12 ack (usually for debug purpose)
+** [13:13] PWR13_ACK
+** pwr13 ack (usually for debug purpose)
+** [14:14] PWR14_ACK
+** pwr14 ack (usually for debug purpose)
+** [15:15] PWR15_ACK
+** pwr15 ack (usually for debug purpose)
+** [16:16] PWR16_ACK
+** pwr16 ack (usually for debug purpose)
+** [17:17] PWR17_ACK
+** pwr17 ack (usually for debug purpose)
+** [18:18] PWR18_ACK
+** pwr18 ack (usually for debug purpose)
+** [19:19] PWR19_ACK
+** pwr19 ack (usually for debug purpose)
+** [20:20] PWR20_ACK
+** pwr20 ack (usually for debug purpose)
+** [21:21] PWR21_ACK
+** pwr21 ack (usually for debug purpose)
+** [22:22] PWR22_ACK
+** pwr22 ack (usually for debug purpose)
+** [23:23] PWR23_ACK
+** pwr23 ack (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05A4))
+/*=========================================
+** SLV channel status:
+** SLV channel status
+** [0:0] SM_SLV0_RDY
+** SLV0 channel ready
+** [1:1] SM_SLV1_RDY
+** SLV1 channel ready
+** [2:2] SM_SLV2_RDY
+** SLV2 channel ready
+** [3:3] SM_SLV3_RDY
+** SLV3 channel ready
+** [4:4] SM_SLV4_RDY
+** SLV4 channel ready
+** [5:5] SM_SLV5_RDY
+** SLV5 channel ready
+** [6:6] SM_SLV6_RDY
+** SLV6 channel ready
+** [7:7] SM_SLV7_RDY
+** SLV7 channel ready
+** [16:16] SM_SLV0_REQ
+** SLV0 channel request (usually for debug purpose)
+** [17:17] SM_SLV1_REQ
+** SLV1 channel request (usually for debug purpose)
+** [18:18] SM_SLV2_REQ
+** SLV2 channel request (usually for debug purpose)
+** [19:19] SM_SLV3_REQ
+** SLV3 channel request (usually for debug purpose)
+** [20:20] SM_SLV4_REQ
+** SLV4 channel request (usually for debug purpose)
+** [21:21] SM_SLV5_REQ
+** SLV5 channel request (usually for debug purpose)
+** [22:22] SM_SLV6_REQ
+** SLV6 channel request (usually for debug purpose)
+** [23:23] SM_SLV7_REQ
+** SLV7 channel request (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05C0))
+/*=========================================
+** DBG channel status:
+** DBG channel status
+** [0:0] SM_DBG0_RDY
+** DBG0 channel ready
+** [1:1] SM_DBG1_RDY
+** DBG1 channel ready
+** [2:2] SM_DBG2_RDY
+** DBG2 channel ready
+** [3:3] SM_DBG3_RDY
+** DBG3 channel ready
+** [4:4] SM_DBG4_RDY
+** DBG4 channel ready
+** [5:5] SM_DBG5_RDY
+** DBG5 channel ready
+** [6:6] SM_DBG6_RDY
+** DBG6 channel ready
+** [7:7] SM_DBG7_RDY
+** DBG7 channel ready
+** [16:16] SM_DBG0_REQ
+** DBG0 channel request (usually for debug purpose)
+** [17:17] SM_DBG1_REQ
+** DBG1 channel request (usually for debug purpose)
+** [18:18] SM_DBG2_REQ
+** DBG2 channel request (usually for debug purpose)
+** [19:19] SM_DBG3_REQ
+** DBG3 channel request (usually for debug purpose)
+** [20:20] SM_DBG4_REQ
+** DBG4 channel request (usually for debug purpose)
+** [21:21] SM_DBG5_REQ
+** DBG5 channel request (usually for debug purpose)
+** [22:22] SM_DBG6_REQ
+** DBG6 channel request (usually for debug purpose)
+** [23:23] SM_DBG7_REQ
+** DBG7 channel request (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05D0))
+/*=========================================
+** mas trigger channel status:
+** mas trigger channel status
+** [0:0] SM_MAS0_RDY
+** mas trigger channel0 ready
+** [1:1] SM_MAS1_RDY
+** mas trigger channel1 ready
+** [2:2] SM_MAS2_RDY
+** mas trigger channel2 ready
+** [3:3] SM_MAS3_RDY
+** mas trigger channel3 ready
+** [16:16] SM_MAS0_REQ
+** mas trigger channel0 request (usually for debug purpose)
+** [17:17] SM_MAS1_REQ
+** mas trigger channel1 request (usually for debug purpose)
+** [18:18] SM_MAS2_REQ
+** mas trigger channel2 request (usually for debug purpose)
+** [19:19] SM_MAS3_REQ
+** mas trigger channel3 request (usually for debug purpose)
+**=========================================*/
+#define MD_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05E0))
+/*=========================================
+** topsm debug selection:
+** Specify the configurations for sw wrok around purpose, or for debug purpose application
+** [0:0] SC_FSM_EN_DBG
+** TIMER or DBG or SLV channels FSM Read enable
+** [1:1] CONFG_RESERVED1
+**
+** [2:2] CONFG_RESERVED2
+**
+** [3:3] CONFG_RESERVED3
+**
+** [4:4] FRC_SW_DBG
+** 0: normal operation
+** [5:5] FRC_SW_DISABLE_DBG
+** 0: normal operation
+** 1: FRC_CK always use f26m_ck
+** [6:6] SYSCLK_CK_DBG
+** 0: normal operation
+** 1: sysclk always force on in topsm
+** [7:7] CONFG_RESERVED7
+**
+** [8:8] PLLCLK_SEL_DBG
+** 0: normal operation
+** 1: pll request always trigger alig with sysclk request
+** [9:9] SW_TRIG_DBG
+** the synchronizer depth for mas trigger @sw trigger mode
+** 0: depth 1
+** 1: depth 2
+** [10:10] PWR_ON_DFF_DLY_DBG
+** 0: pwr on use delay cell (normal operation)
+** 1: pwr on bypass delay cell
+** [11:11] PWR_OFF_1T
+** 0: pwr off flow only cost 1T
+** 1: pwr off flow cost 2T
+** [12:12] CONFG_RESERVED12
+**
+** [15:13] PROBE_DBG
+** debug out signals selection
+** [16:16] SYSCLK_DLY_SEL
+** 0: sysclk_req goes low not delay
+** 1: sysclk _req goes low delay 1T_32K (for power off 3T application)
+** [17:17] PROTECT_ERR_LOCKEN
+** 0: normal operation
+** 1: when protect_rdy is 0 after specific time (general 30us) when power off, lock corresponding resource for the master and provide
+** flag for SW debug
+** [18:18] FRC_1MHZ_EN_DBG
+** 0: normal operation
+** 1: frc_slow_ck_en also refer to f32k_ck_sel
+** [19:19] PROT_END_N1T_SEL
+** This register is only available when PWR_OFF_1T is 0
+** 0: detect protect_rdy time is adjustable (bus_prot settle time)
+** 1: detect protect_rdy time is fixed after 1T_32K when protect_req asserting
+** [20:20] TIMER_TRIG_ERR_LOCK_SEL
+** 0: timer trigger is not forced on when the corresponding client is getting protect lock
+** 1: timer trigger will be forced on when the corresponding client is getting protect lock
+** [21:21] PWR_RDY_SEL
+** 0: pwr_rdy is 1 if the power stage is in PROT or PROT_WAIT or PWR_IS_ON, otherwise it will be 0
+** 1: pwr_rdy is 1 if the power stage is in PWR_IS_ON stage, otherwise it will be 0
+** [31:22] RESERVED
+**
+**=========================================*/
+#define MD_TOPSM_SM_TOPSM_CONFG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0600))
+/*=========================================
+** topsm spare register:
+** topsm spare register
+** [31:0] TOPSM_SPARE_REG
+** topsm spare register
+**=========================================*/
+#define MD_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0608))
+/*=========================================
+** MTCMOS Counter Base:
+**
+** [3:0] MCF_CNT_BASE
+**
+**=========================================*/
+#define MD_TOPSM_SM_TOPSM_MCF_CNT_BASE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x060C))
+/*=========================================
+** debug monitor purpose: sysclk frequency meter:
+** Specify the configurations for debug monitor @sysclk frequency meter
+** [9:0] DBGMON_SYSCLK_FM_1
+** debug monitor purpose: frequency meter configuration
+** [25:16] DBGMON_SYSCLK_FM_2
+** debug monitor purpose: frequency meter configuration
+**=========================================*/
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0610))
+/*=========================================
+** debug monitor purpose: sysclk frequency meter:
+** Specify the configurations for debug monitor @sysclk frequency meter
+** [0:0] DBGMON_SYSCLK_FM_EN
+** debug monitor purpose: frequency meter enable bit
+** [4:4] DBGMON_SYSCLK_FM_ERRCLR
+** debug monitor purpose: frequency meter error clear bit
+**=========================================*/
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0614))
+/*=========================================
+** debug monitor purpose: sysclk frequency meter:
+** Specify the flags for debug monitor @sysclk frequency meter
+** [0:0] F32K_CK_SEL
+** debug monitor purpose: f32k_ck_sel register bit
+** [1:1] DBGMON_SYSCLK_FM_ERR
+** debug monitor purpose: frequency meter error flag. When the 26m frequency (DBGMON_SYSCLK_FM_CNT) is greater than
+** DBGMON_SYSCLK_FM_2 or less than GMON_SYSCLK_FM_1 after sysclk_rdy is asserting, the error flag will be 1.
+** [25:16] DBGMON_SYSCLK_FM_CNT
+** debug monitor purpose: frequency meter counter
+**=========================================*/
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0618))
+/*=========================================
+** :
+**
+** [0:0] USIP0_REQ0
+** topsm general purpose register0 (register control)
+** [1:1] USIP0_REQ1
+** topsm general purpose register1 (register control)
+** [2:2] USIP0_REQ2
+** topsm general purpose register2 (register control)
+** [3:3] USIP0_REQ3
+** topsm general purpose register3 (register control)
+** [4:4] USIP0_REQ4
+** topsm general purpose register4 (register control)
+** [5:5] USIP0_REQ5
+** topsm general purpose register5 (register control)
+** [6:6] USIP0_REQ6
+** topsm general purpose register6 (register control)
+** [7:7] USIP0_REQ7
+** topsm general purpose register7 (register control)
+** [8:8] USIP1_REQ0
+** topsm general purpose register8 (register control)
+** [9:9] USIP1_REQ1
+** topsm general purpose register9 (register control)
+** [10:10] USIP1_REQ2
+** topsm general purpose register10 (register control)
+** [11:11] USIP1_REQ3
+** topsm general purpose register11 (register control)
+** [12:12] USIP1_REQ4
+** topsm general purpose register12 (register control)
+** [13:13] USIP1_REQ5
+** topsm general purpose register13 (register control)
+** [14:14] USIP1_REQ6
+** topsm general purpose register14 (register control)
+** [15:15] USIP1_REQ7
+** topsm general purpose register15 (register control)
+** [16:16] RESERVED16
+** topsm general purpose register16 (register control)
+** [17:17] RESERVED17
+** topsm general purpose register17 (register control)
+** [18:18] RESERVED18
+** topsm general purpose register18 (register control)
+** [19:19] RESERVED19
+** topsm general purpose register19 (register control)
+** [20:20] RESERVED20
+** topsm general purpose register20 (register control)
+** [21:21] RESERVED21
+** topsm general purpose register21 (register control)
+** [22:22] RESERVED22
+** topsm general purpose register22 (register control)
+** [23:23] RESERVED23
+** topsm general purpose register23 (register control)
+** [24:24] RESERVED24
+** topsm general purpose register24 (register control)
+** [25:25] RESERVED25
+** topsm general purpose register25 (register control)
+** [26:26] RESERVED26
+** topsm general purpose register26 (register control)
+** [27:27] RESERVED27
+** topsm general purpose register27 (register control)
+** [28:28] PERI_CHANNEL_MASK0
+** topsm general purpose register28 (register control)
+** [29:29] PERI_CHANNEL_MASK1
+** topsm general purpose register29 (register control)
+** [30:30] PERI_CHANNEL_MASK2
+** topsm general purpose register30 (register control)
+** [31:31] PERI_CHANNEL_MASK3
+** topsm general purpose register31 (register control)
+**=========================================*/
+#define MD_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0640))
+/*=========================================
+** :
+**
+** [0:0] USIP0_REQ0
+** topsm general purpose register0 (register control)
+** [1:1] USIP0_REQ1
+** topsm general purpose register1 (register control)
+** [2:2] USIP0_REQ2
+** topsm general purpose register2 (register control)
+** [3:3] USIP0_REQ3
+** topsm general purpose register3 (register control)
+** [4:4] USIP0_REQ4
+** topsm general purpose register4 (register control)
+** [5:5] USIP0_REQ5
+** topsm general purpose register5 (register control)
+** [6:6] USIP0_REQ6
+** topsm general purpose register6 (register control)
+** [7:7] USIP0_REQ7
+** topsm general purpose register7 (register control)
+** [8:8] USIP1_REQ0
+** topsm general purpose register8 (register control)
+** [9:9] USIP1_REQ1
+** topsm general purpose register9 (register control)
+** [10:10] USIP1_REQ2
+** topsm general purpose register10 (register control)
+** [11:11] USIP1_REQ3
+** topsm general purpose register11 (register control)
+** [12:12] USIP1_REQ4
+** topsm general purpose register12 (register control)
+** [13:13] USIP1_REQ5
+** topsm general purpose register13 (register control)
+** [14:14] USIP1_REQ6
+** topsm general purpose register14 (register control)
+** [15:15] USIP1_REQ7
+** topsm general purpose register15 (register control)
+** [16:16] RESERVED16
+** topsm general purpose register16 (register control)
+** [17:17] RESERVED17
+** topsm general purpose register17 (register control)
+** [18:18] RESERVED18
+** topsm general purpose register18 (register control)
+** [19:19] RESERVED19
+** topsm general purpose register19 (register control)
+** [20:20] RESERVED20
+** topsm general purpose register20 (register control)
+** [21:21] RESERVED21
+** topsm general purpose register21 (register control)
+** [22:22] RESERVED22
+** topsm general purpose register22 (register control)
+** [23:23] RESERVED23
+** topsm general purpose register23 (register control)
+** [24:24] RESERVED24
+** topsm general purpose register24 (register control)
+** [25:25] RESERVED25
+** topsm general purpose register25 (register control)
+** [26:26] RESERVED26
+** topsm general purpose register26 (register control)
+** [27:27] RESERVED27
+** topsm general purpose register27 (register control)
+** [28:28] PERI_CHANNEL_MASK0
+** topsm general purpose register28 (register control)
+** [29:29] PERI_CHANNEL_MASK1
+** topsm general purpose register29 (register control)
+** [30:30] PERI_CHANNEL_MASK2
+** topsm general purpose register30 (register control)
+** [31:31] PERI_CHANNEL_MASK3
+** topsm general purpose register31 (register control)
+**=========================================*/
+#define MD_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0644))
+/*=========================================
+** :
+**
+** [2:0] CORE0_DOMAIN_RDY_ST
+** topsm general purpose register (register read)
+** [3:3] SI_CORE0_PWR_REQ
+** topsm general purpose register (register read)
+** [5:4] CORE0_VDDOK_ST
+** topsm general purpose register (register read)
+** [7:6] RESERVED7_6
+** topsm general purpose register (register read)
+** [10:8] CORE1_DOMAIN_RDY_ST
+** topsm general purpose register (register read)
+** [11:11] SI_CORE1_PWR_REQ
+** topsm general purpose register (register read)
+** [13:12] CORE1_VDDOK_ST
+** topsm general purpose register (register read)
+** [15:14] RESERVED15_14
+** topsm general purpose register (register read)
+** [18:16] CM_DOMAIN_RDY_ST
+** topsm general purpose register (register read)
+** [19:19] SI_CM_PWR_REQ
+** topsm general purpose register (register read)
+** [21:20] CM_VDDOK_ST
+** topsm general purpose register (register read)
+** [23:22] RESERVED23_22
+** topsm general purpose register (register read)
+** [25:24] MDPERI_SLP_STATE
+** topsm general purpose register (register read)
+** [31:26] RESERVED31_26
+** topsm general purpose register (register read)
+**=========================================*/
+#define MD_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0670))
+/*=========================================
+** pwr protect error:
+** Notes:
+** For MTCMOS power on flow, pwr_protect time out value is 256T_26m. This bit will be set if time out happends. (usually last bus transition costs too long)
+** [0:0] PWR0_PWR_PROTECT_ERR
+** pwr0 pwr protect time out
+** [1:1] PWR1_PWR_PROTECT_ERR
+** pwr1 pwr protect time out
+** [2:2] PWR2_PWR_PROTECT_ERR
+** pwr2 pwr protect time out
+** [3:3] PWR3_PWR_PROTECT_ERR
+** pwr3 pwr protect time out
+** [4:4] PWR4_PWR_PROTECT_ERR
+** pwr4 pwr protect time out
+** [5:5] PWR5_PWR_PROTECT_ERR
+** pwr5 pwr protect time out
+** [6:6] PWR6_PWR_PROTECT_ERR
+** pwr6 pwr protect time out
+** [7:7] PWR7_PWR_PROTECT_ERR
+** pwr7 pwr protect time out
+** [8:8] PWR8_PWR_PROTECT_ERR
+** pwr8 pwr protect time out
+** [9:9] PWR9_PWR_PROTECT_ERR
+** pwr9 pwr protect time out
+** [10:10] PWR10_PWR_PROTECT_ERR
+** pwr10 pwr protect time out
+** [11:11] PWR11_PWR_PROTECT_ERR
+** pwr11 pwr protect time out
+** [12:12] PWR12_PWR_PROTECT_ERR
+** pwr12 pwr protect time out
+** [13:13] PWR13_PWR_PROTECT_ERR
+** pwr13 pwr protect time out
+** [14:14] PWR14_PWR_PROTECT_ERR
+** pwr14 pwr protect time out
+** [15:15] PWR15_PWR_PROTECT_ERR
+** pwr15 pwr protect time out
+** [16:16] PWR16_PWR_PROTECT_ERR
+** pwr16 pwr protect time out
+** [17:17] PWR17_PWR_PROTECT_ERR
+** pwr17 pwr protect time out
+** [18:18] PWR18_PWR_PROTECT_ERR
+** pwr18 pwr protect time out
+** [19:19] PWR19_PWR_PROTECT_ERR
+** pwr19 pwr protect time out
+** [20:20] PWR20_PWR_PROTECT_ERR
+** pwr20 pwr protect time out
+** [21:21] PWR21_PWR_PROTECT_ERR
+** pwr21 pwr protect time out
+** [22:22] PWR22_PWR_PROTECT_ERR
+** pwr22 pwr protect time out
+** [23:23] PWR23_PWR_PROTECT_ERR
+** pwr23 pwr protect time out
+**=========================================*/
+#define MD_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0680))
+/*=========================================
+** TIMER channel FSM error:
+** TIMER channel FSM error
+** [0:0] TMR0_FSM_ERROR0
+** TIMER0 sysclk settle time, time-out
+** [1:1] TMR0_FSM_ERROR1
+** TIMER0 pll settle time, time-out
+** [2:2] TMR0_FSM_ERROR2
+** TIMER0 mas trigger channel settle time, time-out
+** [3:3] TMR0_FSM_ERROR3
+** TIMER0 pwr settle time, time-out
+** [4:4] TMR0_FSM_ERROR4
+** TIMER0 channel interface protocol error
+** [8:8] TMR1_FSM_ERROR0
+** TIMER1 sysclk settle time, time-out
+** [9:9] TMR1_FSM_ERROR1
+** TIMER1 pll settle time, time-out
+** [10:10] TMR1_FSM_ERROR2
+** TIMER1 mas trigger channel settle time, time-out
+** [11:11] TMR1_FSM_ERROR3
+** TIMER1 pwr settle time, time-out
+** [12:12] TMR1_FSM_ERROR4
+** TIMER1 channel interface protocol error
+** [16:16] TMR2_FSM_ERROR0
+** TIMER2 sysclk settle time, time-out
+** [17:17] TMR2_FSM_ERROR1
+** TIMER2 pll settle time, time-out
+** [18:18] TMR2_FSM_ERROR2
+** TIMER2 mas trigger channel settle time, time-out
+** [19:19] TMR2_FSM_ERROR3
+** TIMER2 pwr settle time, time-out
+** [20:20] TMR2_FSM_ERROR4
+** TIMER2 channel interface protocol error
+** [24:24] TMR3_FSM_ERROR0
+** TIMER3 sysclk settle time, time-out
+** [25:25] TMR3_FSM_ERROR1
+** TIMER3 pll settle time, time-out
+** [26:26] TMR3_FSM_ERROR2
+** TIMER3 mas trigger channel settle time, time-out
+** [27:27] TMR3_FSM_ERROR3
+** TIMER3 pwr settle time, time-out
+** [28:28] TMR3_FSM_ERROR4
+** TIMER3 channel interface protocol error
+**=========================================*/
+#define MD_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0690))
+/*=========================================
+** TIMER channel FSM error:
+** TIMER channel FSM error
+** [0:0] TMR4_FSM_ERROR0
+** TIMER4 sysclk settle time, time-out
+** [1:1] TMR4_FSM_ERROR1
+** TIMER4 pll settle time, time-out
+** [2:2] TMR4_FSM_ERROR2
+** TIMER4 mas trigger channel settle time, time-out
+** [3:3] TMR4_FSM_ERROR3
+** TIMER4 pwr settle time, time-out
+** [4:4] TMR4_FSM_ERROR4
+** TIMER4 channel interface protocol error
+** [8:8] TMR5_FSM_ERROR0
+** TIMER5 sysclk settle time, time-out
+** [9:9] TMR5_FSM_ERROR1
+** TIMER5 pll settle time, time-out
+** [10:10] TMR5_FSM_ERROR2
+** TIMER5 mas trigger channel settle time, time-out
+** [11:11] TMR5_FSM_ERROR3
+** TIMER5 pwr settle time, time-out
+** [12:12] TMR5_FSM_ERROR4
+** TIMER5 channel interface protocol error
+** [16:16] TMR6_FSM_ERROR0
+** TIMER6 sysclk settle time, time-out
+** [17:17] TMR6_FSM_ERROR1
+** TIMER6 pll settle time, time-out
+** [18:18] TMR6_FSM_ERROR2
+** TIMER6 mas trigger channel settle time, time-out
+** [19:19] TMR6_FSM_ERROR3
+** TIMER6 pwr settle time, time-out
+** [20:20] TMR6_FSM_ERROR4
+** TIMER6 channel interface protocol error
+** [24:24] TMR7_FSM_ERROR0
+** TIMER7 sysclk settle time, time-out
+** [25:25] TMR7_FSM_ERROR1
+** TIMER7 pll settle time, time-out
+** [26:26] TMR7_FSM_ERROR2
+** TIMER7 mas trigger channel settle time, time-out
+** [27:27] TMR7_FSM_ERROR3
+** TIMER7 pwr settle time, time-out
+** [28:28] TMR7_FSM_ERROR4
+** TIMER7 channel interface protocol error
+**=========================================*/
+#define MD_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0694))
+/*=========================================
+** TIMER channel protect err flag:
+** TIMER channel protect err
+** [0:0] TMR0_PROT_ERR
+** TIMER0 channel protect err flag
+** [1:1] TMR1_PROT_ERR
+** TIMER1 channel protect err flag
+** [2:2] TMR2_PROT_ERR
+** TIMER2 channel protect err flag
+** [3:3] TMR3_PROT_ERR
+** TIMER3 channel protect err flag
+** [4:4] TMR4_PROT_ERR
+** TIMER4 channel protect err flag
+** [5:5] TMR5_PROT_ERR
+** TIMER5 channel protect err flag
+** [6:6] TMR6_PROT_ERR
+** TIMER6 channel protect err flag
+** [7:7] TMR7_PROT_ERR
+** TIMER7 channel protect err flag
+**=========================================*/
+#define MD_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0698))
+/*=========================================
+** SLV channel FSM error:
+** SLV channel FSM error
+** [0:0] SLV0_FSM_ERROR0
+** SLV0 sysclk settle time, time-out
+** [1:1] SLV0_FSM_ERROR1
+** SLV0 pll settle time, time-out
+** [2:2] SLV0_FSM_ERROR2
+** SLV0 mas trigger channel settle time, time-out
+** [3:3] SLV0_FSM_ERROR3
+** SLV0 pwr settle time, time-out
+** [4:4] SLV0_FSM_ERROR4
+** SLV0 channel interface protocol error
+** [8:8] SLV1_FSM_ERROR0
+** SLV1 sysclk settle time, time-out
+** [9:9] SLV1_FSM_ERROR1
+** SLV1 pll settle time, time-out
+** [10:10] SLV1_FSM_ERROR2
+** SLV1 mas trigger channel settle time, time-out
+** [11:11] SLV1_FSM_ERROR3
+** SLV1 pwr settle time, time-out
+** [12:12] SLV1_FSM_ERROR4
+** SLV1 channel interface protocol error
+** [16:16] SLV2_FSM_ERROR0
+** SLV2 sysclk settle time, time-out
+** [17:17] SLV2_FSM_ERROR1
+** SLV2 pll settle time, time-out
+** [18:18] SLV2_FSM_ERROR2
+** SLV2 mas trigger channel settle time, time-out
+** [19:19] SLV2_FSM_ERROR3
+** SLV2 pwr settle time, time-out
+** [20:20] SLV2_FSM_ERROR4
+** SLV2 channel interface protocol error
+** [24:24] SLV3_FSM_ERROR0
+** SLV3 sysclk settle time, time-out
+** [25:25] SLV3_FSM_ERROR1
+** SLV3 pll settle time, time-out
+** [26:26] SLV3_FSM_ERROR2
+** SLV3 mas trigger channel settle time, time-out
+** [27:27] SLV3_FSM_ERROR3
+** SLV3 pwr settle time, time-out
+** [28:28] SLV3_FSM_ERROR4
+** SLV3 channel interface protocol error
+**=========================================*/
+#define MD_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06a0))
+/*=========================================
+** SLV channel FSM error:
+** SLV channel FSM error
+** [0:0] SLV4_FSM_ERROR0
+** SLV4 sysclk settle time, time-out
+** [1:1] SLV4_FSM_ERROR1
+** SLV4 pll settle time, time-out
+** [2:2] SLV4_FSM_ERROR2
+** SLV4 mas trigger channel settle time, time-out
+** [3:3] SLV4_FSM_ERROR3
+** SLV4 pwr settle time, time-out
+** [4:4] SLV4_FSM_ERROR4
+** SLV4 channel interface protocol error
+** [8:8] SLV5_FSM_ERROR0
+** SLV5 sysclk settle time, time-out
+** [9:9] SLV5_FSM_ERROR1
+** SLV5 pll settle time, time-out
+** [10:10] SLV5_FSM_ERROR2
+** SLV5 mas trigger channel settle time, time-out
+** [11:11] SLV5_FSM_ERROR3
+** SLV5 pwr settle time, time-out
+** [12:12] SLV5_FSM_ERROR4
+** SLV5 channel interface protocol error
+** [16:16] SLV6_FSM_ERROR0
+** SLV6 sysclk settle time, time-out
+** [17:17] SLV6_FSM_ERROR1
+** SLV6 pll settle time, time-out
+** [18:18] SLV6_FSM_ERROR2
+** SLV6 mas trigger channel settle time, time-out
+** [19:19] SLV6_FSM_ERROR3
+** SLV6 pwr settle time, time-out
+** [20:20] SLV6_FSM_ERROR4
+** SLV6 channel interface protocol error
+** [24:24] SLV7_FSM_ERROR0
+** SLV7 sysclk settle time, time-out
+** [25:25] SLV7_FSM_ERROR1
+** SLV7 pll settle time, time-out
+** [26:26] SLV7_FSM_ERROR2
+** SLV7 mas trigger channel settle time, time-out
+** [27:27] SLV7_FSM_ERROR3
+** SLV7 pwr settle time, time-out
+** [28:28] SLV7_FSM_ERROR4
+** SLV7 channel interface protocol error
+**=========================================*/
+#define MD_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06a4))
+/*=========================================
+** SLV channel protect err flag:
+** SLV channel protect err
+** [0:0] SLV0_PROT_ERR
+** SLV0 channel protect err flag
+** [1:1] SLV1_PROT_ERR
+** SLV1 channel protect err flag
+** [2:2] SLV2_PROT_ERR
+** SLV2 channel protect err flag
+** [3:3] SLV3_PROT_ERR
+** SLV3 channel protect err flag
+** [4:4] SLV4_PROT_ERR
+** SLV4 channel protect err flag
+** [5:5] SLV5_PROT_ERR
+** SLV5 channel protect err flag
+** [6:6] SLV6_PROT_ERR
+** SLV6 channel protect err flag
+** [7:7] SLV7_PROT_ERR
+** SLV7 channel protect err flag
+**=========================================*/
+#define MD_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06a8))
+/*=========================================
+** DBG channel FSM error:
+** DBG channel FSM error
+** [0:0] DBG0_FSM_ERROR0
+** DBG0 sysclk settle time, time-out
+** [1:1] DBG0_FSM_ERROR1
+** DBG0 pll settle time, time-out
+** [2:2] DBG0_FSM_ERROR2
+** DBG0 mas trigger channel settle time, time-out
+** [3:3] DBG0_FSM_ERROR3
+** DBG0 pwr settle time, time-out
+** [4:4] DBG0_FSM_ERROR4
+** DBG0 channel interface protocol error
+** [8:8] DBG1_FSM_ERROR0
+** DBG1 sysclk settle time, time-out
+** [9:9] DBG1_FSM_ERROR1
+** DBG1 pll settle time, time-out
+** [10:10] DBG1_FSM_ERROR2
+** DBG1 mas trigger channel settle time, time-out
+** [11:11] DBG1_FSM_ERROR3
+** DBG1 pwr settle time, time-out
+** [12:12] DBG1_FSM_ERROR4
+** DBG1 channel interface protocol error
+** [16:16] DBG2_FSM_ERROR0
+** DBG2 sysclk settle time, time-out
+** [17:17] DBG2_FSM_ERROR1
+** DBG2 pll settle time, time-out
+** [18:18] DBG2_FSM_ERROR2
+** DBG2 mas trigger channel settle time, time-out
+** [19:19] DBG2_FSM_ERROR3
+** DBG2 pwr settle time, time-out
+** [20:20] DBG2_FSM_ERROR4
+** DBG2 channel interface protocol error
+** [24:24] DBG3_FSM_ERROR0
+** DBG3 sysclk settle time, time-out
+** [25:25] DBG3_FSM_ERROR1
+** DBG3 pll settle time, time-out
+** [26:26] DBG3_FSM_ERROR2
+** DBG3 mas trigger channel settle time, time-out
+** [27:27] DBG3_FSM_ERROR3
+** DBG3 pwr settle time, time-out
+** [28:28] DBG3_FSM_ERROR4
+** DBG3 channel interface protocol error
+**=========================================*/
+#define MD_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06b0))
+/*=========================================
+** DBG channel FSM error:
+** DBG channel FSM error
+** [0:0] DBG4_FSM_ERROR0
+** DBG4 sysclk settle time, time-out
+** [1:1] DBG4_FSM_ERROR1
+** DBG4 pll settle time, time-out
+** [2:2] DBG4_FSM_ERROR2
+** DBG4 mas trigger channel settle time, time-out
+** [3:3] DBG4_FSM_ERROR3
+** DBG4 pwr settle time, time-out
+** [4:4] DBG4_FSM_ERROR4
+** DBG4 channel interface protocol error
+** [8:8] DBG5_FSM_ERROR0
+** DBG5 sysclk settle time, time-out
+** [9:9] DBG5_FSM_ERROR1
+** DBG5 pll settle time, time-out
+** [10:10] DBG5_FSM_ERROR2
+** DBG5 mas trigger channel settle time, time-out
+** [11:11] DBG5_FSM_ERROR3
+** DBG5 pwr settle time, time-out
+** [12:12] DBG5_FSM_ERROR4
+** DBG5 channel interface protocol error
+** [16:16] DBG6_FSM_ERROR0
+** DBG6 sysclk settle time, time-out
+** [17:17] DBG6_FSM_ERROR1
+** DBG6 pll settle time, time-out
+** [18:18] DBG6_FSM_ERROR2
+** DBG6 mas trigger channel settle time, time-out
+** [19:19] DBG6_FSM_ERROR3
+** DBG6 pwr settle time, time-out
+** [20:20] DBG6_FSM_ERROR4
+** DBG6 channel interface protocol error
+** [24:24] DBG7_FSM_ERROR0
+** DBG7 sysclk settle time, time-out
+** [25:25] DBG7_FSM_ERROR1
+** DBG7 pll settle time, time-out
+** [26:26] DBG7_FSM_ERROR2
+** DBG7 mas trigger channel settle time, time-out
+** [27:27] DBG7_FSM_ERROR3
+** DBG7 pwr settle time, time-out
+** [28:28] DBG7_FSM_ERROR4
+** DBG7 channel interface protocol error
+**=========================================*/
+#define MD_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06b4))
+/*=========================================
+** DBG channel protect err flag:
+** DBG channel protect err
+** [0:0] DBG0_PROT_ERR
+** DBG0 channel protect err flag
+** [1:1] DBG1_PROT_ERR
+** DBG1 channel protect err flag
+** [2:2] DBG2_PROT_ERR
+** DBG2 channel protect err flag
+** [3:3] DBG3_PROT_ERR
+** DBG3 channel protect err flag
+** [4:4] DBG4_PROT_ERR
+** DBG4 channel protect err flag
+** [5:5] DBG5_PROT_ERR
+** DBG5 channel protect err flag
+** [6:6] DBG6_PROT_ERR
+** DBG6 channel protect err flag
+** [7:7] DBG7_PROT_ERR
+** DBG7 channel protect err flag
+**=========================================*/
+#define MD_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06b8))
+/*=========================================
+** FRC counter enable:
+** FRC counter enable
+** Notes:
+** Write 0xf2cc << 16 to update this register. Be sure to turn on FRC before using OS Timer function. Turn off FRC_CNT_EN will make system absolute time froze.
+** [0:0] FRC_CNT_EN
+** FRC counter enable
+**=========================================*/
+#define MD_TOPSM_FRC_CON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0800))
+/*=========================================
+** f32k frequency measurement:
+** Notes:
+** Using this register to update FRC_CNT when topsm is in sleep mode (count by each f32k)
+** [27:0] FRC_F32K_FM
+** f32k frequency measurement (used by FRC_CNT)
+**=========================================*/
+#define MD_TOPSM_FRC_F32K_FM ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0810))
+/*=========================================
+** the frame length for FRC counter:
+** the frame length for FRC counter
+** [15:0] FRC_FRAME_LEN
+** the frame length for FRC counter
+**=========================================*/
+#define MD_TOPSM_FRC_FRAME_LEN ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0820))
+/*=========================================
+** Current FRC value:
+** Current FRC value
+** [31:0] FRC_VAL_R
+** Current FRC value (lower part)
+**=========================================*/
+#define MD_TOPSM_FRC_VAL_R ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0830))
+/*=========================================
+** Current FRC value:
+** Current FRC value
+** [7:0] FRC_VAL_R_H
+** Current FRC value (upper part)
+**=========================================*/
+#define MD_TOPSM_FRC_VAL_R_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0834))
+/*=========================================
+** Current Timestamp value:
+** Current Timestamp value
+** [25:0] FRC_TIMESTAMP
+** Current Timestamp value
+**=========================================*/
+#define MD_TOPSM_FRC_TIMESTAMP ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0840))
+/*=========================================
+** free run f32k counter:
+** free run f32k counter
+** [31:0] F32K_CNT
+** free run f32k counter
+**=========================================*/
+#define MD_TOPSM_F32K_CNT ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0850))
+/*=========================================
+** timer sync status:
+** timer sync status
+** Notes: when source timer trigger timer_sync to topsm, topsm will store current FRC counter in corresponding TIMER_SYNC_VAL and trigger corresponding TIMER_SYNC_STATUS bit
+** [0:0] TIMER0_SYNC_STATUS
+** timer0 sync status (triggered from low to high)
+** [1:1] TIMER1_SYNC_STATUS
+** timer1 sync status (triggered from low to high)
+** [2:2] TIMER2_SYNC_STATUS
+** timer2 sync status (triggered from low to high)
+** [3:3] TIMER3_SYNC_STATUS
+** timer3 sync status (triggered from low to high)
+** [4:4] TIMER4_SYNC_STATUS
+** timer4 sync status (triggered from low to high)
+** [5:5] TIMER5_SYNC_STATUS
+** timer5 sync status (triggered from low to high)
+** [6:6] TIMER6_SYNC_STATUS
+** timer6 sync status (triggered from low to high)
+** [7:7] TIMER7_SYNC_STATUS
+** timer7 sync status (triggered from low to high)
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC_STATUS ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0860))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER0_SYNC_VALUE_L
+** timer0 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC0_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0880))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER0_SYNC_VALUE_H
+** timer0 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC0_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0884))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER1_SYNC_VALUE_L
+** timer1 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC1_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0888))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER1_SYNC_VALUE_H
+** timer1 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC1_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x088C))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER2_SYNC_VALUE_L
+** timer2 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC2_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0890))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER2_SYNC_VALUE_H
+** timer2 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC2_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0894))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER3_SYNC_VALUE_L
+** timer3 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC3_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0898))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER3_SYNC_VALUE_H
+** timer3 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC3_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x089C))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER4_SYNC_VALUE_L
+** timer4 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC4_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A0))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER4_SYNC_VALUE_H
+** timer4 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC4_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A4))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER5_SYNC_VALUE_L
+** timer5 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC5_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A8))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER5_SYNC_VALUE_H
+** timer5 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC5_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08AC))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER6_SYNC_VALUE_L
+** timer6 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC6_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B0))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER6_SYNC_VALUE_H
+** timer6 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC6_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B4))
+/*=========================================
+** timer sync value low:
+** time sync value fraction part
+** (unit: 1us)
+** [4:0] TIMER7_SYNC_VALUE_L
+** timer7 sync value fraction part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC7_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B8))
+/*=========================================
+** timer sync value high:
+** time sync value integer part
+** (unit: 1us)
+** [31:0] TIMER7_SYNC_VALUE_H
+** timer7 sync value integer part
+**=========================================*/
+#define MD_TOPSM_TIMER_SYNC7_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08BC))
+/*=========================================
+** gps sync value :
+** gps sync value
+** Notes: when FRC counter is equal as gps sync value, gps sync output signal (GPS_SYNC_CON1) will be triggered. The high pulse width is 5T_26m.
+** [31:0] GPS_SYNC_CON0
+** gps sync value
+**=========================================*/
+#define MD_TOPSM_GPS_SYNC_CON0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08E0))
+/*=========================================
+** gps sync output signal :
+** gps sync output signal
+** [31:31] GPS_SYNC_CON1
+** gps sync output signal
+**=========================================*/
+#define MD_TOPSM_GPS_SYNC_CON1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08E4))
+
+
+/*===========================================================================================================================
+** MDSM
+**===========================================================================================================================*/
+#define MDSM_CPC_CH0_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0000))
+#define MDSM_CPC_CH0_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0010))
+#define MDSM_CSC_CH_CORE_PAUSE_EN_W1E ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0020))
+#define MDSM_CSC_CH_CORE_PAUSE_EN_W1C ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0024))
+#define MDSM_CPC_CH_CORE_SEL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0030))
+#define MDSM_CPC_CH_ABORT_IRQ ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0040))
+#define MDSM_CPC_CH_WAKEUP_IRQ ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0044))
+#define MDSM_CPC_CH_ABORT_IRQ_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0048))
+#define MDSM_CPC_CH_WAKEUP_IRQ_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x004C))
+#define MDSM_CPC_CH_CORE_PWR_ST ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0050))
+#define MDSM_CPC_MDCMORE_CONFG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0080))
+#define MDSM_CPC_SPARE_REG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0090))
+#define MDSM_CPC_USIP0_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0100))
+#define MDSM_CPC_USIP0_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0110))
+#define MDSM_CPC_MDCORE_PROBE_ST0 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0200))
+#define MDSM_CPC_MDCORE_PROBE_ST1 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0204))
+#define MDSM_CPC_MDCORE_ERR_FLAG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0210))
+
+
+#define MD_RM_SYS_CLK_SETTLE (RM_SYS_CLK_SETTLE)
+#define RM_PLL_SETTLE (0x3)
+#define MD_MAS_TRIG_EMI_SETTLE (0x12)
+#define MD_MAS_TRIG_L1_COMM_SETTLE (0xE)
+#define MD_MAS_TRIG_MAX_SETTLE MAX(MD_MAS_TRIG_EMI_SETTLE, MD_MAS_TRIG_L1_COMM_SETTLE)
+#define MD_TIMER_TRIG_SETTLE (0x4)
+#define MD_MAS_TRIG_EMI_SAL (0xA)
+#define MD_MAS_TRIG_L1_COMM_SAL (0x4)
+/* Power settle is also included, this is the total settle time calculate by HW */
+#define MD_RM_RESOURCE_SETTLE (RM_SYS_CLK_SETTLE + 4 + MAX4(RM_PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 2 + 1)
+
+
+#elif defined(__MD95__)
+
+/*===========================================================================================================================
+** TOPSM
+**===========================================================================================================================*/
+#define MD_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0000)) //core0 //0x2503
+#define MD_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0004)) //core1 //0x2403
+#define MD_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0008)) //core2 //0x2303
+#define MD_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x000C)) //usip //0x2203
+#define MD_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0010)) //mdcore //0x1F03
+#define MD_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0014)) //cm2 //0x1D03
+#define MD_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0018)) //MML2 //0x1803
+#define MD_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0080))
+#define MD_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00A0))
+#define MD_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C0))
+#define MD_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C4))
+#define MD_TOPSM_SM_PWR_BYPASS_PROTECT_RDY ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C8))
+#define MD_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00D0))
+#define MD_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00D4))
+#define MD_TOPSM_SW_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00E0))
+#define MD_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0100))
+#define MD_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0108))
+#define MD_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0120))
+#define MD_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0124))
+#define MD_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0140))
+#define MD_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0144))
+#define MD_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0160))
+#define MD_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0170))
+#define MD_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0180))
+#define MD_TOPSM_SM_TMR_PRE_TRIG_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0190))
+#define MD_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x01A0))
+#define MD_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0200))
+#define MD_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0208))
+#define MD_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0220))
+#define MD_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0224))
+#define MD_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0240))
+#define MD_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0244))
+#define MD_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0260))
+#define MD_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0270))
+#define MD_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0280))
+#define MD_TOPSM_SM_SLV_PRE_TRIG_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0290))
+#define MD_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x02A0))
+#define MD_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x02A4))
+#define MD_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0300))
+#define MD_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0308))
+#define MD_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0320))
+#define MD_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0324))
+#define MD_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0340))
+#define MD_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0344))
+#define MD_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0360))
+#define MD_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0370))
+#define MD_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0380))
+#define MD_TOPSM_SM_DBG_PRE_TRIG_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0390))
+#define MD_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x03A0))
+#define MD_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x03A4))
+#define MD_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0400))
+#define MD_TOPSM_SM_PRE_TRIG_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0408))
+#define MD_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0410))
+#define MD_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0418))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0420))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0424))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0430))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0434))
+#define MD_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0440))
+#define MD_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0450))
+#define MD_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0454))
+#define MD_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0458))
+#define MD_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x045C))
+#define MD_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0468))
+#define MD_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04A0))
+#define MD_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04B0))
+#define MD_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04D0))
+#define MD_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04E0))
+#define MD_TOPSM_SW_PRE_TRIG_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04F0))
+#define MD_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0580))
+#define MD_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0590))
+#define MD_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05A0))
+#define MD_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05A4))
+#define MD_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05B0))
+#define MD_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05C0))
+#define MD_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05D0))
+#define MD_TOPSM_SM_CLIENT_ACK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05E0))
+#define MD_TOPSM_SM_PRE_TRIG_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05F0))
+#define MD_TOPSM_SM_TOPSM_CONFG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0600))
+#define MD_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0608))
+#define MD_TOPSM_SM_TOPSM_MCF_CNT_BASE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x060C))
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0610))
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0614))
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0618))
+#define MD_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0640))
+#define MD_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0644))
+#define MD_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0670))
+#define MD_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0680))
+#define MD_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0690))
+#define MD_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0694))
+#define MD_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0698))
+#define MD_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06A0))
+#define MD_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06A4))
+#define MD_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06A8))
+#define MD_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06B0))
+#define MD_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06B4))
+#define MD_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06B8))
+#define MD_TOPSM_FRC_CON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0800))
+#define MD_TOPSM_FRC_F32K_FM ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0810))
+#define MD_TOPSM_FRC_FRAME_LEN ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0820))
+#define MD_TOPSM_FRC_VAL_R ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0830))
+#define MD_TOPSM_FRC_VAL_R_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0834))
+#define MD_TOPSM_FRC_TIMESTAMP ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0840))
+#define MD_TOPSM_F32K_CNT ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0850))
+#define MD_TOPSM_TIMER_SYNC_STATUS ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0860))
+#define MD_TOPSM_TIMER_SYNC0_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0880))
+#define MD_TOPSM_TIMER_SYNC0_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0884))
+#define MD_TOPSM_TIMER_SYNC1_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0888))
+#define MD_TOPSM_TIMER_SYNC1_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x088C))
+#define MD_TOPSM_TIMER_SYNC2_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0890))
+#define MD_TOPSM_TIMER_SYNC2_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0894))
+#define MD_TOPSM_TIMER_SYNC3_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0898))
+#define MD_TOPSM_TIMER_SYNC3_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x089C))
+#define MD_TOPSM_TIMER_SYNC4_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A0))
+#define MD_TOPSM_TIMER_SYNC4_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A4))
+#define MD_TOPSM_TIMER_SYNC5_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A8))
+#define MD_TOPSM_TIMER_SYNC5_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08AC))
+#define MD_TOPSM_TIMER_SYNC6_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B0))
+#define MD_TOPSM_TIMER_SYNC6_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B4))
+#define MD_TOPSM_TIMER_SYNC7_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B8))
+#define MD_TOPSM_TIMER_SYNC7_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08BC))
+#define MD_TOPSM_GPS_SYNC_CON0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08E0))
+#define MD_TOPSM_GPS_SYNC_CON1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08E4))
+
+/*===========================================================================================================================
+** MDSM
+**===========================================================================================================================*/
+#define MDSM_CSC_CH0_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0000))
+#define MDSM_CSC_CH1_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0004))
+#define MDSM_CSC_CH2_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0008))
+#define MDSM_CSC_CH0_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0010))
+#define MDSM_CSC_CH1_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0014))
+#define MDSM_CSC_CH2_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0018))
+#define MDSM_CSC_CH_CORE_PAUSE_EN_W1E ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0020))
+#define MDSM_CSC_CH_CORE_PAUSE_EN_W1C ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0024))
+#define MDSM_CSC_CH_ABORT_IRQ ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0040))
+#define MDSM_CSC_CH_WAKEUP_IRQ ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0044))
+#define MDSM_CSC_CH_ABORT_IRQ_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0048))
+#define MDSM_CSC_CH_WAKEUP_IRQ_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x004C))
+#define MDSM_CSC_CH_CORE_PWR_ST ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0050))
+#define MDSM_CPC_MDCMORE_CONFG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0080))
+#define MDSM_CPC_SPARE_REG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0090))
+#define MDSM_CPC_USIP0_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0100))
+#define MDSM_CPC_USIP0_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0110))
+#define MDSM_CPC_MDCORE_PROBE_ST ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0200))
+#define MDSM_CPC_MDCORE_PROBE_ST1 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0204))
+#define MDSM_CPC_MDCORE_ERR_FLAG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0210))
+
+#define MD_RM_SYS_CLK_SETTLE (0x7C)
+#define MD_RM_PLL_SETTLE (0x2)
+#define MD_MAS_TRIG_EMI_SETTLE (0xE)
+#define MD_MAS_TRIG_L1_COMM_SETTLE (0xC)
+#define MD_MAS_TRIG_MAX_SETTLE MAX(MD_MAS_TRIG_EMI_SETTLE, MD_MAS_TRIG_L1_COMM_SETTLE)
+#define MD_PRE_TRIG_SETTLE (0x1)
+#define MD_TIMER_TRIG_SETTLE (0x4)
+#define MD_MAS_TRIG_EMI_SAL (0xC)
+#define MD_MAS_TRIG_L1_COMM_SAL (0x4)
+#define MD_MAX_PWR_SETTLE (0x3)
+/* Power settle is also included, this is the total settle time calculate by HW */
+#define MD_RM_RESOURCE_SETTLE (MD_PRE_TRIG_SETTLE + MD_RM_SYS_CLK_SETTLE + 4 + MAX4(MD_RM_PLL_SETTLE, MD_MAX_PWR_SETTLE, MD_MAS_TRIG_MAX_SETTLE, MD_TIMER_TRIG_SETTLE) + 2 + 3)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+/*===========================================================================================================================
+** TOPSM
+**===========================================================================================================================*/
+#define MD_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0000)) //core0_sh
+#define MD_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0004)) //core1_sh
+#define MD_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0008)) //core2_sh
+#define MD_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x000C)) //core3_sh
+#define MD_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0010)) //usip
+#define MD_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0014)) //mdcore
+#define MD_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0018)) //MML2
+#define MD_TOPSM_SM_PWR_CON7 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x001C)) //core0_ia
+#define MD_TOPSM_SM_PWR_CON8 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0020)) //core1_ia
+#define MD_TOPSM_SM_PWR_CON9 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0024)) //core2_ia
+#define MD_TOPSM_SM_PWR_CON10 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0028)) //core3_ia
+#define MD_TOPSM_SM_PWR_CON11 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x002C)) //cm
+#define MD_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0080))
+#define MD_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00A0))
+#define MD_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C0))
+#define MD_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C4))
+#define MD_TOPSM_SM_PWR_BYPASS_PROTECT_RDY ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00C8))
+#define MD_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00D0))
+#define MD_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00D4))
+#define MD_TOPSM_SW_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x00E0))
+#define MD_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0100))
+#define MD_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0108))
+#define MD_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0120))
+#define MD_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0124))
+#define MD_TOPSM_SM_TMR_PLL_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0128))
+#define MD_TOPSM_SM_TMR_PLL_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x012C))
+#define MD_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0140))
+#define MD_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0144))
+#define MD_TOPSM_SM_TMR_PWR_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0148))
+#define MD_TOPSM_SM_TMR_PWR_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x014C))
+#define MD_TOPSM_SM_TMR_PWR_MASK4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0150))
+#define MD_TOPSM_SM_TMR_PWR_MASK5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0154))
+#define MD_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0160))
+#define MD_TOPSM_SM_TMR_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0164))
+#define MD_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0170))
+#define MD_TOPSM_SM_TMR_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0174))
+#define MD_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0180))
+#define MD_TOPSM_SM_TMR_CLIENT_PRE_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0188))
+#define MD_TOPSM_SM_TMR_PRE_TRIG_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0190))
+#define MD_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x01A0))
+#define MD_TOPSM_SM_TMR_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x01A4))
+#define MD_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0200))
+#define MD_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0208))
+#define MD_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0220))
+#define MD_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0224))
+#define MD_TOPSM_SM_SLV_PLL_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0228))
+#define MD_TOPSM_SM_SLV_PLL_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x022C))
+#define MD_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0240))
+#define MD_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0244))
+#define MD_TOPSM_SM_SLV_PWR_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0248))
+#define MD_TOPSM_SM_SLV_PWR_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x024C))
+#define MD_TOPSM_SM_SLV_PWR_MASK4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0250))
+#define MD_TOPSM_SM_SLV_PWR_MASK5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0254))
+#define MD_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0260))
+#define MD_TOPSM_SM_SLV_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0264))
+#define MD_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0270))
+#define MD_TOPSM_SM_SLV_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0274))
+#define MD_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0280))
+#define MD_TOPSM_SM_SLV_CLIENT_PRE_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0288))
+#define MD_TOPSM_SM_SLV_PRE_TRIG_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0290))
+#define MD_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x02A0))
+#define MD_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x02A4))
+#define MD_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0300))
+#define MD_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0308))
+#define MD_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0320))
+#define MD_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0324))
+#define MD_TOPSM_SM_DBG_PLL_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0328))
+#define MD_TOPSM_SM_DBG_PLL_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x032C))
+#define MD_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0340))
+#define MD_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0344))
+#define MD_TOPSM_SM_DBG_PWR_MASK2 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0348))
+#define MD_TOPSM_SM_DBG_PWR_MASK3 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x034C))
+#define MD_TOPSM_SM_DBG_PWR_MASK4 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0350))
+#define MD_TOPSM_SM_DBG_PWR_MASK5 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0354))
+#define MD_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0360))
+#define MD_TOPSM_SM_DBG_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0364))
+#define MD_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0370))
+#define MD_TOPSM_SM_DBG_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0374))
+#define MD_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0380))
+#define MD_TOPSM_SM_DBG_CLIENT_PRE_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0388))
+#define MD_TOPSM_SM_DBG_PRE_TRIG_MASK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0390))
+#define MD_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x03A0))
+#define MD_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x03A4))
+#define MD_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0400))
+#define MD_TOPSM_SM_PRE_TRIG_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0408))
+#define MD_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0410))
+#define MD_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0418))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0420))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0424))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0430))
+#define MD_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0434))
+#define MD_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0440))
+#define MD_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0450))
+#define MD_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0454))
+#define MD_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0458))
+#define MD_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x045C))
+#define MD_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0468))
+#define MD_TOPSM_SM_SLV_REQ_IRQ ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0470))
+#define MD_TOPSM_SM_DBG_REQ_IRQ ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0478))
+#define MD_TOPSM_SM_MAS_REQ_IRQ ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0480))
+#define MD_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04A0))
+#define MD_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04B0))
+#define MD_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04D0))
+#define MD_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04E0))
+#define MD_TOPSM_SW_CLIENT_PRE_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04E8))
+#define MD_TOPSM_SW_PRE_TRIG_FORCE_ON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x04F0))
+#define MD_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0580))
+#define MD_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0590))
+#define MD_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05A0))
+#define MD_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05A4))
+#define MD_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05B0))
+#define MD_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05C0))
+#define MD_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05D0))
+#define MD_TOPSM_SM_CLIENT_ACK_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05E0))
+#define MD_TOPSM_SM_CLIENT_PRE_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05E8))
+#define MD_TOPSM_SM_PRE_TRIG_STA ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x05F0))
+#define MD_TOPSM_SM_TOPSM_CONFG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0600))
+#define MD_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0608))
+#define MD_TOPSM_SM_TOPSM_MCF_CNT_BASE ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x060C))
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0610))
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0614))
+#define MD_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0618))
+#define MD_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0640))
+#define MD_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0644))
+#define MD_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0670))
+#define MD_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0680))
+#define MD_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0690))
+#define MD_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0694))
+#define MD_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0698))
+#define MD_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06A0))
+#define MD_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06A4))
+#define MD_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06A8))
+#define MD_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06B0))
+#define MD_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06B4))
+#define MD_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x06B8))
+#define MD_TOPSM_FRC_CON ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0800))
+#define MD_TOPSM_FRC_F32K_FM ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0810))
+#define MD_TOPSM_FRC_FRAME_LEN ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0820))
+#define MD_TOPSM_FRC_VAL_R ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0830))
+#define MD_TOPSM_FRC_VAL_R_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0834))
+#define MD_TOPSM_FRC_TIMESTAMP ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0840))
+#define MD_TOPSM_F32K_CNT ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0850))
+#define MD_TOPSM_TIMER_SYNC_STATUS ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0860))
+#define MD_TOPSM_TIMER_SYNC0_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0880))
+#define MD_TOPSM_TIMER_SYNC0_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0884))
+#define MD_TOPSM_TIMER_SYNC1_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0888))
+#define MD_TOPSM_TIMER_SYNC1_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x088C))
+#define MD_TOPSM_TIMER_SYNC2_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0890))
+#define MD_TOPSM_TIMER_SYNC2_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0894))
+#define MD_TOPSM_TIMER_SYNC3_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x0898))
+#define MD_TOPSM_TIMER_SYNC3_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x089C))
+#define MD_TOPSM_TIMER_SYNC4_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A0))
+#define MD_TOPSM_TIMER_SYNC4_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A4))
+#define MD_TOPSM_TIMER_SYNC5_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08A8))
+#define MD_TOPSM_TIMER_SYNC5_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08AC))
+#define MD_TOPSM_TIMER_SYNC6_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B0))
+#define MD_TOPSM_TIMER_SYNC6_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B4))
+#define MD_TOPSM_TIMER_SYNC7_VAL_L ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08B8))
+#define MD_TOPSM_TIMER_SYNC7_VAL_H ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08BC))
+#define MD_TOPSM_GPS_SYNC_CON0 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08E0))
+#define MD_TOPSM_GPS_SYNC_CON1 ((volatile kal_uint32*)(MD_TOPSM_BASE + 0x08E4))
+
+/*===========================================================================================================================
+** MDSM
+**===========================================================================================================================*/
+#define MDSM_CSC_CH0_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0000))
+#define MDSM_CSC_CH1_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0004))
+#define MDSM_CSC_CH2_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0008))
+#define MDSM_CSC_CH3_CORE_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x000C))
+#define MDSM_CSC_CH0_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0010))
+#define MDSM_CSC_CH1_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0014))
+#define MDSM_CSC_CH2_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0018))
+#define MDSM_CSC_CH3_CORE_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x001C))
+#define MDSM_CSC_CH_CORE_PAUSE_EN_W1E ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0020))
+#define MDSM_CSC_CH_CORE_PAUSE_EN_W1C ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0024))
+#define MDSM_CSC_CH_ABORT_IRQ ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0040))
+#define MDSM_CSC_CH_WAKEUP_IRQ ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0044))
+#define MDSM_CSC_CH_ABORT_IRQ_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0048))
+#define MDSM_CSC_CH_WAKEUP_IRQ_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x004C))
+#define MDSM_CSC_CH_CORE_PWR_ST ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0050))
+#define MDSM_CPC_MDCMORE_CONFG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0080))
+#define MDSM_CPC_SPARE_REG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0090))
+#define MDSM_CSC_CH_CORE_LPACK_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0094))
+#define MDSM_CSC_CH_CORE_SLP_PROT_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0098))
+#define MDSM_CSC_CH_CORE_COHERENCE_MASK ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x009C))
+#define MDSM_CPC_USIP0_ON_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0100))
+#define MDSM_CPC_USIP0_OFF_SW_CTRL ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0110))
+#define MDSM_CPC_MDCORE_PROBE_ST ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0200))
+#define MDSM_CPC_MDCORE_PROBE_ST1 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0204))
+#define MDSM_CPC_MDCORE_PROBE_ST2 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0208))
+#define MDSM_CPC_MDCORE_PROBE_ST3 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x020C))
+#define MDSM_CPC_MDCORE_PROBE_ST4 ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0210))
+#define MDSM_CPC_MDCORE_ERR_FLAG ((volatile kal_uint32*)(MDSM_CORE_PWR_CTRL_BASE + 0x0220))
+
+#define MD_RM_SYS_CLK_SETTLE (RM_SYS_CLK_SETTLE)
+#define MD_PRE_TRIG_SETTLE (0x4)
+#if defined(MT6297) || defined(MT6297_IA)
+#define MD_MAS_TRIG_EMI_SAL (0xA)
+#else
+#define MD_MAS_TRIG_EMI_SAL (0x2)
+#endif
+#define MD_MAS_TRIG_L1_COMM_SAL (0x4)
+#define MD_RM_RESOURCE_SETTLE (MD_PRE_TRIG_SETTLE + MD_RM_SYS_CLK_SETTLE + 4 + MAX4(MD_RM_PLL_SETTLE, MD_MAX_PWR_SETTLE, MD_MAS_TRIG_MAX_SETTLE, MD_TIMER_TRIG_SETTLE) + 2 + 3)
+
+#else
+ #error "no chip match"
+#endif
+
+/* L1 LPM: Low Power Monitor for SM/DCM */
+#define L1DCM_LPM_CTRL ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0080UL))
+#define L1DCM_LPM_STS0 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0088UL))
+#define L1DCM_LPM_STS1 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x008CUL))
+#define L1DCM_LPM_STS2 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0090UL))
+#define L1DCM_LPM_STS3 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0094UL))
+#define L1DCM_LPM_STS4 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0098UL))
+#define L1DCM_LPM_STS5 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x009CUL))
+
+/* LPM: Read status via register */
+#define DCM_STS0 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0100UL))
+#define DCM_STS1 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0104UL))
+#define DCM_STS2 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x0108UL))
+#define DCM_STS3 ((volatile kal_uint32*)(MDGLOBAL_DCM_BASE + 0x010CUL))
+
+/******************** MD_TOPSM ASSERT Macro ********************/
+#ifdef __MTK_INTERNAL__
+#define MD_TOPSM_ASSERT_Bypass( st ) EXT_ASSERT( st, 0, 0, 0 )
+#define MD_TOPSM_ASSERT_Reboot( st ) EXT_ASSERT( st, 0, 0, 0 )
+#define MD_TOPSM_EXT_ASSERT_Bypass( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#define MD_TOPSM_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#else
+#define MD_TOPSM_ASSERT_Bypass( st ) (void)0
+#define MD_TOPSM_ASSERT_Reboot( st ) EXT_ASSERT( st, 0, 0, 0 )
+#define MD_TOPSM_EXT_ASSERT_Bypass( st, d1, d2, d3 ) (void)0
+#define MD_TOPSM_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#endif
+
+/*ML TODO: What's the check?*/
+#if (RM_SYS_CLK_SETTLE < CLK_SETTLE)
+ #error "RM_SYS_CLK_SETTLE should be larger than CLK_SETTLE"
+#endif
+
+#define CLK32K_MICRO_SECOND(n) ((int)(n*32.0/1000))
+#define CLK_SETTLE CLK32K_MICRO_SECOND(5000) // 5000 or 3125
+
+/*Global MD TOPSM data structure*/
+typedef struct
+{
+ kal_uint16 re_K_cnt;
+
+ volatile kal_uint32 fmResult;
+
+ kal_bool SRCLK_ForceOn_HandleInit;
+ #if defined(__MTK_TARGET__)
+ __attribute__((aligned(4))) kal_uint32 SRCLK_ForceOn_Enable; // one bit per module
+ #else
+ /*xl1sim don't support gcc __attribute__*/
+ kal_uint32 SRCLK_ForceOn_Enable; // one bit per module
+ #endif
+ kal_bool PLL_ForceOn_HandleInit;
+ kal_uint32 PLL_ForceOn_Enable[NUM_OF_PLL_FORCEON_USER];
+ kal_uint32 PLL_ForceOn_Count[NUM_OF_PS_TOPSM_PLL];
+ kal_uint32 force_on_usip_frc;
+ kal_uint32 force_on_usip_caller;
+ kal_uint32 pwr_sta_before_force_on_usip;
+ kal_uint32 clear_force_on_usip_frc;
+ kal_uint32 clear_force_on_usip_caller;
+ kal_uint32 pwr_sta_before_clear_force_on_usip;
+} MDTOPSM_Globals;
+
+#if defined(L1_SIM)
+#undef MDTOPSM_US_DELAY
+#define MDTOPSM_US_DELAY(us) PROCSIM_CONSUME_PROCTIME_US(us)
+#endif
+
+#endif /*__ASSEMBLER__*/
+#endif /* !MD_TOPSM_PRIVATE_H*/
+
diff --git a/mcu/driver/sleep_drv/internal/inc/MIXEDSYS_TOPSM_private.h b/mcu/driver/sleep_drv/internal/inc/MIXEDSYS_TOPSM_private.h
new file mode 100644
index 0000000..f611c75
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/MIXEDSYS_TOPSM_private.h
@@ -0,0 +1,219 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MIXEDSYS_TOPSM_private.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * topsm for mixedsys for C2K support
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef MIXEDSYS_TOPSM_PRIVATE_H
+#define MIXEDSYS_TOPSM_PRIVATE_H
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+/* =============== Register for L1Core MIXEDSYS TOPSM ====================== */
+#if defined(__MD93__)
+
+#define MIXEDSYS_TOPSM_base (L1_BASE_MADDR_ABB_MIXEDSYS+0xB000)
+
+#endif
+
+#define MIXEDSYS_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x00))
+#define MIXEDSYS_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x80))
+#define MIXEDSYS_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0xA0))
+#define MIXEDSYS_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0xC0))
+#define MIXEDSYS_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0xC4))
+#define MIXEDSYS_TOPSM_SM_PWR_SW_CTRL_SEL ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0xCC))
+#define MIXEDSYS_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0xD0))
+#define MIXEDSYS_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0xD4))
+
+#define MIXEDSYS_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x100))
+#define MIXEDSYS_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x108))
+#define MIXEDSYS_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x120))
+#define MIXEDSYS_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x140))
+#define MIXEDSYS_TOPSM_SM_TMR_MAS_TRIG_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x160))
+#define MIXEDSYS_TOPSM_SM_TMR_TIMER_TRIG_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x170))
+#define MIXEDSYS_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x180))
+#define MIXEDSYS_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x1A0))
+
+#define MIXEDSYS_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x200))
+#define MIXEDSYS_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x208))
+#define MIXEDSYS_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x220))
+#define MIXEDSYS_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x240))
+#define MIXEDSYS_TOPSM_SM_SLV_MAS_TRIG_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x260))
+#define MIXEDSYS_TOPSM_SM_SLV_TIMER_TRIG_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x270))
+#define MIXEDSYS_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x280))
+#define MIXEDSYS_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x2A0))
+
+#define MIXEDSYS_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x300))
+#define MIXEDSYS_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x308))
+#define MIXEDSYS_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x320))
+#define MIXEDSYS_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x340))
+#define MIXEDSYS_TOPSM_SM_DBG_MAS_TRIG_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x360))
+#define MIXEDSYS_TOPSM_SM_DBG_TIMER_TRIG_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x370))
+#define MIXEDSYS_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x380))
+#define MIXEDSYS_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x3A0))
+
+#define MIXEDSYS_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x400))
+#define MIXEDSYS_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x410))
+#define MIXEDSYS_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x418))
+#define MIXEDSYS_TOPSM_SM_MAS_TRIG_GRP_SETTLE ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x420))
+#define MIXEDSYS_TOPSM_SM_MAS_TRIG_GRP_SAL ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x430))
+#define MIXEDSYS_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x440))
+#define MIXEDSYS_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x450))
+#define MIXEDSYS_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x458))
+#define MIXEDSYS_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x460))
+#define MIXEDSYS_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x464))
+#define MIXEDSYS_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x468))
+#define MIXEDSYS_TOPSM_SM_SLV_REQ_IRQ ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x470))
+#define MIXEDSYS_TOPSM_SM_DBG_REQ_IRQ ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x478))
+#define MIXEDSYS_TOPSM_SM_MAS_REQ_IRQ ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x480))
+
+#define MIXEDSYS_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x4A0))
+#define MIXEDSYS_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x4B0))
+#define MIXEDSYS_TOPSM_SW_PWR_FORCE_ON ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x4C0))
+#define MIXEDSYS_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x4D0))
+#define MIXEDSYS_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x4E0))
+
+#define MIXEDSYS_TOPSM_SM_PWR_STATUS0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x500))
+
+#define MIXEDSYS_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x580))
+#define MIXEDSYS_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x590))
+#define MIXEDSYS_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x5A0))
+#define MIXEDSYS_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x5A4))
+#define MIXEDSYS_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x5C0))
+#define MIXEDSYS_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x5D0))
+#define MIXEDSYS_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x5E0))
+
+#define MIXEDSYS_TOPSM_SM_TOPSM_DBGSEL ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x600))
+#define MIXEDSYS_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x608))
+#define MIXEDSYS_TOPSM_SM_MCF_CNT_BASE ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x610))
+
+#define MIXEDSYS_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x620))
+#define MIXEDSYS_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x624))
+#define MIXEDSYS_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x628))
+
+#define MIXEDSYS_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x680))
+#define MIXEDSYS_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x690))
+#define MIXEDSYS_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x6A0))
+#define MIXEDSYS_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MIXEDSYS_TOPSM_base+0x6B0))
+
+/* =============== Register for L1Core MIXEDSYS TOPSM end ====================== */
+extern void MIXEDSYS_TOPSM_Init(void);
+
+#endif /* MEM_CONFIG_H */
diff --git a/mcu/driver/sleep_drv/internal/inc/MODEM_TOPSM_private.h b/mcu/driver/sleep_drv/internal/inc/MODEM_TOPSM_private.h
new file mode 100644
index 0000000..b8b4427
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/MODEM_TOPSM_private.h
@@ -0,0 +1,929 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * MODEM_TOPSM_private.h
+ *
+ * Project:
+ * --------
+ * MT6250
+ *
+ * Description:
+ * ------------
+ * Modem Resource Management (Modem TOPSM) configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef MODEM_TOPSM_PRIVATE_H
+#define MODEM_TOPSM_PRIVATE_H
+
+// #include "MD_TOPSM_private.h"
+#include "reg_base.h"
+#include "sleepdrv_common.h"
+#include "sleepdrv_interface.h"
+//#include "RM_public.h"
+#include "l1_rm_public.h"
+#include "event_info_utility.h" // MODEM_WARNING_MESSAGE header file
+
+#define __CENTRALIZED_SLEEP_MANAGER_V2__
+
+#ifdef __CENTRALIZED_SLEEP_MANAGER_V2__
+
+/******************** Register Definition ********************/
+#if defined(__MD93__) || defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+#if 0 /* Lanslo: Since Strike is porting XL1SIM to UMOLY, we remove this temp redefinction for XL1SIM to align UMOLY target and this change is done together with L1. */
+ #if defined(L1_SIM)
+/* under construction !*/
+ #endif
+#endif /* if 0 */
+#if defined(L1_SIM)
+ #define TOP_SleepMode_base MODEM_TOPSM_base /* Notice this register base MUST always align with L1. */
+#endif
+#endif
+
+
+#if defined(__MD93__) /*address definition*/
+
+#define MODEM_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x00))
+#define MODEM_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x04))
+#define MODEM_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x08))
+#define MODEM_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x0C))
+#define MODEM_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x10))
+#define MODEM_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x14))
+#define MODEM_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x18))
+#define MODEM_TOPSM_SM_PWR_CON7 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1C))
+
+// not exist in 93, should remove later
+#define MODEM_TOPSM_SM_PWR_CON8 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x20))
+#define MODEM_TOPSM_SM_PWR_CON9 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x24))
+#define MODEM_TOPSM_SM_PWR_CON10 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x28))
+#define MODEM_TOPSM_SM_PWR_CON11 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2C))
+#define MODEM_TOPSM_SM_PWR_CON12 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x30))
+#define MODEM_TOPSM_SM_PWR_CON13 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x34))
+#define MODEM_TOPSM_SM_PWR_CON14 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x38))
+#define MODEM_TOPSM_SM_PWR_CON15 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3C))
+#define MODEM_TOPSM_SM_PWR_CON16 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x40))
+#define MODEM_TOPSM_SM_PWR_CON17 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x44))
+#define MODEM_TOPSM_SM_PWR_CON18 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x48))
+#define MODEM_TOPSM_SM_PWR_CON19 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4C))
+#define MODEM_TOPSM_SM_PWR_CON20 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x50))
+#define MODEM_TOPSM_SM_PWR_CON21 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x54))
+#define MODEM_TOPSM_SM_PWR_CON22 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x58))
+#define MODEM_TOPSM_SM_PWR_CON23 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5C))
+
+#define MODEM_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x80))
+#define MODEM_TOPSM_SM_PWR_ON_SW_CTRL1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x84))
+#define MODEM_TOPSM_SM_PWR_ON_SW_CTRL2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x88))
+#define MODEM_TOPSM_SM_PWR_ON_SW_CTRL3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x8C))
+#define MODEM_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xA0))
+#define MODEM_TOPSM_SM_PWR_OFF_SW_CTRL1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xA4))
+#define MODEM_TOPSM_SM_PWR_OFF_SW_CTRL2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xA8))
+#define MODEM_TOPSM_SM_PWR_OFF_SW_CTRL3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xAC))
+#define MODEM_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC0))
+#define MODEM_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC4))
+#define MODEM_TOPSM_SM_PWR_SW_CTRL_SEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0xCC))
+#define MODEM_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MODEM_TOPSM_base+0xD0))
+#define MODEM_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MODEM_TOPSM_base+0xD4))
+
+#define MODEM_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x100))
+#define MODEM_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x108))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x120))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x124))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x128))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x12C))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x140))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x144))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x148))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x14C))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x150))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x154))
+#define MODEM_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x160))
+#define MODEM_TOPSM_SM_TMR_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x164))
+#define MODEM_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x170))
+#define MODEM_TOPSM_SM_TMR_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x174))
+#define MODEM_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x180))
+#define MODEM_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1A0))
+#define MODEM_TOPSM_SM_TMR_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1A4))
+
+#define MODEM_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x200))
+#define MODEM_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x208))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x220))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x224))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x228))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x22C))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x240))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x244))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x248))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x24C))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x250))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x254))
+#define MODEM_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x260))
+#define MODEM_TOPSM_SM_SLV_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x264))
+#define MODEM_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x270))
+#define MODEM_TOPSM_SM_SLV_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x274))
+#define MODEM_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x280))
+#define MODEM_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2A0))
+#define MODEM_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2A4))
+
+#define MODEM_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x300))
+#define MODEM_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x308))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x320))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x324))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x328))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x32C))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x340))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x344))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x348))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x34C))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x350))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x354))
+#define MODEM_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x360))
+#define MODEM_TOPSM_SM_DBG_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x364))
+#define MODEM_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x370))
+#define MODEM_TOPSM_SM_DBG_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x374))
+#define MODEM_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x380))
+#define MODEM_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3A0))
+#define MODEM_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3A4))
+
+#define MODEM_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x400))
+#define MODEM_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x410))
+#define MODEM_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x418))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x420))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x424))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x430))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x434))
+#define MODEM_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x440))
+#define MODEM_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x450))
+#define MODEM_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x454))
+#define MODEM_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x458))
+#define MODEM_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x45C))
+#define MODEM_TOPSM_SM_SYSCLK_SAL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x460))
+#define MODEM_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x468))
+#define MODEM_TOPSM_SM_SLV_REQ_IRQ ((volatile kal_uint32*)(MODEM_TOPSM_base+0x470))
+#define MODEM_TOPSM_SM_DBG_REQ_IRQ ((volatile kal_uint32*)(MODEM_TOPSM_base+0x478))
+#define MODEM_TOPSM_SM_MAS_REQ_IRQ ((volatile kal_uint32*)(MODEM_TOPSM_base+0x480))
+
+#define MODEM_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4A0))
+#define MODEM_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4B0))
+#define MODEM_TOPSM_SW_PWR_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4C0))
+#define MODEM_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4D0))
+#define MODEM_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4E0))
+
+/* Still exist?*/
+#define MODEM_TOPSM_SM_PWR_STATUS0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x500))
+#define MODEM_TOPSM_SM_PWR_STATUS1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x504))
+#define MODEM_TOPSM_SM_PWR_STATUS2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x508))
+#define MODEM_TOPSM_SM_PWR_STATUS3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x50C))
+#define MODEM_TOPSM_SM_PWR_STATUS4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x510))
+#define MODEM_TOPSM_SM_PWR_STATUS5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x514))
+#define MODEM_TOPSM_SM_PWR_STATUS6 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x518))
+#define MODEM_TOPSM_SM_PWR_STATUS7 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x51C))
+#define MODEM_TOPSM_SM_PWR_STATUS8 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x520))
+#define MODEM_TOPSM_SM_PWR_STATUS9 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x524))
+#define MODEM_TOPSM_SM_PWR_STATUS10 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x528))
+#define MODEM_TOPSM_SM_PWR_STATUS11 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x52C))
+#define MODEM_TOPSM_SM_PWR_STATUS12 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x530))
+#define MODEM_TOPSM_SM_PWR_STATUS13 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x534))
+#define MODEM_TOPSM_SM_PWR_STATUS14 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x538))
+#define MODEM_TOPSM_SM_PWR_STATUS15 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x53C))
+#define MODEM_TOPSM_SM_PWR_STATUS16 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x540))
+#define MODEM_TOPSM_SM_PWR_STATUS17 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x544))
+#define MODEM_TOPSM_SM_PWR_STATUS18 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x548))
+#define MODEM_TOPSM_SM_PWR_STATUS19 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x54C))
+#define MODEM_TOPSM_SM_PWR_STATUS20 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x550))
+#define MODEM_TOPSM_SM_PWR_STATUS21 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x554))
+#define MODEM_TOPSM_SM_PWR_STATUS22 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x558))
+#define MODEM_TOPSM_SM_PWR_STATUS23 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x55C))
+
+#define MODEM_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x580))
+#define MODEM_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x590))
+#define MODEM_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5A0))
+#define MODEM_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5A4))
+#define MODEM_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5C0))
+#define MODEM_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5D0))
+#define MODEM_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5E0))
+
+#define MODEM_TOPSM_SM_TOPSM_DBGSEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x600))
+#define MODEM_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x608))
+#define MODEM_TOPSM_SM_MCF_CNT_BASE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x60C))
+
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MODEM_TOPSM_base+0x620))
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x624))
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x628))
+
+#define MODEM_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(MODEM_TOPSM_base+0x640))
+#define MODEM_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x644))
+#define MODEM_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x670))
+
+#define MODEM_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x680))
+#define MODEM_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x690))
+#define MODEM_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x694))
+#define MODEM_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x698))
+#define MODEM_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A0))
+#define MODEM_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A4))
+#define MODEM_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A8))
+#define MODEM_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B0))
+#define MODEM_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B4))
+#define MODEM_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B8))
+
+#elif defined(__MD95__)
+
+#define MODEM_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x00))
+#define MODEM_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x04))
+#define MODEM_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x08))
+#define MODEM_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x0C))
+#define MODEM_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x10))
+#define MODEM_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x14))
+#define MODEM_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x18))
+//Only 7 Power Con in 95
+
+#define MODEM_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x80))
+#define MODEM_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xA0))
+
+#define MODEM_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC0))
+#define MODEM_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC4))
+#define MODEM_TOPSM_SM_PWR_BYPASS_PROTECT_RDY ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC8))
+#define MODEM_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MODEM_TOPSM_base+0xD0))
+#define MODEM_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MODEM_TOPSM_base+0xD4))
+#define MODEM_TOPSM_SM_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(MODEM_TOPSM_base+0xE0))
+#if defined (L1_SIM)
+#define MODEM_TOPSM_SM_PWR_SW_CTRL_SEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0xF0))
+#endif
+
+#define MODEM_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x100))
+#define MODEM_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x108))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x120))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x124))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x140))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x144))
+#define MODEM_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x160))
+#define MODEM_TOPSM_SM_TMR_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x164))
+#define MODEM_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x170))
+#define MODEM_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x180))
+// PRE_TRIG is new in 95
+#define MODEM_TOPSM_SM_TMR_PRE_TRIG_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x190))
+#define MODEM_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1A0))
+#define MODEM_TOPSM_SM_TMR_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1A4))
+
+#define MODEM_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x200))
+#define MODEM_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x208))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x220))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x224))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x240))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x244))
+#define MODEM_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x260))
+#define MODEM_TOPSM_SM_SLV_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x264))
+#define MODEM_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x270))
+#define MODEM_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x280))
+// PRE_TRIG is new in 95
+#define MODEM_TOPSM_SM_SLV_PRE_TRIG_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x290))
+#define MODEM_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2A0))
+#define MODEM_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2A4))
+
+#define MODEM_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x300))
+#define MODEM_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x308))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x320))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x324))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x340))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x344))
+#define MODEM_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x360))
+#define MODEM_TOPSM_SM_DBG_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x364))
+#define MODEM_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x370))
+#define MODEM_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x380))
+// PRE_TRIG is new in 95
+#define MODEM_TOPSM_SM_DBG_PRE_TRIG_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x390))
+#define MODEM_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3A0))
+#define MODEM_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3A4))
+
+
+#define MODEM_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x400))
+// PRE_TRIG is new in 95
+#define MODEM_TOPSM_SM_PRE_TRIG_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x408))
+#define MODEM_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x410))
+#define MODEM_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x418))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x420))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x424))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x430))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x434))
+#define MODEM_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x440))
+
+#define MODEM_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x450))
+#define MODEM_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x454))
+#define MODEM_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x458))
+#define MODEM_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x45C))
+
+#define MODEM_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x468))
+
+#define MODEM_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4A0))
+#define MODEM_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4B0))
+#define MODEM_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4D0))
+#define MODEM_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4E0))
+// PRE_TRIG is new in 95
+#define MODEM_TOPSM_SW_PRE_TRIG_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4F0))
+
+#define MODEM_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x580))
+#define MODEM_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x590))
+#define MODEM_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5A0))
+#define MODEM_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5A4))
+// the following addresses are different from previous generations/projects
+#define MODEM_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5B0))
+#define MODEM_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5C0))
+#define MODEM_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5D0))
+#define MODEM_TOPSM_SW_CLIENT_ACT_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5E0))
+// PRE_TRIG is new in 95
+#define MODEM_TOPSM_SW_PRE_TRIG_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5F0))
+
+#define MODEM_TOPSM_SM_TOPSM_CONFG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x600))
+#define MODEM_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x608))
+#define MODEM_TOPSM_SM_MCF_CNT_BASE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x60C))
+
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MODEM_TOPSM_base+0x610))
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x614))
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x618))
+
+#define MODEM_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(MODEM_TOPSM_base+0x640))
+#define MODEM_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x644))
+#define MODEM_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x670))
+
+#define MODEM_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x680))
+#define MODEM_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x690))
+#define MODEM_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x694))
+#define MODEM_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x698))
+#define MODEM_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A0))
+#define MODEM_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A4))
+#define MODEM_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A8))
+#define MODEM_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B0))
+#define MODEM_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B4))
+#define MODEM_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B8))
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define MODEM_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x00))
+#define MODEM_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x04))
+#define MODEM_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x08))
+#define MODEM_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x0C))
+#define MODEM_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x10))
+#define MODEM_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x14))
+#define MODEM_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x18))
+#define MODEM_TOPSM_SM_PWR_CON7 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1C))
+#define MODEM_TOPSM_SM_PWR_CON8 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x20))
+#define MODEM_TOPSM_SM_PWR_CON9 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x24))
+#define MODEM_TOPSM_SM_PWR_CON10 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x28))
+#define MODEM_TOPSM_SM_PWR_CON11 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2C))
+#define MODEM_TOPSM_SM_PWR_CON12 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x30))
+#define MODEM_TOPSM_SM_PWR_CON13 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x34))
+#define MODEM_TOPSM_SM_PWR_CON14 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x38))
+#define MODEM_TOPSM_SM_PWR_CON15 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3C))
+#define MODEM_TOPSM_SM_PWR_CON16 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x40))
+#define MODEM_TOPSM_SM_PWR_CON17 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x44))
+#define MODEM_TOPSM_SM_PWR_CON18 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x48))
+
+#define MODEM_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x80))
+#define MODEM_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xA0))
+
+#define MODEM_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC0))
+#define MODEM_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC4))
+#define MODEM_TOPSM_SM_PWR_BYPASS_PROTECT_RDY ((volatile kal_uint32*)(MODEM_TOPSM_base+0xC8))
+#define MODEM_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(MODEM_TOPSM_base+0xD0))
+#define MODEM_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(MODEM_TOPSM_base+0xD4))
+#define MODEM_TOPSM_SM_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(MODEM_TOPSM_base+0xE0))
+#if defined (L1_SIM)
+#define MODEM_TOPSM_SM_PWR_SW_CTRL_SEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0xF0))
+#endif
+
+#define MODEM_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x100))
+#define MODEM_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x108))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x120))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x124))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x128))
+#define MODEM_TOPSM_SM_TMR_PLL_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x12C))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x140))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x144))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x148))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x14C))
+#define MODEM_TOPSM_SM_TMR_PWR_MASK4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x150))
+#define MODEM_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x160))
+#define MODEM_TOPSM_SM_TMR_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x164))
+#define MODEM_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x170))
+#define MODEM_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x180))
+#define MODEM_TOPSM_SM_TMR_CLIENT_PRE_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x188))
+#define MODEM_TOPSM_SM_TMR_PRE_TRIG_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x190))
+#define MODEM_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1A0))
+#define MODEM_TOPSM_SM_TMR_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x1A4))
+
+#define MODEM_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x200))
+#define MODEM_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x208))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x220))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x224))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x228))
+#define MODEM_TOPSM_SM_SLV_PLL_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x22C))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x240))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x244))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x248))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x24C))
+#define MODEM_TOPSM_SM_SLV_PWR_MASK4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x250))
+#define MODEM_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x260))
+#define MODEM_TOPSM_SM_SLV_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x264))
+#define MODEM_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x270))
+#define MODEM_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x280))
+#define MODEM_TOPSM_SM_SLV_CLIENT_PRE_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x288))
+#define MODEM_TOPSM_SM_SLV_PRE_TRIG_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x290))
+#define MODEM_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2A0))
+#define MODEM_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x2A4))
+
+#define MODEM_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x300))
+#define MODEM_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x308))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x320))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x324))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x328))
+#define MODEM_TOPSM_SM_DBG_PLL_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x32C))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x340))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x344))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK2 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x348))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK3 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x34C))
+#define MODEM_TOPSM_SM_DBG_PWR_MASK4 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x350))
+#define MODEM_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x360))
+#define MODEM_TOPSM_SM_DBG_MAS_TRIG_MASK1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x364))
+#define MODEM_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x370))
+#define MODEM_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x380))
+#define MODEM_TOPSM_SM_DBG_CLIENT_PRE_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x388))
+#define MODEM_TOPSM_SM_DBG_PRE_TRIG_MASK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x390))
+#define MODEM_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3A0))
+#define MODEM_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x3A4))
+
+#define MODEM_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x400))
+#define MODEM_TOPSM_SM_PRE_TRIG_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x408))
+#define MODEM_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x410))
+#define MODEM_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x418))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x420))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x424))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x430))
+#define MODEM_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x434))
+#define MODEM_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x440))
+
+#define MODEM_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x450))
+#define MODEM_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x454))
+#define MODEM_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x458))
+#define MODEM_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x45C))
+
+#define MODEM_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(MODEM_TOPSM_base+0x468))
+
+#define MODEM_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4A0))
+#define MODEM_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4B0))
+#define MODEM_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4D0))
+#define MODEM_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4E0))
+#define MODEM_TOPSM_SW_CLIENT_PRE_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4E8))
+#define MODEM_TOPSM_SW_PRE_TRIG_FORCE_ON ((volatile kal_uint32*)(MODEM_TOPSM_base+0x4F0))
+
+#define MODEM_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x580))
+#define MODEM_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x590))
+#define MODEM_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5A0))
+#define MODEM_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5A4))
+#define MODEM_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5B0))
+#define MODEM_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5C0))
+#define MODEM_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5D0))
+#define MODEM_TOPSM_SW_CLIENT_ACT_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5E0))
+#define MODEM_TOPSM_SW_CLIENT_PRE_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5E8))
+#define MODEM_TOPSM_SW_PRE_TRIG_STA ((volatile kal_uint32*)(MODEM_TOPSM_base+0x5F0))
+
+#define MODEM_TOPSM_SM_TOPSM_CONFG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x600))
+#define MODEM_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x608))
+#define MODEM_TOPSM_SM_MCF_CNT_BASE ((volatile kal_uint32*)(MODEM_TOPSM_base+0x60C))
+
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(MODEM_TOPSM_base+0x610))
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(MODEM_TOPSM_base+0x614))
+#define MODEM_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(MODEM_TOPSM_base+0x618))
+
+#define MODEM_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(MODEM_TOPSM_base+0x640))
+#define MODEM_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x644))
+#define MODEM_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x670))
+
+#define MODEM_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x680))
+#define MODEM_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x690))
+#define MODEM_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x694))
+#define MODEM_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x698))
+#define MODEM_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A0))
+#define MODEM_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A4))
+#define MODEM_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6A8))
+#define MODEM_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B0))
+#define MODEM_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B4))
+#define MODEM_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(MODEM_TOPSM_base+0x6B8))
+
+#else /*address definition*/
+
+#error "please check the address definition of modem topsm"
+
+#endif /*address definition*/
+
+
+#ifndef MAX
+#define MAX(a,b) ( ( (a) > (b) ) ? (a) : (b) )
+#endif
+
+#ifndef MIN
+#define MIN(a,b) ( ( (a) < (b) ) ? (a) : (b) )
+#endif
+/******************** MODEM_TOPSM ASSERT Macro ********************/
+#ifdef __MTK_INTERNAL__
+ #define MODEM_TOPSM_ASSERT_Bypass( st ) ASSERT( st )
+ #define MODEM_TOPSM_ASSERT_Reboot( st ) ASSERT( st )
+ #define MODEM_TOPSM_EXT_ASSERT_Bypass( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+ #define MODEM_TOPSM_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#else
+ #define MODEM_TOPSM_ASSERT_Bypass( st ) (void)0
+ #define MODEM_TOPSM_ASSERT_Reboot( st ) ASSERT( st )
+ #define MODEM_TOPSM_EXT_ASSERT_Bypass( st, d1, d2, d3 ) (void)0
+ #define MODEM_TOPSM_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#endif
+
+/******************** MODEM_TOPSM.c usage ********************/
+/* for MODEM_TOPSM_RM_TMR_SSTA */
+#if defined( __UMTS_FDD_MODE__ )
+ #define MD_TIMER_STATE_CHECK_MASK 0x000000FF /* Check TDMA timer and RTR timer status */
+ #define MD_TIMER_STATE_CHECK 0x00000011 /* TDMA timer and RTR timer are in normal state */
+#else /* !__UMTS_FDD_MODE__ */
+ #define MD_TIMER_STATE_CHECK_MASK 0x0000000F /* Check TDMA timer status */
+ #define MD_TIMER_STATE_CHECK 0x00000001 /* TDMA timer is in normal state */
+#endif /* __UMTS_FDD_MODE__ */
+
+/* For 32K Calibration Mechanism */
+//#define TOPSM_LONG_FM_DURATION (FM_DURATION+1) /* 2x(4095+1)=8192T => ideal fmResult = 6500000 @ 26M */
+#define TOPSM_LONG_FM_DURATION 8192
+#define MODEM_TOPSM_LONG_FM_DURATION TOPSM_LONG_FM_DURATION
+
+#define MODEM_TOPSM_ABS(x) ((x) > 0 ? (x) : -(x)) /* Used to get the absolute value */
+
+typedef struct
+{
+ kal_bool init_force_on;
+
+ kal_bool calibrating;
+ kal_bool ReK;
+#ifdef MTK_SLEEP_ENABLE
+ kal_bool UpdateCal_2G;
+#endif
+ kal_uint16 re_K_cnt;
+ kal_uint16 curr_FM_DUR;
+ volatile kal_uint32 fmResult;
+
+ /* backup TXSYS request for meta mode*/
+ kal_bool meta_force_off;
+ kal_bool Is_tx_force_on;
+ kal_uint32 txsys_outcr_req;
+
+ kal_uint32 debug_check_FRC;
+ kal_uint32 debug_check_pwr_rdy;
+
+ kal_uint32 lpmon_debug_info1;
+
+#ifdef BIG_DAC_CHANGE_RECALIBRATION
+ kal_uint32 FreOffThreshold[NUM_OF_CLOCK_SOURCE]; /* Threshold of frequency offset */
+ kal_uint32 FreOffMaxValid[NUM_OF_CLOCK_SOURCE]; /* Maximun valid frequency offset */
+ kal_int32 Ref_FreqOff[NUM_OF_CLOCK_SOURCE]; /* To record current frequency offset base */
+#endif
+#ifdef L1_SIM
+ kal_uint32 check_sta;
+#endif
+} MODEM_TOPSM_Globals;
+
+/*Global MD LPM data log structure*/
+typedef struct
+{
+ kal_uint32 SIM1_active_RAT;
+ kal_uint32 SIM2_active_RAT;
+ kal_uint32 SIM3_active_RAT;
+ kal_uint32 SIM1_RAT_drx; /* unit: ms */
+ kal_uint32 SIM2_RAT_drx;
+ kal_uint32 SIM3_RAT_drx;
+ kal_uint32 SIM1_update_frc;
+ kal_uint32 SIM2_update_frc;
+ kal_uint32 SIM3_update_frc;
+} MDLPM_Globals_Log;
+
+extern void MODEM_TOPSM_SetFRC_32K_FM( kal_uint32 num_32k, kal_uint32 num_208m);
+extern void MODEM_TOPSM_Init( void);
+
+#endif /* __CENTRALIZED_SLEEP_MANAGER_V2__ */
+#endif /* !MODEM_TOPSM_PRIVATE_H*/
+
diff --git a/mcu/driver/sleep_drv/internal/inc/ap_ostd_private.h b/mcu/driver/sleep_drv/internal/inc/ap_ostd_private.h
new file mode 100644
index 0000000..efb101c
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/ap_ostd_private.h
@@ -0,0 +1,185 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ap_ostd_private.h
+ *
+ * Project:
+ * --------
+ * MTK6280
+ *
+ * Description:
+ * ------------
+ * This is the driver layer and corresponding Sleep Mode of AP OS Timer HW
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef AP_OSTD_PRIVATE_H
+#define AP_OSTD_PRIVATE_H
+
+#include "reg_base.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "AP_RM_private.h"
+
+#ifdef __CENTRALIZED_SLEEP_MANAGER_V2__
+#ifdef __AP_SLEEP_MANAGER_SUPPORT__
+
+/*****************************************************************************
+* All DEFINEs
+*****************************************************************************/
+
+/******************** Register Definition ********************/
+#if defined(MT6752) && defined(__MD2__)
+#define AP_OSTD_base AP_OSTIMER_base /* 0xA00E0000 is used for MT6280 */
+#define AP_CMD_MAGIC_VALUE 0x11530000
+#endif
+
+/* Registers for AP side OS Timer. */
+
+#define AP_OST_CON ((volatile kal_uint16*)(AP_OSTD_base+0x00)) /* OS Timer Control Register */
+ /* 0: EN */
+ /* 1: UFN_DOWN */
+ /* 2: OST_DBG: Enable OST wake-up debug function */
+#define AP_OST_CMD ((volatile kal_uint32*)(AP_OSTD_base+0x04)) /* OS Timer Command Register */
+ /* 0: PAUSE_START */
+ /* 1: OST_RD */
+ /* 2: OST_WR */
+ /* 13: OST_UFN_WR */
+ /* 14: OST_AFN_WR */
+ /* 15: OST_CON_WR */
+#define AP_OST_STA ((volatile kal_uint16*)(AP_OSTD_base+0x08)) /* OS Timer Command Status Register */
+ /* 0: READY: to indicate OST is in Normal or Pause mode */
+ /* 1: CMD_CPL: to indicate OST command is completed or not */
+ /* [4:3]: to indicate a Pause request is received by HW or not */
+ /* 00=>last pause command request is not completed yet */
+ /* 01=>last pause command request is completed with OST pause mode active */
+ /* 10=>last pause command request is completed with wakeup sources */
+ /* 11=>last pause command request is completed with UFN < 2 */
+ /* 6: AFN_DLY_OVER: to indicate AFN_DLY Counter is overflow or not*/
+ /* 15: CPU_SLEEP: to indicate the processor is in sleep mode or not (For debug purpose)*/
+#define AP_OST_FRM ((volatile kal_uint32*)(AP_OSTD_base+0x0C)) /* OS Timer Frame Duration [12:0] */
+#define AP_OST_FRM_F32K ((volatile kal_uint32*)(AP_OSTD_base+0x10)) /* OS Timer Frame Duration by 32K clock [8:0] */
+ /* [15:12]: OST_FRM_NUM: set this value if OST_FRM < system settling time */
+ /* [8:0]: OST_FRM_F32K */
+#define AP_OST_UFN ((volatile kal_uint32*)(AP_OSTD_base+0x14)) /* OS Timer Un-alignment Frame Number [31:0] */
+#define AP_OST_AFN ((volatile kal_uint32*)(AP_OSTD_base+0x18)) /* OS Timer Alignment Frame Number [31:0] */
+#define AP_OST_AFN_DLY ((volatile kal_uint32*)(AP_OSTD_base+0x1C)) /* OS Timer Alignment Frame Delay Number [31:0]*/
+#define AP_OST_UFN_R ((volatile kal_uint32*)(AP_OSTD_base+0x20)) /* Current OS Timer Un-alignement Frame Number [31:0] */
+#define AP_OST_AFN_R ((volatile kal_uint32*)(AP_OSTD_base+0x24)) /* Current OS Timer Alignement Frame Number [31:0] */
+#define AP_OST_INT_MASK ((volatile kal_uint16*)(AP_OSTD_base+0x30)) /* OS Timer Interrupt Mask (All default masked: disabled) */
+ /* 0: mask of OS Timer Frame Time Out interrupt */
+ /* 1: mask of OS Timer Alignment Frame Time Out interrupt */
+ /* 2: mask of OS Timer Un-Alignment Frame Time Out interrupt */
+ /* 3: mask of OS Timer Pause Abort interrupt */
+ /* 4: mask of OS Timer Pause Interrupt interrupt */
+#define AP_OST_ISR ((volatile kal_uint16*)(AP_OSTD_base+0x40)) /* OS Timer Interrupt Status */
+ /* 0: OS Timer Frame Time Out interrupt Status */
+ /* 1: OS Timer Alignment Frame Time Out interrupt Status */
+ /* 2: OS Timer Un-Alignment Frame Time Out interrupt Status */
+ /* 3: OS Timer Pause Abort interrupt Status */
+ /* 4: OS Timer Pause Interrupt interrupt Status */
+#define AP_OST_EVENT_MASK ((volatile kal_uint32*)(AP_OSTD_base+0x50)) /* OS Timer Event Mask (All default enabled) */
+#define AP_OST_WAKEUP_STA ((volatile kal_uint32*)(AP_OSTD_base+0x54)) /* OS Timer Event Wakeup Status [auto-clear with source]: record the first wakeup sources */
+#define AP_OST_DBG_WAKEUP ((volatile kal_uint32*)(AP_OSTD_base+0x60)) /* OS Timer Debug Wakeup */
+
+
+//#define AP_TOPSM_RM_PWR_CON0 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x800))
+//#define AP_TOPSM_RM_PWR_CON1 ((volatile kal_uint32*)(AP_TOP_SleepMode_base+0x804))
+
+/*****************************************************************************
+* Functions provided by AP OSTD
+*****************************************************************************/
+extern void AP_OSTD_Init( void );
+
+#endif /* _AP_SLEEP_MANAGER_SUPPORT__ */
+#endif /* __CENTRALIZED_SLEEP_MANAGER_V2__ */
+#endif /* !AP_OSTD_PRIVATE_H*/
diff --git a/mcu/driver/sleep_drv/internal/inc/dcxo_div.h b/mcu/driver/sleep_drv/internal/inc/dcxo_div.h
new file mode 100644
index 0000000..27918cc
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/dcxo_div.h
@@ -0,0 +1,471 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcxo_div.h
+ *
+ * Project:
+ * --------
+ * MTK6250
+ *
+ * Description:
+ * ------------
+ * CSMM 32KHz-less setting.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef DCXO_DIV_H
+#define DCXO_DIV_H
+
+#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
+
+#include "dcxo_div_public.h"
+#include "kal_public_defs.h" /* for kal_atomic define */
+
+#define MAX_LPM_COUNTER_ADJUSTER 4
+
+#define DCXO_IDEAL_32KHZ 32768
+#define DCXO_IDEAL_32KHZ_ORDER 15 /* 32768 = 2^15 */
+#define DCXO_DIVIDER_ACCU_BIT 14 /* 14 bit accumulater fractional divider */
+
+/* 12bit, 26M source, (.-4Hz): integer = 793, fractional = 1872 + (delta_Ferr *30292)>>19 */
+/* 14bit, 26M source, (.-4Hz): integer = 793, fractional = 7488 + (delta_Ferr *121169)>>19 */
+/* 14bit, 26M source: integer = 793, fractional = 7488 + (delta_Ferr *7573)>>19 */
+/* 14bit, 6.5M source: integer = 198, fractional = 5968 + (delta_Ferr *1893)>>19 */
+#if IS_6P5M_CLOCK_SOURCE
+#define DCXO_DIVISOR_FRAC 5968 /* fractional part for 6.5M source */
+#define DCXO_DIV_FRAC_FACTOR 1893 /* fractional part factor after shift 2^19 under 14-bit divider*/
+#define DCXO_DIV_OFFSET_FACTOR 1 /* under 6.5M, delta 1divider = 0.308 ppm */
+#else
+#define DCXO_DIVISOR_FRAC 7488 /* fractional part for 26M source */
+#define DCXO_DIV_FRAC_FACTOR 7573 /* fractional part factor after shift 2^19 under 14-bit divider*/
+#define DCXO_DIV_OFFSET_FACTOR 4 /* under 26M, delta 1divider = 0.077 ppm */
+#endif
+
+#define LPM_DIV_OFFSET_2G_VAR1 100*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_2G_VAR2 110*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_3G_VAR1 43*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_3G_VAR2 86*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_4G_VAR1 7*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_4G_VAR2 13*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_4G_VAR3 3*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_4G_VAR4 6*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_5G_VAR1 6*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_5G_VAR2 11*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_5G_VAR3 3*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_5G_VAR4 6*DCXO_DIV_OFFSET_FACTOR
+#define LPM_DIV_OFFSET_START 6*60000000 //after 10mins from boot up, trigger divider offset
+#define LPM_DIV_OFFSET_DURATION 3*60000000 //each 6mins trigger divider offset
+
+#define FPM_DIV_OFFSET_2G_VAR1 50*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_2G_VAR2 100*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_3G_VAR1 43*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_3G_VAR2 86*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_4G_VAR1 7*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_4G_VAR2 13*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_5G_VAR1 6*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_5G_VAR2 11*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_5G_VAR3 3*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_5G_VAR4 6*DCXO_DIV_OFFSET_FACTOR
+#define FPM_DIV_OFFSET_START 5*60000000 //after 2mins from trigger test, trigger divider offset
+#define FPM_DIV_OFFSET_DURATION 2*60000000 //each 2mins trigger divider offset
+#define FPM_DIV_OFFSET_LOCK_DURATION 10000000 // Set 10s for always using offset value
+
+#if defined(__MD93__) || defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+#define DCXO_Base BASE_MADDR_MDTOP_GLBCON
+#define LPM_CONTROL ((volatile kal_uint32*)(DCXO_Base + 0x0900))// 0xA0130900
+#define LPM_COUNTER_VALUE ((volatile kal_uint32*)(DCXO_Base + 0x0904))// 0xA0130904
+#define LPM_MD_TOP_DUMMY ((volatile kal_uint32*)(DCXO_Base + 0x0F00))// 0xA0130F00
+#else
+#error "Please check register define of LPM counter in new project"
+#endif
+
+#if IS_32K_LESS_TEMPERATURE_SUPPORT
+#if defined(__MD95__) || defined(MT6297)
+#define MODEM_TEMP_SHARE_LATESTSTATUS ((volatile kal_uint32*)((BASE_ADDR_MODEM_TEMP_SHARE) + 0x0C))
+#define MODEM_TEMP_SHARE_LATEST ((volatile kal_uint16*)((BASE_ADDR_MODEM_TEMP_SHARE) + 0x14))
+#elif defined(__MD97__) || defined(__MD97P__) /* After Petrus, use TIA rather than MTS */
+#define TIA_TEMP ((volatile kal_uint32*)((BASE_ADDR_TIA) + 0x20))
+#define TIA_DEBUG ((volatile kal_uint32*)((BASE_ADDR_TIA) + 0xFC))
+#endif
+
+#define DCXO_DIV_UBIN_INDEX_SIZE (53)
+
+enum DCXO_DIV_UBIN_INDEX_PARAM
+{
+ DCXO_DIV_UBIN_INDEX_MIN = 0,
+ DCXO_DIV_UBIN_MIN = 7,
+ DCXO_DIV_UBIN_INDEX_MAX = 52,
+ DCXO_DIV_UBIN_MAX = 59
+};
+
+typedef struct
+{
+ kal_bool is_visited;
+ kal_int32 foe;
+} DCXO_DIV_FREQ_UBIN_TABLE_DATA_T;
+#endif
+
+typedef struct
+{
+ /* for LPM divider */
+ #if !IS_32K_LESS_TEMPERATURE_SUPPORT
+ kal_int32 freq_offset_acc;
+ #endif
+ kal_int32 freq_offset_init_cload;
+ kal_uint32 lpm_frac;
+ kal_uint32 lpm_frac_prev;
+
+ /* for FPM divider */
+ kal_uint32 fpm_frac;
+ kal_uint32 fpm_frac_prev;
+
+ /* Common for both LPM and FPM divider */
+ kal_int32 freq_offset_afc;
+
+ kal_atomic_int32 lpm_atomic_cnt;
+ kal_atomic_int32 fpm_atomic_cnt;
+ DCXO_DIV_UPDATE_MODE lpm_atomic_lock_mode;
+ DCXO_DIV_UPDATE_MODE fpm_atomic_lock_mode;
+
+ kal_uint32 debug[10];
+} DCXO_DIV_T;
+
+typedef struct
+{
+ kal_bool is_started;
+ kal_uint32 acc_lpm_cnt;
+ kal_uint32 last_lpm_cnt; /* error handle */
+ kal_uint32 last_update_time;
+ kal_uint32 last_update_attempt[MAX_LPM_COUNTER_ADJUSTER];
+} LPM_COUNTER;
+
+typedef struct
+{
+ kal_bool ext_32k_exist_check;
+ kal_bool ext_32k_exist; /* External 32k crystal exist */
+ kal_bool init_cload;
+} DCXO_DIV_STATUS;
+
+typedef struct
+{
+ kal_bool Is_trigger;
+ kal_bool Is_offset_lock;
+ /* LPM: 0 for 2/3G; 1 for 4G */
+ /* FPM: 1 for 2G; 2 for 3G_FDD; 4 for 3G_TDD; 8 for 4G */
+ kal_uint32 Trigger_mode;
+ kal_uint32 Trigger_FRC;
+ kal_uint32 FRC_run_stage;
+ kal_uint32 FRC_run_last;
+ kal_uint32 FRC_temp;
+ kal_uint32 FRC_run_lock_timestamp;
+} DCXO_DIV_TRACKING_T;
+
+#endif /* __F32_XOSC_REMOVAL_SUPPORT__ */
+
+extern kal_bool OSTD_Is3gEnabled (void);
+
+#endif /* DCXO_DIV_H */
diff --git a/mcu/driver/sleep_drv/internal/inc/fm.h b/mcu/driver/sleep_drv/internal/inc/fm.h
new file mode 100644
index 0000000..7e00a9f
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/fm.h
@@ -0,0 +1,260 @@
+ /*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * fm.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * Resource Management Central control configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
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+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef FM_H
+#define FM_H
+
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "reg_base.h"
+#include "mml1_rf_global.h" /* for MML1_RF_VCXO_TYPE_E */
+
+#if defined(__MD93__) || defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+#define FREQM_FRC_CON ((volatile kal_uint32*)(L1_BASE_MADDR_FREQM+0x00))
+#define FREQM_FRC_VAL_R ((volatile kal_uint32*)(L1_BASE_MADDR_FREQM+0x10))
+#define FREQM_FM_CON ((volatile kal_uint32*)(L1_BASE_MADDR_FREQM+0x20))
+#define FREQM_FM_CAL ((volatile kal_uint32*)(L1_BASE_MADDR_FREQM+0x30))
+#define FREQM_FM_T0 ((volatile kal_uint32*)(L1_BASE_MADDR_FREQM+0x40))
+#define FREQM_FM_T1 ((volatile kal_uint32*)(L1_BASE_MADDR_FREQM+0x50))
+#else /*address definition*/
+#error "please check the address definition of frequence management"
+#endif /*address definition*/
+
+
+/******************** MD_TOPSM ASSERT Macro ********************/
+#ifdef __MTK_INTERNAL__
+ #define FM_ASSERT_Bypass( st ) ASSERT( st )
+ #define FM_ASSERT_Reboot( st ) ASSERT( st )
+ #define FM_EXT_ASSERT_Bypass( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+ #define FM_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#else
+ #define FM_ASSERT_Bypass( st ) (void)0
+ #define FM_ASSERT_Reboot( st ) ASSERT( st )
+ #define FM_EXT_ASSERT_Bypass( st, d1, d2, d3 ) (void)0
+ #define FM_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#endif
+
+/*Global MD TOPSM data structure*/
+typedef struct
+{
+ kal_bool calibrating; /* A flag to record if doing SW manual K action. */
+ kal_bool ReK; /* trigger ReCalibration form inject message or at command. */
+ kal_uint16 re_K_cnt;
+ kal_uint32 curr_FM_DUR;
+ kal_uint32 curr_FM_FREQ;
+ volatile kal_uint32 fmResult;
+ MML1_RF_VCXO_TYPE_E vcxo_type;
+ kal_atomic_int32 fm_count;
+} FM_Globals;
+
+void FM_Init(void);
+void FM_ReCalibration(void);
+kal_bool FM_IsCalibrating( void );
+
+#define FM_DURATION_SHORT (1024)
+#define FM_DURATION_LONG (1024*4)
+#define FM_DURATION_DEFAULT FM_DURATION_LONG
+#define FM_FREQUENCY (208000000)
+
+extern void FM_SetCalibrationResult( kal_uint32 fm_dur, kal_uint32 fm_freq, kal_uint32 fmResult );
+extern void FM_GetCalibrationResult( kal_uint32 *fm_dur_ptr, kal_uint32 *fm_freq_ptr, kal_uint32 *fmResult_ptr );
+extern kal_bool FM_CheckEverCalibrated( void );
+
+#endif /* !MD_TOPSM_PRIVATE_H*/
diff --git a/mcu/driver/sleep_drv/internal/inc/l1_mem_config.h b/mcu/driver/sleep_drv/internal/inc/l1_mem_config.h
new file mode 100644
index 0000000..daf9e2b
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/l1_mem_config.h
@@ -0,0 +1,770 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1_mem_config.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Modem L1 memory configure
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef L1_MEM_CONFIG_H
+#define L1_MEM_CONFIG_H
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define BASE_ADDR_MEM_CONF_FESYS_PAR BASE_ADDR_MODEML1_AO_U_MEM_CONFIG_FESYS
+#define BASE_ADDR_MEM_CONF_DIGRF 0xAF350000 // A-die address
+#if defined(MT6297) || defined(MERCURY)
+#define BASE_ADDR_MEM_CONF_MDRXSYS BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MEM_CONF_TX_CS_NR_PAR BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_MCORE_PAR BASE_ADDR_MCOREPERI_INFRA_TO_MCORE_PAR_AO_SRAM
+#define BASE_ADDR_MEM_CONF_RXCPC_NR_PAR BASE_ADDR_MCOREPERI_INFRA_TO_CPC_PAR_AO
+#define BASE_ADDR_MEM_CONF_RXDBRP_PAR BASE_ADDR_MCOREPERI_INFRA_TO_RXDBRP_PAR_AO
+#define BASE_ADDR_MEM_CONF_RXDDM_NR BASE_ADDR_MCOREPERI_INFRA_TO_RXDDM_PAR_AO
+#define BASE_ADDR_MEM_CONF_VCOREHRAM_PAR BASE_ADDR_VCOREAO_VCOREHRAM_PAR_AO_SRAM
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(CHIP10992)
+#define BASE_ADDR_MEM_CONF_MDRXSYS BASE_ADDR_MODEML1_AO_MDRXSYS_CONFIG_ADR_IF
+#define BASE_ADDR_MEM_CONF_BRPSYS BASE_ADDR_MODEML1_AO_U_BRPSYS_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_TX_CS_NR_PAR BASE_ADDR_MODEML1_AO_U_TX_CS_NR_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_MCORE_PAR BASE_ADDR_MODEML1_AO_U_MCORE_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_RXCPC_NR_PAR BASE_ADDR_MODEML1_AO_U_RXCPC_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_RXDBRP_PAR BASE_ADDR_MODEML1_AO_U_RXDBRP_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_RXDDM_NR BASE_ADDR_MODEML1_AO_U_RXDDM_MEM_CONFIG
+#define BASE_ADDR_MEM_CONF_VCOREHRAM_PAR BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM
+#else
+#error
+#endif
+
+#define MEM_CONF_CSSYS_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x000))
+#define MEM_CONF_CSSYS_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x004))
+#define MEM_CONF_CSSYS_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x008))
+#define MEM_CONF_CSSYS_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x00C))
+#define MEM_CONF_CSSYS_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x010))
+#define MEM_CONF_CSSYS_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x014))
+#define MEM_CONF_CSSYS_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x018))
+#define MEM_CONF_CSSYS_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x01C))
+#define MEM_CONF_CSSYS_SW_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x020))
+#define MEM_CONF_DFESYS_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x024))
+#define MEM_CONF_DFESYS_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x028))
+#define MEM_CONF_DFESYS_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x02C))
+#define MEM_CONF_DFESYS_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x030))
+#define MEM_CONF_DFESYS_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x034))
+#define MEM_CONF_DFESYS_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x038))
+#define MEM_CONF_DFESYS_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x03C))
+#define MEM_CONF_DFESYS_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x040))
+#define MEM_CONF_DFESYS_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x044))
+#define MEM_CONF_DFESYS_PWDN_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x048))
+#define MEM_CONF_DFESYS_PWDN_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x04C))
+#define MEM_CONF_MD2G_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x050))
+#define MEM_CONF_MD2G_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x054))
+#define MEM_CONF_MD2G_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x058))
+#define MEM_CONF_MD2G_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x05C))
+#define MEM_CONF_MD2G_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x060))
+#define MEM_CONF_FESYS_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x064))
+#define MEM_CONF_FESYS_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x068))
+#define MEM_CONF_FESYS_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS_PAR + 0x06C))
+#define BASE_ADDR_MEM_CONF_FESYS_PAR_END (BASE_ADDR_MEM_CONF_FESYS_PAR + 0x70)
+
+#define MEM_CONF_DIGRF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x000))
+#define MEM_CONF_DIGRF_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x004))
+#define MEM_CONF_DIGRF_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x008))
+#define MEM_CONF_DIGRF_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x00C))
+#define MEM_CONF_DIGRF_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x010))
+#define MEM_CONF_DIGRF_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x014))
+#define MEM_CONF_DIGRF_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x018))
+#define MEM_CONF_DIGRF_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x01C))
+#define MEM_CONF_DIGRF_SW_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x020))
+#define MEM_CONF_DIGRF_SW_PWDN_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_DIGRF + 0x024))
+#define BASE_ADDR_MEM_CONF_DIGRF_END (BASE_ADDR_MEM_CONF_DIGRF + 0x28)
+
+#if defined(MT6297) || defined(MERCURY)
+#define MEM_CONF_RAKE_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x000))
+#define MEM_CONF_RAKE_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x004))
+#define MEM_CONF_RAKE_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x008))
+#define MEM_CONF_RAKE_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x00C))
+#define MEM_CONF_RAKE_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x010))
+#define MEM_CONF_RAKE_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x014))
+#define MEM_CONF_RAKE_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x018))
+#define MEM_CONF_INRMM_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x01C))
+#define MEM_CONF_INRMM_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x020))
+#define MEM_CONF_INRMM_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x024))
+#define MEM_CONF_INRMM_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x028))
+#define MEM_CONF_INRMM_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x02C))
+#define MEM_CONF_INRMM_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x030))
+#define MEM_CONF_INRMM_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x034))
+#define MEM_CONF_INRMM_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x038))
+#define MEM_CONF_INRMM_SW_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x03C))
+#define MEM_CONF_INRMM_SW_PWDN_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x040))
+#define MEM_CONF_INRMM_SW_PWDN_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x044))
+#define MEM_CONF_INRMM_SW_PWDN_7_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x048))
+#define MEM_CONF_BRP_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x04C))
+#define MEM_CONF_BRP_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x050))
+#define MEM_CONF_BRP_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x054))
+#define MEM_CONF_BRP_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x058))
+#define MEM_CONF_BRP_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x05C))
+#define MEM_CONF_BRP_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x060))
+#define MEM_CONF_BRP_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x064))
+#define MEM_CONF_BRP_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x068))
+#define MEM_CONF_BRP_SW_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x06C))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x070))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x074))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x078))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x07C))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x080))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x084))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x088))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_7_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x08C))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_8_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x090))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_9_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x094))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_10_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x098))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x09C))
+#define BASE_ADDR_MEM_CONF_MDRXSYS_END (BASE_ADDR_MEM_CONF_MDRXSYS + 0x100)
+
+#define MEM_CONF_CMNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x000))
+#define MEM_CONF_CMNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x004))
+#define MEM_CONF_CMNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x008))
+#define MEM_CONF_CMNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x00C))
+#define MEM_CONF_CMNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x010))
+#define MEM_CONF_CSNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x014))
+#define MEM_CONF_CSNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x018))
+#define MEM_CONF_CSNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x01C))
+#define MEM_CONF_CSNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x020))
+#define MEM_CONF_CSNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x024))
+#define MEM_CONF_RXT2FNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x028))
+#define MEM_CONF_RXT2FNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x02C))
+#define MEM_CONF_RXT2FNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x030))
+#define MEM_CONF_RXT2FNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x034))
+#define MEM_CONF_RXT2FNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x038))
+#define MEM_CONF_RXT2FNR_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x03C))
+#define MEM_CONF_TXNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x040))
+#define MEM_CONF_TXNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x044))
+#define MEM_CONF_TXNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x048))
+#define MEM_CONF_TXNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x04C))
+#define MEM_CONF_TXNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x050))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x054))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x058))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x05C))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x060))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x064))
+#define BASE_ADDR_MEM_CONF_TX_CS_NR_PAR_END (BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x68)
+
+#define MEM_CONF_MCORESYS_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x000))
+#define MEM_CONF_MCORESYS_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x004))
+#define MEM_CONF_MCORESYS_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x008))
+#define MEM_CONF_MCORESYS_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x00C))
+#define MEM_CONF_MCORESYS_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x010))
+#define MEM_CONF_MCOREINFRA_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x014))
+#define MEM_CONF_MCOREINFRA_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x018))
+#define MEM_CONF_MCOREINFRA_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x01C))
+#define MEM_CONF_MCOREINFRA_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x020))
+#define MEM_CONF_MCOREINFRA_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x024))
+#define MEM_CONF_MCOREINFRA_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x028))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x02C))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x030))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x034))
+#define BASE_ADDR_MEM_CONF_MCORE_PAR_END (BASE_ADDR_MEM_CONF_MCORE_PAR + 0x38)
+
+#define MEM_CONF_RXCPCNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x000))
+#define MEM_CONF_RXCPCNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x004))
+#define MEM_CONF_RXCPCNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x008))
+#define MEM_CONF_RXCPCNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x00C))
+#define MEM_CONF_RXCPCNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x010))
+#define MEM_CONF_RXCPC_NR_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x014))
+#define MEM_CONF_RXCPC_NR_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x018))
+#define BASE_ADDR_MEM_CONF_RXCPC_NR_PAR_END (BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x1C)
+
+#define MEM_CONF_RXDBRPNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x000))
+#define MEM_CONF_RXDBRPNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x004))
+#define MEM_CONF_RXDBRPNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x008))
+#define MEM_CONF_RXDBRPNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x00C))
+#define MEM_CONF_RXDBRPNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x010))
+#define MEM_CONF_RXDBRP_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x014))
+#define MEM_CONF_RXDBRP_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x018))
+#define BASE_ADDR_MEM_CONF_RXDBRP_PAR_END (BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x1C)
+
+#define MEM_CONF_RXDDMNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x000))
+#define MEM_CONF_RXDDMNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x004))
+#define MEM_CONF_RXDDMNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x008))
+#define MEM_CONF_RXDDMNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x00C))
+#define MEM_CONF_RXDDMNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x010))
+#define MEM_CONF_RXDDMNR_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x014))
+#define MEM_CONF_RXDDMNR_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x018))
+#define MEM_CONF_RXDDMNR_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x01C))
+#define MEM_CONF_RXCSINR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x020))
+#define MEM_CONF_RXCSINR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x024))
+#define MEM_CONF_RXCSINR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x028))
+#define MEM_CONF_RXCSINR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x02C))
+#define MEM_CONF_RXCSINR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x030))
+#define MEM_CONF_RXCSINR_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x034))
+#define MEM_CONF_RXDDM_NR_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x038))
+#define MEM_CONF_RXDDM_NR_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x03C))
+#define BASE_ADDR_MEM_CONF_RXDDM_NR_END (BASE_ADDR_MEM_CONF_RXDDM_NR + 0x40)
+
+#define MEM_CONF_HRAM_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x000))
+#define MEM_CONF_HRAM_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x004))
+#define MEM_CONF_HRAM_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x008))
+#define MEM_CONF_HRAM_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x00C))
+#define MEM_CONF_HRAM_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x010))
+#define MEM_CONF_HRAM_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x014))
+#define MEM_CONF_VCORESIL2CSYS_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x018))
+#define MEM_CONF_VCORESIL2CSYS_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x01C))
+#define MEM_CONF_VCORESIL2CSYS_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x020))
+#define MEM_CONF_VCORESIL2CSYS_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x024))
+#define MEM_CONF_VCORESIL2CSYS_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x028))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x02C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x030))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x034))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x038))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x03C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x040))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x044))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_7_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x048))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_8_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x04C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_9_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x050))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_10_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x054))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_11_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x058))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_12_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x05C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x060))
+#define BASE_ADDR_MEM_CONF_VCOREHRAM_PAR_END (BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x64)
+
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(CHIP10992)
+#define MEM_CONF_RAKE_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x000))
+#define MEM_CONF_RAKE_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x004))
+#define MEM_CONF_RAKE_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x008))
+#define MEM_CONF_RAKE_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x00C))
+#define MEM_CONF_RAKE_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x010))
+#define MEM_CONF_RAKE_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x014))
+#define MEM_CONF_RAKE_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x018))
+#define MEM_CONF_INRMM_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x01C))
+#define MEM_CONF_INRMM_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x020))
+#define MEM_CONF_INRMM_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x024))
+#define MEM_CONF_INRMM_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x028))
+#define MEM_CONF_INRMM_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x02C))
+#define MEM_CONF_INRMM_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x030))
+#define MEM_CONF_INRMM_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x034))
+#define MEM_CONF_INRMM_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x038))
+#define MEM_CONF_INRMM_SW_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x03C))
+#define MEM_CONF_INRMM_SW_PWDN_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x040))
+#define MEM_CONF_INRMM_SW_PWDN_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x044))
+#define MEM_CONF_INRMM_SW_PWDN_7_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x048))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x04C))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x050))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x054))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x058))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x05C))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x060))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x064))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_7_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x068))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_8_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x06C))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_9_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x070))
+#define MEM_CONF_MDRXSYS_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRXSYS + 0x074))
+#define BASE_ADDR_MEM_CONF_MDRXSYS_END (BASE_ADDR_MEM_CONF_MDRXSYS + 0x78)
+
+#define MEM_CONF_BRP_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x000))
+#define MEM_CONF_BRP_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x004))
+#define MEM_CONF_BRP_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x008))
+#define MEM_CONF_BRP_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x00C))
+#define MEM_CONF_BRP_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x010))
+#define MEM_CONF_BRP_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x014))
+#define MEM_CONF_BRP_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x018))
+#define MEM_CONF_BRP_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x01C))
+#define MEM_CONF_BRP_SW_PWDN_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x020))
+#define MEM_CONF_BRPSYS_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x024))
+#define MEM_CONF_BRPSYS_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_BRPSYS + 0x028))
+#define BASE_ADDR_MEM_CONF_BRPSYS_END (BASE_ADDR_MEM_CONF_BRPSYS + 0x2C)
+
+#define MEM_CONF_CMNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x000))
+#define MEM_CONF_CMNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x004))
+#define MEM_CONF_CMNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x008))
+#define MEM_CONF_CMNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x00C))
+#define MEM_CONF_CMNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x010))
+#define MEM_CONF_CMNR_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x014))
+#define MEM_CONF_CSNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x018))
+#define MEM_CONF_CSNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x01C))
+#define MEM_CONF_CSNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x020))
+#define MEM_CONF_CSNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x024))
+#define MEM_CONF_CSNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x028))
+#define MEM_CONF_RXT2FNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x02C))
+#define MEM_CONF_RXT2FNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x030))
+#define MEM_CONF_RXT2FNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x034))
+#define MEM_CONF_RXT2FNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x038))
+#define MEM_CONF_RXT2FNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x03C))
+#define MEM_CONF_RXT2FNR_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x040))
+#define MEM_CONF_TXNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x044))
+#define MEM_CONF_TXNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x048))
+#define MEM_CONF_TXNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x04C))
+#define MEM_CONF_TXNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x050))
+#define MEM_CONF_TXNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x054))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x058))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x05C))
+#define MEM_CONF_TX_CS_NR_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x060))
+#define BASE_ADDR_MEM_CONF_TX_CS_NR_PAR_END (BASE_ADDR_MEM_CONF_TX_CS_NR_PAR + 0x64)
+
+#define MEM_CONF_MCORESYS_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x000))
+#define MEM_CONF_MCORESYS_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x004))
+#define MEM_CONF_MCORESYS_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x008))
+#define MEM_CONF_MCORESYS_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x00C))
+#define MEM_CONF_MCORESYS_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x010))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x014))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x018))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x01C))
+#define MEM_CONF_MCORE_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MCORE_PAR + 0x020))
+#define BASE_ADDR_MEM_CONF_MCORE_PAR_END (BASE_ADDR_MEM_CONF_MCORE_PAR + 0x24)
+
+#define MEM_CONF_RXCPCNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x000))
+#define MEM_CONF_RXCPCNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x004))
+#define MEM_CONF_RXCPCNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x008))
+#define MEM_CONF_RXCPCNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x00C))
+#define MEM_CONF_RXCPCNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x010))
+#define MEM_CONF_RXCPC_NR_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x014))
+#define MEM_CONF_RXCPC_NR_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x018))
+#define BASE_ADDR_MEM_CONF_RXCPC_NR_PAR_END (BASE_ADDR_MEM_CONF_RXCPC_NR_PAR + 0x1C)
+
+#define MEM_CONF_RXDBRPNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x000))
+#define MEM_CONF_RXDBRPNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x004))
+#define MEM_CONF_RXDBRPNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x008))
+#define MEM_CONF_RXDBRPNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x00C))
+#define MEM_CONF_RXDBRPNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x010))
+#define MEM_CONF_RXDBRP_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x014))
+#define MEM_CONF_RXDBRP_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x018))
+#define BASE_ADDR_MEM_CONF_RXDBRP_PAR_END (BASE_ADDR_MEM_CONF_RXDBRP_PAR + 0x1C)
+
+#define MEM_CONF_RXDDMNR_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x000))
+#define MEM_CONF_RXDDMNR_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x004))
+#define MEM_CONF_RXDDMNR_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x008))
+#define MEM_CONF_RXDDMNR_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x00C))
+#define MEM_CONF_RXDDMNR_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x010))
+#define MEM_CONF_RXDDMNR_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x014))
+#define MEM_CONF_RXDDMNR_SW_PWDN_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x018))
+#define MEM_CONF_RXDDMNR_SW_PWDN_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x01C))
+#define MEM_CONF_RXDDM_NR_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x020))
+#define MEM_CONF_RXDDM_NR_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_RXDDM_NR + 0x024))
+#define BASE_ADDR_MEM_CONF_RXDDM_NR_END (BASE_ADDR_MEM_CONF_RXDDM_NR + 0x28)
+
+#define MEM_CONF_HRAM_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x000))
+#define MEM_CONF_HRAM_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x004))
+#define MEM_CONF_HRAM_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x008))
+#define MEM_CONF_HRAM_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x00C))
+#define MEM_CONF_HRAM_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x010))
+#define MEM_CONF_HRAM_SW_PWDN_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x014))
+#define MEM_CONF_VCORESIL2CSYS_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x018))
+#define MEM_CONF_VCORESIL2CSYS_WAIT_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x01C))
+#define MEM_CONF_VCORESIL2CSYS_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x020))
+#define MEM_CONF_VCORESIL2CSYS_SRAM_CTRL_AO_IDLE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x024))
+#define MEM_CONF_VCORESIL2CSYS_SW_PWDN_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x028))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_0_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x02C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_1_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x030))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_2_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x034))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_3_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x038))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_4_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x03C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_5_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x040))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_6_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x044))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_7_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x048))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_8_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x04C))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_9_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x050))
+#define MEM_CONF_VCOREHRAM_PAR_WRAP_EFUSE_S2P_RX_RESET_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x054))
+#define MEM_CONF_MEMSLP_CONFIG_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x058))
+#define MEM_CONF_MEMSLP_GRP_ENA_SW1SC_1S_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x05C))
+#define MEM_CONF_MEMSLP_GRP_ENA_SW1SC_1C_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x060))
+#define MEM_CONF_MEMSLP_ISOEN_ST_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x064))
+#define MEM_CONF_MEMSLP_MEMOFF_ST_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x068))
+#define MEM_CONF_MEMSLP_MEMUP_ST_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x06C))
+#define MEM_CONF_MEMSLP_ISODIS_ST_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x070))
+#define MEM_CONF_MEMSLP_STATE_ADDR ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x074))
+#define BASE_ADDR_MEM_CONF_VCOREHRAM_PAR_END (BASE_ADDR_MEM_CONF_VCOREHRAM_PAR + 0x78)
+#endif
+
+#define CG_CTRL_RAKE_PWR_AWARE ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x00))
+#define CG_CTRL_RAKE_CG_CON ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x04))
+#define CG_CTRL_RAKE_CG_SET ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x08))
+#define CG_CTRL_RAKE_CG_CLR ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x0C))
+#define CG_CTRL_RAKE_CG_CON_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x10))
+#define CG_CTRL_RAKE_CG_SET_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x14))
+#define CG_CTRL_RAKE_CG_CLR_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x18))
+#define CG_CTRL_RAKE_CG_CON_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x20))
+#define CG_CTRL_RAKE_CG_SET_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x24))
+#define CG_CTRL_RAKE_CG_CLR_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x28))
+
+#elif defined(__MD95__)
+#define BASE_ADDR_MEM_CONF_FESYS BASE_ADDR_MODEML1_AO_FESYS_P2P_TX
+#define BASE_ADDR_MEM_CONF_MDRX BASE_ADDR_MODEML1_AO_MDRX_P2P_TX
+
+#define MEM_CONF_SW_TYPE_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x000))
+#define MEM_CONF_SW_PWDN_C0_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x004))
+#define MEM_CONF_GROUP_PWDN_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x008))
+#define MEM_CONF_WAITING_FLAG_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x00c))
+#define MEM_CONF_SRAMC_AO_IDLE_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x010))
+#define MEM_CONF_SW_TYPE_MD2G ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x100))
+#define MEM_CONF_SW_PWDN_C0_MD2G ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x104))
+#define MEM_CONF_GROUP_PWDN_MD2G ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x108))
+#define MEM_CONF_WAITING_FLAG_MD2G ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x10c))
+#define MEM_CONF_SRAMC_AO_IDLE_MD2G ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x110))
+#define MEM_CONF_SW_TYPE_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x200))
+#define MEM_CONF_SW_PWDN_C0_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x204))
+#define MEM_CONF_SW_PWDN_C1_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x208))
+#define MEM_CONF_SW_PWDN_C2_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x20c))
+#define MEM_CONF_SW_PWDN_C3_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x210))
+#define MEM_CONF_SW_PWDN_C4_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x214))
+#define MEM_CONF_SW_PWDN_C5_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x218))
+#define MEM_CONF_GROUP_PWDN_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x21c))
+#define MEM_CONF_WAITING_FLAG_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x220))
+#define MEM_CONF_SRAMC_AO_IDLE_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x224))
+#define MEM_CONF_SW_TYPE_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x300))
+#define MEM_CONF_SW_PWDN_C0_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x304))
+#define MEM_CONF_SW_PWDN_C1_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x308))
+#define MEM_CONF_SW_PWDN_C2_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x30c))
+#define MEM_CONF_SW_PWDN_C3_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x310))
+#define MEM_CONF_SW_PWDN_C4_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x314))
+#define MEM_CONF_GROUP_PWDN_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x318))
+#define MEM_CONF_WAITING_FLAG_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x31c))
+#define MEM_CONF_SRAMC_AO_IDLE_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x320))
+#define MEM_CONF_fesys_mbist_efuse_s2p_rx_done ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x400))
+#define MEM_CONF_fesys_mbist_efuse_s2p_0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x500))
+#define MEM_CONF_fesys_mbist_efuse_s2p_1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_FESYS + 0x504))
+#define BASE_ADDR_MEM_CONF_FESYS_END (BASE_ADDR_MEM_CONF_FESYS + 0x508)
+
+#define MEM_CONF_SW_TYPE_DMC ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x0))
+#define MEM_CONF_SW_TYPE_SCQ ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x4))
+#define MEM_CONF_SW_TYPE_BRP ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x8))
+#define MEM_CONF_SW_TYPE_BIGRAM ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xc))
+#define MEM_CONF_SW_TYPE_RAKE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x10))
+#define MEM_CONF_DMC_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x14))
+#define MEM_CONF_SCQ_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x18))
+#define MEM_CONF_SCQ_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x1c))
+#define MEM_CONF_BRP_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x20))
+#define MEM_CONF_BRP_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x24))
+#define MEM_CONF_BRP_SW_PWDN_C2 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x28))
+#define MEM_CONF_BRP_SW_PWDN_C3 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x2c))
+#define MEM_CONF_BRP_SW_PWDN_C4 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x30))
+#define MEM_CONF_BIGRAM_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x34))
+#define MEM_CONF_BIGRAM_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x38))
+#define MEM_CONF_BIGRAM_SW_PWDN_C2 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x3c))
+#define MEM_CONF_BIGRAM_SW_PWDN_C3 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x40))
+#define MEM_CONF_BIGRAM_SW_PWDN_C4 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x44))
+#define MEM_CONF_RAKE_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x48))
+#define MEM_CONF_RAKE_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x4c))
+#define MEM_CONF_RAKE_SW_PWDN_C2 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x50))
+#define MEM_CONF_GROUP_PWDN_DMC ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x54))
+#define MEM_CONF_GROUP_PWDN_SCQ ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x58))
+#define MEM_CONF_GROUP_PWDN_BRP ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x5c))
+#define MEM_CONF_GROUP_PWDN_BIGRAM ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x60))
+#define MEM_CONF_GROUP_PWDN_RAKE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x64))
+#define MEM_CONF_BRPSYS_WAIT_C0_4 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x68))
+#define MEM_CONF_INRMM_WAIT_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x74))
+#define MEM_CONF_INRMM_WAIT_C1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x78))
+#define MEM_CONF_INRMM_WAIT_C2 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x7c))
+#define MEM_CONF_INRMM_WAIT_C3 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x80))
+#define MEM_CONF_INRMM_WAIT_C4 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x84))
+#define MEM_CONF_RAKE_WAIT_C0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x9c))
+#define MEM_CONF_RAKE_WAIT_C1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xa0))
+#define MEM_CONF_RAKE_WAIT_C2 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xa4))
+#define MEM_CONF_SRAM_CTRL_AO_IDLE ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xa8))
+#define MEM_CONF_RAKE_PM_CIPHER_EN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xb0))
+#define MEM_CONF_RAKE_PM_CIPHER_LOCK ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xb4))
+#define MEM_CONF_SCQ_SPM_CIPHER_EN ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xc0))
+#define MEM_CONF_SCQ_SPM_CIPHER_LOCK ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xc4))
+#define MEM_CONF_CK_IDLE_MASK ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xd0))
+#define MEM_CONF_CK_IDLE_DBG_MASK ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xd4))
+#define MEM_CONF_reg_debugapb_timeout_ctrl ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0xe0))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_rx_done ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x400))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_0 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x500))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_1 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x504))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_2 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x508))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_3 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x50c))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_4 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x510))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_5 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x514))
+#define MEM_CONF_mdrxsys_mbist_efuse_s2p_6 ((volatile kal_uint32*)(BASE_ADDR_MEM_CONF_MDRX + 0x518))
+#define BASE_ADDR_MEM_CONF_MDRX_END (BASE_ADDR_MEM_CONF_MDRX + 0x51c)
+
+#define CG_CTRL_RAKE_PWR_AWARE ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x00))
+#define CG_CTRL_RAKE_CG_CON ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x04))
+#define CG_CTRL_RAKE_CG_SET ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x08))
+#define CG_CTRL_RAKE_CG_CLR ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x0C))
+#define CG_CTRL_RAKE_CG_CON_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x10))
+#define CG_CTRL_RAKE_CG_SET_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x14))
+#define CG_CTRL_RAKE_CG_CLR_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x18))
+#define CG_CTRL_RAKE_CG_CON_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x20))
+#define CG_CTRL_RAKE_CG_SET_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x24))
+#define CG_CTRL_RAKE_CG_CLR_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x28))
+
+#elif defined(__MD93__)
+//Register for FESYS SRAM control
+#define MEM_CONF_SW_TYPE_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x000))
+#define MEM_CONF_SW_PWDN_C0_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x004))
+#define MEM_CONF_GROUP_PWDN_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x008))
+#define MEM_CONF_WAITING_FLAG_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x00c))
+#define MEM_CONF_MBIST_MEM_ISOINTB_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x010))
+#define MEM_CONF_MBIST_MEM_PD_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x014))
+#define MEM_CONF_MBIST_PROT_STA_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x018))
+#define MEM_CONF_SRAMC_AO_IDLE_MDL1AO ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x01c))
+#define MEM_CONF_SW_TYPE_MD2G ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x100))
+#define MEM_CONF_SW_PWDN_C0_MD2G ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x104))
+#define MEM_CONF_GROUP_PWDN_MD2G ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x108))
+#define MEM_CONF_WAITING_FLAG_MD2G ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x10c))
+#define MEM_CONF_SRAMC_AO_IDLE_MD2G ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x110))
+#define MEM_CONF_SW_TYPE_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x200))
+#define MEM_CONF_SW_PWDN_C0_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x204))
+#define MEM_CONF_SW_PWDN_C1_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x208))
+#define MEM_CONF_SW_PWDN_C2_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x20c))
+#define MEM_CONF_SW_PWDN_C3_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x210))
+#define MEM_CONF_SW_PWDN_C4_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x214))
+#define MEM_CONF_GROUP_PWDN_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x218))
+#define MEM_CONF_WAITING_FLAG_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x21c))
+#define MEM_CONF_SRAMC_AO_IDLE_TXSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x220))
+#define MEM_CONF_SW_TYPE_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x300))
+#define MEM_CONF_SW_PWDN_C0_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x304))
+#define MEM_CONF_SW_PWDN_C1_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x308))
+#define MEM_CONF_SW_PWDN_C2_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x30c))
+#define MEM_CONF_SW_PWDN_C3_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x310))
+#define MEM_CONF_SW_PWDN_C4_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x314))
+#define MEM_CONF_GROUP_PWDN_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x318))
+#define MEM_CONF_WAITING_FLAG_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x31c))
+#define MEM_CONF_SRAMC_AO_IDLE_CSSYS ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x320))
+#define MEM_CONF_SW_TYPE_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x400))
+#define MEM_CONF_SW_PWDN_C0_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x404))
+#define MEM_CONF_GROUP_PWDN_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x408))
+#define MEM_CONF_WAITING_FLAG_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x40c))
+#define MEM_CONF_SRAMC_AO_IDLE_RXDFE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_FESYS_P2P_TX + 0x410))
+
+//Register for MDRX SRAM control
+#define MEM_CONF_DMC_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x00))
+#define MEM_CONF_SCQ_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x04))
+#define MEM_CONF_BRP_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x08))
+#define MEM_CONF_BIGRAM_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x0c))
+#define MEM_CONF_RAKE_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x10))
+#define MEM_CONF_DMC_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x14))
+#define MEM_CONF_SCQ_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x18))
+#define MEM_CONF_SCQ_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x1c))
+#define MEM_CONF_BRP_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x20))
+#define MEM_CONF_BRP_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x24))
+#define MEM_CONF_BRP_SW_PWDN_C2 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x28))
+#define MEM_CONF_BRP_SW_PWDN_C3 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x2c))
+#define MEM_CONF_BRP_SW_PWDN_C4 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x30))
+#define MEM_CONF_BIGRAM_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x34))
+#define MEM_CONF_BIGRAM_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x38))
+#define MEM_CONF_BIGRAM_SW_PWDN_C2 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x3c))
+#define MEM_CONF_BIGRAM_SW_PWDN_C3 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x40))
+#define MEM_CONF_BIGRAM_SW_PWDN_C4 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x44))
+#define MEM_CONF_RAKE_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x48))
+#define MEM_CONF_RAKE_SW_PWDN_C1 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x4c))
+#define MEM_CONF_RAKE_SW_PWDN_C2 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x50))
+#define MEM_CONF_DMC_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x54))
+#define MEM_CONF_SCQ_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x58))
+#define MEM_CONF_BRP_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x5c))
+#define MEM_CONF_BIGRAM_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x60))
+#define MEM_CONF_RAKE_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x64))
+#define MEM_CONF_DMC_WAIT_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x68))
+#define MEM_CONF_BRAM_WAIT_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x74))
+#define MEM_CONF_BRAM_WAIT_C1 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x78))
+#define MEM_CONF_BRAM_WAIT_C2 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x7c))
+#define MEM_CONF_BRAM_WAIT_C3 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x80))
+#define MEM_CONF_BRAM_WAIT_C4 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x84))
+#define MEM_CONF_RAKE_WAIT_C0 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0x9c))
+#define MEM_CONF_RAKE_WAIT_C1 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xa0))
+#define MEM_CONF_RAKE_WAIT_C2 ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xa4))
+#define MEM_CONF_SRAM_CTRL_AO_IDLE ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xa8))
+#define MEM_CONF_RAKE_PM_CIPHER_EN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xb0))
+#define MEM_CONF_RAKE_PM_CIPHER_LOCK ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xb4))
+#define MEM_CONF_SCQ_SPM_CIPHER_EN ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xc0))
+#define MEM_CONF_SCQ_SPM_CIPHER_LOCK ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xc4))
+#define MEM_CONF_CK_IDLE_MASK ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xd0))
+#define MEM_CONF_CK_IDLE_DBG_MASK ((volatile kal_uint32*)(BASE_ADDR_MODEML1_AO_MDRX_P2P_TX + 0xd4))
+
+//Register for RAKE CLK control
+#define CG_CTRL_RAKE_PWR_AWARE ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x00))
+#define CG_CTRL_RAKE_CG_CON ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x04))
+#define CG_CTRL_RAKE_CG_SET ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x08))
+#define CG_CTRL_RAKE_CG_CLR ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x0C))
+#define CG_CTRL_RAKE_CG_CON_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x10))
+#define CG_CTRL_RAKE_CG_SET_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x14))
+#define CG_CTRL_RAKE_CG_CLR_1X ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x18))
+#define CG_CTRL_RAKE_CG_CON_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x20))
+#define CG_CTRL_RAKE_CG_SET_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x24))
+#define CG_CTRL_RAKE_CG_CLR_DO ((volatile kal_uint32*)(BASE_ADDR_RAKESYS_GLOBAL_CON + 0x28))
+#endif /* defined(__MD93__) */
+
+#if defined(__MD97__) || defined(__MD97P__)
+#if defined(MT6297) || defined(MERCURY)
+#define MEM_CONF_CSSYS_SW_PWDN_MASK 0x3F
+#define MEM_CONF_DFESYS_SW_PWDN_MASK 0x3FFFF
+#define MEM_CONF_MD2G_SW_PWDN_MASK 0x3
+#define MEM_CONF_RAKE_SW_PWDN_MASK 0x7F
+#define MEM_CONF_INRMM_SW_PWDN_MASK 0x3FFF
+#define MEM_CONF_BRP_SW_PWDN_MASK 0xFF
+#define MEM_CONF_CMNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_CSNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_RXT2FNR_SW_PWDN_MASK 0x3
+#define MEM_CONF_TXNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_MCORESYS_SW_PWDN_MASK 0x3F
+#define MEM_CONF_MCOREINFRA_SW_PWDN_MASK 0x1
+#define MEM_CONF_RXCPCNR_SW_PWDN_MASK 0x3
+#define MEM_CONF_RXDBRPNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_RXDDMNR_SW_PWDN_MASK 0xF
+#define MEM_CONF_RXCSINR_SW_PWDN_MASK 0x3
+#define MEM_CONF_HRAM_SW_PWDN_MASK 0x7
+#define MEM_CONF_VCORESIL2CSYS_SW_PWDN_MASK 0x7
+#define MEM_CONF_DIGRF_SW_PWDN_MASK 0x3
+
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(CHIP10992)
+#define MEM_CONF_CSSYS_SW_PWDN_MASK 0x3F
+#define MEM_CONF_DFESYS_SW_PWDN_MASK 0x3FFFF
+#define MEM_CONF_MD2G_SW_PWDN_MASK 0x3
+#define MEM_CONF_RAKE_SW_PWDN_MASK 0x7F
+#define MEM_CONF_INRMM_SW_PWDN_MASK 0x3FFF
+#define MEM_CONF_BRP_SW_PWDN_MASK 0xFF
+#define MEM_CONF_CMNR_SW_PWDN_MASK 0x3
+#define MEM_CONF_CSNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_RXT2FNR_SW_PWDN_MASK 0x3
+#define MEM_CONF_TXNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_MCORESYS_SW_PWDN_MASK 0xF
+#define MEM_CONF_RXCPCNR_SW_PWDN_MASK 0x3
+#define MEM_CONF_RXDBRPNR_SW_PWDN_MASK 0x1
+#define MEM_CONF_RXDDMNR_SW_PWDN_MASK 0xF
+#define MEM_CONF_HRAM_SW_PWDN_MASK 0xFF
+#define MEM_CONF_VCORESIL2CSYS_SW_PWDN_MASK 0x7
+#define MEM_CONF_DIGRF_SW_PWDN_MASK 0x7
+#endif
+
+#define CG_CTRL_RAKE_CG_CON_MASK 0x7 /* bit[0]: rake_core_cg_con; bit[1]: rake_brif_cg_con; bit[2]: rake_mem_cg_con */
+
+#elif defined(__MD95__)
+#define MEM_CONF_RXDFE_SW_PWDN_MASK 0x3
+#define MEM_CONF_MD2G_SW_PWDN_MASK 0x3
+#define MEM_CONF_TXSYS_SW_PWDN_MASK 0x7FF
+#define MEM_CONF_CSSYS_SW_PWDN_MASK 0x3F
+
+#define MEM_CONF_DMC_SW_PWDN_MASK 0xF
+#define MEM_CONF_SCQ_SW_PWDN_MASK 0xFFF
+#define MEM_CONF_BRP_SW_PWDN_MASK 0x7F
+#define MEM_CONF_BIGRAM_SW_PWDN_MASK 0x3F
+#define MEM_CONF_RAKE_SW_PWDN_MASK 0xFF
+
+#define CG_CTRL_RAKE_CG_CON_MASK 0x7 /* bit[0]: rake_core_cg_con; bit[1]: rake_brif_cg_con; bit[2]: rake_mem_cg_con */
+
+#elif defined(__MD93__)
+#define MEM_CONF_RAKE_SW_PWDN_MASK 0xFF
+
+#define CG_CTRL_RAKE_CG_CON_MASK 0x3 /* bit[0]: rake_core_cg_con; bit[1]: rake_brif_cg_con */
+#endif
+
+extern void MEM_CONFIG_Modeml1sysInit(void);
+extern void MEM_CONFIG_Modeml1sysPowerDown(void);
+
+extern void CG_CTRL_Init(void);
+
+#endif /* L1_MEM_CONFIG_H */
diff --git a/mcu/driver/sleep_drv/internal/inc/mem_config.h b/mcu/driver/sleep_drv/internal/inc/mem_config.h
new file mode 100644
index 0000000..73faaaf
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/mem_config.h
@@ -0,0 +1,196 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sleep_drv_internal.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Sleep mode driver setting.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef MEM_CONFIG_H
+#define MEM_CONFIG_H
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+#if defined(__MD93__)
+
+/* ============================= Register for SRAM control ================================== */
+#define CORE0_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_CORE0_MEM_CONFIG + 0x0 ))
+#define CORE1_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_CORE1_MEM_CONFIG + 0x0 ))
+#define USIP0_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_USIP0_MEM_CONFIG + 0x0 ))
+#define MDCORE_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG + 0x0 ))
+#define MDINFRA_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG + 0x0 ))
+#define MDMML2_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG + 0x0 ))
+#define MDPERISYS_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG + 0x0 ))
+#define MDPERISYS_MEM_CONF_SW_PWDN_C0 ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG + 0x10))
+#define MDPERISYS_MEM_CONF_GROUP_PWDN ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDPERISYS_MEM_CONFIG + 0x20))
+/* ============================= Register for SRAM control end =============================== */
+#elif defined(__MD95__)
+#define CORE0_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_CORE0_MEM_CONFIG + 0x0 ))
+#define CORE1_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_CORE1_MEM_CONFIG + 0x0 ))
+#define CORE2_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_CORE2_MEM_CONFIG + 0x0 ))
+#define USIP0_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_USIP0_MEM_CONFIG + 0x0 ))
+#define MDCORE_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDCORE_MEM_CONFIG + 0x0 ))
+#define MDINFRA_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDINFRA_MEM_CONFIG + 0x0 ))
+#define MDMML2_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_ADDR_MDPERI_MDMML2_MEM_CONFIG + 0x0 ))
+#elif defined(__MD97__)
+#define USIP_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x0 ))
+#define MDCORESYS_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x14 ))
+#define SHAOLIN_CORE0_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x38 ))
+#define SHAOLIN_CORE1_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x4C ))
+#define SHAOLIN_CORE2_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x60 ))
+#define SHAOLIN_CORE3_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x74 ))
+#if defined(MT6297_IA)
+#define IA_CORE0_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x88 ))
+#define IA_CORE1_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x9C ))
+#define IA_CORE2_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0xB0 ))
+#define IA_CORE3_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0xC4 ))
+#endif
+#if defined(MT6297) || defined(MT6297_IA)
+#define NRL2SYS_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0xD8 ))
+#else
+#define NRL2SYS_MEM_CONF_SW_TYPE ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF + 0x88 ))
+#endif
+#elif defined(__MD97P__)
+#define USIP_MEM_CONF_SW_TYPE
+#define MDCORESYS_MEM_CONF_SW_TYPE
+#define SHAOLIN_CORE0_MEM_CONF_SW_TYPE
+#define SHAOLIN_CORE1_MEM_CONF_SW_TYPE
+#define SHAOLIN_CORE2_MEM_CONF_SW_TYPE
+#define SHAOLIN_CORE3_MEM_CONF_SW_TYPE
+#define IA_CORE0_MEM_CONF_SW_TYPE
+#define IA_CORE1_MEM_CONF_SW_TYPE
+#define IA_CORE2_MEM_CONF_SW_TYPE
+#define IA_CORE3_MEM_CONF_SW_TYPE
+#define NRL2SYS_MEM_CONF_SW_TYPE
+#else
+ #error "no chip match"
+#endif
+
+extern void MEM_CONFIG_Init(void);
+extern void MEM_CONFIG_Sram_Power_Down(void);
+
+#endif /* MEM_CONFIG_H */
+
diff --git a/mcu/driver/sleep_drv/internal/inc/mips_cpc_private.h b/mcu/driver/sleep_drv/internal/inc/mips_cpc_private.h
new file mode 100644
index 0000000..3a77452
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/mips_cpc_private.h
@@ -0,0 +1,11 @@
+/*This header file add necessary declarations for MIPS CPC*/
+
+#ifndef MIPS_CPC_PRIVATE_H
+#define MIPS_CPC_PRIVATE_H
+
+#if defined(MT6763)
+
+#endif
+
+#endif
+
diff --git a/mcu/driver/sleep_drv/internal/inc/ostd_private.h b/mcu/driver/sleep_drv/internal/inc/ostd_private.h
new file mode 100644
index 0000000..403cc5a
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/ostd_private.h
@@ -0,0 +1,1204 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ostd_private.h
+ *
+ * Project:
+ * --------
+ * MTK6276
+ *
+ * Description:
+ * ------------
+ * This is the driver layer and corresponding Sleep Mode of ARM OS Timer HW
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef OSTD_PRIVATE_H
+#define OSTD_PRIVATE_H
+
+#include "reg_base.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "ostd_public.h"
+#include "sleep_drv_internal.h" // for sleep driver API and EXTENDED_SLEEP_HANDLE_SUPPORT
+#include "sleepdrv_common.h"
+#include "us_timer.h"
+
+/*****************************************************************************
+* All DEFINEs
+*****************************************************************************/
+#if defined(__MAUI_BASIC__) || defined(__UDVT__)
+#define IS_SW_LOAD_L1_EXIST 0 /* L1 module not exist in Basic Load and UDVT Load */
+#else
+#define IS_SW_LOAD_L1_EXIST 1 /* especially for UDVT */
+#endif /* defined(__MAUI_BASIC__) || defined(__UDVT__) */
+
+/******************** Step-Logging Definition ********************/
+typedef enum
+{
+ OSTD_CHKSLP_Enter = 0x01,
+ OSTD_CHKSLP_CSC_Enter = 0x11,
+ OSTD_CHKSLP_CSC_Trig_PAUSE_CMD = 0x12,
+ OSTD_CHKSLP_CSC_In_WAIT = 0x1F,
+ OSTD_CHKSLP_CSC_Not_In_WAIT = 0x1E,
+ OSTD_CHKSLP_OST_Enter = 0x21,
+ OSTD_CHKSLP_OST_Core1_NotReady = 0x2E,
+ OSTD_CHKSLP_OST_Chk_Infinite_Sleep = 0x31,
+ OSTD_CHKSLP_OST_RAT_Not_Infinite_Sleep = 0x3E,
+ OSTD_CHKSLP_OST_Chk_Min_SlpFrm = 0x41,
+ OSTD_CHKSLP_OST_Less_than_Min_SlpFrm = 0x4E,
+ OSTD_CHKSLP_OST_CHK_USB_PENDING = 0x4F,
+ OSTD_CHKSLP_OST_USB_PENDING = 0x50,
+ OSTD_CHKSLP_OST_Chk_EINT_IRQ = 0x51,
+ OSTD_CHKSLP_OST_Detecting_EINT_IRQ = 0x5E,
+ OSTD_CHKSLP_OST_Chk_ResReq = 0x61,
+ OSTD_CHKSLP_OST_Detecting_ResReq = 0x6E,
+ OSTD_CHKSLP_OST_EPOF_MaskWakeUp = 0x70,
+ OSTD_CHKSLP_OST_Issue_PauseCmd = 0x71,
+ OSTD_CHKSLP_OST_UFN_Less_than_Min_SlpFrm_Abort = 0x7E,
+ OSTD_CHKSLP_OST_WakeUp_Event_Abort = 0x7E,
+ OSTD_CHKSLP_OST_PauseCmd_Successful = 0x81,
+ OSTD_CHKSLP_OST_MaskIRQ = 0x82,
+ OSTD_CHKSLP_OST_GetCurrVoltInPMICStep = 0x83,
+ OSTD_CHKSLP_OST_EFUN_RF_OFF = 0x91,
+ OSTD_CHKSLP_OST_EPOF_RF_OFF = 0xA1,
+ OSTD_CHKSLP_OST_EPOF_Return_Dormant = 0xAF,
+ OSTD_CHKSLP_OST_Return_Dormant = 0xFF
+} OSTD_ChkSlp_Step_e;
+
+typedef enum
+{
+ OSTD_INTERRUPT_Enter = 0x01,
+ OSTD_INTERRUPT_Get_Sleep_Info = 0x11,
+ OSTD_INTERRUPT_Record_Sleep_Info = 0x12,
+ OSTD_INTERRUPT_Record_LPM = 0x1E,
+ OSTD_INTERRUPT_Disable_IRQ = 0x1F,
+ OSTD_INTERRUPT_Check_Lock_Status = 0x21,
+ OSTD_INTERRUPT_Print_Trace = 0x2E,
+ OSTD_INTERRUPT_Check_Infinite_Sleep = 0x31,
+ OSTD_INTERRUPT_DCXO_LPM = 0x3E,
+ OSTD_INTERRUPT_Unmask_IRQ = 0x41,
+ OSTD_INTERRUPT_Check_IRQ_Status = 0x4E,
+ OSTD_INTERRUPT_KAL_Resume = 0x51,
+} OSTD_Interrupt_Step_e;
+
+/******************** Register Definition ********************/
+#define OST_BASE BASE_MADDR_MDOSTIMER /* 0xBF840000 is used for 6290 CR4 */
+#define CMD_MAGIC_VALUE 0x057D0000
+
+/*=========================================
+** OSTIMER Version Control Register:
+**
+** [31:0] CODA_VERSION
+**
+**=========================================*/
+#define OSTIMER_CODE_VERSION ((volatile kal_uint32*)(OST_BASE + 0x00))
+/*=========================================
+** OS Timer Control Register:
+**
+** [2:0] OST_CON
+** Bit 2 : OST_DBG
+** Enable OST wakeup debug function
+** 0: Disabled
+** 1: Enabled
+** Bit 1 : UFN_DOWN
+** Enable OST_UFN Down count
+** 0: Disable OST_UFN down count
+** 1: Enable OST_UFN down count
+** Bit 0 : OST_EN
+** OS Timer Enable
+** 0: OS Timer is disabled. Then all internal timers are stop.
+** 1: OS Timer is enabled. Software has to ensure OST_AFN, OST_UFN,
+** OST_FRM are configured before enable OS Timer.
+**=========================================*/
+#define OST_CON ((volatile kal_uint32*)(OST_BASE + 0x10))
+/*=========================================
+** OS Timer Command:
+**
+** [15:15] UPDATE_CON
+** Update OST_CON when OST_WR command is active.
+** (key protected , should write with upper words : 16'h6291)
+** [14:14] UPDATE_AFN
+** Update OST_AFN when OST_WR command is active.
+** (key protected , should write with upper words : 16'h6291)
+** [13:13] UPDATE_UFN
+** Update OST_UFN when OST_WR command is active.
+** (key protected , should write with upper words : 16'h6291)
+** [2:0] OST_CMD
+** Bit2:OST_WR
+** Write 1 at this bit to update bus clock domain OS Timer configuration into OST SYSCLK domain
+** (key protected , should write with upper words : 16'h6291)
+** Bit1: No Use
+** Bit0 :PAUSE_STR
+** Write 1 at this bit to enable OS Timer pause function. Software has to ensure OST_CMD. OST_WR is completed before next software
+** pause sequence.
+** (key protected , should write with upper words : 16'h6291)
+**=========================================*/
+#define OST_CMD ((volatile kal_uint32*)(OST_BASE + 0x14))
+/*=========================================
+** OS Timer Status:
+**
+** [19:16] OST_STATE
+** OS Timer State machine
+** 4'b0001: Normal (non sleep)
+** 4'b0010: Pre clock-off
+** 4'b0100: clock-off
+** 4'b1000: Settle (handling pause interrupt)
+** [15:15] CPU_SLEEP
+** The processor is in sleep mode (For debug purpose)
+** 0: active
+** 1: sleep
+** [6:6] AFN_DLY_OVERFLOW
+** AFN_DLY Counter is overflow. This bit is cleared when AFN is updated.
+** 0: no overflow
+** 1: overflow
+** [4:3] PAUSE_REQ_ST
+** An OS timer pause request is pending. A pause command will be completed when pause command is set,
+** 00: last pause command request is not completed yet (WFI not yet arrived and no wakeup source)
+** 01: last pause command request is completed and OST enters pause mode
+** 10: last pause command request is completed due to some wakeup source goes high
+** 11: last pause command request is completed since currunt UFN count reaches UFN_FRM_NUM
+** [1:1] OST_CMD_BUSY
+** OST Command is complete. It take several clocks from OST_CMD is updated to command take active.
+** 0: OST command is not completed
+** 1: OST command is completed
+** [0:0] OST_PAUSE
+** OS Timer Status
+** 0: OST is in Pause mode
+** 1: OST is in normal mode
+**=========================================*/
+#define OST_STA ((volatile kal_uint32*)(OST_BASE + 0x18))
+/*=========================================
+** OS Timer Frame Duration:
+**
+** [13:0] OST_FRM
+** Specify OS Timer frame duration by micron second resolution.
+** The Max duration is 16ms, and Min duration is 1ms. This register should be set before OS timer is enabled. Hardware will set the
+** OST_ISR[0] periodically at frame duration period when OS timer is enable.
+**=========================================*/
+#define OST_FRM ((volatile kal_uint32*)(OST_BASE + 0x1C))
+/*=========================================
+** Pause Duration:
+**
+** [15:12] OST_FRM_NUM
+** 1.If UFN_CNT <= OST_FRAM_NUM, the pause state will leave pre-off mode and enter off mode
+** 2.OST_FRM_NUM * OST_FRM should be bigger than system settling time. (Pause Duration in unit of Frame Duration)
+** [8:0] OST_FRM_F32K
+** The Pause Duration in cycle of 32KHz, counted by TOPSM when OSTIMER in OFF state.
+** Recommanded Coversion between OST_FRM_F32K and OST_FRM_NUM :
+** OST_FRM_32k = (OST_FRM_NUM-1)*OST_FRM*(32.768K/1M) - 4
+**=========================================*/
+#define OST_PAUSE_DUR ((volatile kal_uint32*)(OST_BASE + 0x20))
+/*=========================================
+** OS Timer Un-Alignment Frame Number:
+**
+** [31:0] OST_UFN
+** Specify OS Timer un-alignment event frame number count.
+** This register value is updated to OS timer only when OST_CMD.OST_WR is set. The read value of this register maybe is not the
+** current OS time Un-alignment Frame Number.
+** Hardware will down count OST_UFN counter at frame time out, and stop to down count when the current value is 0. OST_ISR[2] will be
+** set when OST_AFN changed from 1 to 0 at frame time out. When OS Timer is in pause mode, this counter is still active, and wakeup
+** OS timer when the OST_UFN becoming zero at frame time out boundary.
+** Software should enable OS timer pause mode when OST_UFN is larger than OST_FRM_NUM , or the pause command will be aborted(with
+** pause abort interrupt) by Hardware.
+** OST_UFN is NOT current Hardware UFN down counter value, and Software can't read this register directly. Software can only read
+** current Frame Number thought OST_UFN_R register, and there is synchronization latency from OST_UFN to OST_UFN_R.
+**=========================================*/
+#define OST_UFN ((volatile kal_uint32*)(OST_BASE + 0x24))
+/*=========================================
+** OS Timer Alignment Frame Number:
+**
+** [31:0] OST_AFN
+** Specify OS Timer Alignment event frame number count.
+** This register value is updated to OS timer only when OST_CMD.OST_WR is set. The read value of this register maybe is not the
+** current OS time Alignment Frame Number.
+** Hardware will down count OST_AFN counter at frame time out, and stop to down count when the current value is 0. OST_ISR[1] will be
+** set when OST_AFN changed from 1 to 0 at frame time out when OS timer is in normal mode.
+** OST_AFN is NOT current Hardware AFN down counter value, and Software can't read this register directly. Software can only read
+** current Frame Number thought OST_AFN_R register, and there is synchronization latency from OST_AFN to OST_AFN_R.
+**=========================================*/
+#define OST_AFN ((volatile kal_uint32*)(OST_BASE + 0x28))
+/*=========================================
+** OS Timer Alignment Frame Delay Number Count:
+**
+** [31:0] OST_AFN_DLY
+** (No Reset Default Value)
+** This register specifies the OS Timer Alignment event frame delay count due to OS timer pause mode. This register will be
+** automatically updated. The uncerntainty between this value and real value in OS Timer is one frame.
+**=========================================*/
+#define OST_AFN_DLY ((volatile kal_uint32*)(OST_BASE + 0x2C))
+/*=========================================
+** Current OS Timer Un-Alignment Frame Number:
+**
+** [31:0] UFN_CNT_R
+** (No Reset Default Value)
+** This register specifies the OS Timer current Un-Alignment frame number. This register will be automatically updated. The
+** uncertainty between this value and real value in OS Timer is one frame.
+**=========================================*/
+#define OST_UFN_R ((volatile kal_uint32*)(OST_BASE + 0x30))
+/*=========================================
+** Current OS Timer Alignment Frame Number:
+**
+** [31:0] AFN_CNT_R
+** (No Reset Default Value)
+** This register specifies the OS Timer current Alignment frame number. This register will be automatically updated. The uncertainty
+** between this value and real value in OS Timer is one frame.
+**=========================================*/
+#define OST_AFN_R ((volatile kal_uint32*)(OST_BASE + 0x34))
+/*=========================================
+** OST TIMER Counter:
+**
+** [31:0] OST_TIMER_CNT_R
+** (No Reset Default Value)
+** Start Count when ostimer enable, unit is one os tick and count from 0, reset to 0 when OS timer disable. This register will be
+** automatically updated. The uncertainty between this value and real value in OS Timer is one frame.
+**=========================================*/
+#define OST_TIMER_CNT_R ((volatile kal_uint32*)(OST_BASE + 0x38))
+/*=========================================
+** OS Timer Interrupt Mask:
+**
+** [4:0] OST_INT_MASK
+** This register specifies the OS Timer interrupt mask control. (1 means mask enable)
+** Bit 0: mask OS Timer Frame Time Out interrupt
+** Bit 1: mask OS Timer Alignment Frame Time Out interrupt
+** Bit 2: mask OS Timer Un-Alignment Frame Time Out interrupt
+** Bit 3: mask OS Timer Pause Abort interrupt
+** Bit 4: mask OS Timer Pause Interrupt interrupt
+**=========================================*/
+#define OST_INT_MASK ((volatile kal_uint32*)(OST_BASE + 0x40))
+/*=========================================
+** OSTIMER Trigger Watch Dog Reset:
+**
+** [0:0] reg_en_ostimer_trig_watch_dog_reset
+** Enable Ostimer trigger Watch Dog reset after F32k_wakeup_event (1T f32k_ck pulse)
+** (key protected , should write with upper words : 16'h6291)
+** (no use in this project)
+**=========================================*/
+#define OSTIMER_TRIG_WATCH_DOG_RESET ((volatile kal_uint32*)(OST_BASE + 0x44))
+/*=========================================
+** OS Timer Interrupt Status:
+**
+** [4:0] OST_ISR
+** BIT0 : OS Timer Frame Time Out interrupt Status
+** BIT1 : OS Timer Alignment Frame Time Out interrupt Status
+** BIT2 : OS Timer Un-Alignment Frame Time Out interrupt Status
+** BIT3 : OS Timer Pause Abort interrupt Status
+** BIT4 : OS Timer Pause Interrupt interrupt Status
+** This register specifies the OS Timer interrupt status. Software has write 1 at the corresponding bit to clear the interrupt status
+** bit. OSR_ISR[2-0] are also cleared when OSR_WR command is executed and AFN, UFN are updated
+**=========================================*/
+#define OST_ISR ((volatile kal_uint32*)(OST_BASE + 0x50))
+/*=========================================
+** OST F32K Wakeup Event Mask:
+**
+** [31:0] OST_F32K_EVENT_MASK_31_0
+** Specify which wakeup event will be masked to wakeup OS timer during OS timer pause mode. (for wakeup source 31~0)
+**=========================================*/
+#define OST_F32K_EVENT_MASK_1 ((volatile kal_uint32*)(OST_BASE + 0x60))
+/*=========================================
+** OST F32K Wakeup Event Mask:
+**
+** [31:0] OST_F32K_EVENT_MASK_63_32
+** Specify which wakeup event will be masked to wakeup OS timer during OS timer pause mode. (for wakeup source 63~32)
+**=========================================*/
+#define OST_F32K_EVENT_MASK_2 ((volatile kal_uint32*)(OST_BASE + 0x64))
+/*=========================================
+** OST F32K Wakeup Event Status:
+**
+** [31:0] OST_F32K_WAKEUP_STA_31_0
+** OST F32K Wakeup Event Status (for wakeup source 31~0)
+**=========================================*/
+#define OST_F32K_WAKEUP_STA_1 ((volatile kal_uint32*)(OST_BASE + 0x70))
+/*=========================================
+** OST F32K Wakeup Event Status:
+**
+** [31:0] OST_F32K_WAKEUP_STA_63_32
+** OST F32K Wakeup Event Status (for wakeup source 63~32)
+**=========================================*/
+#define OST_F32K_WAKEUP_STA_2 ((volatile kal_uint32*)(OST_BASE + 0x74))
+/*=========================================
+** OST NON-F32K Wakeup Event Mask:
+**
+** [31:0] OST_NON_F32K_EVENT_MASK_31_0
+** Specify which wakeup event will be masked to wakeup OS timer before OS timer pause mode, just for sleep protection (for wakeup
+** source 31~0)
+**=========================================*/
+#define OST_NON_F32K_EVENT_MASK_1 ((volatile kal_uint32*)(OST_BASE + 0x80))
+/*=========================================
+** OST NON-F32K Wakeup Event Mask:
+**
+** [31:0] OST_NON_F32K_EVENT_MASK_63_42
+** Specify which wakeup event will be masked to wakeup OS timer before OS timer pause mode, just for sleep protection (for wakeup
+** source 63~32)
+**=========================================*/
+#define OST_NON_F32K_EVENT_MASK_2 ((volatile kal_uint32*)(OST_BASE + 0x84))
+/*=========================================
+** OST Non-F32K Wakeup Event Status:
+**
+** [31:0] OST_NON_F32K_WAKEUP_STA_31_0
+** OST Non-F32K Wakeup Event Status (for wakeup source 31~0)
+**=========================================*/
+#define OST_NON_F32K_WAKEUP_STA_1 ((volatile kal_uint32*)(OST_BASE + 0x90))
+/*=========================================
+** OST Non-F32K Wakeup Event Status:
+**
+** [31:0] OST_NON_F32K_WAKEUP_STA_63_32
+** OST Non-F32K Wakeup Event Status (for wakeup source 63~32)
+**=========================================*/
+#define OST_NON_F32K_WAKEUP_STA_2 ((volatile kal_uint32*)(OST_BASE + 0x94))
+/*=========================================
+** OST Non-F32K Wakeup Event Status:
+**
+** [31:0] OST_NON_F32K_WAKEUP_STA_31_0
+** Wakeup source level polarity selection (for wakeup source 31~0)
+** 0: normal polarity
+** 1: inverse polarity
+**=========================================*/
+#define OST_WAKEUP_POLARITY_1 ((volatile kal_uint32*)(OST_BASE + 0xA0))
+/*=========================================
+** OST Non-F32K Wakeup Event Status:
+**
+** [31:0] OST_NON_F32K_WAKEUP_STA_63_32
+** Wakeup source level polarity selection (for wakeup source 63~32)
+** 0: normal polarity
+** 1: inverse polarity
+**=========================================*/
+#define OST_WAKEUP_POLARITY_2 ((volatile kal_uint32*)(OST_BASE + 0xA4))
+/*=========================================
+** OS Timer Debug Wakeup:
+**
+** [31:31] CIRQ_MASK_EN
+** CIRQ_MASK_EN
+** 0: disable cirq mask function
+** 1: enable cirq mask function
+** [1:1] OST_DBG_F32K_WAKEUP
+** Control wakeup status in debug F32K Wakeup Event
+** [0:0] OST_DBG_NON_F32K_WAKEUP
+** Control wakeup status in debug Non-F32K Wakeup Event
+**=========================================*/
+#define OST_DBG_WAKEUP ((volatile kal_uint32*)(OST_BASE + 0xB0))
+/*=========================================
+** OS Timer Debug Wakeup:
+**
+** [0:0] OST_SLEEP_WO_WFI
+** Decide wheather cpu_sleep is refernced when request for puase.
+** (ONLY FOR DEBUG PURPOSE)
+** 0: cpu_sleep(WFI) signal is needed
+** 1. cpu_sleep(WFI) signal is BYPASSed
+**=========================================*/
+#define OST_SLEEP_WO_WFI ((volatile kal_uint32*)(OST_BASE + 0xB4))
+/*=========================================
+** OST_DBG_SEL:
+**
+** [31:24] dbg_flag_sel3
+** Select OST Debug Flag Bit 31-24
+** [23:16] dbg_flag_sel2
+** Select OST Debug Flag Bit 23-16
+** [15:8] dbg_flag_sel1
+** Select OST Debug Flag Bit15-8
+** [7:0] dbg_flag_sel0
+** Select OST Debug Flag Bit 7-0
+**=========================================*/
+#define OST_DBG_SEL ((volatile kal_uint32*)(OST_BASE + 0xF0))
+/*=========================================
+** DUMMY_REG:
+**
+** [31:0] DUMMY1_REG
+** Dummy register
+**=========================================*/
+#define OST_DUMMY0_REG ((volatile kal_uint32*)(OST_BASE + 0x200))
+/*=========================================
+** DUMMY_REG:
+**
+** [31:0] DUMMY2_REG
+** Dummy register
+**=========================================*/
+#define OST_DUMMY1_REG ((volatile kal_uint32*)(OST_BASE + 0x204))
+/*=========================================
+** DUMMY_REG:
+**
+** [31:0] DUMMY3_REG
+** Mirrored Value of AFN count
+** This is a back up solution of OST_AFN_R if the original one can't be read properly. When using this backup register, MUST READ IT
+** TWICE AND CHECK IF BOTH READBACK VALUE ARE THE SAME.
+**=========================================*/
+#define OST_DUMMY2_REG ((volatile kal_uint32*)(OST_BASE + 0x208))
+
+
+/******************** OSTD ASSERT Macro ********************/
+ #define OSTD_ASSERT_Bypass( st ) (void)0
+ #define OSTD_ASSERT_Bypass_Trace( st ) if(!(st)) EXT_ASSERT( 0, 0, 0, 0 ) // MODEM_WARNING_MESSAGE( 0, "[L1SM]" )
+ #define OSTD_ASSERT_Reboot( st ) if(!(st)) EXT_ASSERT( 0, 0, 0, 0 )
+ #define OSTD_EXT_ASSERT_Bypass( st, d1, d2, d3 ) (void)0
+ #define OSTD_EXT_ASSERT_Reboot( st, d1, d2, d3 ) if(!(st)) EXT_ASSERT( 0, d1, d2, d3 )
+
+#ifdef __MTK_INTERNAL__
+ #undef OSTD_ASSERT_Bypass
+ #undef OSTD_EXT_ASSERT_Bypass
+ #define OSTD_ASSERT_Bypass( st ) if(!(st)) EXT_ASSERT( 0, 0, 0, 0 )
+ #define OSTD_EXT_ASSERT_Bypass( st, d1, d2, d3 ) if(!(st)) EXT_ASSERT( 0, d1, d2, d3 )
+#endif
+
+#ifdef L1_SIM
+ #undef OSTD_ASSERT_Bypass_Trace
+ #define OSTD_ASSERT_Bypass_Trace( st ) if(!(st)) ASSERT( 0 )
+#endif
+
+/******************** ostd.c internal usage ********************/
+
+#define OST_MAX_WAIT_TIME 1000 /* Based on designer's guarantee, the wait time for CMD ACK should be less than 1us. (MIPS clock is 900MHz, but designer suggests 1000) */
+#define OST_MAX_SLEEP_UFN 3460 /* 16 sec => 16/4.615 = 3466.67 (for UDVT not care about WatchDog) */
+
+
+/* 26M debug FRC */
+#define MAX_FRC_VAL 0xFFFFFFFF
+
+
+/*****************************************************************************
+* Pre-defined Structure or Extern Global Variable
+*****************************************************************************/
+
+/*Global OST Test data structure*/
+typedef struct
+{
+ kal_uint32 InPauseCnt; /* To record how many times if OST SW want to go to sleep and OST HW is still in Pause Mode. */
+} OST_Test_Globals;
+
+/*Global OSTD & its SMM data structure*/
+typedef struct
+{
+/* Global Info. */
+ kal_bool sleeped;
+ volatile kal_uint16 ost_isr_sta;
+ kal_bool irq_masked; /* Record if IRQ already masked for wake-up INT scheme. (polling scheme not needed). */
+ CIRQ_MASK_VALUE_T irq_mask_sm;
+ CIRQ_MASK_VALUE_T SleepModeMask;
+
+ kal_bool Enable_3G; /* E-FUSE for 3G feature */
+
+ /* Infinite Sleep related */
+ kal_bool infinite_sleep_ind[OSTD_TIMER_MAX];
+ kal_bool infinite_sleep;
+ kal_uint32 infinite_sleep_Lockhandle;
+
+ /* enter Flight mode (AT+EFUN=0) */
+ volatile kal_bool Radio_On;
+ volatile kal_bool Efun_Assert_Timer_On;
+ volatile kal_bool Efun_Assert_Timer_On_SlpAbrt;
+ volatile kal_bool Efun_Assert_Timer_On_SlpAbrt_Bypass;
+ volatile kal_bool Efun_Assert_Timer_On_EnterCheckSleep[MIPS_CORE_NUMBER];
+ kal_uint32 Preliminary_SleepDisable_Core0[(MAX_SLEEP_HANDLE+31)/32];
+ kal_uint32 Preliminary_SleepDisable_Core1[(MAX_SLEEP_HANDLE+31)/32];
+ kal_uint32 Preliminary_SleepDisable_Core2[(MAX_SLEEP_HANDLE+31)/32];
+ kal_uint32 Preliminary_SleepDisable_Core3[(MAX_SLEEP_HANDLE+31)/32];
+ kal_uint32 Radio_On_time_FMA_64;
+ kal_uint32 Radio_Off_time_FMA_64;
+ kal_uint32 EFUN_Done_time_FMA_64;
+ kal_uint32 EPOF_Done_time_FMA_64;
+ kal_uint32 efun_ok_timeStamp;
+ kal_uint32 epof_ok_timeStamp;
+ kal_timerid efun_timer_id_preliminary;
+ kal_timerid efun_timer_id;
+ kal_timerid epof_timer_id;
+ kal_uint32 Efun_Assert_Slept_Cnt_Old;
+
+ /* Setting of System Settling Time */
+ kal_uint16 curr_Settle; /* Unit: 32K cycles */
+
+ /* Power Modelling */
+ kal_uint32 interrupt_elapsedDuration;
+ kal_uint32 ostd_InterruptFRC;
+ kal_uint32 last_TimeStampPWRM;
+ kal_bool curr_idleCondition [MIPS_CORE_NUMBER * 2];
+ kal_uint32 vpe_idleAccumulate [MIPS_CORE_NUMBER * 2][2];
+ kal_uint32 vpe_idleAccumulate_prev[MIPS_CORE_NUMBER * 2];
+ kal_uint32 start_idleFRC [MIPS_CORE_NUMBER * 2][2];
+ kal_uint32 start_idleFRC_common;
+ kal_uint32 end_idleFRC [MIPS_CORE_NUMBER * 2][2];
+ kal_bool bool_idleFRC [MIPS_CORE_NUMBER * 2][2];
+ kal_uint32 idle_index [MIPS_CORE_NUMBER * 2];
+ kal_uint32 vpe_idleDuration [MIPS_CORE_NUMBER * 2];
+
+ /* Debug pool */
+ kal_uint32 last_TimeStamp;
+ kal_uint32 last_TimeStamp2;
+ kal_uint32 last_TimeStamp_LockMod; // for display lock module
+
+ kal_uint32 Minimum_slp_ufn;
+ kal_uint32 f32k_ratio;
+
+ kal_uint32 slept_cnt;
+ OSTD_FRM_INFO_T Frm_Info_Pre; /* log the AFN/UFN before sleeping */
+ OSTD_FRM_INFO_T Frm_Info_After; /* log the AFN/UFN after wakeup */
+ kal_uint32 FRC_Pre;
+ kal_uint32 FRC_After; /* log the FRC after wakeup */
+ kal_uint32 TimeStamp_FMA_64_Pre;
+ kal_uint32 TimeStamp_FMA_64_Aft;
+ kal_uint32 F32k_Pre;
+ kal_uint32 F32k_Aft;
+
+ kal_uint32 FRC_sleep_dur;
+ kal_uint32 FRC_active_dur;
+
+ kal_uint32 md_sysclk_cnt_total;
+ kal_uint32 dhl_md_sysclk_cnt_total;
+
+ kal_uint32 FrmTimeOut_cnt; /* To record the time-out count of Frame Time Out */
+ kal_uint32 AfnTimeOut_cnt; /* To record the time-out count of AFN Time Out */
+ kal_uint32 UfnTimeOut_cnt; /* To record the time-out count of UFN Time Out */
+ kal_uint32 SleepAbort_cnt[MIPS_CORE_NUMBER]; /* To record the time-out count of Sleep Abort */
+ kal_uint32 SleepInt_cnt[MIPS_CORE_NUMBER]; /* To record the time-out count of Sleep Interrupt */
+
+ kal_uint32 last_FrmTimeOut_frc;
+ kal_uint32 last_AfnTimeOut_frc;
+ kal_uint32 last_UfnTimeOut_frc;
+ kal_uint32 last_SleepAbort_frc[MIPS_CORE_NUMBER];
+ kal_uint32 last_SleepInt_frc[MIPS_CORE_NUMBER];
+
+ kal_bool stress; /* RTOS stress test from inject string/at command */
+
+#if defined( __LTE_RAT__ )
+ kal_bool stress4GWakeup; /* 4G S/W wakeup stress test from inject string/at command */
+#endif
+
+ kal_uint32 Dbg_Pwr_OFF_Recored;
+ kal_uint32 md_sysclk_cnt; //if md_sysclk is in off state (unit : 32k)
+ kal_uint32 all_sysclk_cnt; //if all_sysclk is in off state (unit : 32k)
+ kal_uint32 acc_cnt; //For HTC
+ kal_uint32 acc_time; //For HTC
+ kal_uint32 acc_time_2; //For Android N
+
+ kal_uint32 eint_not_clr_cnt;
+ kal_uint32 ssta_not_idle_cnt;
+
+ //volatile kal_int32 UnmaskIRQ_Counter;
+
+ kal_bool OSTD_ReportMdWorkTime_ELT;
+ kal_bool OSTD_ReportMdWorkTime_RMMI;
+
+
+} OSTD_Globals;
+
+#define OSTD_CHKSLP_DEBUG_HISTORY_MAX 40
+#define OSTD_INTERRUPT_DEBUG_HISTORY_MAX 40
+typedef struct
+{
+ kal_uint32 Timestamp;
+ kal_uint32 Action;
+} OSTD_ChkSlp_Debug;
+
+typedef struct
+{
+ kal_uint32 Timestamp;
+ kal_uint32 Action;
+} OSTD_Interrupt_Debug;
+
+/* From L1D : for customer revise */
+extern const kal_uint16 CLK_SETTLE;
+
+
+/*****************************************************************************
+* Functions provided by OSTD
+*****************************************************************************/
+extern void OSTD_Interrupt(kal_uint32 irq_id);
+extern void OSTD_MaskIRQ( void );
+void OSTD_ChkSlp_StepLogging(kal_uint32, OSTD_ChkSlp_Step_e);
+void ostd_Mask_WkupEvent(sm_event_e wakevnt, kal_bool mask);
+
+/*****************************************************************************
+* Functions provided by Other Module
+*****************************************************************************/
+
+/* From RTOS */
+extern void SleepMode_MaskAll(CIRQ_MASK_VALUE_T *val);
+extern void SleepMode_RestoreAll(CIRQ_MASK_VALUE_T *val);
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void TMC_Timer_Interrupt(void);
+
+#endif /* !OSTD_PRIVATE_H */
diff --git a/mcu/driver/sleep_drv/internal/inc/rf_slpc.h b/mcu/driver/sleep_drv/internal/inc/rf_slpc.h
new file mode 100644
index 0000000..b1bfca1
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/rf_slpc.h
@@ -0,0 +1,153 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * rf_slpc.h
+ *
+ * Project:
+ * --------
+ * Gen97
+ *
+ * Description:
+ * ------------
+ * RF sleep control configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef RF_SLPC_H
+#define RF_SLPC_H
+
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "reg_base.h"
+#include "kal_public_api.h"
+
+/******************** Register Definition ********************/
+#if defined(__MD97__) || defined(__MD97P__)
+#define RF_SLPC_base (BASE_MADDR_MODEML1_AO_RF_SLP_CTRL)
+#else
+#define RF_SLPC_base (0xA82B0000)
+#endif
+
+#define RFSLPC_MIPI_26M_SEL_ON_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0000))
+#define RFSLPC_MIPI_26M_SEL_OFF_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0004))
+#define RFSLPC_RF_TOPSM_ON_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0008))
+#define RFSLPC_RF_CG_OFF_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x000C))
+#define RFSLPC_XO_LDO_OFF_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0010))
+#define RFSLPC_AO_LDO_OFF_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0014))
+#define RFSLPC_AO_LDO_ON_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0018))
+#define RFSLPC_XO_LDO_ON_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x001C))
+#define RFSLPC_RF_CG_ON_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0020))
+#define RFSLPC_RF_TOPSM_OFF_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0024))
+#define RFSLPC_LINK_DISABLE_SETTLE ((volatile kal_uint32*)(RF_SLPC_base+0x0028))
+#define RFSLPC_SW_MODE ((volatile kal_uint32*)(RF_SLPC_base+0x0050))
+#define RFSLPC_AOBUF_LDO_EN_M ((volatile kal_uint32*)(RF_SLPC_base+0x0054))
+#define RFSLPC_XOBUF_LDO_EN_M ((volatile kal_uint32*)(RF_SLPC_base+0x0058))
+#define RFSLPC_XOBUF_CG_EN_M ((volatile kal_uint32*)(RF_SLPC_base+0x005C))
+#define RFSLPC_RF_TOPSM_RES_M ((volatile kal_uint32*)(RF_SLPC_base+0x0060))
+#define RFSLPC_CLIENT_ACT_M ((volatile kal_uint32*)(RF_SLPC_base+0x0064))
+#define RFSLPC_CLIENT_ACT_PRE_M ((volatile kal_uint32*)(RF_SLPC_base+0x0068))
+#define RFSLPC_L1SM_RF_RES_REQ_M ((volatile kal_uint32*)(RF_SLPC_base+0x006C))
+#define RFSLPC_L1SM_RF_RES_RDY_M ((volatile kal_uint32*)(RF_SLPC_base+0x0070))
+#define RFSLPC_DFEPLL_CLK_REQ_M ((volatile kal_uint32*)(RF_SLPC_base+0x0074))
+#define RFSLPC_TXBSRP_CLK_REQ_M ((volatile kal_uint32*)(RF_SLPC_base+0x0078))
+#define RFSLPC_RFSLPC_RES_REQ_M ((volatile kal_uint32*)(RF_SLPC_base+0x007C))
+#define RFSLPC_MIPI_SYSCLK_SEL_M ((volatile kal_uint32*)(RF_SLPC_base+0x0080))
+#define RFSLPC_DFE_SLP_PROT_REQ_M ((volatile kal_uint32*)(RF_SLPC_base+0x0084))
+#define RFSLPC_PWR_REQ_MASK ((volatile kal_uint32*)(RF_SLPC_base+0x0100))
+#define RFSLPC_PWR_CON ((volatile kal_uint32*)(RF_SLPC_base+0x0104))
+#define RFSLPC_RFSLPC_PWR_PER_0 ((volatile kal_uint32*)(RF_SLPC_base+0x0108))
+#define RFSLPC_PWR_PER_1 ((volatile kal_uint32*)(RF_SLPC_base+0x010C))
+#define RFSLPC_TOPSM_MCF_CNT_BASE ((volatile kal_uint32*)(RF_SLPC_base+0x0110))
+#define RFSLPC_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(RF_SLPC_base+0x0114))
+#define RFSLPC_PWR_RDY_SEL ((volatile kal_uint32*)(RF_SLPC_base+0x0118))
+#define RFSLPC_PWR_RDY_REG ((volatile kal_uint32*)(RF_SLPC_base+0x011C))
+#define RFSLPC_PWR_RDY ((volatile kal_uint32*)(RF_SLPC_base+0x0120))
+#define RFSLPC_PROT_RDY ((volatile kal_uint32*)(RF_SLPC_base+0x0124))
+#define RFSLPC_MCF_STA ((volatile kal_uint32*)(RF_SLPC_base+0x0128))
+#define RFSLPC_STA ((volatile kal_uint32*)(RF_SLPC_base+0x0150))
+#define RFSLPC_RDY_STA ((volatile kal_uint32*)(RF_SLPC_base+0x0154))
+#define RFSLPC_ERROR_FLAG ((volatile kal_uint32*)(RF_SLPC_base+0x0158))
+#define RFSLPC_MIPI_RDY_BYP ((volatile kal_uint32*)(RF_SLPC_base+0x015C))
+#define RFSLPC_DVFS_IDLE_STA ((volatile kal_uint32*)(RF_SLPC_base+0x0160))
+#define RFSLPC_DVFS_IDLE_BYP ((volatile kal_uint32*)(RF_SLPC_base+0x0164))
+#define RFSLPC_PROT_RDY_BYP ((volatile kal_uint32*)(RF_SLPC_base+0x0168))
+#define RFSLPC_SERDES_TRIG_SW_MODE ((volatile kal_uint32*)(RF_SLPC_base+0x0180))
+#define RFSLPC_SERDES_SW_TRIGGER ((volatile kal_uint32*)(RF_SLPC_base+0x0184))
+
+
+/******************** RFSLPC ASSERT Macro ********************/
+#ifdef __MTK_INTERNAL__
+ #define RFSLPC_ASSERT_Bypass( st ) ASSERT( st )
+ #define RFSLPC_ASSERT_Reboot( st ) ASSERT( st )
+ #define RFSLPC_EXT_ASSERT_Bypass( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+ #define RFSLPC_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#else
+ #define RFSLPC_ASSERT_Bypass( st ) (void)0
+ #define RFSLPC_ASSERT_Reboot( st ) ASSERT( st )
+ #define RFSLPC_EXT_ASSERT_Bypass( st, d1, d2, d3 ) (void)0
+ #define RFSLPC_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#endif
+
+#endif
diff --git a/mcu/driver/sleep_drv/internal/inc/rf_topsm.h b/mcu/driver/sleep_drv/internal/inc/rf_topsm.h
new file mode 100644
index 0000000..4d53ada
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/rf_topsm.h
@@ -0,0 +1,284 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * rf_topsm.h
+ *
+ * Project:
+ * --------
+ * Gen97
+ *
+ * Description:
+ * ------------
+ * RF Resource Management (RF TOPSM) configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef RF_TOPSM_H
+#define RF_TOPSM_H
+
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "reg_base.h"
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define RF_TOPSM_base (0xAF310000)
+#define RF_TOPSM_BACKDOOR_base (0xAF398000)
+#else
+#define RF_TOPSM_base (0xAF310000)
+#define RF_TOPSM_BACKDOOR_base (0xAF398000)
+#endif
+
+/************************* Registers for RF TOPSM begin *********************************/
+#define RF_TOPSM_SM_PWR_CON0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0000))
+#define RF_TOPSM_SM_PWR_CON1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0004))
+#define RF_TOPSM_SM_PWR_CON2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0008))
+#define RF_TOPSM_SM_PWR_CON3 ((volatile kal_uint32*)(RF_TOPSM_base+0x000C))
+#define RF_TOPSM_SM_PWR_CON4 ((volatile kal_uint32*)(RF_TOPSM_base+0x0010))
+#define RF_TOPSM_SM_PWR_CON5 ((volatile kal_uint32*)(RF_TOPSM_base+0x0014))
+#define RF_TOPSM_SM_PWR_CON6 ((volatile kal_uint32*)(RF_TOPSM_base+0x0018))
+#define RF_TOPSM_SM_PWR_CON7 ((volatile kal_uint32*)(RF_TOPSM_base+0x001C))
+#define RF_TOPSM_SM_PWR_CON8 ((volatile kal_uint32*)(RF_TOPSM_base+0x0020))
+#define RF_TOPSM_SM_PWR_CON9 ((volatile kal_uint32*)(RF_TOPSM_base+0x0024))
+#define RF_TOPSM_SM_PWR_CON10 ((volatile kal_uint32*)(RF_TOPSM_base+0x0028))
+#define RF_TOPSM_SM_PWR_CON11 ((volatile kal_uint32*)(RF_TOPSM_base+0x002C))
+#define RF_TOPSM_SM_PWR_ON_SW_CTRL0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0080))
+#define RF_TOPSM_SM_PWR_ON_SW_CTRL1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0084))
+#define RF_TOPSM_SM_PWR_ON_SW_CTRL2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0088))
+#define RF_TOPSM_SM_PWR_ON_SW_CTRL3 ((volatile kal_uint32*)(RF_TOPSM_base+0x008C))
+#define RF_TOPSM_SM_PWR_OFF_SW_CTRL0 ((volatile kal_uint32*)(RF_TOPSM_base+0x00A0))
+#define RF_TOPSM_SM_PWR_OFF_SW_CTRL1 ((volatile kal_uint32*)(RF_TOPSM_base+0x00A4))
+#define RF_TOPSM_SM_PWR_OFF_SW_CTRL2 ((volatile kal_uint32*)(RF_TOPSM_base+0x00A8))
+#define RF_TOPSM_SM_PWR_OFF_SW_CTRL3 ((volatile kal_uint32*)(RF_TOPSM_base+0x00AC))
+#define RF_TOPSM_SM_PWR_PER0 ((volatile kal_uint32*)(RF_TOPSM_base+0x00C0))
+#define RF_TOPSM_SM_PWR_PER1 ((volatile kal_uint32*)(RF_TOPSM_base+0x00C4))
+#define RF_TOPSM_SM_PWR_BYPASS_PROTECT_RDY ((volatile kal_uint32*)(RF_TOPSM_base+0x00C8))
+#define RF_TOPSM_SM_PWR_RDY_REG ((volatile kal_uint32*)(RF_TOPSM_base+0x00D0))
+#define RF_TOPSM_SM_PWR_RDY ((volatile kal_uint32*)(RF_TOPSM_base+0x00D4))
+#define RF_TOPSM_SW_PWR_MTCMOS_SW_CTRL ((volatile kal_uint32*)(RF_TOPSM_base+0x00E0))
+#define RF_TOPSM_SM_TMR_REQ_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0100))
+#define RF_TOPSM_SM_TMR_SYSCLK_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0108))
+#define RF_TOPSM_SM_TMR_PLL_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0120))
+#define RF_TOPSM_SM_TMR_PLL_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0124))
+#define RF_TOPSM_SM_TMR_PLL_MASK2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0128))
+#define RF_TOPSM_SM_TMR_PLL_MASK3 ((volatile kal_uint32*)(RF_TOPSM_base+0x012C))
+#define RF_TOPSM_SM_TMR_PWR_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0140))
+#define RF_TOPSM_SM_TMR_PWR_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0144))
+#define RF_TOPSM_SM_TMR_PWR_MASK2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0148))
+#define RF_TOPSM_SM_TMR_PWR_MASK3 ((volatile kal_uint32*)(RF_TOPSM_base+0x014C))
+#define RF_TOPSM_SM_TMR_PWR_MASK4 ((volatile kal_uint32*)(RF_TOPSM_base+0x0150))
+#define RF_TOPSM_SM_TMR_PWR_MASK5 ((volatile kal_uint32*)(RF_TOPSM_base+0x0154))
+#define RF_TOPSM_SM_TMR_MAS_TRIG_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0160))
+#define RF_TOPSM_SM_TMR_MAS_TRIG_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0164))
+#define RF_TOPSM_SM_TMR_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0170))
+#define RF_TOPSM_SM_TMR_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0174))
+#define RF_TOPSM_SM_TMR_CLIENT_ACT_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0180))
+#define RF_TOPSM_SM_TMR_PRE_TRIG_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0190))
+#define RF_TOPSM_SM_TMR_SSTA0 ((volatile kal_uint32*)(RF_TOPSM_base+0x01A0))
+#define RF_TOPSM_SM_TMR_SSTA1 ((volatile kal_uint32*)(RF_TOPSM_base+0x01A4))
+#define RF_TOPSM_SM_SLV_REQ_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0200))
+#define RF_TOPSM_SM_SLV_SYSCLK_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0208))
+#define RF_TOPSM_SM_SLV_PLL_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0220))
+#define RF_TOPSM_SM_SLV_PLL_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0224))
+#define RF_TOPSM_SM_SLV_PLL_MASK2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0228))
+#define RF_TOPSM_SM_SLV_PLL_MASK3 ((volatile kal_uint32*)(RF_TOPSM_base+0x022C))
+#define RF_TOPSM_SM_SLV_PWR_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0240))
+#define RF_TOPSM_SM_SLV_PWR_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0244))
+#define RF_TOPSM_SM_SLV_PWR_MASK2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0248))
+#define RF_TOPSM_SM_SLV_PWR_MASK3 ((volatile kal_uint32*)(RF_TOPSM_base+0x024C))
+#define RF_TOPSM_SM_SLV_PWR_MASK4 ((volatile kal_uint32*)(RF_TOPSM_base+0x0250))
+#define RF_TOPSM_SM_SLV_PWR_MASK5 ((volatile kal_uint32*)(RF_TOPSM_base+0x0254))
+#define RF_TOPSM_SM_SLV_MAS_TRIG_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0260))
+#define RF_TOPSM_SM_SLV_MAS_TRIG_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0264))
+#define RF_TOPSM_SM_SLV_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0270))
+#define RF_TOPSM_SM_SLV_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0274))
+#define RF_TOPSM_SM_SLV_CLIENT_ACT_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0280))
+#define RF_TOPSM_SM_SLV_PRE_TRIG_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0290))
+#define RF_TOPSM_SM_SLV_SSTA0 ((volatile kal_uint32*)(RF_TOPSM_base+0x02A0))
+#define RF_TOPSM_SM_SLV_SSTA1 ((volatile kal_uint32*)(RF_TOPSM_base+0x02A4))
+#define RF_TOPSM_SM_DBG_REQ_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0300))
+#define RF_TOPSM_SM_DBG_SYSCLK_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0308))
+#define RF_TOPSM_SM_DBG_PLL_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0320))
+#define RF_TOPSM_SM_DBG_PLL_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0324))
+#define RF_TOPSM_SM_DBG_PLL_MASK2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0328))
+#define RF_TOPSM_SM_DBG_PLL_MASK3 ((volatile kal_uint32*)(RF_TOPSM_base+0x032C))
+#define RF_TOPSM_SM_DBG_PWR_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0340))
+#define RF_TOPSM_SM_DBG_PWR_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0344))
+#define RF_TOPSM_SM_DBG_PWR_MASK2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0348))
+#define RF_TOPSM_SM_DBG_PWR_MASK3 ((volatile kal_uint32*)(RF_TOPSM_base+0x034C))
+#define RF_TOPSM_SM_DBG_PWR_MASK4 ((volatile kal_uint32*)(RF_TOPSM_base+0x0350))
+#define RF_TOPSM_SM_DBG_PWR_MASK5 ((volatile kal_uint32*)(RF_TOPSM_base+0x0354))
+#define RF_TOPSM_SM_DBG_MAS_TRIG_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0360))
+#define RF_TOPSM_SM_DBG_MAS_TRIG_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0364))
+#define RF_TOPSM_SM_DBG_TIMER_TRIG_MASK0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0370))
+#define RF_TOPSM_SM_DBG_TIMER_TRIG_MASK1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0374))
+#define RF_TOPSM_SM_DBG_CLIENT_ACT_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0380))
+#define RF_TOPSM_SM_DBG_PRE_TRIG_MASK ((volatile kal_uint32*)(RF_TOPSM_base+0x0390))
+#define RF_TOPSM_SM_DBG_SSTA0 ((volatile kal_uint32*)(RF_TOPSM_base+0x03A0))
+#define RF_TOPSM_SM_DBG_SSTA1 ((volatile kal_uint32*)(RF_TOPSM_base+0x03A4))
+#define RF_TOPSM_SM_CLK_SETTLE ((volatile kal_uint32*)(RF_TOPSM_base+0x0400))
+#define RF_TOPSM_SM_PRE_TRIG_SETTLE ((volatile kal_uint32*)(RF_TOPSM_base+0x0408))
+#define RF_TOPSM_SM_TIMER_TRIG_SETTLE ((volatile kal_uint32*)(RF_TOPSM_base+0x0410))
+#define RF_TOPSM_SM_MAS_TRIG_MAX_SETTLE ((volatile kal_uint32*)(RF_TOPSM_base+0x0418))
+#define RF_TOPSM_SM_MAS_TRIG_GRP_SETTLE0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0420))
+#define RF_TOPSM_SM_MAS_TRIG_GRP_SETTLE1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0424))
+#define RF_TOPSM_SM_MAS_TRIG_GRP_SAL0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0430))
+#define RF_TOPSM_SM_MAS_TRIG_GRP_SAL1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0434))
+#define RF_TOPSM_SM_MAS_TRIG_SEL ((volatile kal_uint32*)(RF_TOPSM_base+0x0440))
+#define RF_TOPSM_SM_TMR_SW_TRIG ((volatile kal_uint32*)(RF_TOPSM_base+0x0450))
+#define RF_TOPSM_SM_SLV_SW_TRIG ((volatile kal_uint32*)(RF_TOPSM_base+0x0454))
+#define RF_TOPSM_SM_DBG_SW_TRIG ((volatile kal_uint32*)(RF_TOPSM_base+0x0458))
+#define RF_TOPSM_SM_MAS_SW_TRIG ((volatile kal_uint32*)(RF_TOPSM_base+0x045C))
+#define RF_TOPSM_SM_TMR_BYPASS_SYSCLK ((volatile kal_uint32*)(RF_TOPSM_base+0x0468))
+#define RF_TOPSM_SM_SLV_REQ_IRQ ((volatile kal_uint32*)(RF_TOPSM_base+0x0470))
+#define RF_TOPSM_SM_DBG_REQ_IRQ ((volatile kal_uint32*)(RF_TOPSM_base+0x0478))
+#define RF_TOPSM_SM_MAS_REQ_IRQ ((volatile kal_uint32*)(RF_TOPSM_base+0x0480))
+#define RF_TOPSM_SW_SYSCLK_FORCE_ON ((volatile kal_uint32*)(RF_TOPSM_base+0x04A0))
+#define RF_TOPSM_SW_PLL_FORCE_ON ((volatile kal_uint32*)(RF_TOPSM_base+0x04B0))
+#define RF_TOPSM_SW_TIMER_TRIG_FORCE_ON ((volatile kal_uint32*)(RF_TOPSM_base+0x04D0))
+#define RF_TOPSM_SW_CLIENT_ACT_FORCE_ON ((volatile kal_uint32*)(RF_TOPSM_base+0x04E0))
+#define RF_TOPSM_SM_PWR_STATUS0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0500))
+#define RF_TOPSM_SM_PWR_STATUS1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0504))
+#define RF_TOPSM_SM_PWR_STATUS2 ((volatile kal_uint32*)(RF_TOPSM_base+0x0508))
+#define RF_TOPSM_SM_PWR_STATUS3 ((volatile kal_uint32*)(RF_TOPSM_base+0x050C))
+#define RF_TOPSM_SM_PWR_STATUS4 ((volatile kal_uint32*)(RF_TOPSM_base+0x0510))
+#define RF_TOPSM_SM_PWR_STATUS5 ((volatile kal_uint32*)(RF_TOPSM_base+0x0514))
+#define RF_TOPSM_SM_PWR_STATUS6 ((volatile kal_uint32*)(RF_TOPSM_base+0x0518))
+#define RF_TOPSM_SM_PWR_STATUS7 ((volatile kal_uint32*)(RF_TOPSM_base+0x051C))
+#define RF_TOPSM_SM_PWR_STATUS8 ((volatile kal_uint32*)(RF_TOPSM_base+0x0520))
+#define RF_TOPSM_SM_PWR_STATUS9 ((volatile kal_uint32*)(RF_TOPSM_base+0x0524))
+#define RF_TOPSM_SM_PWR_STATUS10 ((volatile kal_uint32*)(RF_TOPSM_base+0x0528))
+#define RF_TOPSM_SM_PWR_STATUS11 ((volatile kal_uint32*)(RF_TOPSM_base+0x052C))
+#define RF_TOPSM_SM_PWR_STATUS12 ((volatile kal_uint32*)(RF_TOPSM_base+0x0530))
+#define RF_TOPSM_SM_PWR_STATUS13 ((volatile kal_uint32*)(RF_TOPSM_base+0x0534))
+#define RF_TOPSM_SM_PWR_STATUS14 ((volatile kal_uint32*)(RF_TOPSM_base+0x0538))
+#define RF_TOPSM_SM_PWR_STATUS15 ((volatile kal_uint32*)(RF_TOPSM_base+0x053C))
+#define RF_TOPSM_SM_PWR_STATUS16 ((volatile kal_uint32*)(RF_TOPSM_base+0x0540))
+#define RF_TOPSM_SM_PWR_STATUS17 ((volatile kal_uint32*)(RF_TOPSM_base+0x0544))
+#define RF_TOPSM_SM_PWR_STATUS18 ((volatile kal_uint32*)(RF_TOPSM_base+0x0548))
+#define RF_TOPSM_SM_PWR_STATUS19 ((volatile kal_uint32*)(RF_TOPSM_base+0x054C))
+#define RF_TOPSM_SM_PWR_STATUS20 ((volatile kal_uint32*)(RF_TOPSM_base+0x0550))
+#define RF_TOPSM_SM_PWR_STATUS21 ((volatile kal_uint32*)(RF_TOPSM_base+0x0554))
+#define RF_TOPSM_SM_PWR_STATUS22 ((volatile kal_uint32*)(RF_TOPSM_base+0x0558))
+#define RF_TOPSM_SM_PWR_STATUS23 ((volatile kal_uint32*)(RF_TOPSM_base+0x055C))
+#define RF_TOPSM_SW_PRE_TRIG_FORCE_ON ((volatile kal_uint32*)(RF_TOPSM_base+0x04F0))
+#define RF_TOPSM_SM_SYSCLK_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x0580))
+#define RF_TOPSM_SM_PLL_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x0590))
+#define RF_TOPSM_SM_PWR_REQ_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05A0))
+#define RF_TOPSM_SM_PWR_ACK_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05A4))
+#define RF_TOPSM_SM_SLV_REQ_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05B0))
+#define RF_TOPSM_SM_DBG_REQ_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05C0))
+#define RF_TOPSM_SM_MAS_REQ_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05D0))
+#define RF_TOPSM_SW_CLIENT_ACT_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05E0))
+#define RF_TOPSM_SW_PRE_TRIG_STA ((volatile kal_uint32*)(RF_TOPSM_base+0x05F0))
+#define RF_TOPSM_SM_TOPSM_CONFG ((volatile kal_uint32*)(RF_TOPSM_base+0x0600))
+#define RF_TOPSM_SM_TOPSM_SPARE ((volatile kal_uint32*)(RF_TOPSM_base+0x0608))
+#define RF_TOPSM_SM_TOPSM_MCF_CNT_BASE ((volatile kal_uint32*)(RF_TOPSM_base+0x060C))
+#define RF_TOPSM_SM_DBGMON_SYSCLK_FM ((volatile kal_uint32*)(RF_TOPSM_base+0x0610))
+#define RF_TOPSM_SM_DBGMON_SYSCLK_FM_CTRL ((volatile kal_uint32*)(RF_TOPSM_base+0x0614))
+#define RF_TOPSM_SM_DBGMON_SYSCLK_FM_FLAG ((volatile kal_uint32*)(RF_TOPSM_base+0x0618))
+#define RF_TOPSM_SM_TOPSM_APP_OUTCR_SET ((volatile kal_uint32*)(RF_TOPSM_base+0x0640))
+#define RF_TOPSM_SM_TOPSM_APP_OUTCR_CLR ((volatile kal_uint32*)(RF_TOPSM_base+0x0644))
+#define RF_TOPSM_SM_TOPSM_APP_INCR ((volatile kal_uint32*)(RF_TOPSM_base+0x0670))
+#define RF_TOPSM_SM_PWR_PROTECT_ERR ((volatile kal_uint32*)(RF_TOPSM_base+0x0680))
+#define RF_TOPSM_SM_TMR_FSM_ERR0 ((volatile kal_uint32*)(RF_TOPSM_base+0x0690))
+#define RF_TOPSM_SM_TMR_FSM_ERR1 ((volatile kal_uint32*)(RF_TOPSM_base+0x0694))
+#define RF_TOPSM_SM_TMR_PROT_ERR ((volatile kal_uint32*)(RF_TOPSM_base+0x0698))
+#define RF_TOPSM_SM_SLV_FSM_ERR0 ((volatile kal_uint32*)(RF_TOPSM_base+0x06a0))
+#define RF_TOPSM_SM_SLV_FSM_ERR1 ((volatile kal_uint32*)(RF_TOPSM_base+0x06a4))
+#define RF_TOPSM_SM_SLV_PROT_ERR ((volatile kal_uint32*)(RF_TOPSM_base+0x06a8))
+#define RF_TOPSM_SM_DBG_FSM_ERR0 ((volatile kal_uint32*)(RF_TOPSM_base+0x06b0))
+#define RF_TOPSM_SM_DBG_FSM_ERR1 ((volatile kal_uint32*)(RF_TOPSM_base+0x06b4))
+#define RF_TOPSM_SM_DBG_PROT_ERR ((volatile kal_uint32*)(RF_TOPSM_base+0x06b8))
+#define RF_TOPSM_FRC_CON ((volatile kal_uint32*)(RF_TOPSM_base+0x0800))
+#define RF_TOPSM_FRC_F32K_FM ((volatile kal_uint32*)(RF_TOPSM_base+0x0810))
+#define RF_TOPSM_FRC_FRAME_LEN ((volatile kal_uint32*)(RF_TOPSM_base+0x0820))
+#define RF_TOPSM_FRC_VAL_R ((volatile kal_uint32*)(RF_TOPSM_base+0x0830))
+#define RF_TOPSM_FRC_VAL_R_H ((volatile kal_uint32*)(RF_TOPSM_base+0x0834))
+#define RF_TOPSM_FRC_TIMESTAMP ((volatile kal_uint32*)(RF_TOPSM_base+0x0840))
+#define RF_TOPSM_F32K_CNT ((volatile kal_uint32*)(RF_TOPSM_base+0x0850))
+#define RF_TOPSM_TIMER_SYNC_STATUS ((volatile kal_uint32*)(RF_TOPSM_base+0x0860))
+#define RF_TOPSM_TIMER_SYNC0_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x0880))
+#define RF_TOPSM_TIMER_SYNC0_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x0884))
+#define RF_TOPSM_TIMER_SYNC1_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x0888))
+#define RF_TOPSM_TIMER_SYNC1_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x088C))
+#define RF_TOPSM_TIMER_SYNC2_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x0890))
+#define RF_TOPSM_TIMER_SYNC2_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x0894))
+#define RF_TOPSM_TIMER_SYNC3_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x0898))
+#define RF_TOPSM_TIMER_SYNC3_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x089C))
+#define RF_TOPSM_TIMER_SYNC4_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x08A0))
+#define RF_TOPSM_TIMER_SYNC4_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x08A4))
+#define RF_TOPSM_TIMER_SYNC5_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x08A8))
+#define RF_TOPSM_TIMER_SYNC5_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x08AC))
+#define RF_TOPSM_TIMER_SYNC6_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x08B0))
+#define RF_TOPSM_TIMER_SYNC6_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x08B4))
+#define RF_TOPSM_TIMER_SYNC7_VAL_L ((volatile kal_uint32*)(RF_TOPSM_base+0x08B8))
+#define RF_TOPSM_TIMER_SYNC7_VAL_H ((volatile kal_uint32*)(RF_TOPSM_base+0x08BC))
+#define RF_TOPSM_GPS_SYNC_CON0 ((volatile kal_uint32*)(RF_TOPSM_base+0x08E0))
+#define RF_TOPSM_GPS_SYNC_CON1 ((volatile kal_uint32*)(RF_TOPSM_base+0x08E4))
+/************************* Registers for RF TOPSM end *********************************/
+
+#endif
diff --git a/mcu/driver/sleep_drv/internal/inc/sleep_drv_internal.h b/mcu/driver/sleep_drv/internal/inc/sleep_drv_internal.h
new file mode 100644
index 0000000..6620a9f
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/sleep_drv_internal.h
@@ -0,0 +1,561 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sleep_drv_internal.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Sleep mode driver setting.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef SLEEP_DRV_INTERNAL_H
+#define SLEEP_DRV_INTERNAL_H
+
+#include "kal_general_types.h" // for kal type define
+#include "kal_public_api.h" // for kal assert define
+//#include "sleep_drv_public.h"
+#include "sleepdrv_interface.h"
+
+#ifdef __MTK_TARGET__
+#include "dhl_ebs_logging.h"
+#endif /* __MTK_TARGET__ */
+
+#if defined(__HIF_CCCI_SUPPORT__) && defined(__MTK_TARGET__)
+#include "ccci_if.h"
+#endif
+
+/******************** Sleep Driver ASSERT Macro ********************/
+#ifdef __MTK_INTERNAL__
+ #define SleepDrv_ASSERT_Bypass( st ) ASSERT( st )
+ #define SleepDrv_ASSERT_Reboot( st ) ASSERT( st )
+ #define SleepDrv_EXT_ASSERT_Bypass( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+ #define SleepDrv_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#else
+ #define SleepDrv_ASSERT_Bypass( st ) (void)0
+ #define SleepDrv_ASSERT_Reboot( st ) ASSERT( st )
+ #define SleepDrv_EXT_ASSERT_Bypass( st, d1, d2, d3 ) (void)0
+ #define SleepDrv_EXT_ASSERT_Reboot( st, d1, d2, d3 ) EXT_ASSERT( st, d1, d2, d3 )
+#endif
+
+#if defined(__MD93__)
+#define MIPS_CORE_NUMBER 2
+#elif defined(__MD95__)
+#define MIPS_CORE_NUMBER 3
+#elif defined(__MD97__) || defined(__MD97P__)
+#define MIPS_CORE_NUMBER 4
+#else
+ #error "no chip match"
+#endif
+
+/*Global SleepDrv data structure*/
+typedef struct
+{
+ kal_uint32 sleepDisable[MIPS_CORE_NUMBER][(MAX_SLEEP_HANDLE+31)/32];
+ kal_uint32 DBG_PreSleepDisable[MIPS_CORE_NUMBER][(MAX_SLEEP_HANDLE+31)/32];
+
+ volatile kal_uint32 * shm;
+ kal_uint32 shmSize;
+ #if defined(__HIF_CCCI_SUPPORT__) && defined(__MTK_TARGET__)
+ CCCI_EXCEP_MEMORY_TYPE shmMemType;
+ #endif
+ kal_bool shmIsSupported;
+ volatile kal_uint32 fix_pat_buf_sel_l1;
+
+ struct shm_sleep_info {
+ volatile kal_uint64 record_ttl_time;
+ volatile kal_uint32 record_cnt;
+ volatile kal_uint64 utc;
+ volatile kal_uint64 wall_clk;
+ volatile kal_uint64 sleep_cnt;
+ volatile kal_uint64 sleep_time;
+ // unit is us
+ volatile kal_uint64 md_sleep_time;
+ volatile kal_uint64 gsm_sleep_time;
+ volatile kal_uint64 wcdma_sleep_time;
+ volatile kal_uint64 lte_sleep_time;
+ volatile kal_uint64 nr_sleep_time;
+ volatile kal_uint64 gsm_connect_time;
+ volatile kal_uint64 wcdma_connect_time;
+ volatile kal_uint64 lte_connect_time;
+ volatile kal_uint64 nr_connect_time;
+ volatile kal_uint64 gsm_rx_time;
+ volatile kal_uint64 wcdma_rx_time;
+ volatile kal_uint64 lte_rx_time;
+ volatile kal_uint64 nr_rx_time;
+ volatile kal_uint64 gsm_tx_time;
+ volatile kal_uint64 wcdma_tx_time;
+ volatile kal_uint64 lte_tx_time;
+ volatile kal_uint64 lte_tx_time_prev;
+ volatile kal_uint64 nr_tx_time;
+ volatile kal_uint64 nr_tx_time_prev;
+ volatile kal_uint64 gsm_tx_pwr_time[8];
+ volatile kal_uint64 wcdma_tx_pwr_time[8];
+ volatile kal_uint64 lte_tx_pwr_time[8];
+ volatile kal_uint64 nr_tx_pwr_time[8];
+ volatile kal_uint64 md_total_time;
+ } shm_slp_info;
+} SLEEPDRV_Globals;
+
+typedef struct
+{
+ /*** 32KB low power monitor ***/
+ kal_uint32 address;
+ kal_uint32 size;
+ #if defined(__HIF_CCCI_SUPPORT__) && defined(__MTK_TARGET__)
+ CCCI_EXCEP_MEMORY_TYPE memoryType;
+ #endif
+ kal_bool isSupported;
+ kal_bool isBufferFull;
+
+ kal_uint32 curIndex;
+ kal_uint32 * pCur;
+
+ kal_uint32 TotalRecord;
+
+} SleepDrv_LowPowerMonitorShm;
+
+
+// in SleepDrv_LowPowerMonitor
+typedef struct
+{
+ volatile kal_uint32 * data[MDLPM_MAX_ITEMS]; // this is for address mapping
+ volatile kal_uint32 prev_data[MDLPM_MAX_ITEMS];
+ kal_uint32 version;
+ kal_uint32 timestamp;
+ kal_uint32 wall_clk_low;
+ kal_uint32 wall_clk_high;
+ kal_uint32 utc_us;
+ kal_uint32 utc_s;
+ kal_uint32 sw_lock[(MAX_SLEEP_HANDLE+31)/32];
+ kal_uint32 vmodem_dvfs_gear[8];
+} SleepDrv_LowPowerRecord;
+
+typedef struct
+{
+ /* 512KB/1MB Low Power Monitor ***/
+ kal_uint32 address;
+ kal_uint32 size;
+ #if defined(__HIF_CCCI_SUPPORT__) && defined(__MTK_TARGET__)
+ DHL_EBS_ERROR_CODE init_ret;
+ #endif
+ kal_uint32 last_frc;
+
+ kal_uint32 sampleRate;
+
+ kal_uint32 frame_limit;
+ kal_uint32 single_frame_record_num;
+ kal_uint32 single_record_size;
+
+ kal_uint32 cur_frame;
+ kal_uint32 cur_record;
+ kal_uint32 total_record;
+ kal_uint32 cur_ptr;
+
+ kal_uint32 flush;
+ kal_uint32 end_addr;
+ kal_uint32 tx_call_num;
+ kal_uint32 tx_pre_num;
+ #if defined(__HIF_CCCI_SUPPORT__) && defined(__MTK_TARGET__)
+ dhl_EBS_send_result tx_send_result;
+ #endif /* MTK_TARGET && HIF_CCCI_SUPPORT */
+ kal_bool is_full;
+
+ SleepDrv_LowPowerRecord rec;
+
+} SleepDrv_LowPowerMonitorDHL;
+
+#define SLEEPDRV_LOCKSTATE_DEBUG_HISTORY_MAX 40
+typedef struct
+{
+ kal_uint32 Timestamp;
+ kal_uint32 CallerAddress;
+ kal_uint16 Action;
+ SLEEP_CTL_USER User;
+} SleepDrv_LockState_Debug;
+
+/******************************************************************************
+* Temporal Solution for TK6291 FPGA build pass
+* ./m "TK6291_V7FPGA(BASIC).mak" new
+* CENTRALIZED_SLEEP_MANAGER = FALSE
+******************************************************************************/
+
+
+void SleepDrv_Init( void );
+void SleepDrv_LockState_Logging(SLEEP_CTL_USER, kal_uint8, kal_bool, kal_uint32);
+void SleepDrv_LockSleep( SLEEP_CTL_USER user, kal_uint8 target_core);
+void SleepDrv_UnlockSleep( SLEEP_CTL_USER user, kal_uint8 target_core);
+
+//MD Low Power Monitor API
+void SleepDrv_LowPowerMonitorSet(kal_uint32 index, kal_uint32 element, kal_uint32 address);
+#if defined(__MTK_TARGET__)
+kal_bool SleepDrv_LowPowerMonitorRecord( void );
+#endif
+void SleepDrv_LowPowerMonitorFlushCheck( void );
+
+void SleepDrv_LowPowerMonitorStart(void);
+void SleepDrv_LowPowerMonitorStop(void);
+void SleepDrv_LowPowerMonitorDelete(void);
+void SleepDrv_LowPowerMonitorCreate(void);
+void SleepDrv_LowPowerMonitorFlush(void);
+kal_bool SleepDrv_LowPowerMonitorSetParameter(kal_uint32 data_len, kal_uint8 *data_str);
+void SleepDrv_LowPowerMonitorSetKeyValue(MDLPM_INDEX key, volatile kal_uint32 * value);
+//End of MD Low Power Monitor API
+
+extern void SleepDrv_SyncMDTOPSM32kCalibration(kal_uint32);
+
+#endif /* SLEEP_DRV_INTERNAL_H */
diff --git a/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc.h b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc.h
new file mode 100644
index 0000000..78e7e55
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc.h
@@ -0,0 +1,20 @@
+#ifndef __SLEEP_DRV_TRACE_H__
+#define __SLEEP_DRV_TRACE_H__
+#ifndef GEN_FOR_PC
+#include "stack_config.h"
+#endif
+#include "dhl_trace.h"
+#if !defined(L1_SIM) || defined(__DUMMY_L1_ON_TARGET_4G5G__)
+#if !defined(GEN_FOR_PC)
+#endif
+#if !defined(GEN_FOR_PC) && !defined(__MAUI_BASIC__)
+#include"sleep_drv_trc_mod_ostd_utmd.h"
+#endif
+#if !defined(GEN_FOR_PC) && !defined(__MAUI_BASIC__)
+#include"sleep_drv_trc_mod_mdtopsm_utmd.h"
+#endif
+#if !defined(GEN_FOR_PC) && !defined(__MAUI_BASIC__)
+#include"sleep_drv_trc_mod_sleepdrv_utmd.h"
+#endif
+#endif
+#endif
diff --git a/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_mdtopsm_utmd.json b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_mdtopsm_utmd.json
new file mode 100644
index 0000000..8c9a8ad
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_mdtopsm_utmd.json
@@ -0,0 +1,213 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_MDTOPSM",
+ "startGen": "Legacy",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Medium",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "DesignInfo"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "DesignInfo"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "InternalDesign"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "CoreDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "MDTOPSM_POL_TRC": {
+ "format": "Tar.Addr = 0x%x, HW_READ(Tar.Addr) = 0x%x, Tar.Mask = 0x%x, Tar.value = 0x%x, USC_Elapsed = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDTOPSM_SRCLK_FORCE_OP": {
+ "apiType": "index",
+ "format": "SRCLK_ForceOn_List = 0x%x, Force_Operation = 0x%x, Handle_Count = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDTOPSM_PLL_FORCE_OP": {
+ "apiType": "index",
+ "format": "USER = 0x%x, PLL_ForceOn_Enable = 0x%x, PLL_ForceOn_Count = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "MDTOPSM_CALIBRATION": {
+ "format": "TRC_ID[%d], Value1 = 0x%x, Value2 = 0x%x",
+ "traceClass": "TRACE_WARNING"
+ }
+ },
+ {
+ "MDTOPSM_STATUS1": {
+ "apiType": "index",
+ "format": "[%d] 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MDTOPSM_STATUS2": {
+ "apiType": "index",
+ "format": "[%d] 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MDTOPSM_STATUS3": {
+ "apiType": "index",
+ "format": "[%d] 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MDTOPSM_STATUS4": {
+ "apiType": "index",
+ "format": "[%d] 0x%x 0x%x 0x%x 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "MDTOPSM_LPM_STATUS": {
+ "apiType": "index",
+ "format": "[LPM] Total time = 0x%x, Total high duration time = 0x%x, L1DCM_LPM_CTL = 0x%x, DDR_ON_LPM_DBG_SEL = 0x%x",
+ "traceClass": "TRACE_FUNC"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "MD_TOPSM"
+}
diff --git a/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_ostd_utmd.json b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_ostd_utmd.json
new file mode 100644
index 0000000..2c9ce21
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_ostd_utmd.json
@@ -0,0 +1,385 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_OSTD",
+ "startGen": "Legacy",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "DesignInfo"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "OSTD_ITC": {
+ "format": "Failed to get ITC lock(0x%x)",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "OSTD_ISR": {
+ "format": "OSTD_ISR = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_INF_SLEEP_TRG": {
+ "apiType": "index",
+ "format": "OSTD_IS : Infinite Sleep is Triggered , time_64 = %d",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "OSTD_Radio_Off_SleepCheck_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio OFF SleepCheck is Triggered , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_Radio_Off_2STimer_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio OFF 2s timer timeout, slp_cnt_old = %d , slp_cnt = %d , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_Radio_Off_3STimer_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio OFF 3s timer timeout, slp_cnt_old = %d , slp_cnt = %d , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_Radio_Off_3STimer_ReTRG": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio OFF Valid Wake-Up's FINAL Check , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_Radio_Off_WakeUp_Bypass": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio OFF Bypass Valid Wake-Up Event! Resetting Timer , time_64 = %d",
+ "traceClass": "TRACE_WARNING"
+ }
+ },
+ {
+ "OSTD_Radio_On_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio_On is Triggered , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_Radio_Off_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : Radio_Off is Triggered , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_CheckSleep_EFUN_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : CheckSleep EFUN=0 , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_CheckSleep_EPOF_TRG": {
+ "apiType": "index",
+ "format": "OSTD_F : CheckSleep EPOF , time_64 = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_INF_SLEEP_TimerInform": {
+ "format": "OSTD_IS: [%s] Timer Triggered Infinite Sleep? [%s] -> MD/L1-Timer_STA = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_Flight_MODE_STATUS": {
+ "apiType": "index",
+ "format": "OSTD_F : Flight mode status %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_DBG1": {
+ "apiType": "index",
+ "format": "TRC_ID[%d], Value1 = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_DBG2": {
+ "apiType": "index",
+ "format": "TRC_ID[%d], Value1 = 0x%x, Value2 = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_DBG3": {
+ "apiType": "index",
+ "format": "TRC_ID[%d], Value1 = 0x%x, Value2 = 0x%x, Value3 = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_DBG4": {
+ "apiType": "index",
+ "format": "TRC_ID[%d], Value1 = 0x%x, Value2 = 0x%x, Value3 = 0x%x, Value4 = 0x%x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG": {
+ "apiType": "index",
+ "format": "OSTD_SM : MD active_dur = %u, sleep_dur = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG1": {
+ "apiType": "index",
+ "format": "OSTD_SM : OST_ISR = 0x%x, PWR_off = 0x%x, MD_26M_off_tick = 0x%x, All_26M_off_tick = 0x%x, 32k_Tick = %u, USC_Time = %u, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG3": {
+ "apiType": "index",
+ "format": "OSTD_SM : (%d, %d, 0x%08x), (%d, %d, 0x%08x), (%d, %d, 0x%08x), (%d, %d, 0x%08x), (%d, %d, 0x%08x), (%d, %d, 0x%08x), (%d, %d, 0x%08x), (%d, %d, 0x%08x)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG2_MD95": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x 0x%x, smDis = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG4_MD95": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, OST_ISR = 0x%x, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x 0x%x, F32K_WkUp = 0x%08x 0x%08x, NonF32K_WkUp = 0x%08x 0x%08x, Slave_Req = 0x%08x, Dbg_Req = 0x%08x 0x%08x, recently wakeup timer = %s, dest_mod_id = 0x%x, ev=0x%x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG2_MD95_2CORES": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x, smDis = 0x%08x 0x%08x 0x%08x 0x%08x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG4_MD95_2CORES": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, OST_ISR = 0x%x, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x, F32K_WkUp = 0x%08x 0x%08x, NonF32K_WkUp = 0x%08x 0x%08x, Slave_Req = 0x%08x, Dbg_Req = 0x%08x 0x%08x, recently wakeup timer = %s, dest_mod_id = 0x%x, ev=0x%x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG2_MD93": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x, smDis = 0x%08x 0x%08x 0x%08x 0x%08x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG4_MD93": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, OST_ISR = 0x%x, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x, F32K_WkUp = 0x%08x 0x%08x, NonF32K_WkUp = 0x%08x 0x%08x, Slave_Req = 0x%08x, Dbg_Req = 0x%08x 0x%08x, recently wakeup timer = %s, dest_mod_id = 0x%x, ev=0x%x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG2_MD97": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x 0x%x 0x%x, smDis = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_LEAVE_SLEEP_TRG4_MD97": {
+ "apiType": "index",
+ "format": "OSTD_SM : %Mslp_lock_type_e, OST_ISR = 0x%x, PWR_off_to_on = 0x%x, PWR_status = 0x%x, ForceOn = 0x%x 0x%x 0x%x, F32K_WkUp = 0x%08x 0x%08x, NonF32K_WkUp = 0x%08x 0x%08x, Slave_Req = 0x%08x, Dbg_Req = 0x%08x 0x%08x, recently wakeup timer = %s, dest_mod_id = 0x%x, ev=0x%x, APP_OUTCR_SET = 0x%08x, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_INT_STATUS2": {
+ "format": "OSTD_SM : OST_ISR_STA = 0x%x, USC_Time = 0x%x, Sleep_Disable = 0x%x, Sleep_Disable_ext = 0x%x, F32K_WkUp = 0x%x, F32K_WkUp2 = 0x%x, F32K_WkUp3 = 0x%x, NonF32K_WkUp = 0x%x, NonF32K_WkUp2 = 0x%x, FRC_PRE = 0x%x, FRC_AFT = 0x%x, Sleep_Dur = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_INT_STATUS3": {
+ "format": "OSTD.Dbg : Slp_Record = 0x%x, PWR_OFF_Record = 0x%x, PLL_OFF_Record = 0x%x, Pre.ps_sysclk_cnt = 0x%x, Cnt_After.ps_sysclk_cnt = 0x%x, Cnt_After.md_sysclk_cnt = 0x%x, Cnt_Pre.all_sysclk_cnt = 0x%x, Cnt_After.all_sysclk_cnt = 0x%x, Last_WakeUp_Dur = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "OSTD_PS_BYPASS_AFNUFN": {
+ "apiType": "index",
+ "format": "[Vpe%d]OSTD : OSTD_SetAfnUfn bypass (OSTD_ISR = 0x%02x)",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "OSTD_LPM_STATUS": {
+ "apiType": "index",
+ "format": "OSTD_LPM : base_addr = 0x%x, buf_size = 0x%x, cur_buf_ptr = 0x%x, frame_limit = 0x%x, frame_record_num = 0x%x, record_size = 0x%x, total_rec = 0x%x, cur_rec = 0x%x, cur_frames = 0x%x, dhl_tx_call_num = 0x%x, dhl_tx_pre_num = 0x%x, send_result=0x%x",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "OSTD_AP_CORE_STATUS": {
+ "apiType": "index",
+ "format": "AP status = %Mostd_ap_core_status_enum, CurFRC = %u",
+ "traceClass": "TRACE_INFO"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "OSTD"
+}
diff --git a/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_sleepdrv_utmd.json b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_sleepdrv_utmd.json
new file mode 100644
index 0000000..215df7e
--- /dev/null
+++ b/mcu/driver/sleep_drv/internal/inc/sleep_drv_trc_mod_sleepdrv_utmd.json
@@ -0,0 +1,206 @@
+{
+ "endGen": "Legacy",
+ "legacyParameters": {},
+ "module": "MOD_SLEEPDRV",
+ "startGen": "Legacy",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Medium",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "DesignInfo"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "InternalDesign"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Low",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "CoreDesign"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "SLEEPDRV_MESSAGE": {
+ "format": "Core[%d]: Message = [%s]",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLEEPDRV_DRV_DBG1": {
+ "format": "CMD = 0x%x, Value1 = 0x%x, Value2 = 0x%x, USC_CUR = 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "SLEEPDRV_DRV_DBG2": {
+ "format": "CMD = 0x%x, Value1 = 0x%x, Value2 = 0x%x, Value3 = 0x%x, USC_CUR = 0x%x",
+ "traceClass": "TRACE_STATE"
+ }
+ },
+ {
+ "SLEEPDRV_LOCK": {
+ "format": "[Core%d]SM: Disable SM handler index=%d, caller address = 0x%08x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLEEPDRV_API": {
+ "format": "[Core%d]SM: Call SM handler API=0x%08x, enable(0)/disable(1)=%d, lock_index=%d, smDis=0x%08x, smDis_ext=0x%08x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLEEPDRV_ATCMD": {
+ "format": "[Vpe%d]SM: AT_CMD( AT+EGCMD=%d )",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLEEPDRV_LOCKSTATE": {
+ "format": "[Core%d]SM: Disable state=0x%08x, Disable_ext_state= 0x%08x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLEEPDRV_PWR_STA": {
+ "format": "Power%d(0x%08x) = 0x%08x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "SLEEPDRV_PLL_STA": {
+ "format": "PLL%d(0x%08x) = 0x%08x",
+ "traceClass": "TRACE_INFO"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "SLEEPDRV"
+}