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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/sys_drv/init/inc/config_hw.h b/mcu/driver/sys_drv/init/inc/config_hw.h
new file mode 100644
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+++ b/mcu/driver/sys_drv/init/inc/config_hw.h
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+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * config_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for CONFIG hardware registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CONFIG_HW_H__
+#define __CONFIG_HW_H__
+
+#include "reg_base.h"
+
+/*******************************************************************************
+ * Version
+ *******************************************************************************/
+#define HW_VER ((volatile UINT16P)(MD_CONFIG_base+0x0000))
+#define FW_VER ((volatile UINT16P)(MD_CONFIG_base+0x0004))
+#define SW_VER FW_VER
+#define HW_CODE ((volatile UINT16P)(MD_CONFIG_base+0x0008))
+#define HW_SUBCODE ((volatile UINT16P)(MD_CONFIG_base+0x000C))
+
+/*******************************************************************************
+ * System special register
+ *******************************************************************************/
+#define SW_MISC_L ((volatile UINT32P)(MD_CONFIG_base+0x10))
+#define SW_MISC_H ((volatile UINT32P)(MD_CONFIG_base+0x14))
+
+/* boot mode control register */
+/* New chip will have SW_MISC_L, plesae do not specify specific address */
+#define BOOT_CONFIG_ADDR SW_MISC_L
+#define BOOT_SLAVE_ADDR_PTR ((volatile UINT32P)0xFFFF0020)
+
+#endif /* !__CONFIG_HW_H__ */
+
diff --git a/mcu/driver/sys_drv/init/inc/cps.h b/mcu/driver/sys_drv/init/inc/cps.h
new file mode 100644
index 0000000..c0d5d1a
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/cps.h
@@ -0,0 +1,881 @@
+/*
+ * cps.h
+ *
+ */
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+/*
+ * This include file contains #defines for the memory mapped registers in a coherent Processing system
+ * of both single cores and multi threaded cores. It contains registers offset for all the registers,
+ * defines for the fields with in the registers and encodings for some of the fields.
+ *
+ * The fields in the registers are defined by a pair of #defines, one define is the starting bit position of
+ * the field and another, (with a "_S" appended to the name), is the size of the field. Here is an example of
+ * how you would use these #defines in the the extraction of a filed:
+ *
+ * li $5, GIC_BASE_ADDR # load GIC KSEG0 Address
+ * lw $4, GIC_SH_CONFIG($5) # Read the GIC_SH_CONFIG Register
+ * ext $4, NUMINTERRUPTS, NUMINTERRUPTS_S # Extract NUMINTERRUPTS
+ *
+ * The names for the registers and fields are usually the same as used in the Software Users Manual
+ * (SUM). The exceptions occur when the names would conflict with each other in that case the name
+ * is appended with something to make it unique.
+ */
+
+#ifndef CPS_H_
+#define CPS_H_
+
+// GCR Offset for GCR_CONFIG, field positions and field size
+#define GCR_CONFIG 0x0000
+#define NUM_ADDR_REGIONS 16
+#define NUM_ADDR_REGIONS_S 4
+#define NUMIOCU 8
+#define NUMIOCU_S 4
+#define PCORES 0
+#define PCORES_S 8
+#define PCORE_MASK 0x000000ff
+#define NUMIOCU_MASK 0x00000f00
+#define NUM_ADDR_REGIONS_MASK 0x000f0000
+
+
+// GCR Offset for GCR_BASE, field positions and field size
+#define GCR_BASE 0x0008
+#define GCR_BASE_ADDR 15
+#define GCR_BASE_ADDR_S 17
+#define CCA_DEFAULT_OVERRIDE_VALUE 5
+#define CCA_DEFAULT_OVERRIDE_VALUE_S 3
+#define CCA_DEFAULT_OVERRIDE_ENABLE 4
+#define CCA_DEFAULT_OVERRIDE_ENABLE_S 1
+#define CM_DEFAULT_TARGET 0
+#define CM_DEFAULT_TARGET_S 2
+
+// GCR Offset for GCR_CONTROL, field positions and field size
+#define GCR_CONTROL 0x0010
+#define SYNCCTL 16
+#define SYNCCTL_S 1
+#define CM_SYNC_TX_DISABLE 5
+#define CM_SYNC_TX_DISABLE_S 1
+#define CM_AUTO_CLR_IVU_EN 4
+#define CM_AUTO_CLR_IVU_EN_S 1
+#define CM_COHST_SH_ALWAYS_EN 3
+#define CM_COHST_SH_ALWAYS_EN_S 1
+#define CM_PARK_EN 2
+#define CM_PARK_EN_S 1
+#define CM_DISABLE_MMIO_LIMIT 1
+#define CM_DISABLE_MMIO_LIMIT_S 1
+#define CM_SPEC_READ_EN 0
+#define CM_SPEC_READ_EN_S 1
+
+// GCR Offset for GCR_CONTROL_2, field positions and field size
+#define GCR_CONTROL2 0x0018
+#define L2_CACHEOP_LIMIT 16
+#define L2_CACHEOP_LIMIT_S 4
+#define L1_CACHEOP_LIMIT 3
+#define L1_CACHEOP_LIMIT_S 4
+
+// GCR Offset for GCR_ACCESS, field positions and field size
+#define GCR_ACCESS 0x0020
+#define CM_ACCESS_EN 0
+#define CM_ACCESS_EN_S 8
+
+// GCR Offset for GCR_REV, field positions and field size
+#define GCR_REV 0x0030
+#define MAJOR_REV_GCR 8
+#define MAJOR_REV_GCR_S 8
+#define MINOR_REV_GCR 7
+#define MINOR_REV_GCR_S 8
+
+// GCR Offset for GCR_ERROR_MASK
+#define GCR_ERROR_MASK 0x0040
+
+// error type encoding
+#define GC_WR_ERR 1
+#define GC_RD_ERR 2
+#define COH_WR_ERR 3
+#define COH_RD_ERR 4
+#define MMIO_WR_ERR 5
+#define MMIO_RD_ERR 6
+#define INTVN_WR_ERR 17
+#define INTVN_RD_ERR 18
+
+// GCR Offset for GCR_ERROR_CAUSE, field positions and field size
+#define GCR_ERROR_CAUSE 0x0048
+#define CM_ERROR_TYPE 27
+#define CM_ERROR_TYPE_S 5
+#define CM_ERROR_INFO 0
+#define CM_ERROR_INFO_S 27
+
+// Fields and sizes for Error Types 1 - 5
+#define CCA 15
+#define CCA_S 3
+#define TARGET_REGION 12
+#define TARGET_REGION_S 3
+#define OCP_MCMD_ERROR 7
+#define OCP MCMD_ERROR_S 5
+#define SOURCE_TAGID 3
+#define SOURCE_TAGID_S 4
+#define SOURCE_PORT 0
+#define SOURCE_PORT_S 3
+
+// Fields for Error Types 16 - 17
+#define COHERENT_STATE_CORE_3 19
+#define COHERENT_STATE_CORE_3_S 2
+#define INTERVENTION_SRESP_CORE3 18
+#define INTERVENTION_SRESP_CORE3_S 1
+
+#define COHERENT_STATE_CORE_2 16
+#define COHERENT_STATE_CORE_2_S 2
+#define INTERVENTION_SRESP_CORE2 15
+#define INTERVENTION_SRESP_CORE2_S 1
+
+#define COHERENT_STATE_CORE_1 13
+#define COHERENT_STATE_CORE_1_S 2
+#define INTERVENTION_SRESP_CORE1 12
+#define INTERVENTION_SRESP_CORE1_S 1
+
+#define COHERENT_STATE_CORE_0 10
+#define COHERENT_STATE_CORE_0_S 2
+#define INTERVENTION_SRESP_CORE0 9
+#define INTERVENTION_SRESP_CORE0_S 1
+
+#define FROM_STORE_CONDITIONAL 8
+#define FROM_STORE_CONDITIONAL_S 1
+#define OCP_MCMD 3
+#define OCP_MCMD_S 5
+#define SOURCE_PORT 0
+#define SOURCE_PORT_S 3
+
+// Coherent state encoding
+#define CS_INVALID 0
+#define CS_SHARED 1
+#define CS_MODIFID 2
+#define CS_EXCLUSIVE
+
+// Intervention Response encoding
+#define IR_OK 0
+#define IR_DATA 1
+
+// MCmd Encodings for CM_ERROR_INFO
+#define LEGACY_WRITE 0x01
+#define LEGACY_READ 0x02
+#define COHERENT_READ_OWN 0x08
+#define COHERENT_READ_SHARE 0x09
+#define COHERENT_READ_DISCARD 0x0A
+#define COHERENT_READ_SHARE_ALWAYS 0x0B
+#define COHERENT_UPGRADE 0x0C
+#define COHERENT_WRITEBACK 0x0D
+#define COHERENT_COPYBACK 0x10
+#define COHERENT_COPYBACK_INVALIADATE 0x11
+#define COHERENT_INVALIADATE 0x12
+#define COHERENT_WRITE_INVALIADATE 0x13
+#define COHERENT_COMPLETION_SYNC 0x14
+
+// GCR Offset for GCR_ERROR_ADDR
+#define GCR_ERROR_ADDR 0x0050
+
+// GCR Offset for GCR_ERROR_MULT
+#define GCR_ERROR_MULT 0x0058
+#define CM_ERROR_2ND 0
+#define CM_ERROR_2ND_S 5
+
+// GCR Offset for GCR_GIC_BASE, fields and sizes
+#define GCR_GIC_BASE 0x0080
+#define GIC_BASEADDRESS 17
+#define GIC_BASEADDRESS_S 15
+#define GIC_EN 0
+#define GIC_EN_S 1
+
+// GCR Offset for GCR_CPC_BAS, fields and sizes
+#define GCR_CPC_BASE 0x0088
+#define CPC_BASEADDRESS 15
+#define CPC_BASEADDRESS_S 17
+#define CPC_EN 0
+#define CPC_EN_S 1
+
+// GCR Offset for GCR_REGn_BASE, fields and sizes
+#define GCR_REG0_BASE 0x0090
+#define GCR_REG1_BASE 0x00A0
+#define GCR_REG2_BASE 0x00B0
+#define GCR_REG3_BASE 0x00C0
+#define GCR_REG4_BASE 0x0190
+#define GCR_REG5_BASE 0x01A0
+#define GCR_REG6_BASE 0x0210
+#define GCR_REG7_BASE 0x0220
+
+#define CM_REGION_BASEADDRESS 16
+#define CM_REGION_BASEADDRESS_S 16
+
+// GCR Offset for GCR_REGn_MASK, fields, sizes and encodings
+#define GCR_REG0_MASK 0x0098
+#define GCR_REG1_MASK 0x00A8
+#define GCR_REG2_MASK 0x00B8
+#define GCR_REG3_MASK 0x00C8
+#define GCR_REG4_MASK 0x0198
+#define GCR_REG5_MASK 0x01A8
+#define GCR_REG6_MASK 0x0218
+#define GCR_REG7_MASK 0x0228
+
+#define CM_REGION_ADDRESS_MASK 16
+#define CM_REGION_ADDRESS_MASK_S 16
+#define CCA_OVERRIDE_VALUE 5
+#define CCA_OVERRIDE_VALUE_S 3
+#define CCA_OVERRIDE_ENABLE 4
+#define CCA_OVERRIDE_ENABLE_S 1
+#define CM_REGION_TARGET 0
+#define CM_REGION_TARGET_S 2
+// CM_REGION_TARGET encoding
+#define CM_REGION_TARGET_DISABLE 0x0
+#define CM_REGION_TARGET_MEMORY 0x1
+#define CM_REGION_TARGET_IOCU 0x2
+
+// GCR Offset for GCR_GIC_STATUS, fields and sizes
+#define GCR_GIC_STATUS 0x00D0
+#define GIC_EX 0
+#define GIC_EX_S 1
+
+// GCR Offset for GCR_CACHE_REV, fields and sizes
+#define GCR_CACHE_REV 0x00E0
+#define MAJOR_REV_CACHE 8
+#define MAJOR_REV_CACHE_S 8
+#define MINOR_REV_CACHE 7
+#define MINOR_REV_CACHE_S 8
+
+// GCR Offset for GCR_CPC_STATUS, fields and sizes
+#define GCR_CPC_STATUS 0x00F0
+#define CPC_EX 0
+#define CPC_EX_S 1
+
+// GCR Offset for GCR_IOCU1_REV, fields and sizes
+#define GCR_IOCU1_REV 0x0200
+#define MAJOR_REV_IOCU 8
+#define MAJOR_REV_IOCU_S 8
+#define MINOR_REV_IOCU 7
+#define MINOR_REV_IOCU_S 8
+
+// GCR Core Local and Core other offsets
+#define CORE_LOCAL_CONTROL_BLOCK 0x2000
+#define CORE_OTHER_CONTROL_BLOCK 0x4000
+
+// GCR Core Local and Other COHERENCE, fields and sizes
+#define GCR_CL_COHERENCE 0x0008
+#define GCR_CO_COHERENCE 0x0008
+#define COH_DOMAIN_EN 0
+#define COH_DOMAIN_EN_S 8
+
+// GCR Core Local and Other CONFIG , fields and sizes
+#define GCR_CL_CONFIG 0x0010
+#define GCR_CO_CONFIG 0x0010
+#define IOCU_TYPE 10
+#define IOCU_TYPE_S 2
+#define PVPE 0
+#define PVPE_S 10
+
+// GCR Core Local and Other OTHER, fields and sizes
+#define GCR_CL_OTHER 0x0018
+#define GCR_CO_OTHER 0x0018
+#define OTHER_CORE_NUM 16
+#define OTHER_CORE_NUM_S 16
+
+// GCR Core Local and Other RESET_BASE, fields and sizes
+#define GCR_CL_RESET_BASE 0x0020
+#define GCR_CO_RESET_BASE 0x0020
+#define BEV_EXCEPTION_BASE 12
+#define BEV_EXCEPTION_BASE_S 20
+
+// GCR Core Local and Other ID
+#define GCR_CL_ID 0x0028
+#define GCR_CO_ID 0x0028
+
+// GCR Global Debug Block Offsets
+#define Global_Debug_Block 0x6000
+
+// GCR Global Debug GCR_DB_TCBCONTROLB, fields and sizes
+#define GCR_DB_TCBCONTROLB 0x0008
+#define WE_DB_TCBCONTROLB 31
+#define WE_DB_TCBCONTROLB_S 1
+#define TWSRC_WIDTH 26
+#define TWSRC_WIDTH_S 2
+#define TRPAD 18
+#define TRPAD_S 1
+#define RM 16
+#define RM_S 1
+#define TR 15
+#define TR_S 1
+#define BF 14
+#define BF_S 1
+#define TM 12
+#define TM_S 2
+#define CR 8
+#define CR_S 3
+#define CAL 7
+#define CAL_S 1
+#define OFC 1
+#define OFC_S 1
+#define FUNNEL_TRACE_ENABLE 0
+#define FUNNEL_TRACE_ENABLE_S 1
+
+// GCR Global Debug GCR_DB_TCBCONTROLD, fields and sizes
+#define GCR_DB_TCBCONTROLD 0x0010
+#define P4_CTL 24
+#define P4_CTL_S 2
+#define P3_CTL 22
+#define P3_CTL_S 2
+#define P2_CTL 20
+#define P2_CTL_S 2
+#define P1_CTL 18
+#define P1_CTL_S 2
+#define P0_CTL 16
+#define P0_CTL_S 2
+#define TW_SRC_VAL 8
+#define TW_SRC_VAL_S 3
+#define TRACE_WB 7
+#define TRACE_WB_S 1
+#define CM_INHIBIT_OVERFLOW 5
+#define CM_INHIBIT_OVERFLOW_S 1
+#define TLEV 3
+#define TLEV_S 2
+#define AE_PER_PORT 2
+#define AE_PER_PORT_S 1
+#define GLOBAL_CM_EN 1
+#define GLOBAL_CM_EN_S 1
+#define CM_EN 0
+#define CM_EN_S 1
+
+// GCR Global Debug GCR_DB_TCBCONTROLE, fields and sizes
+#define GCR_DB_TCBCONTROLE 0x0020
+#define TrIdle 8
+#define TrIdle_S 1
+#define PeC 0
+#define PeC_S 1
+
+// GCR Global Debug GCR_DB_TCBConfig, fields and sizes
+#define GCR_DB_TCBCONFIG 0x0028
+#define CF1 31
+#define CF1_S 1
+#define SZ 17
+#define SZ_S 4
+#define CRMAX 14
+#define CRMAX_S 3
+#define CRMIN 11
+#define CRMIN_S 3
+#define PW 9
+#define PW_S 2
+#define ONT 5
+#define ONT_S 1
+#define OFT 4
+#define OFT_S 1
+#define TCB_REV 0
+#define TCB_REV_S 4
+
+// GCR Global Debug GCR_DB_PC_CTL, fields and sizes
+#define GCR_DB_PC_CTL 0x0100
+#define PERF_INT_EN 30
+#define PERF_INT_EN_S 1
+#define PERF_OVF_STOP 29
+#define PERF_OVF_STOP_S 1
+#define P1_RESET 9
+#define P1_RESET_S 1
+#define P1_COUNT_ON 8
+#define P1_COUNT_ON_S 1
+#define P0_RESET 7
+#define P0_RESET_S 1
+#define P0_COUNT_ON 6
+#define P0_COUNT_ON_S 1
+#define CYCL_CNT_RESET 5
+#define CYCL_CNT_RESET_S 1
+#define CYCL_CNT__ON 4
+#define CYCL_CNT__ON_S 1
+#define PERF_NUM_CNT 0
+#define PERF_NUM_CNT_S 4
+
+// GCR Global Debug Read Pointer GCR_DB_TCBRDP
+#define GCR_DB_TCBRDP 0x0108
+
+// GCR Global Debug Write Pointer GCR_DB_TCBWDP
+#define GCR_DB_TCBWRP 0x0110
+
+// GCR Global Debug Start Pointer GCR_DB_TCBSTP
+#define GCR_DB_TCBSTP 0x0118
+
+// GCR_DB_PC_OV, fields and sizes
+#define GCR_DB_PC_OV 0x0120
+#define P1_OVERFLOW 2
+#define P1_OVERFLOW_S 1
+#define P0_OVERFLOW 1
+#define P0_OVERFLOW_S 1_S 1
+#define CYCL_CNT_OVERFLOW 0
+#define CYCL_CNT_OVERFLOW_S 1
+
+// GCR Global Debug GCR_DB_PC_EVENT, fields and sizes
+#define GCR_DB_PC_EVENT 0x0130
+#define P1_EVENT 8
+#define P1_EVENT_S 8
+#define P0_EVENT 0
+#define P0_EVENT_S 8
+
+// GCR Global Debug GCR_DB_PC_CYCLE
+#define GCR_DB_PC_CYCLE 0x0180
+
+
+// GCR Global Debug Qualifier and count registers
+#define GCR_DB_PC_QUAL0 0x0190
+#define GCR_DB_PC_CNT0 0x0198
+#define GCR_DB_PC_QUAL1 0x01a0
+#define GCR_DB_PC_CNT1 0x01a8
+
+// GCR Global Debug Trace word access registers
+#define GCR_DB_TCBTW_LO 0x0200
+#define GCR_DB_TCBTW_HI 0x0208
+
+// GIC Offsets within the Global interrupt controller
+
+#define GIC_SH_CONFIG 0x0000
+#define COUNTSTOP 28
+#define COUNTSTOP_S 1
+#define COUNTBITS 24
+#define COUNTBITS_S 4
+#define NUMINTERRUPTS 16
+#define NUMINTERRUPTS_S 8
+#define PVPES 0
+#define PVPES_S 9
+
+#define GIC_SH_CounterLo 0x0010
+#define GIC_SH_CounterHi 0x0014
+
+#define GIC_RevisionID 0x0020
+
+#define GIC_SH_POL31_0 0x0100
+#define GIC_SH_POL63_32 0x0104
+#define GIC_SH_POL95_64 0x0108
+#define GIC_SH_POL127_96 0x010c
+#define GIC_SH_POL159_128 0x0110
+#define GIC_SH_POL191_160 0x0114
+#define GIC_SH_POL223_192 0x0118
+#define GIC_SH_POL255_224 0x011c
+
+#define GIC_SH_TRIG31_0 0x0180
+#define GIC_SH_TRIG63_32 0x0184
+#define GIC_SH_TRIG95_64 0x0188
+#define GIC_SH_TRIG127_96 0x018c
+#define GIC_SH_TRIG159_128 0x0190
+#define GIC_SH_TRIG191_160 0x0194
+#define GIC_SH_TRIG223_192 0x0198
+#define GIC_SH_TRIG255_224 0x019c
+
+#define GIC_SH_DUAL31_0 0x0200
+#define GIC_SH_DUAL63_32 0x0204
+#define GIC_SH_DUAL95_64 0x0208
+#define GIC_SH_DUAL127_96 0x020c
+#define GIC_SH_DUAL159_128 0x0210
+#define GIC_SH_DUAL159_128 0x0210
+#define GIC_SH_DUAL191_160 0x0214
+#define GIC_SH_DUAL223_192 0x0218
+#define GIC_SH_DUAL255_224 0x021c
+
+#define GIC_SH_WEDGE 0x0280
+
+#define GIC_SH_RMASK31_0 0x0300
+#define GIC_SH_RMASK63_32 0x0304
+#define GIC_SH_RMASK95_64 0x0308
+#define GIC_SH_RMASK127_96 0x030c
+#define GIC_SH_RMASK159_128 0x0310
+#define GIC_SH_RMASK191_160 0x0314
+#define GIC_SH_RMASK223_192 0x0318
+#define GIC_SH_RMASK255_224 0x031c
+
+#define GIC_SH_SMASK31_00 0x0380
+#define GIC_SH_SMASK63_32 0x0384
+#define GIC_SH_SMASK95_64 0x0388
+#define GIC_SH_SMASK127_96 0x038c
+#define GIC_SH_SMASK159_128 0x0390
+#define GIC_SH_SMASK191_160 0x0394
+#define GIC_SH_SMASK223_192 0x0398
+#define GIC_SH_SMASK255_224 0x039c
+
+#define GIC_SH_MASK31_00 0x0400
+#define GIC_SH_MASK63_32 0x0404
+#define GIC_SH_MASK95_64 0x0408
+#define GIC_SH_MASK127_96 0x040c
+#define GIC_SH_MASK159_128 0x0410
+#define GIC_SH_MASK191_160 0x0414
+#define GIC_SH_MASK223_192 0x0418
+#define GIC_SH_MASK255_224 0x041c
+
+#define GIC_SH_PEND31_00 0x0480
+#define GIC_SH_PEND63_32 0x0484
+#define GIC_SH_PEND95_64 0x0488
+#define GIC_SH_PEND127_96 0x048c
+#define GIC_SH_PEND159_128 0x0490
+#define GIC_SH_PEND191_160 0x0494
+#define GIC_SH_PEND223_192 0x0498
+#define GIC_SH_PEND255_224 0x049c
+
+// Global MAP to Pin GIC_SH_MAP_PIN + (4 x interrupt_source)
+#define GIC_SH_MAP_PIN 0x0500
+
+#define GIC_SH_MAP_SPACER 0x20
+// Map source to VPEs 31 - 0 GIC_SH_MAP0_VPE31_0 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_VPE31_0 0x2000
+// Map source to VPEs 63 - 32 GIC_SH_MAP0_VPE63_32 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_VPE63_32 0x2004
+
+// Map source to core 31 - 0 GIC_SH_MAP0_CORE31_0 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_CORE31_0 0x2000
+// Map source to core 63 - 32 GIC_SH_MAP0_CORE63_32 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_CORE63_32 0x2004
+
+#define GIC_VB_DINT_SEND 0x6000
+
+// GIC VPE Local offsets (note the VPEL)
+#define GIC_VPE_LOCAL_SECTION_OFFSET 0x8000
+
+#define GIC_VPEL_CTL 0x0000
+#define GIC_VPEL_PEND 0x0004
+#define GIC_VPEL_MASK 0x0008
+#define GIC_VPEL_RMASK 0x000c
+#define GIC_VPEL_SMASK 0x0010
+#define GIC_VPEL_WD_MAP 0x0040
+#define GIC_VPEL_COMPARE_MAP 0x0044
+#define GIC_VPEL_TIMER_MAP (0x0048 )
+#define GIC_VPEL_FDC_MAP 0x004c
+#define GIC_VPEL_PERFCTR_MAP 0x0050
+#define GIC_VPEL_SWInt0_MAP 0x0054
+#define GIC_VPEL_SWInt1_MAP 0x0058
+#define GIC_VPEL_OTHER_ADDR 0x0080
+#define GIC_VPEL_IDENT 0x0088
+#define GIC_VPEL_WD_CONFIG0 0x0090
+#define GIC_VPEL_WD_COUNT0 0x0094
+#define GIC_VPEL_WD_INITIAL0 0x0098
+#define GIC_VPEL_CompareLo 0x00A0
+#define GIC_VPEL_CompareHi 0x00A4
+
+// NOTE: EIC Shadow set GIC_VPEL_EICSS + (4 x interrupt number)
+#define GIC_VPEL_EICSS 0x0100
+#define GIC_VL_DINT_PART 0x3000
+#define GIC_VL_BRK_GROUP 0x3080
+
+// GIC VPE Other offsets (note the VPEO)
+#define GIC_VPE_OTHER_SECTION_OFFSET 0xc000
+
+#define GIC_VPEO_CTL 0x0000
+#define GIC_VPEO_PEND 0x0004
+#define GIC_VPEO_MASK 0x0008
+#define GIC_VPEO_RMASK 0x000c
+#define GIC_VPEO_SMASK 0x0010
+#define GIC_VPEO_WD_MAP 0x0040
+#define GIC_VPEO_COMPARE_MAP 0x0044
+#define GIC_VPEO_TIMER_MAP 0x0048
+#define GIC_VPEO_FDC_MAP 0x004c
+#define GIC_VPEO_PERFCTR_MAP 0x0050
+#define GIC_VPEO_SWInt0_MAP 0x0054
+#define GIC_VPEO_SWInt1_MAP 0x0058
+#define GIC_VPEO_OTHER_ADDR 0x0080
+#define GIC_VPEO_IDENT 0x0088
+#define GIC_VPEO_WD_CONFIG0 0x0090
+#define GIC_VPEO_WD_COUNT0 0x0094
+#define GIC_VPEO_WD_INITIAL0 0x0098
+#define GIC_VPEO_CompareLo 0x00A0
+#define GIC_VPEO_CompareHi 0x00A4
+
+// NOTE: EIC Shadow set GIC_VPEO_EICSS + (4 x interrupt number)
+#define GIC_VPEO_EICSS 0x0100
+#define GIC_VO_DINT_PART 0x3000
+#define GIC_VO_BRK_GROUP 0x3080
+
+// GIC CORE Local offsets (note the COREL)
+#define GIC_CORE_LOCAL_SECTION_OFFSET 0x8000
+
+#define GIC_COREL_CTL 0x0000
+#define GIC_COREL_PEND 0x0004
+#define GIC_COREL_MASK 0x0008
+#define GIC_COREL_RMASK 0x000c
+#define GIC_COREL_SMASK 0x0010
+#define GIC_COREL_WD_MAP 0x0040
+#define GIC_COREL_COMPARE_MAP 0x0044
+#define GIC_COREL_TIMER_MAP 0x0048
+#define GIC_COREL_FDC_MAP 0x004c
+#define GIC_COREL_PERFCTR_MAP 0x0050
+#define GIC_COREL_SWInt0_MAP 0x0054
+#define GIC_COREL_SWInt1_MAP 0x0058
+#define GIC_COREL_OTHER_ADDR 0x0080
+#define GIC_COREL_IDENT 0x0088
+#define GIC_COREL_WD_CONFIG0 0x0090
+#define GIC_COREL_WD_COUNT0 0x0094
+#define GIC_COREL_WD_INITIAL0 0x0098
+#define GIC_COREL_CompareLo 0x00A0
+#define GIC_COREL_CompareHi 0x00A4
+// NOTE: EIC Shadow set GIC_COREL_EICSS + (4 x interrupt number)
+#define GIC_COREL_EICSS 0x0100
+#define GIC_COREL_DINT_PART 0x3000
+#define GIC_COREL_BRK_GROUP 0x3080
+
+// GIC CORE Other offsets (note the COREO)
+#define GIC_CORE_OTHER_SECTION_OFFSET 0xc000
+#define GIC_COREO_CTL 0x0000
+#define GIC_COREO_PEND 0x0004
+#define GIC_COREO_MASK 0x0008
+#define GIC_COREO_RMASK 0x000c
+#define GIC_COREO_SMASK 0x0010
+#define GIC_COREO_WD_MAP 0x0040
+#define GIC_COREO_COMPARE_MAP 0x0044
+#define GIC_COREO_TIMER_MAP 0x0048
+#define GIC_COREO_FDC_MAP 0x004c
+#define GIC_COREO_PERFCTR_MAP 0x0050
+#define GIC_COREO_SWInt0_MAP 0x0054
+#define GIC_COREO_SWInt1_MAP 0x0058
+#define GIC_COREO_OTHER_ADDR 0x0080
+#define GIC_COREO_IDENT 0x0088
+#define GIC_COREO_WD_CONFIG0 0x0090
+#define GIC_COREO_WD_COUNT0 0x0094
+#define GIC_COREO_WD_INITIAL0 0x0098
+#define GIC_COREO_CompareLo 0x00A0
+#define GIC_COREO_CompareHi 0x00A4
+// NOTE: EIC Shadow set GIC_COREO_EICSS + (4 x interrupt number)
+#define GIC_COREO_EICSS 0x0100
+#define GIC_COREO_DINT_PART 0x3000
+#define GIC_COREO_BRK_GROUP 0x3080
+
+
+// Bit fields for Local Interrupt Control Register (GIC_COREi_CTL) or for MT (GIC_VPEi_CTL) or
+#define FDC_ROUTABLE 4
+#define FDC_ROUTABLE_S 1
+#define SWINT_ROUTABLE 3
+#define SWINT_ROUTABLE_S 1
+#define PERFCOUNT_ROUTABLE 2
+#define PERFCOUNT_ROUTABLE_S 1
+#define TIMER_ROUTABLE 1
+#define TIMER_ROUTABLE_S 1
+#define EIC_MODE 0
+#define EIC_MODE_S 1
+
+// Bit fields for Local Interrupt Pending Registers (GIC_COREi_PEND) or for MT (GIC_VPEi_PEND)
+#define FDC_PEND 6
+#define FDC_PEND_S 1
+#define SWINT1_PEND 5
+#define SWINT1_PEND_S 1
+#define SWINT0_PEND 4
+#define SWINT0_PEND_S 1
+#define PERFCOUNT_PEND 3
+#define PERFCOUNT_PEND_S 1
+#define TIMER_PEND 2
+#define TIMER_PEND_S 1
+#define COMPARE_PEND 1
+#define COMPARE_PEND_S 1
+#define WD_PEND 0
+#define WD_PEND_S 1
+
+// Bit fields for Local Interrupt Mask Registers (GIC_COREi_MASK) or for MT (GIC_VPEi_MASK)
+#define FDC_MASK 6
+#define FDC_MASK_S 1
+#define SWINT1_MASK 5
+#define SWINT1_MASK_S 1
+#define SWINT0_MASK 4
+#define SWINT0_MASK_S 1
+#define PERFCOUNT_MASK 3
+#define PERFCOUNT_MASK_S 1
+#define TIMER_MASK 2
+#define TIMER_MASK_S 1
+#define COMPARE_MASK 1
+#define COMPARE_MASK_S 1
+#define WD_MASK 0
+#define WD_MASK_S 1
+
+// Bit fields for Local Interrupt Reset Mask Registers (GIC_COREi_RMASK) or for MT (GIC_VPEi_RMASK)
+#define FDC_MASK_RESET 6
+#define FDC_MASK_RESET_S 1
+#define SWINT1_MASK_RESET 5
+#define SWINT1_MASK_RESET_S 1
+#define SWINT0_MASK_RESET 4
+#define SWINT0_MASK_RESET_S 1
+#define PERFCOUNT_MASK_RESET 3
+#define PERFCOUNT_MASK_RESET_S 1
+#define TIMER_MASK_RESET 2
+#define TIMER_MASK_RESET_S 1
+#define COMPARE_MASK_RESET 1
+#define COMPARE_MASK_RESET_S 1
+#define WD_MASK_RESET 0
+#define WD_MASK_RESET_S 1
+
+// Bit fields for Local Interrupt Set Mask Registers (GIC_COREi_SMASK) or for MT (GIC_VPEi_SMASK)
+#define FDC_MASK_SET 6
+#define FDC_MASK_SET_S 1
+#define SWINT1_MASK_SET 5
+#define SWINT1_MASK_SET_S 1
+#define SWINT0_MASK_SET 4
+#define SWINT0_MASK_SET_S 1
+#define PERFCOUNT_MASK_SET 3
+#define PERFCOUNT_MASK_SET_S 1
+#define TIMER_MASK_SET 2
+#define TIMER_MASK_SET_S 1
+#define COMPARE_MASK_SET 1
+#define COMPARE_MASK_SET_S 1
+#define WD_MASK_SET 0
+#define WD_MASK_SET_S 1
+
+// Bit fields for CORE-Other or for MT VPE-Other Addressing Register
+#define VPENum 0
+#define VPENum_S 16
+#define CORENum 0
+#define CORENum_S 16
+
+// Bit fields for Core-Local Identification Register (GIC_COREi_IDENT) or for MT (GIC_VPEi_IDENT)
+#define VPENumIDENT 0
+#define VPENumIDENT_S 32
+#define CORENumIDENT 0
+#define CORENumIDENT_S 32
+
+// Bit fields for Local EIC Shadow Set Registers (GIC_COREi_EICSSj) or for MT (GIC_VPEi_EICSSj)
+#define EIC_SS 0
+#define EIC_SS_S 4
+
+// Bit fields for Local WatchDog/Compare/PerfCount/SWIntx Map to Pin Registers
+#define MAP_TO_PIN 31
+#define MAP_TO_PIN_S 1
+#define MAP_TO_NMI 30
+#define MAP_TO_NMI_S 1
+#define MAP_TO_YQ 29
+#define MAP_TO_YQ_S 1
+#define MAP 0
+#define MAP_S 6
+
+// Bit fields for Watchdog Timer Config Register (GIC_COREi_WD_CONFIGk) or for MT (GIC_VPEi_WD_CONFIGk)
+#define WDRESET 7
+#define WDRESET_S 1
+#define WDINTR 6
+#define WDINTR_S 1
+#define WAITMODE_CNTRL 5
+#define WAITMODE_CNTRL_S 1
+#define DEBUGMODE_CNTRL 5
+#define DEBUGMODE_CNTRL_S 1
+#define TYPE 1
+#define TYPE_S 3
+// TYPE Filed encoding:
+#define WD_One_Trip_Mode 0
+#define WD_Second_Countdown_Mode 1
+#define PIT_Mode 2
+
+// Bit fields for Local DINT Group Participate Register (GIC_Cx_DINT_PART) or for MT (GIC_Vx_DINT_PART)
+#define DINT_Group_Particpate 0
+#define DINT_Group_Particpate_S 1
+
+// GIC, GIC User Mode Visible Section Offsets
+#define USER_MODE_VISIBLE_SECTION_OFFSET 0x10000
+#define GIC_SH_COUNTERLO 0x0000
+#define GIC_SH_COUNTERHI 0x0004
+
+// Cluster Power Controller Global Section
+// CPC Block CPC_ACCESS_REG, fields and sizes
+#define CPC_ACCESS_REG 0x000
+#define CM_ACCESS_EN 0
+#define CM_ACCESS_EN_S 8
+
+// CPC Block CPC_SEQDEL_REG, fields and sizes
+#define CPC_SEQDEL_REG 0x008
+#define MICROSTEP 0
+#define MICROSTEP_S 10
+
+// CPC Block CPC_RAIL_REG, fields and sizes
+#define CPC_RAIL_REG 0x010
+#define RAILDELAY 0
+#define RAILDELAY_S 10
+
+// CPC Block CPC_RESETLEN_REG, fields and sizes
+#define CPC_RESETLEN_REG 0x018
+#define RESETLEN 0
+#define RESETLEN_S 10
+
+// CPC Block CPC_REVISION_REG, fields and sizes
+#define CPC_REVISION_REG 0x020
+#define MAJOR_REV_CPC 8
+#define MAJOR_REV_CPC_S 8
+#define MINOR_REV_CPC 0
+#define MINOR_REV_CPC_S 8
+
+// Cluster Power Controller Local and Other section
+#define CPS_CORE_LOCAL_CONTROL_BLOCK 0x2000
+#define CPS_CORE_OTHER_CONTROL_BLOCK 0x4000
+
+// CPC Local and Other CPC_CMD_REG, command encoding
+#define CPC_CMDL_REG 0x000
+#define CPC_CMDO_REG 0x000
+#define CLOCK_OFF 1
+#define PWR_DOWN 2
+#define PWR_UP 3
+#define CPC_RESET 4
+
+// CPC Local and Other CPC_STAT_CONF, fields, sizes and encodings
+#define CPC_STATL_CONF_REG 0x008
+#define CPC_STATO_CONF_REG 0x008
+#define PWRUP_EVENT 23
+#define PWRUP_EVENT_S 1
+#define SEQ_STATE 19
+#define SEQ_STATE_S 4
+
+// sequencer state encodings
+#define PWR_DOWN_STATE 0x0
+#define VDD_OK_STATE 0x1
+#define UP_DELAY_STATE 0x2
+#define UCLK_OFF_STATE 0x3
+#define CPC_RESET_STATE 0x4
+#define CPC_RESET_DLY_STATE 0x5
+#define NON_COHERENT_EXECUTION_STATE 0x6
+#define COHERENT_EXECUTION_STATE 0x7
+#define ISOLATE_STATE 0x8
+#define CLR_BUS_STATE 0x8
+#define DCLK_OFF_STATE 0xA
+
+#define CLKGAT_IMPL 17
+#define CLKGAT_IMPL_S 1
+#define PWRDN_IMPL 16
+#define PWRDN_IMPL_S 1
+#define EJTAG_PROBE 15
+#define EJTAG_PROBE_S 1
+#define PWUP_POLICY 8
+#define PWUP_POLICY_S 2
+// Power up state encodings
+#define POLICY_PWR_DOWN 0
+#define POLICY_GO_CLOCK_OFF 1
+#define PLOICY_PWR_UP 2
+
+#define IO_TRFFC_EN 4
+#define IO_TRFFC_EN_S 1
+#define CPC_CMD_STATE 0
+#define CPC_CMD_STATE_S 4
+
+// CPC Local and Other Addressing Register CPC_OTHER_REG, field and size
+#define CPC_OTHERL_REG 0x010
+#define CPC_OTHERO_REG 0x010
+#define CPC_CORENUM 16
+#define CPC_CORENUM_S 8
+
+
+#endif /* CPS_H_ */
diff --git a/mcu/driver/sys_drv/init/inc/md97/asm_common_def_gcc.h b/mcu/driver/sys_drv/init/inc/md97/asm_common_def_gcc.h
new file mode 100644
index 0000000..8cbcfa1
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/asm_common_def_gcc.h
@@ -0,0 +1,46 @@
+
+#ifndef _ASM_COMMON_DEF_GCC_
+#define _ASM_COMMON_DEF_GCC_
+
+
+#define GCC_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+
+#define GCC_ASM_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_ASM_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+.macro declare_stack name, val=0
+ .type \name , %object
+ \name :
+ .ascii "STACKEND"
+ .space \val
+ 1:
+ .size \name , 1b - \name
+.endm
+
+#if 0
+#ifdef __STACK_ALIGN_MPU__
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+#endif
+
+#endif
+
+
diff --git a/mcu/driver/sys_drv/init/inc/md97/boot_asm.h b/mcu/driver/sys_drv/init/inc/md97/boot_asm.h
new file mode 100644
index 0000000..48fc0c4
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/boot_asm.h
@@ -0,0 +1,196 @@
+
+#ifndef __BOOT_ASM_H__
+#define __BOOT_ASM_H__
+
+#include <bootarm.h>
+
+/*************************************************************************
+ * Macro definition
+ *************************************************************************/
+#define __LEGACY_NMI_CHECK__ (0x0)
+#if defined(__ESL_MASE_GEN97__)
+#define __MULTI_VPE_EN__ (0x0)
+#else /*__ESL_MASE_GEN97__*/
+#define __MULTI_VPE_EN__ (0x1)
+#endif/*__ESL_MASE_GEN97__*/
+#define MX_FEATURE (0x0)
+
+#if defined(_SIMULATION)
+#define INIT_DEF_VALUE (0x0)
+#else
+#define INIT_DEF_VALUE (0xdeadbeef)
+#endif
+
+#define BOOTTRC_MAGIC_ADDR (INT_bootup_magic)
+
+#define BOOTTRC_VPE0_ADDR (INT_bootup_trace0)
+#define BOOTTRC_VPE1_ADDR (INT_bootup_trace1)
+#define BOOTTRC_VPE2_ADDR (INT_bootup_trace2)
+
+#define BOOTTRC_VPE4_ADDR (INT_bootup_trace4)
+#define BOOTTRC_VPE5_ADDR (INT_bootup_trace5)
+#define BOOTTRC_VPE6_ADDR (INT_bootup_trace6)
+
+#define BOOTTRC_VPE8_ADDR (INT_bootup_trace8)
+#define BOOTTRC_VPE9_ADDR (INT_bootup_trace9)
+#define BOOTTRC_VPE10_ADDR (INT_bootup_trace10)
+
+#define BOOTTRC_VPE12_ADDR (INT_bootup_trace12)
+#define BOOTTRC_VPE13_ADDR (INT_bootup_trace13)
+#define BOOTTRC_VPE14_ADDR (INT_bootup_trace14)
+
+.extern Set_HS1_Boot_Trace
+.extern Boot_Trace_PreInit
+#if !defined(__COSIM_BYPASS_DRV__) && !defined(__ESL_MASE_GEN97__)
+.macro INT_TRC_SAVE_RA trace_id
+ //move $t0, $ra
+ INT_TRC \trace_id
+ //move $ra, $t0
+.endm
+.macro INT_TRC trace_id
+//#if defined(__SP_BOOTTRC_ENABLE__)
+ li $a0, \trace_id
+ la $a2, Set_HS1_Boot_Trace
+ //la $a2, INC_TRC
+ jalrc $a2
+//#endif
+.endm
+.macro INT_TRC_INIT_MAGIC
+ la $a2, Set_HS1_Boot_Trace
+ la $a1, INT_bootup_entry
+ sw $a2, 0x0($a1)
+ la $a2, Boot_Trace_PreInit
+ jalrc $a2
+.endm
+#else
+.macro INT_TRC_SAVE_RA trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC_INIT_MAGIC
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+#endif /* !defined(__COSIM_BYPASS_DRV__) */
+
+.macro INT_GET_CPUID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 4
+.endm
+
+.macro INT_GET_VPEID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 2
+.endm
+
+.macro INT_GET_COREID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 2, 2
+.endm
+
+
+/*************************************************************************
+ * Function definition
+ *************************************************************************/
+
+LEAF(INC_TRC)
+//#if defined(__SP_BOOTTRC_ENABLE__)
+
+ INT_GET_CPUID $a2, r23_cpu_num
+
+INT_init_VPE0_boot_trace:
+ li $a3, 0x0
+ bnec r23_cpu_num, $a3, INT_init_VPE1_boot_trace
+
+ li $a1, INIT_MAGIC
+ la $a2, BOOTTRC_MAGIC_ADDR
+ sw $a1, 0x0($a2)
+ la $a2, BOOTTRC_VPE0_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE1_boot_trace:
+ li $a3, 0x1
+ bnec r23_cpu_num, $a3, INT_init_VPE2_boot_trace
+
+ la $a2, BOOTTRC_VPE1_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE2_boot_trace:
+ li $a3, 0x2
+ bnec r23_cpu_num, $a3, INT_init_VPE4_boot_trace
+
+ la $a2, BOOTTRC_VPE2_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE4_boot_trace:
+ li $a3, 0x4
+ bnec r23_cpu_num, $a3, INT_init_VPE5_boot_trace
+
+ la $a2, BOOTTRC_VPE4_ADDR
+ bc INT_init_boot_trace_done
+
+
+INT_init_VPE5_boot_trace:
+ li $a3, 0x5
+ bnec r23_cpu_num, $a3, INT_init_VPE6_boot_trace
+
+ la $a2, BOOTTRC_VPE5_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE6_boot_trace:
+ li $a3, 0x6
+ bnec r23_cpu_num, $a3, INT_init_VPE8_boot_trace
+
+ la $a2, BOOTTRC_VPE6_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE8_boot_trace:
+ li $a3, 0x8
+ bnec r23_cpu_num, $a3, INT_init_VPE9_boot_trace
+
+ la $a2, BOOTTRC_VPE8_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE9_boot_trace:
+ li $a3, 0x9
+ bnec r23_cpu_num, $a3, INT_init_VPE10_boot_trace
+
+ la $a2, BOOTTRC_VPE9_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE10_boot_trace:
+ li $a3, 0xA
+ bnec r23_cpu_num, $a3, INT_init_VPE12_boot_trace
+
+ la $a2, BOOTTRC_VPE10_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE12_boot_trace:
+ li $a3, 0xC
+ bnec r23_cpu_num, $a3, INT_init_VPE13_boot_trace
+
+ la $a2, BOOTTRC_VPE12_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE13_boot_trace:
+ li $a3, 0xD
+ bnec r23_cpu_num, $a3, INT_init_VPE14_boot_trace
+
+ la $a2, BOOTTRC_VPE13_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE14_boot_trace:
+ la $a2, BOOTTRC_VPE14_ADDR
+
+
+INT_init_boot_trace_done:
+ sw $a0, 0x0($a2)
+ jrc $ra
+
+//#endif
+END(INC_TRC)
+
+
+
+#endif /* __BOOTARM_ASM_H__ */
diff --git a/mcu/driver/sys_drv/init/inc/md97/idle_service.h b/mcu/driver/sys_drv/init/inc/md97/idle_service.h
new file mode 100644
index 0000000..6edb0ed
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/idle_service.h
@@ -0,0 +1,276 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_service.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file provides idle service related header.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __IDLE_SERVICE_H__
+#define __IDLE_SERVICE_H__
+
+#include "kal_cpuinfo.h"
+
+#define VPE_NUMBER SYS_MCU_NUM_VPE
+#define CORE_NUMBER SYS_MCU_NUM_CORE
+#define PER_CORE_VPE_NUM 3
+
+#define IRQ_SW_CORE0_VPE0_LEAVE_WAIT IRQ_SW_LISR22_CODE /* IRQ ID 302 */
+#define IRQ_SW_CORE1_VPE0_LEAVE_WAIT IRQ_SW_LISR23_CODE /* IRQ ID 303 */
+#define IRQ_SW_CORE2_VPE0_LEAVE_WAIT IRQ_SW_LISR24_CODE /* IRQ ID 304 */
+#define IRQ_SW_CORE3_VPE0_LEAVE_WAIT IRQ_SW_LISR25_CODE /* IRQ ID 305 */
+
+#define IDLE_SERVICE_STEP_MAX 48
+
+#define IDLE_STATUS_NORMAL 0
+#define IDLE_STATUS_DORMANT 2
+
+#define WHOLE_CORE KAL_TRUE
+#define SINGLE_VPE KAL_FALSE
+
+typedef enum{
+/* Below for step logging */
+ IDLE_HANDLER_USER_IAPMU_CM = 0x1100,
+
+ IDLE_HANDLER_ENTER = 0x0000,
+ IDLE_HANDLER_LEAVE = 0x00FF,
+
+ IDLE_HANDLER_ENTER_DI = 0x02,
+ IDLE_REMOVE_FROM_SCHEDULING = 0x03,
+ IDLE_REMOVE_FROM_SCHEDULING_FAIL = 0x04,
+ IDLE_REMOVE_FROM_SCHEDULING_OK = 0x05,
+ IDLE_CHECK_PENDING_IRQ_FAIL = 0x06,
+ IDLE_CHECK_PENDING_IRQ_OK = 0x07,
+ IDLE_CHECK_SW_LOCK_DONE = 0x08,
+ IDLE_WAIT_CASE = 0x09,
+ IDLE_NOT_SLEEP_TIME = 0x0A,
+ IDLE_CORE_CHECK_SLEEP = 0x0B,
+ IDLE_CORE_CHECK_SLEEP_DONE = 0x0C,
+
+ IDLE_COREx_VPE1_NOT_IN_WAIT = 0x0E,
+ IDLE_DIRECTLY_WAIT = 0x0F,
+
+ IDLE_OSTD_WAIT = 0x10,
+ IDLE_OSTD_WAIT_ENTER = 0x11,
+ IDLE_OSTD_WAIT_LEAVE = 0x12,
+
+ IDLE_OSTD_BUSY = 0x20,
+
+ IDLE_OSTD_DORMANT = 0x30,
+ //IDLE_OSTD_DORMANT_ENTER = 0x31,
+ //IDLE_OSTD_DORMANT_LEAVE = 0x32,
+
+ IDLE_PTP_SLEEP_ENTER = 0x35,
+ IDLE_PTP_SLEEP_LEAVE = 0x36,
+ IDLE_PTP_WAKE_ENTER = 0x37,
+ IDLE_PTP_WAKE_LEAVE = 0x38,
+
+ IDLE_DORMANT_ABORT_LEAVE = 0x40,
+ IDLE_DORMANT_ABORT_WAIT_ENTER = 0x41,
+ IDLE_DORMANT_ABORT_WAIT_LEAVE = 0x42,
+
+ IDLE_DORMANT_RESTORE_LEAVE = 0x45,
+ IDLE_DORMANT_RESTORE_WAIT_ENTER = 0x46,
+ IDLE_DORMANT_RESTORE_WAIT_LEAVE = 0x47,
+
+ IDLE_CSC_HANDLER_ENTER = 0x48,
+ IDLE_CSC_HANDLER_LEAVE = 0x49,
+
+ IDLE_VPE1_VPE2_ENTER_SCHED = 0x50,
+
+ IDLE_WFI_WAIT_ENTER = 0x60,
+ IDLE_WFI_WAIT_LEAVE = 0x61,
+
+ IDLE_OSTD_INVALID_CASE = 0x99,
+/* Above for step logging */
+}IDLE_ACTION_INDEX;
+
+typedef enum{
+// IDLE_EMM_START_PATTERN = 0xEDEC0000 and write by CMM owner
+//IDLE TASK: WFI(=WAIT) ENTER/LEAVE per vpe
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER = 0,
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_LEAVE,
+
+//IDLE TASK: SLEEP ENTER/LEAVE per VPE
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_LEAVE,
+
+// IDLE TASK: step logging
+ IDLE_EMM_VPE0_IDLE_TASK_FMA,
+ IDLE_EMM_VPE0_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE1_IDLE_TASK_FMA,
+ IDLE_EMM_VPE1_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE2_IDLE_TASK_FMA,
+ IDLE_EMM_VPE2_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE3_IDLE_TASK_FMA,
+ IDLE_EMM_VPE3_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE4_IDLE_TASK_FMA,
+ IDLE_EMM_VPE4_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE5_IDLE_TASK_FMA,
+ IDLE_EMM_VPE5_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE6_IDLE_TASK_FMA,
+ IDLE_EMM_VPE6_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE7_IDLE_TASK_FMA,
+ IDLE_EMM_VPE7_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE8_IDLE_TASK_FMA,
+ IDLE_EMM_VPE8_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE9_IDLE_TASK_FMA,
+ IDLE_EMM_VPE9_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE10_IDLE_TASK_FMA,
+ IDLE_EMM_VPE10_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE11_IDLE_TASK_FMA,
+ IDLE_EMM_VPE11_IDLE_TASK_STEPLOGGING,
+
+//IDLE TASK: EPOF end to WFI per CORE
+ IDLE_EMM_Core0_INFINITESLEEP_WFI,
+ IDLE_EMM_Core1_INFINITESLEEP_WFI,
+ IDLE_EMM_Core2_INFINITESLEEP_WFI,
+ IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+ IDLE_EMM_INDEX_MAX = IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+// IDLE_EMM_END_PATTERN = 0xCEDE0000 and write by CMM owner
+
+}IDLE_EMM_LOG_INDEX;
+
+extern void idle_service_step_logging(kal_uint32 vpe_id, IDLE_ACTION_INDEX step, kal_bool Log_To_EMM);
+extern void Idle_Service_Prepare_WAIT(void);
+extern kal_uint32 idle_service_leave_wait_time[VPE_NUMBER];
+#if defined (__MODEM_CCCI_EXIST__)
+extern kal_bool IDLE_EMM_WriteDbgInfo(kal_uint32 index, void* addr);
+#endif
+
+#endif
+
diff --git a/mcu/driver/sys_drv/init/inc/md97/init_comm_trc.h b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc.h
new file mode 100644
index 0000000..f2de8bb
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc.h
@@ -0,0 +1,93 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_comm_trc.h
+ *
+ * Project:
+ * --------
+ * Moly_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _INIT_COMM_TRC_H
+#define _INIT_COMM_TRC_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+/*************************************************************************
+ * Define INIT trace information
+ *************************************************************************/
+#if !defined(GEN_FOR_PC)
+#if !defined(__MAUI_BASIC__)
+#include"init_comm_trc_mod_init_log_utmd.h"
+#endif
+#endif
+#endif /* _INIT_COMM_TRC_H */
diff --git a/mcu/driver/sys_drv/init/inc/md97/init_comm_trc_mod_init_log_utmd.json b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc_mod_init_log_utmd.json
new file mode 100644
index 0000000..cea6b7d
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc_mod_init_log_utmd.json
@@ -0,0 +1,201 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_INIT_LOG",
+ "startGen": "97",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "INIT_LOG_VERSION_CODE_TITLE": {
+ "apiType": "index",
+ "format": "======================= Version code information =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "HW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_SW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "SW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_CODE": {
+ "apiType": "index",
+ "format": "HW_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_SUB_CODE": {
+ "apiType": "index",
+ "format": "HW_SUB_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_MD_BOOT_CHECK": {
+ "apiType": "index",
+ "format": "MD_BOOT_CHECK: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_VERSION_CODE_END": {
+ "apiType": "index",
+ "format": "======================= Version code information end =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "INIT"
+}
\ No newline at end of file
diff --git a/mcu/driver/sys_drv/init/inc/md97/mdmcu_i7200_common_macro.h b/mcu/driver/sys_drv/init/inc/md97/mdmcu_i7200_common_macro.h
new file mode 100644
index 0000000..303f7eb
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/mdmcu_i7200_common_macro.h
@@ -0,0 +1,199 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(GEN_FOR_PC) && !defined(__ASSEMBLER__) && defined(__MTK_TARGET__)\
+ && !defined(__MD97_MDMCU_COMMON_MACRO_H__) && defined(__MIPS_I7200__)
+
+#define __MD97_MDMCU_COMMON_MACRO_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+#ifndef __ASSEMBLER__
+/*******************************************************************************
+ * OS Relative
+ ******************************************************************************/
+#define miu_set_c0_tcschedule2(__throt_cfg__, __grp__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCSCHEDULE); \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_update_reg_bitfd( \
+ MIU_C0_TCSCHEDULE_PRIO, __r, __grp__) \
+ ); \
+ })
+
+#define miu_save_and_set_c0_tcschedule_grp(__grp__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCSCHEDULE); \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_update_reg_bitfd( \
+ MIU_C0_TCSCHEDULE_PRIO, __r, __grp__) \
+ ); \
+ miu_get_reg_bitfd_val(MIU_C0_TCSCHEDULE_PRIO, __r); \
+ })
+
+// WRR2 Throttle Not Supported in I7200
+#define MIU_DEF_NORMAL_DOM_THROT_VAL 0
+#define MIU_DEF_HRT_DOM_THROT_VAL 0
+
+/*******************************************************************************
+ * Register Read/Write
+ ******************************************************************************/
+#define miu_reg(__ADDR__) *(volatile kal_uint32*)(__ADDR__)
+
+#define miu_write_reg(__ADDR__, __VAL__) do { \
+ miu_reg(__ADDR__) = __VAL__; \
+ miu_compiler_barrier(); \
+ } while(0)
+
+#define miu_set_reg(__ADDR__, __VAL__) do { \
+ const kal_uint32 __addr__ = __ADDR__; \
+ miu_write_reg(__addr__, \
+ miu_reg(__addr__) | __VAL__); \
+ } while(0)
+
+#define miu_write_reg_bitfd(__ADDR__, __BITFD__, __VAL__) do { \
+ const kal_uint32 __addr__ = __ADDR__; \
+ const kal_uint32 __val__ = __VAL__; \
+ register kal_uint32 tmp; \
+ tmp = miu_reg(__addr__); \
+ tmp = miu_update_reg_bitfd(__BITFD__, tmp, __val__); \
+ miu_write_reg(__addr__, tmp); \
+ } while(0)
+
+/*******************************************************************************
+ * Special Instructions
+ ******************************************************************************/
+#define miu_count_leading_one(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clo %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_count_leading_zero(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clz %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_yield(yq) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __yqn = (yq); \
+ register miu_reg32_t \
+ __ret; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ ".set mt; \n" \
+ "yield %[ret],%z[yqn]; \n" \
+ ".set pop; \n" \
+ : [ret] "=d" (__ret) \
+ : [yqn] "dJ" (__yqn) \
+ ); \
+ __ret; \
+ })
+
+#define miu_rotr(__x__, __off__) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __res = __x__; \
+ register miu_reg32_t \
+ __off = __off__; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "rotr %0,%1; \n" \
+ ".set pop; \n" \
+ : "=d" (__res) \
+ : "dJ" (__off)); \
+ __res; \
+ })
+
+#define miu_pref(__hint__, __addr__) do { \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ " pref %[hint], 0(%[addr]); \n" \
+ ".set pop; \n" \
+ :: [hint] "i" (__hint__), \
+ [addr] "d" (__addr__) \
+ : \
+ ); \
+ } while(0)
+
+/*******************************************************************************
+ * CP0 Relative
+ ******************************************************************************/
+#define miu_get_and_set_errctl_wst_spr_itc(__wst__, __spr__, __itc__) \
+ __extension__ ({ \
+ register miu_reg32_t __old__; \
+ register miu_reg32_t __new__; \
+ __old__ = miu_mfc0(MIU_C0_ERRCTL); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_WST, __old__, __wst__); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_SPR, __new__, __spr__); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_ITC, __new__, __itc__); \
+ miu_mtc0(MIU_C0_ERRCTL, __new__); \
+ __old__; \
+ })
+
+#define miu_restore_errctl(__newval__) miu_mtc0(MIU_C0_ERRCTL, __newval__);
+
+#define miu_get_binding_vpe_id() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCBIND); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_TCBIND_CURVPE, __r); \
+ })
+
+/*******************************************************************************
+ * C Common
+ ******************************************************************************/
+#define miu_get_current_addr() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push \n" \
+ ".set noreorder \n" \
+ "%=: \n" \
+ " lui %0, %%hi(%=b) \n" \
+ " addiu %0, %%lo(%=b) \n" \
+ ".set pop \n" \
+ : "=d" (__r) :: \
+ ); \
+ __r; \
+ })
+
+// FIXME: not realy safe
+#define miu_array_count_of(x) (sizeof(x)/sizeof(x[0]))
+
+#endif /* __ASSEMBLER__ */
+#endif /* !defined(GEN_FOR_PC) && !defined(__ASSEMBLER__) && defined(__MTK_TARGET__)\
+ && !defined(__MD97_MDMCU_COMMON_MACRO_H__) && defined(__MIPS_I7200__) */
diff --git a/mcu/driver/sys_drv/init/inc/md97/mdmcu_init.h b/mcu/driver/sys_drv/init/inc/md97/mdmcu_init.h
new file mode 100644
index 0000000..f51fc63
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/mdmcu_init.h
@@ -0,0 +1,32 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97__)
+#define __MD97_MDMCU_INIT_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+/* I7200/NanoMIPS common macro */
+#include "md97/mdmcu_i7200_common_macro.h"
+
+#ifndef __ASSEMBLER__
+
+extern void mdmcu_init(void);
+extern void mdmcu_enter_dormant(void);
+extern void mdmcu_leave_dormant(void);
+extern void miu_wait(void);
+
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+
+#endif /* __ASSEMBLER__ */
+#endif /* !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97__) */
diff --git a/mcu/driver/sys_drv/init/inc/md97/sys_stack_config.h b/mcu/driver/sys_drv/init/inc/md97/sys_stack_config.h
new file mode 100644
index 0000000..9842765
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/sys_stack_config.h
@@ -0,0 +1,61 @@
+/*
+ * SYS_STACK_INSTANCE(CORE, VPE, TC, SIZE, SECTION, TYPE)
+ */
+
+#ifndef SYS_STACK_INSTANCE
+# define SYS_STACK_INSTANCE
+#endif
+
+#ifndef SYS_STACK_NAME
+# define SYS_STACK_NAME(CORE, VPE, TC) SYS_Stack_Pool_CORE ## CORE ## _VPE ## VPE ## _TC ## TC
+#endif
+
+#ifndef SYS_STACK_INSTANCE_BEGIN
+# define SYS_STACK_INSTANCE_BEGIN()
+#endif
+
+#ifndef SYS_STACK_INSTANCE_END
+# define SYS_STACK_INSTANCE_END()
+#endif
+
+SYS_STACK_INSTANCE_BEGIN()
+
+SYS_STACK_INSTANCE(0, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(0, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__SINGLE_CORE__)
+SYS_STACK_INSTANCE(1, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(1, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__MD97_IS_2CORES__)
+SYS_STACK_INSTANCE(2, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(2, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+SYS_STACK_INSTANCE(3, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(3, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+SYS_STACK_INSTANCE_END()
+
+#undef SYS_STACK_INSTANCE
+#undef SYS_STACK_NAME
+#undef SYS_STACK_INSTANCE_BEGIN
+#undef SYS_STACK_INSTANCE_END
+
diff --git a/mcu/driver/sys_drv/init/inc/md97p/asm_common_def_gcc.h b/mcu/driver/sys_drv/init/inc/md97p/asm_common_def_gcc.h
new file mode 100644
index 0000000..8cbcfa1
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/asm_common_def_gcc.h
@@ -0,0 +1,46 @@
+
+#ifndef _ASM_COMMON_DEF_GCC_
+#define _ASM_COMMON_DEF_GCC_
+
+
+#define GCC_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+
+#define GCC_ASM_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_ASM_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+.macro declare_stack name, val=0
+ .type \name , %object
+ \name :
+ .ascii "STACKEND"
+ .space \val
+ 1:
+ .size \name , 1b - \name
+.endm
+
+#if 0
+#ifdef __STACK_ALIGN_MPU__
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+#endif
+
+#endif
+
+
diff --git a/mcu/driver/sys_drv/init/inc/md97p/boot_asm.h b/mcu/driver/sys_drv/init/inc/md97p/boot_asm.h
new file mode 100644
index 0000000..48fc0c4
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/boot_asm.h
@@ -0,0 +1,196 @@
+
+#ifndef __BOOT_ASM_H__
+#define __BOOT_ASM_H__
+
+#include <bootarm.h>
+
+/*************************************************************************
+ * Macro definition
+ *************************************************************************/
+#define __LEGACY_NMI_CHECK__ (0x0)
+#if defined(__ESL_MASE_GEN97__)
+#define __MULTI_VPE_EN__ (0x0)
+#else /*__ESL_MASE_GEN97__*/
+#define __MULTI_VPE_EN__ (0x1)
+#endif/*__ESL_MASE_GEN97__*/
+#define MX_FEATURE (0x0)
+
+#if defined(_SIMULATION)
+#define INIT_DEF_VALUE (0x0)
+#else
+#define INIT_DEF_VALUE (0xdeadbeef)
+#endif
+
+#define BOOTTRC_MAGIC_ADDR (INT_bootup_magic)
+
+#define BOOTTRC_VPE0_ADDR (INT_bootup_trace0)
+#define BOOTTRC_VPE1_ADDR (INT_bootup_trace1)
+#define BOOTTRC_VPE2_ADDR (INT_bootup_trace2)
+
+#define BOOTTRC_VPE4_ADDR (INT_bootup_trace4)
+#define BOOTTRC_VPE5_ADDR (INT_bootup_trace5)
+#define BOOTTRC_VPE6_ADDR (INT_bootup_trace6)
+
+#define BOOTTRC_VPE8_ADDR (INT_bootup_trace8)
+#define BOOTTRC_VPE9_ADDR (INT_bootup_trace9)
+#define BOOTTRC_VPE10_ADDR (INT_bootup_trace10)
+
+#define BOOTTRC_VPE12_ADDR (INT_bootup_trace12)
+#define BOOTTRC_VPE13_ADDR (INT_bootup_trace13)
+#define BOOTTRC_VPE14_ADDR (INT_bootup_trace14)
+
+.extern Set_HS1_Boot_Trace
+.extern Boot_Trace_PreInit
+#if !defined(__COSIM_BYPASS_DRV__) && !defined(__ESL_MASE_GEN97__)
+.macro INT_TRC_SAVE_RA trace_id
+ //move $t0, $ra
+ INT_TRC \trace_id
+ //move $ra, $t0
+.endm
+.macro INT_TRC trace_id
+//#if defined(__SP_BOOTTRC_ENABLE__)
+ li $a0, \trace_id
+ la $a2, Set_HS1_Boot_Trace
+ //la $a2, INC_TRC
+ jalrc $a2
+//#endif
+.endm
+.macro INT_TRC_INIT_MAGIC
+ la $a2, Set_HS1_Boot_Trace
+ la $a1, INT_bootup_entry
+ sw $a2, 0x0($a1)
+ la $a2, Boot_Trace_PreInit
+ jalrc $a2
+.endm
+#else
+.macro INT_TRC_SAVE_RA trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC_INIT_MAGIC
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+#endif /* !defined(__COSIM_BYPASS_DRV__) */
+
+.macro INT_GET_CPUID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 4
+.endm
+
+.macro INT_GET_VPEID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 2
+.endm
+
+.macro INT_GET_COREID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 2, 2
+.endm
+
+
+/*************************************************************************
+ * Function definition
+ *************************************************************************/
+
+LEAF(INC_TRC)
+//#if defined(__SP_BOOTTRC_ENABLE__)
+
+ INT_GET_CPUID $a2, r23_cpu_num
+
+INT_init_VPE0_boot_trace:
+ li $a3, 0x0
+ bnec r23_cpu_num, $a3, INT_init_VPE1_boot_trace
+
+ li $a1, INIT_MAGIC
+ la $a2, BOOTTRC_MAGIC_ADDR
+ sw $a1, 0x0($a2)
+ la $a2, BOOTTRC_VPE0_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE1_boot_trace:
+ li $a3, 0x1
+ bnec r23_cpu_num, $a3, INT_init_VPE2_boot_trace
+
+ la $a2, BOOTTRC_VPE1_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE2_boot_trace:
+ li $a3, 0x2
+ bnec r23_cpu_num, $a3, INT_init_VPE4_boot_trace
+
+ la $a2, BOOTTRC_VPE2_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE4_boot_trace:
+ li $a3, 0x4
+ bnec r23_cpu_num, $a3, INT_init_VPE5_boot_trace
+
+ la $a2, BOOTTRC_VPE4_ADDR
+ bc INT_init_boot_trace_done
+
+
+INT_init_VPE5_boot_trace:
+ li $a3, 0x5
+ bnec r23_cpu_num, $a3, INT_init_VPE6_boot_trace
+
+ la $a2, BOOTTRC_VPE5_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE6_boot_trace:
+ li $a3, 0x6
+ bnec r23_cpu_num, $a3, INT_init_VPE8_boot_trace
+
+ la $a2, BOOTTRC_VPE6_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE8_boot_trace:
+ li $a3, 0x8
+ bnec r23_cpu_num, $a3, INT_init_VPE9_boot_trace
+
+ la $a2, BOOTTRC_VPE8_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE9_boot_trace:
+ li $a3, 0x9
+ bnec r23_cpu_num, $a3, INT_init_VPE10_boot_trace
+
+ la $a2, BOOTTRC_VPE9_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE10_boot_trace:
+ li $a3, 0xA
+ bnec r23_cpu_num, $a3, INT_init_VPE12_boot_trace
+
+ la $a2, BOOTTRC_VPE10_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE12_boot_trace:
+ li $a3, 0xC
+ bnec r23_cpu_num, $a3, INT_init_VPE13_boot_trace
+
+ la $a2, BOOTTRC_VPE12_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE13_boot_trace:
+ li $a3, 0xD
+ bnec r23_cpu_num, $a3, INT_init_VPE14_boot_trace
+
+ la $a2, BOOTTRC_VPE13_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE14_boot_trace:
+ la $a2, BOOTTRC_VPE14_ADDR
+
+
+INT_init_boot_trace_done:
+ sw $a0, 0x0($a2)
+ jrc $ra
+
+//#endif
+END(INC_TRC)
+
+
+
+#endif /* __BOOTARM_ASM_H__ */
diff --git a/mcu/driver/sys_drv/init/inc/md97p/idle_service.h b/mcu/driver/sys_drv/init/inc/md97p/idle_service.h
new file mode 100644
index 0000000..6edb0ed
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/idle_service.h
@@ -0,0 +1,276 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_service.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file provides idle service related header.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __IDLE_SERVICE_H__
+#define __IDLE_SERVICE_H__
+
+#include "kal_cpuinfo.h"
+
+#define VPE_NUMBER SYS_MCU_NUM_VPE
+#define CORE_NUMBER SYS_MCU_NUM_CORE
+#define PER_CORE_VPE_NUM 3
+
+#define IRQ_SW_CORE0_VPE0_LEAVE_WAIT IRQ_SW_LISR22_CODE /* IRQ ID 302 */
+#define IRQ_SW_CORE1_VPE0_LEAVE_WAIT IRQ_SW_LISR23_CODE /* IRQ ID 303 */
+#define IRQ_SW_CORE2_VPE0_LEAVE_WAIT IRQ_SW_LISR24_CODE /* IRQ ID 304 */
+#define IRQ_SW_CORE3_VPE0_LEAVE_WAIT IRQ_SW_LISR25_CODE /* IRQ ID 305 */
+
+#define IDLE_SERVICE_STEP_MAX 48
+
+#define IDLE_STATUS_NORMAL 0
+#define IDLE_STATUS_DORMANT 2
+
+#define WHOLE_CORE KAL_TRUE
+#define SINGLE_VPE KAL_FALSE
+
+typedef enum{
+/* Below for step logging */
+ IDLE_HANDLER_USER_IAPMU_CM = 0x1100,
+
+ IDLE_HANDLER_ENTER = 0x0000,
+ IDLE_HANDLER_LEAVE = 0x00FF,
+
+ IDLE_HANDLER_ENTER_DI = 0x02,
+ IDLE_REMOVE_FROM_SCHEDULING = 0x03,
+ IDLE_REMOVE_FROM_SCHEDULING_FAIL = 0x04,
+ IDLE_REMOVE_FROM_SCHEDULING_OK = 0x05,
+ IDLE_CHECK_PENDING_IRQ_FAIL = 0x06,
+ IDLE_CHECK_PENDING_IRQ_OK = 0x07,
+ IDLE_CHECK_SW_LOCK_DONE = 0x08,
+ IDLE_WAIT_CASE = 0x09,
+ IDLE_NOT_SLEEP_TIME = 0x0A,
+ IDLE_CORE_CHECK_SLEEP = 0x0B,
+ IDLE_CORE_CHECK_SLEEP_DONE = 0x0C,
+
+ IDLE_COREx_VPE1_NOT_IN_WAIT = 0x0E,
+ IDLE_DIRECTLY_WAIT = 0x0F,
+
+ IDLE_OSTD_WAIT = 0x10,
+ IDLE_OSTD_WAIT_ENTER = 0x11,
+ IDLE_OSTD_WAIT_LEAVE = 0x12,
+
+ IDLE_OSTD_BUSY = 0x20,
+
+ IDLE_OSTD_DORMANT = 0x30,
+ //IDLE_OSTD_DORMANT_ENTER = 0x31,
+ //IDLE_OSTD_DORMANT_LEAVE = 0x32,
+
+ IDLE_PTP_SLEEP_ENTER = 0x35,
+ IDLE_PTP_SLEEP_LEAVE = 0x36,
+ IDLE_PTP_WAKE_ENTER = 0x37,
+ IDLE_PTP_WAKE_LEAVE = 0x38,
+
+ IDLE_DORMANT_ABORT_LEAVE = 0x40,
+ IDLE_DORMANT_ABORT_WAIT_ENTER = 0x41,
+ IDLE_DORMANT_ABORT_WAIT_LEAVE = 0x42,
+
+ IDLE_DORMANT_RESTORE_LEAVE = 0x45,
+ IDLE_DORMANT_RESTORE_WAIT_ENTER = 0x46,
+ IDLE_DORMANT_RESTORE_WAIT_LEAVE = 0x47,
+
+ IDLE_CSC_HANDLER_ENTER = 0x48,
+ IDLE_CSC_HANDLER_LEAVE = 0x49,
+
+ IDLE_VPE1_VPE2_ENTER_SCHED = 0x50,
+
+ IDLE_WFI_WAIT_ENTER = 0x60,
+ IDLE_WFI_WAIT_LEAVE = 0x61,
+
+ IDLE_OSTD_INVALID_CASE = 0x99,
+/* Above for step logging */
+}IDLE_ACTION_INDEX;
+
+typedef enum{
+// IDLE_EMM_START_PATTERN = 0xEDEC0000 and write by CMM owner
+//IDLE TASK: WFI(=WAIT) ENTER/LEAVE per vpe
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER = 0,
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_LEAVE,
+
+//IDLE TASK: SLEEP ENTER/LEAVE per VPE
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_LEAVE,
+
+// IDLE TASK: step logging
+ IDLE_EMM_VPE0_IDLE_TASK_FMA,
+ IDLE_EMM_VPE0_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE1_IDLE_TASK_FMA,
+ IDLE_EMM_VPE1_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE2_IDLE_TASK_FMA,
+ IDLE_EMM_VPE2_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE3_IDLE_TASK_FMA,
+ IDLE_EMM_VPE3_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE4_IDLE_TASK_FMA,
+ IDLE_EMM_VPE4_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE5_IDLE_TASK_FMA,
+ IDLE_EMM_VPE5_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE6_IDLE_TASK_FMA,
+ IDLE_EMM_VPE6_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE7_IDLE_TASK_FMA,
+ IDLE_EMM_VPE7_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE8_IDLE_TASK_FMA,
+ IDLE_EMM_VPE8_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE9_IDLE_TASK_FMA,
+ IDLE_EMM_VPE9_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE10_IDLE_TASK_FMA,
+ IDLE_EMM_VPE10_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE11_IDLE_TASK_FMA,
+ IDLE_EMM_VPE11_IDLE_TASK_STEPLOGGING,
+
+//IDLE TASK: EPOF end to WFI per CORE
+ IDLE_EMM_Core0_INFINITESLEEP_WFI,
+ IDLE_EMM_Core1_INFINITESLEEP_WFI,
+ IDLE_EMM_Core2_INFINITESLEEP_WFI,
+ IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+ IDLE_EMM_INDEX_MAX = IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+// IDLE_EMM_END_PATTERN = 0xCEDE0000 and write by CMM owner
+
+}IDLE_EMM_LOG_INDEX;
+
+extern void idle_service_step_logging(kal_uint32 vpe_id, IDLE_ACTION_INDEX step, kal_bool Log_To_EMM);
+extern void Idle_Service_Prepare_WAIT(void);
+extern kal_uint32 idle_service_leave_wait_time[VPE_NUMBER];
+#if defined (__MODEM_CCCI_EXIST__)
+extern kal_bool IDLE_EMM_WriteDbgInfo(kal_uint32 index, void* addr);
+#endif
+
+#endif
+
diff --git a/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc.h b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc.h
new file mode 100644
index 0000000..4af3859
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc.h
@@ -0,0 +1,87 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_comm_trc.h
+ *
+ * Project:
+ * --------
+ * Moly_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _INIT_COMM_TRC_H
+#define _INIT_COMM_TRC_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+/*************************************************************************
+ * Define INIT trace information
+ *************************************************************************/
+#if !defined(GEN_FOR_PC)
+#include"init_comm_trc_mod_init_log_utmd.h"
+#endif
+#endif /* _INIT_COMM_TRC_H */
diff --git a/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc_mod_init_log_utmd.json b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc_mod_init_log_utmd.json
new file mode 100755
index 0000000..cea6b7d
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc_mod_init_log_utmd.json
@@ -0,0 +1,201 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_INIT_LOG",
+ "startGen": "97",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "INIT_LOG_VERSION_CODE_TITLE": {
+ "apiType": "index",
+ "format": "======================= Version code information =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "HW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_SW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "SW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_CODE": {
+ "apiType": "index",
+ "format": "HW_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_SUB_CODE": {
+ "apiType": "index",
+ "format": "HW_SUB_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_MD_BOOT_CHECK": {
+ "apiType": "index",
+ "format": "MD_BOOT_CHECK: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_VERSION_CODE_END": {
+ "apiType": "index",
+ "format": "======================= Version code information end =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "INIT"
+}
\ No newline at end of file
diff --git a/mcu/driver/sys_drv/init/inc/md97p/mdmcu_init.h b/mcu/driver/sys_drv/init/inc/md97p/mdmcu_init.h
new file mode 100644
index 0000000..af61bc5
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/mdmcu_init.h
@@ -0,0 +1,32 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97P__)
+#define __MD97_MDMCU_INIT_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+/* I7200/NanoMIPS common macro */
+#include "md97/mdmcu_i7200_common_macro.h"
+
+#ifndef __ASSEMBLER__
+
+extern void mdmcu_init(void);
+extern void mdmcu_enter_dormant(void);
+extern void mdmcu_leave_dormant(void);
+extern void miu_wait(void);
+
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+
+#endif /* __ASSEMBLER__ */
+#endif /* !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97P__) */
diff --git a/mcu/driver/sys_drv/init/inc/md97p/sys_stack_config.h b/mcu/driver/sys_drv/init/inc/md97p/sys_stack_config.h
new file mode 100644
index 0000000..9842765
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/sys_stack_config.h
@@ -0,0 +1,61 @@
+/*
+ * SYS_STACK_INSTANCE(CORE, VPE, TC, SIZE, SECTION, TYPE)
+ */
+
+#ifndef SYS_STACK_INSTANCE
+# define SYS_STACK_INSTANCE
+#endif
+
+#ifndef SYS_STACK_NAME
+# define SYS_STACK_NAME(CORE, VPE, TC) SYS_Stack_Pool_CORE ## CORE ## _VPE ## VPE ## _TC ## TC
+#endif
+
+#ifndef SYS_STACK_INSTANCE_BEGIN
+# define SYS_STACK_INSTANCE_BEGIN()
+#endif
+
+#ifndef SYS_STACK_INSTANCE_END
+# define SYS_STACK_INSTANCE_END()
+#endif
+
+SYS_STACK_INSTANCE_BEGIN()
+
+SYS_STACK_INSTANCE(0, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(0, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__SINGLE_CORE__)
+SYS_STACK_INSTANCE(1, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(1, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__MD97_IS_2CORES__)
+SYS_STACK_INSTANCE(2, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(2, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+SYS_STACK_INSTANCE(3, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(3, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+SYS_STACK_INSTANCE_END()
+
+#undef SYS_STACK_INSTANCE
+#undef SYS_STACK_NAME
+#undef SYS_STACK_INSTANCE_BEGIN
+#undef SYS_STACK_INSTANCE_END
+
diff --git a/mcu/driver/sys_drv/init/inc/mips_ia_utils.h b/mcu/driver/sys_drv/init/inc/mips_ia_utils.h
new file mode 100644
index 0000000..8c335b4
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/mips_ia_utils.h
@@ -0,0 +1,234 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ * Pivate (SS Internal) header for some MIPS utils
+ *****************************************************************************/
+
+#if !defined(__MIPS_IA_UTILS_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__)
+#define __MIPS_IA_UTILS_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#ifndef __ASSEMBLER__
+# include "kal_iram_section_defs.h"
+# include "kal_public_defs.h"
+#endif /* __ASSEMBLER__ */
+
+#if defined(__MIPS_I7200__)
+# if defined(__MD97__)
+# include "md97/mdmcu_init.h"
+# elif defined(__MD97P__)
+# include "md97p/mdmcu_init.h"
+# endif /* __MD97__ */
+
+#elif defined(__MIPS_IA__)
+#define __MIU_STATIC_INLINE__ __attribute__((always_inline)) static inline
+#if defined(__MIPS16__) && defined(__GNUC__)
+# define MIU_M32_FUNC __attribute__((nomips16))
+#else /* defined(__MIPS16__) && defined(__GNUC__) */
+# define MIU_M32_FUNC
+#endif /* defined(__MIPS16__) && defined(__GNUC__) */
+
+#if defined(CONFIG_MIPS_IA_MR2)
+# include "md93/mips_ia_mr2_utils.h"
+#elif defined(CONFIG_MIPS_IA_MR3)
+# include "md95/mips_ia_mr3_utils.h"
+#else /* MR1 (Gen-92) */
+# include "md93/mips_ia_mr1_utils.h"
+#endif /* CONFIG_MIPS_IA_MR2 */
+
+#define miu_c0_tcschedule_throt_val( \
+ __t1_stp__, __t1_grp__, __t1_th__, __t1_qe__, \
+ __t0_stp__, __t0_grp__, __t0_th__, __t0_qe__) \
+ ( \
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_STP, __t1_stp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_GRP, __t1_grp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_TH, __t1_th__ ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_QE, __t1_qe__ ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_STP, __t0_stp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_GRP, __t0_grp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_TH, __t0_th__ ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_QE, __t0_qe__ ) \
+ )
+
+#define miu_c0_tcschedule_val_raw( \
+ __t1_stp__, __t1_grp__, __t1_th__, __t1_qe__, \
+ __t0_stp__, __t0_grp__, __t0_th__, __t0_qe__, \
+ __stp__, __grp__) \
+ ( \
+ miu_c0_tcschedule_throt_val( \
+ __t1_stp__, __t1_grp__, __t1_th__, __t1_qe__, \
+ __t0_stp__, __t0_grp__, __t0_th__, __t0_qe__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_STP, __stp__, ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_GRP, __grp__, ) \
+ )
+
+#define miu_c0_tcschedule_val3( \
+ __throt_cfg__, __stp__, __grp__) \
+ ( \
+ __throt_cfg__ |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_STP, __stp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_GRP, __grp__) \
+ )
+
+#define miu_c0_tcschedule_val2(__throt_cfg__, __grp__) \
+ miu_c0_tcschedule_val3(__throt_cfg__, 0, __grp__)
+
+#define miu_set_c0_tcschedule2(__throt_cfg__, __grp__) \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_c0_tcschedule_val2(__throt_cfg__, __grp__))
+
+#define miu_save_and_set_c0_tcschedule_grp(__grp__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCSCHEDULE); \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_update_reg_bitfd( \
+ MIU_C0_TCSCHEDULE_GRP, __r, __grp__) \
+ ); \
+ miu_get_reg_bitfd_val(MIU_C0_TCSCHEDULE_GRP, __r); \
+ })
+
+// TODO: assume Gen-92/Gen-93 use the same setting
+#define MIU_DEF_NORMAL_DOM_THROT_VAL \
+ miu_c0_tcschedule_throt_val( \
+ 1, 0, 1, MIU_C0_TCSCHEDULE_QE_LDQ, \
+ 1, 0, 1, MIU_C0_TCSCHEDULE_QE_WBB \
+ )
+
+#define MIU_DEF_HRT_DOM_THROT_VAL \
+ miu_c0_tcschedule_throt_val( \
+ 0, 0, 0, MIU_C0_TCSCHEDULE_QE_NOT, \
+ 0, 0, 0, MIU_C0_TCSCHEDULE_QE_NOT \
+ )
+
+#ifndef __ASSEMBLER__
+#define miu_count_leading_one(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clo %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_count_leading_zero(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clz %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_yield(yq) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __yqn = (yq); \
+ register miu_reg32_t \
+ __ret; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ ".set mt; \n" \
+ "yield %[ret],%z[yqn]; \n" \
+ ".set pop; \n" \
+ : [ret] "=d" (__ret) \
+ : [yqn] "dJ" (__yqn) \
+ ); \
+ __ret; \
+ })
+
+#define miu_rotr(__x__, __off__) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __res = __x__; \
+ register miu_reg32_t \
+ __off = __off__; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "rotr %0,%1; \n" \
+ ".set pop; \n" \
+ : "=d" (__res) \
+ : "dJ" (__off)); \
+ __res; \
+ })
+
+#define miu_pref(__hint__, __addr__) do { \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ " pref %[hint], 0(%[addr]); \n" \
+ ".set pop; \n" \
+ :: [hint] "i" (__hint__), \
+ [addr] "d" (__addr__) \
+ : \
+ ); \
+ } while(0)
+
+#define miu_get_and_set_errctl_wst_spr_itc(__wst__, __spr__, __itc__) \
+ __extension__ ({ \
+ register miu_reg32_t __old__; \
+ register miu_reg32_t __new__; \
+ __old__ = miu_mfc0(MIU_C0_ERRCTL); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_WST, __old__, __wst__);\
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_SPR, __new__, __spr__);\
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_ITC, __new__, __itc__);\
+ miu_mtc0(MIU_C0_ERRCTL, __new__); \
+ __old__; \
+ })
+
+#define miu_restore_errctl(__newval__) miu_mtc0(MIU_C0_ERRCTL, __newval__);
+
+// FIXME: not realy safe
+#define miu_array_count_of(x) (sizeof(x)/sizeof(x[0]))
+
+#define miu_get_binding_vpe_id() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCBIND); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_TCBIND_CURVPE, __r); \
+ })
+
+#ifdef CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS
+MIU_M32_FUNC extern
+void mips_ia_mr12_cross_config_vpe_rps(const unsigned int disable);
+# define miu_vpe1_cross_config_vpe0_rps(__disable__) \
+ mips_ia_mr12_cross_config_vpe_rps(__disable__)
+#else
+# define miu_vpe1_cross_config_vpe0_rps(__disable__) do {} while(0)
+#endif /* CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS */
+
+extern void mips_ia_misc_enter_dormant(void);
+extern void mips_ia_misc_leave_dormant(void);
+MIU_M32_FUNC extern void miu_wait(void);
+extern const kal_int32 mips_ia_lv3_dcm_enable(const kal_uint32 en);
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+#endif /* __ASSEMBLER__ */
+#else /* __MIPS_IA__ */
+# error "unknow mdmcu"
+#endif /* __MIPS_IA__ */
+
+#endif /* !defined(__MIPS_IA_UTILS_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) */
diff --git a/mcu/driver/sys_drv/init/src/md97/bootarm_gcc.S b/mcu/driver/sys_drv/init/src/md97/bootarm_gcc.S
new file mode 100644
index 0000000..b359381
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/bootarm_gcc.S
@@ -0,0 +1,1320 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bootarm_gcc.S
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the boot sequence of asm level.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+/*************************************************************************/
+/* */
+/* Copyright (c) 1994 -2000 Accelerated Technology, Inc. */
+/* */
+/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
+/* subject matter of this material. All manufacturing, reproduction, */
+/* use, and sales rights pertaining to this subject matter are governed */
+/* by the license agreement. The recipient of this software implicitly */
+/* accepts the terms of the license. */
+/* */
+/*************************************************************************/
+
+/*************************************************************************/
+/* */
+/* FILE NAME VERSION */
+/* */
+/* bootarm_gcc.s MIPS interAptiv */
+/* */
+/* COMPONENT */
+/* */
+/* IN - Initialization */
+/* */
+/* DESCRIPTION */
+/* */
+/* This file contains the target processor dependent initialization */
+/* routines and data. */
+/* */
+/* */
+/* DATA STRUCTURES */
+/* */
+/* INT_Vectors Interrupt vector table */
+/* */
+/* FUNCTIONS */
+/* */
+/* INT_Initialize Target initialization */
+/* */
+/* */
+/*************************************************************************/
+#include <boot.h>
+#include <boot_comm.h>
+#include <mips/m32c0.h>
+#include <cps.h>
+#include <mips/mt.h>
+#include <bootarm.h>
+#include <rstctl_reg.h>
+#include <MD_TOPSM_private.h>
+#include <drv_pcmon_init.h>
+#include <drv_busmon.h>
+#include <reg_base.h>
+#include <sst_temp_ex_handlers.h>
+#include <boot_asm.h>
+#include <cpu_info.h>
+#if defined(__ESL_SPEEDUP__)
+#include <esl_asm_macro.h>
+#endif
+
+.extern Set_VPE_Domain_Type
+
+.text
+STACKEND:
+ .ascii "STACKEND"
+.size STACKEND,.-STACKEND
+
+
+.section "NONCACHEDZI"
+INT_init_region_sync:
+ .word 0x0
+.size INT_init_region_sync,.-INT_init_region_sync
+
+// Total 8 VPEs each has 2 words for saving ra, sp
+ABN_RST_POOL:
+ .space 0x80
+.size ABN_RST_POOL,.-ABN_RST_POOL
+
+#if defined(UMOLYE_COSIM)
+core_sync_flag:
+ .word 0
+.size core_sync_flag,.-core_sync_flag
+#endif
+
+.section "MCURW_HWRO_DNC_NOINIT"
+INT_bootup_magic:
+ .word 0x0
+.size INT_bootup_magic,.-INT_bootup_magic
+
+INT_bootup_trace0:
+ .word 0x0
+.size INT_bootup_trace0,.-INT_bootup_trace0
+
+INT_bootup_trace1:
+ .word 0x0
+.size INT_bootup_trace1,.-INT_bootup_trace1
+
+INT_bootup_trace2:
+ .word 0x0
+.size INT_bootup_trace2,.-INT_bootup_trace2
+
+INT_bootup_trace4:
+ .word 0x0
+.size INT_bootup_trace4,.-INT_bootup_trace4
+
+INT_bootup_trace5:
+ .word 0x0
+.size INT_bootup_trace5,.-INT_bootup_trace5
+
+INT_bootup_trace6:
+ .word 0x0
+.size INT_bootup_trace6,.-INT_bootup_trace6
+
+INT_bootup_trace8:
+ .word 0x0
+.size INT_bootup_trace8,.-INT_bootup_trace8
+
+INT_bootup_trace9:
+ .word 0x0
+.size INT_bootup_trace9,.-INT_bootup_trace9
+
+INT_bootup_trace10:
+ .word 0x0
+.size INT_bootup_trace10,.-INT_bootup_trace10
+
+INT_bootup_trace12:
+ .word 0x0
+.size INT_bootup_trace12,.-INT_bootup_trace12
+
+INT_bootup_trace13:
+ .word 0x0
+.size INT_bootup_trace13,.-INT_bootup_trace13
+
+INT_bootup_trace14:
+ .word 0x0
+.size INT_bootup_trace14,.-INT_bootup_trace14
+
+INT_bootup_trace16:
+ .word 0x0
+.size INT_bootup_trace16,.-INT_bootup_trace16
+
+INT_bootup_trace17:
+ .word 0x0
+.size INT_bootup_trace17,.-INT_bootup_trace17
+
+INT_bootup_trace18:
+ .word 0x0
+.size INT_bootup_trace18,.-INT_bootup_trace18
+
+
+.set noreorder // Don't allow the assembler to reorder instructions.
+.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+
+/**************************************************************************************
+ * R E S E T E X C E P T I O N H A N D L E R
+ * Note: Run at VA: Bank0
+ **************************************************************************************/
+.section "INT_VECTOR_CODE", "ax"
+.globl INT_Vectors
+.ent INT_Vectors
+INT_Vectors:
+#if defined(UMOLYE_COSIM)
+ /* Only Core1 VPE0 would trap here in Cosim load */
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 0, 4
+ li $a1, 2
+ bnec $a0, $a1, core_sync_done
+ la $a0, core_sync_flag
+core_sync:
+ lw $a1, 0($a0)
+ beqzc $a1, core_sync
+core_sync_done:
+#endif
+
+#if (__LEGACY_NMI_CHECK__ == 1)
+ /*
+ * Every Core's VPEs Check if an NMI than jumps to NMI handler
+ */
+ mfc0 $a0, C0_STATUS
+ srl $a0, 19
+ andi $a0, $a0, 1
+ beqzc $a0, INT_NMICheck_done
+ la $a1, NMI_handler
+ jrc $a1
+INT_NMICheck_done:
+#endif
+ la $a2, INT_Initialize_Phase1
+ jrc $a2
+.size INT_Vectors,.-INT_Vectors
+.end INT_Vectors
+
+/*********************************************************************
+ * [Phase1] first NC function, Jumps here from BankA(temp booting bank)
+ * Note: only could invoke NC function
+ *********************************************************************/
+.section "NONCACHED_ROCODE", "ax"
+.globl INT_Initialize_Phase1
+.ent INT_Initialize_Phase1
+INT_Initialize_Phase1:
+ /*
+ * Only Core0 VPE0 do CM2 routing APB access configuration for boot-up trace and kick dog
+ * Note: Do not corrupt sp, ra
+ */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_CM2_route_MO_done
+
+ // Set region attribute in order to write VA: BankA/B to MO port
+ li $a2, GCR_CONFIG_ADDR
+ lui $a0, 0xA000 //set CM2 Region 0 BASE = 0xA000
+ sw $a0, GCR_REG0_BASE($a2)
+ lui $a0, 0xE000 //set CM2 Region Mask = 0xE000
+ li $a3, 0x1 //set CM2_TARGET to IOCU0
+ ins $a0, $a3, 1, 1
+ sw $a0, GCR_REG0_MASK($a2) //Mask=0xE000, target IOCU0
+ // Set region attribute in order to write VA: BankC/D/E/F to MO port
+ lui $a0, 0xC000 //set CM2 Region 1 BASE = 0xC000
+ sw $a0, GCR_REG1_BASE($a2)
+ lui $a0, 0xC000 //set CM2 Region Mask = 0xC000
+ li $a3, 0x1 //set CM2_TARGET to IOCU0
+ ins $a0, $a3, 1, 1
+ sw $a0, GCR_REG1_MASK($a2) //Mask=0xC000, target IOCU0
+
+#if defined(__ESL_SPEEDUP__)
+ ESL_BACKUP_AND_CLR_EMI_CFG
+#endif
+
+ // Can read from FMA
+ li $a2, GCR_CONFIG_ADDR
+ li $a1, GCR_CUSTOM_ADDR
+ li $a3, 0x1
+ ins $a1, $a3, 0, 1
+ sw $a1, 0x60($a2)
+ sync 0x3
+
+INT_CM2_route_MO_done:
+
+#if !defined(__COSIM_BYPASS_DRV__)
+ /*
+ * Every Core's VPEs backup ra and sp to ABN_RST_POOL for abnormal-reset scenario
+ * Note: 1. Can not call any function which will use ra register or backup it
+ * 2. Backup ra to $t0 if the boot-up trace is logged
+ */
+ la $a0, ABN_RST_POOL
+
+ INT_GET_CPUID $a1, $a2
+ li $a1, 0x8
+ mul $a3, $a1, $a2
+ addu $a0, $a0, $a3
+ sw $ra, 0x0($a0)
+ sw $sp, 0x4($a0)
+#endif
+
+INT_P1_temp_stack_init:
+ /*
+ * Every Core's VPEs initial temp sp for INT_Initialize_Phase1
+ * Note: 1. Every Core use different configuration
+ * 2. Why coding style so foolish? In init flow, simple is the first priority
+ * 3. [Tricky] per-Core VPE0 and VPE1 take the same sp, no concurrency because init_vpe1
+ */
+ INT_GET_COREID $a1, $a0
+
+ addiu $a0, $a0, 1
+ li $a1, BOOT_SYS_STACK_SIZE
+ mul $a1, $a1, $a0
+
+ la $a0, BOOT_SYS_Stack_Pool
+ add $a0, $a0, $a1
+
+ move $sp, $a0
+ li $a0, -16
+ add $sp, $sp ,$a0 //reserve 16 bytes for caller save
+
+INT_P1_temp_stack_init_done:
+
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_HW_PreConfig_done
+ INT_TRC_INIT_MAGIC
+ //PDAMON Mask SPRAM DECERR
+ INT_TRC_SAVE_RA LABEL_PREINIT_PDAMON
+ PDAMON_CONFIG
+ // Busmon switch to MO port
+ INT_TRC_SAVE_RA LABEL_PREINIT_BUSMON
+ BUSMON_PRE_CONFIG
+ // Enable FRC
+ INT_TRC_SAVE_RA LABEL_PREINIT_FRC
+ ENABLE_FRC
+
+ INT_TRC_SAVE_RA LABEL_START_P1
+INT_HW_PreConfig_done:
+
+ mfc0 $a0, C0_CONFIG7
+ lui $a1, 0x0020
+ addiu $a1, 0x0800
+ or $a0, $a0, $a1
+ mtc0 $a0, C0_CONFIG7
+ ehb
+INT_disable_ramslp_busslp_done:
+ /*
+ * Every Core's VPEs kick the WDT in order to avoid the unexpected WDT reset when booting
+ * Note: Kick per-VPE WDT and backup ra to $t0 if the boot-up trace is logged
+ */
+
+ INT_TRC_SAVE_RA LABEL_RESTART_WDT
+ la $a0, g_WATCHDOG_RESTART_REG
+ lw $a0, 0x0($a0)
+ li $a1, RSTCTL_WDTRR_KEY
+ li $a2, RSTCTL_WDTRR_WDT_RESTART
+ addu $a1, $a1, $a2
+ sw $a1, 0x0($a0)
+ sync 0x7
+
+INT_kick_wdt_done:
+ /*
+ * Every Core's VPEs do GPR initialize
+ * Note: 1. Solve RTL Cosim unknown value problem
+ * 2. Reset beginning values and for easy debug
+ */
+ li $at, INIT_DEF_VALUE
+ li $t4, INIT_DEF_VALUE
+ li $t5, INIT_DEF_VALUE
+ li $a0, INIT_DEF_VALUE
+ li $a1, INIT_DEF_VALUE
+ li $a2, INIT_DEF_VALUE
+ li $a3, INIT_DEF_VALUE
+ li $a4, INIT_DEF_VALUE
+ li $a5, INIT_DEF_VALUE
+ li $a6, INIT_DEF_VALUE
+ li $a7, INIT_DEF_VALUE
+ li $t0, INIT_DEF_VALUE
+ li $t1, INIT_DEF_VALUE
+ li $t2, INIT_DEF_VALUE
+ li $t3, INIT_DEF_VALUE
+ li $s0, INIT_DEF_VALUE
+ li $s1, INIT_DEF_VALUE
+ li $s2, INIT_DEF_VALUE
+ li $s3, INIT_DEF_VALUE
+ li $s4, INIT_DEF_VALUE
+ li $s5, INIT_DEF_VALUE
+ li $s6, INIT_DEF_VALUE
+ li $s7, INIT_DEF_VALUE
+ li $t8, INIT_DEF_VALUE
+ li $t9, INIT_DEF_VALUE
+ li $k0, INIT_DEF_VALUE
+ li $k1, INIT_DEF_VALUE
+ li $gp, INIT_DEF_VALUE
+ //li $sp, INIT_DEF_VALUE
+ li $fp, INIT_DEF_VALUE
+ li $ra, INIT_DEF_VALUE
+
+ /* Only Core0 VPE0 initialize NC Sync variables in Booting */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_init_sync_var_done
+
+ la $a0, INT_init_region_sync
+ sw $zero, 0x0($a0)
+INT_init_sync_var_done:
+
+ /* reset exception sp array because it is used in exception vector to know if we are in boot or dormant flow */
+ INT_TRC LABEL_RESET_EXC_SP_ARRAY
+ RESET_EXCEPTION_SP_ARRAY
+
+ /*********************************************************************
+ * Every Core's VPEs config C0_EBASE as temporary exception vector for duration
+ * between switch BEV to normal exception ready
+ *
+ * Every Core's VPEs set C0_CONFIG5 CV[29] and K[30] bits to switch
+ * exception vectors to use C0_EBASE if C0_STATUS.BEV[22] were cleared
+ * Note: Most of exceptions before this will go to
+ * "2'b10||SI_ExceptionBase[31:12]||0x380"
+ *********************************************************************/
+
+ INT_TRC LABEL_SET_C0_COFIG5_K
+ INSTALL_TEMP_EXCEPTION_VECTOR
+
+
+ /*********************************************************************
+ * Every Core's VPEs initialize C0_STATUS, clear ERL[2] and BEV[22]
+ * Note: 1. Most of exceptions before this will go to
+ * "SI_ExceptionBase[31:12]||0x380"
+ * 2. Most of exceptions after this will go to INT_BOOT_<X>_vector, i.e.,
+ * "C0_EBASE[31:12]||0x180"
+ *********************************************************************/
+ INT_TRC LABEL_CLR_C0_STATUS_BEV_ERL
+ li $a1, 0x0
+#if (MX_FEATURE == 0x1)
+ li $a0, 0x1
+ ins $a1, $a0, 24, 1 // set C0_STATUS.MX[24]
+#endif
+ mtc0 $a1, C0_STATUS // write C0_STATUS
+ ehb
+
+INT_Domain_Type_PreInit:
+ la $a2, Set_VPE_Domain_Type
+ jalrc $a2
+
+INT_Interrupt_PreInit:
+ INT_TRC LABEL_INTERRUPT_PREINIT
+ /* Every Core's VPEs write variables for enabling/disabling interrupt API */
+
+ la $a2, interrupt_preinit
+ jalrc $a2
+
+
+INT_CM_L2_init:
+ /* Only Core0 VPE0 do set CM2 GCR_BASE to L2 NC */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_CM_L2_init_done
+
+ INT_TRC LABEL_CM_L2_INIT
+ la $a2, disable_L2_init_stage
+ jalrc $a2
+
+ /* Initialize CM region attr. registers for routing PA: BankA/B/C/D/E/F to MO port */
+ INT_TRC LABEL_CM_INIT
+ la $a2, init_cm
+ jalrc $a2
+INT_CM_L2_init_done:
+
+INT_PLL_init:
+
+ /* Only Core0 VPE0 would set PLL for target load temporarily */
+ INT_TRC LABEL_PLL_INIT
+ /* PLL init */
+
+ la $a2, INT_SetPLL
+ jalrc $a2
+
+
+INT_L1_cache_init:
+ /* Every Core's VPE0 do L1$ initialization */
+ INT_GET_VPEID $a2, $a0
+ bnezc $a0, INT_L1_cache_init_done
+
+ INT_TRC LABEL_L1_CACHE_INIT
+ la $a2, l1_cache_init //init L1 cache & global variables
+ jalrc $a2
+INT_L1_cache_init_done:
+
+INT_L2_cache_init:
+ /* Only Core0 VPE0 do L2$ initialization */
+ INT_GET_CPUID $a0, $a0
+#if !defined(__SINGLE_CORE__)
+ bnezc $a0, INT_untrap_Core123_done
+#else
+ bnezc $a0, INT_join_CH_domain_sync_done
+#endif
+
+INT_init_L2:
+ INT_TRC LABEL_L2_CACHE_INIT
+ la $a2, init_L23
+ jalrc $a2
+
+INT_enable_L2:
+ la $a2, enable_L23
+ jalrc $a2
+
+ /* Set CM2 GCR WT CCA override */
+INT_enable_WT:
+ INT_TRC LABEL_SET_CM_WT
+ la $a2, init_cm_wt
+ jalrc $a2
+
+#if !defined(__SINGLE_CORE__)
+INT_init_other_Cores:
+ INT_TRC LABEL_INIT_OTHER_CORES
+ la $a2, init_otherCores
+ jalrc $a2
+
+INT_untrap_Core123:
+#if defined(__ESL_ENABLE__)||defined(__ESL_MASE__)
+ la $a2, release_mp // Release other cores to execute this boot code.
+ jalrc $a2
+#else /* else of defined(__ESL_ENABLE__) */
+ /* Only Core0 VPE0 do Core1~3 Boot-Slaves setup */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_untrap_Core123_done
+#if defined(UMOLYE_COSIM)
+ la $a0, core_sync_flag
+ li $a1, 1
+ sw $a1, 0($a0)
+#endif
+
+ INT_TRC LABEL_SET_BOOTSLAVE
+ /* Configure Core1 Boot-Slaves jump address */
+ // AP trigger, should use option
+ li $a0, BASE_MADDR_MDPERI_MDCFGCTL
+ li $a1, 0x1
+ sw $a1, 0x24($a0)
+
+ li $a0, 0x1
+ la $a1, INT_Vectors
+ la $a2, INT_Set_BootSlave
+ jalrc $a2
+#if !defined(__MD97_IS_2CORES__)
+ li $a0, 0x2
+ la $a1, INT_Vectors
+ la $a2, INT_Set_BootSlave
+ jalrc $a2
+
+ li $a0, 0x3
+ la $a1, INT_Vectors
+ la $a2, INT_Set_BootSlave
+ jalrc $a2
+#endif /*(__MD97_IS_2CORES__)*/
+
+#endif
+INT_untrap_Core123_done:
+
+INT_join_CH_domain:
+ /* Every Core's VPE0 join coherence domain */
+ INT_GET_VPEID $a2, $a0
+ bnezc $a0, INT_join_CH_domain_sync_done
+
+ INT_TRC LABEL_JOIN_CH_DOMAIN
+//Only core0 vpe0 set this bit, GCR control register offset 0x10,bit 3
+ INT_GET_CPUID $a2, $a0
+ bnezc $a0, set_shst_en_done
+ li $t2, GCR_CONFIG_ADDR
+ lw $t1, 0x10($t2)
+ ori $t1, 0x8
+ sw $t1, 0x10($t2)
+set_shst_en_done:
+
+ la $a2, join_domain
+ jalrc $a2
+
+#endif /* !defined(__SINGLE_CORE__) */
+
+#if defined(__SINGLE_CORE__)
+INT_join_domain_with_only_IOCU:
+ li $a2, (GCR_CONFIG_ADDR | CORE_LOCAL_CONTROL_BLOCK | GCR_CL_COHERENCE)
+ li $a0, 0x11
+ sw $a0, 0x0($a2)
+ ehb
+#endif /* __SINGLE_CORE__ */
+
+INT_join_CH_domain_sync_done:
+
+ /*
+ * Every Core's VPEs do INT_SystemReset_Checkfor abnormal reset scenario:
+ * Note: This function would use sp, thus put it after Phase1 temp stack init
+ *
+ */
+ INT_TRC LABEL_ABN_RST_CHECK
+ la $a0, ABN_RST_POOL
+
+ INT_GET_CPUID $a1, $a2
+ li $a1, 0x8
+ mul $a3, $a1, $a2
+ addu $a0, $a0, $a3
+ lw $a0, 0x0($a0)
+
+ la $a2, INT_SystemReset_Check
+ jalrc $a2
+
+
+INT_init_MPU:
+ /* Every Core's VPE0 do MPU init */
+
+ INT_TRC LABEL_SETUP_CDMMBASE
+ INT_GET_VPEID $a1, $a0
+ bnezc $a0, INT_init_VAS_done
+
+ // Enable C0_CDMMBASE
+ move $a1, $zero
+ li $a0, GCR_CDMM_ADDR
+ ext $a1, $a0, 15, 17
+ sll $a1, $a1, 11
+ ori $a1, $a1, (1<<10)
+
+ mtc0 $a1, C0_CDMMBASE
+ ehb
+
+ INT_TRC LABEL_MPU_INIT
+ /* <TODO> MPU configuration!! */
+ la $a2, MPU_Init
+ jalrc.hb $a2
+
+INT_init_VAS_done:
+ la $a2, INT_Initialize_Phase2
+ jalrc.hb $a2
+
+.size INT_Initialize_Phase1,.-INT_Initialize_Phase1
+.end INT_Initialize_Phase1
+
+/*********************************************************************
+ * [Phase2] C function @ VA: Bank9, Jumps here from VA: Bank0
+ * Note: 1. CFG0-4, per-VPE MMU are ready
+ * 2. CFG5 will be ready later
+ *********************************************************************/
+//.text
+.section "NONCACHED_ROCODE", "ax"
+.globl INT_Initialize_Phase2
+.ent INT_Initialize_Phase2
+INT_Initialize_Phase2:
+ INT_TRC LABEL_START_P2
+
+INT_P2_temp_stack_init:
+ /*
+ * Every Core's VPEs initialize temp sp for INT_Initialize_Phase2
+ * Note: 1. Every Core use different configuration
+ * 2. VA: Bank6 now is cacheable
+ * 3. [Tricky] per-Core VPE0 and VPE1 take the same sp, no concurrency because init_vpe1
+ */
+ INT_GET_COREID $a1, $a0
+
+ addiu $a0, $a0, 1
+ li $a1, BOOT_SYS_STACK_SIZE
+ mul $a1, $a1, $a0
+
+ la $a0, BOOT_SYS_Stack_Pool
+ add $a0, $a0, $a1
+#if !defined(__TCM_ONLY_LOAD__)
+ li $a1, TEMP_CACHE_BOOTSTACK_BANK
+ ins $a0, $a1, 28, 4
+#endif
+ move $sp, $a0
+ li $a0, -16
+ add $sp, $sp, $a0 // reserve 16 bytes for caller save
+INT_P2_temp_stack_init_done:
+
+INT_init_regions:
+ /* Core0 VPE0 must do region init before other Core's VPE0 */
+
+ INT_GET_VPEID $a2, $a0
+ bnezc $a0, INT_init_regions_done
+
+ INT_GET_COREID $a2, $a0
+ bnezc $a0, INT_init_regions_core_others
+
+ INT_TRC LABEL_REGION_INIT
+ la $a2, INT_InitRegions_C
+ jalrc $a2
+
+ la $a0, INT_init_region_sync
+ li $a1, 0x1
+ sw $a1, 0x0($a0)
+ sync 0x3
+ bc INT_init_regions_done
+
+INT_init_regions_core_others:
+
+ /* Otehr Core's VPE0 wait until Core0 VPE0 done and then do region init */
+ la $a0, INT_init_region_sync
+ lw $a0, 0x0($a0)
+ beqzc $a0, INT_init_regions_core_others
+
+ INT_TRC LABEL_REGION_INIT
+ la $a2, INT_InitRegions_C
+ jalrc $a2
+
+INT_init_regions_done:
+ INT_TRC LABEL_REGION_INIT_DONE
+
+ /*
+ * Only Core0 VPE0 initialize global cache variables again,
+ * because they are cleaned after region init
+ */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_cache_var_init_done
+
+ la $a2, l1_cache_init_var
+ jalrc $a2
+
+ la $a2, l2_cache_init_var
+ jalrc $a2
+
+INT_cache_var_init_done:
+
+/*********************************************************************
+ * Config C0_EBASE to redirect exception to general_exception_handler
+ * Note: 1. Most of exceptions after this will go to general_ex_vector @ ex_hdlr_gcc.S, i.e.,
+ * "C0_EBASE[31:12]||0x180"
+ * 2. Most of exceptions before this will go to INT_BOOT_<X>_vector, i.e.,
+ * "C0_EBASE[31:12]||0x180"
+ *********************************************************************/
+INT_ebase_set:
+ INT_TRC LABEL_SET_C0_EBASE
+ la $a0, interrupt_vector // Get Exception Address
+ ins $a0, $zero, 0, 12 // zero write-as-zero fields
+ ori $a0, $a0, EBASE_WG // Set WG (bit 11) to make C0_EBASE[31:30] writeable
+ mtc0 $a0, C0_EBASE
+ ehb
+
+INT_init_sp:
+ /* Every Core's VPEs do initialize its sp */
+ INT_TRC LABEL_STACK_INIT
+
+ INT_GET_CPUID $a0, $a0
+ li $a1, 0x0
+ beqc $a0, $a1,CPU0_VPE0_STACK_INIT
+
+ li $a1, 0x1
+ beqc $a0, $a1,CPU0_VPE1_STACK_INIT
+
+ li $a1, 0x2
+ beqc $a0, $a1,CPU0_VPE2_STACK_INIT
+
+#if !defined(__SINGLE_CORE__)
+ li $a1, 0x4
+ beqc $a0, $a1,CPU1_VPE0_STACK_INIT
+
+ li $a1, 0x5
+ beqc $a0, $a1,CPU1_VPE1_STACK_INIT
+
+ li $a1, 0x6
+ beqc $a0, $a1,CPU1_VPE2_STACK_INIT
+#if !defined(__MD97_IS_2CORES__)
+ li $a1, 0x8
+ beqc $a0, $a1,CPU2_VPE0_STACK_INIT
+
+ li $a1, 0x9
+ beqc $a0, $a1,CPU2_VPE1_STACK_INIT
+
+ li $a1, 0xA
+ beqc $a0, $a1,CPU2_VPE2_STACK_INIT
+
+ li $a1, 0xC
+ beqc $a0, $a1,CPU3_VPE0_STACK_INIT
+
+ li $a1, 0xD
+ beqc $a0, $a1,CPU3_VPE1_STACK_INIT
+
+ li $a1, 0xE
+ beqc $a0, $a1,CPU3_VPE2_STACK_INIT
+#endif/*(__MD97_IS_2CORES__)*/
+
+#endif
+CPU0_VPE0_STACK_INIT:
+ la $sp, CORE0_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU0_VPE1_STACK_INIT:
+ la $sp, CORE0_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU0_VPE2_STACK_INIT:
+ la $sp, CORE0_VPE2_TC4_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_Stack_init_la_done
+
+CPU1_VPE0_STACK_INIT:
+ la $sp, CORE1_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU1_VPE1_STACK_INIT:
+ la $sp, CORE1_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU1_VPE2_STACK_INIT:
+ la $sp, CORE1_VPE2_TC4_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+#if !defined(__MD97_IS_2CORES__)
+CPU2_VPE0_STACK_INIT:
+ la $sp, CORE2_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU2_VPE1_STACK_INIT:
+ la $sp, CORE2_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU2_VPE2_STACK_INIT:
+ la $sp, CORE2_VPE2_TC4_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU3_VPE0_STACK_INIT:
+ la $sp, CORE3_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU3_VPE1_STACK_INIT:
+ la $sp, CORE3_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU3_VPE2_STACK_INIT:
+ la $sp, CORE3_VPE2_TC4_SYS_STACK_PTR
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+INT_Stack_init_la_done:
+ lw $sp, 0x0($sp)
+ //li $a0, -16
+ //add $sp, $sp, $a0 //reserve 16 bytes for caller save
+ li $a0, 0xFFFFFFF0
+ and $sp, $sp, $a0
+INT_init_sp_done:
+
+INT_init_sp_guard_pattern:
+ /* Every Core's VPE0 set guard pattern to its sys stack */
+ INT_GET_VPEID $a0, $a1
+ bnezc $a1, INT_init_sp_guard_done
+
+ ext $a0, $a0, 2, 2
+ la $a1, INT_SetSysStack_GuardPattern
+ jalrc $a1
+
+
+INT_init_sp_guard_done:
+
+INT_init_vpe1_next:
+ /* Every Core's VPE0 do init_vpe1 to enable VPE1 */
+
+#if (__MULTI_VPE_EN__ != 0)
+ INT_TRC LABEL_INIT_VPE1
+
+ INT_GET_VPEID $a2, $a0
+ /*vpe1 do init_vpe2*/
+ li $a1, 0x1
+ beqc $a0, $a1, INT_init_vpe2
+ nop
+ /*vpe0 do init_vpe1 and init vpe2*/
+ bnezc $a0, INT_init_vpe1_done
+
+ la $a2, init_vpe0
+ jalrc $a2
+
+ la $a2, init_vpe1 // Set up MT ASE vpe1 to execute this boot code also.
+ jalrc $a2
+ bc INT_init_vpe1_done
+
+INT_init_vpe2:
+ la $a2, init_vpe2 // Set up MT ASE vpe2 to execute this boot code also.
+ jalrc $a2
+
+#endif
+
+INT_init_vpe1_done:
+
+INT_init_done:
+ la $ra, all_done // If main return then go to all_done:.
+
+INT_cpu_init_done:
+
+ li $a0, 0xA5A55A5A
+ la $a2, INT_init_stage
+ sw $a0, 0x0($a2)
+
+ INT_TRC LABEL_INIT_ASM_DONE
+#if defined(KTEST_RTOS_TEST)
+ la $a2, KTEST_Initialize // Let KTEST setup OS
+#else
+ la $a2, kal_system_init
+#endif
+ jalrc $a2
+
+all_done:
+ // Looks like main returned. Just busy wait spin.
+ bc all_done
+
+.size INT_Initialize_Phase2,.-INT_Initialize_Phase2
+.end INT_Initialize_Phase2
+
diff --git a/mcu/driver/sys_drv/init/src/md97/idle_service.c b/mcu/driver/sys_drv/init/src/md97/idle_service.c
new file mode 100644
index 0000000..9ae6f9a
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/idle_service.c
@@ -0,0 +1,1680 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_service.c
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file provides idle task flow related APIs to enter dormant.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef __MTK_TARGET__
+
+#include "drv_comm.h"
+#include "dcm_sw.h"
+#include "idle_service.h"
+
+#include "kal_public_api.h"
+#include "kal_internal_api.h"
+#include "kal_hrt_api.h"
+#include "mips_ia_utils.h"
+
+#include "us_timer.h"
+#include "intrCtrl.h" /* IRQ Mask/Unmask */
+#include "sync_data.h"
+#include "SST_intrCtrl.h"
+
+#include "RM_public.h"
+#include "sleepdrv_interface.h"
+#include "drv_rstctl.h"
+#include "ostd_public.h"
+#include "task_config.h"
+#include "ptp_public.h"
+#include "pll.h"
+#include "mdmcu_pmu.h"
+
+#if defined (__MODEM_CCCI_EXIST__)
+#include "ccci.h"
+#include "ex_mem_manager_public.h"
+#endif
+
+/* From dormant */
+extern void dormant_mode_activate(void);
+extern void dormant_mode_init(void);
+extern kal_uint32 Dormant_Service_Get_Dormant_Abort(kal_uint32 core_id);
+
+
+/* From MDCIRQ and __MDCIRQ_OSIPI_SPECIAL_FLOW__ macro */
+#include "drv_mdcirq.h"
+extern void interrupt_sleep_init(kal_uint32 vpe_id);
+
+/* From SPV */
+#if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+extern void SPV_core_idlemeter_enter(kal_uint32 coreid);
+extern void SPV_core_idlemeter_exit(kal_uint32 coreid);
+#endif // #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+
+/* The Macro to do IT test */
+//#define IDLE_IT_TEST
+
+/* The Macro to do WAIT duration time check */
+//#define WAIT_DURATION_CHECK
+
+/* DCM_SUPPORT define in dcm_sw.h */
+#if defined(DCM_SUPPORT)
+ #define IFDEF_DCM(def_statement, undef_statement) def_statement
+#else /* Not Support DCM. */
+ #define IFDEF_DCM(def_statement, undef_statement) undef_statement
+#endif /* DCM_SUPPORT */
+
+/* Define in project's makefile (...), TRUE: CPU would execute DORMANT flow. FALSE: No DORMANT flow. */
+#if defined(MTK_SLEEP_ENABLE)
+ #define LOWPWER_ENTER_PAUSE_MODE
+ #define IFDEF_PAUSE_FLOW(def_statement, undef_statement) def_statement
+#else
+ #define IFDEF_PAUSE_FLOW(def_statement, undef_statement) undef_statement
+#endif
+
+#if defined(__PRODUCTION_RELEASE__)
+ #define IFDEF_PRODUCTION(x)
+#else /* __PRODUCTION_RELEASE__ */
+/* under construction !*/
+#endif /* __PRODUCTION_RELEASE__ */
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+#include "drv_vpe_irq.h"
+kal_uint32 idle_service_FMA_not_ready_time[MDCIRQ_TOTAL_VPE_NUM] = {0};
+kal_uint32 idle_service_FMA_ready_time[MDCIRQ_TOTAL_VPE_NUM] = {0};
+#endif
+
+/*
+Below for simple test.
+*//* Remember modify intrCtrl_MT6297.h before test. */
+#if defined(IDLE_IT_TEST)
+kal_uint32 IDLE_IT_InitDone = KAL_FALSE;
+kal_uint32 IDLE_IT_IRQ_count[VPE_NUMBER] = {0};
+kal_timerid IDLE_IT_timer_id;
+kal_uint32 timer_offset = 1;
+
+#define IRQ_SW_VPE0_TEST IRQ_SW_LISR41_CODE /* IRQ ID 321 */
+#define IRQ_SW_VPE1_TEST (IRQ_SW_VPE0_TEST+1) /* IRQ ID 322 */
+#define IRQ_SW_VPE2_TEST (IRQ_SW_VPE1_TEST+1) /* IRQ ID 323 */
+#define IRQ_SW_VPE3_TEST (IRQ_SW_VPE2_TEST+1) /* IRQ ID 324 */
+#define IRQ_SW_VPE4_TEST (IRQ_SW_VPE3_TEST+1) /* IRQ ID 325 */
+#define IRQ_SW_VPE5_TEST (IRQ_SW_VPE4_TEST+1) /* IRQ ID 326 */
+#define IRQ_SW_VPE6_TEST (IRQ_SW_VPE5_TEST+1) /* IRQ ID 327 */
+#define IRQ_SW_VPE7_TEST (IRQ_SW_VPE6_TEST+1) /* IRQ ID 328 */
+#define IRQ_SW_VPE8_TEST (IRQ_SW_VPE7_TEST+1) /* IRQ ID 329 */
+#define IRQ_SW_VPE9_TEST (IRQ_SW_VPE8_TEST+1) /* IRQ ID 330 */
+#define IRQ_SW_VPE10_TEST (IRQ_SW_VPE9_TEST+1) /* IRQ ID 331 */
+#define IRQ_SW_VPE11_TEST (IRQ_SW_VPE10_TEST+1) /* IRQ ID 332 */
+
+static void Idle_Service_IT_timer_cb()
+{
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE1_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE2_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE3_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE4_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE5_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE6_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE7_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE8_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE9_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE10_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE11_TEST);
+
+ kal_cancel_timer(IDLE_IT_timer_id);
+ kal_set_timer(IDLE_IT_timer_id, Idle_Service_IT_timer_cb, NULL, KAL_TICKS_10_MSEC*timer_offset, 0);
+ timer_offset++;
+}
+
+void Idle_Service_IT_vpe_X_lisr(kal_uint32 irqx)
+{
+ IDLE_IT_IRQ_count[irqx-IRQ_SW_VPE0_TEST]++;
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void Idle_Service_IT_test_init(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ if(vpe_id==0)
+ {/* only VPE 0 do the init */
+
+ /* Register ISR for VPE0 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE0_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_0");
+ //IRQSensitivity(IRQ_SW_VPE0_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE0_TEST);
+
+ /* Register ISR for VPE1 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE1_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_1");
+ //IRQSensitivity(IRQ_SW_VPE1_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE1_TEST);
+
+ /* Register ISR for VPE2 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE2_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_2");
+ //IRQSensitivity(IRQ_SW_VPE2_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE2_TEST);
+
+ /* Register ISR for VPE3 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE3_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_3");
+ //IRQSensitivity(IRQ_SW_VPE3_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE3_TEST);
+
+ /* Register ISR for VPE4 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE4_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_4");
+ //IRQSensitivity(IRQ_SW_VPE4_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE4_TEST);
+
+ /* Register ISR for VPE5 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE5_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_5");
+ //IRQSensitivity(IRQ_SW_VPE5_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE5_TEST);
+
+ /* Register ISR for VPE6 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE6_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_6");
+ //IRQSensitivity(IRQ_SW_VPE6_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE6_TEST);
+
+ /* Register ISR for VPE7 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE7_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_7");
+ //IRQSensitivity(IRQ_SW_VPE7_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE7_TEST);
+
+ /* Register ISR for VPE8 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE8_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_8");
+ //IRQSensitivity(IRQ_SW_VPE8_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE8_TEST);
+
+ /* Register ISR for VPE9 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE9_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_9");
+ //IRQSensitivity(IRQ_SW_VPE9_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE9_TEST);
+
+ /* Register ISR for VPE10 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE10_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_10");
+ //IRQSensitivity(IRQ_SW_VPE10_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE10_TEST);
+
+ /* Register ISR for VPE11 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE11_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_11");
+ //IRQSensitivity(IRQ_SW_VPE11_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE11_TEST);
+
+ IDLE_IT_timer_id = kal_create_timer("IDLE_IT_timer");
+ kal_set_timer(IDLE_IT_timer_id, Idle_Service_IT_timer_cb, NULL, KAL_TICKS_5_SEC, 0);
+
+ IDLE_IT_InitDone = KAL_TRUE;
+ }
+}
+#endif/*IDLE_IT_TEST*/
+/*
+Above for simple test.
+*/
+
+kal_uint32 IDLEenterSleep = 1; // Force lock sleep. 1: Could enter DORMANT. 0: Couldn't enter DORMANT.
+kal_uint32 Idle_Service_InitDone = KAL_FALSE; /* Idle Service init done or not, only CORE 0 VPE 0 init in Idle_Service_Init(). */
+kal_uint32 idle_service_hrt_DI_start[CORE_NUMBER] = {0}, idle_service_hrt_DI_end[CORE_NUMBER] = {0}, idle_service_hrt_DI_dur[CORE_NUMBER] = {0};/* Use to Qbit check for HRT domain. */
+//kal_uint32 idle_service_dor_2nd_enter_wait_frc = 0, idle_service_dor_2nd_leave_wait_frc = 0, idle_service_dor_2nd_duration = 0;
+
+kal_uint32 idle_vpe_x_state[VPE_NUMBER] = {0};/* The CIRQ VPE state for each idle task */
+kal_uint32 idle_core_x_vpe_0_tc_grp[CORE_NUMBER] = {0};/* Record the original TC0 group before raise its group(priority) for HRT real time check. */
+
+kal_uint32 idle_emm_start_address;
+kal_uint32 idle_emm_size;
+kal_uint32 idle_emm_init_done;
+
+typedef struct
+{
+ IDLE_ACTION_INDEX action;
+ kal_uint32 frc_ust;
+} IDLE_SERVICE_STEP;
+
+IDLE_SERVICE_STEP idle_service_step[VPE_NUMBER][IDLE_SERVICE_STEP_MAX];
+kal_uint32 idle_service_step_index[VPE_NUMBER] = {0};
+
+typedef struct
+{
+ kal_uint32 idle_service_enter_dormant_frc;/* The us time when entering DORMANT. */
+ kal_uint32 idle_service_dor_abort_leave_dormant_frc; /* The us time when leaving DORMANT due to dormant abort. */
+ kal_uint32 idle_service_leave_dormant_frc; /* The us time when leaving DORMANT. */
+}IDLE_SERVICE_DORMANT_LOG;/* Per-Core's enter/leave dormant time. */
+
+IDLE_SERVICE_DORMANT_LOG idle_service_core_x_dormant_time[CORE_NUMBER];
+
+kal_uint32 idle_service_vpe_x_leave_dormant_frc[VPE_NUMBER] = {0};/* The us time when Each VPE leave DORMANT */
+
+/* Per-CORE's VPE init done or not. CORE could enter DORMANT after This-CORE's all VPE init done.
+Init to 1 in Idle_Service_Init(), clear to 0 before entering DORMANT.
+When This-CORE's VPE 1/2 leave DORMANT, it would config to 1 in Idle_Service_vpe1_vpe2_dormant_leave() again to confirm it is full restore from DORMANT.
+Note: Per-CORE's VPE0 always keep init done after Idle_Service_Init() due to he is the master. */
+volatile kal_uint32 idle_service_vpe_x_init_state[VPE_NUMBER] = {0}; // 1:init doen, 0; not init
+
+kal_uint32 idle_service_enter_wait_time[VPE_NUMBER];
+kal_uint32 idle_service_leave_wait_time[VPE_NUMBER];
+
+/* We use a cacheable parameter to let Per-CORE's VPE 0 could know his VPE1 and VPE2 is in "wait" or not. */
+volatile kal_uint32 idle_service_vpe_x_in_wait_state[VPE_NUMBER]={0};
+
+/* We use a cacheable parameter to let CORE0's VPE0 could know CORE1~3 is in "DORMANT" or not. */
+volatile kal_uint32 idle_service_CoreStatus[CORE_NUMBER] = {0}; //0: normal, 1: WAIT, 2: dormant
+
+/* For debug, to confirm the real dormant/dormant abort flow is right. */
+kal_uint32 idle_service_vpe_real_dormant_times[VPE_NUMBER] = {0};
+
+/*****************************************************************************
+ * Internal Function *
+ *****************************************************************************/
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /*------------------------------------------------------------------------
+ * void idle_service_mask_vpe_irq
+ * Purpose: Mask cirq trigger to specify vpe in Idle_Service_Handler(), this function is only designed for Idle_Service_Handler().
+ * Parameters:
+ * Input: kal_uint32 core_id
+ * kal_uint32 vpe_id
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 Idle_Service_Handler(), Only Per-CORE's VPE 0 could call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+static void idle_service_mask_vpe_irq(kal_uint32 core_id, kal_uint32 vpe_id)
+{
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+
+ /* VPE0 would mask VPE1 and VPE2's IRQ and check HRT Qbit, so we raise up TC0's priority to avoid VPE1/VPE2 occupy pipeline. */
+ idle_core_x_vpe_0_tc_grp[core_id] = miu_save_and_set_c0_tcschedule_grp(HW_ITC_GRP);
+
+ /* Note: Maybe we should raise bus ultra signal here due to normal latency 1us. (EMI_latency) */
+
+ if(0 == core_id)
+ {/* CORE0 VPE0 */
+
+ /* Mask VPE2's CIRQ by set dormant state */
+ drv_mdcirq_set_dormant_state(vpe_id+2);
+
+ /* Mask VPE1's CIRQ by set dormant state */
+ drv_mdcirq_set_dormant_state(vpe_id+1);
+ }
+ else
+ {/* other CORE's VPE0 */
+
+ /* Mask CORE's VPE0 & VPE1 & VPE2's CIRQ by set dormant state */
+ drv_mdcirq_set_dormant_state(vpe_id+2);/* To avoid spurious interrupt, we mask CORE's VPE2 IRQ first. */
+ drv_mdcirq_set_dormant_state(vpe_id+1);/* To avoid spurious interrupt, we mask CORE's VPE1 IRQ first. */
+ drv_mdcirq_set_dormant_state(vpe_id);
+ }
+
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ /* Mask VPE0 & VPE1 & VPE2's OSIRQ */
+ drv_mdcirq_set_OSIPI_Mask(vpe_id+2);
+ drv_mdcirq_set_OSIPI_Mask(vpe_id+1);
+ drv_mdcirq_set_OSIPI_Mask(vpe_id);
+ #endif
+
+ idle_service_hrt_DI_start[core_id] = ust_get_current_time();
+}
+
+ /*------------------------------------------------------------------------
+ * void idle_service_unmask_vpe_irq
+ * Purpose: Unmask cirq trigger to specify vpe in Idle_Service_Handler(), this function is only designed for Idle_Service_Handler().
+ * Parameters:
+ * Input: kal_uint32 core_id
+ * kal_uint32 vpe_id
+ * kal_uint32 Check_hrt_Qbit: Check HRT Qbit or not after enable VPE1 and VPE2's IRQ.
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 Idle_Service_Handler(), Only Per-CORE's VPE 0 could call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+static void idle_service_unmask_vpe_irq(kal_uint32 core_id, kal_uint32 vpe_id, kal_uint32 Check_hrt_Qbit)
+{
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ /* Unmask VPE0 & VPE1 & VPE2's OSIRQ */
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id+2);
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id+1);
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id);
+ #endif
+
+ if (0 == core_id)
+ {/* CORE0 VPE0 */
+
+ /* Unmask VPE1's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id+1);
+
+ /* Unmask VPE2's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id+2);
+ }
+ else
+ {/* other CORE's VPE0 */
+
+ /* Unmask CORE's VPE0 & VPE1 & VPE2's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id);
+ drv_mdcirq_clear_dormant_state(vpe_id+1);
+ drv_mdcirq_clear_dormant_state(vpe_id+2);
+ }
+
+ if (Check_hrt_Qbit==KAL_TRUE)
+ {/* Check HRT Qbit due to we disable VPE1 and VPE2's IRQ */
+
+ idle_service_hrt_DI_end[core_id] = ust_get_current_time();
+ idle_service_hrt_DI_dur[core_id] = ust_us_duration(idle_service_hrt_DI_start[core_id], idle_service_hrt_DI_end[core_id]);
+
+ if( (idle_service_hrt_DI_dur[core_id] > query_Qbits_criteria_HRT_us()))
+ {
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+ IFDEF_PRODUCTION(EXT_ASSERT(0, idle_service_hrt_DI_dur[core_id], idle_service_hrt_DI_start[core_id], query_Qbits_criteria_HRT_us()));
+ }
+
+#if defined(__PRODUCTION_RELEASE__)
+ /* No Check in User load */
+#else /* Eng load */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __PRODUCTION_RELEASE__ */
+
+ /* VPE0 would mask VPE1 and VPE2's IRQ and check HRT Qbit, so we restore TC0's priority after enable VPE1 and VPE2's IRQ and HRT check. */
+ /* Note: Before entering DORMANT, we would restore TC0's priority and don't check HRT Qbit after dormant. */
+ miu_save_and_set_c0_tcschedule_grp(idle_core_x_vpe_0_tc_grp[core_id]);
+
+ /* Note: Maybe we should restore bus ultra signal here due to normal latency 1us. (EMI_latency) */
+
+ }
+
+}
+
+ /*------------------------------------------------------------------------
+ * void idle_service_unmask_vpe_irq_leave_dormant
+ * Purpose: Unmask cirq trigger to specify vpe when leaving DORMANT.
+ * This function copy from idle_service_unmask_vpe_irq() and could be use for each VPE.
+ * This function is only designed for Idle_Service_Handler() and Idle_Service_vpe1_vpe2_dormant_leave().
+ * Parameters:
+ * Input: kal_uint32 vpe_id
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 Idle_Service_Handler() and Per-CORE's VPE1 and VPE2's Idle_Service_vpe1_vpe2_dormant_leave().
+ *
+ *------------------------------------------------------------------------
+ */
+static void idle_service_unmask_vpe_irq_leave_dormant(kal_uint32 vpe_id)
+{
+ /* Set VPE's state to his VPE state */
+ /* The state in GCR would be reset after dormant, so we must re-init it before receiving IRQ,
+ or it would ASSERT in drv_mdcirq_Restore_VPE_state() of isrC_Main(). */
+ drv_mdcirq_Set_VPE_state(vpe_id, idle_vpe_x_state[vpe_id]);
+
+ /* Unmask VPE's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id);
+
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ /* Unmask VPE's OSIRQ */
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id);
+ #endif
+
+}
+
+void idle_service_core0_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void idle_service_core1_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void idle_service_core2_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void idle_service_core3_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+#endif//LOWPWER_ENTER_PAUSE_MODE
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+/*------------------------------------------------------------------------
+* void Idle_Service_Polling_FMA_Status
+* Purpose: APOLLO FMA couln't sync in 2T 26M after WFI. We need to confirm FMA ready and go.
+* Parameters:
+* Input: None.
+*
+* Output: None.
+* returns : None.
+* Note : Called in Per-VPE after WAIT.
+* Normal/HRT domain: Called in mips_enter_wait_mode()
+* Critical HRT domain: Called in Idle_Service_Handler_Wait()
+*------------------------------------------------------------------------
+*/
+static void Idle_Service_Polling_FMA_Status(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ /* Confirm FMA ready and go. */
+ if(fma_sync_status()==0)
+ {//FMA is not ready
+ idle_service_FMA_not_ready_time[vpe_id] = ust_get_current_time_source();
+ while(fma_sync_status()==0)
+ {
+ miu_yield(-1);/*Release Pipeline*/
+ }
+ idle_service_FMA_ready_time[vpe_id] = ust_get_current_time();
+ }
+}
+#endif
+
+/*****************************************************************************
+ * Public Function for users *
+ *****************************************************************************/
+#if defined (__MODEM_CCCI_EXIST__)
+kal_bool IDLE_EMM_WriteDbgInfo(kal_uint32 index, void* addr)
+{
+ if (!idle_emm_init_done)
+ {
+ return KAL_FALSE;
+ }
+ #if defined(__MTK_TARGET__)
+ if (addr == NULL || ((kal_uint32)addr % 4 !=0) || index > IDLE_EMM_INDEX_MAX)
+ {
+ return KAL_FALSE;
+ }
+
+ *((kal_uint32 *)(idle_emm_start_address + (index<<2))) = *((kal_uint32 *)addr);
+ //MM_Sync();
+ #endif
+ return KAL_TRUE;
+}
+#endif
+
+void idle_service_step_logging(kal_uint32 vpe_id, IDLE_ACTION_INDEX step, kal_bool Log_To_EMM)
+{
+ idle_service_step_index[vpe_id]++;
+ if(idle_service_step_index[vpe_id]>=IDLE_SERVICE_STEP_MAX)
+ {
+ idle_service_step_index[vpe_id] = 0;
+ }
+
+ idle_service_step[vpe_id][idle_service_step_index[vpe_id]].action = step;
+ idle_service_step[vpe_id][idle_service_step_index[vpe_id]].frc_ust = ust_get_current_time();
+#if defined (__MODEM_CCCI_EXIST__)
+ if(Log_To_EMM == KAL_TRUE)
+ {/* To reduce UC transaction to EMI, only important log we log to EMM. */
+ IDLE_EMM_WriteDbgInfo(IDLE_EMM_VPE0_IDLE_TASK_STEPLOGGING + (vpe_id<<1), &idle_service_step[vpe_id][idle_service_step_index[vpe_id]].action);
+ IDLE_EMM_WriteDbgInfo(IDLE_EMM_VPE0_IDLE_TASK_FMA + (vpe_id<<1), &idle_service_step[vpe_id][idle_service_step_index[vpe_id]].frc_ust);
+ }
+#endif
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Prepare_WAIT
+ * Purpose: Per-Core Critical HRT domain trigger IRQ to his VPE0 and set WAIT variable.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-Core Critical HRT domain IdleTask and only execute once.
+ * Called in isrC_Main() @ isrentry.c
+ * Note: In our design, Per-Core VPE0 must be Normal domain, so Per-Core VPE0 couldn't call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Prepare_WAIT(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 vpe_0_1_2 = vpe_id%PER_CORE_VPE_NUM;/* To know it is Per-Core VPE0/VPE1/VPE2. */
+
+ if(kal_get_current_domain()!=KAL_DOMAIN_CHRT||vpe_0_1_2==0)
+ {/* Only Critical HRT domain could run this function. Per-Core VPE0 couldn't call this function. */
+ ASSERT(0);
+ }
+
+ /* Note: We didn't DI in Per-Core VPE2's idle task, it would be interrupted any time.
+ But isrC_Main() call this function during DI(EXL==1).*/
+ idle_service_step_logging(vpe_id, IDLE_WFI_WAIT_ENTER, KAL_FALSE);
+ idle_service_enter_wait_time[vpe_id] = ust_get_current_time();
+#if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER + (vpe_id<<1)), (void*)&idle_service_enter_wait_time[vpe_id]);
+#endif
+
+ /* Set the WAIT parameter to let his VPE0 know the VPE is in WAIT. */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_TRUE;
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id = kal_get_current_core_id();
+ /* Trigger IRQ to his VPE0 */
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_CORE0_VPE0_LEAVE_WAIT+core_id);
+#endif
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Check_Init_Done
+ * Purpose: Check Idle Service related init is complete or not .
+ * Parameters:
+ * Input: kal_uint32 vpe_id.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in each VPE IdleTask.
+ * Per-CORE's VPE0 only execute once.
+ * Per-CORE's VPE1/2 would execute many time(due to re-run while IdleTask after DORMANT).
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Check_Init_Done(kal_uint32 vpe_id)
+{
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ //DEBUG_EXT_ASSERT3((vpe_id%PER_CORE_VPE_NUM==0), vpe_id, Idle_Service_InitDone, 0x8967);
+
+ EXT_ASSERT((idle_service_vpe_x_init_state[vpe_id]==1&&Idle_Service_InitDone == KAL_TRUE), vpe_id, idle_service_vpe_x_init_state[vpe_id], Idle_Service_InitDone);
+#endif
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Init
+ * Purpose: Init dormant related functions .
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE 0 IdleTask init function. Only Per-CORE's VPE 0 could call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Init(void)
+{
+
+#if defined(IDLE_IT_TEST)
+ Idle_Service_IT_test_init();
+#endif
+
+/* For using LPM to verify DCM */
+#if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Init();
+#endif
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id, vpe_id, i;
+ dormant_mode_init();
+
+ core_id = kal_get_current_core_id();
+ vpe_id = kal_get_current_vpe_id();
+
+ if((vpe_id%PER_CORE_VPE_NUM) == 0)
+ {/* All CORE's VPE 0 */
+ idle_service_CoreStatus[core_id] = IDLE_STATUS_NORMAL;
+
+ /* Per-CORE's VPE1 and VPE2 init done or not. (Per-CORE's VPE0 help VPE1 and VPE2 init done to confirm they can enter DORMANT at first time.) */
+ idle_service_vpe_x_init_state[vpe_id+1] = 1;
+ idle_service_vpe_x_init_state[vpe_id+2] = 1;
+
+ if(0 == core_id)
+ {/* CORE 0 VPE 0 */
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ kal_bool QueryStatus;
+ QueryStatus = EMM_DirInfo_Query(EMM_DIRECT_WRITE_IDLETASK, &idle_emm_start_address, &idle_emm_size);
+ if( QueryStatus == KAL_TRUE)
+ {
+ idle_emm_init_done = 1;
+ if(IDLE_EMM_INDEX_MAX>(idle_emm_size>>2))
+ {
+ IFDEF_PRODUCTION(EXT_ASSERT(0, IDLE_EMM_INDEX_MAX, idle_emm_start_address, idle_emm_size));
+ }
+ }
+ #endif
+
+ /* Get each VPE state for idle task. */
+ for(i=0;i<VPE_NUMBER;i++)
+ {
+ idle_vpe_x_state[i] = kal_get_idle_task_priority(i);
+ }
+
+ /* Register ISR for Per-CORE VPE1/VPE2 trigger to his VPE0 */
+ //IRQ_Register_LISR(IRQ_SW_CORE0_VPE0_LEAVE_WAIT, idle_service_core0_vpe0_leave_wait_lisr, "IDLE_0");
+ //IRQSensitivity(IRQ_SW_CORE0_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT);
+
+ //IRQ_Register_LISR(IRQ_SW_CORE1_VPE0_LEAVE_WAIT, idle_service_core1_vpe0_leave_wait_lisr, "IDLE_1");
+ //IRQSensitivity(IRQ_SW_CORE1_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE1_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE1_VPE0_LEAVE_WAIT);
+
+ //IRQ_Register_LISR(IRQ_SW_CORE2_VPE0_LEAVE_WAIT, idle_service_core2_vpe0_leave_wait_lisr, "IDLE_2");
+ //IRQSensitivity(IRQ_SW_CORE2_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE2_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE2_VPE0_LEAVE_WAIT);
+
+ //IRQ_Register_LISR(IRQ_SW_CORE3_VPE0_LEAVE_WAIT, idle_service_core3_vpe0_leave_wait_lisr, "IDLE_3");
+ //IRQSensitivity(IRQ_SW_CORE3_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE3_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE3_VPE0_LEAVE_WAIT);
+
+ //core0 Idle_Service_Init should be ready before enter sleep
+ Idle_Service_InitDone = KAL_TRUE;
+ }
+
+ idle_service_vpe_x_init_state[vpe_id] = 1;//Per-CORE's VPE0 init done.
+
+ }
+ else
+ {/* All CORE's VPE1/VPE2 */ /* Only Per-CORE's VPE0 could run this function */
+ ASSERT(0);
+ }
+#endif
+}
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE) && defined(WAIT_DURATION_CHECK)
+#define ILLEGAL_WAIT_TIME 3000000 /* 3 seconds*/
+kal_uint32 vpe_leave_wait_time[VPE_NUMBER] = {0};
+kal_uint32 vpe_wait_duration[VPE_NUMBER] = {0};
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_WaitTime_Check
+ * Purpose: Check the WAIT time duration.
+ * Parameters:
+ * Input: core_id, vpe_id.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE 0 IdleTask==>Idle_Service_Handler()-->mips_enter_wait_mode(void).
+ * Only Per-CORE's VPE 0 could call this function.
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_WaitTime_Check(kal_uint32 core_id, kal_uint32 vpe_id)
+{/* If all VPE on this CORE overlap wait more than 3 seconds, ASSERT!! */
+ kal_uint32 core_1st_leave_wait_time = 0xffffffff, core_final_enter_wait_time = 0;
+ kal_uint32 i = 0;
+ kal_uint32 core_vpe0 = vpe_id, core_vpe1 = vpe_id+1, core_vpe2 = vpe_id+2;
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+ //1. Get leave wait time
+ /* Get the leave wait time for VPE0 */
+ vpe_leave_wait_time[core_vpe0] = idle_service_leave_wait_time[core_vpe0];
+
+ /* Get the leave wait time for VPE1 */
+ if(idle_service_vpe_x_in_wait_state[core_vpe1]==KAL_TRUE)
+ {//This CORE's VPE1 is still in wait
+ vpe_leave_wait_time[core_vpe1] = ust_get_current_time();
+ }
+ else
+ {//This CORE's VPE1 already leave wait
+ vpe_leave_wait_time[core_vpe1] = idle_service_leave_wait_time[core_vpe1];
+ }
+
+ /* Get the leave wait time for VPE2 */
+ if(idle_service_vpe_x_in_wait_state[core_vpe2]==KAL_TRUE)
+ {//This CORE's VPE2 is still in wait
+ vpe_leave_wait_time[core_vpe2] = ust_get_current_time();
+ }
+ else
+ {//This CORE's VPE2 already leave wait
+ vpe_leave_wait_time[core_vpe2] = idle_service_leave_wait_time[core_vpe2];
+ }
+
+ //2. Get wait duration time
+ vpe_wait_duration[core_vpe0] = ust_us_duration(idle_service_enter_wait_time[core_vpe0], vpe_leave_wait_time[core_vpe0]);
+ vpe_wait_duration[core_vpe1] = ust_us_duration(idle_service_enter_wait_time[core_vpe1], vpe_leave_wait_time[core_vpe1]);
+ vpe_wait_duration[core_vpe2] = ust_us_duration(idle_service_enter_wait_time[core_vpe2], vpe_leave_wait_time[core_vpe2]);
+
+ //3. Check all VPE violation
+ if(vpe_wait_duration[core_vpe0]>ILLEGAL_WAIT_TIME&&vpe_wait_duration[core_vpe1]>ILLEGAL_WAIT_TIME&&vpe_wait_duration[core_vpe2]>ILLEGAL_WAIT_TIME)
+ {/* All VPE violation. ==> Get the overlap time. */
+
+ //3-1 Get the core_final_enter_wait_time
+ for(i=0;i<PER_CORE_VPE_NUM;i++)
+ {
+ if(idle_service_enter_wait_time[vpe_id+i] > core_final_enter_wait_time)
+ {
+ core_final_enter_wait_time = idle_service_enter_wait_time[vpe_id+i];
+ }
+ }
+
+ //3-2 Get the core_1st_leave_wait_time
+ for(i=0;i<PER_CORE_VPE_NUM;i++)
+ {
+ if(vpe_leave_wait_time[vpe_id+i] < core_1st_leave_wait_time)
+ {
+ core_1st_leave_wait_time = vpe_leave_wait_time[vpe_id+i];
+ }
+ }
+
+ //3-3 Final check
+ if(core_1st_leave_wait_time < core_final_enter_wait_time)
+ {
+ /* Timer overflow/non-overlap, bypass this time */
+ }
+ else
+ {
+ if( (core_1st_leave_wait_time-core_final_enter_wait_time)>ILLEGAL_WAIT_TIME )
+ {
+ EXT_ASSERT(0, core_1st_leave_wait_time, core_final_enter_wait_time, ILLEGAL_WAIT_TIME);
+ }
+ }
+
+ }
+ else
+ {
+ /* Someone pass, do nothing. */
+ }
+
+
+}
+#endif
+
+ /*------------------------------------------------------------------------
+ * void mips_enter_wait_mode
+ * Purpose: Enter wait mode.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Idle_Service_Handler() by Per-core's VPE0 and Called in Idle_Service_Handler_Slave() by HRT Domain VPE.
+ *
+ *------------------------------------------------------------------------
+ */
+void mips_enter_wait_mode(void)
+{
+ kal_uint32 vpe_id = 0, Idle_CP0_status = 0;
+ vpe_id = kal_get_current_vpe_id();
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id = kal_get_current_core_id();
+ kal_uint32 vpe_0_1_2 = vpe_id%PER_CORE_VPE_NUM;/* To know it is Per-Core VPE0/VPE1/VPE2. */
+#endif
+
+ //disable WDT
+ drv_rstctl_clr_check_bit((vpeid_e)vpe_id);
+
+ idle_service_enter_wait_time[vpe_id] = ust_get_current_time();
+#if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER + (vpe_id<<1)), (void*)&idle_service_enter_wait_time[vpe_id]);
+#endif
+
+ /* Set the WAIT parameter to know this VPE is in WAIT. */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_TRUE;
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ MM_Sync();/* Add this sync to avoid SHAOLIN run out of order */
+
+ if(vpe_0_1_2!=0)
+ {/* Per-CORE's VPE1/VPE2(HRT domain) would run. */
+
+ /* Trigger IRQ to his VPE0 */
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_CORE0_VPE0_LEAVE_WAIT+core_id);
+ }
+#endif
+
+ /* Note: Don't add function here due to we should let "idle_service_vpe_x_in_wait_state[vpe_id] = KAL_TRUE" close WAIT. */
+
+ /* We must DI, then enter WAIT. */
+ Idle_CP0_status = miu_mfc0(MIU_C0_STATUS);
+ if((Idle_CP0_status&0x1)!=0x0)
+ {
+ EXT_ASSERT(0, vpe_id, Idle_CP0_status, 0);
+ }
+
+ /* "WAIT" instruction */
+ miu_wait();
+
+ /* Note!! If per-core's VPE1 recover from DORMANT, it wouldn't run below.
+ It would run dormant recover... -> Idle_Service_vpe1_vpe2_dormant_leave() */
+
+ /* leave WAIT */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_FALSE;
+
+ idle_service_leave_wait_time[vpe_id] = ust_get_current_time_source();
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ /* Confirm FMA ready and go. */
+ Idle_Service_Polling_FMA_Status();
+#endif
+
+#if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_WFI_LEAVE + (vpe_id<<1)), (void*)&idle_service_leave_wait_time[vpe_id]);
+#endif
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE) && defined(WAIT_DURATION_CHECK)
+ /* Wait Duration time check */
+ if(vpe_0_1_2==0)
+ {//Only Per-CORE VPE0 could call this
+ IFDEF_PRODUCTION(Idle_Service_WaitTime_Check(core_id, vpe_id));
+ }
+#endif
+
+ drv_rstctl_set_check_bit((vpeid_e)vpe_id);
+ drv_rstctl_set_kick_bit((vpeid_e)vpe_id);
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Handler
+ * Purpose: Per-CORE's VPE 0's IDLE Service Handler. Called in idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 IdleTask and execute in while loop.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Handler(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 _savedMask;
+ kal_checksleep_e OST_ReadyToSlept = OSTD_WAIT;
+ kal_uint32 Idle_CP0_status = 0;
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id = kal_get_current_core_id();
+ kal_uint32 quit_scheduler;
+ kal_uint32 swLockSleep, validSleepTime = 0;
+ kal_uint32 core1_status = 0;
+ kal_uint32 core2_status = 0;
+ kal_uint32 core3_status = 0;
+ kal_uint32 core_x_vpe1_wait_state = KAL_FALSE;
+ kal_uint32 core_x_vpe2_wait_state = KAL_FALSE;
+ kal_bool core_x_vpe1_pending_irq_status = KAL_FALSE;
+ kal_bool core_x_vpe2_pending_irq_status = KAL_FALSE;
+ kal_bool core_x_vpe1_pending_osirq_status = KAL_FALSE;
+ kal_bool core_x_vpe2_pending_osirq_status = KAL_FALSE;
+ Sleep_Time allow_sleep_dur = {0,0,0};
+ kal_uint32 directly_wait = KAL_FALSE;
+ kal_uint32 core_vpe1 = vpe_id+1, core_vpe2 = vpe_id+2;
+#endif /* LOWPWER_ENTER_PAUSE_MODE */
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+
+ //idle_service_step_logging(vpe_id, IDLE_HANDLER_USER_IAPMU_CM, KAL_FALSE);
+
+ mdmcu_pmu_idle_reset();
+
+ idle_service_step_logging(vpe_id, IDLE_HANDLER_ENTER, KAL_FALSE);
+
+ if(0 == vpe_id)
+ {/* Request by SD10 to flush low power log, only enable by "AT+EGCMD=9487" AT CMD and default off. */
+ SleepDrv_LowPowerMonitorFlushCheck();/* enable when lpm.LPM_NVRAM_LogOn==1 */
+ }
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ if(idle_service_vpe_x_init_state[core_vpe1]==0||idle_service_vpe_x_init_state[core_vpe2]==0)
+ {
+ //This CORE's VPE1/VPE2 init is not ready
+ return;
+ }
+
+ /* Clear Per-Core's VPE1/2 wait IRQ here since VPE0 is re-running Idle_Task. */
+ MDCIRQ_Deactivate_LISR_without_ITC(IRQ_SW_CORE0_VPE0_LEAVE_WAIT + core_id);
+
+ if(0 == core_id)
+ {/* CORE 0 VPE 0 would get the sleep time. */
+ kal_get_sleep_time(&allow_sleep_dur);//Waste time so don't put this function in critical section to avoid HRT Qbit check fail.
+ }
+#endif
+
+ /* Disable Ibit sampling for coreX VPE0 self, and disable IRQ */
+ _savedMask = drv_mdcirq_Idletask_DI();
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+
+ idle_service_step_logging(vpe_id, IDLE_HANDLER_ENTER_DI, KAL_FALSE);
+
+ /* To avoid spurious interrupt, we confirm per-CORE's VPE1 and VPE2 in wait before masking his IRQ. */
+ /* To get more wait time, we pre-check SleepLock here, but we still check SleepLock again later when mask VPE1/VPE2's IRQ to avoid race condition. */
+ if (idle_service_vpe_x_in_wait_state[core_vpe1]!=KAL_TRUE||idle_service_vpe_x_in_wait_state[core_vpe2]!=KAL_TRUE||OSTD_CheckIsSleepLock()==KAL_TRUE)
+ {/* Since this CORE's VPE1/VPE2 is not in WAIT or someone lock sleep, we couldn't enter DORMANT. This CORE's VPE0 go to WAIT directly. */
+ //idle_service_step_logging(vpe_id, IDLE_COREx_VPE1_NOT_IN_WAIT, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ directly_wait = KAL_TRUE;
+ }
+ else
+ {/* Check CORE could go to DORMANT or not. */
+
+ idle_service_step_logging(vpe_id, IDLE_REMOVE_FROM_SCHEDULING, KAL_FALSE);
+
+ quit_scheduler = kal_remove_core_from_scheduling();/* Remove this CORE's VPE 0~2 from scheduler */
+ if (quit_scheduler == 0) /*Not quit scheduler*/
+ {/* Remove fail means related VPE1&VPE2 is not in idle task or there is pending IRQ on this CORE. ==> we could go to wait directly. */
+ idle_service_step_logging(vpe_id, IDLE_REMOVE_FROM_SCHEDULING_FAIL, KAL_FALSE);
+
+ OST_ReadyToSlept = OSTD_WAIT;
+ directly_wait = KAL_TRUE;
+ }
+ else /* Remove scheduler success!! */
+ {
+ idle_service_step_logging(vpe_id, IDLE_REMOVE_FROM_SCHEDULING_OK, KAL_TRUE);
+
+ idle_service_mask_vpe_irq(core_id, vpe_id);/* Mask this Core's all VPE's IRQ from CIRQ!! */
+
+ if(drv_mdcirq_IRQ_B_status(vpe_id) == KAL_TRUE
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ || drv_mdcirq_OSIPI_status(vpe_id) == KAL_TRUE
+ #endif
+ )
+ {// means that there is pending interrupt. Per-CORE's VPE 0 check here.
+ idle_service_step_logging(vpe_id, IDLE_CHECK_PENDING_IRQ_FAIL, KAL_FALSE);
+
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_TRUE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE0 & VPE1 & VPE2 to scheduler */
+
+ /* Enable Ibit sampling for coreX VPE0 self and enable IRQ */
+ drv_mdcirq_Idletask_EI(_savedMask);
+
+ return;
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_CHECK_PENDING_IRQ_OK, KAL_TRUE);
+ swLockSleep = OSTD_CheckIsSleepLock();
+ idle_service_step_logging(vpe_id, IDLE_CHECK_SW_LOCK_DONE, KAL_TRUE);
+
+ core_x_vpe1_pending_irq_status = drv_mdcirq_IRQ_B_status(core_vpe1);/* Check IRQ pending for Per-CORE's VPE 1 here. */
+ core_x_vpe2_pending_irq_status = drv_mdcirq_IRQ_B_status(core_vpe2);/* Check IRQ pending for Per-CORE's VPE 2 here. */
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ core_x_vpe1_pending_osirq_status = drv_mdcirq_OSIPI_status(core_vpe1);/* Check OSIRQ pending for Per-CORE's VPE 1 here. */
+ core_x_vpe2_pending_osirq_status = drv_mdcirq_OSIPI_status(core_vpe2);/* Check OSIRQ pending for Per-CORE's VPE 2 here. */
+ #endif
+ core_x_vpe1_wait_state = idle_service_vpe_x_in_wait_state[core_vpe1];/* After masking IRQ of per-CORE's VPE1, we must check per-CORE's VPE1 is still in WAIT or not */
+ core_x_vpe2_wait_state = idle_service_vpe_x_in_wait_state[core_vpe2];/* After masking IRQ of per-CORE's VPE2, we must check per-CORE's VPE2 is still in WAIT or not */
+
+ if(0 == core_id)
+ {/* CORE 0 VPE 0 */
+ core1_status = idle_service_CoreStatus[1];
+ #if defined(__MD97_IS_2CORES__)/* For 6297 H3 FPGA only, only 2 CORE */
+ core2_status = IDLE_STATUS_DORMANT;
+ core3_status = IDLE_STATUS_DORMANT;
+ #else /* run here~ */
+ core2_status = idle_service_CoreStatus[2];
+ core3_status = idle_service_CoreStatus[3];
+ #endif
+
+ if( (core1_status!=IDLE_STATUS_DORMANT) || (core2_status!=IDLE_STATUS_DORMANT) || (core3_status!=IDLE_STATUS_DORMANT) || (IDLEenterSleep==0) /* Force disable sleep */
+ || (swLockSleep) || core_x_vpe1_wait_state!=KAL_TRUE || core_x_vpe2_wait_state!=KAL_TRUE || core_x_vpe1_pending_irq_status == KAL_TRUE
+ || core_x_vpe2_pending_irq_status == KAL_TRUE || core_x_vpe1_pending_osirq_status == KAL_TRUE || core_x_vpe2_pending_osirq_status == KAL_TRUE )
+ {/* WAIT case 1 */
+ idle_service_step_logging(vpe_id, IDLE_WAIT_CASE, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ }
+ else
+ {/* Check validSleepTime, do OSTD_CheckSleep() */
+
+ /* In kal_is_valid_sleep_time(), it would set AFN & UFN. We should prove no other VPE set AFN & UFN at the same time to
+ avoid race condition due to we don't take lock.
+ So we call kal_is_valid_sleep_time() here due to all the other VPEs is in wait or DORMANT. */
+ validSleepTime = kal_is_valid_sleep_time(&allow_sleep_dur);
+
+ if(validSleepTime==0)
+ {/* WAIT case 2 */
+ idle_service_step_logging(vpe_id, IDLE_NOT_SLEEP_TIME, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ }
+ else
+ {/* OSTD_CheckSleep() */
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP, KAL_TRUE);
+ OST_ReadyToSlept = OSTD_CheckSleep();
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP_DONE, KAL_TRUE);
+ }
+ }
+
+ }
+ else
+ {/* CORE1/CORE2/CORE3 VPE 0 */
+ if( (swLockSleep) || core_x_vpe1_wait_state!=KAL_TRUE || core_x_vpe2_wait_state!=KAL_TRUE || core_x_vpe1_pending_irq_status == KAL_TRUE || core_x_vpe2_pending_irq_status == KAL_TRUE
+ || core_x_vpe1_pending_osirq_status == KAL_TRUE || core_x_vpe2_pending_osirq_status == KAL_TRUE || (IDLEenterSleep==0) /* Force disable sleep */)
+ {/* WAIT */
+ idle_service_step_logging(vpe_id, IDLE_WAIT_CASE, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ }
+ else
+ {/* do OSTD_CheckSleep() */
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP, KAL_TRUE);
+ OST_ReadyToSlept = OSTD_CheckSleep();
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP_DONE, KAL_TRUE);
+ }
+
+ }
+
+ }
+ }
+
+ /*-----Below Check Normal Domain Qbit before enter WAIT/DORMANT-----*/
+ #if 0/* Since we would check HRT Qbit, we don't need to check SMP Qbit here. */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+ /*-----Above Check Normal Domain Qbit before enter WAIT/DORMANT-----*/
+
+#endif /* LOWPWER_ENTER_PAUSE_MODE */
+
+ if(OSTD_WAIT == OST_ReadyToSlept)
+ {
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ if(directly_wait == KAL_TRUE)
+ {
+ idle_service_step_logging(vpe_id, IDLE_DIRECTLY_WAIT, KAL_FALSE);
+ /* We didn't mask VPE IRQ, so no need to call idle_service_unmask_vpe_irq() here. */
+
+ /* We didn't remove VPE from scheduler or remove fail, so no need to call kal_add_core_to_scheduling(WHOLE_CORE); here. */
+ }
+ else
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_WAIT, KAL_FALSE);
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_TRUE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE 0~2 to scheduler */
+ }
+#endif
+
+ /* For using LPM to verify DCM */
+ #if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Start();
+ #endif
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /* We unmask Per-Core's VPE1/2 wait IRQ here due to VPE0 would enter WAIT. */
+ IRQUnmask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT + core_id);
+#endif
+
+ idle_service_step_logging(vpe_id, IDLE_OSTD_WAIT_ENTER, KAL_FALSE);
+ mips_enter_wait_mode();
+ idle_service_step_logging(vpe_id, IDLE_OSTD_WAIT_LEAVE, KAL_FALSE);
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /* We mask Per-Core's VPE1/2 wait IRQ here due to VPE0 leave WAIT. We could ignore this IRQ. */
+ IRQMask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT + core_id);
+#endif
+
+ /* For using LPM to verify DCM */
+ #if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Stop();
+ #endif
+
+ }
+ else if(OSTD_BUSY == OST_ReadyToSlept)
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_BUSY, KAL_FALSE);
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_TRUE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE0 & VPE1 & VPE2 to scheduler */
+
+ // do nothing, to re-entry handler soon
+
+ if(core_id != 0)
+ {/* CSC IRQ would cause leaving from DORMANT or get BUSY, so we put here to clear. */
+ /* Note: For CORE0, SD10 clear DORMANT abort states in OSTD_Interrupt().
+ For CORE1~3, SD10 clear DORMANT abort states in OSTD_CSC_handler(). */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_ENTER, KAL_TRUE);
+ OSTD_CSC_handler(); /* External function from SD10. Core 1/2/3 clear CSC IM bit & CSC IRQ. */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_LEAVE, KAL_FALSE);
+ }
+#endif
+ }
+ else if(OSTD_DORMANT == OST_ReadyToSlept)
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_DORMANT, KAL_FALSE);
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /* We should restore TC0's priority before DORMANT due to there is no HRT Qbit check. */
+ miu_save_and_set_c0_tcschedule_grp(idle_core_x_vpe_0_tc_grp[core_id]);
+
+ /* Note: Maybe we should restore bus ultra signal here due to normal latency 1us. (EMI_latency) */
+
+ if(core_id == 0)
+ {
+ //kick WDT
+ drv_rstctl_set_kick_bit((vpeid_e)vpe_id);
+
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE0 go to sleep, Only Enable clock disable */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Control(KAL_TRUE, DCM_Lv2_SHAOLIN_DCM_ONLY_CLK_DISABLE),);
+ #endif
+
+ /* Call before sleep, request by SD10 */
+ idle_service_step_logging(vpe_id, IDLE_PTP_SLEEP_ENTER, KAL_TRUE);
+ ptp_sleep();
+ idle_service_step_logging(vpe_id, IDLE_PTP_SLEEP_LEAVE, KAL_TRUE);
+
+ /* Before DORMANT, VPE0 check DCXO_RDY_WO_ACK to know 26M is ready or not. */
+ IFDEF_PRODUCTION(PLL_Check_26M_ACK_Status(0x1111));
+
+ }
+ else/* CORE1~3 */
+ {
+ //disable WDT
+ drv_rstctl_clr_check_bit((vpeid_e)vpe_id);
+
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE1 or CORE2 or CORE3 go to sleep, disable the memslp control path of core1/2/3 */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Core_Memslp_Path_Control(KAL_FALSE, core_id),);
+ #endif
+ }
+
+ idle_service_CoreStatus[core_id] = IDLE_STATUS_DORMANT;
+
+ idle_service_core_x_dormant_time[core_id].idle_service_enter_dormant_frc = ust_get_current_time();
+ idle_service_core_x_dormant_time[core_id].idle_service_dor_abort_leave_dormant_frc = 0;
+ idle_service_core_x_dormant_time[core_id].idle_service_leave_dormant_frc = 0;
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ if(OSTD_Infinite_Sleep_Query())
+ {
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_Core0_INFINITESLEEP_WFI + core_id), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_enter_dormant_frc));
+ }
+ else
+ {
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_ENTER + (vpe_id*3)), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_enter_dormant_frc));
+ }
+ #endif //#if defined (__MODEM_CCCI_EXIST__)
+
+ idle_service_vpe_x_init_state[core_vpe1] = 0; //clear VPE1 init state by VPE0.
+ idle_service_vpe_x_init_state[core_vpe2] = 0; //clear VPE2 init state by VPE0.
+
+ #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+ SPV_core_idlemeter_enter(core_id);
+ #endif // #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+
+ /* ---Enter DORMANT Mode--- */
+
+ dormant_mode_activate();
+
+ /* ---Leave DORMANT Mode--- */
+
+ idle_service_CoreStatus[core_id] = IDLE_STATUS_NORMAL;
+ idle_service_vpe_x_leave_dormant_frc[vpe_id] = ust_get_current_time();//you could see idle_service_core_x_dormant_time[core_id] to know it is dormant abort or not
+
+ #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+ SPV_core_idlemeter_exit(core_id);
+ #endif // #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+
+ if(core_id == 0)
+ {
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE0 wake up, Enable memslp function + clock disable @WFI */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Control(KAL_TRUE, DCM_Lv2_SHAOLIN_DCM_MEMSLP_AND_CLK_DISABLE),);
+ #endif
+
+ /* Call after wakeup, request by SD10 */
+ idle_service_step_logging(vpe_id, IDLE_PTP_WAKE_ENTER, KAL_TRUE);
+ ptp_wake();
+ idle_service_step_logging(vpe_id, IDLE_PTP_WAKE_LEAVE, KAL_TRUE);
+
+ /* After DORMANT(No matter dormant abort or not), VPE0 check DCXO_RDY_WO_ACK to know 26M is ready or not. */
+ IFDEF_PRODUCTION(PLL_Check_26M_ACK_Status(0x2222));
+ }
+ else/* CORE1~3 */
+ {
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE1 or CORE2 or CORE3 wake up, enable the memslp control path of core1/2/3 */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Core_Memslp_Path_Control(KAL_TRUE, core_id),);
+ #endif
+ }
+
+ /* After DORMANT(No matter dormant abort or not), Per-core's VPE0 call SD10's check function. */
+ MD_TOPSM_GetErrorStatus();
+
+ if(Dormant_Service_Get_Dormant_Abort(core_id)==KAL_TRUE)
+ {/* 1. DORMANT abort ==> run WAIT flow */
+ idle_service_core_x_dormant_time[core_id].idle_service_dor_abort_leave_dormant_frc = ust_get_current_time();
+
+ /* When DORMANT abort, This-CORE's VPE1/VPE2 is still in wait and his idle_service_vpe_x_init_state==0. We should re-init by VPE0. */
+ idle_service_vpe_x_init_state[core_vpe1] = 1;
+ idle_service_vpe_x_init_state[core_vpe2] = 1;
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE + (vpe_id*3)), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_dor_abort_leave_dormant_frc));
+ #endif
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_ABORT_LEAVE, KAL_FALSE);
+
+ /* We don't check HRT Qbit when OSTD_DORMANT */
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_FALSE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE0 & VPE1 & VPE2 to scheduler */
+
+ }
+ else
+ {/* 2. Really restore from DORMANT */
+
+ idle_service_core_x_dormant_time[core_id].idle_service_leave_dormant_frc = ust_get_current_time();
+
+ idle_service_vpe_real_dormant_times[vpe_id]++;
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE + (vpe_id*3)), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_leave_dormant_frc));
+ #endif
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_LEAVE, KAL_FALSE);
+
+ if(vpe_id == 0)
+ {/* CORE0 VPE0 re-init Lv3 DCM */
+ /* Re-init Lv3 SHAOLIN DCM in GCR due to it would be disable after DORMANT. */
+ IFDEF_DCM(DCM_Lv3_SHAOLIN_DCM_Control(KAL_TRUE),);
+ IFDEF_DCM(DCM_Lv3_SFU_SPU_DCM_Control(DCM_Lv3_SFU_SPU_ALL_DCM, KAL_TRUE),);
+ /* Restore/Check wake up source mask after DORMANT. */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Mask_WakeUp_Source_In_GCR(),);
+ /* Re-init Lv3 Cache DCM */
+ IFDEF_DCM(DCM_Lv3CACHE_DCM_Control(KAL_TRUE),);
+ }
+
+ #if 0//We would keep this IRQ mask before entering Dormant, so no need mask here.
+/* under construction !*/
+/* under construction !*/
+ #endif
+ idle_service_unmask_vpe_irq_leave_dormant(vpe_id);
+ kal_add_core_to_scheduling(SINGLE_VPE);/* Add this CORE's VPE0 to scheduler */ /* VPE1/VPE2 would add to Scheduler by himself */
+
+ }
+
+ if( core_id != 0 )
+ {/* CSC IRQ would cause leaving from DORMANT or get BUSY, so we put here to clear. */
+ /* Note: For CORE0, SD10 clear DORMANT abort states in OSTD_Interrupt().
+ For CORE1 & CORE2 & CORE3, SD10 clear DORMANT abort states in OSTD_CSC_handler(). */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_ENTER, KAL_TRUE);
+ OSTD_CSC_handler(); /* External function from SD10. Core 1/2/3 clear CSC IM bit & CSC IRQ. */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_LEAVE, KAL_TRUE);
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_WAIT_ENTER, KAL_FALSE);
+ /* Enter WAIT mode again due to wakeup event would come first, and IRQ comes later.
+ By the way, for CORE1, some user(EX: 4G timer) may only trigger IRQ to VPE1 with wakeup event,
+ so CORE1 VPE0 may stay in this wait for a long time. */
+ mips_enter_wait_mode();
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_WAIT_LEAVE, KAL_FALSE);
+
+ #if 0//We would keep this IRQ mask before entering Dormant, so no need mask above and no need unmask here.
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+
+#else /* This path didn't support. */
+ ASSERT(0);
+#endif
+
+ }
+ else
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_INVALID_CASE, KAL_TRUE);
+ ASSERT(0);
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_HANDLER_LEAVE, KAL_TRUE);
+
+ /* We must DI, then leave WAIT. */
+ Idle_CP0_status = miu_mfc0(MIU_C0_STATUS);
+ if((Idle_CP0_status&0x1)!=0x0)
+ {
+ EXT_ASSERT(0, vpe_id, Idle_CP0_status, 0);
+ }
+
+ /* Enable Ibit sampling for coreX VPE0 self and enable IRQ */
+ drv_mdcirq_Idletask_EI(_savedMask);
+
+ /* For using LPM to verify DCM */
+ #if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Print_and_Update_Setting(vpe_id, OST_ReadyToSlept);
+ #endif
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Handler_Slave
+ * Purpose: HRT Domain's IDLE Service Handler. Called in idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's HRT Domain IdleTask and execute in while loop.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Handler_Slave(void)
+{
+ kal_uint32 vpe_id;
+ kal_uint32 _savedMask;
+
+ vpe_id = kal_get_current_vpe_id();
+
+ /* Only HRT Domain could run this function. (But Per-Core VPE0 always couldn't run this function.) */
+ EXT_ASSERT(((kal_get_current_domain()==KAL_DOMAIN_HRT)&&(vpe_id%PER_CORE_VPE_NUM!=0)), vpe_id, kal_get_current_domain(), 0x22567);
+
+ /* Disable Ibit sampling for this VPE and disable IRQ */
+ _savedMask = drv_mdcirq_Idletask_DI();
+
+ kal_set_slave_vpe_idle_flag();
+
+ idle_service_step_logging(vpe_id, IDLE_WFI_WAIT_ENTER, KAL_FALSE);
+ mips_enter_wait_mode();
+ idle_service_step_logging(vpe_id, IDLE_WFI_WAIT_LEAVE, KAL_FALSE);
+
+ kal_remove_slave_vpe_idle_flag();
+
+ /* Note!! If this VPE recover from DORMANT, it wouldn't run below.
+ It would run dormant recover... -> Idle_Service_vpe1_vpe2_dormant_leave() */
+
+ /* Enable Ibit sampling for this VPE and enable IRQ */
+ drv_mdcirq_Idletask_EI(_savedMask);
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Handler_Wait
+ * Purpose: Critical HRT Domain's IDLE Service Handler. Called in idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's Critical HRT Domain IdleTask and execute in while loop.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Handler_Wait(void)
+{
+ /*
+ Note: Critical HRT Domain Disable WDT and Idle_Service_Prepare_WAIT() are called in isrentry.c
+ */
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ Set_EXL();
+#endif
+
+ /* "WAIT" instruction */
+ miu_wait();
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ /* Confirm FMA ready and go. */
+ Idle_Service_Polling_FMA_Status();
+ Clear_EXL();
+#endif
+
+ /* Note!! If this VPE recover from DORMANT, it wouldn't run below.
+ It would run dormant recover... -> Idle_Service_vpe1_vpe2_dormant_leave() */
+
+#if 0 //Already move to MDCIRQ
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if defined (__MODEM_CCCI_EXIST__)
+/* under construction !*/
+ #endif
+/* under construction !*/
+#endif
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_vpe1_vpe2_dormant_leave
+ * Purpose: When Per-CORE's VPE1/VPE2 leave DORMANT, re-run idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Only Per-CORE's VPE1/VPE2 would call this function.
+ * This function only be called when Per-CORE's VPE1/VPE2 leave DORMANT.
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_vpe1_vpe2_dormant_leave(void)
+{/* Called in interAptiv-dormantMode_gcc.S */
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ //kal_uint32 core_id = kal_get_current_core_id();
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 Idle_CP0_status = 0;
+ kal_uint32 vpe_0_1_2 = vpe_id%PER_CORE_VPE_NUM;/* To know it is Per-Core VPE0/VPE1/VPE2. */
+ kal_uint32 domain = kal_get_current_domain();
+
+ EXT_ASSERT((vpe_0_1_2==1||vpe_0_1_2==2), vpe_id, domain, 0x456);
+
+ idle_service_vpe_x_leave_dormant_frc[vpe_id] = ust_get_current_time();
+ #if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE + (vpe_id*3)), (void*)&idle_service_vpe_x_leave_dormant_frc[vpe_id]);
+ #endif
+
+ /* Clear the WAIT parameter to let his VPE0 know VPE1/VPE2 is not in WAIT. */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_FALSE;
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_LEAVE, KAL_FALSE);
+
+ idle_service_vpe_real_dormant_times[vpe_id]++;
+
+ if(domain==KAL_DOMAIN_HRT)
+ {/* HRT Domain */
+ /* Re-enable WDT */
+ drv_rstctl_set_check_bit((vpeid_e)vpe_id);
+ drv_rstctl_set_kick_bit((vpeid_e)vpe_id);
+
+ /* Enable IBit sampling for HRT Domain */
+ drv_mdcirq_IBit_sampling_enable(vpe_id, KAL_TRUE);/* Note: We must not enable IRQ here. We enable IRQ in sceduler. */
+ }
+ else if(domain==KAL_DOMAIN_CHRT)
+ {/* Critical HRT Domain */
+
+ /* Note: We didn't enable this VPE's WDT here due to this VPE is WAIT directly for critical LISR. */
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ /* Since this VPE is Set_EXL enter DORMANT, we need to restore it. */
+ Clear_EXL();
+#endif
+
+ /* Since this VPE is EI enter DORMANT and we need to remain DI, then handover to scheduler.
+ We DI here before unmask from CIRQ. */
+ __asm__ __volatile__( \
+ "di \n\t" \
+ "ehb\n\t" \
+ : \
+ : \
+ );
+ }
+
+ idle_service_unmask_vpe_irq_leave_dormant(vpe_id);
+
+ /* We disable IRQ and enter DORMANT.(So no one restore IRQ after entering DORMANT).
+ Before VPE1/VPE2 re-run the scheduler, we should restore "sst_hrt_qbit_count" and "di_tc" to avoid checking fail. */
+ interrupt_sleep_init(vpe_id);
+
+ idle_service_vpe_x_init_state[vpe_id] = 1; // VPE1/VPE2 init is ready.
+
+ /* We must remain DI, then handover to scheduler. */
+ Idle_CP0_status = miu_mfc0(MIU_C0_STATUS);
+ if((Idle_CP0_status&0x1)!=0x0)
+ {
+ EXT_ASSERT(0, vpe_id, Idle_CP0_status, 0);
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_VPE1_VPE2_ENTER_SCHED, KAL_TRUE);
+ /* Add this CORE's VPE1/VPE2 to scheduler and re-run idle task in TCCT_Schedule */
+ kal_add_core_to_scheduling(SINGLE_VPE);
+#endif
+
+}
+
+#endif //__MTK_TARGET__
+
diff --git a/mcu/driver/sys_drv/init/src/md97/idle_task.c b/mcu/driver/sys_drv/init/src/md97/idle_task.c
new file mode 100644
index 0000000..83ec2b9
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/idle_task.c
@@ -0,0 +1,860 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_task.c
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file is for the functions of idle task.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
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+ * removed!
+ *
+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef __MTK_TARGET__
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "syscomp_config.h"
+#include "task_config.h" /* Task creation */
+#include "kal_general_types.h"
+#include "kal_internal_api.h"
+#include "us_timer.h"
+#include "drv_rstctl.h"
+#include "mips_ia_utils.h"
+#include "kal_cpuinfo.h"
+#if defined(__BW_RUNTIME_PF__)/* For SPV */
+#include "spv_api.h"
+#endif
+
+/* Force idle task only while(1) */
+#if defined(__ESL_MASE_GEN97__)
+#define IDLE_TASK_BUSY_LOOPING
+#endif
+
+extern void DCM_Init(void);
+extern void Idle_Service_Check_Init_Done(kal_uint32 vpe_id);
+extern void Idle_Service_Init(void);
+extern void Idle_Service_Handler(void);
+extern void Idle_Service_Handler_Slave(void);
+extern void Idle_Service_Handler_Wait(void);
+extern void Idle_Service_Prepare_WAIT(void);
+
+kal_bool IdleTask_init(void)
+{/* Due to OS design, only Per-Core VPE0 would do task init. */
+
+ #if defined(MT6297_IA)
+ //Idle_Service_Init()& DCM_Init() didn't support 97 IA
+ #else
+ Idle_Service_Init();
+
+ /* Note: If you want to move DCM_Init() to IdleTask(), you should avoid memslp control race condition:
+ 1st boot up, Core 1~3 would run faster than Core0 ==> Core1~3 didn't wait Core0 finish DCM_Init() and would disable memslp, go to sleep.
+ Then Core0 enable memslp for all core in DCM_Init()->dcm_Lv2_shaolin_dcm_init(),
+ it would cause CPU hang due to Core1~3's memslp is enable when Core1~3 sleep!! */
+ DCM_Init();
+
+ #endif
+
+ return KAL_TRUE;
+}
+
+//Put in UC region to avoid high priority TC occupy pipeline.
+//__attribute__((__section__("NONCACHEDRW"))) volatile kal_uint32 temptag = 1;
+
+kal_uint32 IdleTask_domain[SYS_MCU_NUM_VPE] = {0};
+void IdleTask(task_entry_struct * task_entry_ptr)
+{
+ volatile kal_uint32 temptag = 1;
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 domain;
+
+ /* Each VPE/Idle Task help OS set TC priority.
+ Note: Per-Core VPE1/2 leave dormant would re-run full IdleTask(),
+ so the function would be called again after dormant. */
+ KAL_SET_DEFAULT_TC_PRIO();
+
+ domain = kal_get_current_domain();
+
+ IdleTask_domain[vpe_id] = domain;
+
+/* For BASIC load, it is only while loop. */
+#if defined(__MAUI_BASIC__) || defined(IDLE_TASK_BUSY_LOOPING)
+ while(temptag)
+ {/* Infinite loop */
+ miu_wait();/* "WAIT" instruction */
+ }
+#else
+
+ /* Confirm related init is complete. */
+ Idle_Service_Check_Init_Done(vpe_id);
+
+ if(domain==KAL_DOMAIN_NORMAL)
+ {
+ while(temptag)
+ {/* Infinite loop */
+ miu_relinquish();//Release Pipeline
+ Idle_Service_Handler();
+ }
+ }
+ else if(domain==KAL_DOMAIN_HRT)
+ {
+ while(temptag)
+ {/* Infinite loop */
+ miu_relinquish();//Release Pipeline
+ Idle_Service_Handler_Slave();
+ }
+ }
+ else if(domain==KAL_DOMAIN_CHRT)
+ {
+ //Due to Critical HRT domain WDT is controled by IRQ handler, we disable WDT here to avoid no IRQ coming.
+ drv_rstctl_clr_check_bit((vpeid_e)vpe_id);
+ Idle_Service_Prepare_WAIT();
+
+ while(temptag)
+ {/* Infinite loop */
+ miu_relinquish();//Release Pipeline
+ Idle_Service_Handler_Wait();
+ }
+ }
+ else
+ {
+ EXT_ASSERT(0, vpe_id, domain, 0x2244);/* invalid domain */
+ }
+
+#endif
+}
+
+
+/*************************************************************************
+* FUNCTION
+* idle_create
+*
+* DESCRIPTION
+* This function implements idle entity's create handler.
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+#if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+extern void hrt_idle_task_main(task_entry_struct * task_entry_ptr);
+extern kal_bool hrt_idle_task_init(void);
+#elif defined(__EL2_HRT_EVALUATION__)
+void hrt_eval_idle_task_main(void);
+void hrt_eval_idle_task_init(void);
+#elif defined(__ESL_COSIM_LTE__)
+void el1_adapt_idle_task_main(void);
+void el1_adapt_idle_task_init(void);
+#elif defined(__MASE__)
+extern void mase_adapt_idle_task_main(task_entry_struct *task_entry_ptr);
+#elif defined(MTK_C2K_COSIM)
+extern kal_bool cl1_cosim_idle_task_main(void);
+extern void cl1_cosim_idle_task_init(void);
+extern kal_bool cl1_cosim_idle_task_main1(void);
+extern void cl1_cosim_idle_task_init1(void);
+extern kal_bool cl1_cosim_idle_task_main2(void);
+extern void cl1_cosim_idle_task_init2(void);
+extern kal_bool cl1_cosim_idle_task_main3(void);
+extern void cl1_cosim_idle_task_init3(void);
+extern kal_bool cl1_cosim_idle_task_main4(void);
+extern void cl1_cosim_idle_task_init4(void);
+extern kal_bool cl1_cosim_idle_task_main5(void);
+extern void cl1_cosim_idle_task_init5(void);
+extern kal_bool cl1_cosim_idle_task_main6(void);
+extern void cl1_cosim_idle_task_init6(void);
+extern kal_bool cl1_cosim_idle_task_main7(void);
+extern void cl1_cosim_idle_task_init7(void);
+extern kal_bool cl1_cosim_idle_task_main8(void);
+extern void cl1_cosim_idle_task_init8(void);
+extern kal_bool cl1_cosim_idle_task_main9(void);
+extern void cl1_cosim_idle_task_init9(void);
+extern kal_bool cl1_cosim_idle_task_main10(void);
+extern void cl1_cosim_idle_task_init10(void);
+extern kal_bool cl1_cosim_idle_task_main11(void);
+extern void cl1_cosim_idle_task_init11(void);
+#elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask1( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask2( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask3( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask4( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask5( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask6( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask7( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask8( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask9( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask10( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask11( task_entry_struct * task_entry_ptr );
+#elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+extern void idle_task_xl1r_main(task_entry_struct * task_entry_ptr);
+#endif
+
+#if SYS_MCU_NUM_VPE >= 1
+ /* idle task for VPE 0 */
+ kal_bool idle_create(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main,
+ cl1_cosim_idle_task_init,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__)
+ SPV_IdleTask0,
+ IdleTask_init,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 2
+ /* idle task for VPE 1 */
+ kal_bool idle_create1(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main1,
+ cl1_cosim_idle_task_init1,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask1,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 3
+ /* idle task for VPE 2 */
+ kal_bool idle_create2(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main2,
+ cl1_cosim_idle_task_init2,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask2,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD95__)
+ SPV_IdleTask1,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 4
+ /* idle task for VPE 3 */
+ kal_bool idle_create3(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main3,
+ cl1_cosim_idle_task_init3,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask3,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD97__)
+ SPV_IdleTask1,
+ IdleTask_init,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 5
+ /* idle task for VPE 4 */
+ kal_bool idle_create4(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main4,
+ cl1_cosim_idle_task_init4,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask4,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 6
+ /* idle task for VPE 5 */
+ kal_bool idle_create5(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main5,
+ cl1_cosim_idle_task_init5,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask5,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 7
+ /* idle task for VPE 6 */
+ kal_bool idle_create6(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main6,
+ cl1_cosim_idle_task_init6,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask6,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD97__)
+ SPV_IdleTask2,
+ IdleTask_init,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 8
+ /* idle task for VPE 7 */
+ kal_bool idle_create7(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main7,
+ cl1_cosim_idle_task_init7,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask7,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 9
+ /* idle task for VPE 8 */
+ kal_bool idle_create8(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main8,
+ cl1_cosim_idle_task_init8,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask8,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 10
+ /* idle task for VPE 9 */
+ kal_bool idle_create9(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main9,
+ cl1_cosim_idle_task_init9,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask9,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD97__)
+ SPV_IdleTask3,
+ IdleTask_init,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 11
+ /* idle task for VPE 10 */
+ kal_bool idle_create10(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main10,
+ cl1_cosim_idle_task_init10,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask10,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 12
+ /* idle task for VPE 11 */
+ kal_bool idle_create11(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main11,
+ cl1_cosim_idle_task_init11,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask11,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 13
+ /* idle task for VPE 12 */
+ #error "Unsupported idle task numbers!"
+#endif
+
+#else /* __MTK_TARGET__ */
+
+#endif
+
diff --git a/mcu/driver/sys_drv/init/src/md97/init.c b/mcu/driver/sys_drv/init/src/md97/init.c
new file mode 100644
index 0000000..3553f35
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init.c
@@ -0,0 +1,2751 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+//#include <stdio.h>
+//#include <string.h>
+#include <stdlib.h>
+#include <boot_comm.h>
+
+// kal
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_internal_api.h"
+#include "kal_trace.h"
+#include "reg_base.h"
+#include "system_profiler_public.h"
+#include "multiboot_config.h"
+
+// init
+#include "cp15.h"
+#include "config_hw.h"
+//#include "init.h"
+#include "init_comm.h"
+
+// trace
+#include "system_trc.h" //INT_Trace_Enter, INT_Trace_Exit
+#include "init_trc_api.h" //INT_Trace_Enter, INT_Trace_Exit
+#include "bootarm.h"
+#include "br_time_stamp.h" // TS_END
+
+// system service hw
+#include "pll.h" // INT_SetPLL
+//#include "dsp_loader.h" // DSP_Load
+#include "bus_drv.h" // Bus_Init
+#include "elm.h" // ELM_INIT
+#include "sleepdrv_interface.h" //Sleep_DrvLowPowerMonitorInit
+// system service sw
+#include "stack_buff_pool.h" //stack_resources_init, stack_init_buff_pool_info
+#include "ex_item.h" // ex_memory_dump_init
+#include "mpu.h" // CPU_SET_STACK_MPU_PROTECT, mpu_dump
+#include "ex_mem_manager_public.h" // EMM_Init
+#include "dsp_file_public.h" // DSP_Init, DSP_OutputVersionInfo
+
+
+//misc
+#include "dcl.h" // for peripheral related
+#include "wdt_hw_public.h" //Get_WATCHDOG_BASE, Get_WATCHDOG_RESTART_CMD
+//#include "bl_common.h" // BL_Info_Wrapper_st
+#include "drv_cfgctl.h" //drv_cfgctl_clear_misc, drv_cfgctl_set_misc
+#ifdef __HMU_ENABLE__
+#include "hmu.h" // hif_boot_init
+#endif
+#if defined(__SMART_PHONE_MODEM__)
+#include "ccci.h"
+#endif
+#ifdef __HIF_CCCI_SUPPORT__
+#include "ccci_if.h"
+#endif
+#include "us_timer.h"
+#if !defined(__UBL__) && !defined(__FUE__)
+
+#include "ostd_public.h"
+extern void SleepDrv_Init( void );
+extern void RM_Init( void );
+
+#endif
+#include "DVFS_drv_public.h"
+#include "ptp_public.h"
+#include "RM_public.h"
+
+#ifndef __MAUI_BASIC__
+extern void MML1_TXSYS_Init(void);
+#endif
+
+#include "drv_mdcirq.h"
+#include "drv_gdma.h"
+#include "drv_busmon.h"
+#include "drv_pcmon.h"
+#include "busmpu.h"
+#include "drv_mdap_interface.h"
+#include "mips_ia_utils.h"
+#include "pms.h"
+#include "drv_sfu.h"
+#include "drv_spu.h"
+#include "che_api.h" // for SST_SSF_Init
+#include "tg_hisr.h"
+#include "drv_rstctl.h" // for wdt_enable
+#include "md_boot_check.h"
+#include "scc.h" // for scc_init_dvfs_ctrl()
+/******************************************************
+ * Declaration and definition of global data
+ ******************************************************/
+//WDT
+WDT_CTRL_ENABLE_T wdt_data;
+DCL_HANDLE init_dcl_wdt_handle;
+DCL_HANDLE init_dcl_handle;
+
+#if 0
+/* under construction !*/
+#endif
+__attribute__((section ("MCURW_HWRO_DNC_NOINIT"))) kal_uint32 INT_bootup_entry = 0;
+
+volatile DEFINE_NC_SHARED_VAR_ASSIGN(kal_uint16, _boot_mode,0xFFFF);
+volatile DEFINE_NC_SHARED_VAR_ASSIGN(kal_uint32, g_l_sw_misc_l,0xFFFF);
+volatile DEFINE_NC_SHARED_VAR_ASSIGN(kal_bool, _IsBootForUSBAT,KAL_FALSE);
+
+// <TODO>: fix this LR11 address
+//static const kal_uint32 RAND_GEN_START_ADDR = 0x70002000;
+
+#define INT_CLEAR_RETN_FLAG(_flag) drv_cfgctl_clear_misc()
+#define INT_CLEAR_SET_FLAG(_flag) drv_cfgctl_set_misc(_flag)
+
+/******************************************************
+ * Declaration of function prototype
+ ******************************************************/
+static void INT_SetBootMode(void);
+static void HWDInitialization(void);
+static void systemInitialization(void);
+static void systemInitializeResource(void);
+
+
+/******************************************************
+ * Declaration of import data and function prototype
+ ******************************************************/
+/* Application_Initialize */
+extern boot_mode_type system_boot_mode;
+
+/* Application_Initialize */
+#ifndef __BL_ENABLE__
+void boot_init_clock();
+#endif
+extern kal_uint32 DummyReference();
+extern void Drv_Init_Phase2(void);
+extern void ECT_Init(void);
+extern int mainp(void);
+
+/* HWDInitialization */
+extern void L1SM_Init(void);
+extern void UL1SM_Init(void);
+extern void EL1SM_Init(void);
+extern void NFI_Reset(void);
+extern void Drv_Init_Phase1(void);
+extern void DIGRF_Platform_Init(void);
+
+/* systemInitialization */
+#if !(defined(__NONE_FLASH_EXIST__))
+#if !(defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)) || defined(__NANDFDM_MULTI_INSTANCE__)
+extern void Initialize_FDD_tables(void);
+#endif
+#endif
+extern void kal_hrt_init(void);
+extern void kal_profile_init(void);
+
+/* systemInitializeResource */
+extern kal_uint32 rand_num_seed;
+
+/* INT_VersionNumbers */
+extern kal_char *release_dsp_fw(void);
+extern kal_char *release_dsp_ptch(void);
+extern kal_char *release_verno(void);
+extern kal_char *release_branch(void);
+extern kal_char *release_hw_ver(void);
+extern kal_char *release_flavor(void);
+extern kal_char *release_mcu_platform(void);
+
+/* Misc. */
+extern void SST_InvokEngine(kal_int32, kal_int32);
+
+// for Security
+#ifdef __SECURE_DATA_STORAGE__
+extern kal_int32 SDS_Init(void);
+#endif
+#if defined(__BOOT_CERT__)
+extern kal_uint32 srd_dl_ctrl_check(void);
+extern kal_uint32 srd_dl_ctrl_pre_check(void);
+#endif
+
+/* Generate CORE#_VPE#_TC#_SYS_STACK_PTR and extern SYS_Stack_Pool_CORE#_VPE#_TC# */
+#define STACK_PTR_NAME(C,V,T) CORE ## C ##_VPE ## V ##_TC ## T ##_SYS_STACK_PTR
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ extern kal_uint32 SYS_STACK_NAME(CORE,VPE,TC)[]; \
+ kal_uint32 STACK_PTR_NAME(CORE,VPE,TC) = (((unsigned int)SYS_STACK_NAME(CORE,VPE,TC)) + SIZE - 4);
+
+#include "sys_stack_config.h"
+
+/*************************************************************************
+* FUNCTION
+* INT_SysStack_Disptach
+*
+* DESCRIPTION
+* This function would set all system stack ptrs
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_SetSysStack_GuardPattern
+*
+* DESCRIPTION
+* This function would set STACKEND to system stacks of a core
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_SetSysStack_GuardPattern(kal_uint32 core)
+{
+ volatile kal_uint8 *base;
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ if (CORE == core) { \
+ base = (kal_uint8 *)SYS_STACK_NAME(CORE,VPE,TC); \
+ *(base + 0) = 'S'; \
+ *(base + 1) = 'T'; \
+ *(base + 2) = 'A'; \
+ *(base + 3) = 'C'; \
+ *(base + 4) = 'K'; \
+ *(base + 5) = 'E'; \
+ *(base + 6) = 'N'; \
+ *(base + 7) = 'D'; \
+ }
+
+#include "sys_stack_config.h"
+
+ return;
+}
+
+void INT_GetStackInfo(kal_uint32 * const base, kal_uint32 * const end)
+{
+ const kal_uint32 vpe = kal_get_current_vpe_id() % 3;
+ const kal_uint32 tc = kal_get_current_tc_id();
+ const kal_uint32 core = kal_get_current_core_id();
+
+ *base = *end = 0xFFFFFFFF;
+
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ if (CORE == core && VPE == vpe && TC == tc) { \
+ *base = (unsigned int)SYS_STACK_NAME(CORE,VPE,TC); \
+ *end = STACK_PTR_NAME(CORE,VPE,TC); \
+ return; \
+ }
+
+#include "sys_stack_config.h"
+
+ return;
+}
+
+void INT_GetSysStackInfo(kal_uint32 * const base, kal_uint32 * const end,
+ kal_uint32 core, kal_uint32 vpe, kal_uint32 tc)
+{
+ *base = *end = 0xFFFFFFFF;
+ vpe = vpe%3;
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ if (CORE == core && VPE == vpe && TC == tc) { \
+ *base = (unsigned int)SYS_STACK_NAME(CORE,VPE,TC); \
+ *end = STACK_PTR_NAME(CORE,VPE,TC); \
+ return; \
+ }
+
+#include "sys_stack_config.h"
+
+ return;
+}
+/******************************************************
+ * Definition of functions
+ ******************************************************/
+
+/*__FUE__ compile option is used for FOTA firmware update engine */
+/*add this compile option to avoid compiling other function*/
+#ifndef __FUE__
+/*
+ * NoteXXX:
+ * Please DO NOT place your code in the execution region EMIINITCODE.
+ * Code in this region is used for EMI/PLL initialization, and will be
+ * OVERWRITTEN after INT_InitRegions.
+ */
+/* [BB porting] Make sure the flow to set EMI&SFI and the placement of the code */
+/*************************************************************************
+* FUNCTION
+* INT_SetEMIPLL
+*
+* DESCRIPTION
+* This function dedicates for PLL setting.
+*
+* CALLS
+* Non
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+__attribute__ ((section ("EMIINITCODE"))) void INT_SetEMIPLL(void)
+{
+ custom_setEMI();
+ //INT_SetPLL(PLL_MODE_MAUI);
+}
+
+/* A test procedure for CIRQ driver and UART */
+//#define BASICLOAD_BRINGUP_TEST
+#ifdef BASICLOAD_BRINGUP_TEST
+extern void slt_dbg_print(char* fmt,...);
+void INT_BasicLoad_SimepleTest_GPTCallback(void *para)
+{
+ slt_dbg_print("uart test\r\n");
+ return;
+}
+
+kal_int32 INT_BasicLoad_SimpleTest(kal_uint32 dummy)
+{
+ kal_uint32 cbms_para = 0;
+ DCL_HANDLE handle_cbms;
+ SGPT_CTRL_START_T sgpt_ctrls;
+
+ handle_cbms = DclSGPT_Open(DCL_GPT_CB, 0);
+ sgpt_ctrls.u2Tick = (1);
+ sgpt_ctrls.pfCallback = INT_BasicLoad_SimepleTest_GPTCallback;
+ sgpt_ctrls.vPara = &cbms_para;
+
+ DclSGPT_Control(handle_cbms, SGPT_CMD_START, (DCL_CTRL_DATA_T*)&sgpt_ctrls);
+ return 0;
+}
+#endif
+
+void init_otherCores(void)
+{
+ MD_TOPSM_Init_Other_Cores();
+ return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* init_main
+*
+* DESCRIPTION
+* This function implements project protocol stack, hardware depedent
+* initialization
+*
+* CALLS
+* Initialize()
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+__attribute__((section ("MCURW_HWRO_DNC_NOINIT"))) volatile kal_uint32 app_step_logging = 0;
+void init_main(void)
+{
+#if !defined(_SIMULATION)
+#if !defined(__BL_ENABLE__)
+ //boot_init_clock();
+#endif
+#endif
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ app_step_logging = 0;
+ /* set-up locale for trace */
+ //INT_Trace_Enter(INIT_CLIB1);
+ INT_TRC_C(LABEL_CLIB_BASE_INIT);
+ clib_basic_init();
+ //INT_Trace_Exit(INIT_CLIB1);
+ app_step_logging = 1;
+
+#ifdef __HIF_CCCI_SUPPORT__
+ /* Call HIF initialize and do phase-1 handshake with AP */
+ //INT_Trace_Enter(INIT_CCCIHS1);
+ INT_TRC_C(LABEL_CCCI_HW_INIT);
+ lte_ccci_hw_init();
+ INT_TRC_C(LABEL_CCCI_HS1);
+ lte_ccci_init_handshake_phase1();
+ //INT_Trace_Exit(INIT_CCCIHS1);
+#endif
+
+ /* Enable EMM Feature */
+ INT_TRC_C(LABEL_EMM_INIT);
+#if !defined(__ESL_MASE_GEN97__)
+ EMM_Init();
+#endif /* !__ESL_MASE_GEN97__ */
+
+#if !defined(__ESL_MASE_GEN97__)
+ /* Set INT_BootMode config done flag to untrap L1Core */
+ INT_Trace_Enter(INIT_BOOTMODE);
+ INT_SetBootMode();
+ INT_Trace_Exit(INIT_BOOTMODE);
+#endif /* !__ESL_MASE_GEN97__ */
+
+ INT_Trace_Enter(INIT_BOOTMODE_CHECK);
+ check_md_boot_mode();
+ INT_Trace_Exit(INIT_BOOTMODE_CHECK);
+
+ /* Initialize system specific module */
+ INT_Trace_Enter(INIT_SYSTEMINIT);
+ systemInitialization();
+ INT_Trace_Exit(INIT_SYSTEMINIT);
+ app_step_logging = 2;
+
+#if !defined(_SIMULATION)
+ /* Initialize ECT in the begging of Application_Initialize */
+ INT_Trace_Enter(INIT_ECT);
+ ECT_Init();
+ INT_Trace_Exit(INIT_ECT);
+#endif
+
+
+ /* Initialize HW module */
+ INT_Trace_Enter(INIT_HWDINIT);
+ HWDInitialization();
+ INT_Trace_Exit(INIT_HWDINIT);
+
+ /* Disable Watch dog */
+ INT_Trace_Enter(INIT_DISABLE_WDT);
+ wdt_enable(KAL_FALSE);
+ INT_Trace_Exit(INIT_DISABLE_WDT);
+
+#if !defined(_SIMULATION) && !defined(__ESL_MASE__)
+ /* Note: Not all HW modules are avaiable in the Co-SIM envrionment */
+ /* Note: Need to bypass DRV INIT in Co-SIM (via _SIMULATION) */
+ INT_Trace_Enter(INIT_DRV2);
+ Drv_Init_Phase2();
+ INT_Trace_Exit(INIT_DRV2);
+#endif
+
+ /* Resource initialization */
+ INT_Trace_Enter(INIT_RESINIT);
+ systemInitializeResource();
+ INT_Trace_Exit(INIT_RESINIT);
+
+ /* Initialize heap for c library usage */
+ INT_Trace_Enter(INIT_CLIB2);
+ clib_init();
+ INT_Trace_Exit(INIT_CLIB2);
+ app_step_logging = 3;
+
+ /* Initialize specific sss features */
+ INT_Trace_Enter(INIT_SSF);
+ SST_SSF_Init();
+ INT_Trace_Exit(INIT_SSF);
+
+ INT_Trace_Enter(INIT_DSPINIT);
+#if !defined(__TCM_ONLY_LOAD__)
+ DSP_Init();
+#endif
+ INT_Trace_Exit(INIT_DSPINIT);
+ app_step_logging = 4;
+
+#if defined (__LP_SCHEDULE_ENABLE__)
+ /* Need to be called after spinlock init and gpt init(drv_init_phase1) */
+ INT_Trace_Enter(INIT_TG_HISR_INIT);
+ tg_hisr_init();
+ INT_Trace_Exit(INIT_TG_HISR_INIT);
+#endif
+
+ /* MAUI protocol stack entry routine */
+ INT_Trace_Enter(INIT_MAINP);
+ mainp();
+ INT_Trace_Exit(INIT_MAINP);
+ app_step_logging = 5;
+
+#if 0
+/* under construction !*/
+#endif
+
+ /* enable SWLA by default for easy debug */
+#if !defined(_SIMULATION) || defined(__ESL_MASE__)
+ INT_Trace_Enter(INIT_SLA);
+ SysProfiler_Init();
+#if defined(DEBUG_SWLA)
+ SysProfiler_Start(); // enable SWLA by default for easy debug
+#endif
+ INT_Trace_Exit(INIT_SLA);
+#endif
+
+
+#ifdef __MULTI_BOOT__
+ if ( system_boot_mode!=FACTORY_BOOT )
+#endif
+ {
+ INT_Trace_Enter(INIT_ENABLE_WDT);
+#if !defined(__ESL_MASE_GEN97__)
+ /* Enable watch dog */
+ wdt_enable(KAL_TRUE);
+#endif /* !__ESL_MASE_GEN97__ */
+ }
+
+#ifdef __HMU_ENABLE__
+ INT_Trace_Enter(INIT_HIFBOOT);
+ hif_boot_init();
+ INT_Trace_Exit(INIT_HIFBOOT);
+#endif
+
+ INT_Trace_Enter(INIT_SLP_LPM_INIT);
+ Sleep_DrvLowPowerMonitorInit();
+ INT_Trace_Exit(INIT_SLP_LPM_INIT);
+
+#ifdef __HIF_CCCI_SUPPORT__
+ /* Do phase-2 handshake with AP */
+ INT_Trace_Enter(INIT_CCCIHS2);
+ lte_ccci_init_handshake_phase2(SHARED_VAR(_boot_mode));
+ lte_ccci_hw_init_phase2();
+ INT_Trace_Exit(INIT_CCCIHS2);
+ INT_Trace_Enter(INIT_CCCIHS2_DONE);
+ INT_Trace_Exit(INIT_CCCIHS2_DONE);
+#endif
+
+ INT_backupBootLogs();
+
+#ifdef BASICLOAD_BRINGUP_TEST
+ INT_BasicLoad_SimpleTest(0);
+#endif
+ app_step_logging = 0xFF;
+
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_SetBootMode
+*
+* DESCRIPTION
+* This function sets global variables related to boot mode
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+* _boot_mode
+* g_l_sw_misc_l
+* _IsBootForUSBAT
+*
+*************************************************************************/
+
+static void INT_SetBootMode(void)
+{
+ /* for SiP TDD SLT, force META bootup */
+#if defined(__TDDSYS_SLT_FACTORY_BOOT__) || defined(__LTE_PHY_TEST__)
+ INT_SetMetaMode();
+#endif
+
+ /* Multi-Boot */
+#ifdef __MULTI_BOOT__
+
+ SHARED_VAR(_boot_mode) = 0x1 & *(volatile kal_uint16 *)BOOT_CONFIG_ADDR;
+
+ SHARED_VAR(g_l_sw_misc_l) = *(volatile kal_uint16 *)BOOT_CONFIG_ADDR;
+
+ if (0x4 & *(volatile kal_uint16 *)BOOT_CONFIG_ADDR)
+ {
+ SHARED_VAR(_IsBootForUSBAT) = KAL_TRUE;
+ }
+
+#if !defined(L1_NOT_PRESENT) && !defined(ATEST_DRV_ENVIRON)
+ /* Set mode for L1 usage */
+ //pcore doesn't need L1D_SetInitMode.
+ //L1D_SetInitMode(_boot_mode);
+#endif /* !L1_NOT_PRESENT && !ATEST_DRV_ENVIRON */
+
+#endif /* __MULTI_BOOT__ */
+
+ // Seamless META feature: always normal boot
+ SHARED_VAR(_boot_mode) = 0x0;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* systemInitialization
+*
+* DESCRIPTION
+* This function implements the system specific initialization, including
+* interrupt central controller, FDD and KAL.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+volatile kal_uint32 app_bypass = 0;
+static void systemInitialization(void)
+{
+ app_step_logging = 0x11;
+ if (!app_bypass){
+ /* initialize CIRQ interrupt controller */
+ initINTR();
+ app_step_logging = 0x12;
+ /* initialize VPE interrupt setting */
+ initVPEIRQ();
+ }
+
+#if !(defined(__NONE_FLASH_EXIST__))
+#if !(defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)) || defined(__NANDFDM_MULTI_INSTANCE__)
+ Initialize_FDD_tables();
+ app_step_logging = 0x13;
+#endif /* !(_NAND_FLASH_BOOTING_ || __EMMC_BOOTING__) || __NANDFDM_MULTI_INSTANCE__ */
+#endif /* !(__NONE_FLASH_EXIST__) */
+
+ /* Register display handler */
+ kal_register_print_string_function((kal_print_string_func_ptr)stack_print);
+ app_step_logging = 0x14;
+ app_step_logging = 0x15;
+
+ /* Initialize HRT workqueue */
+ kal_hrt_init();
+ app_step_logging = 0x17;
+ /* Initializing the Buffer Pool Information */
+ stack_init_buff_pool_info();
+ app_step_logging = 0x18;
+ /* Create buffer pools */
+ stack_resources_init();
+ app_step_logging = 0x19;
+ /* Initialize KAL resources */
+ kal_initialize();
+ app_step_logging = 0x20;
+ /* Initialize KAL CPU usage profiling */
+ kal_profile_init();
+ app_step_logging = 0x21;
+ /* Initialize memory dump switch */
+ ex_memory_dump_init();
+ app_step_logging = 0x22;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* HWDInitialization
+*
+* DESCRIPTION
+* This function implements hardware dependent initialization and
+* management
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+static void HWDInitialization(void)
+{
+
+#if !defined(_SIMULATION) && !defined(__ESL_MASE__)
+ //INT_SetChipReg();
+
+ INT_Trace_Enter(INIT_PDAMON);
+ drv_pdamon_init();
+ INT_Trace_Exit(INIT_PDAMON);
+
+ INT_Trace_Enter(INIT_INIT_MISC);
+ INT_Init_Misc();
+ INT_Trace_Exit(INIT_INIT_MISC);
+
+ INT_Trace_Enter(INIT_BUS);
+ BusDrv_Init();
+ INT_Trace_Exit(INIT_BUS);
+
+ INT_Trace_Enter(INIT_ELM);
+ ELM_INIT();
+ INT_Trace_Exit(INIT_ELM);
+
+ INT_Trace_Enter(INIT_USC);
+ USC_Start();
+ INT_Trace_Exit(INIT_USC);
+
+ INT_Trace_Enter(INIT_PMS);
+ PMS_Init();
+ INT_Trace_Exit(INIT_PMS);
+
+ INT_Trace_Enter(INIT_RM);
+ RM_Init(); // before OSTD_Init() and before 2G and 3G SMM's init() function
+ INT_Trace_Exit(INIT_RM);
+
+ INT_Trace_Enter(INIT_OSTD);
+ OSTD_Init();
+ INT_Trace_Exit(INIT_OSTD);
+
+ INT_Trace_Enter(INIT_GDMA);
+ DRV_GDMA_INITIALIZATION();
+ INT_Trace_Exit(INIT_GDMA);
+
+
+#ifdef MTK_SLEEP_ENABLE
+#ifndef ATEST_DRV_ENABLE
+ /* Added by Anthony Chin 03/18/2002. For sleep mode management. */
+
+#ifdef __GSM_RAT__
+ INT_Trace_Enter(INIT_L1SM);
+ L1SM_Init();
+ INT_Trace_Exit(INIT_L1SM);
+#endif /* __GSM_RAT__ */
+
+#ifdef __MTK_UL1_FDD__
+ INT_Trace_Enter(INIT_UL1SM);
+ UL1SM_Init();
+ INT_Trace_Exit(INIT_UL1SM);
+#endif /* __MTK_UL1_FDD__ */
+
+#if defined(__LTE_RAT__) && defined(__EL1_ENABLE__)
+ INT_Trace_Enter(INIT_EL1SM);
+ EL1SM_Init();
+ INT_Trace_Exit(INIT_EL1SM);
+#endif /* __LTE_RAT__ && __EL1_ENABLE__ */
+
+#endif /* ATEST_DRV_ENABLE */
+#endif /* MTK_SLEEP_ENABLE */
+
+
+
+
+ INT_Trace_Enter(INIT_OSTD);
+#ifdef __HAPS_FPGA_CLK_ADJUST__
+ OSTD_SetFrmDur(KAL_MICROSECS_PER_TICK_REAL);
+#else
+ OSTD_SetFrmDur(KAL_MICROSECS_PER_TICK);
+#endif
+ OSTD_EnOST(KAL_TRUE);
+ INT_Trace_Exit(INIT_OSTD);
+
+
+#if 1 //wait for driver ready
+ INT_Trace_Enter(INIT_PTP);
+ ptp_init();
+ INT_Trace_Exit(INIT_PTP);
+#endif //wait for driver ready
+#if 0
+#if defined(IDMA_DOWNLOAD) && !defined(ATEST_DRV_ENVIRON)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* IDMA_DOWNLOAD && !ATEST_DRV_ENVIRON */
+#endif
+
+
+#ifdef NAND_SUPPORT
+ INT_Trace_Enter(INIT_NFIRESET);
+ NFI_Reset();
+ INT_Trace_Exit(INIT_NFIRESET);
+#endif /* NAND_SUPPORT */
+
+ /* Called before Drv_Init_Phase1() because AMIF user init is in Drv_Init_Phase1() */
+ INT_Trace_Enter(INIT_AMIF);
+ Drv_MDAPInterface_Init();
+ INT_Trace_Exit(INIT_AMIF);
+
+ INT_Trace_Enter(INIT_DRV1);
+ Drv_Init_Phase1();
+ INT_Trace_Exit(INIT_DRV1);
+
+ //Called after ccci init
+ INT_Trace_Enter(INIT_DIGRF);
+ DIGRF_Platform_Init();
+ INT_Trace_Exit(INIT_DIGRF);
+
+#if !(defined(__ESL_ENABLE__) || defined(__SPV_UFPS_LOAD__))
+ INT_Trace_Enter(INIT_DVFS);
+ DVFS_init();
+ INT_Trace_Exit(INIT_DVFS);
+#endif
+ // SIB driver initialize, need execute after DVFS_init()
+ INT_Trace_Enter(INIT_SIB);
+ scc_init_dvfs_ctrl();
+ INT_Trace_Exit(INIT_SIB);
+
+ #ifndef __MAUI_BASIC__
+ /* MML1 H/W TXSYS initial */
+ INT_Trace_Enter(INIT_MML1_TXSYS);
+ MML1_TXSYS_Init();
+ INT_Trace_Exit(INIT_MML1_TXSYS);
+ #endif
+
+#if 0
+/* under construction !*/
+#endif
+
+#if 0//(__ZIMAGE_SUPPORT__)
+/* under construction !*/
+#endif /* __ZIMAGE_SUPPORT__ */
+
+#if 0
+#if defined(__DCM_WITH_COMPRESSION__) || defined(__DYNAMIC_CODE_MANAGER__)
+/* under construction !*/
+#endif
+#endif
+#if 0 //wait for driver ready
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //wait for driver ready
+ INT_Trace_Enter(INIT_RMPU_MD_INIT);
+ rmpu_md_init();
+ INT_Trace_Exit(INIT_RMPU_MD_INIT);
+
+ INT_Trace_Enter(INIT_BUSMON);
+ busmon_init();
+ INT_Trace_Exit(INIT_BUSMON);
+
+ INT_Trace_Enter(INIT_SFU_INIT);
+ drv_sfu_wrap_init();
+ INT_Trace_Exit(INIT_SFU_INIT);
+
+ INT_Trace_Enter(INIT_SPU_INIT);
+ drv_spu_init();
+ INT_Trace_Exit(INIT_SPU_INIT);
+
+#else /*!defined(_SIMULATION) && !defined(__ESL_MASE__)*/
+
+#if defined(_SIMULATION)
+
+ INT_Trace_Enter(INIT_RM);
+ MODEM_TOPSM_ForceOnAllResource();
+ INT_Trace_Exit(INIT_RM);
+
+ INT_Trace_Enter(INIT_DIGRF);
+ DIGRF_Platform_Init();
+ INT_Trace_Exit(INIT_DIGRF);
+
+
+#endif /*_SIMULATION*/
+#endif /*!defined(_SIMULATION) && !defined(__ESL_MASE__)*/
+
+ //needed for ESL platform
+#if defined(__ESL_MASE_GEN97__) && defined(__MTK_TARGET__)
+ INT_Trace_Enter(INIT_DRV1);
+ Drv_Init_Phase1();
+ INT_Trace_Exit(INIT_DRV1);
+#endif /* __ESL_MASE_GEN97__ && __MTK_TARGET__ */
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_Get_PowerOn_Type
+*
+* DESCRIPTION
+* This function used to return the power on reason
+*
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* systemInitializeResource
+*
+* DESCRIPTION
+* This function aims resource initialization, including audio, image,
+* font etc.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void systemInitializeResource(void)
+{
+#if defined(__MTK_TARGET__) && defined (__HIF_CCCI_SUPPORT__)
+ kal_uint32 rand_seed_num_from_ap;
+
+ //If AP exist, MD will get random seed from AP through CCCI and then override the rand_num_seed
+ if (CCCI_MISC_INFO_SUPPORT != ccci_misc_data_feature_support(CCMSG_ID_MISCINFO_RANDOM_SEED_NUM, 4, &rand_seed_num_from_ap))
+ {
+ INT_Trace_Enter(INIT_GETRANDOMSEED_INTRAM);
+ }
+ else
+ {
+ rand_num_seed = rand_seed_num_from_ap;
+ INT_Trace_Enter(INIT_GETRANDOMSEED_AP);
+ }
+#else
+ INT_Trace_Enter(INIT_GETRANDOMSEED_INTRAM);
+#endif
+ srand(rand_num_seed);
+}
+
+/*************************************************************************
+* FUNCTION
+* INT_Config
+*
+* DESCRIPTION
+* This function implements adjusting Memory Block 0 (EMI_CON0) Wait
+* State's setting
+*
+* CALLS
+* INT_Decrypt, INT_SetPLL, INT_SetChipReg
+*
+* PARAMETERS
+*
+* RETURNS
+* the seed value for random number
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_Config(void)
+{
+#if !defined(_SIMULATION)
+
+#if 0
+#if defined(__MULTI_BOOT__) && !defined(L1D_TEST_COSIM)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(MCU_26M)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(MCU_52M)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* __MULTI_BOOT__ & !L1D_TEST_COSIM */
+#endif
+ INT_SetEMIPLL();
+
+#endif
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_BootMode
+*
+* DESCRIPTION
+* This function implements to return boot mode. Remember the routine muse
+* be called after Application_Initialize.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_uint16 INT_BootMode(void)
+{
+ /* Seamless META feature:
+ a. Always return normal boot
+ b. Assert when being used after scheduler */
+ if (KAL_FALSE == kal_query_systemInit())
+ {
+ ASSERT(0);
+ }
+ return (kal_uint16)MTK_NORMAL_MODE;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_SetMetaMode
+*
+* DESCRIPTION
+* This function implements to set hw register to enable meta mode.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_SetMetaMode(void)
+{
+ *(volatile kal_uint16 *)BOOT_CONFIG_ADDR |= 0x0001;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_InvokeSSTEngine
+*
+*************************************************************************/
+#define _SST_FUNCTION_ENABLE_
+void INT_InvokeSSTEngine(kal_int32 err_code, kal_int32 os_err_code)
+{
+#ifdef _SST_FUNCTION_ENABLE_
+ /* _SST_FUNCTION_ENABLE_ should be locally defined such that
+ * custom release will remove these code
+ */
+ SST_InvokEngine(err_code, os_err_code);
+#endif
+ return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* release_bb_chip
+*
+* DESCRIPTION
+* This function returns the version number of the baseband chip
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_char* release_bb_chip(void)
+{
+ return release_mcu_platform();
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_VersionNumbers
+*
+* DESCRIPTION
+* This function returns the version number of the followings
+* 1. Chip version
+* 2. DSP version
+* 3. DSP patch version
+* 4. MCU software version
+* 5. Baseband board version
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_VersionNumbers(version_struct * ptr_version)
+{
+ ptr_version->bb_chip = release_bb_chip();
+#if !defined(__DSP_FCORE4__)
+ ptr_version->dsp_fw = release_dsp_fw();
+ ptr_version->dsp_ptch = release_dsp_ptch();
+#else
+ // Note: use empty string temporarily, need to discuss how we should fill these fields in FCore case
+ ptr_version->dsp_fw = " ";
+ ptr_version->dsp_ptch = " ";
+#endif //!__DSP_FCORE4__
+ ptr_version->mcu_sw = release_verno();
+ ptr_version->mcu_sw_branch = release_branch();
+ ptr_version->bb_board = release_hw_ver();
+ ptr_version->mcu_sw_flavor = release_flavor();
+ return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_LteDspVersionNumbers
+*
+* DESCRIPTION
+* This function returns the version number of LTE DSP version
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_bool INT_LteDspVersionNumbers(lte_dsp_version_struct * ptr_version)
+{
+#if defined(__LTE_RAT__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ {
+ ptr_version->dsp_fw = " ";
+ ptr_version->dsp_btime = " ";
+ return KAL_FALSE;
+ }
+
+#else
+ ptr_version->dsp_fw = " ";
+ ptr_version->dsp_btime = " ";
+
+ return KAL_FALSE;
+#endif
+}
+
+
+#if 1
+/*************************************************************************
+* FUNCTION
+* INT_SetCmdToSys
+*
+* DESCRIPTION
+* This function provide API for user to set necessary command to system
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+void INT_SetCmdToSys(INIT_SYSCMD_CODE cmd_val)
+{
+#if !defined(__SMART_PHONE_MODEM__) && !defined(__MODEM_ONLY__) /* 2012/07/13: Currently, only MT6280 is defined with __SMART_PHONE_MODEM__ */
+
+ // RETN_REG[2]: 1: Enter USBDL
+ // RETN_REG[1]: 1: BL download, 0: BROM download
+
+ /* Secure mode or BL support USB DL */
+ // Normal mode: enter bootloader download after reboot
+ // Rescue mode: enter BROM download after reboot
+
+ /* Others */
+ // Enter BROM download after reboot under either mode
+
+ INT_CLEAR_RETN_FLAG(0x06); // 3'b110
+
+ switch (cmd_val)
+ {
+#if defined(__MTK_SECURE_PLATFORM__) || defined(__USB_DOWNLOAD__)
+ case SYS_CMD_SET_BL_DL:
+ INT_CLEAR_SET_FLAG(0x06); // 3'b110
+ break;
+
+ case SYS_CMD_SET_BROM_DL:
+ INT_CLEAR_SET_FLAG(0x04); // 3'b100
+ break;
+#else /* __MTK_SECURE_PLATFORM__ || __USB_DOWNLOAD__ */
+ /* if BL does not support USB DL, enter BROM download after reboot under either mode */
+ case SYS_CMD_SET_BROM_DL:
+ case SYS_CMD_SET_BL_DL: /* this is actually BROM download */
+ INT_CLEAR_SET_FLAG(0x04); // 3'b100
+ break;
+#endif /* __MTK_SECURE_PLATFORM__ || __USB_DOWNLOAD__ */
+
+ // do not enter download mode
+ case SYS_CMD_CLR_DL_FLAG:
+ break;
+
+ default:
+ ASSERT(0);
+ break;
+ }
+
+#endif /* __SMART_PHONE_MODEM__ */
+
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetSysStaByCmd
+*
+* DESCRIPTION
+* This function provided for user to query the status of system
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+kal_uint32 INT_GetSysStaByCmd(INIT_SYSCMD_CODE cmd_val, void *data_p)
+{
+#if !defined(__SMART_PHONE_MODEM__)
+
+ switch (cmd_val)
+ {
+ case CHK_USB_META_WO_BAT:
+ if (SHARED_VAR(g_l_sw_misc_l) & (0x1 << 3))
+ {
+ return KAL_TRUE;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+
+ case CHK_FAST_META:
+
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+#else
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+ {
+ return KAL_FALSE;
+ }
+
+ case SYS_CMD_BL_LOGO_DISPLAYED:
+
+#if defined(__FAST_LOGO__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif /* __FAST_LOGO__ */
+ {
+ return KAL_FALSE;
+ }
+
+ case SYS_CMD_GET_PWN_STA:
+
+
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+ return KAL_FALSE;
+
+#else
+
+#if 0
+/* under construction !*/
+#endif
+#endif
+
+ case SYS_CMD_GET_EMI_PARAM:
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+ return KAL_FALSE;
+
+#else
+
+#if 0
+/* under construction !*/
+#endif
+ return KAL_TRUE;
+#endif
+
+ break;
+
+ case SYS_CMD_BL_BROM_CMD_MODE_DISABLED:
+#if defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+ {
+ return KAL_FALSE;
+ }
+ default:
+ ASSERT(0);
+ break;
+ }
+
+
+#endif /* __SMART_PHONE_MODEM__ */
+
+ return KAL_FALSE;
+}
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_GetMetaModeSrc
+*
+* DESCRIPTION
+* Get Random Seed
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+MODE_ENTRY_SRC INT_GetMetaModeSrc(void)
+{
+ MODE_ENTRY_SRC state = E_BROM;
+
+
+ return state;
+
+
+
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetRandomSeed
+*
+* DESCRIPTION
+* Get Random Seed -- maybed passed from bootloader or use memory region
+* to create
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+#if defined(__SSDVT_TEST__)
+/* under construction !*/
+#else /* __SSDVT_TEST__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef __TIME_STAMP__
+/* under construction !*/
+#if 0
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+#endif
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#if defined(_SIMULATION)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* _SIMULATION */
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* !(__BL_ENABLE__ || _NAND_FLASH_BOOTING_ || __NOR_FLASH_BOOTING__) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* !(__BL_ENABLE__ || _NAND_FLASH_BOOTING_ || __NOR_FLASH_BOOTING__) */
+/* under construction !*/
+#endif /* _SIMULATION */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __SSDVT_TEST__ */
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_IsBootForUSBAT
+*
+* DESCRIPTION
+* This function is used to for user to query if USBAT is enabled
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+kal_bool INT_IsBootForUSBAT(void)
+{
+ return SHARED_VAR(_IsBootForUSBAT);
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetBromBlSyncType
+*
+* DESCRIPTION
+* For DHL, it needs to know the channel used to sync with tool in bootrom
+* or boorloader
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* The sync channel used by bootrom or bootloader
+*
+*************************************************************************/
+ser_chl_t INT_GetBromBlSyncType(void)
+{
+#ifdef __BL_ENABLE__
+#if 0
+/* under construction !*/
+#endif
+#else
+ //For internal phone project, it does not have bootloader
+ //Always return CHL_CCCI
+ return CHL_CCCI;
+#endif /*__BL_ENABLE__*/
+}
+
+__attribute__((__section__("NONCACHEDRW"))) INIT_STAGE INT_init_stage = E_DEFAULT;
+INIT_STAGE INT_QueryInitStage(void)
+{
+ return INT_init_stage;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_PollingShareVariable
+*
+* DESCRIPTION
+*
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+*************************************************************************/
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if ( defined(__FS_SYSDRV_ON_NAND__) || defined( _NAND_FLASH_BOOTING_) )
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __FS_SYSDRV_ON_NAND__ || _NAND_FLASH_BOOTING_ */
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* _NAND_FLASH_BOOTING_ || __EMMC_BOOTING__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if (defined(_NAND_FLASH_BOOTING_) && !defined(__NFB_SINGLE_ROM__)) || defined(__EMMC_BOOTING__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* _NAND_FLASH_BOOTING_ || __EMMC_BOOTING__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM9_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM9_MMU__ */
+/* under construction !*/
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef __TIME_STAMP__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef __TIME_STAMP__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__SV5_ENABLED__) || defined(__SV5X_ENABLED__) /* __SV5_ENABLED__ || __SV5X_ENABLED__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* __SV5_ENABLED__ || __SV5X_ENABLED__ */
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* !(__BL_ENABLE__ || _NAND_FLASH_BOOTING_ || __NOR_FLASH_BOOTING__ || __EMMC_BOOTING__) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* _NAND_FLASH_BOOTING_ */
+/* under construction !*/
+#endif /* __SV5_ENABLED__ || __SV5X_ENABLED__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if defined __MD97__ && !defined MT6297_IA
+#define INIT_RO_NOINIT_DATA __attribute__((section("NONCACHED_RODATA"))) __attribute__((noinline))
+INIT_RO_NOINIT_DATA kal_uint32 domain_config[12] = {0, 1, 1, 0, 1, 2, 0, 1, 2, 0, 1, 2};
+void Set_VPE_Domain_Type()
+{
+
+ kal_uint32 domain_type;
+ kal_uint32 cpu_id = kal_get_current_vpe_id();
+ /* KScratch4 bits 1:0 are used to keep VPE domain type identifier for quick
+ look-up for each VPE */
+ domain_type = domain_config[cpu_id];
+
+ __asm__ __volatile__(
+ "mfc0 $a0, $31, 5 \n" \
+ "ins $a0, %0, 0, 2 \n" \
+ "mtc0 $a0, $31, 5 \n" \
+ "ehb \n" \
+ : \
+ :"d" (domain_type) \
+ :"$a0"
+ );
+
+}
+#endif /* defined __MD97__ && !defined MT6297_IA */
+
+#define PROFILE_CNT 100
+#define INIT_MCURW_NOINIT_DATA __attribute__((section("MCURW_HWRO_DNC_NOINIT"))) __attribute__((noinline))
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 EMM_Init_Flag = 0;
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 EMM_HS1_BootTrace_Addr = 0;
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 BootTrace_Profile_Data[16][PROFILE_CNT][2] = {0};
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 BootTrace_Profile_Idx[16] = {0};
+
+#include <boot_comm.h>
+#include <sst_defs.h>
+
+#if defined(__ESL_MASE__)
+kal_uint32 Boot_Trace_PreInit(){
+ EMM_Init_Flag = 0;
+ return 0;
+}
+kal_uint32 INC_TRC_PROFILE(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ return 0;
+}
+
+void Set_HS1_Boot_Trace(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ return ;
+}
+
+
+#else
+kal_uint32 Boot_Trace_PreInit(){
+ kal_uint32 i = 0;
+ EMM_Init_Flag = 0;
+ for(i=0 ; i<16; i++)
+ {
+ BootTrace_Profile_Idx[i] = 0;
+ }
+ *(volatile kal_uint32*)(MDCCIF_BOOTTRC_DATA)=0x56552552;
+ return 0;
+}
+kal_uint32 INC_TRC_PROFILE(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ kal_uint32 cpu_id = kal_get_current_vpe_id();
+ BootTrace_Profile_Data[cpu_id][BootTrace_Profile_Idx[cpu_id]][0]=traceData;
+ BootTrace_Profile_Data[cpu_id][BootTrace_Profile_Idx[cpu_id]][1]=traceTime;
+ BootTrace_Profile_Idx[cpu_id] +=1;
+ if(BootTrace_Profile_Idx[cpu_id] == PROFILE_CNT)
+ BootTrace_Profile_Idx[cpu_id] = 0;
+
+ return 0;
+}
+void Set_HS1_Boot_Trace(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ kal_uint32 cpu_id = kal_get_current_vpe_id();
+ kal_uint32 HS1Time = ust_get_current_time();
+
+ if(EMM_Init_Flag == 0)
+ {
+ /*Ongoing*/
+ /*Check EMM address in CCIF SRAM*/
+ /*1: dispatch 2:not dispatch*/
+ if(*(volatile kal_uint32*)(g_EMM_MAIN_BUFF_MAGIC_ADDR) == g_EMM_MAIN_BUFF_MAGIC)
+ {
+ EMM_Init_Flag = 1;
+ EMM_HS1_BootTrace_Addr = *(volatile kal_uint32*)(g_EMM_MAIN_BUFF_ADDR_PTR) + HS1_BOOT_TRACE_OFFSET;
+ *(volatile kal_uint32*)(EMM_HS1_BootTrace_Addr)=0x56552552;
+ }
+ else
+ {
+ EMM_Init_Flag = 2;
+ }
+ }
+ else if(EMM_Init_Flag == 1)
+ { //write to CCIF SRAM
+ *(volatile kal_uint32*)(MDCCIF_BOOTTRC_DATA + (cpu_id+1)*4 )=traceData;
+ //Write to EMM
+ *(volatile kal_uint32*)(EMM_HS1_BootTrace_Addr + (cpu_id+1)*8 )=traceData;
+ *(volatile kal_uint32*)(EMM_HS1_BootTrace_Addr + (cpu_id+1)*8 +4)=HS1Time;
+
+ }
+ else
+ {
+ *(volatile kal_uint32*)(MDCCIF_BOOTTRC_DATA + (cpu_id+1)*4 )=traceData;
+ }
+#if defined(__PROFILE_INIT__)
+ //write log for profiling
+ INC_TRC_PROFILE(traceData,traceTime);
+
+#endif
+ return;
+}
+#endif //defined(__ESL_MASE__)
+
+kal_bool INT_hasEMMAddress(void)
+{
+#if 1
+ kal_bool hasEMM = (EMM_Init_Flag == 1);
+ kal_uint32 emmSize = 0;
+
+ if(hasEMM)
+ {
+ emmSize = (*(kal_uint32 volatile*)(g_EMM_MAIN_BUFF_SIZE_PTR));
+ if (emmSize < (BOOTUP_TRC_OFFSET + (VPE_BOOTUP_TRC_SIZE * SYS_MCU_NUM_VPE)) || emmSize > 0x10000000)
+ {
+ EXT_ASSERT(0, emmSize, (BOOTUP_TRC_OFFSET + (VPE_BOOTUP_TRC_SIZE * SYS_MCU_NUM_VPE)), 0x10000000);
+ }
+ }
+
+ return hasEMM;
+#else
+/* under construction !*/
+#endif
+}
+
+#endif /*__FUE__*/
diff --git a/mcu/driver/sys_drv/init/src/md97/init_cm.S b/mcu/driver/sys_drv/init/src/md97/init_cm.S
new file mode 100644
index 0000000..935e8f0
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_cm.S
@@ -0,0 +1,119 @@
+/*
+ * init_cm.S
+ *
+ * initializatoin of the Coherency Manager
+ */
+
+#include <boot.h>
+#include <cps.h>
+#include <l2cache_def.h>
+
+#define GCR_CUSTOM_BASE (0x60)
+#define GCR_L2_ONLY_SYNC_BASE (0x70)
+
+.set noreorder // Don't allow the assembler to reorder instructions.
+.set noat // Don't allow the assembler to use r1(at) for synthetic instr
+.set nomt
+.set nodsp
+
+/**************************************************************************************/
+
+.macro set_region gcr_reg, base_off, mask_off, base_reg, mask_reg
+ sw \base_reg, \base_off(\gcr_reg);
+ sw \mask_reg, \mask_off(\gcr_reg);
+.endm
+
+.macro cfg_region gcr_reg, base_off, mask_off, reg, addr, addr_msk, target, cca_ov_en, cca_ov_val, drop_l2
+ lui \reg, %hi(\addr);
+ sw \reg, \base_off(\gcr_reg);
+ li \reg, ( ((\addr_msk & 0xffff) <<16) |\
+ ((\cca_ov_val & 0x7) <<5) |\
+ ((\cca_ov_en & 0x1) <<4) |\
+ ((\drop_l2 & 0x1) <<2) |\
+ ((\target & 0x3) <<0) );
+ sw \reg, \mask_off(\gcr_reg);
+.endm
+
+.macro init_cm_macro
+
+#if defined(no_cpc)
+ beqzc r11_is_cps, 1f // skip if not a CPS or CM register verification failed.
+#endif
+
+ li r22_gcr_addr, GCR_CONFIG_ADDR // Use r22 ($s6) for GCR Base Address
+
+ // Allow each core access to the CM registers (they should only access their local registers.)
+ lw $a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
+ ext r19_more_cores, $a0, PCORES, PCORES_S // Extract PCORES
+ li $a0, 2 // Start building mask for cores in this cps
+ sll $a0, $a0, r19_more_cores
+ addiu $a0, -1 // Complete mask.
+ sw $a0, GCR_ACCESS(r22_gcr_addr) // GCR_ACCESS
+
+ // Force Disabled All Regions
+ lui $a0, %hi(0xffff0000)
+ set_region r22_gcr_addr, GCR_REG0_BASE, GCR_REG0_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG1_BASE, GCR_REG1_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG2_BASE, GCR_REG2_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG3_BASE, GCR_REG3_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG4_BASE, GCR_REG4_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG5_BASE, GCR_REG5_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG6_BASE, GCR_REG6_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG7_BASE, GCR_REG7_MASK, $a0, $a0
+
+ // Config MMIO Regions
+ cfg_region r22_gcr_addr, GCR_REG0_BASE, GCR_REG0_MASK, $a0, 0xA0000000, 0xE000 /* 512MB */, 2 /* MMIO0 */, 0 /* CCA_OV_EN */, 0x0 /* CCA_OV */, 0x0 /* DROP_L2 */
+ cfg_region r22_gcr_addr, GCR_REG1_BASE, GCR_REG1_MASK, $a0, 0xC0000000, 0xE000 /* 512MB */, 2 /* MMIO0 */, 0 /* CCA_OV_EN */, 0x0 /* CCA_OV */, 0x0 /* DROP_L2 */
+
+ /* Set Custom GCR Base Address */
+ li $a1, (GCR_CUSTOM_ADDR | 0x1 /* Enable-Bit */)
+ sw $a1, GCR_CUSTOM_BASE(r22_gcr_addr)
+
+ /* Set all errors to cause exception instead of interrupt */
+ sw $zero, GCR_ERROR_MASK(r22_gcr_addr)
+
+ /* Set L2-Only-Sync address (defined in l2cache_def.h) */
+ li $a0, (l2_sync_base | 0x1 /* Enable-Bit */)
+ sw $a0, GCR_L2_ONLY_SYNC_BASE(r22_gcr_addr)
+1:
+ jrc.hb $ra
+.endm init_cm_macro
+
+.macro init_cm_wt_macro
+#if (defined(MIPS_IA_ENABLE_L2_CACHE) && defined(MIPS_IA_ENABLE_L2_CACHE_WT))
+ li r22_gcr_addr, GCR_CONFIG_ADDR
+ cfg_region r22_gcr_addr, GCR_REG2_BASE, GCR_REG2_MASK, $a0, 0x60000000, 0xE000 /* 512MB */, 1 /* MEM */, 1 /* CCA_OV_EN */, 0x0 /* WT */, 0x0 /* DROP_L2 */
+ cfg_region r22_gcr_addr, GCR_REG5_BASE, GCR_REG5_MASK, $a0, 0x80000000, 0xF000 /* 256MB */, 1 /* MEM */, 1 /* CCA_OV_EN */, 0x0 /* WT */, 0x0 /* DROP_L2 */
+ cfg_region r22_gcr_addr, GCR_REG6_BASE, GCR_REG6_MASK, $a0, 0x40000000, 0xF000 /* 256MB */, 1 /* MEM */, 1 /* CCA_OV_EN */, 0x0 /* WT */, 0x0 /* DROP_L2 */
+#endif
+ jrc.hb $ra
+.endm init_cm_wt_macro
+
+.section ".text.init_cm_c", "ax"
+.globl init_cm_c
+.ent init_cm_c
+init_cm_c:
+ init_cm_macro
+.end init_cm_c
+
+.section ".text.init_cm_wt_c", "ax"
+.globl init_cm_wt_c
+.ent init_cm_wt_c
+init_cm_wt_c:
+ init_cm_wt_macro
+.end init_cm_wt_c
+
+.section "NONCACHED_ROCODE", "ax"
+.globl init_cm
+.ent init_cm
+init_cm:
+ init_cm_macro
+.end init_cm
+
+.section "NONCACHED_ROCODE", "ax"
+.globl init_cm_wt
+.ent init_cm_wt
+init_cm_wt:
+ init_cm_wt_macro
+.end init_cm_wt
+
diff --git a/mcu/driver/sys_drv/init/src/md97/init_comm.c b/mcu/driver/sys_drv/init/src/md97/init_comm.c
new file mode 100644
index 0000000..6f632b8
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_comm.c
@@ -0,0 +1,1122 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+[MAUI_03149504] ([MAUI_03180970]) all time memory dump
+[MAUI_03121063] remove PDN registers
+[MAUI_03147344] Dummy read for early response HW
+[MAUI_03161918] remove custom_setAdvEMI from bootarm.S
+[MAUI_03157059] security use meta to write
+
+ * removed!
+ *
+ * removed!
+ * removed!
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+ *
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#include "kal_internal_api.h"
+#include "kal_trace.h"
+#include "reg_base.h"
+#include "config_hw.h"
+#include "emi_hw.h"
+//#include "init.h"
+#include "intrCtrl.h"
+#include "isrentry.h"
+//MSBB remove #include "custom_config.h"
+#include "stack_buff_pool.h"
+#include "fat_fs.h"
+#include "drv_comm.h"
+//MSBB remove #include "wdt_hw.h"
+#include "wdt_sw.h"
+#include "bmt.h"
+#include "dcl.h"
+#include "drvpdn.h"
+//#include "SST_init.h" /* for sw version check in INT_Version_Check() */
+#include <stdio.h>
+#include <string.h>
+#if defined(__ARMCC_VERSION)
+#include <rt_misc.h> /* for __rt_lib_init() */
+#endif
+#include <stdlib.h>
+#include "cache_sw.h"
+//#include "page.h"
+#include "md2g_drv.h"
+//#include "bl_features.h"
+//#include "bl_setting.h"
+//#include "bl_loader.h"
+#include "system_trc.h"
+#include "init_trc_api.h"
+//#include "ex_item.h"
+#include "init_comm.h"
+#include "init_comm_trc.h"
+#include "md_boot_check.h"
+#include "cp15.h"
+#include "cpu_info.h"
+
+
+
+#ifdef __MULTI_BOOT__
+#include "syscomp_config.h"
+#include "multiboot_config.h"
+#endif /* __MULTI_BOOT__ */
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+#include "cp15.h"
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+
+#if defined(__SMART_PHONE_MODEM__)
+#include "ccci.h"
+#endif /* __SMART_PHONE_MODEM__ */
+
+#if defined(__FOTA_DM__)
+#include "fue_err.h"
+#include "custom_fota.h"
+#include "custom_img_config.h"
+#include "fue.h"
+#include "SSF_fue_support.h"
+#endif
+#if !defined(__UBL__) && !defined(__FUE__)
+#include "ostd_public.h"
+#endif
+
+#include "ex_public.h"
+#include "cm2_drv.h"
+
+/*******************************************************************************
+ * Define pragma
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Define global data
+ *******************************************************************************/
+/* [BB porting] please make sure the register address is correct and scatter file palced in the correct region */
+#if defined(EMI_base)
+const kal_uint32 g_EMI_BASE_REG = EMI_base;
+#endif /* EMI_base */
+// Bootup trace global array
+__attribute__((aligned(32))) BOOTTRACE_FINAL_STEP_STRUCT INC_Init_Step[SYS_MCU_NUM_VPE] = {{0}};
+
+#if defined(__MTK_TARGET__)
+/* bb reg dump setting */
+EX_BBREG_DUMP chipversion_dump;
+const kal_uint32 chipversion_dump_regions[] =
+{
+#if (defined(MT6763))
+ MD_CONFIG_base, 0x0020, 4, /* chip version and sw misc registers*/
+#else
+ 0, 0, 0
+#endif
+};
+#endif /* __MTK_TARGET__ */
+
+
+/*******************************************************************************
+ * Declare import data
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Declare import function prototype
+ *******************************************************************************/
+
+
+
+/*************************************************************************
+* FUNCTION
+* AnalogDieID
+*
+* DESCRIPTION
+* This function returns identification of analog die
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* Identification of analog die
+*
+* GLOBALS AFFECTED
+* None
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef ExtraVer
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* fake function */
+void INT_Version_Check(void)
+{
+}
+
+void INT_SW_VersionCheck(void)
+{
+}
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_ecoVersion
+*
+* DESCRIPTION
+* This function returns the ECO version number of baseband chipset
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+/* [BB porting] Please make sure the the correlated enum and code is added since the default case is ext_assert */
+/* Please be aware that new chips may use INT_SW_SecVersion */
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetCurrentTime
+*
+* DESCRIPTION
+* This function access 32KHz Counter and return Counter Value
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+* Value of 32KHz Counter
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+/* for SNOR, this function should be placed in RAM */
+#if defined(__MTK_TARGET__)
+#if defined(__UBL__) || defined(__FUE__)
+//#pragma arm section code = "INTERNCODE"
+#endif
+#endif //__MTK_TARGET__
+
+/* [BB porting] confirm with L1 if the function is support in new chip */
+kal_uint32 INT_GetCurrentTime(void)
+{
+#if defined(__APPLICATION_PROCESSOR__)
+ return 0; // Not Support Yet
+#elif defined(ATEST_DRV_ENVIRON)
+ return 0; // Not Support Yet
+#else
+ /*
+ * Call API provided by L1
+ */
+ return 0;
+#endif /* __APPLICATION_PROCESSOR__ */
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_ChipName
+*
+* DESCRIPTION
+* This function is a special use for those users desire to run on
+* different chips with the same SW load.
+*
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+/* [BB porting] Make sure if the rule is changed or need to add for a new chip */
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_ChipGroup
+*
+* DESCRIPTION
+* This function is a special use for those users desire to run on
+* different chips with the same SW load.
+*
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*Only FPGA support this function*/
+#if defined (__FPGA__)
+HW_PURPOSE INT_FPGA_PURPOSE(void)
+{
+
+ kal_uint32 purpose_code = *((volatile kal_uint32 *)(PURPOSE_CODE_BASE));
+ HW_PURPOSE purpose;
+
+ if(purpose_code==0x55AA55AA)
+ {
+#if defined(__PALLADIUM__)
+ purpose = FPGA_U4G_LTEL2;
+ return purpose;
+#else // __PALLADIUM__
+ return PURPOSE_NotSupport;
+#endif // __PALLADIUM__
+ }
+ else
+ {
+ purpose_code = (purpose_code & PURPOSE_CODE_MASK)>>PURPOSE_CODE_BIT;
+ purpose = PURPOSE_NotSupport;
+#if defined(__MD97__)
+#if defined (__FPGA__)
+ if(purpose_code==1) purpose = FPGA_H1;
+ else if(purpose_code==2) purpose = FPGA_H2;
+ else if(purpose_code==3) purpose = FPGA_H3;
+ else if(purpose_code==4) purpose = FPGA_H4;
+ else if(purpose_code==5) purpose = FPGA_H5;
+ else if(purpose_code==6) purpose = FPGA_H6;
+ else purpose = PURPOSE_NotSupport;
+#else
+ purpose = FPGA_H5;
+#endif
+#else
+ if(purpose_code==1)
+ {
+ purpose = FPGA_Platform;
+ }
+ else if(purpose_code==2)
+ {
+ purpose = FPGA_LTEL2;
+ }
+ else if(purpose_code==3)
+ {
+ purpose = FPGA_SIB;
+ }
+ else if(purpose_code==5)
+ {
+ purpose = FPGA_U4G;
+ }
+ else if(purpose_code==6)
+ {
+ purpose = FPGA_U4G_LTEL2;
+ }
+ else
+ {
+ purpose = PURPOSE_NotSupport;
+ }
+#endif
+ return purpose;
+ }
+}
+#endif
+HW_CORENUM INT_FPGA_CORENUM(void)
+{
+
+ kal_uint32 purpose_code = *((volatile kal_uint32 *)(PURPOSE_CODE_BASE));
+ HW_CORENUM corenum;
+
+ if(purpose_code==0x55AA55AA)
+ {
+#if defined(__PALLADIUM__)
+ corenum = CORENUM_2;
+ return corenum;
+#else // __PALLADIUM__
+ return CORENUM_NotSupport;
+#endif // __PALLADIUM__
+ }
+ else
+ {
+ purpose_code = (purpose_code & CORENUM_MASK)>>CORENUM_BIT;
+ corenum = CORENUM_NotSupport;
+ if(purpose_code==1)
+ {
+ corenum = CORENUM_1;
+ }
+ else if(purpose_code==2)
+ {
+ corenum = CORENUM_2;
+ }
+ else if(purpose_code==3)
+ {
+ corenum = CORENUM_3;
+ }
+ else if(purpose_code==4)
+ {
+ corenum = CORENUM_4;
+ }
+ return corenum;
+ }
+}
+HW_CORENUM INT_QUERY_CORENUM(void)
+{
+#if defined(__SINGLE_CORE__)
+ return CORENUM_1;
+#else
+#if defined(__MTK_TARGET__) || defined(__FPGA__) || defined(__ESL_ENABLE__) || defined(UMOLYE_COSIM) || defined(__PALLADIUM__)
+ HW_CORENUM corenum;
+ corenum = query_cm2_corenum();
+ return corenum;
+#else
+#error("Not support now.");
+#endif
+#endif
+}
+
+/**
+ * This function is used to detect ASIC or FPGA version of Palladium
+ * If @0xA02100FC = 0xA51C, it means ASIC version of Palladium;
+ * otherwise others.
+ */
+#if 0
+/* under construction !*/
+/* under construction !*/
+#if defined(__FPGA__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INITSYNC_WriteAndPoll
+*
+* DESCRIPTION
+* This function used for system init dual core sync procedure
+*
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_Set_BootSlave
+*
+* DESCRIPTION
+* This function is used to set the Boot-Slave
+*
+*
+* PARAMETERS
+* kal_uint32 core_index: assigned core index
+* kal_uint32 jmp_addr: set jump address
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_Set_BootSlave(kal_uint32 core_index, kal_uint32 jmp_addr)
+{
+#if defined(__MTK_TARGET__)
+ ASSERT(core_index <= 3);
+
+ *(volatile kal_uint32 *)MCU_BOOTSLV_JUMP_ADDR_UNLOCK(core_index) = MCU_BOOTSLV_JUMP_KEY_VALUE;
+ *(volatile kal_uint32 *)MCU_BOOTSLV_JUMP_ADDR(core_index) = jmp_addr;
+ *(volatile kal_uint32 *)MCU_BOOTSLV_JUMP_ADDR_UPDATE(core_index) = 1;
+ // Make sure write to destination
+ // Check that if MO_Sync() is sync 0x6?
+
+ MO_Sync();
+#endif
+ return;
+}
+
+kal_bool INT_ChipVersion_BBREG_callback()
+{
+ #if defined(__DHL_MODULE__)
+ kal_uint32 hw_version_code = DRV_Reg32(MD_CONFIG_base+0x0);
+ kal_uint32 sw_version_code = DRV_Reg32(MD_CONFIG_base+0x4);
+ kal_uint32 hw_code = DRV_Reg32(MD_CONFIG_base+0x8);
+ kal_uint32 hw_sub_code = DRV_Reg32(MD_CONFIG_base+0xC);
+
+ MD_TRC_INIT_LOG_VERSION_CODE_TITLE();
+ MD_TRC_INIT_LOG_HW_VERSION_CODE(hw_version_code);
+ MD_TRC_INIT_LOG_SW_VERSION_CODE(sw_version_code);
+ MD_TRC_INIT_LOG_HW_CODE(hw_code);
+ MD_TRC_INIT_LOG_HW_SUB_CODE(hw_sub_code);
+ MD_TRC_INIT_LOG_MD_BOOT_CHECK(md_boot_check_val);
+ MD_TRC_INIT_LOG_MD_BOOT_CHECK(md_boot_check_val2);
+ MD_TRC_INIT_LOG_VERSION_CODE_END();
+#endif
+ return KAL_TRUE;
+}
+void INT_Init_Misc()
+{
+#if defined(__MTK_TARGET__)
+ /* register bb reg dump */
+ chipversion_dump.regions = (kal_uint32*)chipversion_dump_regions;
+ chipversion_dump.num = sizeof(chipversion_dump_regions) / (sizeof(kal_uint32) * 3);
+ chipversion_dump.bbreg_dump_callback = INT_ChipVersion_BBREG_callback;
+ EX_REGISTER_BBREG_DUMP(&chipversion_dump);
+#endif /* __MTK_TARGET__ */
+}
+
diff --git a/mcu/driver/sys_drv/init/src/md97/init_tc.S b/mcu/driver/sys_drv/init/src/md97/init_tc.S
new file mode 100644
index 0000000..ef997d1
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_tc.S
@@ -0,0 +1,213 @@
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+ .set nomips16
+/**************************************************************************************
+ $a0 = vpe id, $a1 = tc id, $a2 = stack pointer, $a3 = isMVP?
+**************************************************************************************/
+LEAF(init_tc)
+
+ /* This is executing on TC_a1 bound to VPE_a1. Therefore VPEConf0.MVP is set. */
+
+ /* Config C0_MVPCONTROL.VPC[1]
+ * Purpose: Enter config mode */
+ mfc0 $t0, C0_MVPCONTROL
+ or $t0, (1 << 1) // set VPC[1]
+ ins $t0, $zero, 0, 1 // clear EVP[0]
+ mtc0 $t0, C0_MVPCONTROL
+ ehb
+
+ /* Config C0_VPECONTROL.TargTC[7:0]
+ * to set target TC be configured */
+// li a3_TC, 0x2
+ mfc0 $t0, C0_VPECONTROL // read C0_VPECONTROL
+ ins $t0, $a1, 0, 8 // insert TargTC[7:0]
+// ins $t0, a3_TC, 0, 8 // insert TargTC[7:0]
+ mtc0 $t0, C0_VPECONTROL // write C0_VPECONTROL
+ ehb
+
+ /* Config C0_TCHALT.H[0]
+ * to halt target TC, a3_TC */
+ li $t0, 1 // set Halt bit
+ mttc0 $t0, C0_TCHALT // write C0_TCHALT
+ ehb
+
+ /* Config C0_TCBIND.CurVPE[3:0]
+ * bind TC2 to VPE1 */
+// li $t1, INDEX_VPE1
+ mftc0 $t0, C0_TCBIND // Read C0_TCBIND
+ ins $t0, $a0, 0, 4 // change CurVPE[3:0]
+// ins $t0, $t1, 0, 4 // change CurVPE[3:0]
+ mttc0 $t0, C0_TCBIND // write C0_TCBIND
+ ehb
+
+ beqzc $a3, INT_Initialize_GPR
+
+INT_MVP_SetupConfig1:
+ /* Only VPE1 TC1 set YQMask */
+ addi $t0, $zero, 0xF0F // bit 0~3 for VPE0, 8~11 for VPE1
+ mttc0 $t0, C0_YQMASK
+
+ // Set XTC for active a3_TC's
+ mftc0 $t0, C0_VPECONF0 // read C0_VPECONF0
+ ins $t0, $a1, 21, 8 // insert XTC[28:21]
+ mttc0 $t0, C0_VPECONF0 // write C0_VPECONF0
+
+
+/***************************************************
+ Set up TCStatus register:
+ * Disable Coprocessor Usable bits
+ * Disable MDMX/DSP ASE
+ * Clear Dirty TC_a1
+ * not dynamically allocatable
+ * not allocated
+ * Kernel mode
+ * interrupt exempt
+ * ASID 0
+****************************************************/
+
+INT_Initialize_GPR:
+
+ li $t1, 0x2
+ beqc $t1, $a1, INT_Set_IXMT_done
+ li $t1, 0x4
+ beqc $t1, $a1, INT_Set_IXMT_done
+
+ li $t0, (1 << 10) // set IXMT[10]
+ mttc0 $t0, C0_TCSTATUS // write C0_TCSTATUS
+.set noat
+INT_Set_IXMT_done:
+
+ // Initialize the a3_TC's register file
+ li $t0, 0xDEADBEEF
+ mttgpr $t0, $at
+ mttgpr $t0, $t4
+ mttgpr $t0, $t5
+ mttgpr $t0, $a0
+ mttgpr $t0, $a1
+ mttgpr $t0, $a2
+ mttgpr $t0, $a3
+ mttgpr $t0, $a4
+ mttgpr $t0, $a5
+ mttgpr $t0, $a6
+ mttgpr $t0, $a7
+ mttgpr $t0, $t0
+ mttgpr $t0, $t1
+ mttgpr $t0, $t2
+ mttgpr $t0, $t3
+ mttgpr $t0, $s0
+ mttgpr $t0, $s1
+ mttgpr $t0, $s2
+ mttgpr $t0, $s3
+ mttgpr $t0, $s4
+ mttgpr $t0, $s5
+ mttgpr $t0, $s6
+ mttgpr $t0, $s7
+ mttgpr $t0, $t8
+ mttgpr $t0, $t9
+ mttgpr $t0, $k0
+ mttgpr $t0, $k1
+ mttgpr $t0, $gp
+// mttgpr $t0, $sp
+ mttgpr $t0, $fp
+ mttgpr $t0, $ra
+
+
+ bnezc $a3, INT_MVP_SetupConfig2
+ // Initialize the sp
+ lw $a2, 0x0($a2)
+ li $t0, 0xFFFFFFF0
+ and $a2, $a2, $t0
+ mttgpr $a2, $sp
+
+
+ // VPE1 of each core can execute cached as it's L1 I$ has already been initialized.
+ // and the L2$ has been initialized or "disabled" via CCA override.
+ la $a1, HRT_domain_C_env // Convert to cached kseg0 address in case we linked to kseg1.
+ mttc0 $a1, C0_TCRESTART // write C0_TCRESTART
+ ehb
+
+ bc INT_SetupTCRESTART_done
+
+.set at
+INT_MVP_SetupConfig2:
+ /* Enable multi-threading with a3_TC's VPE
+ * Enable multi-threading of VPE1 */
+ li $t1, 1
+ mftc0 $t0, C0_VPECONTROL // read C0_VPECONTROL
+ ins $t0, $t1, 15, 1 // set TE[15]
+ mttc0 $t0, C0_VPECONTROL // write C0_VPECONTROL
+
+ // For VPE1..n
+ // Only VPE1 TC1 clear VPA and set master VPE
+ mftc0 $t0, C0_VPECONF0 // read C0_VPECONF0
+ ins $t0, $zero, 0, 1 // clear VPA[0]
+ or $t0, (1 << 1) // set MVP[1]
+ mttc0 $t0, C0_VPECONF0 // write C0_VPECONF0
+
+ la $t0, INT_Vectors
+ mttc0 $t0, C0_EPC // write C0_EPC
+
+ mttc0 $zero, C0_CAUSE // write C0_CAUSE
+
+ mfc0 $t0, C0_CONFIG // read C0_CONFIG
+ mttc0 $t0, C0_CONFIG // write C0_CONFIG
+
+ // VPE1 of each core can execute cached as it's L1 I$ has already been initialized.
+ // and the L2$ has been initialized or "disabled" via CCA override.
+ la $a1, INT_Vectors // Convert to cached kseg0 address in case we linked to kseg1.
+ mttc0 $a1, C0_TCRESTART // write C0_TCRESTART
+ ehb
+
+INT_SetupTCRESTART_done:
+ // Yes.. this is undoing all of the work done above... :)
+ mftc0 $t0, C0_TCSTATUS // read C0_TCSTATUS
+ //ins $t0, $zero, 10, 1 // clear IXMT[10]
+ li $t1, (1 << 13)
+ or $t0, $t0, $t1
+ li $t1, (1 << 15)
+ or $t0, $t0, $t1
+// ori $t0, (1 << 13) // set A[13]
+// ori $t0, (1 << 15) // set DA[15]
+#if (MX_FEATURE == 1)
+ li $t1, 0x1
+ ins $t0, $t1, 27, 1 // set TMX[27]
+#endif
+ mttc0 $t0, C0_TCSTATUS // write C0_TCSTATUS
+
+ // keep halt status
+ //mttc0 $zero, C0_TCHALT // write C0_TCHALT
+ beqzc $a3, INT_Init_TC_done
+
+INT_MVP_SetupConfig3:
+
+ /* Set C0_TCSCHEDULE */
+ mttc0 $zero, C0_TCSCHEDULE
+
+ mttc0 $zero, C0_TCHALT // write C0_TCHALT
+
+ // Only VPE1 TC1 set VPA
+ mftc0 $t0, C0_VPECONF0 // read C0_VPECONF0
+ ori $t0, 1 // set VPA[0]
+ mttc0 $t0, C0_VPECONF0 // write C0_VPECONF0
+
+INT_Init_TC_done:
+ // Exit config mode
+ mfc0 $t0, C0_MVPCONTROL // read C0_MVPCONTROL
+ ori $t0, 1 // set EVP[0] will enable execution by vpe1
+ ins $t0, $zero, 1, 1 // clear VPC[1]
+ mtc0 $t0, C0_MVPCONTROL // write C0_MVPCONTROL
+ ehb
+
+ jrc $ra
+
+END(init_tc)
+.set pop
diff --git a/mcu/driver/sys_drv/init/src/md97/init_trc.c b/mcu/driver/sys_drv/init/src/md97/init_trc.c
new file mode 100644
index 0000000..48f24d7
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_trc.c
@@ -0,0 +1,483 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_trc.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines bootup trace functions.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include <string.h>
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_trace.h"
+#include "ccci_if.h"
+#include "init_trc_api.h"
+#include "ex_mem_manager_public.h" //EMM_GetBufInfo, EMM_ClearDbgInfo
+/*******************************************************************************
+ * Define global data
+ *******************************************************************************/
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+ kal_bool is_init_log_enable; // setup in INT_setInitLogFlag
+ kal_bool is_init_stage;
+#else /* __KEYPAD_DEBUG_TRACE__ */
+ const kal_bool is_init_log_enable = KAL_FALSE;
+ kal_bool is_init_stage = KAL_TRUE;
+#endif /* __KEYPAD_DEBUG_TRACE__ */
+
+//#if defined(__SP_BOOTTRC_ENABLE__)
+#if defined(__HIF_CCCI_SUPPORT__)
+#define BOOTTRACE_BKBUF_SIZE (1024*3)
+//#define BOOTTRACE_BKBUF_SIZE (768*2)
+kal_uint8 boot_trace_log[BOOTTRACE_BKBUF_SIZE] = {0}; // EMM reserves 1.5k currently
+#endif
+
+/*******************************************************************************
+ * Declare import data
+ *******************************************************************************/
+extern boot_mode_type system_boot_mode;
+
+
+/*******************************************************************************
+ * Declare function prototype
+
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Declare import function prototype
+ *******************************************************************************/
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+#if 0 //
+/* under construction !*/
+/* under construction !*/
+#else
+extern void UART_Bootup_Init(void);
+extern void Seriport_Driver_Boot_Trace_Init(void);//want bootup trace,but VFIFO maybe not ready,so close vfifo and init uart1 driver
+#endif
+#endif /* __KAL_RECORD_BOOTUP_LOG__ || __KEYPAD_DEBUG_TRACE__ */
+
+
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+/*************************************************************************
+* FUNCTION
+* INT_setInitLogFlag
+*
+* DESCRIPTION
+* This function is used to set init flag for tst, which will use the flag to determine whether
+* the system is at init. stage or not.
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_setInitLogFlag(void)
+{
+ is_init_stage = KAL_TRUE;
+#if defined(__KAL_RECORD_BOOTUP_LOG__)
+ is_init_log_enable = KAL_TRUE;
+#else
+
+ custom_InitKeypadGPIO();
+
+ if(custom_IsBootupTraceKeyPressed())
+ {
+ is_init_log_enable = KAL_TRUE;
+ }
+ else
+ {
+ is_init_log_enable = KAL_FALSE;
+ }
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* INT_InitBootupTrace
+*
+* DESCRIPTION
+* This function is used to init bootup trace driver.
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_InitBootupTrace(void)
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+ /* init uart baudrate (HW related) */
+ UART_Bootup_Init();
+ INT_setInitLogFlag();
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* INT_printBootMode
+*
+* DESCRIPTION
+* This function is used to print out current boot-up mode.
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_printBootMode(void)
+{
+ kal_char buff[40];
+
+#if defined(__FACTORY_BIN__)
+ sprintf(buff, "Supported Boot mode: META only");
+#else
+
+#if defined(__SPLIT_BINARY__)
+ sprintf(buff, "Supported Boot mode: MAUI only");
+#else
+ sprintf(buff, "Supported Boot mode: ALL");
+#endif /* __SPLIT_BINARY__ */
+
+#endif /* __FACTORY_BIN__ */
+
+ kal_bootup_print(buff);
+
+ memset(buff, 0x0, sizeof(buff));
+ sprintf(buff, "Boot mode: ");
+ switch(system_boot_mode) {
+ case FACTORY_BOOT:
+ strcat(buff, "FACTORY");
+ break;
+
+ case NORMAL_BOOT:
+ strcat(buff, "NORMAL");
+ break;
+
+ case USBMS_BOOT:
+ strcat(buff, "USB");
+ break;
+
+ case FUE_BOOT:
+ strcat(buff, "FUE");
+ break;
+
+ default:
+ strcat(buff, "UNKNOWN");
+ break;
+ }
+ kal_bootup_print(buff);
+}
+#endif /* __KAL_RECORD_BOOTUP_LOG__ || __KEYPAD_DEBUG_TRACE__ */
+
+void INT_backupBootLogs(void)
+{
+//#if defined(__SP_BOOTTRC_ENABLE__)
+#if defined(__HIF_CCCI_SUPPORT__)
+ //for external smart phone, there is no share memory for back up
+ kal_uint32 log_addr = 0, log_size = 0;
+
+ if (EMM_GetBufInfo(&log_addr, &log_size, EMM_BOOTUP_TRACE)) {
+ if (log_addr && log_size) {
+ memcpy(boot_trace_log, (void*)log_addr, BOOTTRACE_BKBUF_SIZE);
+ }
+ }
+ EMM_ClearDbgInfo();
+#endif
+}
+
+#if defined(__COSIM_BYPASS_DRV__)
+/*************************************************************************
+* FUNCTION
+* MDM_ASSERT
+*
+* DESCRIPTION
+* This function created for RTL CoSim load for ASSERT support
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void MDM_ASSERT(kal_uint32 e1, kal_uint32 e2, kal_uint32 e3)
+{
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('A');
+ MDM_STR0_WRITE('S');
+ MDM_STR0_WRITE('S');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('R');
+ MDM_STR0_WRITE('T');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('e');
+ MDM_STR0_WRITE('1');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(e1);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('e');
+ MDM_STR0_WRITE('2');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(e2);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('e');
+ MDM_STR0_WRITE('3');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(e3);
+ MDM_INT32_WRITE(ASSERT_ERROR_MAGIC);
+ MDM_TM_END_FAIL_WRITE;
+ while(1);
+}
+/*************************************************************************
+* FUNCTION
+* MDM_kal_fatal_error_handler
+*
+* DESCRIPTION
+* This function created for RTL CoSim load for fatal error handler support
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+
+void MDM_kal_fatal_error_handler(kal_uint32 code1, kal_uint32 code2)
+{
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('F');
+ MDM_STR0_WRITE('A');
+ MDM_STR0_WRITE('T');
+ MDM_STR0_WRITE('A');
+ MDM_STR0_WRITE('L');
+ MDM_STR0_WRITE(' ');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('R');
+ MDM_STR0_WRITE('R');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('R');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('C');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('D');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('1');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(code1);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('C');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('D');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('2');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(code2);
+ MDM_INT32_WRITE(FATAL_ERROR_MAGIC);
+ MDM_TM_END_FAIL_WRITE;
+ while(1);
+}
+
+
+void MDM_EXCEPTION(void)
+{
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('X');
+ MDM_STR0_WRITE('C');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('P');
+ MDM_STR0_WRITE('T');
+ MDM_STR0_WRITE('I');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('N');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(EXCEPTION_ERROR_MAGIC);
+ MDM_TM_END_FAIL_WRITE;
+ while (1);
+}
+#endif
+
diff --git a/mcu/driver/sys_drv/init/src/md97/init_vpe0.S b/mcu/driver/sys_drv/init/src/md97/init_vpe0.S
new file mode 100644
index 0000000..5f7428e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_vpe0.S
@@ -0,0 +1,132 @@
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+#define QOS_MODE (0x1)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+ .set nomips16
+/**************************************************************************************
+**************************************************************************************/
+LEAF(init_vpe0)
+
+/* Check this core has more than 1 TC, if only 1 TC than trapping */
+INT_VPEINIT_TC_CHECK:
+ mfc0 $a0, C0_MVPCONF0
+ ext $a0, $a0, 0, 8
+ bgtzc $a0, INT_VPEINIT_VPE_CHECK
+
+INT_VPEINIT_TC_CHECK_FAIL:
+ bc INT_VPEINIT_TC_CHECK_FAIL
+
+
+/* Check this core has more than 1 VPE, if only 1 VPE than trapping */
+INT_VPEINIT_VPE_CHECK:
+ mfc0 $a0, C0_MVPCONF0
+ ext $a0, $a0, 10, 4
+ bgtzc $a0, INT_VPEINIT
+
+INT_VPEINIT_VPE_CHECK_FAIL:
+ bc INT_VPEINIT_VPE_CHECK_FAIL
+
+INT_VPEINIT:
+
+ /* This is executing on TC0 bound to VPE0. Therefore VPEConf0.MVP is set. */
+
+ /* Config C0_MVPCONTROL.VPC[1]
+ * Purpose: Enter config mode */
+ mfc0 $t0, C0_MVPCONTROL
+ or $t0, (1 << 1) // set VPC[1]
+ mtc0 $t0, C0_MVPCONTROL
+ ehb
+
+INT_QOS_init:
+ /* Every Core's VPE0 do QOS initialization */
+ /*clear all core ctrl to 0..(disable IDU SPRRAM)*/
+ mtc0 $zero, $22, 3
+ ehb
+#if (QOS_MODE == 1)
+ mfc0 $t0, C0_MVPCONTROL
+ or $t0, (1 << 16) // set QOS[16]
+ mtc0 $t0, C0_MVPCONTROL
+ ehb
+#endif
+
+INT_VPEINIT_VPE0_TC0:
+
+ /* Enable multi-threading of VPE0 */
+ li $a0, 1
+ mfc0 $t0, C0_VPECONTROL // read C0_VPECONTROL
+ ins $t0, $a0, 15, 1 // set TE[15]
+ mtc0 $t0, C0_VPECONTROL // write C0_VPECONTROL
+
+ /* Set YQMask */
+ addi $t0, $zero, 0xF0F // bit 0~3 for VPE0, 8~11 for VPE1
+ mtc0 $t0, C0_YQMASK
+
+ /* Set C0_TCSCHEDULE */
+ mtc0 $zero, C0_TCSCHEDULE
+
+INT_VPEINIT_VPEn_TC1:
+
+ move $t3, $ra
+
+
+INT_VPEINIT_VPE0_TC_StackInit:
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 2, 2
+
+ li $a1, 0
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core0
+
+#if !defined(__SINGLE_CORE__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core1
+#if !defined(__MD97_IS_2CORES__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core2
+
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core3
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE0_TC_StackInit_Core0:
+ la $a2, CORE0_VPE0_TC1_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_VPEINIT_VPE0_TC_StackInit_done
+
+INT_VPEINIT_VPE0_TC_StackInit_Core1:
+ la $a2, CORE1_VPE0_TC1_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE0_TC_StackInit_done
+#if !defined(__MD97_IS_2CORES__)
+INT_VPEINIT_VPE0_TC_StackInit_Core2:
+ la $a2, CORE2_VPE0_TC1_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE0_TC_StackInit_done
+
+INT_VPEINIT_VPE0_TC_StackInit_Core3:
+ la $a2, CORE3_VPE0_TC1_SYS_STACK_PTR
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE0_TC_StackInit_done:
+
+
+ li $a0, 0x0
+ li $a1, 0x1
+// la $a2, CORE0_VPE0_TC1_SYS_STACK_PTR
+ li $a3, 0x0
+ la $t0, init_tc
+ jalrc $t0
+
+ move $ra, $t3
+ jrc $ra
+
+END(init_vpe0)
+.set pop
diff --git a/mcu/driver/sys_drv/init/src/md97/init_vpe1.S b/mcu/driver/sys_drv/init/src/md97/init_vpe1.S
new file mode 100644
index 0000000..775df0e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_vpe1.S
@@ -0,0 +1,120 @@
+/*
+ * init_vpe1.S
+ *
+ * Initialize the second vpe and additional TCs
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+ .set nomips16
+/**************************************************************************************
+**************************************************************************************/
+LEAF(init_vpe1)
+// Each vpe will need to set up additional TC bound to it. (No rebinding.)
+
+INT_VPEINIT_VPE1_TC2:
+
+ move $t3, $ra
+
+ li $a0, 0x1
+ li $a1, 0x2
+ la $a2, 0xdeadbeef // no need to assign stack pointer here
+ li $a3, 0x1
+ la $t0, init_tc
+ jalrc $t0
+
+
+INT_VPEINIT_VPE1_TC_StackInit:
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 2, 2
+
+ li $a1, 0
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core0
+
+#if !defined(__SINGLE_CORE__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core1
+#if !defined(__MD97_IS_2CORES__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core2
+
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core3
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE1_TC_StackInit_Core0:
+ la $a2, CORE0_VPE1_TC3_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_VPEINIT_VPE1_TC_StackInit_done
+
+INT_VPEINIT_VPE1_TC_StackInit_Core1:
+ la $a2, CORE1_VPE1_TC3_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE1_TC_StackInit_done
+
+#if !defined(__MD97_IS_2CORES__)
+INT_VPEINIT_VPE1_TC_StackInit_Core2:
+ la $a2, CORE2_VPE1_TC3_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE1_TC_StackInit_done
+
+INT_VPEINIT_VPE1_TC_StackInit_Core3:
+ la $a2, CORE3_VPE1_TC3_SYS_STACK_PTR
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE1_TC_StackInit_done:
+
+
+INT_VPEINIT_VPE1_TC3:
+
+ li $a0, 0x1
+ li $a1, 0x3
+ li $a3, 0x0
+ la $t0, init_tc
+ jalrc $t0
+
+ move $ra, $t3
+ jrc $ra
+
+END(init_vpe1)
+.set pop
diff --git a/mcu/driver/sys_drv/init/src/md97/init_vpe2.S b/mcu/driver/sys_drv/init/src/md97/init_vpe2.S
new file mode 100644
index 0000000..57c5a45
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/init_vpe2.S
@@ -0,0 +1,122 @@
+/*
+ * init_vpe1.S
+ *
+ * Initialize the second vpe and additional TCs
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+// .set nomips16
+/**************************************************************************************
+**************************************************************************************/
+.section "NONCACHED_ROCODE", "ax"
+
+.globl init_vpe2
+.ent init_vpe2
+init_vpe2:
+
+
+ move $t3, $ra
+
+INT_VPEINIT_VPE2_TC4:
+ li $a0, 0x2
+ li $a1, 0x4
+ la $a2, 0xdeadbeef // no need to assign stack pointer here
+ li $a3, 0x1
+ la $t0, init_tc
+ jalrc $t0
+
+INT_VPEINIT_VPE2_TC_StackInit:
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 2, 2
+
+ li $a1, 0
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core0
+
+#if !defined(__SINGLE_CORE__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core1
+
+#if !defined(__MD97_IS_2CORES__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core2
+
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core3
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE2_TC_StackInit_Core0:
+ la $a2, CORE0_VPE2_TC5_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_VPEINIT_VPE2_TC_StackInit_done
+
+INT_VPEINIT_VPE2_TC_StackInit_Core1:
+ la $a2, CORE1_VPE2_TC5_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE2_TC_StackInit_done
+
+#if !defined(__MD97_IS_2CORES__)
+INT_VPEINIT_VPE2_TC_StackInit_Core2:
+ la $a2, CORE2_VPE2_TC5_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE2_TC_StackInit_done
+
+INT_VPEINIT_VPE2_TC_StackInit_Core3:
+ la $a2, CORE3_VPE2_TC5_SYS_STACK_PTR
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE2_TC_StackInit_done:
+
+INT_VPEINIT_VPE2_TC5:
+
+ li $a0, 0x2
+ li $a1, 0x5
+ li $a3, 0x0
+ la $t0, init_tc
+ jalrc $t0
+
+ move $ra, $t3
+ jrc $ra
+
+END(init_vpe2)
+.set pop
\ No newline at end of file
diff --git a/mcu/driver/sys_drv/init/src/md97/join_domain.S b/mcu/driver/sys_drv/init/src/md97/join_domain.S
new file mode 100644
index 0000000..13103ad
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/join_domain.S
@@ -0,0 +1,119 @@
+/*
+ * join_domain.S
+ *
+ * For CPS cores join processing domain
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <boot.h>
+#include <cps.h>
+#include <cpu_info.h>
+//#define U4G_LTEL2_3CORE
+
+.set noreorder // Don't allow the assembler to reorder instructions.
+.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+
+/**************************************************************************************
+**************************************************************************************/
+
+.section "NONCACHED_ROCODE", "ax"
+.globl join_domain
+.ent join_domain
+join_domain:
+ li r22_gcr_addr, GCR_CONFIG_ADDR
+ li r11_is_cps, 0x1
+ beqzc r11_is_cps, done_join_domain // If this is not a CPS then we are done.
+
+ // GCR_ACCESS, [0x1F00_0020] must be enable
+ //lw $t1, 0(r22_gcr_addr)
+ //ext $t1, $t1, 0, 8
+ li $t1, SYS_MCU_NUM_CORE
+ li $t2, 4
+ beqc $t1, $t2, four_core_ver
+
+ li $t2, 3
+ beqc $t1, $t2, three_core_ver
+
+ li $t2, 2
+ beqc $t1, $t2, two_core_ver
+
+ li $t2, 1
+ beqc $t1, $t2, done_join_domain
+
+ // Enable coherence and allow interventions from all other cores.
+ // (Write access enabled via GCR_ACCESS by core 0.)
+
+four_core_ver: //if ($t1==4) || ($t1 !=1)||($t1 !=2)||($t1 !=3)) will enter this flow
+ li $a2, 0x3
+ li $a0, 0x1F // Set Coherent domain enable for 4 cores
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_COHERENCE($a1) // GCR_CL_COHERENCE
+ ehb
+ bc Set_Coherence_Domain_Done
+
+three_core_ver:
+ li $a2, 0x2
+ li $a0, 0x17 // Set Coherent domain enable for 3 cores
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_COHERENCE($a1) // GCR_CL_COHERENCE
+ ehb
+ bc Set_Coherence_Domain_Done
+
+two_core_ver:
+ li $a2, 0x1
+ li $a0, 0x13 // Set Coherent domain enable for 3 cores
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_COHERENCE($a1) // GCR_CL_COHERENCE
+ ehb
+ bc Set_Coherence_Domain_Done
+
+Set_Coherence_Domain_Done:
+
+ // Cores other than core 0 can relinquish write access to CM regs here.
+
+ move $a3, $zero
+
+next_coherent_core:
+ sll $a0, $a3, 16
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_OTHER($a1) // GCR_CL_OTHER[CoreNum]
+
+busy_wait_coherent_core:
+ lw $a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
+ beqzc $a0, busy_wait_coherent_core // Busy wait on cores joining.
+
+ addiu $a3, 1
+ bnec $a3, $a2, next_coherent_core
+
+done_join_domain:
+ jrc $ra
+
+END(join_domain)
diff --git a/mcu/driver/sys_drv/init/src/md97/mdmcu_init.c b/mcu/driver/sys_drv/init/src/md97/mdmcu_init.c
new file mode 100644
index 0000000..8e4273e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/mdmcu_init.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97__)
+#include "mdmcu_init.h"
+#include "mdmcu_pmu.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+#define is_vpe0_of_each_core(__vpe_id__) (0 == ((__vpe_id__) % 2))
+
+void miu_wait(void)
+{
+ __asm__ __volatile__ ( "wait;\n");
+}
+
+// Do at INC_Initialize (every core)
+void mdmcu_init(void)
+{
+ mdmcu_pmu_init();
+}
+
+// Do at dormant_mode_activate (every core)
+void mdmcu_enter_dormant(void)
+{
+ mdmcu_pmu_enter_dormant();
+}
+
+// Do at dormant_mode_activate (every core)
+void mdmcu_leave_dormant(void)
+{
+ mdmcu_pmu_leave_dormant();
+}
+
+// Do at INC_Initialize before TCCT_Schedule, every core would do this
+void mips_ia_misc_init_by_core(void)
+{
+ //To Be Removed
+}
+
+// Do at HWDInitialization / Application_Initialize, only core0 would do this
+// Early than mips_ia_misc_init_by_core
+void mips_ia_misc_init(void)
+{
+ //To Be Removed
+}
+
+#endif /* !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97__) */
diff --git a/mcu/driver/sys_drv/init/src/md97/release_mp.S b/mcu/driver/sys_drv/init/src/md97/release_mp.S
new file mode 100644
index 0000000..ae7af25
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/release_mp.S
@@ -0,0 +1,154 @@
+/*
+ * release_mp.S
+ *
+ * Release other processors so they can boot
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <boot.h>
+#include <mips/regdef.h>
+#include <cps.h>
+
+#ifndef __MIPS16
+ .set noreorder // Don't allow the assembler to reorder instructions.
+ .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+/**************************************************************************************
+**************************************************************************************/
+
+//LEAF(release_mp)
+.section "NONCACHED_ROCODE", "ax"
+.globl release_mp
+.ent release_mp
+release_mp:
+
+ // Copy from set_gpr_boot_values.S due to boot register cannot be assumed as correct
+ li r22_gcr_addr, GCR_CONFIG_ADDR
+ lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
+ ext r19_more_cores, a0, PCORES, PCORES_S // Extract PCORES
+ li r30_cpc_addr, CPC_BASE_ADDR // Maintain address of CPC register block.
+
+ blez r19_more_cores, done_release_mp // If no more cores then we are done.
+ li a3, 1
+
+ beqz r30_cpc_addr, release_next_core // If no CPC then use GCR_CO_RESET_RELEASE
+ nop // else use CPC Power Up command.
+
+powerup_next_core:
+ // Send PwrUp command to next core causing execution at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(r30_cpc_addr)
+ li a0, PWR_UP // "PwrUp" power domain command.
+ sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(r30_cpc_addr)
+ bne r19_more_cores, a3, powerup_next_core
+ addiu a3, a3, 1
+
+ jalr zero, ra
+ nop
+
+release_next_core:
+ // Release next core to execute at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER
+ sw zero, 0x4000(r22_gcr_addr) // GCR_CO_RESET_RELEASE
+ bne r19_more_cores, a3, release_next_core
+ addiu a3, a3, 1
+
+done_release_mp:
+ jalr zero, ra
+ nop
+//END(release_mp)
+.end release_mp
+
+#else //__MIPS16
+
+ .set noreorder // Don't allow the assembler to reorder instructions.
+ .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+/**************************************************************************************
+**************************************************************************************/
+
+//LEAF(release_mp)
+.section "NONCACHED_ROCODE", "ax"
+
+__GCR_CONFIG_ADDR:
+ .word GCR_CONFIG_ADDR
+
+__CPC_BASE_ADDR:
+ .word CPC_BASE_ADDR
+
+.globl release_mp
+.ent release_mp
+release_mp:
+
+ // Copy from set_gpr_boot_values.S due to boot register cannot be assumed as correct
+ lw a2, __GCR_CONFIG_ADDR
+ lw a0, GCR_CONFIG(a2) // Load GCR_CONFIG
+ ext a1, a0, PCORES, PCORES_S // Extract PCORES
+ lw s0, __CPC_BASE_ADDR // Maintain address of CPC register block.
+
+ beqz a1, done_release_mp // If no more cores then we are done.
+ li a3, 1
+ addiu a1, 1
+
+ li s1, 0
+ beqz s0, release_next_core // If no CPC then use GCR_CO_RESET_RELEASE
+ // else use CPC Power Up command.
+
+powerup_next_core:
+ // Send PwrUp command to next core causing execution at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(s0)
+ li a0, PWR_UP // "PwrUp" power domain command.
+ sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(s0)
+ addiu a3, 1
+ bne a1, a3, powerup_next_core
+
+ jr ra
+ nop
+
+release_next_core:
+ // Release next core to execute at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(a2) // GCR_CL_OTHER
+ sw s1, 0x4000(a2) // GCR_CO_RESET_RELEASE
+ addiu a3, 1
+ bne a1, a3, release_next_core
+
+done_release_mp:
+ jr ra
+ nop
+//END(release_mp)
+.end release_mp
+#endif
diff --git a/mcu/driver/sys_drv/init/src/md97/stack_init.S b/mcu/driver/sys_drv/init/src/md97/stack_init.S
new file mode 100644
index 0000000..0bdf54e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97/stack_init.S
@@ -0,0 +1,280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bootarm_gcc.S
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the boot sequence of asm level.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ * removed!
+ * removed!
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+ *
+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+/*************************************************************************/
+/* */
+/* Copyright (c) 1994 -2000 Accelerated Technology, Inc. */
+/* */
+/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
+/* subject matter of this material. All manufacturing, reproduction, */
+/* use, and sales rights pertaining to this subject matter are governed */
+/* by the license agreement. The recipient of this software implicitly */
+/* accepts the terms of the license. */
+/* */
+/*************************************************************************/
+
+/*************************************************************************/
+/* */
+/* FILE NAME VERSION */
+/* */
+/* bootarm_gcc.s MIPS interAptiv */
+/* */
+/* COMPONENT */
+/* */
+/* IN - Initialization */
+/* */
+/* DESCRIPTION */
+/* */
+/* This file contains the target processor dependent initialization */
+/* routines and data. */
+/* */
+/* */
+/* DATA STRUCTURES */
+/* */
+/* INT_Vectors Interrupt vector table */
+/* */
+/* FUNCTIONS */
+/* */
+/* INT_Initialize Target initialization */
+/* */
+/* */
+/*************************************************************************/
+#include <boot_comm.h>
+#include <cpu_info.h>
+
+#define STACK_ALIGN_NUM (5)
+//.data
+
+#if !defined(__SINGLE_CORE__)
+#define BOOT_TOTAL_STACK_SIZE (BOOT_SYS_STACK_SIZE * SYS_MCU_NUM_CORE * 4)
+#else
+#define BOOT_TOTAL_STACK_SIZE (BOOT_SYS_STACK_SIZE * 3)
+#endif
+//.data
+
+.section "MCURW_HWRO_DNC_NOINIT", "aw", @progbits
+.align STACK_ALIGN_NUM
+.global BOOT_SYS_Stack_Pool
+BOOT_SYS_Stack_Pool:
+ .space BOOT_TOTAL_STACK_SIZE//-8
+ .size BOOT_SYS_Stack_Pool, .-BOOT_SYS_Stack_Pool
+
+
+/******************************************************************************/
+
+.macro gen_stack name, size, section, file, line
+.section \section, "aw", @progbits
+.align STACK_ALIGN_NUM
+.global \name
+.loc \file \line
+\name:
+ .ascii "STACKEND"
+ .space \size - 8
+ .type \name, @object
+ .size \name, . - \name
+.endm
+
+#define SYS_STACK_INSTANCE_BEGIN() \
+ /* WARNING: this will be add to dep file by cpp but not check in cpp */ \
+ .file 1 __FILE__; \
+ .loc 1 __LINE__;
+
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ gen_stack SYS_STACK_NAME(CORE,VPE,TC), SIZE, #SECTION, 1, __LINE__
+
+#include "sys_stack_config.h"
+
+/******************************************************************************/
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/bootarm_gcc.S b/mcu/driver/sys_drv/init/src/md97p/bootarm_gcc.S
new file mode 100644
index 0000000..74d52ed
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/bootarm_gcc.S
@@ -0,0 +1,1315 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bootarm_gcc.S
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the boot sequence of asm level.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+/*************************************************************************/
+/* */
+/* Copyright (c) 1994 -2000 Accelerated Technology, Inc. */
+/* */
+/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
+/* subject matter of this material. All manufacturing, reproduction, */
+/* use, and sales rights pertaining to this subject matter are governed */
+/* by the license agreement. The recipient of this software implicitly */
+/* accepts the terms of the license. */
+/* */
+/*************************************************************************/
+
+/*************************************************************************/
+/* */
+/* FILE NAME VERSION */
+/* */
+/* bootarm_gcc.s MIPS interAptiv */
+/* */
+/* COMPONENT */
+/* */
+/* IN - Initialization */
+/* */
+/* DESCRIPTION */
+/* */
+/* This file contains the target processor dependent initialization */
+/* routines and data. */
+/* */
+/* */
+/* DATA STRUCTURES */
+/* */
+/* INT_Vectors Interrupt vector table */
+/* */
+/* FUNCTIONS */
+/* */
+/* INT_Initialize Target initialization */
+/* */
+/* */
+/*************************************************************************/
+#include <boot.h>
+#include <boot_comm.h>
+#include <mips/m32c0.h>
+#include <cps.h>
+#include <mips/mt.h>
+#include <bootarm.h>
+#include <rstctl_reg.h>
+#include <MD_TOPSM_private.h>
+#include <drv_pcmon_init.h>
+#include <drv_busmon.h>
+#include <reg_base.h>
+#include <sst_temp_ex_handlers.h>
+#include <boot_asm.h>
+#include <cpu_info.h>
+#if defined(__ESL_SPEEDUP__)
+#include <esl_asm_macro.h>
+#endif
+
+.extern Set_VPE_Domain_Type
+
+.text
+STACKEND:
+ .ascii "STACKEND"
+.size STACKEND,.-STACKEND
+
+
+.section "NONCACHEDZI"
+INT_init_region_sync:
+ .word 0x0
+.size INT_init_region_sync,.-INT_init_region_sync
+
+// Total 8 VPEs each has 2 words for saving ra, sp
+ABN_RST_POOL:
+ .space 0x40
+.size ABN_RST_POOL,.-ABN_RST_POOL
+
+#if defined(UMOLYE_COSIM)
+core_sync_flag:
+ .word 0
+.size core_sync_flag,.-core_sync_flag
+#endif
+
+.section "MCURW_HWRO_DNC_NOINIT"
+INT_bootup_magic:
+ .word 0x0
+.size INT_bootup_magic,.-INT_bootup_magic
+
+INT_bootup_trace0:
+ .word 0x0
+.size INT_bootup_trace0,.-INT_bootup_trace0
+
+INT_bootup_trace1:
+ .word 0x0
+.size INT_bootup_trace1,.-INT_bootup_trace1
+
+INT_bootup_trace2:
+ .word 0x0
+.size INT_bootup_trace2,.-INT_bootup_trace2
+
+INT_bootup_trace4:
+ .word 0x0
+.size INT_bootup_trace4,.-INT_bootup_trace4
+
+INT_bootup_trace5:
+ .word 0x0
+.size INT_bootup_trace5,.-INT_bootup_trace5
+
+INT_bootup_trace6:
+ .word 0x0
+.size INT_bootup_trace6,.-INT_bootup_trace6
+
+INT_bootup_trace8:
+ .word 0x0
+.size INT_bootup_trace8,.-INT_bootup_trace8
+
+INT_bootup_trace9:
+ .word 0x0
+.size INT_bootup_trace9,.-INT_bootup_trace9
+
+INT_bootup_trace10:
+ .word 0x0
+.size INT_bootup_trace10,.-INT_bootup_trace10
+
+INT_bootup_trace12:
+ .word 0x0
+.size INT_bootup_trace12,.-INT_bootup_trace12
+
+INT_bootup_trace13:
+ .word 0x0
+.size INT_bootup_trace13,.-INT_bootup_trace13
+
+INT_bootup_trace14:
+ .word 0x0
+.size INT_bootup_trace14,.-INT_bootup_trace14
+
+INT_bootup_trace16:
+ .word 0x0
+.size INT_bootup_trace16,.-INT_bootup_trace16
+
+INT_bootup_trace17:
+ .word 0x0
+.size INT_bootup_trace17,.-INT_bootup_trace17
+
+INT_bootup_trace18:
+ .word 0x0
+.size INT_bootup_trace18,.-INT_bootup_trace18
+
+
+.set noreorder // Don't allow the assembler to reorder instructions.
+.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+
+/**************************************************************************************
+ * R E S E T E X C E P T I O N H A N D L E R
+ * Note: Run at VA: Bank0
+ **************************************************************************************/
+.section "INT_VECTOR_CODE", "ax"
+.globl INT_Vectors
+.ent INT_Vectors
+INT_Vectors:
+#if defined(UMOLYE_COSIM)
+ /* Only Core1 VPE0 would trap here in Cosim load */
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 0, 4
+ li $a1, 2
+ bnec $a0, $a1, core_sync_done
+ la $a0, core_sync_flag
+core_sync:
+ lw $a1, 0($a0)
+ beqzc $a1, core_sync
+core_sync_done:
+#endif
+
+#if (__LEGACY_NMI_CHECK__ == 1)
+ /*
+ * Every Core's VPEs Check if an NMI than jumps to NMI handler
+ */
+ mfc0 $a0, C0_STATUS
+ srl $a0, 19
+ andi $a0, $a0, 1
+ beqzc $a0, INT_NMICheck_done
+ la $a1, NMI_handler
+ jrc $a1
+INT_NMICheck_done:
+#endif
+ la $a2, INT_Initialize_Phase1
+ jrc $a2
+.size INT_Vectors,.-INT_Vectors
+.end INT_Vectors
+
+/*********************************************************************
+ * [Phase1] first NC function, Jumps here from BankA(temp booting bank)
+ * Note: only could invoke NC function
+ *********************************************************************/
+.section "NONCACHED_ROCODE", "ax"
+.globl INT_Initialize_Phase1
+.ent INT_Initialize_Phase1
+INT_Initialize_Phase1:
+ /*
+ * Only Core0 VPE0 do CM2 routing APB access configuration for boot-up trace and kick dog
+ * Note: Do not corrupt sp, ra
+ */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_CM2_route_MO_done
+
+ // Set region attribute in order to write VA: BankA/B to MO port
+ li $a2, GCR_CONFIG_ADDR
+ lui $a0, 0xA000 //set CM2 Region 0 BASE = 0xA000
+ sw $a0, GCR_REG0_BASE($a2)
+ lui $a0, 0xE000 //set CM2 Region Mask = 0xE000
+ li $a3, 0x1 //set CM2_TARGET to IOCU0
+ ins $a0, $a3, 1, 1
+ sw $a0, GCR_REG0_MASK($a2) //Mask=0xE000, target IOCU0
+ // Set region attribute in order to write VA: BankC/D/E/F to MO port
+ lui $a0, 0xC000 //set CM2 Region 1 BASE = 0xC000
+ sw $a0, GCR_REG1_BASE($a2)
+ lui $a0, 0xC000 //set CM2 Region Mask = 0xC000
+ li $a3, 0x1 //set CM2_TARGET to IOCU0
+ ins $a0, $a3, 1, 1
+ sw $a0, GCR_REG1_MASK($a2) //Mask=0xC000, target IOCU0
+
+#if defined(__ESL_SPEEDUP__)
+ ESL_BACKUP_AND_CLR_EMI_CFG
+#endif
+
+ // Can read from FMA
+ li $a2, GCR_CONFIG_ADDR
+ li $a1, GCR_CUSTOM_ADDR
+ li $a3, 0x1
+ ins $a1, $a3, 0, 1
+ sw $a1, 0x60($a2)
+ sync 0x3
+
+INT_CM2_route_MO_done:
+
+#if !defined(__COSIM_BYPASS_DRV__)
+ /*
+ * Every Core's VPEs backup ra and sp to ABN_RST_POOL for abnormal-reset scenario
+ * Note: 1. Can not call any function which will use ra register or backup it
+ * 2. Backup ra to $t0 if the boot-up trace is logged
+ */
+ la $a0, ABN_RST_POOL
+
+ INT_GET_CPUID $a1, $a2
+ li $a1, 0x8
+ mul $a3, $a1, $a2
+ addu $a0, $a0, $a3
+ sw $ra, 0x0($a0)
+ sw $sp, 0x4($a0)
+#endif
+
+INT_P1_temp_stack_init:
+ /*
+ * Every Core's VPEs initial temp sp for INT_Initialize_Phase1
+ * Note: 1. Every Core use different configuration
+ * 2. Why coding style so foolish? In init flow, simple is the first priority
+ * 3. [Tricky] per-Core VPE0 and VPE1 take the same sp, no concurrency because init_vpe1
+ */
+ INT_GET_COREID $a1, $a0
+
+ addiu $a0, $a0, 1
+ li $a1, BOOT_SYS_STACK_SIZE
+ mul $a1, $a1, $a0
+
+ la $a0, BOOT_SYS_Stack_Pool
+ add $a0, $a0, $a1
+
+ move $sp, $a0
+ li $a0, -16
+ add $sp, $sp ,$a0 //reserve 16 bytes for caller save
+
+INT_P1_temp_stack_init_done:
+
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_HW_PreConfig_done
+ INT_TRC_INIT_MAGIC
+ //PDAMON Mask SPRAM DECERR
+ INT_TRC_SAVE_RA LABEL_PREINIT_PDAMON
+ PDAMON_CONFIG
+ // Busmon switch to MO port
+ INT_TRC_SAVE_RA LABEL_PREINIT_BUSMON
+ BUSMON_PRE_CONFIG
+ // Enable FRC
+ INT_TRC_SAVE_RA LABEL_PREINIT_FRC
+ ENABLE_FRC
+
+ INT_TRC_SAVE_RA LABEL_START_P1
+INT_HW_PreConfig_done:
+
+ mfc0 $a0, C0_CONFIG7
+ lui $a1, 0x0020
+ addiu $a1, 0x0800
+ or $a0, $a0, $a1
+ mtc0 $a0, C0_CONFIG7
+ ehb
+INT_disable_ramslp_busslp_done:
+ /*
+ * Every Core's VPEs kick the WDT in order to avoid the unexpected WDT reset when booting
+ * Note: Kick per-VPE WDT and backup ra to $t0 if the boot-up trace is logged
+ */
+
+ INT_TRC_SAVE_RA LABEL_RESTART_WDT
+ la $a0, g_WATCHDOG_RESTART_REG
+ lw $a0, 0x0($a0)
+ li $a1, RSTCTL_WDTRR_KEY
+ li $a2, RSTCTL_WDTRR_WDT_RESTART
+ addu $a1, $a1, $a2
+ sw $a1, 0x0($a0)
+ sync 0x7
+
+INT_kick_wdt_done:
+ /*
+ * Every Core's VPEs do GPR initialize
+ * Note: 1. Solve RTL Cosim unknown value problem
+ * 2. Reset beginning values and for easy debug
+ */
+ li $at, INIT_DEF_VALUE
+ li $t4, INIT_DEF_VALUE
+ li $t5, INIT_DEF_VALUE
+ li $a0, INIT_DEF_VALUE
+ li $a1, INIT_DEF_VALUE
+ li $a2, INIT_DEF_VALUE
+ li $a3, INIT_DEF_VALUE
+ li $a4, INIT_DEF_VALUE
+ li $a5, INIT_DEF_VALUE
+ li $a6, INIT_DEF_VALUE
+ li $a7, INIT_DEF_VALUE
+ li $t0, INIT_DEF_VALUE
+ li $t1, INIT_DEF_VALUE
+ li $t2, INIT_DEF_VALUE
+ li $t3, INIT_DEF_VALUE
+ li $s0, INIT_DEF_VALUE
+ li $s1, INIT_DEF_VALUE
+ li $s2, INIT_DEF_VALUE
+ li $s3, INIT_DEF_VALUE
+ li $s4, INIT_DEF_VALUE
+ li $s5, INIT_DEF_VALUE
+ li $s6, INIT_DEF_VALUE
+ li $s7, INIT_DEF_VALUE
+ li $t8, INIT_DEF_VALUE
+ li $t9, INIT_DEF_VALUE
+ li $k0, INIT_DEF_VALUE
+ li $k1, INIT_DEF_VALUE
+ li $gp, INIT_DEF_VALUE
+ //li $sp, INIT_DEF_VALUE
+ li $fp, INIT_DEF_VALUE
+ li $ra, INIT_DEF_VALUE
+
+ /* Only Core0 VPE0 initialize NC Sync variables in Booting */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_init_sync_var_done
+
+ la $a0, INT_init_region_sync
+ sw $zero, 0x0($a0)
+INT_init_sync_var_done:
+
+ /* reset exception sp array because it is used in exception vector to know if we are in boot or dormant flow */
+ INT_TRC LABEL_RESET_EXC_SP_ARRAY
+ RESET_EXCEPTION_SP_ARRAY
+
+ /*********************************************************************
+ * Every Core's VPEs config C0_EBASE as temporary exception vector for duration
+ * between switch BEV to normal exception ready
+ *
+ * Every Core's VPEs set C0_CONFIG5 CV[29] and K[30] bits to switch
+ * exception vectors to use C0_EBASE if C0_STATUS.BEV[22] were cleared
+ * Note: Most of exceptions before this will go to
+ * "2'b10||SI_ExceptionBase[31:12]||0x380"
+ *********************************************************************/
+
+ INT_TRC LABEL_SET_C0_COFIG5_K
+ INSTALL_TEMP_EXCEPTION_VECTOR
+
+
+ /*********************************************************************
+ * Every Core's VPEs initialize C0_STATUS, clear ERL[2] and BEV[22]
+ * Note: 1. Most of exceptions before this will go to
+ * "SI_ExceptionBase[31:12]||0x380"
+ * 2. Most of exceptions after this will go to INT_BOOT_<X>_vector, i.e.,
+ * "C0_EBASE[31:12]||0x180"
+ *********************************************************************/
+ INT_TRC LABEL_CLR_C0_STATUS_BEV_ERL
+ li $a1, 0x0
+#if (MX_FEATURE == 0x1)
+ li $a0, 0x1
+ ins $a1, $a0, 24, 1 // set C0_STATUS.MX[24]
+#endif
+ mtc0 $a1, C0_STATUS // write C0_STATUS
+ ehb
+
+INT_Domain_Type_PreInit:
+ la $a2, Set_VPE_Domain_Type
+ jalrc $a2
+
+INT_Interrupt_PreInit:
+ INT_TRC LABEL_INTERRUPT_PREINIT
+ /* Every Core's VPEs write variables for enabling/disabling interrupt API */
+
+ la $a2, interrupt_preinit
+ jalrc $a2
+
+
+INT_CM_L2_init:
+ /* Only Core0 VPE0 do set CM2 GCR_BASE to L2 NC */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_CM_L2_init_done
+
+ INT_TRC LABEL_CM_L2_INIT
+ la $a2, disable_L2_init_stage
+ jalrc $a2
+
+ /* Initialize CM region attr. registers for routing PA: BankA/B/C/D/E/F to MO port */
+ INT_TRC LABEL_CM_INIT
+ la $a2, init_cm
+ jalrc $a2
+INT_CM_L2_init_done:
+
+INT_PLL_init:
+
+ /* Only Core0 VPE0 would set PLL for target load temporarily */
+ INT_TRC LABEL_PLL_INIT
+ /* PLL init */
+
+ la $a2, INT_SetPLL
+ jalrc $a2
+
+
+INT_L1_cache_init:
+ /* Every Core's VPE0 do L1$ initialization */
+ INT_GET_VPEID $a2, $a0
+ bnezc $a0, INT_L1_cache_init_done
+
+ INT_TRC LABEL_L1_CACHE_INIT
+ la $a2, l1_cache_init //init L1 cache & global variables
+ jalrc $a2
+INT_L1_cache_init_done:
+
+INT_L2_cache_init:
+ /* Only Core0 VPE0 do L2$ initialization */
+ INT_GET_CPUID $a0, $a0
+#if !defined(__SINGLE_CORE__)
+ bnezc $a0, INT_untrap_Core123_done
+#else
+ bnezc $a0, INT_join_CH_domain_sync_done
+#endif
+
+INT_init_L2:
+ INT_TRC LABEL_L2_CACHE_INIT
+ la $a2, init_L23
+ jalrc $a2
+
+INT_enable_L2:
+ la $a2, enable_L23
+ jalrc $a2
+
+ /* Set CM2 GCR WT CCA override */
+INT_enable_WT:
+ INT_TRC LABEL_SET_CM_WT
+ la $a2, init_cm_wt
+ jalrc $a2
+
+#if !defined(__SINGLE_CORE__)
+INT_init_other_Cores:
+ INT_TRC LABEL_INIT_OTHER_CORES
+ la $a2, init_otherCores
+ jalrc $a2
+
+INT_untrap_Core123:
+#if defined(__ESL_ENABLE__)||defined(__ESL_MASE__)
+ la $a2, release_mp // Release other cores to execute this boot code.
+ jalrc $a2
+#else /* else of defined(__ESL_ENABLE__) */
+ /* Only Core0 VPE0 do Core1~3 Boot-Slaves setup */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_untrap_Core123_done
+#if defined(UMOLYE_COSIM)
+ la $a0, core_sync_flag
+ li $a1, 1
+ sw $a1, 0($a0)
+#endif
+
+ INT_TRC LABEL_SET_BOOTSLAVE
+ /* Configure Core1 Boot-Slaves jump address */
+ // AP trigger, should use option
+ li $a0, BASE_MADDR_MDPERI_MDCFGCTL
+ li $a1, 0x1
+ sw $a1, 0x24($a0)
+
+ li $a0, 0x1
+ la $a1, INT_Vectors
+ la $a2, INT_Set_BootSlave
+ jalrc $a2
+#if !defined(__MD97_IS_2CORES__)
+ li $a0, 0x2
+ la $a1, INT_Vectors
+ la $a2, INT_Set_BootSlave
+ jalrc $a2
+
+ li $a0, 0x3
+ la $a1, INT_Vectors
+ la $a2, INT_Set_BootSlave
+ jalrc $a2
+#endif /*(__MD97_IS_2CORES__)*/
+
+#endif
+INT_untrap_Core123_done:
+
+INT_join_CH_domain:
+ /* Every Core's VPE0 join coherence domain */
+ INT_GET_VPEID $a2, $a0
+ bnezc $a0, INT_join_CH_domain_sync_done
+
+ INT_TRC LABEL_JOIN_CH_DOMAIN
+//Only core0 vpe0 set this bit, GCR control register offset 0x10,bit 3
+ INT_GET_CPUID $a2, $a0
+ bnezc $a0, set_shst_en_done
+ li $t2, GCR_CONFIG_ADDR
+ lw $t1, 0x10($t2)
+ ori $t1, 0x8
+ sw $t1, 0x10($t2)
+set_shst_en_done:
+
+ la $a2, join_domain
+ jalrc $a2
+
+#endif /* !defined(__SINGLE_CORE__) */
+
+#if defined(__SINGLE_CORE__)
+INT_join_domain_with_only_IOCU:
+ li $a2, (GCR_CONFIG_ADDR | CORE_LOCAL_CONTROL_BLOCK | GCR_CL_COHERENCE)
+ li $a0, 0x11
+ sw $a0, 0x0($a2)
+ ehb
+#endif /* __SINGLE_CORE__ */
+
+INT_join_CH_domain_sync_done:
+
+ /*
+ * Every Core's VPEs do INT_SystemReset_Checkfor abnormal reset scenario:
+ * Note: This function would use sp, thus put it after Phase1 temp stack init
+ *
+ */
+ INT_TRC LABEL_ABN_RST_CHECK
+ la $a0, ABN_RST_POOL
+
+ INT_GET_CPUID $a1, $a2
+ li $a1, 0x8
+ mul $a3, $a1, $a2
+ addu $a0, $a0, $a3
+ lw $a0, 0x0($a0)
+
+ la $a2, INT_SystemReset_Check
+ jalrc $a2
+
+
+INT_init_MPU:
+ /* Every Core's VPE0 do MPU init */
+
+ INT_TRC LABEL_SETUP_CDMMBASE
+ INT_GET_VPEID $a1, $a0
+ bnezc $a0, INT_init_VAS_done
+
+ // Enable C0_CDMMBASE
+ move $a1, $zero
+ li $a0, GCR_CDMM_ADDR
+ ext $a1, $a0, 15, 17
+ sll $a1, $a1, 11
+ ori $a1, $a1, (1<<10)
+
+ mtc0 $a1, C0_CDMMBASE
+ ehb
+
+ INT_TRC LABEL_MPU_INIT
+ /* <TODO> MPU configuration!! */
+ la $a2, MPU_Init
+ jalrc.hb $a2
+
+INT_init_VAS_done:
+ la $a2, INT_Initialize_Phase2
+ jalrc.hb $a2
+
+.size INT_Initialize_Phase1,.-INT_Initialize_Phase1
+.end INT_Initialize_Phase1
+
+/*********************************************************************
+ * [Phase2] C function @ VA: Bank9, Jumps here from VA: Bank0
+ * Note: 1. CFG0-4, per-VPE MMU are ready
+ * 2. CFG5 will be ready later
+ *********************************************************************/
+//.text
+.section "NONCACHED_ROCODE", "ax"
+.globl INT_Initialize_Phase2
+.ent INT_Initialize_Phase2
+INT_Initialize_Phase2:
+ INT_TRC LABEL_START_P2
+
+INT_P2_temp_stack_init:
+ /*
+ * Every Core's VPEs initialize temp sp for INT_Initialize_Phase2
+ * Note: 1. Every Core use different configuration
+ * 2. VA: Bank6 now is cacheable
+ * 3. [Tricky] per-Core VPE0 and VPE1 take the same sp, no concurrency because init_vpe1
+ */
+ INT_GET_COREID $a1, $a0
+
+ addiu $a0, $a0, 1
+ li $a1, BOOT_SYS_STACK_SIZE
+ mul $a1, $a1, $a0
+
+ la $a0, BOOT_SYS_Stack_Pool
+ add $a0, $a0, $a1
+
+ li $a1, TEMP_CACHE_BOOTSTACK_BANK
+ ins $a0, $a1, 28, 4
+ move $sp, $a0
+ li $a0, -16
+ add $sp, $sp, $a0 // reserve 16 bytes for caller save
+INT_P2_temp_stack_init_done:
+
+INT_init_regions:
+ /* Core0 VPE0 must do region init before other Core's VPE0 */
+
+ INT_GET_VPEID $a2, $a0
+ bnezc $a0, INT_init_regions_done
+
+ INT_GET_COREID $a2, $a0
+ bnezc $a0, INT_init_regions_core_others
+
+ INT_TRC LABEL_REGION_INIT
+ la $a2, INT_InitRegions_C
+ jalrc $a2
+
+ la $a0, INT_init_region_sync
+ li $a1, 0x1
+ sw $a1, 0x0($a0)
+ sync 0x3
+ bc INT_init_regions_done
+
+INT_init_regions_core_others:
+
+ /* Otehr Core's VPE0 wait until Core0 VPE0 done and then do region init */
+ la $a0, INT_init_region_sync
+ lw $a0, 0x0($a0)
+ beqzc $a0, INT_init_regions_core_others
+
+ INT_TRC LABEL_REGION_INIT
+ la $a2, INT_InitRegions_C
+ jalrc $a2
+
+INT_init_regions_done:
+ INT_TRC LABEL_REGION_INIT_DONE
+
+ /*
+ * Only Core0 VPE0 initialize global cache variables again,
+ * because they are cleaned after region init
+ */
+ INT_GET_CPUID $a0, $a0
+ bnezc $a0, INT_cache_var_init_done
+
+ la $a2, l1_cache_init_var
+ jalrc $a2
+
+ la $a2, l2_cache_init_var
+ jalrc $a2
+
+INT_cache_var_init_done:
+
+/*********************************************************************
+ * Config C0_EBASE to redirect exception to general_exception_handler
+ * Note: 1. Most of exceptions after this will go to general_ex_vector @ ex_hdlr_gcc.S, i.e.,
+ * "C0_EBASE[31:12]||0x180"
+ * 2. Most of exceptions before this will go to INT_BOOT_<X>_vector, i.e.,
+ * "C0_EBASE[31:12]||0x180"
+ *********************************************************************/
+INT_ebase_set:
+ INT_TRC LABEL_SET_C0_EBASE
+ la $a0, interrupt_vector // Get Exception Address
+ ins $a0, $zero, 0, 12 // zero write-as-zero fields
+ ori $a0, $a0, EBASE_WG // Set WG (bit 11) to make C0_EBASE[31:30] writeable
+ mtc0 $a0, C0_EBASE
+ ehb
+
+INT_init_sp:
+ /* Every Core's VPEs do initialize its sp */
+ INT_TRC LABEL_STACK_INIT
+
+ INT_GET_CPUID $a0, $a0
+ li $a1, 0x0
+ beqc $a0, $a1,CPU0_VPE0_STACK_INIT
+
+ li $a1, 0x1
+ beqc $a0, $a1,CPU0_VPE1_STACK_INIT
+
+ li $a1, 0x2
+ beqc $a0, $a1,CPU0_VPE2_STACK_INIT
+
+#if !defined(__SINGLE_CORE__)
+ li $a1, 0x4
+ beqc $a0, $a1,CPU1_VPE0_STACK_INIT
+
+ li $a1, 0x5
+ beqc $a0, $a1,CPU1_VPE1_STACK_INIT
+
+ li $a1, 0x6
+ beqc $a0, $a1,CPU1_VPE2_STACK_INIT
+#if !defined(__MD97_IS_2CORES__)
+ li $a1, 0x8
+ beqc $a0, $a1,CPU2_VPE0_STACK_INIT
+
+ li $a1, 0x9
+ beqc $a0, $a1,CPU2_VPE1_STACK_INIT
+
+ li $a1, 0xA
+ beqc $a0, $a1,CPU2_VPE2_STACK_INIT
+
+ li $a1, 0xC
+ beqc $a0, $a1,CPU3_VPE0_STACK_INIT
+
+ li $a1, 0xD
+ beqc $a0, $a1,CPU3_VPE1_STACK_INIT
+
+ li $a1, 0xE
+ beqc $a0, $a1,CPU3_VPE2_STACK_INIT
+#endif/*(__MD97_IS_2CORES__)*/
+
+#endif
+CPU0_VPE0_STACK_INIT:
+ la $sp, CORE0_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU0_VPE1_STACK_INIT:
+ la $sp, CORE0_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU0_VPE2_STACK_INIT:
+ la $sp, CORE0_VPE2_TC4_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_Stack_init_la_done
+
+CPU1_VPE0_STACK_INIT:
+ la $sp, CORE1_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU1_VPE1_STACK_INIT:
+ la $sp, CORE1_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU1_VPE2_STACK_INIT:
+ la $sp, CORE1_VPE2_TC4_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+#if !defined(__MD97_IS_2CORES__)
+CPU2_VPE0_STACK_INIT:
+ la $sp, CORE2_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU2_VPE1_STACK_INIT:
+ la $sp, CORE2_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU2_VPE2_STACK_INIT:
+ la $sp, CORE2_VPE2_TC4_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU3_VPE0_STACK_INIT:
+ la $sp, CORE3_VPE0_TC0_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU3_VPE1_STACK_INIT:
+ la $sp, CORE3_VPE1_TC2_SYS_STACK_PTR
+ bc INT_Stack_init_la_done
+
+CPU3_VPE2_STACK_INIT:
+ la $sp, CORE3_VPE2_TC4_SYS_STACK_PTR
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+INT_Stack_init_la_done:
+ lw $sp, 0x0($sp)
+ //li $a0, -16
+ //add $sp, $sp, $a0 //reserve 16 bytes for caller save
+ li $a0, 0xFFFFFFF0
+ and $sp, $sp, $a0
+INT_init_sp_done:
+
+INT_init_sp_guard_pattern:
+ /* Every Core's VPE0 set guard pattern to its sys stack */
+ INT_GET_VPEID $a0, $a1
+ bnezc $a1, INT_init_sp_guard_done
+
+ ext $a0, $a0, 2, 2
+ la $a1, INT_SetSysStack_GuardPattern
+ jalrc $a1
+
+
+INT_init_sp_guard_done:
+
+INT_init_vpe1_next:
+ /* Every Core's VPE0 do init_vpe1 to enable VPE1 */
+
+#if (__MULTI_VPE_EN__ != 0)
+ INT_TRC LABEL_INIT_VPE1
+
+ INT_GET_VPEID $a2, $a0
+ /*vpe1 do init_vpe2*/
+ li $a1, 0x1
+ beqc $a0, $a1, INT_init_vpe2
+ nop
+ /*vpe0 do init_vpe1 and init vpe2*/
+ bnezc $a0, INT_init_vpe1_done
+
+ la $a2, init_vpe0
+ jalrc $a2
+
+ la $a2, init_vpe1 // Set up MT ASE vpe1 to execute this boot code also.
+ jalrc $a2
+ bc INT_init_vpe1_done
+
+INT_init_vpe2:
+ la $a2, init_vpe2 // Set up MT ASE vpe2 to execute this boot code also.
+ jalrc $a2
+
+#endif
+
+INT_init_vpe1_done:
+
+INT_init_done:
+ la $ra, all_done // If main return then go to all_done:.
+
+INT_cpu_init_done:
+
+ li $a0, 0xA5A55A5A
+ la $a2, INT_init_stage
+ sw $a0, 0x0($a2)
+
+ INT_TRC LABEL_INIT_ASM_DONE
+#if defined(KTEST_RTOS_TEST)
+ la $a2, KTEST_Initialize // Let KTEST setup OS
+#else
+ la $a2, kal_system_init
+#endif
+ jalrc $a2
+
+all_done:
+ // Looks like main returned. Just busy wait spin.
+ bc all_done
+
+.size INT_Initialize_Phase2,.-INT_Initialize_Phase2
+.end INT_Initialize_Phase2
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/idle_service.c b/mcu/driver/sys_drv/init/src/md97p/idle_service.c
new file mode 100644
index 0000000..9aa0f1c
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/idle_service.c
@@ -0,0 +1,1676 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_service.c
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file provides idle task flow related APIs to enter dormant.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef __MTK_TARGET__
+
+#include "drv_comm.h"
+#include "dcm_sw.h"
+#include "idle_service.h"
+
+#include "kal_public_api.h"
+#include "kal_internal_api.h"
+#include "kal_hrt_api.h"
+#include "mips_ia_utils.h"
+
+#include "us_timer.h"
+#include "intrCtrl.h" /* IRQ Mask/Unmask */
+#include "sync_data.h"
+#include "SST_intrCtrl.h"
+
+#include "RM_public.h"
+#include "sleepdrv_interface.h"
+#include "drv_rstctl.h"
+#include "ostd_public.h"
+#include "task_config.h"
+#include "ptp_public.h"
+#include "pll.h"
+#include "mdmcu_pmu.h"
+
+#if defined (__MODEM_CCCI_EXIST__)
+#include "ccci.h"
+#include "ex_mem_manager_public.h"
+#endif
+
+/* From dormant */
+extern void dormant_mode_activate(void);
+extern void dormant_mode_init(void);
+extern kal_uint32 Dormant_Service_Get_Dormant_Abort(kal_uint32 core_id);
+
+
+/* From MDCIRQ and __MDCIRQ_OSIPI_SPECIAL_FLOW__ macro */
+#include "drv_mdcirq.h"
+extern void interrupt_sleep_init(kal_uint32 vpe_id);
+
+/* From SPV */
+#if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+extern void SPV_core_idlemeter_enter(kal_uint32 coreid);
+extern void SPV_core_idlemeter_exit(kal_uint32 coreid);
+#endif // #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+
+/* The Macro to do IT test */
+//#define IDLE_IT_TEST
+
+/* The Macro to do WAIT duration time check */
+//#define WAIT_DURATION_CHECK
+
+/* DCM_SUPPORT define in dcm_sw.h */
+#if defined(DCM_SUPPORT)
+ #define IFDEF_DCM(def_statement, undef_statement) def_statement
+#else /* Not Support DCM. */
+ #define IFDEF_DCM(def_statement, undef_statement) undef_statement
+#endif /* DCM_SUPPORT */
+
+/* Define in project's makefile (...), TRUE: CPU would execute DORMANT flow. FALSE: No DORMANT flow. */
+#if defined(MTK_SLEEP_ENABLE)
+ #define LOWPWER_ENTER_PAUSE_MODE
+ #define IFDEF_PAUSE_FLOW(def_statement, undef_statement) def_statement
+#else
+ #define IFDEF_PAUSE_FLOW(def_statement, undef_statement) undef_statement
+#endif
+
+#if defined(__PRODUCTION_RELEASE__)
+ #define IFDEF_PRODUCTION(x)
+#else /* __PRODUCTION_RELEASE__ */
+/* under construction !*/
+#endif /* __PRODUCTION_RELEASE__ */
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+#include "drv_vpe_irq.h"
+kal_uint32 idle_service_FMA_not_ready_time[MDCIRQ_TOTAL_VPE_NUM] = {0};
+kal_uint32 idle_service_FMA_ready_time[MDCIRQ_TOTAL_VPE_NUM] = {0};
+#endif
+
+/*
+Below for simple test.
+*//* Remember modify intrCtrl_MT6297.h before test. */
+#if defined(IDLE_IT_TEST)
+kal_uint32 IDLE_IT_InitDone = KAL_FALSE;
+kal_uint32 IDLE_IT_IRQ_count[VPE_NUMBER] = {0};
+kal_timerid IDLE_IT_timer_id;
+kal_uint32 timer_offset = 1;
+
+#define IRQ_SW_VPE0_TEST IRQ_SW_LISR41_CODE /* IRQ ID 321 */
+#define IRQ_SW_VPE1_TEST (IRQ_SW_VPE0_TEST+1) /* IRQ ID 322 */
+#define IRQ_SW_VPE2_TEST (IRQ_SW_VPE1_TEST+1) /* IRQ ID 323 */
+#define IRQ_SW_VPE3_TEST (IRQ_SW_VPE2_TEST+1) /* IRQ ID 324 */
+#define IRQ_SW_VPE4_TEST (IRQ_SW_VPE3_TEST+1) /* IRQ ID 325 */
+#define IRQ_SW_VPE5_TEST (IRQ_SW_VPE4_TEST+1) /* IRQ ID 326 */
+#define IRQ_SW_VPE6_TEST (IRQ_SW_VPE5_TEST+1) /* IRQ ID 327 */
+#define IRQ_SW_VPE7_TEST (IRQ_SW_VPE6_TEST+1) /* IRQ ID 328 */
+#define IRQ_SW_VPE8_TEST (IRQ_SW_VPE7_TEST+1) /* IRQ ID 329 */
+#define IRQ_SW_VPE9_TEST (IRQ_SW_VPE8_TEST+1) /* IRQ ID 330 */
+#define IRQ_SW_VPE10_TEST (IRQ_SW_VPE9_TEST+1) /* IRQ ID 331 */
+#define IRQ_SW_VPE11_TEST (IRQ_SW_VPE10_TEST+1) /* IRQ ID 332 */
+
+static void Idle_Service_IT_timer_cb()
+{
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE1_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE2_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE3_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE4_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE5_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE6_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE7_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE8_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE9_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE10_TEST);
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_VPE11_TEST);
+
+ kal_cancel_timer(IDLE_IT_timer_id);
+ kal_set_timer(IDLE_IT_timer_id, Idle_Service_IT_timer_cb, NULL, KAL_TICKS_10_MSEC*timer_offset, 0);
+ timer_offset++;
+}
+
+void Idle_Service_IT_vpe_X_lisr(kal_uint32 irqx)
+{
+ IDLE_IT_IRQ_count[irqx-IRQ_SW_VPE0_TEST]++;
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void Idle_Service_IT_test_init(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ if(vpe_id==0)
+ {/* only VPE 0 do the init */
+
+ /* Register ISR for VPE0 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE0_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_0");
+ //IRQSensitivity(IRQ_SW_VPE0_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE0_TEST);
+
+ /* Register ISR for VPE1 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE1_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_1");
+ //IRQSensitivity(IRQ_SW_VPE1_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE1_TEST);
+
+ /* Register ISR for VPE2 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE2_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_2");
+ //IRQSensitivity(IRQ_SW_VPE2_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE2_TEST);
+
+ /* Register ISR for VPE3 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE3_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_3");
+ //IRQSensitivity(IRQ_SW_VPE3_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE3_TEST);
+
+ /* Register ISR for VPE4 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE4_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_4");
+ //IRQSensitivity(IRQ_SW_VPE4_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE4_TEST);
+
+ /* Register ISR for VPE5 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE5_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_5");
+ //IRQSensitivity(IRQ_SW_VPE5_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE5_TEST);
+
+ /* Register ISR for VPE6 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE6_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_6");
+ //IRQSensitivity(IRQ_SW_VPE6_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE6_TEST);
+
+ /* Register ISR for VPE7 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE7_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_7");
+ //IRQSensitivity(IRQ_SW_VPE7_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE7_TEST);
+
+ /* Register ISR for VPE8 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE8_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_8");
+ //IRQSensitivity(IRQ_SW_VPE8_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE8_TEST);
+
+ /* Register ISR for VPE9 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE9_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_9");
+ //IRQSensitivity(IRQ_SW_VPE9_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE9_TEST);
+
+ /* Register ISR for VPE10 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE10_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_10");
+ //IRQSensitivity(IRQ_SW_VPE10_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE10_TEST);
+
+ /* Register ISR for VPE11 to test */
+ //IRQ_Register_LISR(IRQ_SW_VPE11_TEST, Idle_Service_IT_vpe_X_lisr, "IDLE_IT_11");
+ //IRQSensitivity(IRQ_SW_VPE11_TEST, LEVEL_SENSITIVE);/* level trigger */
+ IRQUnmask(IRQ_SW_VPE11_TEST);
+
+ IDLE_IT_timer_id = kal_create_timer("IDLE_IT_timer");
+ kal_set_timer(IDLE_IT_timer_id, Idle_Service_IT_timer_cb, NULL, KAL_TICKS_5_SEC, 0);
+
+ IDLE_IT_InitDone = KAL_TRUE;
+ }
+}
+#endif/*IDLE_IT_TEST*/
+/*
+Above for simple test.
+*/
+
+kal_uint32 IDLEenterSleep = 1; // Force lock sleep. 1: Could enter DORMANT. 0: Couldn't enter DORMANT.
+kal_uint32 Idle_Service_InitDone = KAL_FALSE; /* Idle Service init done or not, only CORE 0 VPE 0 init in Idle_Service_Init(). */
+kal_uint32 idle_service_hrt_DI_start[CORE_NUMBER] = {0}, idle_service_hrt_DI_end[CORE_NUMBER] = {0}, idle_service_hrt_DI_dur[CORE_NUMBER] = {0};/* Use to Qbit check for HRT domain. */
+//kal_uint32 idle_service_dor_2nd_enter_wait_frc = 0, idle_service_dor_2nd_leave_wait_frc = 0, idle_service_dor_2nd_duration = 0;
+
+kal_uint32 idle_vpe_x_state[VPE_NUMBER] = {0};/* The CIRQ VPE state for each idle task */
+kal_uint32 idle_core_x_vpe_0_tc_grp[CORE_NUMBER] = {0};/* Record the original TC0 group before raise its group(priority) for HRT real time check. */
+
+kal_uint32 idle_emm_start_address;
+kal_uint32 idle_emm_size;
+kal_uint32 idle_emm_init_done;
+
+typedef struct
+{
+ IDLE_ACTION_INDEX action;
+ kal_uint32 frc_ust;
+} IDLE_SERVICE_STEP;
+
+IDLE_SERVICE_STEP idle_service_step[VPE_NUMBER][IDLE_SERVICE_STEP_MAX];
+kal_uint32 idle_service_step_index[VPE_NUMBER] = {0};
+
+typedef struct
+{
+ kal_uint32 idle_service_enter_dormant_frc;/* The us time when entering DORMANT. */
+ kal_uint32 idle_service_dor_abort_leave_dormant_frc; /* The us time when leaving DORMANT due to dormant abort. */
+ kal_uint32 idle_service_leave_dormant_frc; /* The us time when leaving DORMANT. */
+}IDLE_SERVICE_DORMANT_LOG;/* Per-Core's enter/leave dormant time. */
+
+IDLE_SERVICE_DORMANT_LOG idle_service_core_x_dormant_time[CORE_NUMBER];
+
+kal_uint32 idle_service_vpe_x_leave_dormant_frc[VPE_NUMBER] = {0};/* The us time when Each VPE leave DORMANT */
+
+/* Per-CORE's VPE init done or not. CORE could enter DORMANT after This-CORE's all VPE init done.
+Init to 1 in Idle_Service_Init(), clear to 0 before entering DORMANT.
+When This-CORE's VPE 1/2 leave DORMANT, it would config to 1 in Idle_Service_vpe1_vpe2_dormant_leave() again to confirm it is full restore from DORMANT.
+Note: Per-CORE's VPE0 always keep init done after Idle_Service_Init() due to he is the master. */
+volatile kal_uint32 idle_service_vpe_x_init_state[VPE_NUMBER] = {0}; // 1:init doen, 0; not init
+
+kal_uint32 idle_service_enter_wait_time[VPE_NUMBER];
+kal_uint32 idle_service_leave_wait_time[VPE_NUMBER];
+
+/* We use a cacheable parameter to let Per-CORE's VPE 0 could know his VPE1 and VPE2 is in "wait" or not. */
+volatile kal_uint32 idle_service_vpe_x_in_wait_state[VPE_NUMBER]={0};
+
+/* We use a cacheable parameter to let CORE0's VPE0 could know CORE1~3 is in "DORMANT" or not. */
+volatile kal_uint32 idle_service_CoreStatus[CORE_NUMBER] = {0}; //0: normal, 1: WAIT, 2: dormant
+
+/* For debug, to confirm the real dormant/dormant abort flow is right. */
+kal_uint32 idle_service_vpe_real_dormant_times[VPE_NUMBER] = {0};
+
+/*****************************************************************************
+ * Internal Function *
+ *****************************************************************************/
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /*------------------------------------------------------------------------
+ * void idle_service_mask_vpe_irq
+ * Purpose: Mask cirq trigger to specify vpe in Idle_Service_Handler(), this function is only designed for Idle_Service_Handler().
+ * Parameters:
+ * Input: kal_uint32 core_id
+ * kal_uint32 vpe_id
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 Idle_Service_Handler(), Only Per-CORE's VPE 0 could call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+static void idle_service_mask_vpe_irq(kal_uint32 core_id, kal_uint32 vpe_id)
+{
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+
+ /* VPE0 would mask VPE1 and VPE2's IRQ and check HRT Qbit, so we raise up TC0's priority to avoid VPE1/VPE2 occupy pipeline. */
+ idle_core_x_vpe_0_tc_grp[core_id] = miu_save_and_set_c0_tcschedule_grp(HW_ITC_GRP);
+
+ /* Note: Maybe we should raise bus ultra signal here due to normal latency 1us. (EMI_latency) */
+
+ if(0 == core_id)
+ {/* CORE0 VPE0 */
+
+ /* Mask VPE2's CIRQ by set dormant state */
+ drv_mdcirq_set_dormant_state(vpe_id+2);
+
+ /* Mask VPE1's CIRQ by set dormant state */
+ drv_mdcirq_set_dormant_state(vpe_id+1);
+ }
+ else
+ {/* other CORE's VPE0 */
+
+ /* Mask CORE's VPE0 & VPE1 & VPE2's CIRQ by set dormant state */
+ drv_mdcirq_set_dormant_state(vpe_id+2);/* To avoid spurious interrupt, we mask CORE's VPE2 IRQ first. */
+ drv_mdcirq_set_dormant_state(vpe_id+1);/* To avoid spurious interrupt, we mask CORE's VPE1 IRQ first. */
+ drv_mdcirq_set_dormant_state(vpe_id);
+ }
+
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ /* Mask VPE0 & VPE1 & VPE2's OSIRQ */
+ drv_mdcirq_set_OSIPI_Mask(vpe_id+2);
+ drv_mdcirq_set_OSIPI_Mask(vpe_id+1);
+ drv_mdcirq_set_OSIPI_Mask(vpe_id);
+ #endif
+
+ idle_service_hrt_DI_start[core_id] = ust_get_current_time();
+}
+
+ /*------------------------------------------------------------------------
+ * void idle_service_unmask_vpe_irq
+ * Purpose: Unmask cirq trigger to specify vpe in Idle_Service_Handler(), this function is only designed for Idle_Service_Handler().
+ * Parameters:
+ * Input: kal_uint32 core_id
+ * kal_uint32 vpe_id
+ * kal_uint32 Check_hrt_Qbit: Check HRT Qbit or not after enable VPE1 and VPE2's IRQ.
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 Idle_Service_Handler(), Only Per-CORE's VPE 0 could call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+static void idle_service_unmask_vpe_irq(kal_uint32 core_id, kal_uint32 vpe_id, kal_uint32 Check_hrt_Qbit)
+{
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ /* Unmask VPE0 & VPE1 & VPE2's OSIRQ */
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id+2);
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id+1);
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id);
+ #endif
+
+ if (0 == core_id)
+ {/* CORE0 VPE0 */
+
+ /* Unmask VPE1's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id+1);
+
+ /* Unmask VPE2's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id+2);
+ }
+ else
+ {/* other CORE's VPE0 */
+
+ /* Unmask CORE's VPE0 & VPE1 & VPE2's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id);
+ drv_mdcirq_clear_dormant_state(vpe_id+1);
+ drv_mdcirq_clear_dormant_state(vpe_id+2);
+ }
+
+ if (Check_hrt_Qbit==KAL_TRUE)
+ {/* Check HRT Qbit due to we disable VPE1 and VPE2's IRQ */
+
+ idle_service_hrt_DI_end[core_id] = ust_get_current_time();
+ idle_service_hrt_DI_dur[core_id] = ust_us_duration(idle_service_hrt_DI_start[core_id], idle_service_hrt_DI_end[core_id]);
+
+ if( (idle_service_hrt_DI_dur[core_id] > query_Qbits_criteria_HRT_us()))
+ {
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+ IFDEF_PRODUCTION(EXT_ASSERT(0, idle_service_hrt_DI_dur[core_id], idle_service_hrt_DI_start[core_id], query_Qbits_criteria_HRT_us()));
+ }
+
+#if defined(__PRODUCTION_RELEASE__)
+ /* No Check in User load */
+#else /* Eng load */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __PRODUCTION_RELEASE__ */
+
+ /* VPE0 would mask VPE1 and VPE2's IRQ and check HRT Qbit, so we restore TC0's priority after enable VPE1 and VPE2's IRQ and HRT check. */
+ /* Note: Before entering DORMANT, we would restore TC0's priority and don't check HRT Qbit after dormant. */
+ miu_save_and_set_c0_tcschedule_grp(idle_core_x_vpe_0_tc_grp[core_id]);
+
+ /* Note: Maybe we should restore bus ultra signal here due to normal latency 1us. (EMI_latency) */
+
+ }
+
+}
+
+ /*------------------------------------------------------------------------
+ * void idle_service_unmask_vpe_irq_leave_dormant
+ * Purpose: Unmask cirq trigger to specify vpe when leaving DORMANT.
+ * This function copy from idle_service_unmask_vpe_irq() and could be use for each VPE.
+ * This function is only designed for Idle_Service_Handler() and Idle_Service_vpe1_vpe2_dormant_leave().
+ * Parameters:
+ * Input: kal_uint32 vpe_id
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 Idle_Service_Handler() and Per-CORE's VPE1 and VPE2's Idle_Service_vpe1_vpe2_dormant_leave().
+ *
+ *------------------------------------------------------------------------
+ */
+static void idle_service_unmask_vpe_irq_leave_dormant(kal_uint32 vpe_id)
+{
+ /* Set VPE's state to his VPE state */
+ /* The state in GCR would be reset after dormant, so we must re-init it before receiving IRQ,
+ or it would ASSERT in drv_mdcirq_Restore_VPE_state() of isrC_Main(). */
+ drv_mdcirq_Set_VPE_state(vpe_id, idle_vpe_x_state[vpe_id]);
+
+ /* Unmask VPE's CIRQ by clear dormant state */
+ drv_mdcirq_clear_dormant_state(vpe_id);
+
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ /* Unmask VPE's OSIRQ */
+ drv_mdcirq_clear_OSIPI_Mask(vpe_id);
+ #endif
+
+}
+
+void idle_service_core0_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void idle_service_core1_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void idle_service_core2_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+void idle_service_core3_vpe0_leave_wait_lisr(kal_uint32 irqx)
+{
+ DEBUG_ASSERT(0);
+ MDCIRQ_Deactivate_LISR_without_ITC(irqx);
+}
+
+#endif//LOWPWER_ENTER_PAUSE_MODE
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+/*------------------------------------------------------------------------
+* void Idle_Service_Polling_FMA_Status
+* Purpose: APOLLO FMA couln't sync in 2T 26M after WFI. We need to confirm FMA ready and go.
+* Parameters:
+* Input: None.
+*
+* Output: None.
+* returns : None.
+* Note : Called in Per-VPE after WAIT.
+* Normal/HRT domain: Called in mips_enter_wait_mode()
+* Critical HRT domain: Called in Idle_Service_Handler_Wait()
+*------------------------------------------------------------------------
+*/
+static void Idle_Service_Polling_FMA_Status(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ /* Confirm FMA ready and go. */
+ if(fma_sync_status()==0)
+ {//FMA is not ready
+ idle_service_FMA_not_ready_time[vpe_id] = ust_get_current_time_source();
+ while(fma_sync_status()==0)
+ {
+ miu_yield(-1);/*Release Pipeline*/
+ }
+ idle_service_FMA_ready_time[vpe_id] = ust_get_current_time();
+ }
+}
+#endif
+
+/*****************************************************************************
+ * Public Function for users *
+ *****************************************************************************/
+#if defined (__MODEM_CCCI_EXIST__)
+kal_bool IDLE_EMM_WriteDbgInfo(kal_uint32 index, void* addr)
+{
+ if (!idle_emm_init_done)
+ {
+ return KAL_FALSE;
+ }
+ #if defined(__MTK_TARGET__)
+ if (addr == NULL || ((kal_uint32)addr % 4 !=0) || index > IDLE_EMM_INDEX_MAX)
+ {
+ return KAL_FALSE;
+ }
+
+ *((kal_uint32 *)(idle_emm_start_address + (index<<2))) = *((kal_uint32 *)addr);
+ //MM_Sync();
+ #endif
+ return KAL_TRUE;
+}
+#endif
+
+void idle_service_step_logging(kal_uint32 vpe_id, IDLE_ACTION_INDEX step, kal_bool Log_To_EMM)
+{
+ idle_service_step_index[vpe_id]++;
+ if(idle_service_step_index[vpe_id]>=IDLE_SERVICE_STEP_MAX)
+ {
+ idle_service_step_index[vpe_id] = 0;
+ }
+
+ idle_service_step[vpe_id][idle_service_step_index[vpe_id]].action = step;
+ idle_service_step[vpe_id][idle_service_step_index[vpe_id]].frc_ust = ust_get_current_time();
+#if defined (__MODEM_CCCI_EXIST__)
+ if(Log_To_EMM == KAL_TRUE)
+ {/* To reduce UC transaction to EMI, only important log we log to EMM. */
+ IDLE_EMM_WriteDbgInfo(IDLE_EMM_VPE0_IDLE_TASK_STEPLOGGING + (vpe_id<<1), &idle_service_step[vpe_id][idle_service_step_index[vpe_id]].action);
+ IDLE_EMM_WriteDbgInfo(IDLE_EMM_VPE0_IDLE_TASK_FMA + (vpe_id<<1), &idle_service_step[vpe_id][idle_service_step_index[vpe_id]].frc_ust);
+ }
+#endif
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Prepare_WAIT
+ * Purpose: Per-Core Critical HRT domain trigger IRQ to his VPE0 and set WAIT variable.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-Core Critical HRT domain IdleTask and only execute once.
+ * Called in isrC_Main() @ isrentry.c
+ * Note: In our design, Per-Core VPE0 must be Normal domain, so Per-Core VPE0 couldn't call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Prepare_WAIT(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 vpe_0_1_2 = vpe_id%PER_CORE_VPE_NUM;/* To know it is Per-Core VPE0/VPE1/VPE2. */
+
+ if(kal_get_current_domain()!=KAL_DOMAIN_CHRT||vpe_0_1_2==0)
+ {/* Only Critical HRT domain could run this function. Per-Core VPE0 couldn't call this function. */
+ ASSERT(0);
+ }
+
+ /* Note: We didn't DI in Per-Core VPE2's idle task, it would be interrupted any time.
+ But isrC_Main() call this function during DI(EXL==1).*/
+ idle_service_step_logging(vpe_id, IDLE_WFI_WAIT_ENTER, KAL_FALSE);
+ idle_service_enter_wait_time[vpe_id] = ust_get_current_time();
+#if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER + (vpe_id<<1)), (void*)&idle_service_enter_wait_time[vpe_id]);
+#endif
+
+ /* Set the WAIT parameter to let his VPE0 know the VPE is in WAIT. */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_TRUE;
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id = kal_get_current_core_id();
+ /* Trigger IRQ to his VPE0 */
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_CORE0_VPE0_LEAVE_WAIT+core_id);
+#endif
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Check_Init_Done
+ * Purpose: Check Idle Service related init is complete or not .
+ * Parameters:
+ * Input: kal_uint32 vpe_id.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in each VPE IdleTask.
+ * Per-CORE's VPE0 only execute once.
+ * Per-CORE's VPE1/2 would execute many time(due to re-run while IdleTask after DORMANT).
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Check_Init_Done(kal_uint32 vpe_id)
+{
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ //DEBUG_EXT_ASSERT3((vpe_id%PER_CORE_VPE_NUM==0), vpe_id, Idle_Service_InitDone, 0x8967);
+
+ EXT_ASSERT((idle_service_vpe_x_init_state[vpe_id]==1&&Idle_Service_InitDone == KAL_TRUE), vpe_id, idle_service_vpe_x_init_state[vpe_id], Idle_Service_InitDone);
+#endif
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Init
+ * Purpose: Init dormant related functions .
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE 0 IdleTask init function. Only Per-CORE's VPE 0 could call this function.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Init(void)
+{
+
+#if defined(IDLE_IT_TEST)
+ Idle_Service_IT_test_init();
+#endif
+
+/* For using LPM to verify DCM */
+#if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Init();
+#endif
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id, vpe_id, i;
+ dormant_mode_init();
+
+ core_id = kal_get_current_core_id();
+ vpe_id = kal_get_current_vpe_id();
+
+ if((vpe_id%PER_CORE_VPE_NUM) == 0)
+ {/* All CORE's VPE 0 */
+ idle_service_CoreStatus[core_id] = IDLE_STATUS_NORMAL;
+
+ /* Per-CORE's VPE1 and VPE2 init done or not. (Per-CORE's VPE0 help VPE1 and VPE2 init done to confirm they can enter DORMANT at first time.) */
+ idle_service_vpe_x_init_state[vpe_id+1] = 1;
+ idle_service_vpe_x_init_state[vpe_id+2] = 1;
+
+ if(0 == core_id)
+ {/* CORE 0 VPE 0 */
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ kal_bool QueryStatus;
+ QueryStatus = EMM_DirInfo_Query(EMM_DIRECT_WRITE_IDLETASK, &idle_emm_start_address, &idle_emm_size);
+ if( QueryStatus == KAL_TRUE)
+ {
+ idle_emm_init_done = 1;
+ if(IDLE_EMM_INDEX_MAX>(idle_emm_size>>2))
+ {
+ IFDEF_PRODUCTION(EXT_ASSERT(0, IDLE_EMM_INDEX_MAX, idle_emm_start_address, idle_emm_size));
+ }
+ }
+ #endif
+
+ /* Get each VPE state for idle task. */
+ for(i=0;i<VPE_NUMBER;i++)
+ {
+ idle_vpe_x_state[i] = kal_get_idle_task_priority(i);
+ }
+
+ /* Register ISR for Per-CORE VPE1/VPE2 trigger to his VPE0 */
+ //IRQ_Register_LISR(IRQ_SW_CORE0_VPE0_LEAVE_WAIT, idle_service_core0_vpe0_leave_wait_lisr, "IDLE_0");
+ //IRQSensitivity(IRQ_SW_CORE0_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT);
+
+ //IRQ_Register_LISR(IRQ_SW_CORE1_VPE0_LEAVE_WAIT, idle_service_core1_vpe0_leave_wait_lisr, "IDLE_1");
+ //IRQSensitivity(IRQ_SW_CORE1_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE1_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE1_VPE0_LEAVE_WAIT);
+
+ //IRQ_Register_LISR(IRQ_SW_CORE2_VPE0_LEAVE_WAIT, idle_service_core2_vpe0_leave_wait_lisr, "IDLE_2");
+ //IRQSensitivity(IRQ_SW_CORE2_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE2_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE2_VPE0_LEAVE_WAIT);
+
+ //IRQ_Register_LISR(IRQ_SW_CORE3_VPE0_LEAVE_WAIT, idle_service_core3_vpe0_leave_wait_lisr, "IDLE_3");
+ //IRQSensitivity(IRQ_SW_CORE3_VPE0_LEAVE_WAIT, LEVEL_SENSITIVE);/* level trigger */
+ //IRQUnmask(IRQ_SW_CORE3_VPE0_LEAVE_WAIT);
+ IRQMask(IRQ_SW_CORE3_VPE0_LEAVE_WAIT);
+
+ //core0 Idle_Service_Init should be ready before enter sleep
+ Idle_Service_InitDone = KAL_TRUE;
+ }
+
+ idle_service_vpe_x_init_state[vpe_id] = 1;//Per-CORE's VPE0 init done.
+
+ }
+ else
+ {/* All CORE's VPE1/VPE2 */ /* Only Per-CORE's VPE0 could run this function */
+ ASSERT(0);
+ }
+#endif
+}
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE) && defined(WAIT_DURATION_CHECK)
+#define ILLEGAL_WAIT_TIME 3000000 /* 3 seconds*/
+kal_uint32 vpe_leave_wait_time[VPE_NUMBER] = {0};
+kal_uint32 vpe_wait_duration[VPE_NUMBER] = {0};
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_WaitTime_Check
+ * Purpose: Check the WAIT time duration.
+ * Parameters:
+ * Input: core_id, vpe_id.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE 0 IdleTask==>Idle_Service_Handler()-->mips_enter_wait_mode(void).
+ * Only Per-CORE's VPE 0 could call this function.
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_WaitTime_Check(kal_uint32 core_id, kal_uint32 vpe_id)
+{/* If all VPE on this CORE overlap wait more than 3 seconds, ASSERT!! */
+ kal_uint32 core_1st_leave_wait_time = 0xffffffff, core_final_enter_wait_time = 0;
+ kal_uint32 i = 0;
+ kal_uint32 core_vpe0 = vpe_id, core_vpe1 = vpe_id+1, core_vpe2 = vpe_id+2;
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+ //1. Get leave wait time
+ /* Get the leave wait time for VPE0 */
+ vpe_leave_wait_time[core_vpe0] = idle_service_leave_wait_time[core_vpe0];
+
+ /* Get the leave wait time for VPE1 */
+ if(idle_service_vpe_x_in_wait_state[core_vpe1]==KAL_TRUE)
+ {//This CORE's VPE1 is still in wait
+ vpe_leave_wait_time[core_vpe1] = ust_get_current_time();
+ }
+ else
+ {//This CORE's VPE1 already leave wait
+ vpe_leave_wait_time[core_vpe1] = idle_service_leave_wait_time[core_vpe1];
+ }
+
+ /* Get the leave wait time for VPE2 */
+ if(idle_service_vpe_x_in_wait_state[core_vpe2]==KAL_TRUE)
+ {//This CORE's VPE2 is still in wait
+ vpe_leave_wait_time[core_vpe2] = ust_get_current_time();
+ }
+ else
+ {//This CORE's VPE2 already leave wait
+ vpe_leave_wait_time[core_vpe2] = idle_service_leave_wait_time[core_vpe2];
+ }
+
+ //2. Get wait duration time
+ vpe_wait_duration[core_vpe0] = ust_us_duration(idle_service_enter_wait_time[core_vpe0], vpe_leave_wait_time[core_vpe0]);
+ vpe_wait_duration[core_vpe1] = ust_us_duration(idle_service_enter_wait_time[core_vpe1], vpe_leave_wait_time[core_vpe1]);
+ vpe_wait_duration[core_vpe2] = ust_us_duration(idle_service_enter_wait_time[core_vpe2], vpe_leave_wait_time[core_vpe2]);
+
+ //3. Check all VPE violation
+ if(vpe_wait_duration[core_vpe0]>ILLEGAL_WAIT_TIME&&vpe_wait_duration[core_vpe1]>ILLEGAL_WAIT_TIME&&vpe_wait_duration[core_vpe2]>ILLEGAL_WAIT_TIME)
+ {/* All VPE violation. ==> Get the overlap time. */
+
+ //3-1 Get the core_final_enter_wait_time
+ for(i=0;i<PER_CORE_VPE_NUM;i++)
+ {
+ if(idle_service_enter_wait_time[vpe_id+i] > core_final_enter_wait_time)
+ {
+ core_final_enter_wait_time = idle_service_enter_wait_time[vpe_id+i];
+ }
+ }
+
+ //3-2 Get the core_1st_leave_wait_time
+ for(i=0;i<PER_CORE_VPE_NUM;i++)
+ {
+ if(vpe_leave_wait_time[vpe_id+i] < core_1st_leave_wait_time)
+ {
+ core_1st_leave_wait_time = vpe_leave_wait_time[vpe_id+i];
+ }
+ }
+
+ //3-3 Final check
+ if(core_1st_leave_wait_time < core_final_enter_wait_time)
+ {
+ /* Timer overflow/non-overlap, bypass this time */
+ }
+ else
+ {
+ if( (core_1st_leave_wait_time-core_final_enter_wait_time)>ILLEGAL_WAIT_TIME )
+ {
+ EXT_ASSERT(0, core_1st_leave_wait_time, core_final_enter_wait_time, ILLEGAL_WAIT_TIME);
+ }
+ }
+
+ }
+ else
+ {
+ /* Someone pass, do nothing. */
+ }
+
+
+}
+#endif
+
+ /*------------------------------------------------------------------------
+ * void mips_enter_wait_mode
+ * Purpose: Enter wait mode.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Idle_Service_Handler() by Per-core's VPE0 and Called in Idle_Service_Handler_Slave() by HRT Domain VPE.
+ *
+ *------------------------------------------------------------------------
+ */
+void mips_enter_wait_mode(void)
+{
+ kal_uint32 vpe_id = 0, Idle_CP0_status = 0;
+ vpe_id = kal_get_current_vpe_id();
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id = kal_get_current_core_id();
+ kal_uint32 vpe_0_1_2 = vpe_id%PER_CORE_VPE_NUM;/* To know it is Per-Core VPE0/VPE1/VPE2. */
+#endif
+
+ //disable WDT
+ drv_rstctl_clr_check_bit((vpeid_e)vpe_id);
+
+ idle_service_enter_wait_time[vpe_id] = ust_get_current_time();
+#if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER + (vpe_id<<1)), (void*)&idle_service_enter_wait_time[vpe_id]);
+#endif
+
+ /* Set the WAIT parameter to know this VPE is in WAIT. */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_TRUE;
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ MM_Sync();/* Add this sync to avoid SHAOLIN run out of order */
+
+ if(vpe_0_1_2!=0)
+ {/* Per-CORE's VPE1/VPE2(HRT domain) would run. */
+
+ /* Trigger IRQ to his VPE0 */
+ MDCIRQ_Activate_LISR_without_ITC(IRQ_SW_CORE0_VPE0_LEAVE_WAIT+core_id);
+ }
+#endif
+
+ /* Note: Don't add function here due to we should let "idle_service_vpe_x_in_wait_state[vpe_id] = KAL_TRUE" close WAIT. */
+
+ /* We must DI, then enter WAIT. */
+ Idle_CP0_status = miu_mfc0(MIU_C0_STATUS);
+ if((Idle_CP0_status&0x1)!=0x0)
+ {
+ EXT_ASSERT(0, vpe_id, Idle_CP0_status, 0);
+ }
+
+ /* "WAIT" instruction */
+ miu_wait();
+
+ /* Note!! If per-core's VPE1 recover from DORMANT, it wouldn't run below.
+ It would run dormant recover... -> Idle_Service_vpe1_vpe2_dormant_leave() */
+
+ /* leave WAIT */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_FALSE;
+
+ idle_service_leave_wait_time[vpe_id] = ust_get_current_time_source();
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ /* Confirm FMA ready and go. */
+ Idle_Service_Polling_FMA_Status();
+#endif
+
+#if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_WFI_LEAVE + (vpe_id<<1)), (void*)&idle_service_leave_wait_time[vpe_id]);
+#endif
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE) && defined(WAIT_DURATION_CHECK)
+ /* Wait Duration time check */
+ if(vpe_0_1_2==0)
+ {//Only Per-CORE VPE0 could call this
+ IFDEF_PRODUCTION(Idle_Service_WaitTime_Check(core_id, vpe_id));
+ }
+#endif
+
+ drv_rstctl_set_check_bit((vpeid_e)vpe_id);
+ drv_rstctl_set_kick_bit((vpeid_e)vpe_id);
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Handler
+ * Purpose: Per-CORE's VPE 0's IDLE Service Handler. Called in idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's VPE0 IdleTask and execute in while loop.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Handler(void)
+{
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 _savedMask;
+ kal_checksleep_e OST_ReadyToSlept = OSTD_WAIT;
+ kal_uint32 Idle_CP0_status = 0;
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ kal_uint32 core_id = kal_get_current_core_id();
+ kal_uint32 quit_scheduler;
+ kal_uint32 swLockSleep, validSleepTime = 0;
+ kal_uint32 core1_status = 0;
+ kal_uint32 core2_status = 0;
+ kal_uint32 core3_status = 0;
+ kal_uint32 core_x_vpe1_wait_state = KAL_FALSE;
+ kal_uint32 core_x_vpe2_wait_state = KAL_FALSE;
+ kal_bool core_x_vpe1_pending_irq_status = KAL_FALSE;
+ kal_bool core_x_vpe2_pending_irq_status = KAL_FALSE;
+ kal_bool core_x_vpe1_pending_osirq_status = KAL_FALSE;
+ kal_bool core_x_vpe2_pending_osirq_status = KAL_FALSE;
+ Sleep_Time allow_sleep_dur = {0,0,0};
+ kal_uint32 directly_wait = KAL_FALSE;
+ kal_uint32 core_vpe1 = vpe_id+1, core_vpe2 = vpe_id+2;
+#endif /* LOWPWER_ENTER_PAUSE_MODE */
+
+ if(vpe_id%PER_CORE_VPE_NUM!=0)
+ {/* Only Per-CORE's VPE 0 could run this function */
+ ASSERT(0);
+ }
+
+ //idle_service_step_logging(vpe_id, IDLE_HANDLER_USER_IAPMU_CM, KAL_FALSE);
+
+ mdmcu_pmu_idle_reset();
+
+ idle_service_step_logging(vpe_id, IDLE_HANDLER_ENTER, KAL_FALSE);
+
+ if(0 == vpe_id)
+ {/* Request by SD10 to flush low power log, only enable by "AT+EGCMD=9487" AT CMD and default off. */
+ SleepDrv_LowPowerMonitorFlushCheck();/* enable when lpm.LPM_NVRAM_LogOn==1 */
+ }
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ if(idle_service_vpe_x_init_state[core_vpe1]==0||idle_service_vpe_x_init_state[core_vpe2]==0)
+ {
+ //This CORE's VPE1/VPE2 init is not ready
+ return;
+ }
+
+ /* Clear Per-Core's VPE1/2 wait IRQ here since VPE0 is re-running Idle_Task. */
+ MDCIRQ_Deactivate_LISR_without_ITC(IRQ_SW_CORE0_VPE0_LEAVE_WAIT + core_id);
+
+ if(0 == core_id)
+ {/* CORE 0 VPE 0 would get the sleep time. */
+ kal_get_sleep_time(&allow_sleep_dur);//Waste time so don't put this function in critical section to avoid HRT Qbit check fail.
+ }
+#endif
+
+ /* Disable Ibit sampling for coreX VPE0 self, and disable IRQ */
+ _savedMask = drv_mdcirq_Idletask_DI();
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+
+ idle_service_step_logging(vpe_id, IDLE_HANDLER_ENTER_DI, KAL_TRUE);
+
+ /* To avoid spurious interrupt, we confirm per-CORE's VPE1 and VPE2 in wait before masking his IRQ. */
+ /* To get more wait time, we pre-check SleepLock here, but we still check SleepLock again later when mask VPE1/VPE2's IRQ to avoid race condition. */
+ if (idle_service_vpe_x_in_wait_state[core_vpe1]!=KAL_TRUE||idle_service_vpe_x_in_wait_state[core_vpe2]!=KAL_TRUE||OSTD_CheckIsSleepLock()==KAL_TRUE)
+ {/* Since this CORE's VPE1/VPE2 is not in WAIT or someone lock sleep, we couldn't enter DORMANT. This CORE's VPE0 go to WAIT directly. */
+ //idle_service_step_logging(vpe_id, IDLE_COREx_VPE1_NOT_IN_WAIT, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ directly_wait = KAL_TRUE;
+ }
+ else
+ {/* Check CORE could go to DORMANT or not. */
+
+ idle_service_step_logging(vpe_id, IDLE_REMOVE_FROM_SCHEDULING, KAL_TRUE);
+
+ quit_scheduler = kal_remove_core_from_scheduling();/* Remove this CORE's VPE 0~2 from scheduler */
+ if (quit_scheduler == 0) /*Not quit scheduler*/
+ {/* Remove fail means related VPE1&VPE2 is not in idle task or there is pending IRQ on this CORE. ==> we could go to wait directly. */
+ idle_service_step_logging(vpe_id, IDLE_REMOVE_FROM_SCHEDULING_FAIL, KAL_FALSE);
+
+ OST_ReadyToSlept = OSTD_WAIT;
+ directly_wait = KAL_TRUE;
+ }
+ else /* Remove scheduler success!! */
+ {
+ idle_service_step_logging(vpe_id, IDLE_REMOVE_FROM_SCHEDULING_OK, KAL_TRUE);
+
+ idle_service_mask_vpe_irq(core_id, vpe_id);/* Mask this Core's all VPE's IRQ from CIRQ!! */
+
+ if(drv_mdcirq_IRQ_B_status(vpe_id) == KAL_TRUE
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ || drv_mdcirq_OSIPI_status(vpe_id) == KAL_TRUE
+ #endif
+ )
+ {// means that there is pending interrupt. Per-CORE's VPE 0 check here.
+ idle_service_step_logging(vpe_id, IDLE_CHECK_PENDING_IRQ_FAIL, KAL_FALSE);
+
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_TRUE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE0 & VPE1 & VPE2 to scheduler */
+
+ /* Enable Ibit sampling for coreX VPE0 self and enable IRQ */
+ drv_mdcirq_Idletask_EI(_savedMask);
+
+ return;
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_CHECK_PENDING_IRQ_OK, KAL_TRUE);
+ swLockSleep = OSTD_CheckIsSleepLock();
+ idle_service_step_logging(vpe_id, IDLE_CHECK_SW_LOCK_DONE, KAL_TRUE);
+
+ core_x_vpe1_pending_irq_status = drv_mdcirq_IRQ_B_status(core_vpe1);/* Check IRQ pending for Per-CORE's VPE 1 here. */
+ core_x_vpe2_pending_irq_status = drv_mdcirq_IRQ_B_status(core_vpe2);/* Check IRQ pending for Per-CORE's VPE 2 here. */
+ #if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
+ core_x_vpe1_pending_osirq_status = drv_mdcirq_OSIPI_status(core_vpe1);/* Check OSIRQ pending for Per-CORE's VPE 1 here. */
+ core_x_vpe2_pending_osirq_status = drv_mdcirq_OSIPI_status(core_vpe2);/* Check OSIRQ pending for Per-CORE's VPE 2 here. */
+ #endif
+ core_x_vpe1_wait_state = idle_service_vpe_x_in_wait_state[core_vpe1];/* After masking IRQ of per-CORE's VPE1, we must check per-CORE's VPE1 is still in WAIT or not */
+ core_x_vpe2_wait_state = idle_service_vpe_x_in_wait_state[core_vpe2];/* After masking IRQ of per-CORE's VPE2, we must check per-CORE's VPE2 is still in WAIT or not */
+
+ if(0 == core_id)
+ {/* CORE 0 VPE 0 */
+ core1_status = idle_service_CoreStatus[1];
+ #if defined(__MD97_IS_2CORES__)/* For 6297 H3 FPGA only, only 2 CORE */
+ core2_status = IDLE_STATUS_DORMANT;
+ core3_status = IDLE_STATUS_DORMANT;
+ #else /* run here~ */
+ core2_status = idle_service_CoreStatus[2];
+ core3_status = idle_service_CoreStatus[3];
+ #endif
+
+ if( (core1_status!=IDLE_STATUS_DORMANT) || (core2_status!=IDLE_STATUS_DORMANT) || (core3_status!=IDLE_STATUS_DORMANT) || (IDLEenterSleep==0) /* Force disable sleep */
+ || (swLockSleep) || core_x_vpe1_wait_state!=KAL_TRUE || core_x_vpe2_wait_state!=KAL_TRUE || core_x_vpe1_pending_irq_status == KAL_TRUE
+ || core_x_vpe2_pending_irq_status == KAL_TRUE || core_x_vpe1_pending_osirq_status == KAL_TRUE || core_x_vpe2_pending_osirq_status == KAL_TRUE )
+ {/* WAIT case 1 */
+ idle_service_step_logging(vpe_id, IDLE_WAIT_CASE, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ }
+ else
+ {/* Check validSleepTime, do OSTD_CheckSleep() */
+
+ /* In kal_is_valid_sleep_time(), it would set AFN & UFN. We should prove no other VPE set AFN & UFN at the same time to
+ avoid race condition due to we don't take lock.
+ So we call kal_is_valid_sleep_time() here due to all the other VPEs is in wait or DORMANT. */
+ validSleepTime = kal_is_valid_sleep_time(&allow_sleep_dur);
+
+ if(validSleepTime==0)
+ {/* WAIT case 2 */
+ idle_service_step_logging(vpe_id, IDLE_NOT_SLEEP_TIME, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ }
+ else
+ {/* OSTD_CheckSleep() */
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP, KAL_TRUE);
+ OST_ReadyToSlept = OSTD_CheckSleep();
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP_DONE, KAL_TRUE);
+ }
+ }
+
+ }
+ else
+ {/* CORE1/CORE2/CORE3 VPE 0 */
+ if( (swLockSleep) || core_x_vpe1_wait_state!=KAL_TRUE || core_x_vpe2_wait_state!=KAL_TRUE || core_x_vpe1_pending_irq_status == KAL_TRUE || core_x_vpe2_pending_irq_status == KAL_TRUE
+ || core_x_vpe1_pending_osirq_status == KAL_TRUE || core_x_vpe2_pending_osirq_status == KAL_TRUE || (IDLEenterSleep==0) /* Force disable sleep */)
+ {/* WAIT */
+ idle_service_step_logging(vpe_id, IDLE_WAIT_CASE, KAL_FALSE);
+ OST_ReadyToSlept = OSTD_WAIT;
+ }
+ else
+ {/* do OSTD_CheckSleep() */
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP, KAL_TRUE);
+ OST_ReadyToSlept = OSTD_CheckSleep();
+ idle_service_step_logging(vpe_id, IDLE_CORE_CHECK_SLEEP_DONE, KAL_TRUE);
+ }
+
+ }
+
+ }
+ }
+
+ /*-----Below Check Normal Domain Qbit before enter WAIT/DORMANT-----*/
+ #if 0/* Since we would check HRT Qbit, we don't need to check SMP Qbit here. */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+ /*-----Above Check Normal Domain Qbit before enter WAIT/DORMANT-----*/
+
+#endif /* LOWPWER_ENTER_PAUSE_MODE */
+
+ if(OSTD_WAIT == OST_ReadyToSlept)
+ {
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ if(directly_wait == KAL_TRUE)
+ {
+ idle_service_step_logging(vpe_id, IDLE_DIRECTLY_WAIT, KAL_FALSE);
+ /* We didn't mask VPE IRQ, so no need to call idle_service_unmask_vpe_irq() here. */
+
+ /* We didn't remove VPE from scheduler or remove fail, so no need to call kal_add_core_to_scheduling(WHOLE_CORE); here. */
+ }
+ else
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_WAIT, KAL_FALSE);
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_TRUE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE 0~2 to scheduler */
+ }
+#endif
+
+ /* For using LPM to verify DCM */
+ #if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Start();
+ #endif
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /* We unmask Per-Core's VPE1/2 wait IRQ here due to VPE0 would enter WAIT. */
+ IRQUnmask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT + core_id);
+#endif
+
+ idle_service_step_logging(vpe_id, IDLE_OSTD_WAIT_ENTER, KAL_FALSE);
+ mips_enter_wait_mode();
+ idle_service_step_logging(vpe_id, IDLE_OSTD_WAIT_LEAVE, KAL_FALSE);
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /* We mask Per-Core's VPE1/2 wait IRQ here due to VPE0 leave WAIT. We could ignore this IRQ. */
+ IRQMask(IRQ_SW_CORE0_VPE0_LEAVE_WAIT + core_id);
+#endif
+
+ /* For using LPM to verify DCM */
+ #if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Stop();
+ #endif
+
+ }
+ else if(OSTD_BUSY == OST_ReadyToSlept)
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_BUSY, KAL_FALSE);
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_TRUE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE0 & VPE1 & VPE2 to scheduler */
+
+ // do nothing, to re-entry handler soon
+
+ if(core_id != 0)
+ {/* CSC IRQ would cause leaving from DORMANT or get BUSY, so we put here to clear. */
+ /* Note: For CORE0, SD10 clear DORMANT abort states in OSTD_Interrupt().
+ For CORE1~3, SD10 clear DORMANT abort states in OSTD_CSC_handler(). */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_ENTER, KAL_TRUE);
+ OSTD_CSC_handler(); /* External function from SD10. Core 1/2/3 clear CSC IM bit & CSC IRQ. */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_LEAVE, KAL_TRUE);
+ }
+#endif
+ }
+ else if(OSTD_DORMANT == OST_ReadyToSlept)
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_DORMANT, KAL_FALSE);
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ /* We should restore TC0's priority before DORMANT due to there is no HRT Qbit check. */
+ miu_save_and_set_c0_tcschedule_grp(idle_core_x_vpe_0_tc_grp[core_id]);
+
+ /* Note: Maybe we should restore bus ultra signal here due to normal latency 1us. (EMI_latency) */
+
+ if(core_id == 0)
+ {
+ //kick WDT
+ drv_rstctl_set_kick_bit((vpeid_e)vpe_id);
+
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE0 go to sleep, Only Enable clock disable */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Control(KAL_TRUE, DCM_Lv2_SHAOLIN_DCM_ONLY_CLK_DISABLE),);
+ #endif
+
+ /* Call before sleep, request by SD10 */
+ idle_service_step_logging(vpe_id, IDLE_PTP_SLEEP_ENTER, KAL_TRUE);
+ ptp_sleep();
+ idle_service_step_logging(vpe_id, IDLE_PTP_SLEEP_LEAVE, KAL_TRUE);
+
+ /* Before DORMANT, VPE0 check DCXO_RDY_WO_ACK to know 26M is ready or not. */
+ IFDEF_PRODUCTION(PLL_Check_26M_ACK_Status(0x1111));
+
+ }
+ else/* CORE1~3 */
+ {
+ //disable WDT
+ drv_rstctl_clr_check_bit((vpeid_e)vpe_id);
+
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE1 or CORE2 or CORE3 go to sleep, disable the memslp control path of core1/2/3 */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Core_Memslp_Path_Control(KAL_FALSE, core_id),);
+ #endif
+ }
+
+ idle_service_CoreStatus[core_id] = IDLE_STATUS_DORMANT;
+
+ idle_service_core_x_dormant_time[core_id].idle_service_enter_dormant_frc = ust_get_current_time();
+ idle_service_core_x_dormant_time[core_id].idle_service_dor_abort_leave_dormant_frc = 0;
+ idle_service_core_x_dormant_time[core_id].idle_service_leave_dormant_frc = 0;
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ if(OSTD_Infinite_Sleep_Query())
+ {
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_Core0_INFINITESLEEP_WFI + core_id), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_enter_dormant_frc));
+ }
+ else
+ {
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_ENTER + (vpe_id*3)), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_enter_dormant_frc));
+ }
+ #endif //#if defined (__MODEM_CCCI_EXIST__)
+
+ idle_service_vpe_x_init_state[core_vpe1] = 0; //clear VPE1 init state by VPE0.
+ idle_service_vpe_x_init_state[core_vpe2] = 0; //clear VPE2 init state by VPE0.
+
+ #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+ SPV_core_idlemeter_enter(core_id);
+ #endif // #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+
+ /* ---Enter DORMANT Mode--- */
+
+ dormant_mode_activate();
+
+ /* ---Leave DORMANT Mode--- */
+
+ idle_service_CoreStatus[core_id] = IDLE_STATUS_NORMAL;
+ idle_service_vpe_x_leave_dormant_frc[vpe_id] = ust_get_current_time();//you could see idle_service_core_x_dormant_time[core_id] to know it is dormant abort or not
+
+ #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+ SPV_core_idlemeter_exit(core_id);
+ #endif // #if defined(__MTK_TARGET__) && defined(__SPV_IDLEMETER__)
+
+ if(core_id == 0)
+ {
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE0 wake up, Enable memslp function + clock disable @WFI */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Control(KAL_TRUE, DCM_Lv2_SHAOLIN_DCM_MEMSLP_AND_CLK_DISABLE),);
+ #endif
+
+ /* Call after wakeup, request by SD10 */
+ idle_service_step_logging(vpe_id, IDLE_PTP_WAKE_ENTER, KAL_TRUE);
+ ptp_wake();
+ idle_service_step_logging(vpe_id, IDLE_PTP_WAKE_LEAVE, KAL_TRUE);
+
+ /* After DORMANT(No matter dormant abort or not), VPE0 check DCXO_RDY_WO_ACK to know 26M is ready or not. */
+ IFDEF_PRODUCTION(PLL_Check_26M_ACK_Status(0x2222));
+ }
+ else/* CORE1~3 */
+ {
+ #if defined(LV2_DCM_MEMSLP_ENABLE)
+ /* When CORE1 or CORE2 or CORE3 wake up, enable the memslp control path of core1/2/3 */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Core_Memslp_Path_Control(KAL_TRUE, core_id),);
+ #endif
+ }
+
+ /* After DORMANT(No matter dormant abort or not), Per-core's VPE0 call SD10's check function. */
+ MD_TOPSM_GetErrorStatus();
+
+ if(Dormant_Service_Get_Dormant_Abort(core_id)==KAL_TRUE)
+ {/* 1. DORMANT abort ==> run WAIT flow */
+ idle_service_core_x_dormant_time[core_id].idle_service_dor_abort_leave_dormant_frc = ust_get_current_time();
+
+ /* When DORMANT abort, This-CORE's VPE1/VPE2 is still in wait and his idle_service_vpe_x_init_state==0. We should re-init by VPE0. */
+ idle_service_vpe_x_init_state[core_vpe1] = 1;
+ idle_service_vpe_x_init_state[core_vpe2] = 1;
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE + (vpe_id*3)), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_dor_abort_leave_dormant_frc));
+ #endif
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_ABORT_LEAVE, KAL_FALSE);
+
+ /* We don't check HRT Qbit when OSTD_DORMANT */
+ idle_service_unmask_vpe_irq(core_id, vpe_id, KAL_FALSE);
+ kal_add_core_to_scheduling(WHOLE_CORE);/* Add this CORE's VPE0 & VPE1 & VPE2 to scheduler */
+
+ }
+ else
+ {/* 2. Really restore from DORMANT */
+
+ idle_service_core_x_dormant_time[core_id].idle_service_leave_dormant_frc = ust_get_current_time();
+
+ idle_service_vpe_real_dormant_times[vpe_id]++;
+
+ #if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE + (vpe_id*3)), (void*)&(idle_service_core_x_dormant_time[core_id].idle_service_leave_dormant_frc));
+ #endif
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_LEAVE, KAL_FALSE);
+
+ if(vpe_id == 0)
+ {/* CORE0 VPE0 re-init Lv3 DCM */
+ /* Re-init Lv3 SHAOLIN DCM in GCR due to it would be disable after DORMANT. */
+ IFDEF_DCM(DCM_Lv3_SHAOLIN_DCM_Control(KAL_TRUE),);
+ IFDEF_DCM(DCM_Lv3_SFU_SPU_DCM_Control(DCM_Lv3_SFU_SPU_ALL_DCM, KAL_TRUE),);
+ /* Restore/Check wake up source mask after DORMANT. */
+ IFDEF_DCM(DCM_Lv2_SHAOLIN_DCM_Mask_WakeUp_Source_In_GCR(),);
+ /* Re-init Lv3 Cache DCM */
+ IFDEF_DCM(DCM_Lv3CACHE_DCM_Control(KAL_TRUE),);
+ }
+
+ #if 0//We would keep this IRQ mask before entering Dormant, so no need mask here.
+/* under construction !*/
+/* under construction !*/
+ #endif
+ idle_service_unmask_vpe_irq_leave_dormant(vpe_id);
+ kal_add_core_to_scheduling(SINGLE_VPE);/* Add this CORE's VPE0 to scheduler */ /* VPE1/VPE2 would add to Scheduler by himself */
+
+ }
+
+ if( core_id != 0 )
+ {/* CSC IRQ would cause leaving from DORMANT or get BUSY, so we put here to clear. */
+ /* Note: For CORE0, SD10 clear DORMANT abort states in OSTD_Interrupt().
+ For CORE1 & CORE2 & CORE3, SD10 clear DORMANT abort states in OSTD_CSC_handler(). */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_ENTER, KAL_TRUE);
+ OSTD_CSC_handler(); /* External function from SD10. Core 1/2/3 clear CSC IM bit & CSC IRQ. */
+ idle_service_step_logging(vpe_id, IDLE_CSC_HANDLER_LEAVE, KAL_TRUE);
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_WAIT_ENTER, KAL_FALSE);
+ /* Enter WAIT mode again due to wakeup event would come first, and IRQ comes later.
+ By the way, for CORE1, some user(EX: 4G timer) may only trigger IRQ to VPE1 with wakeup event,
+ so CORE1 VPE0 may stay in this wait for a long time. */
+ mips_enter_wait_mode();
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_WAIT_LEAVE, KAL_FALSE);
+
+ #if 0//We would keep this IRQ mask before entering Dormant, so no need mask above and no need unmask here.
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #endif
+
+#else /* This path didn't support. */
+ ASSERT(0);
+#endif
+
+ }
+ else
+ {
+ idle_service_step_logging(vpe_id, IDLE_OSTD_INVALID_CASE, KAL_TRUE);
+ ASSERT(0);
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_HANDLER_LEAVE, KAL_TRUE);
+
+ /* We must DI, then leave WAIT. */
+ Idle_CP0_status = miu_mfc0(MIU_C0_STATUS);
+ if((Idle_CP0_status&0x1)!=0x0)
+ {
+ EXT_ASSERT(0, vpe_id, Idle_CP0_status, 0);
+ }
+
+ /* Enable Ibit sampling for coreX VPE0 self and enable IRQ */
+ drv_mdcirq_Idletask_EI(_savedMask);
+
+ /* For using LPM to verify DCM */
+ #if defined(DCM_SUPPORT) && defined(DCM_LPM_ENABLE)
+ LPM_Print_and_Update_Setting(vpe_id, OST_ReadyToSlept);
+ #endif
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Handler_Slave
+ * Purpose: HRT Domain's IDLE Service Handler. Called in idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's HRT Domain IdleTask and execute in while loop.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Handler_Slave(void)
+{
+ kal_uint32 vpe_id;
+ kal_uint32 _savedMask;
+
+ vpe_id = kal_get_current_vpe_id();
+
+ /* Only HRT Domain could run this function. (But Per-Core VPE0 always couldn't run this function.) */
+ EXT_ASSERT(((kal_get_current_domain()==KAL_DOMAIN_HRT)&&(vpe_id%PER_CORE_VPE_NUM!=0)), vpe_id, kal_get_current_domain(), 0x22567);
+
+ /* Disable Ibit sampling for this VPE and disable IRQ */
+ _savedMask = drv_mdcirq_Idletask_DI();
+
+ kal_set_slave_vpe_idle_flag();
+
+ idle_service_step_logging(vpe_id, IDLE_WFI_WAIT_ENTER, KAL_FALSE);
+ mips_enter_wait_mode();
+ idle_service_step_logging(vpe_id, IDLE_WFI_WAIT_LEAVE, KAL_FALSE);
+
+ kal_remove_slave_vpe_idle_flag();
+
+ /* Note!! If this VPE recover from DORMANT, it wouldn't run below.
+ It would run dormant recover... -> Idle_Service_vpe1_vpe2_dormant_leave() */
+
+ /* Enable Ibit sampling for this VPE and enable IRQ */
+ drv_mdcirq_Idletask_EI(_savedMask);
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_Handler_Wait
+ * Purpose: Critical HRT Domain's IDLE Service Handler. Called in idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Called in Per-CORE's Critical HRT Domain IdleTask and execute in while loop.
+ *
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_Handler_Wait(void)
+{
+ /*
+ Note: Critical HRT Domain Disable WDT and Idle_Service_Prepare_WAIT() are called in isrentry.c
+ */
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ Set_EXL();
+#endif
+
+ /* "WAIT" instruction */
+ miu_wait();
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ /* Confirm FMA ready and go. */
+ Idle_Service_Polling_FMA_Status();
+ Clear_EXL();
+#endif
+
+ /* Note!! If this VPE recover from DORMANT, it wouldn't run below.
+ It would run dormant recover... -> Idle_Service_vpe1_vpe2_dormant_leave() */
+
+#if 0 //Already move to MDCIRQ
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if defined (__MODEM_CCCI_EXIST__)
+/* under construction !*/
+ #endif
+/* under construction !*/
+#endif
+
+}
+
+ /*------------------------------------------------------------------------
+ * void Idle_Service_vpe1_vpe2_dormant_leave
+ * Purpose: When Per-CORE's VPE1/VPE2 leave DORMANT, re-run idle task.
+ * Parameters:
+ * Input: None.
+ *
+ * Output: None.
+ * returns : None.
+ * Note : Only Per-CORE's VPE1/VPE2 would call this function.
+ * This function only be called when Per-CORE's VPE1/VPE2 leave DORMANT.
+ *------------------------------------------------------------------------
+ */
+void Idle_Service_vpe1_vpe2_dormant_leave(void)
+{/* Called in interAptiv-dormantMode_gcc.S */
+
+#if defined(LOWPWER_ENTER_PAUSE_MODE)
+ //kal_uint32 core_id = kal_get_current_core_id();
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 Idle_CP0_status = 0;
+ kal_uint32 vpe_0_1_2 = vpe_id%PER_CORE_VPE_NUM;/* To know it is Per-Core VPE0/VPE1/VPE2. */
+ kal_uint32 domain = kal_get_current_domain();
+
+ EXT_ASSERT((vpe_0_1_2==1||vpe_0_1_2==2), vpe_id, domain, 0x456);
+
+ idle_service_vpe_x_leave_dormant_frc[vpe_id] = ust_get_current_time();
+ #if defined (__MODEM_CCCI_EXIST__)
+ IDLE_EMM_WriteDbgInfo((IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE + (vpe_id*3)), (void*)&idle_service_vpe_x_leave_dormant_frc[vpe_id]);
+ #endif
+
+ /* Clear the WAIT parameter to let his VPE0 know VPE1/VPE2 is not in WAIT. */
+ idle_service_vpe_x_in_wait_state[vpe_id] = KAL_FALSE;
+
+ idle_service_step_logging(vpe_id, IDLE_DORMANT_RESTORE_LEAVE, KAL_FALSE);
+
+ idle_service_vpe_real_dormant_times[vpe_id]++;
+
+ if(domain==KAL_DOMAIN_HRT)
+ {/* HRT Domain */
+ /* Re-enable WDT */
+ drv_rstctl_set_check_bit((vpeid_e)vpe_id);
+ drv_rstctl_set_kick_bit((vpeid_e)vpe_id);
+
+ /* Enable IBit sampling for HRT Domain */
+ drv_mdcirq_IBit_sampling_enable(vpe_id, KAL_TRUE);/* Note: We must not enable IRQ here. We enable IRQ in sceduler. */
+ }
+ else if(domain==KAL_DOMAIN_CHRT)
+ {/* Critical HRT Domain */
+
+ /* Note: We didn't enable this VPE's WDT here due to this VPE is WAIT directly for critical LISR. */
+
+#if defined(MT6297)/* APOLLO *//* FMA couln't sync in 2T 26M after WFI.*/
+ /* Since this VPE is Set_EXL enter DORMANT, we need to restore it. */
+ Clear_EXL();
+#endif
+
+ /* Since this VPE is EI enter DORMANT and we need to remain DI, then handover to scheduler.
+ We DI here before unmask from CIRQ. */
+ __asm__ __volatile__( \
+ "di \n\t" \
+ "ehb\n\t" \
+ : \
+ : \
+ );
+ }
+
+ idle_service_unmask_vpe_irq_leave_dormant(vpe_id);
+
+ /* We disable IRQ and enter DORMANT.(So no one restore IRQ after entering DORMANT).
+ Before VPE1/VPE2 re-run the scheduler, we should restore "sst_hrt_qbit_count" and "di_tc" to avoid checking fail. */
+ interrupt_sleep_init(vpe_id);
+
+ idle_service_vpe_x_init_state[vpe_id] = 1; // VPE1/VPE2 init is ready.
+
+ /* We must remain DI, then handover to scheduler. */
+ Idle_CP0_status = miu_mfc0(MIU_C0_STATUS);
+ if((Idle_CP0_status&0x1)!=0x0)
+ {
+ EXT_ASSERT(0, vpe_id, Idle_CP0_status, 0);
+ }
+
+ idle_service_step_logging(vpe_id, IDLE_VPE1_VPE2_ENTER_SCHED, KAL_TRUE);
+ /* Add this CORE's VPE1/VPE2 to scheduler and re-run idle task in TCCT_Schedule */
+ kal_add_core_to_scheduling(SINGLE_VPE);
+#endif
+
+}
+
+#endif //__MTK_TARGET__
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/idle_task.c b/mcu/driver/sys_drv/init/src/md97p/idle_task.c
new file mode 100644
index 0000000..dd8100a
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/idle_task.c
@@ -0,0 +1,848 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_task.c
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file is for the functions of idle task.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef __MTK_TARGET__
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "syscomp_config.h"
+#include "task_config.h" /* Task creation */
+#include "kal_general_types.h"
+#include "kal_internal_api.h"
+#include "us_timer.h"
+#include "drv_rstctl.h"
+#include "mips_ia_utils.h"
+#include "kal_cpuinfo.h"
+#if defined(__BW_RUNTIME_PF__)/* For SPV */
+#include "spv_api.h"
+#endif
+
+/* Force idle task only while(1) */
+#if defined(__ESL_MASE_GEN97__)
+#define IDLE_TASK_BUSY_LOOPING
+#endif
+
+extern void DCM_Init(void);
+extern void Idle_Service_Check_Init_Done(kal_uint32 vpe_id);
+extern void Idle_Service_Init(void);
+extern void Idle_Service_Handler(void);
+extern void Idle_Service_Handler_Slave(void);
+extern void Idle_Service_Handler_Wait(void);
+extern void Idle_Service_Prepare_WAIT(void);
+
+kal_bool IdleTask_init(void)
+{/* Due to OS design, only Per-Core VPE0 would do task init. */
+
+ #if defined(MT6297_IA)
+ //Idle_Service_Init()& DCM_Init() didn't support 97 IA
+ #else
+ Idle_Service_Init();
+
+ /* Note: If you want to move DCM_Init() to IdleTask(), you should avoid memslp control race condition:
+ 1st boot up, Core 1~3 would run faster than Core0 ==> Core1~3 didn't wait Core0 finish DCM_Init() and would disable memslp, go to sleep.
+ Then Core0 enable memslp for all core in DCM_Init()->dcm_Lv2_shaolin_dcm_init(),
+ it would cause CPU hang due to Core1~3's memslp is enable when Core1~3 sleep!! */
+ DCM_Init();
+
+ #endif
+
+ return KAL_TRUE;
+}
+
+//Put in UC region to avoid high priority TC occupy pipeline.
+//__attribute__((__section__("NONCACHEDRW"))) volatile kal_uint32 temptag = 1;
+
+kal_uint32 IdleTask_domain[SYS_MCU_NUM_VPE] = {0};
+void IdleTask(task_entry_struct * task_entry_ptr)
+{
+ volatile kal_uint32 temptag = 1;
+ kal_uint32 vpe_id = kal_get_current_vpe_id();
+ kal_uint32 domain;
+
+ /* Each VPE/Idle Task help OS set TC priority.
+ Note: Per-Core VPE1/2 leave dormant would re-run full IdleTask(),
+ so the function would be called again after dormant. */
+ KAL_SET_DEFAULT_TC_PRIO();
+
+ domain = kal_get_current_domain();
+
+ IdleTask_domain[vpe_id] = domain;
+
+/* For BASIC load, it is only while loop. */
+#if defined(__MAUI_BASIC__) || defined(IDLE_TASK_BUSY_LOOPING)
+ while(temptag)
+ {/* Infinite loop */
+ miu_wait();/* "WAIT" instruction */
+ }
+#else
+
+ /* Confirm related init is complete. */
+ Idle_Service_Check_Init_Done(vpe_id);
+
+ if(domain==KAL_DOMAIN_NORMAL)
+ {
+ while(temptag)
+ {/* Infinite loop */
+ miu_yield(-1);//Release Pipeline
+ Idle_Service_Handler();
+ }
+ }
+ else if(domain==KAL_DOMAIN_HRT)
+ {
+ while(temptag)
+ {/* Infinite loop */
+ miu_yield(-1);//Release Pipeline
+ Idle_Service_Handler_Slave();
+ }
+ }
+ else if(domain==KAL_DOMAIN_CHRT)
+ {
+ //Due to Critical HRT domain WDT is controled by IRQ handler, we disable WDT here to avoid no IRQ coming.
+ drv_rstctl_clr_check_bit((vpeid_e)vpe_id);
+ Idle_Service_Prepare_WAIT();
+
+ while(temptag)
+ {/* Infinite loop */
+ miu_yield(-1);//Release Pipeline
+ Idle_Service_Handler_Wait();
+ }
+ }
+ else
+ {
+ EXT_ASSERT(0, vpe_id, domain, 0x2244);/* invalid domain */
+ }
+
+#endif
+}
+
+
+/*************************************************************************
+* FUNCTION
+* idle_create
+*
+* DESCRIPTION
+* This function implements idle entity's create handler.
+*
+* PARAMETERS
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+#if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+extern void hrt_idle_task_main(task_entry_struct * task_entry_ptr);
+extern kal_bool hrt_idle_task_init(void);
+#elif defined(__EL2_HRT_EVALUATION__)
+void hrt_eval_idle_task_main(void);
+void hrt_eval_idle_task_init(void);
+#elif defined(__ESL_COSIM_LTE__)
+void el1_adapt_idle_task_main(void);
+void el1_adapt_idle_task_init(void);
+#elif defined(__MASE__)
+extern void mase_adapt_idle_task_main(task_entry_struct *task_entry_ptr);
+#elif defined(MTK_C2K_COSIM)
+extern kal_bool cl1_cosim_idle_task_main(void);
+extern void cl1_cosim_idle_task_init(void);
+extern kal_bool cl1_cosim_idle_task_main1(void);
+extern void cl1_cosim_idle_task_init1(void);
+extern kal_bool cl1_cosim_idle_task_main2(void);
+extern void cl1_cosim_idle_task_init2(void);
+extern kal_bool cl1_cosim_idle_task_main3(void);
+extern void cl1_cosim_idle_task_init3(void);
+extern kal_bool cl1_cosim_idle_task_main4(void);
+extern void cl1_cosim_idle_task_init4(void);
+extern kal_bool cl1_cosim_idle_task_main5(void);
+extern void cl1_cosim_idle_task_init5(void);
+extern kal_bool cl1_cosim_idle_task_main6(void);
+extern void cl1_cosim_idle_task_init6(void);
+extern kal_bool cl1_cosim_idle_task_main7(void);
+extern void cl1_cosim_idle_task_init7(void);
+extern kal_bool cl1_cosim_idle_task_main8(void);
+extern void cl1_cosim_idle_task_init8(void);
+extern kal_bool cl1_cosim_idle_task_main9(void);
+extern void cl1_cosim_idle_task_init9(void);
+extern kal_bool cl1_cosim_idle_task_main10(void);
+extern void cl1_cosim_idle_task_init10(void);
+extern kal_bool cl1_cosim_idle_task_main11(void);
+extern void cl1_cosim_idle_task_init11(void);
+#elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask1( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask2( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask3( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask4( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask5( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask6( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask7( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask8( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask9( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask10( task_entry_struct * task_entry_ptr );
+extern __attribute__ ((section ("INTSRAM_ROCODE"))) void Sleep_IdleTask11( task_entry_struct * task_entry_ptr );
+#elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+extern void idle_task_xl1r_main(task_entry_struct * task_entry_ptr);
+#endif
+
+#if SYS_MCU_NUM_VPE >= 1
+ /* idle task for VPE 0 */
+ kal_bool idle_create(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main,
+ cl1_cosim_idle_task_init,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__)
+ SPV_IdleTask0,
+ IdleTask_init,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 2
+ /* idle task for VPE 1 */
+ kal_bool idle_create1(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main1,
+ cl1_cosim_idle_task_init1,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask1,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 3
+ /* idle task for VPE 2 */
+ kal_bool idle_create2(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main2,
+ cl1_cosim_idle_task_init2,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask2,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD95__)
+ SPV_IdleTask1,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 4
+ /* idle task for VPE 3 */
+ kal_bool idle_create3(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main3,
+ cl1_cosim_idle_task_init3,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask3,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD97__)
+ SPV_IdleTask1,
+ IdleTask_init,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 5
+ /* idle task for VPE 4 */
+ kal_bool idle_create4(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main4,
+ cl1_cosim_idle_task_init4,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask4,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 6
+ /* idle task for VPE 5 */
+ kal_bool idle_create5(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main5,
+ cl1_cosim_idle_task_init5,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask5,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 7
+ /* idle task for VPE 6 */
+ kal_bool idle_create6(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main6,
+ cl1_cosim_idle_task_init6,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask6,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD97__)
+ SPV_IdleTask2,
+ IdleTask_init,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 8
+ /* idle task for VPE 7 */
+ kal_bool idle_create7(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main7,
+ cl1_cosim_idle_task_init7,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask7,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 9
+ /* idle task for VPE 8 */
+ kal_bool idle_create8(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main8,
+ cl1_cosim_idle_task_init8,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask8,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 10
+ /* idle task for VPE 9 */
+ kal_bool idle_create9(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main9,
+ cl1_cosim_idle_task_init9,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask9,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #elif defined(__BW_RUNTIME_PF__) && defined(__MD97__)
+ SPV_IdleTask3,
+ IdleTask_init,
+ #else
+ IdleTask,/* task entry function */
+ IdleTask_init,/* task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 11
+ /* idle task for VPE 10 */
+ kal_bool idle_create10(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main10,
+ cl1_cosim_idle_task_init10,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask10,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 12
+ /* idle task for VPE 11 */
+ kal_bool idle_create11(comptask_handler_struct **handle)
+ {
+ static const comptask_handler_struct idle_handler_info =
+ {
+ #if defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)
+ hrt_idle_task_main,
+ hrt_idle_task_init,
+ #elif defined(__EL2_HRT_EVALUATION__)
+ hrt_eval_idle_task_main,
+ hrt_eval_idle_task_init,
+ #elif defined(__ESL_COSIM_LTE__)
+ el1_adapt_idle_task_main,
+ el1_adapt_idle_task_init,
+ #elif defined(__MASE__)
+ mase_adapt_idle_task_main,
+ NULL,
+ #elif defined(MTK_C2K_COSIM)
+ cl1_cosim_idle_task_main11,
+ cl1_cosim_idle_task_init11,
+ #elif defined(__SLEEP_IT__) && !defined(__SLEEP_IT_IDLE__)
+ Sleep_IdleTask11,
+ NULL,
+ #elif defined(__DUMMY_L1_ON_TARGET_4G5G__)
+ idle_task_xl1r_main,
+ NULL,
+ #else
+ IdleTask,/* task entry function */
+ NULL,/* This VPE wouldn't run task initialization function */
+ #endif
+ NULL /* task reset handler */
+ };
+
+ *handle = (comptask_handler_struct *)&idle_handler_info;
+
+ return KAL_TRUE;
+ }
+#endif
+
+#if SYS_MCU_NUM_VPE >= 13
+ /* idle task for VPE 12 */
+ #error "Unsupported idle task numbers!"
+#endif
+
+#else /* __MTK_TARGET__ */
+
+#endif
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/init.c b/mcu/driver/sys_drv/init/src/md97p/init.c
new file mode 100644
index 0000000..9179876
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init.c
@@ -0,0 +1,2762 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+//#include <stdio.h>
+//#include <string.h>
+#include <stdlib.h>
+#include <boot_comm.h>
+
+// kal
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_internal_api.h"
+#include "kal_trace.h"
+#include "reg_base.h"
+#include "system_profiler_public.h"
+#include "multiboot_config.h"
+
+// init
+#include "cp15.h"
+#include "config_hw.h"
+//#include "init.h"
+#include "init_comm.h"
+
+// trace
+#include "system_trc.h" //INT_Trace_Enter, INT_Trace_Exit
+#include "init_trc_api.h" //INT_Trace_Enter, INT_Trace_Exit
+#include "bootarm.h"
+#include "br_time_stamp.h" // TS_END
+
+// system service hw
+#include "pll.h" // INT_SetPLL
+//#include "dsp_loader.h" // DSP_Load
+#include "bus_drv.h" // Bus_Init
+#include "elm.h" // ELM_INIT
+#include "sleepdrv_interface.h" //Sleep_DrvLowPowerMonitorInit
+// system service sw
+#include "stack_buff_pool.h" //stack_resources_init, stack_init_buff_pool_info
+#include "ex_item.h" // ex_memory_dump_init
+#include "mpu.h" // CPU_SET_STACK_MPU_PROTECT, mpu_dump
+#include "ex_mem_manager_public.h" // EMM_Init
+#include "dsp_file_public.h" // DSP_Init, DSP_OutputVersionInfo
+
+
+//misc
+#include "dcl.h" // for peripheral related
+#include "wdt_hw_public.h" //Get_WATCHDOG_BASE, Get_WATCHDOG_RESTART_CMD
+//#include "bl_common.h" // BL_Info_Wrapper_st
+#include "drv_cfgctl.h" //drv_cfgctl_clear_misc, drv_cfgctl_set_misc
+#ifdef __HMU_ENABLE__
+#include "hmu.h" // hif_boot_init
+#endif
+#if defined(__SMART_PHONE_MODEM__)
+#include "ccci.h"
+#endif
+#ifdef __HIF_CCCI_SUPPORT__
+#include "ccci_if.h"
+#endif
+#include "us_timer.h"
+#if !defined(__UBL__) && !defined(__FUE__)
+
+#include "ostd_public.h"
+extern void SleepDrv_Init( void );
+extern void RM_Init( void );
+
+#endif
+#include "DVFS_drv_public.h"
+#include "ptp_public.h"
+#include "RM_public.h"
+
+#ifndef __MAUI_BASIC__
+extern void MML1_TXSYS_Init(void);
+#endif
+
+#include "drv_mdcirq.h"
+#include "drv_gdma.h"
+#include "drv_busmon.h"
+#include "drv_pcmon.h"
+#include "busmpu.h"
+#include "drv_mdap_interface.h"
+#include "mips_ia_utils.h"
+#include "pms.h"
+#include "drv_sfu.h"
+#include "che_api.h" // for SST_SSF_Init
+#include "tg_hisr.h"
+#include "drv_rstctl.h" // for wdt_enable
+
+/******************************************************
+ * Declaration and definition of global data
+ ******************************************************/
+//WDT
+WDT_CTRL_ENABLE_T wdt_data;
+DCL_HANDLE init_dcl_wdt_handle;
+DCL_HANDLE init_dcl_handle;
+
+#if 0
+/* under construction !*/
+#endif
+__attribute__((section ("MCURW_HWRO_DNC_NOINIT"))) kal_uint32 INT_bootup_entry = 0;
+
+volatile DEFINE_NC_SHARED_VAR_ASSIGN(kal_uint16, _boot_mode,0xFFFF);
+volatile DEFINE_NC_SHARED_VAR_ASSIGN(kal_uint32, g_l_sw_misc_l,0xFFFF);
+volatile DEFINE_NC_SHARED_VAR_ASSIGN(kal_bool, _IsBootForUSBAT,KAL_FALSE);
+
+// <TODO>: fix this LR11 address
+//static const kal_uint32 RAND_GEN_START_ADDR = 0x70002000;
+
+#define INT_CLEAR_RETN_FLAG(_flag) drv_cfgctl_clear_misc()
+#define INT_CLEAR_SET_FLAG(_flag) drv_cfgctl_set_misc(_flag)
+
+/******************************************************
+ * Declaration of function prototype
+ ******************************************************/
+static void INT_SetBootMode(void);
+static void HWDInitialization(void);
+static void systemInitialization(void);
+static void systemInitializeResource(void);
+
+
+/******************************************************
+ * Declaration of import data and function prototype
+ ******************************************************/
+/* Application_Initialize */
+extern boot_mode_type system_boot_mode;
+
+/* Application_Initialize */
+#ifndef __BL_ENABLE__
+void boot_init_clock();
+#endif
+extern kal_uint32 DummyReference();
+extern void Drv_Init_Phase2(void);
+extern void ECT_Init(void);
+extern int mainp(void);
+
+/* HWDInitialization */
+extern void L1SM_Init(void);
+extern void UL1SM_Init(void);
+extern void EL1SM_Init(void);
+extern void NFI_Reset(void);
+extern void Drv_Init_Phase1(void);
+extern void DIGRF_Platform_Init_Phase_1(void);
+extern void DIGRF_Platform_Init_Phase_2(void);
+
+/* systemInitialization */
+#if !(defined(__NONE_FLASH_EXIST__))
+#if !(defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)) || defined(__NANDFDM_MULTI_INSTANCE__)
+extern void Initialize_FDD_tables(void);
+#endif
+#endif
+extern void kal_hrt_init(void);
+extern void kal_profile_init(void);
+
+/* systemInitializeResource */
+extern kal_uint32 rand_num_seed;
+
+/* INT_VersionNumbers */
+extern kal_char *release_dsp_fw(void);
+extern kal_char *release_dsp_ptch(void);
+extern kal_char *release_verno(void);
+extern kal_char *release_branch(void);
+extern kal_char *release_hw_ver(void);
+extern kal_char* release_flavor(void);
+
+/* Misc. */
+extern void SST_InvokEngine(kal_int32, kal_int32);
+
+// for Security
+#ifdef __SECURE_DATA_STORAGE__
+extern kal_int32 SDS_Init(void);
+#endif
+#if defined(__BOOT_CERT__)
+extern kal_uint32 srd_dl_ctrl_check(void);
+extern kal_uint32 srd_dl_ctrl_pre_check(void);
+#endif
+
+/* Generate CORE#_VPE#_TC#_SYS_STACK_PTR and extern SYS_Stack_Pool_CORE#_VPE#_TC# */
+#define STACK_PTR_NAME(C,V,T) CORE ## C ##_VPE ## V ##_TC ## T ##_SYS_STACK_PTR
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ extern kal_uint32 SYS_STACK_NAME(CORE,VPE,TC)[]; \
+ kal_uint32 STACK_PTR_NAME(CORE,VPE,TC) = (((unsigned int)SYS_STACK_NAME(CORE,VPE,TC)) + SIZE - 4);
+
+#include "sys_stack_config.h"
+
+/*************************************************************************
+* FUNCTION
+* INT_SysStack_Disptach
+*
+* DESCRIPTION
+* This function would set all system stack ptrs
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_SetSysStack_GuardPattern
+*
+* DESCRIPTION
+* This function would set STACKEND to system stacks of a core
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_SetSysStack_GuardPattern(kal_uint32 core)
+{
+ volatile kal_uint8 *base;
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ if (CORE == core) { \
+ base = (kal_uint8 *)SYS_STACK_NAME(CORE,VPE,TC); \
+ *(base + 0) = 'S'; \
+ *(base + 1) = 'T'; \
+ *(base + 2) = 'A'; \
+ *(base + 3) = 'C'; \
+ *(base + 4) = 'K'; \
+ *(base + 5) = 'E'; \
+ *(base + 6) = 'N'; \
+ *(base + 7) = 'D'; \
+ }
+
+#include "sys_stack_config.h"
+
+ return;
+}
+
+void INT_GetStackInfo(kal_uint32 * const base, kal_uint32 * const end)
+{
+ const kal_uint32 vpe = kal_get_current_vpe_id() % 3;
+ const kal_uint32 tc = kal_get_current_tc_id();
+ const kal_uint32 core = kal_get_current_core_id();
+
+ *base = *end = 0xFFFFFFFF;
+
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ if (CORE == core && VPE == vpe && TC == tc) { \
+ *base = (unsigned int)SYS_STACK_NAME(CORE,VPE,TC); \
+ *end = STACK_PTR_NAME(CORE,VPE,TC); \
+ return; \
+ }
+
+#include "sys_stack_config.h"
+
+ return;
+}
+
+void INT_GetSysStackInfo(kal_uint32 * const base, kal_uint32 * const end,
+ kal_uint32 core, kal_uint32 vpe, kal_uint32 tc)
+{
+ *base = *end = 0xFFFFFFFF;
+ vpe = vpe%3;
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ if (CORE == core && VPE == vpe && TC == tc) { \
+ *base = (unsigned int)SYS_STACK_NAME(CORE,VPE,TC); \
+ *end = STACK_PTR_NAME(CORE,VPE,TC); \
+ return; \
+ }
+
+#include "sys_stack_config.h"
+
+ return;
+}
+/******************************************************
+ * Definition of functions
+ ******************************************************/
+
+/*__FUE__ compile option is used for FOTA firmware update engine */
+/*add this compile option to avoid compiling other function*/
+#ifndef __FUE__
+/*
+ * NoteXXX:
+ * Please DO NOT place your code in the execution region EMIINITCODE.
+ * Code in this region is used for EMI/PLL initialization, and will be
+ * OVERWRITTEN after INT_InitRegions.
+ */
+/* [BB porting] Make sure the flow to set EMI&SFI and the placement of the code */
+/*************************************************************************
+* FUNCTION
+* INT_SetEMIPLL
+*
+* DESCRIPTION
+* This function dedicates for PLL setting.
+*
+* CALLS
+* Non
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+__attribute__ ((section ("EMIINITCODE"))) void INT_SetEMIPLL(void)
+{
+ custom_setEMI();
+ //INT_SetPLL(PLL_MODE_MAUI);
+}
+
+/* A test procedure for CIRQ driver and UART */
+//#define BASICLOAD_BRINGUP_TEST
+#ifdef BASICLOAD_BRINGUP_TEST
+extern void slt_dbg_print(char* fmt,...);
+void INT_BasicLoad_SimepleTest_GPTCallback(void *para)
+{
+ slt_dbg_print("uart test\r\n");
+ return;
+}
+
+kal_int32 INT_BasicLoad_SimpleTest(kal_uint32 dummy)
+{
+ kal_uint32 cbms_para = 0;
+ DCL_HANDLE handle_cbms;
+ SGPT_CTRL_START_T sgpt_ctrls;
+
+ handle_cbms = DclSGPT_Open(DCL_GPT_CB, 0);
+ sgpt_ctrls.u2Tick = (1);
+ sgpt_ctrls.pfCallback = INT_BasicLoad_SimepleTest_GPTCallback;
+ sgpt_ctrls.vPara = &cbms_para;
+
+ DclSGPT_Control(handle_cbms, SGPT_CMD_START, (DCL_CTRL_DATA_T*)&sgpt_ctrls);
+ return 0;
+}
+#endif
+
+void init_otherCores(void)
+{
+ MD_TOPSM_Init_Other_Cores();
+ return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* init_main
+*
+* DESCRIPTION
+* This function implements project protocol stack, hardware depedent
+* initialization
+*
+* CALLS
+* Initialize()
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+__attribute__((section ("MCURW_HWRO_DNC_NOINIT"))) volatile kal_uint32 app_step_logging = 0;
+void init_main(void)
+{
+#if !defined(_SIMULATION)
+#if !defined(__BL_ENABLE__)
+ //boot_init_clock();
+#endif
+#endif
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+
+ app_step_logging = 0;
+ /* set-up locale for trace */
+ //INT_Trace_Enter(INIT_CLIB1);
+ INT_TRC_C(LABEL_CLIB_BASE_INIT);
+ clib_basic_init();
+ //INT_Trace_Exit(INIT_CLIB1);
+ app_step_logging = 1;
+
+#ifdef __HIF_CCCI_SUPPORT__
+ /* Call HIF initialize and do phase-1 handshake with AP */
+ //INT_Trace_Enter(INIT_CCCIHS1);
+ INT_TRC_C(LABEL_CCCI_HW_INIT);
+ lte_ccci_hw_init();
+ //INT_TRC_C(LABEL_CCCI_HS1);
+ lte_ccci_init_handshake_phase1();
+ //INT_Trace_Exit(INIT_CCCIHS1);
+#endif
+
+ /* Enable EMM Feature */
+ //INT_TRC_C(LABEL_EMM_INIT);
+#if !defined(__ESL_MASE_GEN97__)
+ EMM_Init();
+#endif /* !__ESL_MASE_GEN97__ */
+
+#if !defined(__ESL_MASE_GEN97__)
+ /* Set INT_BootMode config done flag to untrap L1Core */
+ INT_Trace_Enter(INIT_BOOTMODE);
+ INT_SetBootMode();
+ INT_Trace_Exit(INIT_BOOTMODE);
+#endif /* !__ESL_MASE_GEN97__ */
+
+ /* Initialize system specific module */
+ INT_Trace_Enter(INIT_SYSTEMINIT);
+ systemInitialization();
+ INT_Trace_Exit(INIT_SYSTEMINIT);
+ app_step_logging = 2;
+
+
+ /* Initialize HW module */
+ INT_Trace_Enter(INIT_HWDINIT);
+ HWDInitialization();
+ INT_Trace_Exit(INIT_HWDINIT);
+
+ /* Disable Watch dog */
+ INT_Trace_Enter(INIT_DISABLE_WDT);
+ wdt_enable(KAL_FALSE);
+ INT_Trace_Exit(INIT_DISABLE_WDT);
+
+#if !defined(_SIMULATION) && !defined(__ESL_MASE__)
+ /* Note: Not all HW modules are avaiable in the Co-SIM envrionment */
+ /* Note: Need to bypass DRV INIT in Co-SIM (via _SIMULATION) */
+ INT_Trace_Enter(INIT_DRV2);
+ Drv_Init_Phase2();
+ INT_Trace_Exit(INIT_DRV2);
+#endif
+
+ /* Resource initialization */
+ INT_Trace_Enter(INIT_RESINIT);
+ systemInitializeResource();
+ INT_Trace_Exit(INIT_RESINIT);
+
+ /* Initialize heap for c library usage */
+ INT_Trace_Enter(INIT_CLIB2);
+ clib_init();
+ INT_Trace_Exit(INIT_CLIB2);
+ app_step_logging = 3;
+
+ /* Initialize specific sss features */
+ INT_Trace_Enter(INIT_SSF);
+ SST_SSF_Init();
+ INT_Trace_Exit(INIT_SSF);
+
+#if !defined(_SIMULATION)
+ /* Initialize ECT in the begging of Application_Initialize */
+ INT_Trace_Enter(INIT_ECT);
+ ECT_Init();
+ INT_Trace_Exit(INIT_ECT);
+#endif
+
+
+ INT_Trace_Enter(INIT_DSPINIT);
+#if !defined(__TCM_ONLY_LOAD__)
+ DSP_Init();
+#endif
+ INT_Trace_Exit(INIT_DSPINIT);
+ app_step_logging = 4;
+
+#if defined (__LP_SCHEDULE_ENABLE__)
+ /* Need to be called after spinlock init and gpt init(drv_init_phase1) */
+ INT_Trace_Enter(INIT_TG_HISR_INIT);
+ tg_hisr_init();
+ INT_Trace_Exit(INIT_TG_HISR_INIT);
+#endif
+
+ /* MAUI protocol stack entry routine */
+ INT_Trace_Enter(INIT_MAINP);
+ mainp();
+ INT_Trace_Exit(INIT_MAINP);
+ app_step_logging = 5;
+
+#if 0
+/* under construction !*/
+#endif
+
+ /* enable SWLA by default for easy debug */
+#if !defined(_SIMULATION) || defined(__ESL_MASE__)
+ INT_Trace_Enter(INIT_SLA);
+ SysProfiler_Init();
+#if defined(DEBUG_SWLA)
+ SysProfiler_Start(); // enable SWLA by default for easy debug
+#endif
+ INT_Trace_Exit(INIT_SLA);
+#endif
+
+
+#ifdef __MULTI_BOOT__
+ if ( system_boot_mode!=FACTORY_BOOT )
+#endif
+ {
+ INT_Trace_Enter(INIT_ENABLE_WDT);
+#if !defined(__ESL_MASE_GEN97__)
+ /* Enable watch dog */
+ wdt_enable(KAL_TRUE);
+#endif /* !__ESL_MASE_GEN97__ */
+ }
+
+#ifdef __HMU_ENABLE__
+ INT_Trace_Enter(INIT_HIFBOOT);
+ hif_boot_init();
+ INT_Trace_Exit(INIT_HIFBOOT);
+#endif
+
+ INT_Trace_Enter(INIT_SLP_LPM_INIT);
+ Sleep_DrvLowPowerMonitorInit();
+ INT_Trace_Exit(INIT_SLP_LPM_INIT);
+
+#ifdef __HIF_CCCI_SUPPORT__
+ /* Do phase-2 handshake with AP */
+ INT_Trace_Enter(INIT_CCCIHS2);
+ lte_ccci_init_handshake_phase2(SHARED_VAR(_boot_mode));
+ lte_ccci_hw_init_phase2();
+ INT_Trace_Exit(INIT_CCCIHS2);
+ INT_Trace_Enter(INIT_CCCIHS2_DONE);
+ INT_Trace_Exit(INIT_CCCIHS2_DONE);
+#endif
+
+ INT_backupBootLogs();
+
+#ifdef BASICLOAD_BRINGUP_TEST
+ INT_BasicLoad_SimpleTest(0);
+#endif
+ app_step_logging = 0xFF;
+
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_SetBootMode
+*
+* DESCRIPTION
+* This function sets global variables related to boot mode
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+* _boot_mode
+* g_l_sw_misc_l
+* _IsBootForUSBAT
+*
+*************************************************************************/
+
+static void INT_SetBootMode(void)
+{
+ /* for SiP TDD SLT, force META bootup */
+#if defined(__TDDSYS_SLT_FACTORY_BOOT__) || defined(__LTE_PHY_TEST__)
+ INT_SetMetaMode();
+#endif
+
+ /* Multi-Boot */
+#ifdef __MULTI_BOOT__
+
+ SHARED_VAR(_boot_mode) = 0x1 & *(volatile kal_uint16 *)BOOT_CONFIG_ADDR;
+
+ SHARED_VAR(g_l_sw_misc_l) = *(volatile kal_uint16 *)BOOT_CONFIG_ADDR;
+
+ if (0x4 & *(volatile kal_uint16 *)BOOT_CONFIG_ADDR)
+ {
+ SHARED_VAR(_IsBootForUSBAT) = KAL_TRUE;
+ }
+
+#if !defined(L1_NOT_PRESENT) && !defined(ATEST_DRV_ENVIRON)
+ /* Set mode for L1 usage */
+ //pcore doesn't need L1D_SetInitMode.
+ //L1D_SetInitMode(_boot_mode);
+#endif /* !L1_NOT_PRESENT && !ATEST_DRV_ENVIRON */
+
+#endif /* __MULTI_BOOT__ */
+
+ // Seamless META feature: always normal boot
+ SHARED_VAR(_boot_mode) = 0x0;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* systemInitialization
+*
+* DESCRIPTION
+* This function implements the system specific initialization, including
+* interrupt central controller, FDD and KAL.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+volatile kal_uint32 app_bypass = 0;
+static void systemInitialization(void)
+{
+ app_step_logging = 0x11;
+ if (!app_bypass){
+ /* initialize CIRQ interrupt controller */
+ initINTR();
+ app_step_logging = 0x12;
+ /* initialize VPE interrupt setting */
+ initVPEIRQ();
+ }
+
+#if !(defined(__NONE_FLASH_EXIST__))
+#if !(defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)) || defined(__NANDFDM_MULTI_INSTANCE__)
+ Initialize_FDD_tables();
+ app_step_logging = 0x13;
+#endif /* !(_NAND_FLASH_BOOTING_ || __EMMC_BOOTING__) || __NANDFDM_MULTI_INSTANCE__ */
+#endif /* !(__NONE_FLASH_EXIST__) */
+
+ /* Register display handler */
+ kal_register_print_string_function((kal_print_string_func_ptr)stack_print);
+ app_step_logging = 0x14;
+ app_step_logging = 0x15;
+
+ /* Initialize HRT workqueue */
+ kal_hrt_init();
+ app_step_logging = 0x17;
+ /* Initializing the Buffer Pool Information */
+ stack_init_buff_pool_info();
+ app_step_logging = 0x18;
+ /* Create buffer pools */
+ stack_resources_init();
+ app_step_logging = 0x19;
+ /* Initialize KAL resources */
+ kal_initialize();
+ app_step_logging = 0x20;
+ /* Initialize KAL CPU usage profiling */
+ kal_profile_init();
+ app_step_logging = 0x21;
+ /* Initialize memory dump switch */
+ ex_memory_dump_init();
+ app_step_logging = 0x22;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* HWDInitialization
+*
+* DESCRIPTION
+* This function implements hardware dependent initialization and
+* management
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+static void HWDInitialization(void)
+{
+
+#if !defined(_SIMULATION) && !defined(__ESL_MASE__)
+ //INT_SetChipReg();
+
+ INT_Trace_Enter(INIT_PDAMON);
+ drv_pdamon_init();
+ INT_Trace_Exit(INIT_PDAMON);
+
+#if 1 //wait for driver ready
+ INT_Trace_Enter(INIT_INIT_MISC);
+ INT_Init_Misc();
+ INT_Trace_Exit(INIT_INIT_MISC);
+#endif //wait for driver ready
+ INT_Trace_Enter(INIT_BUS);
+ BusDrv_Init();
+ INT_Trace_Exit(INIT_BUS);
+
+#if 1 //wait for driver ready
+ INT_Trace_Enter(INIT_ELM);
+ ELM_INIT();
+ INT_Trace_Exit(INIT_ELM);
+#endif
+ INT_Trace_Enter(INIT_USC);
+ USC_Start();
+ INT_Trace_Exit(INIT_USC);
+
+ INT_Trace_Enter(INIT_PMS);
+ PMS_Init();
+ INT_Trace_Exit(INIT_PMS);
+
+ //DIGRF_Platform_Init_Phase_1 : call before topsm init
+ INT_Trace_Enter(INIT_DIGRF1);
+ DIGRF_Platform_Init_Phase_1();
+ INT_Trace_Exit(INIT_DIGRF1);
+
+ INT_Trace_Enter(INIT_RM);
+ RM_Init(); // before OSTD_Init() and before 2G and 3G SMM's init() function
+ INT_Trace_Exit(INIT_RM);
+
+ //DIGRF_Platform_Init_Phase_2 : call after topsm init
+ INT_Trace_Enter(INIT_DIGRF2);
+ DIGRF_Platform_Init_Phase_2();
+ INT_Trace_Exit(INIT_DIGRF2);
+
+
+ INT_Trace_Enter(INIT_OSTD);
+ OSTD_Init();
+ INT_Trace_Exit(INIT_OSTD);
+
+
+ INT_Trace_Enter(INIT_GDMA);
+ DRV_GDMA_INITIALIZATION();
+ INT_Trace_Exit(INIT_GDMA);
+
+
+#ifdef MTK_SLEEP_ENABLE
+#ifndef ATEST_DRV_ENABLE
+ /* Added by Anthony Chin 03/18/2002. For sleep mode management. */
+
+#ifdef __GSM_RAT__
+ INT_Trace_Enter(INIT_L1SM);
+ L1SM_Init();
+ INT_Trace_Exit(INIT_L1SM);
+#endif /* __GSM_RAT__ */
+
+#ifdef __MTK_UL1_FDD__
+ INT_Trace_Enter(INIT_UL1SM);
+ UL1SM_Init();
+ INT_Trace_Exit(INIT_UL1SM);
+#endif /* __MTK_UL1_FDD__ */
+
+#if defined(__LTE_RAT__) && defined(__EL1_ENABLE__)
+ INT_Trace_Enter(INIT_EL1SM);
+ EL1SM_Init();
+ INT_Trace_Exit(INIT_EL1SM);
+#endif /* __LTE_RAT__ && __EL1_ENABLE__ */
+
+#endif /* ATEST_DRV_ENABLE */
+#endif /* MTK_SLEEP_ENABLE */
+
+
+
+
+ INT_Trace_Enter(INIT_OSTD);
+#ifdef __HAPS_FPGA_CLK_ADJUST__
+ OSTD_SetFrmDur(KAL_MICROSECS_PER_TICK_REAL);
+#else
+ OSTD_SetFrmDur(KAL_MICROSECS_PER_TICK);
+#endif
+ OSTD_EnOST(KAL_TRUE);
+ INT_Trace_Exit(INIT_OSTD);
+
+
+#if 1 //wait for driver ready
+ INT_Trace_Enter(INIT_PTP);
+ ptp_init();
+ INT_Trace_Exit(INIT_PTP);
+#endif //wait for driver ready
+#if 0
+#if defined(IDMA_DOWNLOAD) && !defined(ATEST_DRV_ENVIRON)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* IDMA_DOWNLOAD && !ATEST_DRV_ENVIRON */
+#endif
+
+
+#ifdef NAND_SUPPORT
+ INT_Trace_Enter(INIT_NFIRESET);
+ NFI_Reset();
+ INT_Trace_Exit(INIT_NFIRESET);
+#endif /* NAND_SUPPORT */
+
+ /* Called before Drv_Init_Phase1() because AMIF user init is in Drv_Init_Phase1() */
+ INT_Trace_Enter(INIT_AMIF);
+ Drv_MDAPInterface_Init();
+ INT_Trace_Exit(INIT_AMIF);
+
+ INT_Trace_Enter(INIT_DRV1);
+ Drv_Init_Phase1();
+ INT_Trace_Exit(INIT_DRV1);
+
+#if !(defined(__ESL_ENABLE__) || defined(__SPV_UFPS_LOAD__))
+ INT_Trace_Enter(INIT_DVFS);
+ DVFS_init();
+ INT_Trace_Exit(INIT_DVFS);
+#endif
+
+
+ #ifndef __MAUI_BASIC__
+ /* MML1 H/W TXSYS initial */
+ INT_Trace_Enter(INIT_MML1_TXSYS);
+ MML1_TXSYS_Init();
+ INT_Trace_Exit(INIT_MML1_TXSYS);
+ #endif
+
+#if 0
+/* under construction !*/
+#endif
+
+#if 0//(__ZIMAGE_SUPPORT__)
+/* under construction !*/
+#endif /* __ZIMAGE_SUPPORT__ */
+
+#if 0
+#if defined(__DCM_WITH_COMPRESSION__) || defined(__DYNAMIC_CODE_MANAGER__)
+/* under construction !*/
+#endif
+#endif
+#if 0 //wait for driver ready
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //wait for driver ready
+ INT_Trace_Enter(INIT_RMPU_MD_INIT);
+ rmpu_md_init();
+ INT_Trace_Exit(INIT_RMPU_MD_INIT);
+
+ INT_Trace_Enter(INIT_BUSMON);
+ busmon_init();
+ INT_Trace_Exit(INIT_BUSMON);
+
+ INT_Trace_Enter(INIT_SFU_INIT);
+ drv_sfu_wrap_init();
+ INT_Trace_Exit(INIT_SFU_INIT);
+
+#else /*!defined(_SIMULATION) && !defined(__ESL_MASE__)*/
+
+#if defined(_SIMULATION)
+
+ //DIGRF_Platform_Init_Phase_1 : call before topsm init
+ INT_Trace_Enter(INIT_DIGRF1);
+ DIGRF_Platform_Init_Phase_1();
+ INT_Trace_Exit(INIT_DIGRF1);
+
+ INT_Trace_Enter(INIT_RM);
+ MODEM_TOPSM_ForceOnAllResource();
+ INT_Trace_Exit(INIT_RM);
+
+ //DIGRF_Platform_Init_Phase_2 : call after topsm init
+ INT_Trace_Enter(INIT_DIGRF2);
+ DIGRF_Platform_Init_Phase_2();
+ INT_Trace_Exit(INIT_DIGRF2);
+
+
+#endif /*_SIMULATION*/
+#endif /*!defined(_SIMULATION) && !defined(__ESL_MASE__)*/
+
+ //needed for ESL platform
+#if defined(__ESL_MASE_GEN97__) && defined(__MTK_TARGET__)
+ INT_Trace_Enter(INIT_DRV1);
+ Drv_Init_Phase1();
+ INT_Trace_Exit(INIT_DRV1);
+#endif /* __ESL_MASE_GEN97__ && __MTK_TARGET__ */
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_Get_PowerOn_Type
+*
+* DESCRIPTION
+* This function used to return the power on reason
+*
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* systemInitializeResource
+*
+* DESCRIPTION
+* This function aims resource initialization, including audio, image,
+* font etc.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void systemInitializeResource(void)
+{
+#if defined(__MTK_TARGET__) && defined (__HIF_CCCI_SUPPORT__)
+ kal_uint32 rand_seed_num_from_ap;
+
+ //If AP exist, MD will get random seed from AP through CCCI and then override the rand_num_seed
+ if (CCCI_MISC_INFO_SUPPORT != ccci_misc_data_feature_support(CCMSG_ID_MISCINFO_RANDOM_SEED_NUM, 4, &rand_seed_num_from_ap))
+ {
+ INT_Trace_Enter(INIT_GETRANDOMSEED_INTRAM);
+ }
+ else
+ {
+ rand_num_seed = rand_seed_num_from_ap;
+ INT_Trace_Enter(INIT_GETRANDOMSEED_AP);
+ }
+#else
+ INT_Trace_Enter(INIT_GETRANDOMSEED_INTRAM);
+#endif
+ srand(rand_num_seed);
+}
+
+/*************************************************************************
+* FUNCTION
+* INT_Config
+*
+* DESCRIPTION
+* This function implements adjusting Memory Block 0 (EMI_CON0) Wait
+* State's setting
+*
+* CALLS
+* INT_Decrypt, INT_SetPLL, INT_SetChipReg
+*
+* PARAMETERS
+*
+* RETURNS
+* the seed value for random number
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_Config(void)
+{
+#if !defined(_SIMULATION)
+
+#if 0
+#if defined(__MULTI_BOOT__) && !defined(L1D_TEST_COSIM)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(MCU_26M)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(MCU_52M)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* __MULTI_BOOT__ & !L1D_TEST_COSIM */
+#endif
+ INT_SetEMIPLL();
+
+#endif
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_BootMode
+*
+* DESCRIPTION
+* This function implements to return boot mode. Remember the routine muse
+* be called after Application_Initialize.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_uint16 INT_BootMode(void)
+{
+ /* Seamless META feature:
+ a. Always return normal boot
+ b. Assert when being used after scheduler */
+ if (KAL_FALSE == kal_query_systemInit())
+ {
+ ASSERT(0);
+ }
+ return (kal_uint16)MTK_NORMAL_MODE;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_SetMetaMode
+*
+* DESCRIPTION
+* This function implements to set hw register to enable meta mode.
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_SetMetaMode(void)
+{
+ *(volatile kal_uint16 *)BOOT_CONFIG_ADDR |= 0x0001;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_InvokeSSTEngine
+*
+*************************************************************************/
+#define _SST_FUNCTION_ENABLE_
+void INT_InvokeSSTEngine(kal_int32 err_code, kal_int32 os_err_code)
+{
+#ifdef _SST_FUNCTION_ENABLE_
+ /* _SST_FUNCTION_ENABLE_ should be locally defined such that
+ * custom release will remove these code
+ */
+ SST_InvokEngine(err_code, os_err_code);
+#endif
+ return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* release_bb_chip
+*
+* DESCRIPTION
+* This function returns the version number of the baseband chip
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_char* release_bb_chip(void)
+{
+ static kal_char str_return[]="MTxxxxx";
+
+#if defined(FPGA)
+ strcpy(str_return, "FPGA");
+#elif defined(MT6763)
+ strcpy(str_return, "MT6763");
+#elif defined(ZION)
+ strcpy(str_return, "ZION");
+#elif defined(MT6295M)
+ strcpy(str_return, "MT6295M");
+#elif defined(MT6297)
+ strcpy(str_return, "MT6297");
+#elif defined(MT6885)
+ strcpy(str_return, "MT6885");
+#elif defined(MERCURY)
+ strcpy(str_return, "MERCURY");
+#else
+#endif
+
+ return str_return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_VersionNumbers
+*
+* DESCRIPTION
+* This function returns the version number of the followings
+* 1. Chip version
+* 2. DSP version
+* 3. DSP patch version
+* 4. MCU software version
+* 5. Baseband board version
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+void INT_VersionNumbers(version_struct * ptr_version)
+{
+ ptr_version->bb_chip = release_bb_chip();
+#if !defined(__DSP_FCORE4__)
+ ptr_version->dsp_fw = release_dsp_fw();
+ ptr_version->dsp_ptch = release_dsp_ptch();
+#else
+ // Note: use empty string temporarily, need to discuss how we should fill these fields in FCore case
+ ptr_version->dsp_fw = " ";
+ ptr_version->dsp_ptch = " ";
+#endif //!__DSP_FCORE4__
+ ptr_version->mcu_sw = release_verno();
+ ptr_version->mcu_sw_branch = release_branch();
+ ptr_version->bb_board = release_hw_ver();
+ ptr_version->mcu_sw_flavor = release_flavor();
+ return;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_LteDspVersionNumbers
+*
+* DESCRIPTION
+* This function returns the version number of LTE DSP version
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+kal_bool INT_LteDspVersionNumbers(lte_dsp_version_struct * ptr_version)
+{
+#if defined(__LTE_RAT__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ {
+ ptr_version->dsp_fw = " ";
+ ptr_version->dsp_btime = " ";
+ return KAL_FALSE;
+ }
+
+#else
+ ptr_version->dsp_fw = " ";
+ ptr_version->dsp_btime = " ";
+
+ return KAL_FALSE;
+#endif
+}
+
+
+#if 1
+/*************************************************************************
+* FUNCTION
+* INT_SetCmdToSys
+*
+* DESCRIPTION
+* This function provide API for user to set necessary command to system
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+void INT_SetCmdToSys(INIT_SYSCMD_CODE cmd_val)
+{
+#if !defined(__SMART_PHONE_MODEM__) && !defined(__MODEM_ONLY__) /* 2012/07/13: Currently, only MT6280 is defined with __SMART_PHONE_MODEM__ */
+
+ // RETN_REG[2]: 1: Enter USBDL
+ // RETN_REG[1]: 1: BL download, 0: BROM download
+
+ /* Secure mode or BL support USB DL */
+ // Normal mode: enter bootloader download after reboot
+ // Rescue mode: enter BROM download after reboot
+
+ /* Others */
+ // Enter BROM download after reboot under either mode
+
+ INT_CLEAR_RETN_FLAG(0x06); // 3'b110
+
+ switch (cmd_val)
+ {
+#if defined(__MTK_SECURE_PLATFORM__) || defined(__USB_DOWNLOAD__)
+ case SYS_CMD_SET_BL_DL:
+ INT_CLEAR_SET_FLAG(0x06); // 3'b110
+ break;
+
+ case SYS_CMD_SET_BROM_DL:
+ INT_CLEAR_SET_FLAG(0x04); // 3'b100
+ break;
+#else /* __MTK_SECURE_PLATFORM__ || __USB_DOWNLOAD__ */
+ /* if BL does not support USB DL, enter BROM download after reboot under either mode */
+ case SYS_CMD_SET_BROM_DL:
+ case SYS_CMD_SET_BL_DL: /* this is actually BROM download */
+ INT_CLEAR_SET_FLAG(0x04); // 3'b100
+ break;
+#endif /* __MTK_SECURE_PLATFORM__ || __USB_DOWNLOAD__ */
+
+ // do not enter download mode
+ case SYS_CMD_CLR_DL_FLAG:
+ break;
+
+ default:
+ ASSERT(0);
+ break;
+ }
+
+#endif /* __SMART_PHONE_MODEM__ */
+
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetSysStaByCmd
+*
+* DESCRIPTION
+* This function provided for user to query the status of system
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+kal_uint32 INT_GetSysStaByCmd(INIT_SYSCMD_CODE cmd_val, void *data_p)
+{
+#if !defined(__SMART_PHONE_MODEM__)
+
+ switch (cmd_val)
+ {
+ case CHK_USB_META_WO_BAT:
+ if (SHARED_VAR(g_l_sw_misc_l) & (0x1 << 3))
+ {
+ return KAL_TRUE;
+ }
+ else
+ {
+ return KAL_FALSE;
+ }
+
+ case CHK_FAST_META:
+
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+#else
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+ {
+ return KAL_FALSE;
+ }
+
+ case SYS_CMD_BL_LOGO_DISPLAYED:
+
+#if defined(__FAST_LOGO__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif /* __FAST_LOGO__ */
+ {
+ return KAL_FALSE;
+ }
+
+ case SYS_CMD_GET_PWN_STA:
+
+
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+ return KAL_FALSE;
+
+#else
+
+#if 0
+/* under construction !*/
+#endif
+#endif
+
+ case SYS_CMD_GET_EMI_PARAM:
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+ return KAL_FALSE;
+
+#else
+
+#if 0
+/* under construction !*/
+#endif
+ return KAL_TRUE;
+#endif
+
+ break;
+
+ case SYS_CMD_BL_BROM_CMD_MODE_DISABLED:
+#if defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+ {
+ return KAL_FALSE;
+ }
+ default:
+ ASSERT(0);
+ break;
+ }
+
+
+#endif /* __SMART_PHONE_MODEM__ */
+
+ return KAL_FALSE;
+}
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_GetMetaModeSrc
+*
+* DESCRIPTION
+* Get Random Seed
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+MODE_ENTRY_SRC INT_GetMetaModeSrc(void)
+{
+ MODE_ENTRY_SRC state = E_BROM;
+
+
+#if defined(__TOOL_ACCESS_CTRL__)
+
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+#endif /* __TOOL_ACCESS_CTRL__ */
+ return state;
+
+
+
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetRandomSeed
+*
+* DESCRIPTION
+* Get Random Seed -- maybed passed from bootloader or use memory region
+* to create
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* random seed
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+#if defined(__SSDVT_TEST__)
+/* under construction !*/
+#else /* __SSDVT_TEST__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef __TIME_STAMP__
+/* under construction !*/
+#if 0
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+#endif
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#if defined(_SIMULATION)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* _SIMULATION */
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* !(__BL_ENABLE__ || _NAND_FLASH_BOOTING_ || __NOR_FLASH_BOOTING__) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* !(__BL_ENABLE__ || _NAND_FLASH_BOOTING_ || __NOR_FLASH_BOOTING__) */
+/* under construction !*/
+#endif /* _SIMULATION */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __SSDVT_TEST__ */
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_IsBootForUSBAT
+*
+* DESCRIPTION
+* This function is used to for user to query if USBAT is enabled
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+kal_bool INT_IsBootForUSBAT(void)
+{
+ return SHARED_VAR(_IsBootForUSBAT);
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetBromBlSyncType
+*
+* DESCRIPTION
+* For DHL, it needs to know the channel used to sync with tool in bootrom
+* or boorloader
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* The sync channel used by bootrom or bootloader
+*
+*************************************************************************/
+ser_chl_t INT_GetBromBlSyncType(void)
+{
+#ifdef __BL_ENABLE__
+#if 0
+/* under construction !*/
+#endif
+#else
+ //For internal phone project, it does not have bootloader
+ //Always return CHL_CCCI
+ return CHL_CCCI;
+#endif /*__BL_ENABLE__*/
+}
+
+__attribute__((__section__("NONCACHEDRW"))) INIT_STAGE INT_init_stage = E_DEFAULT;
+INIT_STAGE INT_QueryInitStage(void)
+{
+ return INT_init_stage;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_PollingShareVariable
+*
+* DESCRIPTION
+*
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+*************************************************************************/
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if ( defined(__FS_SYSDRV_ON_NAND__) || defined( _NAND_FLASH_BOOTING_) )
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __FS_SYSDRV_ON_NAND__ || _NAND_FLASH_BOOTING_ */
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* _NAND_FLASH_BOOTING_ || __EMMC_BOOTING__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if (defined(_NAND_FLASH_BOOTING_) && !defined(__NFB_SINGLE_ROM__)) || defined(__EMMC_BOOTING__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* _NAND_FLASH_BOOTING_ || __EMMC_BOOTING__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__ARM9_MMU__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __ARM9_MMU__ */
+/* under construction !*/
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef __TIME_STAMP__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifdef __TIME_STAMP__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__)) */
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__SV5_ENABLED__) || defined(__SV5X_ENABLED__) /* __SV5_ENABLED__ || __SV5X_ENABLED__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* __SV5_ENABLED__ || __SV5X_ENABLED__ */
+/* under construction !*/
+#if !(defined(__BL_ENABLE__) || defined(_NAND_FLASH_BOOTING_) || defined(__NOR_FLASH_BOOTING__) || defined(__EMMC_BOOTING__))
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else /* !(__BL_ENABLE__ || _NAND_FLASH_BOOTING_ || __NOR_FLASH_BOOTING__ || __EMMC_BOOTING__) */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* _NAND_FLASH_BOOTING_ */
+/* under construction !*/
+#endif /* __SV5_ENABLED__ || __SV5X_ENABLED__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if defined __MD97__ || defined __MD97P__
+#define INIT_RO_NOINIT_DATA __attribute__((section("NONCACHED_RODATA"))) __attribute__((noinline))
+INIT_RO_NOINIT_DATA kal_uint32 domain_config[12] = {0, 1, 1, 0, 1, 2, 0, 1, 2, 0, 1, 2};
+void Set_VPE_Domain_Type()
+{
+
+ kal_uint32 domain_type;
+ kal_uint32 cpu_id = kal_get_current_vpe_id();
+ /* KScratch4 bits 1:0 are used to keep VPE domain type identifier for quick
+ look-up for each VPE */
+ domain_type = domain_config[cpu_id];
+
+ __asm__ __volatile__(
+ "mfc0 $a0, $31, 5 \n" \
+ "ins $a0, %0, 0, 2 \n" \
+ "mtc0 $a0, $31, 5 \n" \
+ "ehb \n" \
+ : \
+ :"d" (domain_type) \
+ :"$a0"
+ );
+
+}
+#endif /* defined __MD97__ && !defined MT6297_IA */
+
+#define PROFILE_CNT 100
+#define INIT_MCURW_NOINIT_DATA __attribute__((section("MCURW_HWRO_DNC_NOINIT"))) __attribute__((noinline))
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 EMM_Init_Flag = 0;
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 EMM_HS1_BootTrace_Addr = 0;
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 BootTrace_Profile_Data[16][PROFILE_CNT][2] = {0};
+INIT_MCURW_NOINIT_DATA volatile kal_uint32 BootTrace_Profile_Idx[16] = {0};
+
+#include <boot_comm.h>
+#include <sst_defs.h>
+
+#if defined(__ESL_MASE__)
+kal_uint32 Boot_Trace_PreInit(){
+ EMM_Init_Flag = 0;
+ return 0;
+}
+kal_uint32 INC_TRC_PROFILE(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ return 0;
+}
+
+void Set_HS1_Boot_Trace(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ return ;
+}
+
+
+#else
+kal_uint32 Boot_Trace_PreInit(){
+ kal_uint32 i = 0;
+ EMM_Init_Flag = 0;
+ for(i=0 ; i<16; i++)
+ {
+ BootTrace_Profile_Idx[i] = 0;
+ }
+ *(volatile kal_uint32*)(MDCCIF_BOOTTRC_DATA)=0x56552552;
+ return 0;
+}
+kal_uint32 INC_TRC_PROFILE(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ kal_uint32 cpu_id = kal_get_current_vpe_id();
+ BootTrace_Profile_Data[cpu_id][BootTrace_Profile_Idx[cpu_id]][0]=traceData;
+ BootTrace_Profile_Data[cpu_id][BootTrace_Profile_Idx[cpu_id]][1]=traceTime;
+ BootTrace_Profile_Idx[cpu_id] +=1;
+ if(BootTrace_Profile_Idx[cpu_id] == PROFILE_CNT)
+ BootTrace_Profile_Idx[cpu_id] = 0;
+
+ return 0;
+}
+void Set_HS1_Boot_Trace(kal_uint32 traceData, kal_uint32 traceTime)
+{
+ kal_uint32 cpu_id = kal_get_current_vpe_id();
+ kal_uint32 HS1Time = ust_get_current_time();
+
+ if(EMM_Init_Flag == 0)
+ {
+ /*Ongoing*/
+ /*Check EMM address in CCIF SRAM*/
+ /*1: dispatch 2:not dispatch*/
+ if(*(volatile kal_uint32*)(g_EMM_MAIN_BUFF_MAGIC_ADDR) == g_EMM_MAIN_BUFF_MAGIC)
+ {
+ EMM_Init_Flag = 1;
+ EMM_HS1_BootTrace_Addr = *(volatile kal_uint32*)(g_EMM_MAIN_BUFF_ADDR_PTR) + HS1_BOOT_TRACE_OFFSET;
+ *(volatile kal_uint32*)(EMM_HS1_BootTrace_Addr)=0x56552552;
+ }
+ else
+ {
+ EMM_Init_Flag = 2;
+ }
+ }
+ else if(EMM_Init_Flag == 1)
+ { //write to CCIF SRAM
+ *(volatile kal_uint32*)(MDCCIF_BOOTTRC_DATA + (cpu_id+1)*4 )=traceData;
+ //Write to EMM
+ *(volatile kal_uint32*)(EMM_HS1_BootTrace_Addr + (cpu_id+1)*8 )=traceData;
+ *(volatile kal_uint32*)(EMM_HS1_BootTrace_Addr + (cpu_id+1)*8 +4)=HS1Time;
+
+ }
+ else
+ {
+ *(volatile kal_uint32*)(MDCCIF_BOOTTRC_DATA + (cpu_id+1)*4 )=traceData;
+ }
+#if defined(__PROFILE_INIT__)
+ //write log for profiling
+ INC_TRC_PROFILE(traceData,traceTime);
+
+#endif
+ return;
+}
+#endif //defined(__ESL_MASE__)
+
+kal_bool INT_hasEMMAddress(void)
+{
+#if 1
+ kal_bool hasEMM = (EMM_Init_Flag == 1);
+ kal_uint32 emmSize = 0;
+
+ if(hasEMM)
+ {
+ emmSize = (*(kal_uint32 volatile*)(g_EMM_MAIN_BUFF_SIZE_PTR));
+ if (emmSize < (BOOTUP_TRC_OFFSET + (VPE_BOOTUP_TRC_SIZE * SYS_MCU_NUM_VPE)) || emmSize > 0x10000000)
+ {
+ EXT_ASSERT(0, emmSize, (BOOTUP_TRC_OFFSET + (VPE_BOOTUP_TRC_SIZE * SYS_MCU_NUM_VPE)), 0x10000000);
+ }
+ }
+
+ return hasEMM;
+#else
+/* under construction !*/
+#endif
+}
+
+#endif /*__FUE__*/
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_cm.S b/mcu/driver/sys_drv/init/src/md97p/init_cm.S
new file mode 100644
index 0000000..935e8f0
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_cm.S
@@ -0,0 +1,119 @@
+/*
+ * init_cm.S
+ *
+ * initializatoin of the Coherency Manager
+ */
+
+#include <boot.h>
+#include <cps.h>
+#include <l2cache_def.h>
+
+#define GCR_CUSTOM_BASE (0x60)
+#define GCR_L2_ONLY_SYNC_BASE (0x70)
+
+.set noreorder // Don't allow the assembler to reorder instructions.
+.set noat // Don't allow the assembler to use r1(at) for synthetic instr
+.set nomt
+.set nodsp
+
+/**************************************************************************************/
+
+.macro set_region gcr_reg, base_off, mask_off, base_reg, mask_reg
+ sw \base_reg, \base_off(\gcr_reg);
+ sw \mask_reg, \mask_off(\gcr_reg);
+.endm
+
+.macro cfg_region gcr_reg, base_off, mask_off, reg, addr, addr_msk, target, cca_ov_en, cca_ov_val, drop_l2
+ lui \reg, %hi(\addr);
+ sw \reg, \base_off(\gcr_reg);
+ li \reg, ( ((\addr_msk & 0xffff) <<16) |\
+ ((\cca_ov_val & 0x7) <<5) |\
+ ((\cca_ov_en & 0x1) <<4) |\
+ ((\drop_l2 & 0x1) <<2) |\
+ ((\target & 0x3) <<0) );
+ sw \reg, \mask_off(\gcr_reg);
+.endm
+
+.macro init_cm_macro
+
+#if defined(no_cpc)
+ beqzc r11_is_cps, 1f // skip if not a CPS or CM register verification failed.
+#endif
+
+ li r22_gcr_addr, GCR_CONFIG_ADDR // Use r22 ($s6) for GCR Base Address
+
+ // Allow each core access to the CM registers (they should only access their local registers.)
+ lw $a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
+ ext r19_more_cores, $a0, PCORES, PCORES_S // Extract PCORES
+ li $a0, 2 // Start building mask for cores in this cps
+ sll $a0, $a0, r19_more_cores
+ addiu $a0, -1 // Complete mask.
+ sw $a0, GCR_ACCESS(r22_gcr_addr) // GCR_ACCESS
+
+ // Force Disabled All Regions
+ lui $a0, %hi(0xffff0000)
+ set_region r22_gcr_addr, GCR_REG0_BASE, GCR_REG0_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG1_BASE, GCR_REG1_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG2_BASE, GCR_REG2_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG3_BASE, GCR_REG3_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG4_BASE, GCR_REG4_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG5_BASE, GCR_REG5_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG6_BASE, GCR_REG6_MASK, $a0, $a0
+ set_region r22_gcr_addr, GCR_REG7_BASE, GCR_REG7_MASK, $a0, $a0
+
+ // Config MMIO Regions
+ cfg_region r22_gcr_addr, GCR_REG0_BASE, GCR_REG0_MASK, $a0, 0xA0000000, 0xE000 /* 512MB */, 2 /* MMIO0 */, 0 /* CCA_OV_EN */, 0x0 /* CCA_OV */, 0x0 /* DROP_L2 */
+ cfg_region r22_gcr_addr, GCR_REG1_BASE, GCR_REG1_MASK, $a0, 0xC0000000, 0xE000 /* 512MB */, 2 /* MMIO0 */, 0 /* CCA_OV_EN */, 0x0 /* CCA_OV */, 0x0 /* DROP_L2 */
+
+ /* Set Custom GCR Base Address */
+ li $a1, (GCR_CUSTOM_ADDR | 0x1 /* Enable-Bit */)
+ sw $a1, GCR_CUSTOM_BASE(r22_gcr_addr)
+
+ /* Set all errors to cause exception instead of interrupt */
+ sw $zero, GCR_ERROR_MASK(r22_gcr_addr)
+
+ /* Set L2-Only-Sync address (defined in l2cache_def.h) */
+ li $a0, (l2_sync_base | 0x1 /* Enable-Bit */)
+ sw $a0, GCR_L2_ONLY_SYNC_BASE(r22_gcr_addr)
+1:
+ jrc.hb $ra
+.endm init_cm_macro
+
+.macro init_cm_wt_macro
+#if (defined(MIPS_IA_ENABLE_L2_CACHE) && defined(MIPS_IA_ENABLE_L2_CACHE_WT))
+ li r22_gcr_addr, GCR_CONFIG_ADDR
+ cfg_region r22_gcr_addr, GCR_REG2_BASE, GCR_REG2_MASK, $a0, 0x60000000, 0xE000 /* 512MB */, 1 /* MEM */, 1 /* CCA_OV_EN */, 0x0 /* WT */, 0x0 /* DROP_L2 */
+ cfg_region r22_gcr_addr, GCR_REG5_BASE, GCR_REG5_MASK, $a0, 0x80000000, 0xF000 /* 256MB */, 1 /* MEM */, 1 /* CCA_OV_EN */, 0x0 /* WT */, 0x0 /* DROP_L2 */
+ cfg_region r22_gcr_addr, GCR_REG6_BASE, GCR_REG6_MASK, $a0, 0x40000000, 0xF000 /* 256MB */, 1 /* MEM */, 1 /* CCA_OV_EN */, 0x0 /* WT */, 0x0 /* DROP_L2 */
+#endif
+ jrc.hb $ra
+.endm init_cm_wt_macro
+
+.section ".text.init_cm_c", "ax"
+.globl init_cm_c
+.ent init_cm_c
+init_cm_c:
+ init_cm_macro
+.end init_cm_c
+
+.section ".text.init_cm_wt_c", "ax"
+.globl init_cm_wt_c
+.ent init_cm_wt_c
+init_cm_wt_c:
+ init_cm_wt_macro
+.end init_cm_wt_c
+
+.section "NONCACHED_ROCODE", "ax"
+.globl init_cm
+.ent init_cm
+init_cm:
+ init_cm_macro
+.end init_cm
+
+.section "NONCACHED_ROCODE", "ax"
+.globl init_cm_wt
+.ent init_cm_wt
+init_cm_wt:
+ init_cm_wt_macro
+.end init_cm_wt
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_comm.c b/mcu/driver/sys_drv/init/src/md97p/init_comm.c
new file mode 100644
index 0000000..792394c
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_comm.c
@@ -0,0 +1,1101 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+[MAUI_03149504] ([MAUI_03180970]) all time memory dump
+[MAUI_03121063] remove PDN registers
+[MAUI_03147344] Dummy read for early response HW
+[MAUI_03161918] remove custom_setAdvEMI from bootarm.S
+[MAUI_03157059] security use meta to write
+
+ * removed!
+ *
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#include "kal_internal_api.h"
+#include "kal_trace.h"
+#include "reg_base.h"
+#include "config_hw.h"
+#include "emi_hw.h"
+//#include "init.h"
+#include "intrCtrl.h"
+#include "isrentry.h"
+//MSBB remove #include "custom_config.h"
+#include "stack_buff_pool.h"
+#include "fat_fs.h"
+#include "drv_comm.h"
+//MSBB remove #include "wdt_hw.h"
+#include "wdt_sw.h"
+#include "bmt.h"
+#include "dcl.h"
+#include "drvpdn.h"
+//#include "SST_init.h" /* for sw version check in INT_Version_Check() */
+#include <stdio.h>
+#include <string.h>
+#if defined(__ARMCC_VERSION)
+#include <rt_misc.h> /* for __rt_lib_init() */
+#endif
+#include <stdlib.h>
+#include "cache_sw.h"
+//#include "page.h"
+#include "md2g_drv.h"
+//#include "bl_features.h"
+//#include "bl_setting.h"
+//#include "bl_loader.h"
+#include "system_trc.h"
+#include "init_trc_api.h"
+//#include "ex_item.h"
+#include "init_comm.h"
+#include "cp15.h"
+#include "cpu_info.h"
+
+
+
+#ifdef __MULTI_BOOT__
+#include "syscomp_config.h"
+#include "multiboot_config.h"
+#endif /* __MULTI_BOOT__ */
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+#include "cp15.h"
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+
+#if defined(__SMART_PHONE_MODEM__)
+#include "ccci.h"
+#endif /* __SMART_PHONE_MODEM__ */
+
+#if defined(__FOTA_DM__)
+#include "fue_err.h"
+#include "custom_fota.h"
+#include "custom_img_config.h"
+#include "fue.h"
+#include "SSF_fue_support.h"
+#endif
+#if !defined(__UBL__) && !defined(__FUE__)
+#include "ostd_public.h"
+#endif
+
+#include "ex_public.h"
+#include "cm2_drv.h"
+
+/*******************************************************************************
+ * Define pragma
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Define global data
+ *******************************************************************************/
+/* [BB porting] please make sure the register address is correct and scatter file palced in the correct region */
+#if defined(EMI_base)
+const kal_uint32 g_EMI_BASE_REG = EMI_base;
+#endif /* EMI_base */
+// Bootup trace global array
+__attribute__((aligned(32))) BOOTTRACE_FINAL_STEP_STRUCT INC_Init_Step[SYS_MCU_NUM_VPE] = {{0}};
+
+#if defined(__MTK_TARGET__)
+/* bb reg dump setting */
+EX_BBREG_DUMP chipversion_dump;
+const kal_uint32 chipversion_dump_regions[] =
+{
+#if (defined(MT6763))
+ MD_CONFIG_base, 0x0020, 4, /* chip version and sw misc registers*/
+#else
+ 0, 0, 0
+#endif
+};
+#endif /* __MTK_TARGET__ */
+
+
+/*******************************************************************************
+ * Declare import data
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Declare import function prototype
+ *******************************************************************************/
+
+
+
+/*************************************************************************
+* FUNCTION
+* AnalogDieID
+*
+* DESCRIPTION
+* This function returns identification of analog die
+*
+* CALLS
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* Identification of analog die
+*
+* GLOBALS AFFECTED
+* None
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
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+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef ExtraVer
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
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+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* fake function */
+void INT_Version_Check(void)
+{
+}
+
+void INT_SW_VersionCheck(void)
+{
+}
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_ecoVersion
+*
+* DESCRIPTION
+* This function returns the ECO version number of baseband chipset
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+/* [BB porting] Please make sure the the correlated enum and code is added since the default case is ext_assert */
+/* Please be aware that new chips may use INT_SW_SecVersion */
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+/*************************************************************************
+* FUNCTION
+* INT_GetCurrentTime
+*
+* DESCRIPTION
+* This function access 32KHz Counter and return Counter Value
+*
+* CALLS
+*
+* PARAMETERS
+*
+* RETURNS
+* Value of 32KHz Counter
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+/* for SNOR, this function should be placed in RAM */
+#if defined(__MTK_TARGET__)
+#if defined(__UBL__) || defined(__FUE__)
+//#pragma arm section code = "INTERNCODE"
+#endif
+#endif //__MTK_TARGET__
+
+/* [BB porting] confirm with L1 if the function is support in new chip */
+kal_uint32 INT_GetCurrentTime(void)
+{
+#if defined(__APPLICATION_PROCESSOR__)
+ return 0; // Not Support Yet
+#elif defined(ATEST_DRV_ENVIRON)
+ return 0; // Not Support Yet
+#else
+ /*
+ * Call API provided by L1
+ */
+ return 0;
+#endif /* __APPLICATION_PROCESSOR__ */
+}
+
+
+/*************************************************************************
+* FUNCTION
+* INT_ChipName
+*
+* DESCRIPTION
+* This function is a special use for those users desire to run on
+* different chips with the same SW load.
+*
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+/* [BB porting] Make sure if the rule is changed or need to add for a new chip */
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_ChipGroup
+*
+* DESCRIPTION
+* This function is a special use for those users desire to run on
+* different chips with the same SW load.
+*
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*Only FPGA support this function*/
+#if defined (__FPGA__)
+HW_PURPOSE INT_FPGA_PURPOSE(void)
+{
+
+ kal_uint32 purpose_code = *((volatile kal_uint32 *)(PURPOSE_CODE_BASE));
+ HW_PURPOSE purpose;
+
+ if(purpose_code==0x55AA55AA)
+ {
+#if defined(__PALLADIUM__)
+ purpose = FPGA_U4G_LTEL2;
+ return purpose;
+#else // __PALLADIUM__
+ return PURPOSE_NotSupport;
+#endif // __PALLADIUM__
+ }
+ else
+ {
+ purpose_code = (purpose_code & PURPOSE_CODE_MASK)>>PURPOSE_CODE_BIT;
+ purpose = PURPOSE_NotSupport;
+#if defined(__MD97__) || defined(__MD97P__)
+#if defined (__FPGA__)
+ if(purpose_code==1) purpose = FPGA_H1;
+ else if(purpose_code==2) purpose = FPGA_H2;
+ else if(purpose_code==3) purpose = FPGA_H3;
+ else if(purpose_code==4) purpose = FPGA_H4;
+ else if(purpose_code==5) purpose = FPGA_H5;
+ else if(purpose_code==6) purpose = FPGA_H6;
+ else purpose = PURPOSE_NotSupport;
+#else
+ purpose = FPGA_H5;
+#endif
+#else
+ if(purpose_code==1)
+ {
+ purpose = FPGA_Platform;
+ }
+ else if(purpose_code==2)
+ {
+ purpose = FPGA_LTEL2;
+ }
+ else if(purpose_code==3)
+ {
+ purpose = FPGA_SIB;
+ }
+ else if(purpose_code==5)
+ {
+ purpose = FPGA_U4G;
+ }
+ else if(purpose_code==6)
+ {
+ purpose = FPGA_U4G_LTEL2;
+ }
+ else
+ {
+ purpose = PURPOSE_NotSupport;
+ }
+#endif
+ return purpose;
+ }
+}
+#endif
+HW_CORENUM INT_FPGA_CORENUM(void)
+{
+
+ kal_uint32 purpose_code = *((volatile kal_uint32 *)(PURPOSE_CODE_BASE));
+ HW_CORENUM corenum;
+
+ if(purpose_code==0x55AA55AA)
+ {
+#if defined(__PALLADIUM__)
+ corenum = CORENUM_2;
+ return corenum;
+#else // __PALLADIUM__
+ return CORENUM_NotSupport;
+#endif // __PALLADIUM__
+ }
+ else
+ {
+ purpose_code = (purpose_code & CORENUM_MASK)>>CORENUM_BIT;
+ corenum = CORENUM_NotSupport;
+ if(purpose_code==1)
+ {
+ corenum = CORENUM_1;
+ }
+ else if(purpose_code==2)
+ {
+ corenum = CORENUM_2;
+ }
+ else if(purpose_code==3)
+ {
+ corenum = CORENUM_3;
+ }
+ else if(purpose_code==4)
+ {
+ corenum = CORENUM_4;
+ }
+ return corenum;
+ }
+}
+HW_CORENUM INT_QUERY_CORENUM(void)
+{
+#if defined(__SINGLE_CORE__)
+ return CORENUM_1;
+#else
+#if defined(__MTK_TARGET__) || defined(__FPGA__) || defined(__ESL_ENABLE__) || defined(UMOLYE_COSIM) || defined(__PALLADIUM__)
+ HW_CORENUM corenum;
+ corenum = query_cm2_corenum();
+ return corenum;
+#else
+#error("Not support now.");
+#endif
+#endif
+}
+
+/**
+ * This function is used to detect ASIC or FPGA version of Palladium
+ * If @0xA02100FC = 0xA51C, it means ASIC version of Palladium;
+ * otherwise others.
+ */
+#if 0
+/* under construction !*/
+/* under construction !*/
+#if defined(__FPGA__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INITSYNC_WriteAndPoll
+*
+* DESCRIPTION
+* This function used for system init dual core sync procedure
+*
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*************************************************************************
+* FUNCTION
+* INT_Set_BootSlave
+*
+* DESCRIPTION
+* This function is used to set the Boot-Slave
+*
+*
+* PARAMETERS
+* kal_uint32 core_index: assigned core index
+* kal_uint32 jmp_addr: set jump address
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_Set_BootSlave(kal_uint32 core_index, kal_uint32 jmp_addr)
+{
+#if defined(__MTK_TARGET__)
+ ASSERT(core_index <= 3);
+
+ *(volatile kal_uint32 *)MCU_BOOTSLV_JUMP_ADDR_UNLOCK(core_index) = MCU_BOOTSLV_JUMP_KEY_VALUE;
+ *(volatile kal_uint32 *)MCU_BOOTSLV_JUMP_ADDR(core_index) = jmp_addr;
+ *(volatile kal_uint32 *)MCU_BOOTSLV_JUMP_ADDR_UPDATE(core_index) = 1;
+ // Make sure write to destination
+ // Check that if MO_Sync() is sync 0x6?
+
+ MO_Sync();
+#endif
+ return;
+}
+
+kal_bool INT_ChipVersion_BBREG_callback()
+{
+ return KAL_TRUE;
+}
+void INT_Init_Misc()
+{
+#if defined(__MTK_TARGET__)
+ /* register bb reg dump */
+ chipversion_dump.regions = (kal_uint32*)chipversion_dump_regions;
+ chipversion_dump.num = sizeof(chipversion_dump_regions) / (sizeof(kal_uint32) * 3);
+ chipversion_dump.bbreg_dump_callback = INT_ChipVersion_BBREG_callback;
+ EX_REGISTER_BBREG_DUMP(&chipversion_dump);
+#endif /* __MTK_TARGET__ */
+}
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_tc.S b/mcu/driver/sys_drv/init/src/md97p/init_tc.S
new file mode 100644
index 0000000..ef997d1
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_tc.S
@@ -0,0 +1,213 @@
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+ .set nomips16
+/**************************************************************************************
+ $a0 = vpe id, $a1 = tc id, $a2 = stack pointer, $a3 = isMVP?
+**************************************************************************************/
+LEAF(init_tc)
+
+ /* This is executing on TC_a1 bound to VPE_a1. Therefore VPEConf0.MVP is set. */
+
+ /* Config C0_MVPCONTROL.VPC[1]
+ * Purpose: Enter config mode */
+ mfc0 $t0, C0_MVPCONTROL
+ or $t0, (1 << 1) // set VPC[1]
+ ins $t0, $zero, 0, 1 // clear EVP[0]
+ mtc0 $t0, C0_MVPCONTROL
+ ehb
+
+ /* Config C0_VPECONTROL.TargTC[7:0]
+ * to set target TC be configured */
+// li a3_TC, 0x2
+ mfc0 $t0, C0_VPECONTROL // read C0_VPECONTROL
+ ins $t0, $a1, 0, 8 // insert TargTC[7:0]
+// ins $t0, a3_TC, 0, 8 // insert TargTC[7:0]
+ mtc0 $t0, C0_VPECONTROL // write C0_VPECONTROL
+ ehb
+
+ /* Config C0_TCHALT.H[0]
+ * to halt target TC, a3_TC */
+ li $t0, 1 // set Halt bit
+ mttc0 $t0, C0_TCHALT // write C0_TCHALT
+ ehb
+
+ /* Config C0_TCBIND.CurVPE[3:0]
+ * bind TC2 to VPE1 */
+// li $t1, INDEX_VPE1
+ mftc0 $t0, C0_TCBIND // Read C0_TCBIND
+ ins $t0, $a0, 0, 4 // change CurVPE[3:0]
+// ins $t0, $t1, 0, 4 // change CurVPE[3:0]
+ mttc0 $t0, C0_TCBIND // write C0_TCBIND
+ ehb
+
+ beqzc $a3, INT_Initialize_GPR
+
+INT_MVP_SetupConfig1:
+ /* Only VPE1 TC1 set YQMask */
+ addi $t0, $zero, 0xF0F // bit 0~3 for VPE0, 8~11 for VPE1
+ mttc0 $t0, C0_YQMASK
+
+ // Set XTC for active a3_TC's
+ mftc0 $t0, C0_VPECONF0 // read C0_VPECONF0
+ ins $t0, $a1, 21, 8 // insert XTC[28:21]
+ mttc0 $t0, C0_VPECONF0 // write C0_VPECONF0
+
+
+/***************************************************
+ Set up TCStatus register:
+ * Disable Coprocessor Usable bits
+ * Disable MDMX/DSP ASE
+ * Clear Dirty TC_a1
+ * not dynamically allocatable
+ * not allocated
+ * Kernel mode
+ * interrupt exempt
+ * ASID 0
+****************************************************/
+
+INT_Initialize_GPR:
+
+ li $t1, 0x2
+ beqc $t1, $a1, INT_Set_IXMT_done
+ li $t1, 0x4
+ beqc $t1, $a1, INT_Set_IXMT_done
+
+ li $t0, (1 << 10) // set IXMT[10]
+ mttc0 $t0, C0_TCSTATUS // write C0_TCSTATUS
+.set noat
+INT_Set_IXMT_done:
+
+ // Initialize the a3_TC's register file
+ li $t0, 0xDEADBEEF
+ mttgpr $t0, $at
+ mttgpr $t0, $t4
+ mttgpr $t0, $t5
+ mttgpr $t0, $a0
+ mttgpr $t0, $a1
+ mttgpr $t0, $a2
+ mttgpr $t0, $a3
+ mttgpr $t0, $a4
+ mttgpr $t0, $a5
+ mttgpr $t0, $a6
+ mttgpr $t0, $a7
+ mttgpr $t0, $t0
+ mttgpr $t0, $t1
+ mttgpr $t0, $t2
+ mttgpr $t0, $t3
+ mttgpr $t0, $s0
+ mttgpr $t0, $s1
+ mttgpr $t0, $s2
+ mttgpr $t0, $s3
+ mttgpr $t0, $s4
+ mttgpr $t0, $s5
+ mttgpr $t0, $s6
+ mttgpr $t0, $s7
+ mttgpr $t0, $t8
+ mttgpr $t0, $t9
+ mttgpr $t0, $k0
+ mttgpr $t0, $k1
+ mttgpr $t0, $gp
+// mttgpr $t0, $sp
+ mttgpr $t0, $fp
+ mttgpr $t0, $ra
+
+
+ bnezc $a3, INT_MVP_SetupConfig2
+ // Initialize the sp
+ lw $a2, 0x0($a2)
+ li $t0, 0xFFFFFFF0
+ and $a2, $a2, $t0
+ mttgpr $a2, $sp
+
+
+ // VPE1 of each core can execute cached as it's L1 I$ has already been initialized.
+ // and the L2$ has been initialized or "disabled" via CCA override.
+ la $a1, HRT_domain_C_env // Convert to cached kseg0 address in case we linked to kseg1.
+ mttc0 $a1, C0_TCRESTART // write C0_TCRESTART
+ ehb
+
+ bc INT_SetupTCRESTART_done
+
+.set at
+INT_MVP_SetupConfig2:
+ /* Enable multi-threading with a3_TC's VPE
+ * Enable multi-threading of VPE1 */
+ li $t1, 1
+ mftc0 $t0, C0_VPECONTROL // read C0_VPECONTROL
+ ins $t0, $t1, 15, 1 // set TE[15]
+ mttc0 $t0, C0_VPECONTROL // write C0_VPECONTROL
+
+ // For VPE1..n
+ // Only VPE1 TC1 clear VPA and set master VPE
+ mftc0 $t0, C0_VPECONF0 // read C0_VPECONF0
+ ins $t0, $zero, 0, 1 // clear VPA[0]
+ or $t0, (1 << 1) // set MVP[1]
+ mttc0 $t0, C0_VPECONF0 // write C0_VPECONF0
+
+ la $t0, INT_Vectors
+ mttc0 $t0, C0_EPC // write C0_EPC
+
+ mttc0 $zero, C0_CAUSE // write C0_CAUSE
+
+ mfc0 $t0, C0_CONFIG // read C0_CONFIG
+ mttc0 $t0, C0_CONFIG // write C0_CONFIG
+
+ // VPE1 of each core can execute cached as it's L1 I$ has already been initialized.
+ // and the L2$ has been initialized or "disabled" via CCA override.
+ la $a1, INT_Vectors // Convert to cached kseg0 address in case we linked to kseg1.
+ mttc0 $a1, C0_TCRESTART // write C0_TCRESTART
+ ehb
+
+INT_SetupTCRESTART_done:
+ // Yes.. this is undoing all of the work done above... :)
+ mftc0 $t0, C0_TCSTATUS // read C0_TCSTATUS
+ //ins $t0, $zero, 10, 1 // clear IXMT[10]
+ li $t1, (1 << 13)
+ or $t0, $t0, $t1
+ li $t1, (1 << 15)
+ or $t0, $t0, $t1
+// ori $t0, (1 << 13) // set A[13]
+// ori $t0, (1 << 15) // set DA[15]
+#if (MX_FEATURE == 1)
+ li $t1, 0x1
+ ins $t0, $t1, 27, 1 // set TMX[27]
+#endif
+ mttc0 $t0, C0_TCSTATUS // write C0_TCSTATUS
+
+ // keep halt status
+ //mttc0 $zero, C0_TCHALT // write C0_TCHALT
+ beqzc $a3, INT_Init_TC_done
+
+INT_MVP_SetupConfig3:
+
+ /* Set C0_TCSCHEDULE */
+ mttc0 $zero, C0_TCSCHEDULE
+
+ mttc0 $zero, C0_TCHALT // write C0_TCHALT
+
+ // Only VPE1 TC1 set VPA
+ mftc0 $t0, C0_VPECONF0 // read C0_VPECONF0
+ ori $t0, 1 // set VPA[0]
+ mttc0 $t0, C0_VPECONF0 // write C0_VPECONF0
+
+INT_Init_TC_done:
+ // Exit config mode
+ mfc0 $t0, C0_MVPCONTROL // read C0_MVPCONTROL
+ ori $t0, 1 // set EVP[0] will enable execution by vpe1
+ ins $t0, $zero, 1, 1 // clear VPC[1]
+ mtc0 $t0, C0_MVPCONTROL // write C0_MVPCONTROL
+ ehb
+
+ jrc $ra
+
+END(init_tc)
+.set pop
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_trc.c b/mcu/driver/sys_drv/init/src/md97p/init_trc.c
new file mode 100644
index 0000000..48f24d7
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_trc.c
@@ -0,0 +1,483 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_trc.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines bootup trace functions.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include <string.h>
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_trace.h"
+#include "ccci_if.h"
+#include "init_trc_api.h"
+#include "ex_mem_manager_public.h" //EMM_GetBufInfo, EMM_ClearDbgInfo
+/*******************************************************************************
+ * Define global data
+ *******************************************************************************/
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+ kal_bool is_init_log_enable; // setup in INT_setInitLogFlag
+ kal_bool is_init_stage;
+#else /* __KEYPAD_DEBUG_TRACE__ */
+ const kal_bool is_init_log_enable = KAL_FALSE;
+ kal_bool is_init_stage = KAL_TRUE;
+#endif /* __KEYPAD_DEBUG_TRACE__ */
+
+//#if defined(__SP_BOOTTRC_ENABLE__)
+#if defined(__HIF_CCCI_SUPPORT__)
+#define BOOTTRACE_BKBUF_SIZE (1024*3)
+//#define BOOTTRACE_BKBUF_SIZE (768*2)
+kal_uint8 boot_trace_log[BOOTTRACE_BKBUF_SIZE] = {0}; // EMM reserves 1.5k currently
+#endif
+
+/*******************************************************************************
+ * Declare import data
+ *******************************************************************************/
+extern boot_mode_type system_boot_mode;
+
+
+/*******************************************************************************
+ * Declare function prototype
+
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Declare import function prototype
+ *******************************************************************************/
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+#if 0 //
+/* under construction !*/
+/* under construction !*/
+#else
+extern void UART_Bootup_Init(void);
+extern void Seriport_Driver_Boot_Trace_Init(void);//want bootup trace,but VFIFO maybe not ready,so close vfifo and init uart1 driver
+#endif
+#endif /* __KAL_RECORD_BOOTUP_LOG__ || __KEYPAD_DEBUG_TRACE__ */
+
+
+#if defined(__KAL_RECORD_BOOTUP_LOG__) || defined(__KEYPAD_DEBUG_TRACE__)
+/*************************************************************************
+* FUNCTION
+* INT_setInitLogFlag
+*
+* DESCRIPTION
+* This function is used to set init flag for tst, which will use the flag to determine whether
+* the system is at init. stage or not.
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_setInitLogFlag(void)
+{
+ is_init_stage = KAL_TRUE;
+#if defined(__KAL_RECORD_BOOTUP_LOG__)
+ is_init_log_enable = KAL_TRUE;
+#else
+
+ custom_InitKeypadGPIO();
+
+ if(custom_IsBootupTraceKeyPressed())
+ {
+ is_init_log_enable = KAL_TRUE;
+ }
+ else
+ {
+ is_init_log_enable = KAL_FALSE;
+ }
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* INT_InitBootupTrace
+*
+* DESCRIPTION
+* This function is used to init bootup trace driver.
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_InitBootupTrace(void)
+{
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+ /* init uart baudrate (HW related) */
+ UART_Bootup_Init();
+ INT_setInitLogFlag();
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* INT_printBootMode
+*
+* DESCRIPTION
+* This function is used to print out current boot-up mode.
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void INT_printBootMode(void)
+{
+ kal_char buff[40];
+
+#if defined(__FACTORY_BIN__)
+ sprintf(buff, "Supported Boot mode: META only");
+#else
+
+#if defined(__SPLIT_BINARY__)
+ sprintf(buff, "Supported Boot mode: MAUI only");
+#else
+ sprintf(buff, "Supported Boot mode: ALL");
+#endif /* __SPLIT_BINARY__ */
+
+#endif /* __FACTORY_BIN__ */
+
+ kal_bootup_print(buff);
+
+ memset(buff, 0x0, sizeof(buff));
+ sprintf(buff, "Boot mode: ");
+ switch(system_boot_mode) {
+ case FACTORY_BOOT:
+ strcat(buff, "FACTORY");
+ break;
+
+ case NORMAL_BOOT:
+ strcat(buff, "NORMAL");
+ break;
+
+ case USBMS_BOOT:
+ strcat(buff, "USB");
+ break;
+
+ case FUE_BOOT:
+ strcat(buff, "FUE");
+ break;
+
+ default:
+ strcat(buff, "UNKNOWN");
+ break;
+ }
+ kal_bootup_print(buff);
+}
+#endif /* __KAL_RECORD_BOOTUP_LOG__ || __KEYPAD_DEBUG_TRACE__ */
+
+void INT_backupBootLogs(void)
+{
+//#if defined(__SP_BOOTTRC_ENABLE__)
+#if defined(__HIF_CCCI_SUPPORT__)
+ //for external smart phone, there is no share memory for back up
+ kal_uint32 log_addr = 0, log_size = 0;
+
+ if (EMM_GetBufInfo(&log_addr, &log_size, EMM_BOOTUP_TRACE)) {
+ if (log_addr && log_size) {
+ memcpy(boot_trace_log, (void*)log_addr, BOOTTRACE_BKBUF_SIZE);
+ }
+ }
+ EMM_ClearDbgInfo();
+#endif
+}
+
+#if defined(__COSIM_BYPASS_DRV__)
+/*************************************************************************
+* FUNCTION
+* MDM_ASSERT
+*
+* DESCRIPTION
+* This function created for RTL CoSim load for ASSERT support
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+void MDM_ASSERT(kal_uint32 e1, kal_uint32 e2, kal_uint32 e3)
+{
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('A');
+ MDM_STR0_WRITE('S');
+ MDM_STR0_WRITE('S');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('R');
+ MDM_STR0_WRITE('T');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('e');
+ MDM_STR0_WRITE('1');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(e1);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('e');
+ MDM_STR0_WRITE('2');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(e2);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('e');
+ MDM_STR0_WRITE('3');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(e3);
+ MDM_INT32_WRITE(ASSERT_ERROR_MAGIC);
+ MDM_TM_END_FAIL_WRITE;
+ while(1);
+}
+/*************************************************************************
+* FUNCTION
+* MDM_kal_fatal_error_handler
+*
+* DESCRIPTION
+* This function created for RTL CoSim load for fatal error handler support
+*
+* PARAMETERS
+* none
+*
+* RETURNS
+* 0
+*
+*************************************************************************/
+
+void MDM_kal_fatal_error_handler(kal_uint32 code1, kal_uint32 code2)
+{
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('F');
+ MDM_STR0_WRITE('A');
+ MDM_STR0_WRITE('T');
+ MDM_STR0_WRITE('A');
+ MDM_STR0_WRITE('L');
+ MDM_STR0_WRITE(' ');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('R');
+ MDM_STR0_WRITE('R');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('R');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('C');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('D');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('1');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(code1);
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('C');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('D');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('2');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(code2);
+ MDM_INT32_WRITE(FATAL_ERROR_MAGIC);
+ MDM_TM_END_FAIL_WRITE;
+ while(1);
+}
+
+
+void MDM_EXCEPTION(void)
+{
+ MDM_TM_STR_CLEAR_WRITE(0x0);
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('X');
+ MDM_STR0_WRITE('C');
+ MDM_STR0_WRITE('E');
+ MDM_STR0_WRITE('P');
+ MDM_STR0_WRITE('T');
+ MDM_STR0_WRITE('I');
+ MDM_STR0_WRITE('O');
+ MDM_STR0_WRITE('N');
+ MDM_TM_STR_DISPLAY_WRITE(0x0);
+ MDM_INT32_WRITE(EXCEPTION_ERROR_MAGIC);
+ MDM_TM_END_FAIL_WRITE;
+ while (1);
+}
+#endif
+
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_vpe0.S b/mcu/driver/sys_drv/init/src/md97p/init_vpe0.S
new file mode 100644
index 0000000..5f7428e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_vpe0.S
@@ -0,0 +1,132 @@
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+#define QOS_MODE (0x1)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+ .set nomips16
+/**************************************************************************************
+**************************************************************************************/
+LEAF(init_vpe0)
+
+/* Check this core has more than 1 TC, if only 1 TC than trapping */
+INT_VPEINIT_TC_CHECK:
+ mfc0 $a0, C0_MVPCONF0
+ ext $a0, $a0, 0, 8
+ bgtzc $a0, INT_VPEINIT_VPE_CHECK
+
+INT_VPEINIT_TC_CHECK_FAIL:
+ bc INT_VPEINIT_TC_CHECK_FAIL
+
+
+/* Check this core has more than 1 VPE, if only 1 VPE than trapping */
+INT_VPEINIT_VPE_CHECK:
+ mfc0 $a0, C0_MVPCONF0
+ ext $a0, $a0, 10, 4
+ bgtzc $a0, INT_VPEINIT
+
+INT_VPEINIT_VPE_CHECK_FAIL:
+ bc INT_VPEINIT_VPE_CHECK_FAIL
+
+INT_VPEINIT:
+
+ /* This is executing on TC0 bound to VPE0. Therefore VPEConf0.MVP is set. */
+
+ /* Config C0_MVPCONTROL.VPC[1]
+ * Purpose: Enter config mode */
+ mfc0 $t0, C0_MVPCONTROL
+ or $t0, (1 << 1) // set VPC[1]
+ mtc0 $t0, C0_MVPCONTROL
+ ehb
+
+INT_QOS_init:
+ /* Every Core's VPE0 do QOS initialization */
+ /*clear all core ctrl to 0..(disable IDU SPRRAM)*/
+ mtc0 $zero, $22, 3
+ ehb
+#if (QOS_MODE == 1)
+ mfc0 $t0, C0_MVPCONTROL
+ or $t0, (1 << 16) // set QOS[16]
+ mtc0 $t0, C0_MVPCONTROL
+ ehb
+#endif
+
+INT_VPEINIT_VPE0_TC0:
+
+ /* Enable multi-threading of VPE0 */
+ li $a0, 1
+ mfc0 $t0, C0_VPECONTROL // read C0_VPECONTROL
+ ins $t0, $a0, 15, 1 // set TE[15]
+ mtc0 $t0, C0_VPECONTROL // write C0_VPECONTROL
+
+ /* Set YQMask */
+ addi $t0, $zero, 0xF0F // bit 0~3 for VPE0, 8~11 for VPE1
+ mtc0 $t0, C0_YQMASK
+
+ /* Set C0_TCSCHEDULE */
+ mtc0 $zero, C0_TCSCHEDULE
+
+INT_VPEINIT_VPEn_TC1:
+
+ move $t3, $ra
+
+
+INT_VPEINIT_VPE0_TC_StackInit:
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 2, 2
+
+ li $a1, 0
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core0
+
+#if !defined(__SINGLE_CORE__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core1
+#if !defined(__MD97_IS_2CORES__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core2
+
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE0_TC_StackInit_Core3
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE0_TC_StackInit_Core0:
+ la $a2, CORE0_VPE0_TC1_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_VPEINIT_VPE0_TC_StackInit_done
+
+INT_VPEINIT_VPE0_TC_StackInit_Core1:
+ la $a2, CORE1_VPE0_TC1_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE0_TC_StackInit_done
+#if !defined(__MD97_IS_2CORES__)
+INT_VPEINIT_VPE0_TC_StackInit_Core2:
+ la $a2, CORE2_VPE0_TC1_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE0_TC_StackInit_done
+
+INT_VPEINIT_VPE0_TC_StackInit_Core3:
+ la $a2, CORE3_VPE0_TC1_SYS_STACK_PTR
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE0_TC_StackInit_done:
+
+
+ li $a0, 0x0
+ li $a1, 0x1
+// la $a2, CORE0_VPE0_TC1_SYS_STACK_PTR
+ li $a3, 0x0
+ la $t0, init_tc
+ jalrc $t0
+
+ move $ra, $t3
+ jrc $ra
+
+END(init_vpe0)
+.set pop
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_vpe1.S b/mcu/driver/sys_drv/init/src/md97p/init_vpe1.S
new file mode 100644
index 0000000..775df0e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_vpe1.S
@@ -0,0 +1,120 @@
+/*
+ * init_vpe1.S
+ *
+ * Initialize the second vpe and additional TCs
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+ .set nomips16
+/**************************************************************************************
+**************************************************************************************/
+LEAF(init_vpe1)
+// Each vpe will need to set up additional TC bound to it. (No rebinding.)
+
+INT_VPEINIT_VPE1_TC2:
+
+ move $t3, $ra
+
+ li $a0, 0x1
+ li $a1, 0x2
+ la $a2, 0xdeadbeef // no need to assign stack pointer here
+ li $a3, 0x1
+ la $t0, init_tc
+ jalrc $t0
+
+
+INT_VPEINIT_VPE1_TC_StackInit:
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 2, 2
+
+ li $a1, 0
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core0
+
+#if !defined(__SINGLE_CORE__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core1
+#if !defined(__MD97_IS_2CORES__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core2
+
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE1_TC_StackInit_Core3
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE1_TC_StackInit_Core0:
+ la $a2, CORE0_VPE1_TC3_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_VPEINIT_VPE1_TC_StackInit_done
+
+INT_VPEINIT_VPE1_TC_StackInit_Core1:
+ la $a2, CORE1_VPE1_TC3_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE1_TC_StackInit_done
+
+#if !defined(__MD97_IS_2CORES__)
+INT_VPEINIT_VPE1_TC_StackInit_Core2:
+ la $a2, CORE2_VPE1_TC3_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE1_TC_StackInit_done
+
+INT_VPEINIT_VPE1_TC_StackInit_Core3:
+ la $a2, CORE3_VPE1_TC3_SYS_STACK_PTR
+#endif/*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE1_TC_StackInit_done:
+
+
+INT_VPEINIT_VPE1_TC3:
+
+ li $a0, 0x1
+ li $a1, 0x3
+ li $a3, 0x0
+ la $t0, init_tc
+ jalrc $t0
+
+ move $ra, $t3
+ jrc $ra
+
+END(init_vpe1)
+.set pop
diff --git a/mcu/driver/sys_drv/init/src/md97p/init_vpe2.S b/mcu/driver/sys_drv/init/src/md97p/init_vpe2.S
new file mode 100644
index 0000000..57c5a45
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/init_vpe2.S
@@ -0,0 +1,122 @@
+/*
+ * init_vpe1.S
+ *
+ * Initialize the second vpe and additional TCs
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <boot.h>
+#include <mips/mt.h>
+#include <mips/m32c0.h>
+
+#define MX_FEATURE (0x0)
+
+.extern HRT_domain_C_env
+
+ .set push
+ .set noreorder // Don't allow the assembler to reorder instructions.
+// .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+// .set nomips16
+/**************************************************************************************
+**************************************************************************************/
+.section "NONCACHED_ROCODE", "ax"
+
+.globl init_vpe2
+.ent init_vpe2
+init_vpe2:
+
+
+ move $t3, $ra
+
+INT_VPEINIT_VPE2_TC4:
+ li $a0, 0x2
+ li $a1, 0x4
+ la $a2, 0xdeadbeef // no need to assign stack pointer here
+ li $a3, 0x1
+ la $t0, init_tc
+ jalrc $t0
+
+INT_VPEINIT_VPE2_TC_StackInit:
+
+ mfc0 $a0, C0_EBASE
+ ext $a0, $a0, 2, 2
+
+ li $a1, 0
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core0
+
+#if !defined(__SINGLE_CORE__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core1
+
+#if !defined(__MD97_IS_2CORES__)
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core2
+
+ addi $a1, $a1, 1
+ beqc $a0, $a1, INT_VPEINIT_VPE2_TC_StackInit_Core3
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE2_TC_StackInit_Core0:
+ la $a2, CORE0_VPE2_TC5_SYS_STACK_PTR
+#if !defined(__SINGLE_CORE__)
+ bc INT_VPEINIT_VPE2_TC_StackInit_done
+
+INT_VPEINIT_VPE2_TC_StackInit_Core1:
+ la $a2, CORE1_VPE2_TC5_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE2_TC_StackInit_done
+
+#if !defined(__MD97_IS_2CORES__)
+INT_VPEINIT_VPE2_TC_StackInit_Core2:
+ la $a2, CORE2_VPE2_TC5_SYS_STACK_PTR
+ bc INT_VPEINIT_VPE2_TC_StackInit_done
+
+INT_VPEINIT_VPE2_TC_StackInit_Core3:
+ la $a2, CORE3_VPE2_TC5_SYS_STACK_PTR
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+INT_VPEINIT_VPE2_TC_StackInit_done:
+
+INT_VPEINIT_VPE2_TC5:
+
+ li $a0, 0x2
+ li $a1, 0x5
+ li $a3, 0x0
+ la $t0, init_tc
+ jalrc $t0
+
+ move $ra, $t3
+ jrc $ra
+
+END(init_vpe2)
+.set pop
\ No newline at end of file
diff --git a/mcu/driver/sys_drv/init/src/md97p/join_domain.S b/mcu/driver/sys_drv/init/src/md97p/join_domain.S
new file mode 100644
index 0000000..13103ad
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/join_domain.S
@@ -0,0 +1,119 @@
+/*
+ * join_domain.S
+ *
+ * For CPS cores join processing domain
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <boot.h>
+#include <cps.h>
+#include <cpu_info.h>
+//#define U4G_LTEL2_3CORE
+
+.set noreorder // Don't allow the assembler to reorder instructions.
+.set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+
+/**************************************************************************************
+**************************************************************************************/
+
+.section "NONCACHED_ROCODE", "ax"
+.globl join_domain
+.ent join_domain
+join_domain:
+ li r22_gcr_addr, GCR_CONFIG_ADDR
+ li r11_is_cps, 0x1
+ beqzc r11_is_cps, done_join_domain // If this is not a CPS then we are done.
+
+ // GCR_ACCESS, [0x1F00_0020] must be enable
+ //lw $t1, 0(r22_gcr_addr)
+ //ext $t1, $t1, 0, 8
+ li $t1, SYS_MCU_NUM_CORE
+ li $t2, 4
+ beqc $t1, $t2, four_core_ver
+
+ li $t2, 3
+ beqc $t1, $t2, three_core_ver
+
+ li $t2, 2
+ beqc $t1, $t2, two_core_ver
+
+ li $t2, 1
+ beqc $t1, $t2, done_join_domain
+
+ // Enable coherence and allow interventions from all other cores.
+ // (Write access enabled via GCR_ACCESS by core 0.)
+
+four_core_ver: //if ($t1==4) || ($t1 !=1)||($t1 !=2)||($t1 !=3)) will enter this flow
+ li $a2, 0x3
+ li $a0, 0x1F // Set Coherent domain enable for 4 cores
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_COHERENCE($a1) // GCR_CL_COHERENCE
+ ehb
+ bc Set_Coherence_Domain_Done
+
+three_core_ver:
+ li $a2, 0x2
+ li $a0, 0x17 // Set Coherent domain enable for 3 cores
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_COHERENCE($a1) // GCR_CL_COHERENCE
+ ehb
+ bc Set_Coherence_Domain_Done
+
+two_core_ver:
+ li $a2, 0x1
+ li $a0, 0x13 // Set Coherent domain enable for 3 cores
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_COHERENCE($a1) // GCR_CL_COHERENCE
+ ehb
+ bc Set_Coherence_Domain_Done
+
+Set_Coherence_Domain_Done:
+
+ // Cores other than core 0 can relinquish write access to CM regs here.
+
+ move $a3, $zero
+
+next_coherent_core:
+ sll $a0, $a3, 16
+ addiu $a1, r22_gcr_addr, CORE_LOCAL_CONTROL_BLOCK
+ sw $a0, GCR_CL_OTHER($a1) // GCR_CL_OTHER[CoreNum]
+
+busy_wait_coherent_core:
+ lw $a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
+ beqzc $a0, busy_wait_coherent_core // Busy wait on cores joining.
+
+ addiu $a3, 1
+ bnec $a3, $a2, next_coherent_core
+
+done_join_domain:
+ jrc $ra
+
+END(join_domain)
diff --git a/mcu/driver/sys_drv/init/src/md97p/mdmcu_init.c b/mcu/driver/sys_drv/init/src/md97p/mdmcu_init.c
new file mode 100644
index 0000000..9fd1edd
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/mdmcu_init.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97P__)
+#include "mdmcu_init.h"
+#include "mdmcu_pmu.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+#define is_vpe0_of_each_core(__vpe_id__) (0 == ((__vpe_id__) % 2))
+
+void miu_wait(void)
+{
+ __asm__ __volatile__ ( "wait;\n");
+}
+
+// Do at INC_Initialize (every core)
+void mdmcu_init(void)
+{
+ mdmcu_pmu_init();
+}
+
+// Do at dormant_mode_activate (every core)
+void mdmcu_enter_dormant(void)
+{
+ mdmcu_pmu_enter_dormant();
+}
+
+// Do at dormant_mode_activate (every core)
+void mdmcu_leave_dormant(void)
+{
+ mdmcu_pmu_leave_dormant();
+}
+
+// Do at INC_Initialize before TCCT_Schedule, every core would do this
+void mips_ia_misc_init_by_core(void)
+{
+ //To Be Removed
+}
+
+// Do at HWDInitialization / Application_Initialize, only core0 would do this
+// Early than mips_ia_misc_init_by_core
+void mips_ia_misc_init(void)
+{
+ //To Be Removed
+}
+
+#endif /* !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97P__) */
diff --git a/mcu/driver/sys_drv/init/src/md97p/release_mp.S b/mcu/driver/sys_drv/init/src/md97p/release_mp.S
new file mode 100644
index 0000000..ae7af25
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/release_mp.S
@@ -0,0 +1,154 @@
+/*
+ * release_mp.S
+ *
+ * Release other processors so they can boot
+*/
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+#include <boot.h>
+#include <mips/regdef.h>
+#include <cps.h>
+
+#ifndef __MIPS16
+ .set noreorder // Don't allow the assembler to reorder instructions.
+ .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+/**************************************************************************************
+**************************************************************************************/
+
+//LEAF(release_mp)
+.section "NONCACHED_ROCODE", "ax"
+.globl release_mp
+.ent release_mp
+release_mp:
+
+ // Copy from set_gpr_boot_values.S due to boot register cannot be assumed as correct
+ li r22_gcr_addr, GCR_CONFIG_ADDR
+ lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
+ ext r19_more_cores, a0, PCORES, PCORES_S // Extract PCORES
+ li r30_cpc_addr, CPC_BASE_ADDR // Maintain address of CPC register block.
+
+ blez r19_more_cores, done_release_mp // If no more cores then we are done.
+ li a3, 1
+
+ beqz r30_cpc_addr, release_next_core // If no CPC then use GCR_CO_RESET_RELEASE
+ nop // else use CPC Power Up command.
+
+powerup_next_core:
+ // Send PwrUp command to next core causing execution at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(r30_cpc_addr)
+ li a0, PWR_UP // "PwrUp" power domain command.
+ sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(r30_cpc_addr)
+ bne r19_more_cores, a3, powerup_next_core
+ addiu a3, a3, 1
+
+ jalr zero, ra
+ nop
+
+release_next_core:
+ // Release next core to execute at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER
+ sw zero, 0x4000(r22_gcr_addr) // GCR_CO_RESET_RELEASE
+ bne r19_more_cores, a3, release_next_core
+ addiu a3, a3, 1
+
+done_release_mp:
+ jalr zero, ra
+ nop
+//END(release_mp)
+.end release_mp
+
+#else //__MIPS16
+
+ .set noreorder // Don't allow the assembler to reorder instructions.
+ .set noat // Don't allow the assembler to use r1(at) for synthetic instr.
+/**************************************************************************************
+**************************************************************************************/
+
+//LEAF(release_mp)
+.section "NONCACHED_ROCODE", "ax"
+
+__GCR_CONFIG_ADDR:
+ .word GCR_CONFIG_ADDR
+
+__CPC_BASE_ADDR:
+ .word CPC_BASE_ADDR
+
+.globl release_mp
+.ent release_mp
+release_mp:
+
+ // Copy from set_gpr_boot_values.S due to boot register cannot be assumed as correct
+ lw a2, __GCR_CONFIG_ADDR
+ lw a0, GCR_CONFIG(a2) // Load GCR_CONFIG
+ ext a1, a0, PCORES, PCORES_S // Extract PCORES
+ lw s0, __CPC_BASE_ADDR // Maintain address of CPC register block.
+
+ beqz a1, done_release_mp // If no more cores then we are done.
+ li a3, 1
+ addiu a1, 1
+
+ li s1, 0
+ beqz s0, release_next_core // If no CPC then use GCR_CO_RESET_RELEASE
+ // else use CPC Power Up command.
+
+powerup_next_core:
+ // Send PwrUp command to next core causing execution at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(s0)
+ li a0, PWR_UP // "PwrUp" power domain command.
+ sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(s0)
+ addiu a3, 1
+ bne a1, a3, powerup_next_core
+
+ jr ra
+ nop
+
+release_next_core:
+ // Release next core to execute at their reset exception vector.
+ move a0, a3
+ sll a0, 16
+ sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(a2) // GCR_CL_OTHER
+ sw s1, 0x4000(a2) // GCR_CO_RESET_RELEASE
+ addiu a3, 1
+ bne a1, a3, release_next_core
+
+done_release_mp:
+ jr ra
+ nop
+//END(release_mp)
+.end release_mp
+#endif
diff --git a/mcu/driver/sys_drv/init/src/md97p/stack_init.S b/mcu/driver/sys_drv/init/src/md97p/stack_init.S
new file mode 100644
index 0000000..0bdf54e
--- /dev/null
+++ b/mcu/driver/sys_drv/init/src/md97p/stack_init.S
@@ -0,0 +1,280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bootarm_gcc.S
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the boot sequence of asm level.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+/*************************************************************************/
+/* */
+/* Copyright (c) 1994 -2000 Accelerated Technology, Inc. */
+/* */
+/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
+/* subject matter of this material. All manufacturing, reproduction, */
+/* use, and sales rights pertaining to this subject matter are governed */
+/* by the license agreement. The recipient of this software implicitly */
+/* accepts the terms of the license. */
+/* */
+/*************************************************************************/
+
+/*************************************************************************/
+/* */
+/* FILE NAME VERSION */
+/* */
+/* bootarm_gcc.s MIPS interAptiv */
+/* */
+/* COMPONENT */
+/* */
+/* IN - Initialization */
+/* */
+/* DESCRIPTION */
+/* */
+/* This file contains the target processor dependent initialization */
+/* routines and data. */
+/* */
+/* */
+/* DATA STRUCTURES */
+/* */
+/* INT_Vectors Interrupt vector table */
+/* */
+/* FUNCTIONS */
+/* */
+/* INT_Initialize Target initialization */
+/* */
+/* */
+/*************************************************************************/
+#include <boot_comm.h>
+#include <cpu_info.h>
+
+#define STACK_ALIGN_NUM (5)
+//.data
+
+#if !defined(__SINGLE_CORE__)
+#define BOOT_TOTAL_STACK_SIZE (BOOT_SYS_STACK_SIZE * SYS_MCU_NUM_CORE * 4)
+#else
+#define BOOT_TOTAL_STACK_SIZE (BOOT_SYS_STACK_SIZE * 3)
+#endif
+//.data
+
+.section "MCURW_HWRO_DNC_NOINIT", "aw", @progbits
+.align STACK_ALIGN_NUM
+.global BOOT_SYS_Stack_Pool
+BOOT_SYS_Stack_Pool:
+ .space BOOT_TOTAL_STACK_SIZE//-8
+ .size BOOT_SYS_Stack_Pool, .-BOOT_SYS_Stack_Pool
+
+
+/******************************************************************************/
+
+.macro gen_stack name, size, section, file, line
+.section \section, "aw", @progbits
+.align STACK_ALIGN_NUM
+.global \name
+.loc \file \line
+\name:
+ .ascii "STACKEND"
+ .space \size - 8
+ .type \name, @object
+ .size \name, . - \name
+.endm
+
+#define SYS_STACK_INSTANCE_BEGIN() \
+ /* WARNING: this will be add to dep file by cpp but not check in cpp */ \
+ .file 1 __FILE__; \
+ .loc 1 __LINE__;
+
+#define SYS_STACK_INSTANCE(CORE,VPE,TC,SIZE,SECTION,TYPE) \
+ gen_stack SYS_STACK_NAME(CORE,VPE,TC), SIZE, #SECTION, 1, __LINE__
+
+#include "sys_stack_config.h"
+
+/******************************************************************************/
+