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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/driver/sys_drv/init/inc/config_hw.h b/mcu/driver/sys_drv/init/inc/config_hw.h
new file mode 100644
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+++ b/mcu/driver/sys_drv/init/inc/config_hw.h
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+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * config_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Definition for CONFIG hardware registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CONFIG_HW_H__
+#define __CONFIG_HW_H__
+
+#include "reg_base.h"
+
+/*******************************************************************************
+ * Version
+ *******************************************************************************/
+#define HW_VER ((volatile UINT16P)(MD_CONFIG_base+0x0000))
+#define FW_VER ((volatile UINT16P)(MD_CONFIG_base+0x0004))
+#define SW_VER FW_VER
+#define HW_CODE ((volatile UINT16P)(MD_CONFIG_base+0x0008))
+#define HW_SUBCODE ((volatile UINT16P)(MD_CONFIG_base+0x000C))
+
+/*******************************************************************************
+ * System special register
+ *******************************************************************************/
+#define SW_MISC_L ((volatile UINT32P)(MD_CONFIG_base+0x10))
+#define SW_MISC_H ((volatile UINT32P)(MD_CONFIG_base+0x14))
+
+/* boot mode control register */
+/* New chip will have SW_MISC_L, plesae do not specify specific address */
+#define BOOT_CONFIG_ADDR SW_MISC_L
+#define BOOT_SLAVE_ADDR_PTR ((volatile UINT32P)0xFFFF0020)
+
+#endif /* !__CONFIG_HW_H__ */
+
diff --git a/mcu/driver/sys_drv/init/inc/cps.h b/mcu/driver/sys_drv/init/inc/cps.h
new file mode 100644
index 0000000..c0d5d1a
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/cps.h
@@ -0,0 +1,881 @@
+/*
+ * cps.h
+ *
+ */
+/*
+Copyright (c) 2015, Imagination Technologies Limited and/or its affiliated group companies
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific prior
+written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+/*
+ * This include file contains #defines for the memory mapped registers in a coherent Processing system
+ * of both single cores and multi threaded cores. It contains registers offset for all the registers,
+ * defines for the fields with in the registers and encodings for some of the fields.
+ *
+ * The fields in the registers are defined by a pair of #defines, one define is the starting bit position of
+ * the field and another, (with a "_S" appended to the name), is the size of the field. Here is an example of
+ * how you would use these #defines in the the extraction of a filed:
+ *
+ * li $5, GIC_BASE_ADDR # load GIC KSEG0 Address
+ * lw $4, GIC_SH_CONFIG($5) # Read the GIC_SH_CONFIG Register
+ * ext $4, NUMINTERRUPTS, NUMINTERRUPTS_S # Extract NUMINTERRUPTS
+ *
+ * The names for the registers and fields are usually the same as used in the Software Users Manual
+ * (SUM). The exceptions occur when the names would conflict with each other in that case the name
+ * is appended with something to make it unique.
+ */
+
+#ifndef CPS_H_
+#define CPS_H_
+
+// GCR Offset for GCR_CONFIG, field positions and field size
+#define GCR_CONFIG 0x0000
+#define NUM_ADDR_REGIONS 16
+#define NUM_ADDR_REGIONS_S 4
+#define NUMIOCU 8
+#define NUMIOCU_S 4
+#define PCORES 0
+#define PCORES_S 8
+#define PCORE_MASK 0x000000ff
+#define NUMIOCU_MASK 0x00000f00
+#define NUM_ADDR_REGIONS_MASK 0x000f0000
+
+
+// GCR Offset for GCR_BASE, field positions and field size
+#define GCR_BASE 0x0008
+#define GCR_BASE_ADDR 15
+#define GCR_BASE_ADDR_S 17
+#define CCA_DEFAULT_OVERRIDE_VALUE 5
+#define CCA_DEFAULT_OVERRIDE_VALUE_S 3
+#define CCA_DEFAULT_OVERRIDE_ENABLE 4
+#define CCA_DEFAULT_OVERRIDE_ENABLE_S 1
+#define CM_DEFAULT_TARGET 0
+#define CM_DEFAULT_TARGET_S 2
+
+// GCR Offset for GCR_CONTROL, field positions and field size
+#define GCR_CONTROL 0x0010
+#define SYNCCTL 16
+#define SYNCCTL_S 1
+#define CM_SYNC_TX_DISABLE 5
+#define CM_SYNC_TX_DISABLE_S 1
+#define CM_AUTO_CLR_IVU_EN 4
+#define CM_AUTO_CLR_IVU_EN_S 1
+#define CM_COHST_SH_ALWAYS_EN 3
+#define CM_COHST_SH_ALWAYS_EN_S 1
+#define CM_PARK_EN 2
+#define CM_PARK_EN_S 1
+#define CM_DISABLE_MMIO_LIMIT 1
+#define CM_DISABLE_MMIO_LIMIT_S 1
+#define CM_SPEC_READ_EN 0
+#define CM_SPEC_READ_EN_S 1
+
+// GCR Offset for GCR_CONTROL_2, field positions and field size
+#define GCR_CONTROL2 0x0018
+#define L2_CACHEOP_LIMIT 16
+#define L2_CACHEOP_LIMIT_S 4
+#define L1_CACHEOP_LIMIT 3
+#define L1_CACHEOP_LIMIT_S 4
+
+// GCR Offset for GCR_ACCESS, field positions and field size
+#define GCR_ACCESS 0x0020
+#define CM_ACCESS_EN 0
+#define CM_ACCESS_EN_S 8
+
+// GCR Offset for GCR_REV, field positions and field size
+#define GCR_REV 0x0030
+#define MAJOR_REV_GCR 8
+#define MAJOR_REV_GCR_S 8
+#define MINOR_REV_GCR 7
+#define MINOR_REV_GCR_S 8
+
+// GCR Offset for GCR_ERROR_MASK
+#define GCR_ERROR_MASK 0x0040
+
+// error type encoding
+#define GC_WR_ERR 1
+#define GC_RD_ERR 2
+#define COH_WR_ERR 3
+#define COH_RD_ERR 4
+#define MMIO_WR_ERR 5
+#define MMIO_RD_ERR 6
+#define INTVN_WR_ERR 17
+#define INTVN_RD_ERR 18
+
+// GCR Offset for GCR_ERROR_CAUSE, field positions and field size
+#define GCR_ERROR_CAUSE 0x0048
+#define CM_ERROR_TYPE 27
+#define CM_ERROR_TYPE_S 5
+#define CM_ERROR_INFO 0
+#define CM_ERROR_INFO_S 27
+
+// Fields and sizes for Error Types 1 - 5
+#define CCA 15
+#define CCA_S 3
+#define TARGET_REGION 12
+#define TARGET_REGION_S 3
+#define OCP_MCMD_ERROR 7
+#define OCP MCMD_ERROR_S 5
+#define SOURCE_TAGID 3
+#define SOURCE_TAGID_S 4
+#define SOURCE_PORT 0
+#define SOURCE_PORT_S 3
+
+// Fields for Error Types 16 - 17
+#define COHERENT_STATE_CORE_3 19
+#define COHERENT_STATE_CORE_3_S 2
+#define INTERVENTION_SRESP_CORE3 18
+#define INTERVENTION_SRESP_CORE3_S 1
+
+#define COHERENT_STATE_CORE_2 16
+#define COHERENT_STATE_CORE_2_S 2
+#define INTERVENTION_SRESP_CORE2 15
+#define INTERVENTION_SRESP_CORE2_S 1
+
+#define COHERENT_STATE_CORE_1 13
+#define COHERENT_STATE_CORE_1_S 2
+#define INTERVENTION_SRESP_CORE1 12
+#define INTERVENTION_SRESP_CORE1_S 1
+
+#define COHERENT_STATE_CORE_0 10
+#define COHERENT_STATE_CORE_0_S 2
+#define INTERVENTION_SRESP_CORE0 9
+#define INTERVENTION_SRESP_CORE0_S 1
+
+#define FROM_STORE_CONDITIONAL 8
+#define FROM_STORE_CONDITIONAL_S 1
+#define OCP_MCMD 3
+#define OCP_MCMD_S 5
+#define SOURCE_PORT 0
+#define SOURCE_PORT_S 3
+
+// Coherent state encoding
+#define CS_INVALID 0
+#define CS_SHARED 1
+#define CS_MODIFID 2
+#define CS_EXCLUSIVE
+
+// Intervention Response encoding
+#define IR_OK 0
+#define IR_DATA 1
+
+// MCmd Encodings for CM_ERROR_INFO
+#define LEGACY_WRITE 0x01
+#define LEGACY_READ 0x02
+#define COHERENT_READ_OWN 0x08
+#define COHERENT_READ_SHARE 0x09
+#define COHERENT_READ_DISCARD 0x0A
+#define COHERENT_READ_SHARE_ALWAYS 0x0B
+#define COHERENT_UPGRADE 0x0C
+#define COHERENT_WRITEBACK 0x0D
+#define COHERENT_COPYBACK 0x10
+#define COHERENT_COPYBACK_INVALIADATE 0x11
+#define COHERENT_INVALIADATE 0x12
+#define COHERENT_WRITE_INVALIADATE 0x13
+#define COHERENT_COMPLETION_SYNC 0x14
+
+// GCR Offset for GCR_ERROR_ADDR
+#define GCR_ERROR_ADDR 0x0050
+
+// GCR Offset for GCR_ERROR_MULT
+#define GCR_ERROR_MULT 0x0058
+#define CM_ERROR_2ND 0
+#define CM_ERROR_2ND_S 5
+
+// GCR Offset for GCR_GIC_BASE, fields and sizes
+#define GCR_GIC_BASE 0x0080
+#define GIC_BASEADDRESS 17
+#define GIC_BASEADDRESS_S 15
+#define GIC_EN 0
+#define GIC_EN_S 1
+
+// GCR Offset for GCR_CPC_BAS, fields and sizes
+#define GCR_CPC_BASE 0x0088
+#define CPC_BASEADDRESS 15
+#define CPC_BASEADDRESS_S 17
+#define CPC_EN 0
+#define CPC_EN_S 1
+
+// GCR Offset for GCR_REGn_BASE, fields and sizes
+#define GCR_REG0_BASE 0x0090
+#define GCR_REG1_BASE 0x00A0
+#define GCR_REG2_BASE 0x00B0
+#define GCR_REG3_BASE 0x00C0
+#define GCR_REG4_BASE 0x0190
+#define GCR_REG5_BASE 0x01A0
+#define GCR_REG6_BASE 0x0210
+#define GCR_REG7_BASE 0x0220
+
+#define CM_REGION_BASEADDRESS 16
+#define CM_REGION_BASEADDRESS_S 16
+
+// GCR Offset for GCR_REGn_MASK, fields, sizes and encodings
+#define GCR_REG0_MASK 0x0098
+#define GCR_REG1_MASK 0x00A8
+#define GCR_REG2_MASK 0x00B8
+#define GCR_REG3_MASK 0x00C8
+#define GCR_REG4_MASK 0x0198
+#define GCR_REG5_MASK 0x01A8
+#define GCR_REG6_MASK 0x0218
+#define GCR_REG7_MASK 0x0228
+
+#define CM_REGION_ADDRESS_MASK 16
+#define CM_REGION_ADDRESS_MASK_S 16
+#define CCA_OVERRIDE_VALUE 5
+#define CCA_OVERRIDE_VALUE_S 3
+#define CCA_OVERRIDE_ENABLE 4
+#define CCA_OVERRIDE_ENABLE_S 1
+#define CM_REGION_TARGET 0
+#define CM_REGION_TARGET_S 2
+// CM_REGION_TARGET encoding
+#define CM_REGION_TARGET_DISABLE 0x0
+#define CM_REGION_TARGET_MEMORY 0x1
+#define CM_REGION_TARGET_IOCU 0x2
+
+// GCR Offset for GCR_GIC_STATUS, fields and sizes
+#define GCR_GIC_STATUS 0x00D0
+#define GIC_EX 0
+#define GIC_EX_S 1
+
+// GCR Offset for GCR_CACHE_REV, fields and sizes
+#define GCR_CACHE_REV 0x00E0
+#define MAJOR_REV_CACHE 8
+#define MAJOR_REV_CACHE_S 8
+#define MINOR_REV_CACHE 7
+#define MINOR_REV_CACHE_S 8
+
+// GCR Offset for GCR_CPC_STATUS, fields and sizes
+#define GCR_CPC_STATUS 0x00F0
+#define CPC_EX 0
+#define CPC_EX_S 1
+
+// GCR Offset for GCR_IOCU1_REV, fields and sizes
+#define GCR_IOCU1_REV 0x0200
+#define MAJOR_REV_IOCU 8
+#define MAJOR_REV_IOCU_S 8
+#define MINOR_REV_IOCU 7
+#define MINOR_REV_IOCU_S 8
+
+// GCR Core Local and Core other offsets
+#define CORE_LOCAL_CONTROL_BLOCK 0x2000
+#define CORE_OTHER_CONTROL_BLOCK 0x4000
+
+// GCR Core Local and Other COHERENCE, fields and sizes
+#define GCR_CL_COHERENCE 0x0008
+#define GCR_CO_COHERENCE 0x0008
+#define COH_DOMAIN_EN 0
+#define COH_DOMAIN_EN_S 8
+
+// GCR Core Local and Other CONFIG , fields and sizes
+#define GCR_CL_CONFIG 0x0010
+#define GCR_CO_CONFIG 0x0010
+#define IOCU_TYPE 10
+#define IOCU_TYPE_S 2
+#define PVPE 0
+#define PVPE_S 10
+
+// GCR Core Local and Other OTHER, fields and sizes
+#define GCR_CL_OTHER 0x0018
+#define GCR_CO_OTHER 0x0018
+#define OTHER_CORE_NUM 16
+#define OTHER_CORE_NUM_S 16
+
+// GCR Core Local and Other RESET_BASE, fields and sizes
+#define GCR_CL_RESET_BASE 0x0020
+#define GCR_CO_RESET_BASE 0x0020
+#define BEV_EXCEPTION_BASE 12
+#define BEV_EXCEPTION_BASE_S 20
+
+// GCR Core Local and Other ID
+#define GCR_CL_ID 0x0028
+#define GCR_CO_ID 0x0028
+
+// GCR Global Debug Block Offsets
+#define Global_Debug_Block 0x6000
+
+// GCR Global Debug GCR_DB_TCBCONTROLB, fields and sizes
+#define GCR_DB_TCBCONTROLB 0x0008
+#define WE_DB_TCBCONTROLB 31
+#define WE_DB_TCBCONTROLB_S 1
+#define TWSRC_WIDTH 26
+#define TWSRC_WIDTH_S 2
+#define TRPAD 18
+#define TRPAD_S 1
+#define RM 16
+#define RM_S 1
+#define TR 15
+#define TR_S 1
+#define BF 14
+#define BF_S 1
+#define TM 12
+#define TM_S 2
+#define CR 8
+#define CR_S 3
+#define CAL 7
+#define CAL_S 1
+#define OFC 1
+#define OFC_S 1
+#define FUNNEL_TRACE_ENABLE 0
+#define FUNNEL_TRACE_ENABLE_S 1
+
+// GCR Global Debug GCR_DB_TCBCONTROLD, fields and sizes
+#define GCR_DB_TCBCONTROLD 0x0010
+#define P4_CTL 24
+#define P4_CTL_S 2
+#define P3_CTL 22
+#define P3_CTL_S 2
+#define P2_CTL 20
+#define P2_CTL_S 2
+#define P1_CTL 18
+#define P1_CTL_S 2
+#define P0_CTL 16
+#define P0_CTL_S 2
+#define TW_SRC_VAL 8
+#define TW_SRC_VAL_S 3
+#define TRACE_WB 7
+#define TRACE_WB_S 1
+#define CM_INHIBIT_OVERFLOW 5
+#define CM_INHIBIT_OVERFLOW_S 1
+#define TLEV 3
+#define TLEV_S 2
+#define AE_PER_PORT 2
+#define AE_PER_PORT_S 1
+#define GLOBAL_CM_EN 1
+#define GLOBAL_CM_EN_S 1
+#define CM_EN 0
+#define CM_EN_S 1
+
+// GCR Global Debug GCR_DB_TCBCONTROLE, fields and sizes
+#define GCR_DB_TCBCONTROLE 0x0020
+#define TrIdle 8
+#define TrIdle_S 1
+#define PeC 0
+#define PeC_S 1
+
+// GCR Global Debug GCR_DB_TCBConfig, fields and sizes
+#define GCR_DB_TCBCONFIG 0x0028
+#define CF1 31
+#define CF1_S 1
+#define SZ 17
+#define SZ_S 4
+#define CRMAX 14
+#define CRMAX_S 3
+#define CRMIN 11
+#define CRMIN_S 3
+#define PW 9
+#define PW_S 2
+#define ONT 5
+#define ONT_S 1
+#define OFT 4
+#define OFT_S 1
+#define TCB_REV 0
+#define TCB_REV_S 4
+
+// GCR Global Debug GCR_DB_PC_CTL, fields and sizes
+#define GCR_DB_PC_CTL 0x0100
+#define PERF_INT_EN 30
+#define PERF_INT_EN_S 1
+#define PERF_OVF_STOP 29
+#define PERF_OVF_STOP_S 1
+#define P1_RESET 9
+#define P1_RESET_S 1
+#define P1_COUNT_ON 8
+#define P1_COUNT_ON_S 1
+#define P0_RESET 7
+#define P0_RESET_S 1
+#define P0_COUNT_ON 6
+#define P0_COUNT_ON_S 1
+#define CYCL_CNT_RESET 5
+#define CYCL_CNT_RESET_S 1
+#define CYCL_CNT__ON 4
+#define CYCL_CNT__ON_S 1
+#define PERF_NUM_CNT 0
+#define PERF_NUM_CNT_S 4
+
+// GCR Global Debug Read Pointer GCR_DB_TCBRDP
+#define GCR_DB_TCBRDP 0x0108
+
+// GCR Global Debug Write Pointer GCR_DB_TCBWDP
+#define GCR_DB_TCBWRP 0x0110
+
+// GCR Global Debug Start Pointer GCR_DB_TCBSTP
+#define GCR_DB_TCBSTP 0x0118
+
+// GCR_DB_PC_OV, fields and sizes
+#define GCR_DB_PC_OV 0x0120
+#define P1_OVERFLOW 2
+#define P1_OVERFLOW_S 1
+#define P0_OVERFLOW 1
+#define P0_OVERFLOW_S 1_S 1
+#define CYCL_CNT_OVERFLOW 0
+#define CYCL_CNT_OVERFLOW_S 1
+
+// GCR Global Debug GCR_DB_PC_EVENT, fields and sizes
+#define GCR_DB_PC_EVENT 0x0130
+#define P1_EVENT 8
+#define P1_EVENT_S 8
+#define P0_EVENT 0
+#define P0_EVENT_S 8
+
+// GCR Global Debug GCR_DB_PC_CYCLE
+#define GCR_DB_PC_CYCLE 0x0180
+
+
+// GCR Global Debug Qualifier and count registers
+#define GCR_DB_PC_QUAL0 0x0190
+#define GCR_DB_PC_CNT0 0x0198
+#define GCR_DB_PC_QUAL1 0x01a0
+#define GCR_DB_PC_CNT1 0x01a8
+
+// GCR Global Debug Trace word access registers
+#define GCR_DB_TCBTW_LO 0x0200
+#define GCR_DB_TCBTW_HI 0x0208
+
+// GIC Offsets within the Global interrupt controller
+
+#define GIC_SH_CONFIG 0x0000
+#define COUNTSTOP 28
+#define COUNTSTOP_S 1
+#define COUNTBITS 24
+#define COUNTBITS_S 4
+#define NUMINTERRUPTS 16
+#define NUMINTERRUPTS_S 8
+#define PVPES 0
+#define PVPES_S 9
+
+#define GIC_SH_CounterLo 0x0010
+#define GIC_SH_CounterHi 0x0014
+
+#define GIC_RevisionID 0x0020
+
+#define GIC_SH_POL31_0 0x0100
+#define GIC_SH_POL63_32 0x0104
+#define GIC_SH_POL95_64 0x0108
+#define GIC_SH_POL127_96 0x010c
+#define GIC_SH_POL159_128 0x0110
+#define GIC_SH_POL191_160 0x0114
+#define GIC_SH_POL223_192 0x0118
+#define GIC_SH_POL255_224 0x011c
+
+#define GIC_SH_TRIG31_0 0x0180
+#define GIC_SH_TRIG63_32 0x0184
+#define GIC_SH_TRIG95_64 0x0188
+#define GIC_SH_TRIG127_96 0x018c
+#define GIC_SH_TRIG159_128 0x0190
+#define GIC_SH_TRIG191_160 0x0194
+#define GIC_SH_TRIG223_192 0x0198
+#define GIC_SH_TRIG255_224 0x019c
+
+#define GIC_SH_DUAL31_0 0x0200
+#define GIC_SH_DUAL63_32 0x0204
+#define GIC_SH_DUAL95_64 0x0208
+#define GIC_SH_DUAL127_96 0x020c
+#define GIC_SH_DUAL159_128 0x0210
+#define GIC_SH_DUAL159_128 0x0210
+#define GIC_SH_DUAL191_160 0x0214
+#define GIC_SH_DUAL223_192 0x0218
+#define GIC_SH_DUAL255_224 0x021c
+
+#define GIC_SH_WEDGE 0x0280
+
+#define GIC_SH_RMASK31_0 0x0300
+#define GIC_SH_RMASK63_32 0x0304
+#define GIC_SH_RMASK95_64 0x0308
+#define GIC_SH_RMASK127_96 0x030c
+#define GIC_SH_RMASK159_128 0x0310
+#define GIC_SH_RMASK191_160 0x0314
+#define GIC_SH_RMASK223_192 0x0318
+#define GIC_SH_RMASK255_224 0x031c
+
+#define GIC_SH_SMASK31_00 0x0380
+#define GIC_SH_SMASK63_32 0x0384
+#define GIC_SH_SMASK95_64 0x0388
+#define GIC_SH_SMASK127_96 0x038c
+#define GIC_SH_SMASK159_128 0x0390
+#define GIC_SH_SMASK191_160 0x0394
+#define GIC_SH_SMASK223_192 0x0398
+#define GIC_SH_SMASK255_224 0x039c
+
+#define GIC_SH_MASK31_00 0x0400
+#define GIC_SH_MASK63_32 0x0404
+#define GIC_SH_MASK95_64 0x0408
+#define GIC_SH_MASK127_96 0x040c
+#define GIC_SH_MASK159_128 0x0410
+#define GIC_SH_MASK191_160 0x0414
+#define GIC_SH_MASK223_192 0x0418
+#define GIC_SH_MASK255_224 0x041c
+
+#define GIC_SH_PEND31_00 0x0480
+#define GIC_SH_PEND63_32 0x0484
+#define GIC_SH_PEND95_64 0x0488
+#define GIC_SH_PEND127_96 0x048c
+#define GIC_SH_PEND159_128 0x0490
+#define GIC_SH_PEND191_160 0x0494
+#define GIC_SH_PEND223_192 0x0498
+#define GIC_SH_PEND255_224 0x049c
+
+// Global MAP to Pin GIC_SH_MAP_PIN + (4 x interrupt_source)
+#define GIC_SH_MAP_PIN 0x0500
+
+#define GIC_SH_MAP_SPACER 0x20
+// Map source to VPEs 31 - 0 GIC_SH_MAP0_VPE31_0 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_VPE31_0 0x2000
+// Map source to VPEs 63 - 32 GIC_SH_MAP0_VPE63_32 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_VPE63_32 0x2004
+
+// Map source to core 31 - 0 GIC_SH_MAP0_CORE31_0 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_CORE31_0 0x2000
+// Map source to core 63 - 32 GIC_SH_MAP0_CORE63_32 + (0x20 x interrupt source)
+#define GIC_SH_MAP0_CORE63_32 0x2004
+
+#define GIC_VB_DINT_SEND 0x6000
+
+// GIC VPE Local offsets (note the VPEL)
+#define GIC_VPE_LOCAL_SECTION_OFFSET 0x8000
+
+#define GIC_VPEL_CTL 0x0000
+#define GIC_VPEL_PEND 0x0004
+#define GIC_VPEL_MASK 0x0008
+#define GIC_VPEL_RMASK 0x000c
+#define GIC_VPEL_SMASK 0x0010
+#define GIC_VPEL_WD_MAP 0x0040
+#define GIC_VPEL_COMPARE_MAP 0x0044
+#define GIC_VPEL_TIMER_MAP (0x0048 )
+#define GIC_VPEL_FDC_MAP 0x004c
+#define GIC_VPEL_PERFCTR_MAP 0x0050
+#define GIC_VPEL_SWInt0_MAP 0x0054
+#define GIC_VPEL_SWInt1_MAP 0x0058
+#define GIC_VPEL_OTHER_ADDR 0x0080
+#define GIC_VPEL_IDENT 0x0088
+#define GIC_VPEL_WD_CONFIG0 0x0090
+#define GIC_VPEL_WD_COUNT0 0x0094
+#define GIC_VPEL_WD_INITIAL0 0x0098
+#define GIC_VPEL_CompareLo 0x00A0
+#define GIC_VPEL_CompareHi 0x00A4
+
+// NOTE: EIC Shadow set GIC_VPEL_EICSS + (4 x interrupt number)
+#define GIC_VPEL_EICSS 0x0100
+#define GIC_VL_DINT_PART 0x3000
+#define GIC_VL_BRK_GROUP 0x3080
+
+// GIC VPE Other offsets (note the VPEO)
+#define GIC_VPE_OTHER_SECTION_OFFSET 0xc000
+
+#define GIC_VPEO_CTL 0x0000
+#define GIC_VPEO_PEND 0x0004
+#define GIC_VPEO_MASK 0x0008
+#define GIC_VPEO_RMASK 0x000c
+#define GIC_VPEO_SMASK 0x0010
+#define GIC_VPEO_WD_MAP 0x0040
+#define GIC_VPEO_COMPARE_MAP 0x0044
+#define GIC_VPEO_TIMER_MAP 0x0048
+#define GIC_VPEO_FDC_MAP 0x004c
+#define GIC_VPEO_PERFCTR_MAP 0x0050
+#define GIC_VPEO_SWInt0_MAP 0x0054
+#define GIC_VPEO_SWInt1_MAP 0x0058
+#define GIC_VPEO_OTHER_ADDR 0x0080
+#define GIC_VPEO_IDENT 0x0088
+#define GIC_VPEO_WD_CONFIG0 0x0090
+#define GIC_VPEO_WD_COUNT0 0x0094
+#define GIC_VPEO_WD_INITIAL0 0x0098
+#define GIC_VPEO_CompareLo 0x00A0
+#define GIC_VPEO_CompareHi 0x00A4
+
+// NOTE: EIC Shadow set GIC_VPEO_EICSS + (4 x interrupt number)
+#define GIC_VPEO_EICSS 0x0100
+#define GIC_VO_DINT_PART 0x3000
+#define GIC_VO_BRK_GROUP 0x3080
+
+// GIC CORE Local offsets (note the COREL)
+#define GIC_CORE_LOCAL_SECTION_OFFSET 0x8000
+
+#define GIC_COREL_CTL 0x0000
+#define GIC_COREL_PEND 0x0004
+#define GIC_COREL_MASK 0x0008
+#define GIC_COREL_RMASK 0x000c
+#define GIC_COREL_SMASK 0x0010
+#define GIC_COREL_WD_MAP 0x0040
+#define GIC_COREL_COMPARE_MAP 0x0044
+#define GIC_COREL_TIMER_MAP 0x0048
+#define GIC_COREL_FDC_MAP 0x004c
+#define GIC_COREL_PERFCTR_MAP 0x0050
+#define GIC_COREL_SWInt0_MAP 0x0054
+#define GIC_COREL_SWInt1_MAP 0x0058
+#define GIC_COREL_OTHER_ADDR 0x0080
+#define GIC_COREL_IDENT 0x0088
+#define GIC_COREL_WD_CONFIG0 0x0090
+#define GIC_COREL_WD_COUNT0 0x0094
+#define GIC_COREL_WD_INITIAL0 0x0098
+#define GIC_COREL_CompareLo 0x00A0
+#define GIC_COREL_CompareHi 0x00A4
+// NOTE: EIC Shadow set GIC_COREL_EICSS + (4 x interrupt number)
+#define GIC_COREL_EICSS 0x0100
+#define GIC_COREL_DINT_PART 0x3000
+#define GIC_COREL_BRK_GROUP 0x3080
+
+// GIC CORE Other offsets (note the COREO)
+#define GIC_CORE_OTHER_SECTION_OFFSET 0xc000
+#define GIC_COREO_CTL 0x0000
+#define GIC_COREO_PEND 0x0004
+#define GIC_COREO_MASK 0x0008
+#define GIC_COREO_RMASK 0x000c
+#define GIC_COREO_SMASK 0x0010
+#define GIC_COREO_WD_MAP 0x0040
+#define GIC_COREO_COMPARE_MAP 0x0044
+#define GIC_COREO_TIMER_MAP 0x0048
+#define GIC_COREO_FDC_MAP 0x004c
+#define GIC_COREO_PERFCTR_MAP 0x0050
+#define GIC_COREO_SWInt0_MAP 0x0054
+#define GIC_COREO_SWInt1_MAP 0x0058
+#define GIC_COREO_OTHER_ADDR 0x0080
+#define GIC_COREO_IDENT 0x0088
+#define GIC_COREO_WD_CONFIG0 0x0090
+#define GIC_COREO_WD_COUNT0 0x0094
+#define GIC_COREO_WD_INITIAL0 0x0098
+#define GIC_COREO_CompareLo 0x00A0
+#define GIC_COREO_CompareHi 0x00A4
+// NOTE: EIC Shadow set GIC_COREO_EICSS + (4 x interrupt number)
+#define GIC_COREO_EICSS 0x0100
+#define GIC_COREO_DINT_PART 0x3000
+#define GIC_COREO_BRK_GROUP 0x3080
+
+
+// Bit fields for Local Interrupt Control Register (GIC_COREi_CTL) or for MT (GIC_VPEi_CTL) or
+#define FDC_ROUTABLE 4
+#define FDC_ROUTABLE_S 1
+#define SWINT_ROUTABLE 3
+#define SWINT_ROUTABLE_S 1
+#define PERFCOUNT_ROUTABLE 2
+#define PERFCOUNT_ROUTABLE_S 1
+#define TIMER_ROUTABLE 1
+#define TIMER_ROUTABLE_S 1
+#define EIC_MODE 0
+#define EIC_MODE_S 1
+
+// Bit fields for Local Interrupt Pending Registers (GIC_COREi_PEND) or for MT (GIC_VPEi_PEND)
+#define FDC_PEND 6
+#define FDC_PEND_S 1
+#define SWINT1_PEND 5
+#define SWINT1_PEND_S 1
+#define SWINT0_PEND 4
+#define SWINT0_PEND_S 1
+#define PERFCOUNT_PEND 3
+#define PERFCOUNT_PEND_S 1
+#define TIMER_PEND 2
+#define TIMER_PEND_S 1
+#define COMPARE_PEND 1
+#define COMPARE_PEND_S 1
+#define WD_PEND 0
+#define WD_PEND_S 1
+
+// Bit fields for Local Interrupt Mask Registers (GIC_COREi_MASK) or for MT (GIC_VPEi_MASK)
+#define FDC_MASK 6
+#define FDC_MASK_S 1
+#define SWINT1_MASK 5
+#define SWINT1_MASK_S 1
+#define SWINT0_MASK 4
+#define SWINT0_MASK_S 1
+#define PERFCOUNT_MASK 3
+#define PERFCOUNT_MASK_S 1
+#define TIMER_MASK 2
+#define TIMER_MASK_S 1
+#define COMPARE_MASK 1
+#define COMPARE_MASK_S 1
+#define WD_MASK 0
+#define WD_MASK_S 1
+
+// Bit fields for Local Interrupt Reset Mask Registers (GIC_COREi_RMASK) or for MT (GIC_VPEi_RMASK)
+#define FDC_MASK_RESET 6
+#define FDC_MASK_RESET_S 1
+#define SWINT1_MASK_RESET 5
+#define SWINT1_MASK_RESET_S 1
+#define SWINT0_MASK_RESET 4
+#define SWINT0_MASK_RESET_S 1
+#define PERFCOUNT_MASK_RESET 3
+#define PERFCOUNT_MASK_RESET_S 1
+#define TIMER_MASK_RESET 2
+#define TIMER_MASK_RESET_S 1
+#define COMPARE_MASK_RESET 1
+#define COMPARE_MASK_RESET_S 1
+#define WD_MASK_RESET 0
+#define WD_MASK_RESET_S 1
+
+// Bit fields for Local Interrupt Set Mask Registers (GIC_COREi_SMASK) or for MT (GIC_VPEi_SMASK)
+#define FDC_MASK_SET 6
+#define FDC_MASK_SET_S 1
+#define SWINT1_MASK_SET 5
+#define SWINT1_MASK_SET_S 1
+#define SWINT0_MASK_SET 4
+#define SWINT0_MASK_SET_S 1
+#define PERFCOUNT_MASK_SET 3
+#define PERFCOUNT_MASK_SET_S 1
+#define TIMER_MASK_SET 2
+#define TIMER_MASK_SET_S 1
+#define COMPARE_MASK_SET 1
+#define COMPARE_MASK_SET_S 1
+#define WD_MASK_SET 0
+#define WD_MASK_SET_S 1
+
+// Bit fields for CORE-Other or for MT VPE-Other Addressing Register
+#define VPENum 0
+#define VPENum_S 16
+#define CORENum 0
+#define CORENum_S 16
+
+// Bit fields for Core-Local Identification Register (GIC_COREi_IDENT) or for MT (GIC_VPEi_IDENT)
+#define VPENumIDENT 0
+#define VPENumIDENT_S 32
+#define CORENumIDENT 0
+#define CORENumIDENT_S 32
+
+// Bit fields for Local EIC Shadow Set Registers (GIC_COREi_EICSSj) or for MT (GIC_VPEi_EICSSj)
+#define EIC_SS 0
+#define EIC_SS_S 4
+
+// Bit fields for Local WatchDog/Compare/PerfCount/SWIntx Map to Pin Registers
+#define MAP_TO_PIN 31
+#define MAP_TO_PIN_S 1
+#define MAP_TO_NMI 30
+#define MAP_TO_NMI_S 1
+#define MAP_TO_YQ 29
+#define MAP_TO_YQ_S 1
+#define MAP 0
+#define MAP_S 6
+
+// Bit fields for Watchdog Timer Config Register (GIC_COREi_WD_CONFIGk) or for MT (GIC_VPEi_WD_CONFIGk)
+#define WDRESET 7
+#define WDRESET_S 1
+#define WDINTR 6
+#define WDINTR_S 1
+#define WAITMODE_CNTRL 5
+#define WAITMODE_CNTRL_S 1
+#define DEBUGMODE_CNTRL 5
+#define DEBUGMODE_CNTRL_S 1
+#define TYPE 1
+#define TYPE_S 3
+// TYPE Filed encoding:
+#define WD_One_Trip_Mode 0
+#define WD_Second_Countdown_Mode 1
+#define PIT_Mode 2
+
+// Bit fields for Local DINT Group Participate Register (GIC_Cx_DINT_PART) or for MT (GIC_Vx_DINT_PART)
+#define DINT_Group_Particpate 0
+#define DINT_Group_Particpate_S 1
+
+// GIC, GIC User Mode Visible Section Offsets
+#define USER_MODE_VISIBLE_SECTION_OFFSET 0x10000
+#define GIC_SH_COUNTERLO 0x0000
+#define GIC_SH_COUNTERHI 0x0004
+
+// Cluster Power Controller Global Section
+// CPC Block CPC_ACCESS_REG, fields and sizes
+#define CPC_ACCESS_REG 0x000
+#define CM_ACCESS_EN 0
+#define CM_ACCESS_EN_S 8
+
+// CPC Block CPC_SEQDEL_REG, fields and sizes
+#define CPC_SEQDEL_REG 0x008
+#define MICROSTEP 0
+#define MICROSTEP_S 10
+
+// CPC Block CPC_RAIL_REG, fields and sizes
+#define CPC_RAIL_REG 0x010
+#define RAILDELAY 0
+#define RAILDELAY_S 10
+
+// CPC Block CPC_RESETLEN_REG, fields and sizes
+#define CPC_RESETLEN_REG 0x018
+#define RESETLEN 0
+#define RESETLEN_S 10
+
+// CPC Block CPC_REVISION_REG, fields and sizes
+#define CPC_REVISION_REG 0x020
+#define MAJOR_REV_CPC 8
+#define MAJOR_REV_CPC_S 8
+#define MINOR_REV_CPC 0
+#define MINOR_REV_CPC_S 8
+
+// Cluster Power Controller Local and Other section
+#define CPS_CORE_LOCAL_CONTROL_BLOCK 0x2000
+#define CPS_CORE_OTHER_CONTROL_BLOCK 0x4000
+
+// CPC Local and Other CPC_CMD_REG, command encoding
+#define CPC_CMDL_REG 0x000
+#define CPC_CMDO_REG 0x000
+#define CLOCK_OFF 1
+#define PWR_DOWN 2
+#define PWR_UP 3
+#define CPC_RESET 4
+
+// CPC Local and Other CPC_STAT_CONF, fields, sizes and encodings
+#define CPC_STATL_CONF_REG 0x008
+#define CPC_STATO_CONF_REG 0x008
+#define PWRUP_EVENT 23
+#define PWRUP_EVENT_S 1
+#define SEQ_STATE 19
+#define SEQ_STATE_S 4
+
+// sequencer state encodings
+#define PWR_DOWN_STATE 0x0
+#define VDD_OK_STATE 0x1
+#define UP_DELAY_STATE 0x2
+#define UCLK_OFF_STATE 0x3
+#define CPC_RESET_STATE 0x4
+#define CPC_RESET_DLY_STATE 0x5
+#define NON_COHERENT_EXECUTION_STATE 0x6
+#define COHERENT_EXECUTION_STATE 0x7
+#define ISOLATE_STATE 0x8
+#define CLR_BUS_STATE 0x8
+#define DCLK_OFF_STATE 0xA
+
+#define CLKGAT_IMPL 17
+#define CLKGAT_IMPL_S 1
+#define PWRDN_IMPL 16
+#define PWRDN_IMPL_S 1
+#define EJTAG_PROBE 15
+#define EJTAG_PROBE_S 1
+#define PWUP_POLICY 8
+#define PWUP_POLICY_S 2
+// Power up state encodings
+#define POLICY_PWR_DOWN 0
+#define POLICY_GO_CLOCK_OFF 1
+#define PLOICY_PWR_UP 2
+
+#define IO_TRFFC_EN 4
+#define IO_TRFFC_EN_S 1
+#define CPC_CMD_STATE 0
+#define CPC_CMD_STATE_S 4
+
+// CPC Local and Other Addressing Register CPC_OTHER_REG, field and size
+#define CPC_OTHERL_REG 0x010
+#define CPC_OTHERO_REG 0x010
+#define CPC_CORENUM 16
+#define CPC_CORENUM_S 8
+
+
+#endif /* CPS_H_ */
diff --git a/mcu/driver/sys_drv/init/inc/md97/asm_common_def_gcc.h b/mcu/driver/sys_drv/init/inc/md97/asm_common_def_gcc.h
new file mode 100644
index 0000000..8cbcfa1
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/asm_common_def_gcc.h
@@ -0,0 +1,46 @@
+
+#ifndef _ASM_COMMON_DEF_GCC_
+#define _ASM_COMMON_DEF_GCC_
+
+
+#define GCC_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+
+#define GCC_ASM_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_ASM_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+.macro declare_stack name, val=0
+ .type \name , %object
+ \name :
+ .ascii "STACKEND"
+ .space \val
+ 1:
+ .size \name , 1b - \name
+.endm
+
+#if 0
+#ifdef __STACK_ALIGN_MPU__
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+#endif
+
+#endif
+
+
diff --git a/mcu/driver/sys_drv/init/inc/md97/boot_asm.h b/mcu/driver/sys_drv/init/inc/md97/boot_asm.h
new file mode 100644
index 0000000..48fc0c4
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/boot_asm.h
@@ -0,0 +1,196 @@
+
+#ifndef __BOOT_ASM_H__
+#define __BOOT_ASM_H__
+
+#include <bootarm.h>
+
+/*************************************************************************
+ * Macro definition
+ *************************************************************************/
+#define __LEGACY_NMI_CHECK__ (0x0)
+#if defined(__ESL_MASE_GEN97__)
+#define __MULTI_VPE_EN__ (0x0)
+#else /*__ESL_MASE_GEN97__*/
+#define __MULTI_VPE_EN__ (0x1)
+#endif/*__ESL_MASE_GEN97__*/
+#define MX_FEATURE (0x0)
+
+#if defined(_SIMULATION)
+#define INIT_DEF_VALUE (0x0)
+#else
+#define INIT_DEF_VALUE (0xdeadbeef)
+#endif
+
+#define BOOTTRC_MAGIC_ADDR (INT_bootup_magic)
+
+#define BOOTTRC_VPE0_ADDR (INT_bootup_trace0)
+#define BOOTTRC_VPE1_ADDR (INT_bootup_trace1)
+#define BOOTTRC_VPE2_ADDR (INT_bootup_trace2)
+
+#define BOOTTRC_VPE4_ADDR (INT_bootup_trace4)
+#define BOOTTRC_VPE5_ADDR (INT_bootup_trace5)
+#define BOOTTRC_VPE6_ADDR (INT_bootup_trace6)
+
+#define BOOTTRC_VPE8_ADDR (INT_bootup_trace8)
+#define BOOTTRC_VPE9_ADDR (INT_bootup_trace9)
+#define BOOTTRC_VPE10_ADDR (INT_bootup_trace10)
+
+#define BOOTTRC_VPE12_ADDR (INT_bootup_trace12)
+#define BOOTTRC_VPE13_ADDR (INT_bootup_trace13)
+#define BOOTTRC_VPE14_ADDR (INT_bootup_trace14)
+
+.extern Set_HS1_Boot_Trace
+.extern Boot_Trace_PreInit
+#if !defined(__COSIM_BYPASS_DRV__) && !defined(__ESL_MASE_GEN97__)
+.macro INT_TRC_SAVE_RA trace_id
+ //move $t0, $ra
+ INT_TRC \trace_id
+ //move $ra, $t0
+.endm
+.macro INT_TRC trace_id
+//#if defined(__SP_BOOTTRC_ENABLE__)
+ li $a0, \trace_id
+ la $a2, Set_HS1_Boot_Trace
+ //la $a2, INC_TRC
+ jalrc $a2
+//#endif
+.endm
+.macro INT_TRC_INIT_MAGIC
+ la $a2, Set_HS1_Boot_Trace
+ la $a1, INT_bootup_entry
+ sw $a2, 0x0($a1)
+ la $a2, Boot_Trace_PreInit
+ jalrc $a2
+.endm
+#else
+.macro INT_TRC_SAVE_RA trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC_INIT_MAGIC
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+#endif /* !defined(__COSIM_BYPASS_DRV__) */
+
+.macro INT_GET_CPUID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 4
+.endm
+
+.macro INT_GET_VPEID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 2
+.endm
+
+.macro INT_GET_COREID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 2, 2
+.endm
+
+
+/*************************************************************************
+ * Function definition
+ *************************************************************************/
+
+LEAF(INC_TRC)
+//#if defined(__SP_BOOTTRC_ENABLE__)
+
+ INT_GET_CPUID $a2, r23_cpu_num
+
+INT_init_VPE0_boot_trace:
+ li $a3, 0x0
+ bnec r23_cpu_num, $a3, INT_init_VPE1_boot_trace
+
+ li $a1, INIT_MAGIC
+ la $a2, BOOTTRC_MAGIC_ADDR
+ sw $a1, 0x0($a2)
+ la $a2, BOOTTRC_VPE0_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE1_boot_trace:
+ li $a3, 0x1
+ bnec r23_cpu_num, $a3, INT_init_VPE2_boot_trace
+
+ la $a2, BOOTTRC_VPE1_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE2_boot_trace:
+ li $a3, 0x2
+ bnec r23_cpu_num, $a3, INT_init_VPE4_boot_trace
+
+ la $a2, BOOTTRC_VPE2_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE4_boot_trace:
+ li $a3, 0x4
+ bnec r23_cpu_num, $a3, INT_init_VPE5_boot_trace
+
+ la $a2, BOOTTRC_VPE4_ADDR
+ bc INT_init_boot_trace_done
+
+
+INT_init_VPE5_boot_trace:
+ li $a3, 0x5
+ bnec r23_cpu_num, $a3, INT_init_VPE6_boot_trace
+
+ la $a2, BOOTTRC_VPE5_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE6_boot_trace:
+ li $a3, 0x6
+ bnec r23_cpu_num, $a3, INT_init_VPE8_boot_trace
+
+ la $a2, BOOTTRC_VPE6_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE8_boot_trace:
+ li $a3, 0x8
+ bnec r23_cpu_num, $a3, INT_init_VPE9_boot_trace
+
+ la $a2, BOOTTRC_VPE8_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE9_boot_trace:
+ li $a3, 0x9
+ bnec r23_cpu_num, $a3, INT_init_VPE10_boot_trace
+
+ la $a2, BOOTTRC_VPE9_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE10_boot_trace:
+ li $a3, 0xA
+ bnec r23_cpu_num, $a3, INT_init_VPE12_boot_trace
+
+ la $a2, BOOTTRC_VPE10_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE12_boot_trace:
+ li $a3, 0xC
+ bnec r23_cpu_num, $a3, INT_init_VPE13_boot_trace
+
+ la $a2, BOOTTRC_VPE12_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE13_boot_trace:
+ li $a3, 0xD
+ bnec r23_cpu_num, $a3, INT_init_VPE14_boot_trace
+
+ la $a2, BOOTTRC_VPE13_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE14_boot_trace:
+ la $a2, BOOTTRC_VPE14_ADDR
+
+
+INT_init_boot_trace_done:
+ sw $a0, 0x0($a2)
+ jrc $ra
+
+//#endif
+END(INC_TRC)
+
+
+
+#endif /* __BOOTARM_ASM_H__ */
diff --git a/mcu/driver/sys_drv/init/inc/md97/idle_service.h b/mcu/driver/sys_drv/init/inc/md97/idle_service.h
new file mode 100644
index 0000000..6edb0ed
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/idle_service.h
@@ -0,0 +1,276 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_service.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file provides idle service related header.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __IDLE_SERVICE_H__
+#define __IDLE_SERVICE_H__
+
+#include "kal_cpuinfo.h"
+
+#define VPE_NUMBER SYS_MCU_NUM_VPE
+#define CORE_NUMBER SYS_MCU_NUM_CORE
+#define PER_CORE_VPE_NUM 3
+
+#define IRQ_SW_CORE0_VPE0_LEAVE_WAIT IRQ_SW_LISR22_CODE /* IRQ ID 302 */
+#define IRQ_SW_CORE1_VPE0_LEAVE_WAIT IRQ_SW_LISR23_CODE /* IRQ ID 303 */
+#define IRQ_SW_CORE2_VPE0_LEAVE_WAIT IRQ_SW_LISR24_CODE /* IRQ ID 304 */
+#define IRQ_SW_CORE3_VPE0_LEAVE_WAIT IRQ_SW_LISR25_CODE /* IRQ ID 305 */
+
+#define IDLE_SERVICE_STEP_MAX 48
+
+#define IDLE_STATUS_NORMAL 0
+#define IDLE_STATUS_DORMANT 2
+
+#define WHOLE_CORE KAL_TRUE
+#define SINGLE_VPE KAL_FALSE
+
+typedef enum{
+/* Below for step logging */
+ IDLE_HANDLER_USER_IAPMU_CM = 0x1100,
+
+ IDLE_HANDLER_ENTER = 0x0000,
+ IDLE_HANDLER_LEAVE = 0x00FF,
+
+ IDLE_HANDLER_ENTER_DI = 0x02,
+ IDLE_REMOVE_FROM_SCHEDULING = 0x03,
+ IDLE_REMOVE_FROM_SCHEDULING_FAIL = 0x04,
+ IDLE_REMOVE_FROM_SCHEDULING_OK = 0x05,
+ IDLE_CHECK_PENDING_IRQ_FAIL = 0x06,
+ IDLE_CHECK_PENDING_IRQ_OK = 0x07,
+ IDLE_CHECK_SW_LOCK_DONE = 0x08,
+ IDLE_WAIT_CASE = 0x09,
+ IDLE_NOT_SLEEP_TIME = 0x0A,
+ IDLE_CORE_CHECK_SLEEP = 0x0B,
+ IDLE_CORE_CHECK_SLEEP_DONE = 0x0C,
+
+ IDLE_COREx_VPE1_NOT_IN_WAIT = 0x0E,
+ IDLE_DIRECTLY_WAIT = 0x0F,
+
+ IDLE_OSTD_WAIT = 0x10,
+ IDLE_OSTD_WAIT_ENTER = 0x11,
+ IDLE_OSTD_WAIT_LEAVE = 0x12,
+
+ IDLE_OSTD_BUSY = 0x20,
+
+ IDLE_OSTD_DORMANT = 0x30,
+ //IDLE_OSTD_DORMANT_ENTER = 0x31,
+ //IDLE_OSTD_DORMANT_LEAVE = 0x32,
+
+ IDLE_PTP_SLEEP_ENTER = 0x35,
+ IDLE_PTP_SLEEP_LEAVE = 0x36,
+ IDLE_PTP_WAKE_ENTER = 0x37,
+ IDLE_PTP_WAKE_LEAVE = 0x38,
+
+ IDLE_DORMANT_ABORT_LEAVE = 0x40,
+ IDLE_DORMANT_ABORT_WAIT_ENTER = 0x41,
+ IDLE_DORMANT_ABORT_WAIT_LEAVE = 0x42,
+
+ IDLE_DORMANT_RESTORE_LEAVE = 0x45,
+ IDLE_DORMANT_RESTORE_WAIT_ENTER = 0x46,
+ IDLE_DORMANT_RESTORE_WAIT_LEAVE = 0x47,
+
+ IDLE_CSC_HANDLER_ENTER = 0x48,
+ IDLE_CSC_HANDLER_LEAVE = 0x49,
+
+ IDLE_VPE1_VPE2_ENTER_SCHED = 0x50,
+
+ IDLE_WFI_WAIT_ENTER = 0x60,
+ IDLE_WFI_WAIT_LEAVE = 0x61,
+
+ IDLE_OSTD_INVALID_CASE = 0x99,
+/* Above for step logging */
+}IDLE_ACTION_INDEX;
+
+typedef enum{
+// IDLE_EMM_START_PATTERN = 0xEDEC0000 and write by CMM owner
+//IDLE TASK: WFI(=WAIT) ENTER/LEAVE per vpe
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER = 0,
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_LEAVE,
+
+//IDLE TASK: SLEEP ENTER/LEAVE per VPE
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_LEAVE,
+
+// IDLE TASK: step logging
+ IDLE_EMM_VPE0_IDLE_TASK_FMA,
+ IDLE_EMM_VPE0_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE1_IDLE_TASK_FMA,
+ IDLE_EMM_VPE1_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE2_IDLE_TASK_FMA,
+ IDLE_EMM_VPE2_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE3_IDLE_TASK_FMA,
+ IDLE_EMM_VPE3_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE4_IDLE_TASK_FMA,
+ IDLE_EMM_VPE4_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE5_IDLE_TASK_FMA,
+ IDLE_EMM_VPE5_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE6_IDLE_TASK_FMA,
+ IDLE_EMM_VPE6_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE7_IDLE_TASK_FMA,
+ IDLE_EMM_VPE7_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE8_IDLE_TASK_FMA,
+ IDLE_EMM_VPE8_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE9_IDLE_TASK_FMA,
+ IDLE_EMM_VPE9_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE10_IDLE_TASK_FMA,
+ IDLE_EMM_VPE10_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE11_IDLE_TASK_FMA,
+ IDLE_EMM_VPE11_IDLE_TASK_STEPLOGGING,
+
+//IDLE TASK: EPOF end to WFI per CORE
+ IDLE_EMM_Core0_INFINITESLEEP_WFI,
+ IDLE_EMM_Core1_INFINITESLEEP_WFI,
+ IDLE_EMM_Core2_INFINITESLEEP_WFI,
+ IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+ IDLE_EMM_INDEX_MAX = IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+// IDLE_EMM_END_PATTERN = 0xCEDE0000 and write by CMM owner
+
+}IDLE_EMM_LOG_INDEX;
+
+extern void idle_service_step_logging(kal_uint32 vpe_id, IDLE_ACTION_INDEX step, kal_bool Log_To_EMM);
+extern void Idle_Service_Prepare_WAIT(void);
+extern kal_uint32 idle_service_leave_wait_time[VPE_NUMBER];
+#if defined (__MODEM_CCCI_EXIST__)
+extern kal_bool IDLE_EMM_WriteDbgInfo(kal_uint32 index, void* addr);
+#endif
+
+#endif
+
diff --git a/mcu/driver/sys_drv/init/inc/md97/init_comm_trc.h b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc.h
new file mode 100644
index 0000000..f2de8bb
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc.h
@@ -0,0 +1,93 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_comm_trc.h
+ *
+ * Project:
+ * --------
+ * Moly_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _INIT_COMM_TRC_H
+#define _INIT_COMM_TRC_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+/*************************************************************************
+ * Define INIT trace information
+ *************************************************************************/
+#if !defined(GEN_FOR_PC)
+#if !defined(__MAUI_BASIC__)
+#include"init_comm_trc_mod_init_log_utmd.h"
+#endif
+#endif
+#endif /* _INIT_COMM_TRC_H */
diff --git a/mcu/driver/sys_drv/init/inc/md97/init_comm_trc_mod_init_log_utmd.json b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc_mod_init_log_utmd.json
new file mode 100644
index 0000000..cea6b7d
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/init_comm_trc_mod_init_log_utmd.json
@@ -0,0 +1,201 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_INIT_LOG",
+ "startGen": "97",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "INIT_LOG_VERSION_CODE_TITLE": {
+ "apiType": "index",
+ "format": "======================= Version code information =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "HW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_SW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "SW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_CODE": {
+ "apiType": "index",
+ "format": "HW_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_SUB_CODE": {
+ "apiType": "index",
+ "format": "HW_SUB_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_MD_BOOT_CHECK": {
+ "apiType": "index",
+ "format": "MD_BOOT_CHECK: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_VERSION_CODE_END": {
+ "apiType": "index",
+ "format": "======================= Version code information end =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "INIT"
+}
\ No newline at end of file
diff --git a/mcu/driver/sys_drv/init/inc/md97/mdmcu_i7200_common_macro.h b/mcu/driver/sys_drv/init/inc/md97/mdmcu_i7200_common_macro.h
new file mode 100644
index 0000000..303f7eb
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/mdmcu_i7200_common_macro.h
@@ -0,0 +1,199 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(GEN_FOR_PC) && !defined(__ASSEMBLER__) && defined(__MTK_TARGET__)\
+ && !defined(__MD97_MDMCU_COMMON_MACRO_H__) && defined(__MIPS_I7200__)
+
+#define __MD97_MDMCU_COMMON_MACRO_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+#ifndef __ASSEMBLER__
+/*******************************************************************************
+ * OS Relative
+ ******************************************************************************/
+#define miu_set_c0_tcschedule2(__throt_cfg__, __grp__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCSCHEDULE); \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_update_reg_bitfd( \
+ MIU_C0_TCSCHEDULE_PRIO, __r, __grp__) \
+ ); \
+ })
+
+#define miu_save_and_set_c0_tcschedule_grp(__grp__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCSCHEDULE); \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_update_reg_bitfd( \
+ MIU_C0_TCSCHEDULE_PRIO, __r, __grp__) \
+ ); \
+ miu_get_reg_bitfd_val(MIU_C0_TCSCHEDULE_PRIO, __r); \
+ })
+
+// WRR2 Throttle Not Supported in I7200
+#define MIU_DEF_NORMAL_DOM_THROT_VAL 0
+#define MIU_DEF_HRT_DOM_THROT_VAL 0
+
+/*******************************************************************************
+ * Register Read/Write
+ ******************************************************************************/
+#define miu_reg(__ADDR__) *(volatile kal_uint32*)(__ADDR__)
+
+#define miu_write_reg(__ADDR__, __VAL__) do { \
+ miu_reg(__ADDR__) = __VAL__; \
+ miu_compiler_barrier(); \
+ } while(0)
+
+#define miu_set_reg(__ADDR__, __VAL__) do { \
+ const kal_uint32 __addr__ = __ADDR__; \
+ miu_write_reg(__addr__, \
+ miu_reg(__addr__) | __VAL__); \
+ } while(0)
+
+#define miu_write_reg_bitfd(__ADDR__, __BITFD__, __VAL__) do { \
+ const kal_uint32 __addr__ = __ADDR__; \
+ const kal_uint32 __val__ = __VAL__; \
+ register kal_uint32 tmp; \
+ tmp = miu_reg(__addr__); \
+ tmp = miu_update_reg_bitfd(__BITFD__, tmp, __val__); \
+ miu_write_reg(__addr__, tmp); \
+ } while(0)
+
+/*******************************************************************************
+ * Special Instructions
+ ******************************************************************************/
+#define miu_count_leading_one(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clo %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_count_leading_zero(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clz %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_yield(yq) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __yqn = (yq); \
+ register miu_reg32_t \
+ __ret; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ ".set mt; \n" \
+ "yield %[ret],%z[yqn]; \n" \
+ ".set pop; \n" \
+ : [ret] "=d" (__ret) \
+ : [yqn] "dJ" (__yqn) \
+ ); \
+ __ret; \
+ })
+
+#define miu_rotr(__x__, __off__) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __res = __x__; \
+ register miu_reg32_t \
+ __off = __off__; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "rotr %0,%1; \n" \
+ ".set pop; \n" \
+ : "=d" (__res) \
+ : "dJ" (__off)); \
+ __res; \
+ })
+
+#define miu_pref(__hint__, __addr__) do { \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ " pref %[hint], 0(%[addr]); \n" \
+ ".set pop; \n" \
+ :: [hint] "i" (__hint__), \
+ [addr] "d" (__addr__) \
+ : \
+ ); \
+ } while(0)
+
+/*******************************************************************************
+ * CP0 Relative
+ ******************************************************************************/
+#define miu_get_and_set_errctl_wst_spr_itc(__wst__, __spr__, __itc__) \
+ __extension__ ({ \
+ register miu_reg32_t __old__; \
+ register miu_reg32_t __new__; \
+ __old__ = miu_mfc0(MIU_C0_ERRCTL); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_WST, __old__, __wst__); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_SPR, __new__, __spr__); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_ITC, __new__, __itc__); \
+ miu_mtc0(MIU_C0_ERRCTL, __new__); \
+ __old__; \
+ })
+
+#define miu_restore_errctl(__newval__) miu_mtc0(MIU_C0_ERRCTL, __newval__);
+
+#define miu_get_binding_vpe_id() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCBIND); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_TCBIND_CURVPE, __r); \
+ })
+
+/*******************************************************************************
+ * C Common
+ ******************************************************************************/
+#define miu_get_current_addr() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push \n" \
+ ".set noreorder \n" \
+ "%=: \n" \
+ " lui %0, %%hi(%=b) \n" \
+ " addiu %0, %%lo(%=b) \n" \
+ ".set pop \n" \
+ : "=d" (__r) :: \
+ ); \
+ __r; \
+ })
+
+// FIXME: not realy safe
+#define miu_array_count_of(x) (sizeof(x)/sizeof(x[0]))
+
+#endif /* __ASSEMBLER__ */
+#endif /* !defined(GEN_FOR_PC) && !defined(__ASSEMBLER__) && defined(__MTK_TARGET__)\
+ && !defined(__MD97_MDMCU_COMMON_MACRO_H__) && defined(__MIPS_I7200__) */
diff --git a/mcu/driver/sys_drv/init/inc/md97/mdmcu_init.h b/mcu/driver/sys_drv/init/inc/md97/mdmcu_init.h
new file mode 100644
index 0000000..f51fc63
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/mdmcu_init.h
@@ -0,0 +1,32 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97__)
+#define __MD97_MDMCU_INIT_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+/* I7200/NanoMIPS common macro */
+#include "md97/mdmcu_i7200_common_macro.h"
+
+#ifndef __ASSEMBLER__
+
+extern void mdmcu_init(void);
+extern void mdmcu_enter_dormant(void);
+extern void mdmcu_leave_dormant(void);
+extern void miu_wait(void);
+
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+
+#endif /* __ASSEMBLER__ */
+#endif /* !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97__) */
diff --git a/mcu/driver/sys_drv/init/inc/md97/sys_stack_config.h b/mcu/driver/sys_drv/init/inc/md97/sys_stack_config.h
new file mode 100644
index 0000000..9842765
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97/sys_stack_config.h
@@ -0,0 +1,61 @@
+/*
+ * SYS_STACK_INSTANCE(CORE, VPE, TC, SIZE, SECTION, TYPE)
+ */
+
+#ifndef SYS_STACK_INSTANCE
+# define SYS_STACK_INSTANCE
+#endif
+
+#ifndef SYS_STACK_NAME
+# define SYS_STACK_NAME(CORE, VPE, TC) SYS_Stack_Pool_CORE ## CORE ## _VPE ## VPE ## _TC ## TC
+#endif
+
+#ifndef SYS_STACK_INSTANCE_BEGIN
+# define SYS_STACK_INSTANCE_BEGIN()
+#endif
+
+#ifndef SYS_STACK_INSTANCE_END
+# define SYS_STACK_INSTANCE_END()
+#endif
+
+SYS_STACK_INSTANCE_BEGIN()
+
+SYS_STACK_INSTANCE(0, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(0, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__SINGLE_CORE__)
+SYS_STACK_INSTANCE(1, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(1, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__MD97_IS_2CORES__)
+SYS_STACK_INSTANCE(2, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(2, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+SYS_STACK_INSTANCE(3, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(3, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+SYS_STACK_INSTANCE_END()
+
+#undef SYS_STACK_INSTANCE
+#undef SYS_STACK_NAME
+#undef SYS_STACK_INSTANCE_BEGIN
+#undef SYS_STACK_INSTANCE_END
+
diff --git a/mcu/driver/sys_drv/init/inc/md97p/asm_common_def_gcc.h b/mcu/driver/sys_drv/init/inc/md97p/asm_common_def_gcc.h
new file mode 100644
index 0000000..8cbcfa1
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/asm_common_def_gcc.h
@@ -0,0 +1,46 @@
+
+#ifndef _ASM_COMMON_DEF_GCC_
+#define _ASM_COMMON_DEF_GCC_
+
+
+#define GCC_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+
+#define GCC_ASM_FUNC_LEAF(name)\
+ .##text;\
+ .##globl name;\
+ .##ent name;\
+name:
+
+#define GCC_ASM_FUNC_END(name)\
+ .##size name,.-name;\
+ .##end name
+
+.macro declare_stack name, val=0
+ .type \name , %object
+ \name :
+ .ascii "STACKEND"
+ .space \val
+ 1:
+ .size \name , 1b - \name
+.endm
+
+#if 0
+#ifdef __STACK_ALIGN_MPU__
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+#endif
+
+#endif
+
+
diff --git a/mcu/driver/sys_drv/init/inc/md97p/boot_asm.h b/mcu/driver/sys_drv/init/inc/md97p/boot_asm.h
new file mode 100644
index 0000000..48fc0c4
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/boot_asm.h
@@ -0,0 +1,196 @@
+
+#ifndef __BOOT_ASM_H__
+#define __BOOT_ASM_H__
+
+#include <bootarm.h>
+
+/*************************************************************************
+ * Macro definition
+ *************************************************************************/
+#define __LEGACY_NMI_CHECK__ (0x0)
+#if defined(__ESL_MASE_GEN97__)
+#define __MULTI_VPE_EN__ (0x0)
+#else /*__ESL_MASE_GEN97__*/
+#define __MULTI_VPE_EN__ (0x1)
+#endif/*__ESL_MASE_GEN97__*/
+#define MX_FEATURE (0x0)
+
+#if defined(_SIMULATION)
+#define INIT_DEF_VALUE (0x0)
+#else
+#define INIT_DEF_VALUE (0xdeadbeef)
+#endif
+
+#define BOOTTRC_MAGIC_ADDR (INT_bootup_magic)
+
+#define BOOTTRC_VPE0_ADDR (INT_bootup_trace0)
+#define BOOTTRC_VPE1_ADDR (INT_bootup_trace1)
+#define BOOTTRC_VPE2_ADDR (INT_bootup_trace2)
+
+#define BOOTTRC_VPE4_ADDR (INT_bootup_trace4)
+#define BOOTTRC_VPE5_ADDR (INT_bootup_trace5)
+#define BOOTTRC_VPE6_ADDR (INT_bootup_trace6)
+
+#define BOOTTRC_VPE8_ADDR (INT_bootup_trace8)
+#define BOOTTRC_VPE9_ADDR (INT_bootup_trace9)
+#define BOOTTRC_VPE10_ADDR (INT_bootup_trace10)
+
+#define BOOTTRC_VPE12_ADDR (INT_bootup_trace12)
+#define BOOTTRC_VPE13_ADDR (INT_bootup_trace13)
+#define BOOTTRC_VPE14_ADDR (INT_bootup_trace14)
+
+.extern Set_HS1_Boot_Trace
+.extern Boot_Trace_PreInit
+#if !defined(__COSIM_BYPASS_DRV__) && !defined(__ESL_MASE_GEN97__)
+.macro INT_TRC_SAVE_RA trace_id
+ //move $t0, $ra
+ INT_TRC \trace_id
+ //move $ra, $t0
+.endm
+.macro INT_TRC trace_id
+//#if defined(__SP_BOOTTRC_ENABLE__)
+ li $a0, \trace_id
+ la $a2, Set_HS1_Boot_Trace
+ //la $a2, INC_TRC
+ jalrc $a2
+//#endif
+.endm
+.macro INT_TRC_INIT_MAGIC
+ la $a2, Set_HS1_Boot_Trace
+ la $a1, INT_bootup_entry
+ sw $a2, 0x0($a1)
+ la $a2, Boot_Trace_PreInit
+ jalrc $a2
+.endm
+#else
+.macro INT_TRC_SAVE_RA trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC trace_id
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+.macro INT_TRC_INIT_MAGIC
+ // Bootup trace for MDM supported RTL Cosim
+.endm
+#endif /* !defined(__COSIM_BYPASS_DRV__) */
+
+.macro INT_GET_CPUID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 4
+.endm
+
+.macro INT_GET_VPEID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 0, 2
+.endm
+
+.macro INT_GET_COREID temp_r1, temp_r2
+ mfc0 \temp_r1, C0_EBASE
+ ext \temp_r2, \temp_r1, 2, 2
+.endm
+
+
+/*************************************************************************
+ * Function definition
+ *************************************************************************/
+
+LEAF(INC_TRC)
+//#if defined(__SP_BOOTTRC_ENABLE__)
+
+ INT_GET_CPUID $a2, r23_cpu_num
+
+INT_init_VPE0_boot_trace:
+ li $a3, 0x0
+ bnec r23_cpu_num, $a3, INT_init_VPE1_boot_trace
+
+ li $a1, INIT_MAGIC
+ la $a2, BOOTTRC_MAGIC_ADDR
+ sw $a1, 0x0($a2)
+ la $a2, BOOTTRC_VPE0_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE1_boot_trace:
+ li $a3, 0x1
+ bnec r23_cpu_num, $a3, INT_init_VPE2_boot_trace
+
+ la $a2, BOOTTRC_VPE1_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE2_boot_trace:
+ li $a3, 0x2
+ bnec r23_cpu_num, $a3, INT_init_VPE4_boot_trace
+
+ la $a2, BOOTTRC_VPE2_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE4_boot_trace:
+ li $a3, 0x4
+ bnec r23_cpu_num, $a3, INT_init_VPE5_boot_trace
+
+ la $a2, BOOTTRC_VPE4_ADDR
+ bc INT_init_boot_trace_done
+
+
+INT_init_VPE5_boot_trace:
+ li $a3, 0x5
+ bnec r23_cpu_num, $a3, INT_init_VPE6_boot_trace
+
+ la $a2, BOOTTRC_VPE5_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE6_boot_trace:
+ li $a3, 0x6
+ bnec r23_cpu_num, $a3, INT_init_VPE8_boot_trace
+
+ la $a2, BOOTTRC_VPE6_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE8_boot_trace:
+ li $a3, 0x8
+ bnec r23_cpu_num, $a3, INT_init_VPE9_boot_trace
+
+ la $a2, BOOTTRC_VPE8_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE9_boot_trace:
+ li $a3, 0x9
+ bnec r23_cpu_num, $a3, INT_init_VPE10_boot_trace
+
+ la $a2, BOOTTRC_VPE9_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE10_boot_trace:
+ li $a3, 0xA
+ bnec r23_cpu_num, $a3, INT_init_VPE12_boot_trace
+
+ la $a2, BOOTTRC_VPE10_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE12_boot_trace:
+ li $a3, 0xC
+ bnec r23_cpu_num, $a3, INT_init_VPE13_boot_trace
+
+ la $a2, BOOTTRC_VPE12_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE13_boot_trace:
+ li $a3, 0xD
+ bnec r23_cpu_num, $a3, INT_init_VPE14_boot_trace
+
+ la $a2, BOOTTRC_VPE13_ADDR
+ bc INT_init_boot_trace_done
+
+INT_init_VPE14_boot_trace:
+ la $a2, BOOTTRC_VPE14_ADDR
+
+
+INT_init_boot_trace_done:
+ sw $a0, 0x0($a2)
+ jrc $ra
+
+//#endif
+END(INC_TRC)
+
+
+
+#endif /* __BOOTARM_ASM_H__ */
diff --git a/mcu/driver/sys_drv/init/inc/md97p/idle_service.h b/mcu/driver/sys_drv/init/inc/md97p/idle_service.h
new file mode 100644
index 0000000..6edb0ed
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/idle_service.h
@@ -0,0 +1,276 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * idle_service.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * This file provides idle service related header.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __IDLE_SERVICE_H__
+#define __IDLE_SERVICE_H__
+
+#include "kal_cpuinfo.h"
+
+#define VPE_NUMBER SYS_MCU_NUM_VPE
+#define CORE_NUMBER SYS_MCU_NUM_CORE
+#define PER_CORE_VPE_NUM 3
+
+#define IRQ_SW_CORE0_VPE0_LEAVE_WAIT IRQ_SW_LISR22_CODE /* IRQ ID 302 */
+#define IRQ_SW_CORE1_VPE0_LEAVE_WAIT IRQ_SW_LISR23_CODE /* IRQ ID 303 */
+#define IRQ_SW_CORE2_VPE0_LEAVE_WAIT IRQ_SW_LISR24_CODE /* IRQ ID 304 */
+#define IRQ_SW_CORE3_VPE0_LEAVE_WAIT IRQ_SW_LISR25_CODE /* IRQ ID 305 */
+
+#define IDLE_SERVICE_STEP_MAX 48
+
+#define IDLE_STATUS_NORMAL 0
+#define IDLE_STATUS_DORMANT 2
+
+#define WHOLE_CORE KAL_TRUE
+#define SINGLE_VPE KAL_FALSE
+
+typedef enum{
+/* Below for step logging */
+ IDLE_HANDLER_USER_IAPMU_CM = 0x1100,
+
+ IDLE_HANDLER_ENTER = 0x0000,
+ IDLE_HANDLER_LEAVE = 0x00FF,
+
+ IDLE_HANDLER_ENTER_DI = 0x02,
+ IDLE_REMOVE_FROM_SCHEDULING = 0x03,
+ IDLE_REMOVE_FROM_SCHEDULING_FAIL = 0x04,
+ IDLE_REMOVE_FROM_SCHEDULING_OK = 0x05,
+ IDLE_CHECK_PENDING_IRQ_FAIL = 0x06,
+ IDLE_CHECK_PENDING_IRQ_OK = 0x07,
+ IDLE_CHECK_SW_LOCK_DONE = 0x08,
+ IDLE_WAIT_CASE = 0x09,
+ IDLE_NOT_SLEEP_TIME = 0x0A,
+ IDLE_CORE_CHECK_SLEEP = 0x0B,
+ IDLE_CORE_CHECK_SLEEP_DONE = 0x0C,
+
+ IDLE_COREx_VPE1_NOT_IN_WAIT = 0x0E,
+ IDLE_DIRECTLY_WAIT = 0x0F,
+
+ IDLE_OSTD_WAIT = 0x10,
+ IDLE_OSTD_WAIT_ENTER = 0x11,
+ IDLE_OSTD_WAIT_LEAVE = 0x12,
+
+ IDLE_OSTD_BUSY = 0x20,
+
+ IDLE_OSTD_DORMANT = 0x30,
+ //IDLE_OSTD_DORMANT_ENTER = 0x31,
+ //IDLE_OSTD_DORMANT_LEAVE = 0x32,
+
+ IDLE_PTP_SLEEP_ENTER = 0x35,
+ IDLE_PTP_SLEEP_LEAVE = 0x36,
+ IDLE_PTP_WAKE_ENTER = 0x37,
+ IDLE_PTP_WAKE_LEAVE = 0x38,
+
+ IDLE_DORMANT_ABORT_LEAVE = 0x40,
+ IDLE_DORMANT_ABORT_WAIT_ENTER = 0x41,
+ IDLE_DORMANT_ABORT_WAIT_LEAVE = 0x42,
+
+ IDLE_DORMANT_RESTORE_LEAVE = 0x45,
+ IDLE_DORMANT_RESTORE_WAIT_ENTER = 0x46,
+ IDLE_DORMANT_RESTORE_WAIT_LEAVE = 0x47,
+
+ IDLE_CSC_HANDLER_ENTER = 0x48,
+ IDLE_CSC_HANDLER_LEAVE = 0x49,
+
+ IDLE_VPE1_VPE2_ENTER_SCHED = 0x50,
+
+ IDLE_WFI_WAIT_ENTER = 0x60,
+ IDLE_WFI_WAIT_LEAVE = 0x61,
+
+ IDLE_OSTD_INVALID_CASE = 0x99,
+/* Above for step logging */
+}IDLE_ACTION_INDEX;
+
+typedef enum{
+// IDLE_EMM_START_PATTERN = 0xEDEC0000 and write by CMM owner
+//IDLE TASK: WFI(=WAIT) ENTER/LEAVE per vpe
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_ENTER = 0,
+ IDLE_EMM_VPE0_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_WFI_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_WFI_LEAVE,
+
+//IDLE TASK: SLEEP ENTER/LEAVE per VPE
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE0_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE1_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE2_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE3_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE4_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE5_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE6_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE7_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE8_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE9_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE10_IDLE_TASK_SLEEP_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_ENTER,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_DORMANT_ABORT_LEAVE,
+ IDLE_EMM_VPE11_IDLE_TASK_SLEEP_LEAVE,
+
+// IDLE TASK: step logging
+ IDLE_EMM_VPE0_IDLE_TASK_FMA,
+ IDLE_EMM_VPE0_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE1_IDLE_TASK_FMA,
+ IDLE_EMM_VPE1_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE2_IDLE_TASK_FMA,
+ IDLE_EMM_VPE2_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE3_IDLE_TASK_FMA,
+ IDLE_EMM_VPE3_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE4_IDLE_TASK_FMA,
+ IDLE_EMM_VPE4_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE5_IDLE_TASK_FMA,
+ IDLE_EMM_VPE5_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE6_IDLE_TASK_FMA,
+ IDLE_EMM_VPE6_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE7_IDLE_TASK_FMA,
+ IDLE_EMM_VPE7_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE8_IDLE_TASK_FMA,
+ IDLE_EMM_VPE8_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE9_IDLE_TASK_FMA,
+ IDLE_EMM_VPE9_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE10_IDLE_TASK_FMA,
+ IDLE_EMM_VPE10_IDLE_TASK_STEPLOGGING,
+ IDLE_EMM_VPE11_IDLE_TASK_FMA,
+ IDLE_EMM_VPE11_IDLE_TASK_STEPLOGGING,
+
+//IDLE TASK: EPOF end to WFI per CORE
+ IDLE_EMM_Core0_INFINITESLEEP_WFI,
+ IDLE_EMM_Core1_INFINITESLEEP_WFI,
+ IDLE_EMM_Core2_INFINITESLEEP_WFI,
+ IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+ IDLE_EMM_INDEX_MAX = IDLE_EMM_Core3_INFINITESLEEP_WFI,
+
+// IDLE_EMM_END_PATTERN = 0xCEDE0000 and write by CMM owner
+
+}IDLE_EMM_LOG_INDEX;
+
+extern void idle_service_step_logging(kal_uint32 vpe_id, IDLE_ACTION_INDEX step, kal_bool Log_To_EMM);
+extern void Idle_Service_Prepare_WAIT(void);
+extern kal_uint32 idle_service_leave_wait_time[VPE_NUMBER];
+#if defined (__MODEM_CCCI_EXIST__)
+extern kal_bool IDLE_EMM_WriteDbgInfo(kal_uint32 index, void* addr);
+#endif
+
+#endif
+
diff --git a/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc.h b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc.h
new file mode 100644
index 0000000..4af3859
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc.h
@@ -0,0 +1,87 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * init_comm_trc.h
+ *
+ * Project:
+ * --------
+ * Moly_Software
+ *
+ * Description:
+ * ------------
+ * This file contains definitions for trace on target.
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _INIT_COMM_TRC_H
+#define _INIT_COMM_TRC_H
+#ifndef GEN_FOR_PC
+#include "kal_public_defs.h"
+#endif /* GEN_FOR_PC */
+#include "kal_trace.h"
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+/*************************************************************************
+ * Define INIT trace information
+ *************************************************************************/
+#if !defined(GEN_FOR_PC)
+#include"init_comm_trc_mod_init_log_utmd.h"
+#endif
+#endif /* _INIT_COMM_TRC_H */
diff --git a/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc_mod_init_log_utmd.json b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc_mod_init_log_utmd.json
new file mode 100755
index 0000000..cea6b7d
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/init_comm_trc_mod_init_log_utmd.json
@@ -0,0 +1,201 @@
+{
+ "endGen": "-",
+ "legacyParameters": {},
+ "module": "MOD_INIT_LOG",
+ "startGen": "97",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-High",
+ "tag": [
+ "Baseline"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "INIT_LOG_VERSION_CODE_TITLE": {
+ "apiType": "index",
+ "format": "======================= Version code information =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "HW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_SW_VERSION_CODE": {
+ "apiType": "index",
+ "format": "SW_VERSION_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_CODE": {
+ "apiType": "index",
+ "format": "HW_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_HW_SUB_CODE": {
+ "apiType": "index",
+ "format": "HW_SUB_CODE: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_MD_BOOT_CHECK": {
+ "apiType": "index",
+ "format": "MD_BOOT_CHECK: 0x%x",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "INIT_LOG_VERSION_CODE_END": {
+ "apiType": "index",
+ "format": "======================= Version code information end =======================",
+ "traceClass": "TRACE_ERROR"
+ }
+ }
+ ],
+ "traceFamily": "PS",
+ "userModule": "INIT"
+}
\ No newline at end of file
diff --git a/mcu/driver/sys_drv/init/inc/md97p/mdmcu_init.h b/mcu/driver/sys_drv/init/inc/md97p/mdmcu_init.h
new file mode 100644
index 0000000..af61bc5
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/mdmcu_init.h
@@ -0,0 +1,32 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+#if !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97P__)
+#define __MD97_MDMCU_INIT_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#include "kal_iram_section_defs.h"
+#include "kal_public_defs.h"
+
+/* I7200/NanoMIPS common macro */
+#include "md97/mdmcu_i7200_common_macro.h"
+
+#ifndef __ASSEMBLER__
+
+extern void mdmcu_init(void);
+extern void mdmcu_enter_dormant(void);
+extern void mdmcu_leave_dormant(void);
+extern void miu_wait(void);
+
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+
+#endif /* __ASSEMBLER__ */
+#endif /* !defined(__MD97_MDMCU_INIT_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) && defined(__MD97P__) */
diff --git a/mcu/driver/sys_drv/init/inc/md97p/sys_stack_config.h b/mcu/driver/sys_drv/init/inc/md97p/sys_stack_config.h
new file mode 100644
index 0000000..9842765
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/md97p/sys_stack_config.h
@@ -0,0 +1,61 @@
+/*
+ * SYS_STACK_INSTANCE(CORE, VPE, TC, SIZE, SECTION, TYPE)
+ */
+
+#ifndef SYS_STACK_INSTANCE
+# define SYS_STACK_INSTANCE
+#endif
+
+#ifndef SYS_STACK_NAME
+# define SYS_STACK_NAME(CORE, VPE, TC) SYS_Stack_Pool_CORE ## CORE ## _VPE ## VPE ## _TC ## TC
+#endif
+
+#ifndef SYS_STACK_INSTANCE_BEGIN
+# define SYS_STACK_INSTANCE_BEGIN()
+#endif
+
+#ifndef SYS_STACK_INSTANCE_END
+# define SYS_STACK_INSTANCE_END()
+#endif
+
+SYS_STACK_INSTANCE_BEGIN()
+
+SYS_STACK_INSTANCE(0, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(0, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(0, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(0, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__SINGLE_CORE__)
+SYS_STACK_INSTANCE(1, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(1, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(1, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(1, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+#if !defined(__MD97_IS_2CORES__)
+SYS_STACK_INSTANCE(2, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(2, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(2, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(2, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+
+SYS_STACK_INSTANCE(3, 0, 0, 32*1024, CACHED_EXTSRAM_ZI, NUv3)
+SYS_STACK_INSTANCE(3, 0, 1, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 1, 2, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 1, 3, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+SYS_STACK_INSTANCE(3, 2, 4, 32*1024, CACHED_EXTSRAM_ZI, HRT)
+SYS_STACK_INSTANCE(3, 2, 5, 16*1024, CACHED_EXTSRAM_ZI, HRT_MT)
+#endif /*(__MD97_IS_2CORES__)*/
+#endif
+
+SYS_STACK_INSTANCE_END()
+
+#undef SYS_STACK_INSTANCE
+#undef SYS_STACK_NAME
+#undef SYS_STACK_INSTANCE_BEGIN
+#undef SYS_STACK_INSTANCE_END
+
diff --git a/mcu/driver/sys_drv/init/inc/mips_ia_utils.h b/mcu/driver/sys_drv/init/inc/mips_ia_utils.h
new file mode 100644
index 0000000..8c335b4
--- /dev/null
+++ b/mcu/driver/sys_drv/init/inc/mips_ia_utils.h
@@ -0,0 +1,234 @@
+/******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2019
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ * Pivate (SS Internal) header for some MIPS utils
+ *****************************************************************************/
+
+#if !defined(__MIPS_IA_UTILS_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__)
+#define __MIPS_IA_UTILS_H__
+#include "mips_ia_utils_public.h"
+#include "boot.h"
+#ifndef __ASSEMBLER__
+# include "kal_iram_section_defs.h"
+# include "kal_public_defs.h"
+#endif /* __ASSEMBLER__ */
+
+#if defined(__MIPS_I7200__)
+# if defined(__MD97__)
+# include "md97/mdmcu_init.h"
+# elif defined(__MD97P__)
+# include "md97p/mdmcu_init.h"
+# endif /* __MD97__ */
+
+#elif defined(__MIPS_IA__)
+#define __MIU_STATIC_INLINE__ __attribute__((always_inline)) static inline
+#if defined(__MIPS16__) && defined(__GNUC__)
+# define MIU_M32_FUNC __attribute__((nomips16))
+#else /* defined(__MIPS16__) && defined(__GNUC__) */
+# define MIU_M32_FUNC
+#endif /* defined(__MIPS16__) && defined(__GNUC__) */
+
+#if defined(CONFIG_MIPS_IA_MR2)
+# include "md93/mips_ia_mr2_utils.h"
+#elif defined(CONFIG_MIPS_IA_MR3)
+# include "md95/mips_ia_mr3_utils.h"
+#else /* MR1 (Gen-92) */
+# include "md93/mips_ia_mr1_utils.h"
+#endif /* CONFIG_MIPS_IA_MR2 */
+
+#define miu_c0_tcschedule_throt_val( \
+ __t1_stp__, __t1_grp__, __t1_th__, __t1_qe__, \
+ __t0_stp__, __t0_grp__, __t0_th__, __t0_qe__) \
+ ( \
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_STP, __t1_stp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_GRP, __t1_grp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_TH, __t1_th__ ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T1_QE, __t1_qe__ ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_STP, __t0_stp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_GRP, __t0_grp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_TH, __t0_th__ ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_T0_QE, __t0_qe__ ) \
+ )
+
+#define miu_c0_tcschedule_val_raw( \
+ __t1_stp__, __t1_grp__, __t1_th__, __t1_qe__, \
+ __t0_stp__, __t0_grp__, __t0_th__, __t0_qe__, \
+ __stp__, __grp__) \
+ ( \
+ miu_c0_tcschedule_throt_val( \
+ __t1_stp__, __t1_grp__, __t1_th__, __t1_qe__, \
+ __t0_stp__, __t0_grp__, __t0_th__, __t0_qe__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_STP, __stp__, ) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_GRP, __grp__, ) \
+ )
+
+#define miu_c0_tcschedule_val3( \
+ __throt_cfg__, __stp__, __grp__) \
+ ( \
+ __throt_cfg__ |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_STP, __stp__) |\
+ miu_reg_bitfd_mskoff_val(MIU_C0_TCSCHEDULE_GRP, __grp__) \
+ )
+
+#define miu_c0_tcschedule_val2(__throt_cfg__, __grp__) \
+ miu_c0_tcschedule_val3(__throt_cfg__, 0, __grp__)
+
+#define miu_set_c0_tcschedule2(__throt_cfg__, __grp__) \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_c0_tcschedule_val2(__throt_cfg__, __grp__))
+
+#define miu_save_and_set_c0_tcschedule_grp(__grp__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCSCHEDULE); \
+ miu_mtc0(MIU_C0_TCSCHEDULE, \
+ miu_update_reg_bitfd( \
+ MIU_C0_TCSCHEDULE_GRP, __r, __grp__) \
+ ); \
+ miu_get_reg_bitfd_val(MIU_C0_TCSCHEDULE_GRP, __r); \
+ })
+
+// TODO: assume Gen-92/Gen-93 use the same setting
+#define MIU_DEF_NORMAL_DOM_THROT_VAL \
+ miu_c0_tcschedule_throt_val( \
+ 1, 0, 1, MIU_C0_TCSCHEDULE_QE_LDQ, \
+ 1, 0, 1, MIU_C0_TCSCHEDULE_QE_WBB \
+ )
+
+#define MIU_DEF_HRT_DOM_THROT_VAL \
+ miu_c0_tcschedule_throt_val( \
+ 0, 0, 0, MIU_C0_TCSCHEDULE_QE_NOT, \
+ 0, 0, 0, MIU_C0_TCSCHEDULE_QE_NOT \
+ )
+
+#ifndef __ASSEMBLER__
+#define miu_count_leading_one(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clo %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_count_leading_zero(__x__) \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "clz %0, %1; \n" \
+ ".set pop; \n" \
+ : "=d" (__r) \
+ : "d" (__x__) \
+ ); \
+ __r; \
+ })
+
+#define miu_yield(yq) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __yqn = (yq); \
+ register miu_reg32_t \
+ __ret; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ ".set mt; \n" \
+ "yield %[ret],%z[yqn]; \n" \
+ ".set pop; \n" \
+ : [ret] "=d" (__ret) \
+ : [yqn] "dJ" (__yqn) \
+ ); \
+ __ret; \
+ })
+
+#define miu_rotr(__x__, __off__) \
+ __extension__ ({ \
+ register miu_reg32_t \
+ __res = __x__; \
+ register miu_reg32_t \
+ __off = __off__; \
+ __asm__ __volatile ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ "rotr %0,%1; \n" \
+ ".set pop; \n" \
+ : "=d" (__res) \
+ : "dJ" (__off)); \
+ __res; \
+ })
+
+#define miu_pref(__hint__, __addr__) do { \
+ __asm__ __volatile__ ( \
+ ".set push; \n" \
+ ".set noreorder; \n" \
+ " pref %[hint], 0(%[addr]); \n" \
+ ".set pop; \n" \
+ :: [hint] "i" (__hint__), \
+ [addr] "d" (__addr__) \
+ : \
+ ); \
+ } while(0)
+
+#define miu_get_and_set_errctl_wst_spr_itc(__wst__, __spr__, __itc__) \
+ __extension__ ({ \
+ register miu_reg32_t __old__; \
+ register miu_reg32_t __new__; \
+ __old__ = miu_mfc0(MIU_C0_ERRCTL); \
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_WST, __old__, __wst__);\
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_SPR, __new__, __spr__);\
+ __new__ = miu_update_reg_bitfd(MIU_C0_ERRCTL_ITC, __new__, __itc__);\
+ miu_mtc0(MIU_C0_ERRCTL, __new__); \
+ __old__; \
+ })
+
+#define miu_restore_errctl(__newval__) miu_mtc0(MIU_C0_ERRCTL, __newval__);
+
+// FIXME: not realy safe
+#define miu_array_count_of(x) (sizeof(x)/sizeof(x[0]))
+
+#define miu_get_binding_vpe_id() \
+ __extension__ ({ \
+ register miu_reg32_t __r; \
+ __r = miu_mfc0(MIU_C0_TCBIND); \
+ miu_get_reg_bitfd_val( \
+ MIU_C0_TCBIND_CURVPE, __r); \
+ })
+
+#ifdef CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS
+MIU_M32_FUNC extern
+void mips_ia_mr12_cross_config_vpe_rps(const unsigned int disable);
+# define miu_vpe1_cross_config_vpe0_rps(__disable__) \
+ mips_ia_mr12_cross_config_vpe_rps(__disable__)
+#else
+# define miu_vpe1_cross_config_vpe0_rps(__disable__) do {} while(0)
+#endif /* CONFIG_MIPS_IA_MR2_VPE1_DISABLE_VPE0_RPS */
+
+extern void mips_ia_misc_enter_dormant(void);
+extern void mips_ia_misc_leave_dormant(void);
+MIU_M32_FUNC extern void miu_wait(void);
+extern const kal_int32 mips_ia_lv3_dcm_enable(const kal_uint32 en);
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+extern void mips_ia_misc_init_by_core(void);
+extern void mips_ia_misc_init(void);
+#endif /* __ASSEMBLER__ */
+#else /* __MIPS_IA__ */
+# error "unknow mdmcu"
+#endif /* __MIPS_IA__ */
+
+#endif /* !defined(__MIPS_IA_UTILS_H__) && !defined(GEN_FOR_PC) && defined(__MTK_TARGET__) */