[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/devdrv/busmpu/busmpu.h b/mcu/interface/driver/devdrv/busmpu/busmpu.h
new file mode 100644
index 0000000..d2cb878
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/busmpu.h
@@ -0,0 +1,171 @@
+#ifndef __BUSMPU_H__
+#define __BUSMPU_H__
+
+/*****************************************************************************
+
+ * Symbol/Type Definition *
+
+ *****************************************************************************/
+#if defined(__MD97__) || defined(__MD97P__)
+
+#include "gen97_busmpu.h"
+
+#else
+
+typedef enum BUSMPU_REGION_ATTRIBUTE_T
+{
+ BUSMPU_RO = 0x0,
+ BUSMPU_RW = 0x1,
+ BUSMON_PERMISSION_MAX
+}BUSMPU_PERMISSION_TYPE;
+
+typedef kal_uint32 FIELD;
+
+/**
+ * 0x00 : MPU_IOCU_CTRL
+ */
+typedef union {
+ struct {
+ FIELD iocu_err_trig_mode : 1;
+ FIELD iocu_vio_clr : 1;
+ FIELD iocu_vio_info_clr : 1;
+ FIELD iocu_domain_int_en : 1;
+ FIELD iocu_align_int_en : 1;
+ FIELD rsv_5 : 27;
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_int_ctrl, *pbusmpu_iocu_int_ctrl;
+
+/**
+ * 0x04 : MPU_EMI_CTRL
+ */
+typedef union {
+ struct {
+ FIELD emi_err_trig_mode : 1;
+ FIELD emi_vio_clr : 1;
+ FIELD emi_vio_info_clr : 1;
+ FIELD emi_domain_int_en : 1;
+ FIELD rsv_4 : 28;
+ } Bits;
+ FIELD Raw;
+} busmpu_emi_int_ctrl, *pbusmpu_emi_int_ctrl;
+
+/**
+ * 0x10 : MPU_IRQ_STATUS
+ */
+typedef union {
+ struct {
+ FIELD iocu_wt_domain : 1;
+ FIELD iocu_rd_domain : 1;
+ FIELD iocu_wt_align : 1;
+ FIELD iocu_rd_align : 1;
+ FIELD iocu_int_status : 1;
+ FIELD emi_wt_domain : 1;
+ FIELD emi_rd_domain : 1;
+ FIELD emi_int_status : 1;
+ FIELD rsv_8 : 24;
+ } Bits;
+ FIELD Raw;
+} busmpu_irq_status, *pbusmpu_irq_status;
+
+/**
+ * 0x20 : MPU_IOCU_VIO_DATA0
+ */
+typedef union {
+ struct {
+ FIELD iocu_addr : 32;
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_vio_addr, *pbusmpu_iocu_vio_addr;
+
+/**
+ * 0x24 : MPU_IOCU_VIO_DATA1
+ */
+typedef union {
+ struct {
+ FIELD iocu_id : 12;
+ FIELD iocu_domain : 3;
+ FIELD iocu_ro : 1;
+ FIELD iocu_region : 5;
+ FIELD iocu_burst : 2;
+ FIELD iocu_size : 3;
+ FIELD iocu_len : 4;
+ FIELD rsv_30 : 2;
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_vio_info, *pbusmpu_iocu_vio_info;
+
+/**
+ * 0x28 : MPU_EMI_VIO_DATA0
+ */
+typedef union {
+ struct {
+ FIELD emi_addr : 32;
+ } Bits;
+ FIELD Raw;
+} busmpu_emi_vio_addr, *pbusmpu_emi_vio_addr;
+
+/**
+ * 0x2C : MPU_EMI_VIO_DATA1
+ */
+typedef union {
+ struct {
+ FIELD emi_id : 12;
+ FIELD emi_domain : 3;
+ FIELD emi_ro : 1;
+ FIELD emi_region : 8;
+ FIELD rsv_24 : 8;
+ } Bits;
+ FIELD Raw;
+} busmpu_emi_vio_info, *pbusmpu_emi_vio_info;
+
+/**
+ * 0x30 : MPU_EMI_VIO_DATA2
+ */
+typedef union {
+ struct {
+ FIELD emi_user : 12;
+ FIELD rsv_12 : 20;
+ } Bits;
+ FIELD Raw;
+} busmpu_emi_vio_user, *pbusmpu_emi_vio_user;
+
+typedef volatile struct {
+ busmpu_iocu_int_ctrl iocu_ctrl; // 0000
+ busmpu_emi_int_ctrl emi_ctrl; // 0004
+ FIELD rsv_0008[2]; // 0008..000C
+ busmpu_irq_status irq_status; // 0010
+ FIELD rsv_0014[3]; // 0014..001C
+ busmpu_iocu_vio_addr iocu_vio_addr; // 0020
+ busmpu_iocu_vio_info iocu_vio_info; // 0024
+ busmpu_emi_vio_addr emi_vio_addr; // 0028
+ busmpu_emi_vio_info emi_vio_info; // 002C
+ busmpu_emi_vio_user emi_vio_user; // 0030
+} busmpu_reg, *pbusmpu_reg;
+
+typedef struct {
+ busmpu_iocu_vio_addr addr;
+ busmpu_iocu_vio_info info;
+} busmpu_iocu_vio_data, busmpu_mdinfra_error_info_st;
+
+typedef struct {
+ busmpu_emi_vio_addr addr;
+ busmpu_emi_vio_info info;
+ busmpu_emi_vio_user user;
+} busmpu_emi_vio_data, busmpu_mdmcu_error_info_st;
+
+extern kal_bool busmpu_mdinfra_dump_err(void);
+extern kal_bool busmpu_mdmcu_dump_err(void);
+extern kal_bool busmpu_dump_irq_sts(void);
+extern void busmpu_init(void);
+extern volatile busmpu_emi_vio_data busmpu_emi_err;
+extern volatile busmpu_iocu_vio_data busmpu_iocu_err;
+extern volatile busmpu_irq_status busmpu_irq_sts;
+void drv_iocu_lisr(kal_uint32 v);
+void iocu_align_init(void);
+void drv_rmpu_lisr(kal_uint32 v);
+void rmpu_md_init(void);
+
+#endif /*#if defined(__MD97__)*/
+#endif /*__BUSMPU_H__*/
+
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h
new file mode 100644
index 0000000..3c3b11f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h
@@ -0,0 +1,173 @@
+#ifndef __GEN97_BUSMPU_H__
+#define __GEN97_BUSMPU_H__
+
+#if defined(MT6297) || defined(CHIP10992)
+#define EMIMPU_MD2AP_INFODUMP_ENABLE
+#endif
+
+/*****************************************************************************
+ * Symbol/Type Definition *
+ *****************************************************************************/
+typedef kal_uint32 FIELD;
+
+/**
+ * 0x00 : MPU_IOCU_CTRL
+ */
+typedef union {
+ struct {
+ FIELD reg_mpu_iocu_disable : 1; //default:1 (RW)
+ FIELD reg_mpu_iocu_bank2_default_pms : 2; //default:3 (RW)
+ FIELD reg_mpu_iocu_bank3_default_pms : 2; //default:3 (RW)
+ FIELD reg_mpu_iocu_bank9f_default_pms : 2; //default:3 (RW)
+ FIELD reg_mpu_iocu_err_trig_mode : 1; //default:0 (RW)
+ FIELD reg_mpu_iocu_vio_clr : 1; //default:0 (W1C)
+ FIELD reg_mpu_iocu_vio_info_clr : 1; //default:0 (W1C)
+ FIELD reg_mpu_iocu_int_en : 1; //default:1 (RW)
+ FIELD reg_mpu_iocu_align_int_en : 1; //default:0 (RW)
+ FIELD reg_mpu_ctrl_update : 1; //default:0 (WP)
+ FIELD reg_mpu_algin_rule_sel : 1; //default:0 (RW)
+ FIELD reg_mpu_iocu_int_msk : 1; //default:1 (RW)
+ FIELD reg_mpu_unused : 16;
+ FIELD reg_speed_sim : 1; //default:0 (RW)
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_ctrl, *pbusmpu_iocu_ctrl;
+
+/**
+ * 0x04 : MPU_IOCU_IRQ_STS
+ */
+typedef union {
+ struct {
+ FIELD o_vio_mpu_iocu_wt : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_rd : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_wt_align : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_rd_align : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_int_status : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_id : 12;//default:0 (RU)
+ FIELD o_vio_mpu_iocu_ro : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_region : 5; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_burst : 2; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_size : 3; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_len : 4; //default:0 (RU)
+ } Bits;
+ FIELD Raw;
+} busmpu_irq_status, *pbusmpu_irq_status;
+
+/**
+ * 0x8 : MPU_IOCU_VIO_ADDR
+ */
+typedef union {
+ struct {
+ FIELD iocu_vio_addr : 32; //default:0 (RU)
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_vio_addr, *pbusmpu_iocu_vio_addr;
+
+typedef struct {
+ busmpu_iocu_vio_addr addr;
+} busmpu_iocu_vio_data, busmpu_mdinfra_error_info_st;
+
+typedef volatile struct {
+ busmpu_iocu_ctrl iocu_ctrl; // 0000
+} busmpu_reg, *pbusmpu_reg;
+
+typedef struct{
+ kal_uint32 axi_id;
+ kal_uint32 port_id;
+ kal_uint32 vio_addr;
+ kal_uint32 wt_vio;
+ kal_uint32 rd_vio;
+} emimpu_vio_info_debug;
+
+
+typedef struct{
+ kal_uint32 mpus;
+ kal_uint32 mput;
+ kal_uint32 mput_2;
+ emimpu_vio_info_debug emimpu_info_debug;
+} emimpu_vio_info;
+
+//init RMPU & busmpu @HWDInitialization
+extern void rmpu_md_init(void);
+
+//dump busmpu info called by exception handler
+extern kal_bool busmpu_mdinfra_dump_err(void);
+extern kal_bool busmpu_dump_irq_sts(void);
+extern volatile busmpu_iocu_vio_data busmpu_iocu_err;
+extern volatile busmpu_irq_status busmpu_irq_sts;
+#if defined(EMIMPU_MD2AP_INFODUMP_ENABLE)
+extern volatile emimpu_vio_info emimpu_vio_dump;
+#endif
+
+//for bank2 wb
+extern void busmpu_wb_permission(kal_uint32 start_addr, kal_uint32 end_addr, kal_uint32 mask_filter, kal_uint32 busid);
+
+//bank2
+extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+
+//bank3
+extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+#endif /*__GEN97_BUSMPU_H__*/
+
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_config.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_config.h
new file mode 100644
index 0000000..57e213c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_config.h
@@ -0,0 +1,11 @@
+//user need to register busmpu channel for valid usage
+
+//define BUSMPU_CONFIG(entry_index, start_addr, end_addr, bus_id, mask_filter, permission, user_name)
+//addr>=start_addr & addr <= end_addr
+//bus id table http://mtkteams.mediatek.inc/sites/WCT/CD1/DE1_DE2/Shared%20Documents/U3G_U4G%20modemsys/MT6297/Bus/BUS%20ID/97%20MD%20ID%20table.xlsx
+//permission: 0 (R/W), 2 (RO), 3 (NA)
+//
+BUSMPU_CONFIG(0, IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb, IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb, 0, 0x7E0, 2, wei-hao.kuo)
+BUSMPU_CONFIG(1, IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb, IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb, 0, 0x7E0, 0, wei-hao.kuo)
+BUSMPU_CONFIG(2, IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb, IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb, 0x4C8, 0x10, 0, SJ.cheng)
+
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_master_config.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_master_config.h
new file mode 100644
index 0000000..f0c1734
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_master_config.h
@@ -0,0 +1,208 @@
+//Auto-dispatch List for Busmpu violation issue
+
+// define BUSMPU_MASTER_SRC(master_name, master_mdinfra_src_id, master_mdinfra_src_id_dontcare_mask, master_src_name, master_src_pic, dispatch_function_name)
+// please only modify master_src_name, master_src_pic and dispatch_function_name for changeing SW PIC.
+// Other field do not modified.
+// Make sure your registered function could be built pass in every load flavor.
+// Otherwise you should use correct option
+
+BUSMPU_MASTER_BEGIN(NRL2, 0x000)
+#if (defined(__NR_RAT__)||defined(__LTE_RAT__)) && defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(NRL2, 0b001000, 0b0, dl_decphr_qp__5g_pre_loader__qcache, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001001, 0b0, dl_decphr_qp__5g_pre_loader__rdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001010, 0b0, lted1_qp__pre_loader, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001011, 0b0, lted1_rdma__pre_loader, "Chi-Yen", dpcopro_desc_tbl_restore)
+
+BUSMPU_MASTER_SRC(NRL2, 0b010000, 0b0, nrul_cphr_qp__cotf_cc0, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010001, 0b0, nrul_cphr_qp__cotf_cc1, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010010, 0b0, nrul_cphr_cc_gen0_rdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010011, 0b0, nrul_cphr_cc_gen1_rdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010100, 0b0, nrul_cphr_qp__jump_cotf_cc0, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010101, 0b0, nrul_cphr_qp__jump_cotf_cc1, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b011000, 0b0, nrul_cphr_qp__ul_arbi_qp, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b011001, 0b0, nrul_cphr_qp__ul_retx_rdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+
+BUSMPU_MASTER_SRC(NRL2, 0b100000, 0b0, ul_lhif_qp, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b100001, 0b0, ul_lhif_rdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b101000, 0b0, qch_dma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b101001, 0b0, qch_qp, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b110000, 0b0, mmu_tlb, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b111000, 0b0, ipf, "Chi-Yen", dpcopro_desc_tbl_restore)
+
+BUSMPU_MASTER_SRC(NRL2, 0b000000, 0b1, dl_upp_wdma, "Wei-Hao", upp_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001000, 0b1, dl_decphr_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010000, 0b10, nrul_cphr_cc_gen0_wdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010001, 0b10, nrul_cphr_cc_gen1_wdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b011000, 0b1, ul_retx_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b100000, 0b1, ul_lhif_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b101000, 0b1, ltedl_lmac_wdma, "Wei-Hao", upp_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b110000, 0b1, gen95_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b111000, 0b111, gen95_lite_wdma, "NO_OWNER", drv_iocu_lisr)
+#endif
+BUSMPU_MASTER_END(NRL2)
+
+BUSMPU_MASTER_BEGIN(RXDBRP_NR, 0x100)
+#if (defined(__NR_RAT__)||defined(__LTE_RAT__)) && defined(__MTK_TARGET__)
+// BUSMPU_MASTER_SRC(RXDBRP_NR, 0b001, 0b0, nr_do, "tzu-han hsu", nr_pdsch_dbrp_hw_init)
+// BUSMPU_MASTER_SRC(RXDBRP_NR, 0b000, 0b10, nr_harq, "tzu-han hsu", nr_pdsch_dbrp_hw_init)
+#endif
+BUSMPU_MASTER_END(RXDBRP_NR)
+
+BUSMPU_MASTER_BEGIN(MCORE,0x200)
+BUSMPU_MASTER_SRC(MCORE, 0b1100000, 0b1100000, btdma, "Po-Sheng Wang", BTDMA_SW_Enable_Ungate_Signal)
+#if defined(__MD97__)
+BUSMPU_MASTER_SRC(MCORE, 0b0000010, 0b0, mcore0_pmu, "Terry.liao", DSP_BUS_Ultra_Config)
+BUSMPU_MASTER_SRC(MCORE, 0b0000110, 0b0, mcore1_pmu, "Terry.liao", DSP_BUS_Ultra_Config)
+BUSMPU_MASTER_SRC(MCORE, 0b0000011, 0b1111100, mcore, "Tzu-Ching Lin", DSP_BUS_Ultra_Config)
+BUSMPU_MASTER_SRC(MCORE, 0b0000001, 0b0, vcore_pmu, "Terry.liao", DSP_BUS_Ultra_Config)
+#endif
+BUSMPU_MASTER_END(MCORE)
+
+BUSMPU_MASTER_BEGIN(FE,0x300)
+#if !defined(__MAUI_BASIC__)
+BUSMPU_MASTER_SRC(FE, 0b1100000, 0b0, Md2gsys_md2g, "Jason Huang", idma_load_Genral)
+BUSMPU_MASTER_SRC(FE, 0b1000000, 0b0, Dfesys_rxdfe_xdma, "Owen Hsieh", MML1_RXDFE_D2D_DMA_TRIG)
+#endif
+BUSMPU_MASTER_SRC(FE, 0b1000010, 0b0, Dfesys_mrsg_dbg1, "HS Yang", drv_iocu_lisr/*TBD*/)
+BUSMPU_MASTER_SRC(FE, 0b1000100, 0b0, Dfesys_mrsg_dbg0, "HS Yang", drv_iocu_lisr/*TBD*/)
+#if !defined(__MAUI_BASIC__)
+BUSMPU_MASTER_SRC(FE, 0b1000110, 0b0, Dfesys_tpc_xdma, "Rick-YH Lin", MML1_TPC_Cfg_Hw_Dma)
+#if defined(__UMTS_TDD128_MODE__)
+BUSMPU_MASTER_SRC(FE, 0b1001010, 0b0, Dfesys_txbsrp, "Yanhai Xuan", TxHwInit)
+#endif
+#endif
+
+BUSMPU_MASTER_SRC(FE, 0b1001100, 0b0, Dfesys_CoS_0, "Sen Chang", cos_mpu_violation)
+BUSMPU_MASTER_SRC(FE, 0b1001101, 0b0, Dfesys_CoS_1, "Sen Chang", cos_mpu_violation)
+BUSMPU_MASTER_SRC(FE, 0b1001110, 0b0, Dfesys_tpc_nr_txsrp, "NO_OWNER", drv_iocu_lisr/*TBD*/)
+
+#if !defined(__MAUI_BASIC__)
+BUSMPU_MASTER_SRC(FE, 0b1010000, 0b0, Dfesys_D_GDMA_5_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010001, 0b0, Dfesys_D_GDMA_4_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010010, 0b0, Dfesys_D_GDMA_3_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010011, 0b0, Dfesys_D_GDMA_2_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010100, 0b0, Dfesys_D_GDMA_1_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010101, 0b0, Dfesys_D_GDMA_0_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010110, 0b0, Dfesys_D_GDMA_5_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010111, 0b0, Dfesys_D_GDMA_4_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011000, 0b0, Dfesys_D_GDMA_3_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011001, 0b0, Dfesys_D_GDMA_2_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011010, 0b0, Dfesys_D_GDMA_1_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011011, 0b0, Dfesys_D_GDMA_0_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+
+BUSMPU_MASTER_SRC(FE, 0b0100010, 0b0, cssys_CNWDMA, "Roy yu", EL1D_CS_Main_Init)
+BUSMPU_MASTER_SRC(FE, 0b0100001, 0b0, cssys_CSH, "Roy yu", EL1D_CS_Main_Init)
+BUSMPU_MASTER_SRC(FE, 0b0100000, 0b0, cssys_DCXO, "Roy yu", EL1D_CS_Main_Init)
+#endif
+
+#if (defined(__NR_RAT__) && defined(__MTK_TARGET__))
+BUSMPU_MASTER_SRC(FE, 0b0000000, 0b0, cssys_nr_cs_nr, "WY chou", NL1_MPC_Api_Drv_Cs_Irq_Handle)
+BUSMPU_MASTER_SRC(FE, 0b0000001, 0b0, cm_nr_Cm_nr, "Wesley Fang", NL1_MPC_Api_Drv_Cm_Handle_Error_Irq)
+#endif
+#if (defined(__NR_RAT__)||defined(__LTE_RAT__)) && defined(__MTK_TARGET__)
+// BUSMPU_MASTER_SRC(FE, 0b0000010, 0b0, rxtfc_nr_Rxtfc_nr, "Leo Wu", nr_rxtfc_init)
+// BUSMPU_MASTER_SRC(FE, 0b0000011, 0b0, rxtdb_nr_Rxtdb_nr, "Leo Wu", nr_rxtfc_init)
+#endif
+#if !defined(__MAUI_BASIC__)
+// Confirmed with owner that the SW is migrated from Shaolin to DSP MCORE.
+// BUSMPU_MASTER_SRC(FE, 0b0000100, 0b0, tx_nr_Txnr_cc0, "Cheng-Long Wu", NL1_TX_MCU_Api_Init)
+// BUSMPU_MASTER_SRC(FE, 0b0001100, 0b0, tx_nr_Txnr_cc1, "Cheng-Long Wu", NL1_TX_MCU_Api_Init)
+#endif
+BUSMPU_MASTER_END(FE)
+
+BUSMPU_MASTER_BEGIN(BIGRAM0,0x400)
+BUSMPU_MASTER_SRC(BIGRAM0, 0b001, 0b0, Bigramsys_0_br_dma, "TBD", drv_iocu_lisr/*TBD*/)
+BUSMPU_MASTER_END(BIGRAM0)
+
+BUSMPU_MASTER_BEGIN(RXBRP0,0x500)
+#if defined(__IS_EL1D_CONFIG_BUS_PRE_FETCH__)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00000, 0b0, brp0_harq_r, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00100, 0b0, brp0_harq_r1, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00001, 0b0, brp0_harq_w, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00101, 0b0, brp0_harq_w1, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00111, 0b0, brp0_tbo, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00011, 0b0, brp0_vtb, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+#endif
+BUSMPU_MASTER_END(RXBRP0)
+
+BUSMPU_MASTER_BEGIN(ABM,0x600)
+BUSMPU_MASTER_SRC(ABM, 0b001, 0b0, Shaolin_ABM0, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b011, 0b0, Shaolin_ABM1, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b101, 0b0, Shaolin_ABM2, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b111, 0b0, Shaolin_ABM3, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b000, 0b0, IA_ABM0, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b010, 0b0, IA_ABM1, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b100, 0b0, IA_ABM2, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b110, 0b0, IA_ABM3, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_END(ABM)
+
+BUSMPU_MASTER_BEGIN(LOG_TOP_MCU,0x700)
+#if defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(LOG_TOP_MCU, 0b000, 0b0, log_top_mcu_normal, "Guan-Ren Chen", logseq_drv_init)
+BUSMPU_MASTER_SRC(LOG_TOP_MCU, 0b101, 0b0, log_top_mcu_onemand, "Guan-Ren Chen", logseq_drv_init)
+#endif
+BUSMPU_MASTER_END(LOG_TOP_MCU)
+
+BUSMPU_MASTER_BEGIN(LOG_TOP_DSP4G,0x800)
+#if defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP4G, 0b000, 0b0, log_top_dsp4g_normal, "Guan-Ren Chen", logseq_drv_init)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP4G, 0b101, 0b0, log_top_dsp4g_onemand, "Guan-Ren Chen", logseq_drv_init)
+#endif
+BUSMPU_MASTER_END(LOG_TOP_DSP4G)
+
+BUSMPU_MASTER_BEGIN(LOG_TOP_DSP5G,0x900)
+#if defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP5G, 0b000, 0b0, log_top_dsp5g_normal, "Guan-Ren Chen", logseq_drv_init)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP5G, 0b101, 0b0, log_top_dsp5g_onemand, "Guan-Ren Chen", logseq_drv_init)
+#endif
+BUSMPU_MASTER_END(LOG_TOP_DSP5G)
+
+BUSMPU_MASTER_BEGIN(TRACE_TOP,0x1000)
+#if defined(__SCC_SIB_SUPPORT__)
+BUSMPU_MASTER_SRC(TRACE_TOP, 0b00, 0b0, trace_top, "Globe.Yan", drv_tracetop_capture_start_EMI)
+#endif
+BUSMPU_MASTER_END(TRACE_TOP)
+
+BUSMPU_MASTER_BEGIN(PPPHA,0x1100)
+#if defined(__MTK_TARGET__) && defined(__CDMA2000_RAT__)
+BUSMPU_MASTER_SRC(PPPHA, 0b0, 0b0, pppha, "Stun Wu", HlpPppHaRegInit)
+#endif
+BUSMPU_MASTER_END(PPPHA)
+
+BUSMPU_MASTER_BEGIN(GDMA,0x1200)
+BUSMPU_MASTER_SRC(GDMA, 0b0000, 0b0, channel_0, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0001, 0b0, channel_1, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0010, 0b0, channel_2, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0011, 0b0, channel_3, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0100, 0b0, channel_4, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0101, 0b0, channel_5, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0110, 0b0, channel_6, "Minni.Li", drv_gdma_set_config)
+
+BUSMPU_MASTER_SRC(GDMA, 0b1000, 0b0, channel_8, "Bernie.chang", L1sim_Cmd_Layer_MTK)
+BUSMPU_MASTER_SRC(GDMA, 0b1001, 0b0, channel_9, "Bernie.chang", L1sim_Cmd_Layer_MTK)
+
+BUSMPU_MASTER_SRC(GDMA, 0b1010, 0b0, channel_10, "Yao.Xue", UART_DriverInit )
+BUSMPU_MASTER_SRC(GDMA, 0b1011, 0b0, channel_11, "Yao.Xue", UART_DriverInit )
+BUSMPU_MASTER_END(GDMA)
+
+
+/* master_name
+*/
+BUSMPU_MASTER(NRL2)
+BUSMPU_MASTER(RXDBRP_NR)
+BUSMPU_MASTER(MCORE)
+BUSMPU_MASTER(FE)
+BUSMPU_MASTER(BIGRAM0)
+BUSMPU_MASTER(RXBRP0)
+// BUSMPU_MASTER(BIGRAM1)
+// BUSMPU_MASTER(RXBRP1)
+BUSMPU_MASTER(ABM)
+BUSMPU_MASTER(LOG_TOP_MCU)
+BUSMPU_MASTER(LOG_TOP_DSP4G)
+BUSMPU_MASTER(LOG_TOP_DSP5G)
+BUSMPU_MASTER(TRACE_TOP)
+BUSMPU_MASTER(PPPHA)
+// BUSMPU_MASTER(IPSEC)
+BUSMPU_MASTER(GDMA)
+// BUSMPU_MASTER(DBGSYS)
+// BUSMPU_MASTER(AP)