[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h
new file mode 100644
index 0000000..3c3b11f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h
@@ -0,0 +1,173 @@
+#ifndef __GEN97_BUSMPU_H__
+#define __GEN97_BUSMPU_H__
+
+#if defined(MT6297) || defined(CHIP10992)
+#define EMIMPU_MD2AP_INFODUMP_ENABLE
+#endif
+
+/*****************************************************************************
+ * Symbol/Type Definition *
+ *****************************************************************************/
+typedef kal_uint32 FIELD;
+
+/**
+ * 0x00 : MPU_IOCU_CTRL
+ */
+typedef union {
+ struct {
+ FIELD reg_mpu_iocu_disable : 1; //default:1 (RW)
+ FIELD reg_mpu_iocu_bank2_default_pms : 2; //default:3 (RW)
+ FIELD reg_mpu_iocu_bank3_default_pms : 2; //default:3 (RW)
+ FIELD reg_mpu_iocu_bank9f_default_pms : 2; //default:3 (RW)
+ FIELD reg_mpu_iocu_err_trig_mode : 1; //default:0 (RW)
+ FIELD reg_mpu_iocu_vio_clr : 1; //default:0 (W1C)
+ FIELD reg_mpu_iocu_vio_info_clr : 1; //default:0 (W1C)
+ FIELD reg_mpu_iocu_int_en : 1; //default:1 (RW)
+ FIELD reg_mpu_iocu_align_int_en : 1; //default:0 (RW)
+ FIELD reg_mpu_ctrl_update : 1; //default:0 (WP)
+ FIELD reg_mpu_algin_rule_sel : 1; //default:0 (RW)
+ FIELD reg_mpu_iocu_int_msk : 1; //default:1 (RW)
+ FIELD reg_mpu_unused : 16;
+ FIELD reg_speed_sim : 1; //default:0 (RW)
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_ctrl, *pbusmpu_iocu_ctrl;
+
+/**
+ * 0x04 : MPU_IOCU_IRQ_STS
+ */
+typedef union {
+ struct {
+ FIELD o_vio_mpu_iocu_wt : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_rd : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_wt_align : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_rd_align : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_int_status : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_id : 12;//default:0 (RU)
+ FIELD o_vio_mpu_iocu_ro : 1; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_region : 5; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_burst : 2; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_size : 3; //default:0 (RU)
+ FIELD o_vio_mpu_iocu_len : 4; //default:0 (RU)
+ } Bits;
+ FIELD Raw;
+} busmpu_irq_status, *pbusmpu_irq_status;
+
+/**
+ * 0x8 : MPU_IOCU_VIO_ADDR
+ */
+typedef union {
+ struct {
+ FIELD iocu_vio_addr : 32; //default:0 (RU)
+ } Bits;
+ FIELD Raw;
+} busmpu_iocu_vio_addr, *pbusmpu_iocu_vio_addr;
+
+typedef struct {
+ busmpu_iocu_vio_addr addr;
+} busmpu_iocu_vio_data, busmpu_mdinfra_error_info_st;
+
+typedef volatile struct {
+ busmpu_iocu_ctrl iocu_ctrl; // 0000
+} busmpu_reg, *pbusmpu_reg;
+
+typedef struct{
+ kal_uint32 axi_id;
+ kal_uint32 port_id;
+ kal_uint32 vio_addr;
+ kal_uint32 wt_vio;
+ kal_uint32 rd_vio;
+} emimpu_vio_info_debug;
+
+
+typedef struct{
+ kal_uint32 mpus;
+ kal_uint32 mput;
+ kal_uint32 mput_2;
+ emimpu_vio_info_debug emimpu_info_debug;
+} emimpu_vio_info;
+
+//init RMPU & busmpu @HWDInitialization
+extern void rmpu_md_init(void);
+
+//dump busmpu info called by exception handler
+extern kal_bool busmpu_mdinfra_dump_err(void);
+extern kal_bool busmpu_dump_irq_sts(void);
+extern volatile busmpu_iocu_vio_data busmpu_iocu_err;
+extern volatile busmpu_irq_status busmpu_irq_sts;
+#if defined(EMIMPU_MD2AP_INFODUMP_ENABLE)
+extern volatile emimpu_vio_info emimpu_vio_dump;
+#endif
+
+//for bank2 wb
+extern void busmpu_wb_permission(kal_uint32 start_addr, kal_uint32 end_addr, kal_uint32 mask_filter, kal_uint32 busid);
+
+//bank2
+extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+
+//bank3
+extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+#endif /*__GEN97_BUSMPU_H__*/
+