[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/devdrv/cirq/dummy.txt.txt b/mcu/interface/driver/devdrv/cirq/dummy.txt.txt
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+++ b/mcu/interface/driver/devdrv/cirq/dummy.txt.txt
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl.h
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@@ -0,0 +1,909 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+
+#if defined(MT6763)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6763.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6763 MDSYS."
+#endif
+#endif
+
+#if defined(MT6739)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6739.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6739 MDSYS."
+#endif
+#endif
+
+#if defined(MT6771)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6771.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6771 MDSYS."
+#endif
+#endif
+
+#if defined(MT6765)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6765.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6765 MDSYS."
+#endif
+#endif
+
+#if defined(MT6761)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6761.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6761 MDSYS."
+#endif
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+
+#define EDGE_SENSITIVE KAL_TRUE
+#define LEVEL_SENSITIVE KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+ kal_uint32 irq_mask[8];
+} CIRQ_MASK_VALUE_T;
+
+typedef struct MIPSGIC_IRQ_MASK_VALUE_STRUCT
+{
+#if defined(__MIPSGIC_MASK_REG_NR_2_NEW__)
+ kal_uint32 irq_mask0;
+ kal_uint32 irq_mask1;
+#else
+ kal_uint32 irq_maskl;
+ kal_uint32 irq_maskh;
+#endif
+} MIPSGIC_IRQ_MASK_VALUE_T;
+
+typedef struct MIPSGIC_IRQ_SEN_VALUE_STRUCT
+{
+#if defined(__MIPSGIC_MASK_REG_NR_2_NEW__)
+ kal_uint32 irq_sen0;
+ kal_uint32 irq_sen1;
+#else
+ kal_uint32 irq_maskl;
+ kal_uint32 irq_maskh;
+#endif
+} MIPSGIC_IRQ_SEN_VALUE_T;
+
+
+/* To enable SW Trigger Interrupt for new BB chips
+ Need to modify 3 files
+ 1. add a file intrCtrl_MTxxxx_SW_Handler.h
+ 2. add an entry on intrCtrl_SW_Handler.h
+ 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+ SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern const kal_uint8 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a) (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint8);
+extern void MDCIRQ_IRQMask(kal_uint8);
+extern void MDCIRQ_IRQUnmask(kal_uint8);
+extern void MDCIRQ_IRQSensitivity(kal_uint8, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint8 code);
+extern kal_uint32 IRQ_Status(void);
+extern kal_bool MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(kal_uint32 VPE, kal_uint32 code);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+ MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+//extern void IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+extern void initVPEIRQ(void);
+
+#if !defined(__SINGLE_CORE__)
+extern kal_uint32 sst_dhl_irq_count[4];
+extern kal_uint32 sst_dhl_irq_caller[4];
+extern kal_uint32 DHLIrqCounter[4];
+#else
+extern kal_uint32 sst_dhl_irq_count[2];
+extern kal_uint32 sst_dhl_irq_caller[2];
+extern kal_uint32 DHLIrqCounter[2];
+#endif
+extern kal_int32 INC_Initialize_State;
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+//#define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && defined(__MIPS_IA__)
+#if defined(__NESTED_DI_CHECK__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ kal_uint32 vpe_num = 0;\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+ vpe_num = miu_get_current_vpe_id();\
+ sst_dhl_irq_count[vpe_num]++;\
+ sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+ DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS.h
new file mode 100644
index 0000000..1973c88
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS.h
@@ -0,0 +1,896 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_ELBRUS.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_ELBRUS_H__
+#define __INTRCTRL_ELBRUS_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (256)
+
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDINFRA_BUSMON_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_LMAC_RAR_CODE MD_IRQID_LMAC_RAR
+#define IRQ_LMAC_EAR_CODE MD_IRQID_LMAC_EAR
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+//#define IRQ_NFI_CODE MD_IRQID_NFI
+#define IRQ_L2COPRO_CODE MD_IRQID_L2COPRO
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_MDMCU_BUSMON_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_I2C_0_CODE MD_IRQID_I2C_0
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_UART_MD2_CODE MD_IRQID_UART_MD2
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TOPSM_CODE MD_IRQID_TOPSM
+#define IRQ_DEM_TRIG_PS_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_C2K_ST_SLOT_CODE MD_IRQID_C2K_ST_SLOT_INT
+#define IRQ_C2K_ST_HALF_SLOT_CODE MD_IRQID_C2K_ST_HALF_SLOT_INT
+#define IRQ_C2K_MPDU_CODE MD_IRQID_C2K_MPDU_INT
+#define IRQ_C2K_M2C_DAT_WRDY_CODE MD_IRQID_C2K_M2C_DAT_WRDY_INT
+#define IRQ_C2K_M2C_CTL_WRDY_CODE MD_IRQID_C2K_M2C_CTL_WRDY_INT
+#define IRQ_C2K_M2C_FST_WRDY_CODE MD_IRQID_C2K_M2C_FST_WRDY_INT
+#define IRQ_C2K_NIRQ_CODE MD_IRQID_C2K_NIRQ
+//#define IRQ_PMU_CODE MD_IRQID_PMU
+#define IRQ_ECT_CODE MD_IRQID_ECT
+//#define IRQ_PS_L1_WDT_CODE MD_IRQID_PS_L1_WDT_INT
+#define IRQ_PTP_THERM_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_ABM_CODE MD_IRQID_MDINFRA_ABM_INT
+#define IRQ_MDLITE_GPTM_CODE MD_IRQID_MDLITE_GPTM_INT
+#define IRQ_AP2MD_PCCIF_CODE MD_IRQID_AP2MD_PCCIF_IRQ
+#define IRQ_PCCIF_AP_MD_CODE MD_IRQID_PCCIF_AP_MD
+#define IRQ_CCIF2_MD_CODE MD_IRQID_CCIF2_MD_IRQ
+#define IRQ_CCIF2_MD_EVENT_CODE MD_IRQID_CCIF2_MD_EVENT
+//#define IRQ_SPI_CODE MD_IRQID_SPI
+#define IRQ_MDINFRA_ABM_ERROR_CODE MD_IRQID_MDINFRA_ABM_ERROR_INT
+#define IRQ_USB3_CODE MD_IRQID_USB3
+//#define IRQ_SDIO_CODE MD_IRQID_SDIO
+#define IRQ_MSDC0_CODE MD_IRQID_MSDC0
+#define IRQ_EHPI0_CODE MD_IRQID_EHPI0
+//#define IRQ_RTC_CODE MD_IRQID_RTC
+//#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_MSDC1_CODE MD_IRQID_MSDC1
+//#define IRQ_PFC_LV_CODE MD_IRQID_PFC_INT_LV
+//#define IRQ_AUXACD_CODE MD_IRQID_AUXACD
+//#define IRQ_LED_CODE MD_IRQID_LED
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_ELMTOP_IOCU_CODE MD_IRQID_ELMTOP_IOCU_IRQ
+#define IRQ_ELMTOP_EMI_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ULSR_CODE MD_IRQID_ULS_INTR
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_SHARE_D12MINT2_CODE MD_IRQID_SHARE_D12MINT2
+#define IRQ_SHARE_D12MINT3_CODE MD_IRQID_SHARE_D12MINT3
+//#define IRQ_LTE_TIMER_EMAC_SF_TICK_CODE MD_IRQID_LTE_TIMER_EMAC_SF_TICK
+#define IRQ_IRDBG_MCU_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_LTE_MODEMSYS_TRACE_CODE MD_IRQID_LTE_MODEMSYS_TRACE_IRQ
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_L1SYS_SLV_DECERR_LEVEL_CODE MD_IRQ_ID_L1SYS_SLV_DECERR_IRQ_LEVEL
+#define IRQ_ABM_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MO_WERR_CODE MD_IRQID_MO_WERR_INT
+#define IRQ_BC_CODE MD_IRQID_BC_IRQ
+#define IRQ_UEA_UIA_CODE MD_IRQID_UEA_UIA_IRQ
+#define IRQ_UPA_ACC_CODE MD_IRQID_UPA_ACC_IRQ
+#define IRQ_DPA_ACC_CODE MD_IRQID_DPA_ACC_IRQ
+#define IRQ_C2K_MD_0_CODE MD_IRQID_C2K_MD_INT_0
+#define IRQ_C2K_MD_1_CODE MD_IRQID_C2K_MD_INT_1
+#define IRQ_C2K_MD_2_CODE MD_IRQID_C2K_MD_INT_2
+#define IRQ_C2K_MD_3_CODE MD_IRQID_C2K_MD_INT_3
+#define IRQ_C2K_L1_0_CODE MD_IRQID_C2K_L1_INT_0
+#define IRQ_C2K_L1_1_CODE MD_IRQID_C2K_L1_INT_1
+#define IRQ_C2K_L1_2_CODE MD_IRQID_C2K_L1_INT_2
+#define IRQ_C2K_L1_3_CODE MD_IRQID_C2K_L1_INT_3
+#define IRQ_C2K_L1_4_CODE MD_IRQID_C2K_L1_INT_4
+#define IRQ_C2K_L1_5_CODE MD_IRQID_C2K_L1_INT_5
+#define IRQ_C2K_L1_6_CODE MD_IRQID_C2K_L1_INT_6
+#define IRQ_C2K_L1_7_CODE MD_IRQID_C2K_L1_INT_7
+#define IRQ_PB0_PM_CNTRSAT_0_CODE MD_IRQID_PB0_PM_CNTRSAT_INT_0
+#define IRQ_PB0_PM_CNTRSAT_1_CODE MD_IRQID_PB0_PM_CNTRSAT_INT_1
+#define IRQ_PB1_PM_CNTRSAT_0_CODE MD_IRQID_PB1_PM_CNTRSAT_INT_0
+#define IRQ_PB1_PM_CNTRSAT_1_CODE MD_IRQID_PB1_PM_CNTRSAT_INT_1
+#define IRQ_PB2_PM_CNTRSAT_0_CODE MD_IRQID_PB2_PM_CNTRSAT_INT_0
+#define IRQ_PB2_PM_CNTRSAT_1_CODE MD_IRQID_PB2_PM_CNTRSAT_INT_1
+#define IRQ_PB3_PM_CNTRSAT_0_CODE MD_IRQID_PB3_PM_CNTRSAT_INT_0
+#define IRQ_PB3_PM_CNTRSAT_1_CODE MD_IRQID_PB3_PM_CNTRSAT_INT_1
+#define IRQ_PTP_FSM_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_PTP_SLPCTL_EVENT_CODE MD_IRQID_PTP_SLPCTL_EVENT
+#define IRQ_PCCIF_MDMCU0_CODE MD_IRQID_PCCIF_MDMCU0_IRQ
+#define IRQ_PCCIF_MDMCU1_CODE MD_IRQID_PCCIF_MDMCU1_IRQ
+#define IRQ_ELM_DMA_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_ELM_L1_CODE MD_IRQID_ELM_L1_IRQ
+#define IRQ_MDCIRQ_LV_CODE MD_IRQID_MDCIRQ_IRQ_LV
+#define IRQ_LOGGDMA0_LV_CODE MD_IRQID_LOGGDMA_IRQ0_LV
+#define IRQ_SOE_LV_CODE MD_IRQID_SOE_INT_LV
+#define IRQ_TRACE_CODE MD_IRQID_TRACE_INT
+#define IRQ_SPM2MD_DVFS_MDPERISYS_CODE MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDMCU_MACRO_BUS_CODE MD_IRQID_MDMCU_MACRO_BUS_INT
+#define IRQ_MDMCU_PERI_BUS_CODE MD_IRQID_MDMCU_PERI_BUS_INT
+#define IRQ_MM_WERR_CODE MD_IRQID_MM_WERR_INT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_DCXO_RDY_WO_ACK_CODE MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define IRQ_PLL_REQ_WO_DCXO_CODE MD_IRQID_PLL_REQ_WO_DCXO_IRQ
+#define IRQ_TOP_PLL_DSNS_CODE MD_IRQID_TOP_PLL_DSNS_IRQ
+#define IRQ_BRP_BRP_CMIF_M2C_0_CODE MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_0
+#define IRQ_BRP_BRP_CMIF_M2C_1_CODE MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_1
+#define IRQ_BRP_BRP_CMIF_M2C_2_CODE MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_2
+#define IRQ_CMP_CMTDB_CODE MD_IRQID_CMP_CMTDB_IRQ
+#define IRQ_CS_SRAM_CTRL_CODE MD_IRQID_CS_SRAM_CTRL_IRQ
+#define IRQ_CSTXB_FDD_CS_CODE MD_IRQID_CSTXB_FDD_CS_IRQ
+#define IRQ_CSTXB_TDD_CS_CODE MD_IRQID_CSTXB_TDD_CS_IRQ
+#define IRQ_DFE0_CMIF_M2C_0_CODE MD_IRQID_DFE0_CMIF_M2C_IRQ_0
+#define IRQ_DFE0_CMIF_M2C_1_CODE MD_IRQID_DFE0_CMIF_M2C_IRQ_1
+#define IRQ_DFE0_CMIF_M2C_2_CODE MD_IRQID_DFE0_CMIF_M2C_IRQ_2
+#define IRQ_DFE0_PCC_TOP_0_FULL_CODE MD_IRQID_DFE0_PCC_TOP_0_FULL_IRQ
+#define IRQ_DFE0_PCC_TOP_1_FULL_CODE MD_IRQID_DFE0_PCC_TOP_1_FULL_IRQ
+#define IRQ_DFE0_RXDFEIF_L_CODE MD_IRQID_DFE0_RXDFEIF_L_IRQ
+#define IRQ_DFE0_TCU_L1D_1_CODE MD_IRQID_DFE0_TCU_L1D_1_IRQ
+#define IRQ_DFE0_TCU_L1D_2_CODE MD_IRQID_DFE0_TCU_L1D_2_IRQ
+#define IRQ_DFE1_CMIF_M2C_0_CODE MD_IRQID_DFE1_CMIF_M2C_IRQ_0
+#define IRQ_DFE1_CMIF_M2C_1_CODE MD_IRQID_DFE1_CMIF_M2C_IRQ_1
+#define IRQ_DFE1_CMIF_M2C_2_CODE MD_IRQID_DFE1_CMIF_M2C_IRQ_2
+#define IRQ_DFE1_PCC_TOP_0_FULL_CODE MD_IRQID_DFE1_PCC_TOP_0_FULL_IRQ
+#define IRQ_DFE1_PCC_TOP_1_FULL_CODE MD_IRQID_DFE1_PCC_TOP_1_FULL_IRQ
+#define IRQ_DFE1_RXDFEIF_L_CODE MD_IRQID_DFE1_RXDFEIF_L_IRQ
+#define IRQ_L1GDMA_CODE MD_IRQID_GDMA_IRQ
+#define IRQ_ICC_DSP_0_CODE MD_IRQID_ICC_DSP_IRQ_0
+#define IRQ_ICC_DSP_1_CODE MD_IRQID_ICC_DSP_IRQ_1
+#define IRQ_ICC_SRAM_CTRL_CODE MD_IRQID_ICC_SRAM_CTRL_IRQ
+#define IRQ_IDC_PM_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_IMC_DSP_0_CODE MD_IRQID_IMC_DSP_IRQ_0
+#define IRQ_IMC_DSP_1_CODE MD_IRQID_IMC_DSP_IRQ_1
+#define IRQ_IMC_MMU_0_CODE MD_IRQID_IMC_MMU_IRQ_0
+#define IRQ_IMC_MMU_1_CODE MD_IRQID_IMC_MMU_IRQ_1
+#define IRQ_IMC_RXDMP_CODE MD_IRQID_IMC_RXDMP_IRQ
+#define IRQ_IMC_RXTDB_CODE MD_IRQID_IMC_RXTDB_IRQ
+#define IRQ_IMC_SRAM_CTRL_CODE MD_IRQID_IMC_SRAM_CTRL_IRQ
+#define IRQ_INR_RAKE_CMIF_M2C_0_CODE MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_INR_RAKE_CMIF_M2C_1_CODE MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_INR_TD1_BRP_DMA_CODE MD_IRQID_INR_TD1_BRP_DMA_IRQ
+#define IRQ_INR_TD1_CSCE_CODE MD_IRQID_INR_TD1_CSCE_IRQ
+#define IRQ_INR_TD1_DFE_BRG_CODE MD_IRQID_INR_TD1_DFE_BRG_IRQ
+#define IRQ_INR_TD1_JDA_CODE MD_IRQID_INR_TD1_JDA_IRQ
+#define IRQ_INR_TD1_PP_CODE MD_IRQID_INR_TD1_PP_IRQ
+#define IRQ_INR_TD2_BRP_DMA_CODE MD_IRQID_INR_TD2_BRP_DMA_IRQ
+#define IRQ_INR_TD2_CSCE_CODE MD_IRQID_INR_TD2_CSCE_IRQ
+#define IRQ_INR_TD2_DFE_BRG_CODE MD_IRQID_INR_TD2_DFE_BRG_IRQ
+#define IRQ_INR_TD2_JDA_CODE MD_IRQID_INR_TD2_JDA_IRQ
+#define IRQ_TD2_PP_CODE MD_IRQID_TD2_PP_IRQ
+#define IRQ_L1_LTE_SLEEP_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_LTEL1_CS_CODE MD_IRQID_LTEL1_CS_IRQ
+#define IRQ_LTXB0_BSI_L_AB_CODE MD_IRQID_LTXB0_BSI_L_AB_IRQ
+#define IRQ_LTXB0_BSI_L_C_CODE MD_IRQID_LTXB0_BSI_L_C_IRQ
+#define IRQ_LTXB0_BSI_L_D_CODE MD_IRQID_LTXB0_BSI_L_D_IRQ
+#define IRQ_LTXB0_TXENC_ERROR_CODE MD_IRQID_LTXB0_TXENC_ERROR_IRQ
+#define IRQ_LTXB1_BSI_L_AB_CODE MD_IRQID_LTXB1_BSI_L_AB_IRQ
+#define IRQ_LTXB1_BSI_L_C_CODE MD_IRQID_LTXB1_BSI_L_C_IRQ
+#define IRQ_LTXB1_BSI_L_D_CODE MD_IRQID_LTXB1_BSI_L_D_IRQ
+#define IRQ_LTXB1_TXENC_ERROR_CODE MD_IRQID_LTXB1_TXENC_ERROR_IRQ
+#define IRQ_MMU_SRAM_CTRL_CODE MD_IRQID_MMU_SRAM_CTRL_IRQ
+#define IRQ_MPC_DSP_0_CODE MD_IRQID_MPC_DSP_IRQ_0
+#define IRQ_MPC_DSP_1_CODE MD_IRQID_MPC_DSP_IRQ_1
+#define IRQ_MPC_SRAM_CTRL_CODE MD_IRQID_MPC_SRAM_CTRL_IRQ
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_L1_LTE_WAKEUP_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_FREQM_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDL1_TOPSM_CODE MD_IRQID_MDL1_TOPSM_IRQ
+#define IRQ_RTR_FRAME_CODE MD_IRQID_RTR_FRAME_IRQ
+#define IRQ_RTR_SLT_CODE MD_IRQID_RTR_SLT_IRQ
+#define IRQ_WTIMER_CODE MD_IRQID_WTIMER_IRQ
+#define IRQ_TDD_WAKEUP_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDMA_WAKEUP_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_MODEML1_DVFS_CODE MD_IRQID_MODEML1_DVFS_IRQ
+#define IRQ_MODEML1_DVFS_MIPS_DVS_CODE MD_IRQID_MODEML1_DVFS_MIPS_DVS_IRQ
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_RESERVED_FOR_CC_IRQ_0_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_0
+#define IRQ_RESERVED_FOR_CC_IRQ_1_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_1
+#define IRQ_RESERVED_FOR_CC_IRQ_2_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_2
+#define IRQ_RESERVED_FOR_CC_IRQ_3_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_3
+#define IRQ_RESERVED_FOR_CC_IRQ_4_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_4
+#define IRQ_RESERVED_FOR_CC_IRQ_5_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_5
+#define IRQ_RESERVED_FOR_CC_IRQ_6_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_6
+#define IRQ_RESERVED_FOR_CC_IRQ_7_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_7
+#define IRQ_RESERVED_FOR_CC_IRQ_8_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_8
+#define IRQ_RESERVED_FOR_CC_IRQ_9_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_9
+#define IRQ_RESERVED_FOR_CC_IRQ_10_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_10
+#define IRQ_RESERVED_FOR_CC_IRQ_11_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_11
+#define IRQ_RESERVED_FOR_CC_IRQ_12_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_12
+#define IRQ_RESERVED_FOR_CC_IRQ_13_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_13
+#define IRQ_RESERVED_FOR_CC_IRQ_14_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_14
+#define IRQ_RESERVED_FOR_CC_IRQ_15_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_15
+#define IRQ_RESERVED_FOR_CC_IRQ_16_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_16
+#define IRQ_RESERVED_FOR_CC_IRQ_17_CODE MD_IRQID_RESERVED_FOR_CC_IRQ_17
+#define IRQ_L1_GPTM1_CODE MD_IRQID_L1_GPTM1
+#define IRQ_L1_GPTM2_CODE MD_IRQID_L1_GPTM2
+#define IRQ_L1_GPTM3_CODE MD_IRQID_L1_GPTM3
+#define IRQ_L1_GPTM4_CODE MD_IRQID_L1_GPTM4
+#define IRQ_L1_GPTM5_CODE MD_IRQID_L1_GPTM5
+#define IRQ_L1_GPTM6_CODE MD_IRQID_L1_GPTM6
+#define IRQ_L1LITE_GPTM_CODE MD_IRQID_L1LITE_GPTM_INT
+#define IRQ_PPC_CIRQ_CODE MD_IRQID_PPC_CIRQ
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/* 0 ~ 7 */ 127, 6, 127, 11, 127, 7, 127, 127, \
+/* 8 ~ 15 */ 127, 127, 127, 127, 127, 127, 127, 6, \
+/* 16 ~ 23 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 32 ~ 39 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 40 ~ 47 */ 127, 7, 7, 6, 127, 7, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 56 ~ 63 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 64 ~ 71 */ 127, 127, 127, 127, 127, 127, 73, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */ 81, 80, 83, 82, 127, 127, 127, 127, \
+/* 88 ~ 95 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 96 ~103 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*104 ~111 */ 79, 7, 127, 127, 127, 127, 127, 127, \
+/*112 ~119 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*120 ~127 */ 127, 127, 127, 76, 58, 29, 60, 6, \
+/*128 ~135 */ 38, 32, 62, 62, 62, 127, 127, 127, \
+/*136 ~143 */ 33, 33, 62, 62, 62, 127, 127, 127, \
+/*144 ~151 */ 127, 40, 6, 6, 127, 127, 36, 6, \
+/*152 ~159 */ 127, 127, 56, 60, 6, 75, 34, 43, \
+/*160 ~167 */ 34, 38, 44, 59, 43, 34, 38, 44, \
+/*168 ~175 */ 59, 54, 52, 53, 37, 37, 50, 46, \
+/*176 ~183 */ 48, 49, 50, 29, 57, 76, 77, 127, \
+/*184 ~191 */ 61, 76, 127, 127, 61, 6, 42, 6, \
+/*192 ~199 */ 6, 66, 67, 65, 28, 72, 71, 74, \
+/*200 ~207 */ 31, 26, 27, 63, 25, 7, 69, 68, \
+/*208 ~215 */ 70, 14, 15, 55, 69, 70, 127, 11, \
+/*216 ~223 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*224 ~231 */ 127, 53, 68, 6, 127, 127, 78, 64, \
+/*232 ~239 */ 78, 78, 68, 32, 47, 30, 13, 71, \
+/*240 ~247 */ 65, 65, 12, 11, 10, 25, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 14, 4, 5, 14, 0, 4, 10, \
+ /* 8 ~ 15 */ 10, 10, 10, 10, 10, 10, 10, 14, \
+ /* 16 ~ 23 */ 10, 10, 10, 16, 10, 10, 10, 0, \
+ /* 24 ~ 31 */ 7, 10, 10, 10, 10, 10, 0, 0, \
+ /* 32 ~ 39 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+ /* 40 ~ 47 */ 10, 2, 4, 14, 10, 0, 10, 0, \
+ /* 48 ~ 55 */ 10, 10, 10, 10, 10, 10, 0, 10, \
+ /* 56 ~ 63 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+ /* 64 ~ 71 */ 10, 0, 10, 10, 10, 1, 0, 12, \
+ /* 72 ~ 79 */ 10, 10, 10, 10, 10, 0, 0, 10, \
+ /* 80 ~ 87 */ 4, 4, 4, 4, 0, 0, 10, 10, \
+ /* 88 ~ 95 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+ /* 96 ~103 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+ /*104 ~111 */ 0, 0, 10, 7, 10, 10, 10, 10, \
+ /*112 ~119 */ 10, 0, 10, 10, 10, 10, 10, 13, \
+ /*120 ~127 */ 10, 10, 10, 1, 1, 10, 10, 14, \
+ /*128 ~135 */ 1, 10, 1, 0, 0, 0, 0, 10, \
+ /*136 ~143 */ 10, 10, 1, 0, 0, 0, 0, 10, \
+ /*144 ~151 */ 10, 3, 14, 14, 10, 10, 3, 14, \
+ /*152 ~159 */ 10, 10, 10, 10, 14, 1, 1, 10, \
+ /*160 ~167 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+ /*168 ~175 */ 10, 3, 1, 3, 1, 1, 3, 5, \
+ /*176 ~183 */ 1, 1, 3, 1, 0, 10, 10, 10, \
+ /*184 ~191 */ 1, 10, 10, 10, 1, 14, 1, 14, \
+ /*192 ~199 */ 14, 1, 1, 1, 3, 0, 0, 1, \
+ /*200 ~207 */ 1, 1, 10, 1, 0, 1, 1, 1, \
+ /*208 ~215 */ 1, 5, 5, 1, 1, 1, 10, 5, \
+ /*216 ~223 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /*224 ~231 */ 7, 15, 1, 13, 1, 13, 0, 0, \
+ /*232 ~239 */ 0, 0, 1, 1, 1, 1, 4, 4, \
+ /*240 ~247 */ 5, 5, 5, 5, 5, 4, 10, 10, \
+ /*248 ~255 */ 7, 7, 10, 10, 10, 10, 10, 0,
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD, \
+ 0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD, \
+ 0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD, \
+ 0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFE, \
+ /* Group1(1) */ 0xFD, \
+ /* Group2(2) */ 0xFB, \
+ /* Group3(3) */ 0xF7, \
+ /* Group4(4) */ 0xEF, \
+ /* Group5(5) */ 0xDF, \
+ /* Group6(6) */ 0xBF, \
+ /* Group7(7) */ 0x7F, \
+ /* Group8(0,2) */ 0xFA, \
+ /* Group9(0,2,4) */ 0xEA, \
+ /* Group10(0,2,4,6) */ 0xAA, \
+ /* Group11(0,4) */ 0xEE, \
+ /* Group12(0,6) */ 0xBE, \
+ /* Group13(0,1,2,3,4,5,6) */ 0x80, \
+ /* Group14(0,1,2,3,4,5,6,7)*/ 0x00, \
+ /* Group15(1,3) */ 0xF5, \
+ /* Group16(0,2,4,6,7) */ 0x2A, \
+ /* Group17 */ 0xFF, \
+ /* Group18 */ 0xFF, \
+ /* Group19 */ 0xFF, \
+ /* Group20 */ 0xFF, \
+ /* Group21 */ 0xFF, \
+ /* Group22 */ 0xFF, \
+ /* Group23 */ 0xFF, \
+ /* Group24 */ 0xFF, \
+ /* Group25 */ 0xFF, \
+ /* Group26 */ 0xFF, \
+ /* Group27 */ 0xFF, \
+ /* Group28 */ 0xFF, \
+ /* Group29 */ 0xFF, \
+ /* Group30 */ 0xFF, \
+ /* Group31 */ 0xFF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x00, \
+ /* Group1(1) */ 0xFF, \
+ /* Group2(2) */ 0xFF, \
+ /* Group3(3) */ 0xFF,
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0xE180807F, \
+ /* 32-63 */ 0x0040AE00, \
+ /* 64-95 */ 0x003FF0E2, \
+ /* 96-127 */ 0x98760B00, \
+ /* 128-159 */ 0x70CE7C7D, \
+ /* 160-191 */ 0xF11FFE00, \
+ /* 192-223 */ 0xFFBFFBFF, \
+ /* 224-255 */ 0x833FFFFF,
+
+#define INTERRUPT_TYPE \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00000000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+#define INTERRUPT_HRT_MT \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00063000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+ /* VPE0 */ 60,\
+ /* VPE1 */ 60,\
+ /* VPE2 */ 60,\
+ /* VPE3 */ 60,\
+ /* VPE4 */ 60,\
+ /* VPE5 */ 60,\
+ /* VPE6 */ 60,\
+ /* VPE7 */ 60,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+ #error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+#define __ENABLE_SWGIC_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+
+/*********************************************************************
+ GIC configuration
+**********************************************************************/
+#define NUM_GIC_SOURCES (64)
+
+#define GIC_OS_priority 0
+#define GIC_DUMMY_priority 1
+#define GIC_INT_priority 3
+#define GIC_INT_EX_priority 4
+#define GIC_NONE_priority 64
+
+#define GIC_IRQ_TYPE 0
+#define GIC_NMI_TYPE 1
+#define GIC_YQ_TYPE 2
+#define GIC_UNDEF_TYPE 3
+
+
+#define VPE0_NMI_CODE MD_GICID_VPE0NMI
+#define VPE1_NMI_CODE MD_GICID_VPE1NMI
+#define VPE2_NMI_CODE MD_GICID_VPE2NMI
+#define VPE3_NMI_CODE MD_GICID_VPE3NMI
+#define VPE4_NMI_CODE MD_GICID_VPE4NMI
+#define VPE5_NMI_CODE MD_GICID_VPE5NMI
+#define VPE6_NMI_CODE MD_GICID_VPE6NMI
+#define VPE7_NMI_CODE MD_GICID_VPE7NMI
+
+#define VPE0_OS_IPI_CODE MD_GICID_VPE0WEDGE
+#define VPE1_OS_IPI_CODE MD_GICID_VPE1WEDGE
+#define VPE2_OS_IPI_CODE MD_GICID_VPE2WEDGE
+#define VPE3_OS_IPI_CODE MD_GICID_VPE3WEDGE
+#define VPE4_OS_IPI_CODE MD_GICID_VPE4WEDGE
+#define VPE5_OS_IPI_CODE MD_GICID_VPE5WEDGE
+#define VPE6_OS_IPI_CODE MD_GICID_VPE6WEDGE
+#define VPE7_OS_IPI_CODE MD_GICID_VPE7WEDGE
+
+#define GICID_RESERVED0_CODE MD_GICID_RESERVED0
+#define GICID_RESERVED1_CODE MD_GICID_RESERVED1
+#define GICID_RESERVED2_CODE MD_GICID_RESERVED2
+#define GICID_RESERVED3_CODE MD_GICID_RESERVED3
+#define GICID_RESERVED4_CODE MD_GICID_RESERVED4
+#define GICID_RESERVED5_CODE MD_GICID_RESERVED5
+#define GICID_RESERVED6_CODE MD_GICID_RESERVED6
+#define GICID_RESERVED7_CODE MD_GICID_RESERVED7
+
+
+#define GIC_PRIORITY_LIST \
+/* 0 ~ 7 */ 3, 3, 3, 3, 3, 3, 3, 3, \
+/* 8 ~ 15 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+/* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* 24 ~ 31 */ 0, 1, 2, 3, 8, 9, 10, 11, \
+/* 32 ~ 39 */ 0, 1, 2, 3, 8, 9, 10, 11, \
+/* 40 ~ 47 */ 0, 1, 2, 3, 8, 9, 10, 11, \
+/* 48 ~ 55 */ 0, 1, 2, 3, 8, 9, 10, 11, \
+/* 56 ~ 63 */ 1, 1 , 1, 64, 64, 64, 64, 64, \
+
+#define GIC_TYPE_LIST \
+/* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* 8 ~ 15 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* 24 ~ 31 */ 2, 2, 2, 2, 2, 2, 2, 2, \
+/* 32 ~ 39 */ 2, 2, 2, 2, 2, 2, 2, 2, \
+/* 40 ~ 47 */ 2, 2, 2, 2, 2, 2, 2, 2, \
+/* 48 ~ 55 */ 2, 2, 2, 2, 2, 2, 2, 2, \
+/* 56 ~ 63 */ 0 , 0, 0, 3, 3, 3, 3, 3, \
+
+#define GIC_MAP2VPE_LIST \
+/* 0 ~ 7 */ 0, 1, 2, 3, 4, 5, 6, 7, \
+/* 8 ~ 15 */ 0, 1, 2, 3, 4, 5, 6, 7, \
+/* 16 ~ 23 */ 0, 1, 2, 3, 4, 5, 6, 7, \
+/* 24 ~ 31 */ 0, 0, 0, 0, 1, 1, 1, 1, \
+/* 32 ~ 39 */ 2, 2, 2, 2, 3, 3, 3, 3, \
+/* 40 ~ 47 */ 4, 4, 4, 4, 5, 5, 5, 5, \
+/* 48 ~ 55 */ 6, 6, 6, 6, 7, 7, 7, 7, \
+/* 56 ~ 63 */ 0, 2, 4, 8, 8, 8, 8, 8, \
+
+
+typedef enum
+{
+ VPE_STATUS_TASK_L = 0,
+ VPE_STATUS_TASK_H = 1,
+ VPE_STATUS_HISR = 2,
+ VPE_STATUS_LISR = 3,
+} VPE_STATUS;
+
+#if (MAX_GIC_NUM<=64)
+#define __MIPSGIC_MASK_REG_NR_2_NEW__
+#else
+ #error "Unsupport mask number"
+#endif
+
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_MDINFRA_BUSMON = IRQ_MDINFRA_BUSMON_CODE,
+ IRQ_LMAC_RAR = IRQ_LMAC_RAR_CODE,
+ IRQ_LMAC_EAR = IRQ_LMAC_EAR_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_L2COPRO = IRQ_L2COPRO_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_MDMCU_BUSMON = IRQ_MDMCU_BUSMON_CODE,
+ IRQ_I2C_0 = IRQ_I2C_0_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_UART_MD2 = IRQ_UART_MD2_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TOPSM = IRQ_TOPSM_CODE,
+ IRQ_DEM_TRIG_PS = IRQ_DEM_TRIG_PS_CODE,
+ IRQ_C2K_ST_SLOT = IRQ_C2K_ST_SLOT_CODE,
+ IRQ_C2K_ST_HALF_SLOT = IRQ_C2K_ST_HALF_SLOT_CODE,
+ IRQ_C2K_MPDU = IRQ_C2K_MPDU_CODE,
+ IRQ_C2K_M2C_DAT_WRDY = IRQ_C2K_M2C_DAT_WRDY_CODE,
+ IRQ_C2K_M2C_CTL_WRDY = IRQ_C2K_M2C_CTL_WRDY_CODE,
+ IRQ_C2K_M2C_FST_WRDY = IRQ_C2K_M2C_FST_WRDY_CODE,
+ IRQ_C2K_NIRQ = IRQ_C2K_NIRQ_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM = IRQ_PTP_THERM_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_ABM = IRQ_MDINFRA_ABM_CODE,
+ IRQ_MDLITE_GPTM = IRQ_MDLITE_GPTM_CODE,
+ IRQ_AP2MD_PCCIF = IRQ_AP2MD_PCCIF_CODE,
+ IRQ_PCCIF_AP_MD = IRQ_PCCIF_AP_MD_CODE,
+ IRQ_CCIF2_MD = IRQ_CCIF2_MD_CODE,
+ IRQ_CCIF2_MD_EVENT = IRQ_CCIF2_MD_EVENT_CODE,
+ IRQ_MDINFRA_ABM_ERROR = IRQ_MDINFRA_ABM_ERROR_CODE,
+ IRQ_USB3 = IRQ_USB3_CODE,
+ IRQ_MSDC0 = IRQ_MSDC0_CODE,
+ IRQ_EHPI0 = IRQ_EHPI0_CODE,
+ IRQ_MSDC1 = IRQ_MSDC1_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_ELMTOP_IOCU = IRQ_ELMTOP_IOCU_CODE,
+ IRQ_ELMTOP_EMI = IRQ_ELMTOP_EMI_CODE,
+ IRQ_ULSR = IRQ_ULSR_CODE,
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_SHARE_D12MINT2 = IRQ_SHARE_D12MINT2_CODE,
+ IRQ_SHARE_D12MINT3 = IRQ_SHARE_D12MINT3_CODE,
+ IRQ_IRDBG_MCU = IRQ_IRDBG_MCU_CODE,
+ IRQ_LTE_MODEMSYS_TRACE = IRQ_LTE_MODEMSYS_TRACE_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_L1SYS_SLV_DECERR_LEVEL = IRQ_L1SYS_SLV_DECERR_LEVEL_CODE,
+ IRQ_ABM = IRQ_ABM_CODE,
+ IRQ_ABM_ERROR = IRQ_ABM_ERROR_CODE,
+ IRQ_MO_WERR = IRQ_MO_WERR_CODE,
+ IRQ_BC = IRQ_BC_CODE,
+ IRQ_UEA_UIA = IRQ_UEA_UIA_CODE,
+ IRQ_UPA_ACC = IRQ_UPA_ACC_CODE,
+ IRQ_DPA_ACC = IRQ_DPA_ACC_CODE,
+ IRQ_C2K_MD_0 = IRQ_C2K_MD_0_CODE,
+ IRQ_C2K_MD_1 = IRQ_C2K_MD_1_CODE,
+ IRQ_C2K_MD_2 = IRQ_C2K_MD_2_CODE,
+ IRQ_C2K_MD_3 = IRQ_C2K_MD_3_CODE,
+ IRQ_C2K_L1_0 = IRQ_C2K_L1_0_CODE,
+ IRQ_C2K_L1_1 = IRQ_C2K_L1_1_CODE,
+ IRQ_C2K_L1_2 = IRQ_C2K_L1_2_CODE,
+ IRQ_C2K_L1_3 = IRQ_C2K_L1_3_CODE,
+ IRQ_C2K_L1_4 = IRQ_C2K_L1_4_CODE,
+ IRQ_C2K_L1_5 = IRQ_C2K_L1_5_CODE,
+ IRQ_C2K_L1_6 = IRQ_C2K_L1_6_CODE,
+ IRQ_C2K_L1_7 = IRQ_C2K_L1_7_CODE,
+ IRQ_PB0_PM_CNTRSAT_0 = IRQ_PB0_PM_CNTRSAT_0_CODE,
+ IRQ_PB0_PM_CNTRSAT_1 = IRQ_PB0_PM_CNTRSAT_1_CODE,
+ IRQ_PB1_PM_CNTRSAT_0 = IRQ_PB1_PM_CNTRSAT_0_CODE,
+ IRQ_PB1_PM_CNTRSAT_1 = IRQ_PB1_PM_CNTRSAT_1_CODE,
+ IRQ_PB2_PM_CNTRSAT_0 = IRQ_PB2_PM_CNTRSAT_0_CODE,
+ IRQ_PB2_PM_CNTRSAT_1 = IRQ_PB2_PM_CNTRSAT_1_CODE,
+ IRQ_PB3_PM_CNTRSAT_0 = IRQ_PB3_PM_CNTRSAT_0_CODE,
+ IRQ_PB3_PM_CNTRSAT_1 = IRQ_PB3_PM_CNTRSAT_1_CODE,
+ IRQ_PTP_FSM = IRQ_PTP_FSM_CODE,
+ IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+ IRQ_PCCIF_MDMCU0 = IRQ_PCCIF_MDMCU0_CODE,
+ IRQ_PCCIF_MDMCU1 = IRQ_PCCIF_MDMCU1_CODE,
+ IRQ_ELM_DMA = IRQ_ELM_DMA_CODE,
+ IRQ_ELM_L1 = IRQ_ELM_L1_CODE,
+ IRQ_MDCIRQ_LV = IRQ_MDCIRQ_LV_CODE,
+ IRQ_LOGGDMA0_LV = IRQ_LOGGDMA0_LV_CODE,
+ IRQ_SOE_LV = IRQ_SOE_LV_CODE,
+ IRQ_TRACE = IRQ_TRACE_CODE,
+ IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_MDMCU_MACRO_BUS = IRQ_MDMCU_MACRO_BUS_CODE,
+ IRQ_MDMCU_PERI_BUS = IRQ_MDMCU_PERI_BUS_CODE,
+ IRQ_MM_WERR = IRQ_MM_WERR_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_DCXO_RDY_WO_ACK = IRQ_DCXO_RDY_WO_ACK_CODE,
+ IRQ_PLL_REQ_WO_DCXO = IRQ_PLL_REQ_WO_DCXO_CODE,
+ IRQ_TOP_PLL_DSNS = IRQ_TOP_PLL_DSNS_CODE,
+ IRQ_BRP_BRP_CMIF_M2C_0 = IRQ_BRP_BRP_CMIF_M2C_0_CODE,
+ IRQ_BRP_BRP_CMIF_M2C_1 = IRQ_BRP_BRP_CMIF_M2C_1_CODE,
+ IRQ_BRP_BRP_CMIF_M2C_2 = IRQ_BRP_BRP_CMIF_M2C_2_CODE,
+ IRQ_CMP_CMTDB = IRQ_CMP_CMTDB_CODE,
+ IRQ_CS_SRAM_CTRL = IRQ_CS_SRAM_CTRL_CODE,
+ IRQ_CSTXB_FDD_CS = IRQ_CSTXB_FDD_CS_CODE,
+ IRQ_CSTXB_TDD_CS = IRQ_CSTXB_TDD_CS_CODE,
+ IRQ_DFE0_CMIF_M2C_0 = IRQ_DFE0_CMIF_M2C_0_CODE,
+ IRQ_DFE0_CMIF_M2C_1 = IRQ_DFE0_CMIF_M2C_1_CODE,
+ IRQ_DFE0_CMIF_M2C_2 = IRQ_DFE0_CMIF_M2C_2_CODE,
+ IRQ_DFE0_PCC_TOP_0_FULL = IRQ_DFE0_PCC_TOP_0_FULL_CODE,
+ IRQ_DFE0_PCC_TOP_1_FULL = IRQ_DFE0_PCC_TOP_1_FULL_CODE,
+ IRQ_DFE0_RXDFEIF_L = IRQ_DFE0_RXDFEIF_L_CODE,
+ IRQ_DFE0_TCU_L1D_1 = IRQ_DFE0_TCU_L1D_1_CODE,
+ IRQ_DFE0_TCU_L1D_2 = IRQ_DFE0_TCU_L1D_2_CODE,
+ IRQ_DFE1_CMIF_M2C_0 = IRQ_DFE1_CMIF_M2C_0_CODE,
+ IRQ_DFE1_CMIF_M2C_1 = IRQ_DFE1_CMIF_M2C_1_CODE,
+ IRQ_DFE1_CMIF_M2C_2 = IRQ_DFE1_CMIF_M2C_2_CODE,
+ IRQ_DFE1_PCC_TOP_0_FULL = IRQ_DFE1_PCC_TOP_0_FULL_CODE,
+ IRQ_DFE1_PCC_TOP_1_FULL = IRQ_DFE1_PCC_TOP_1_FULL_CODE,
+ IRQ_DFE1_RXDFEIF_L = IRQ_DFE1_RXDFEIF_L_CODE,
+ IRQ_L1GDMA = IRQ_L1GDMA_CODE,
+ IRQ_ICC_DSP_0 = IRQ_ICC_DSP_0_CODE,
+ IRQ_ICC_DSP_1 = IRQ_ICC_DSP_1_CODE,
+ IRQ_ICC_SRAM_CTRL = IRQ_ICC_SRAM_CTRL_CODE,
+ IRQ_IDC_PM = IRQ_IDC_PM_CODE,
+ IRQ_IDC_UART = IRQ_IDC_UART_CODE,
+ IRQ_IMC_DSP_0 = IRQ_IMC_DSP_0_CODE,
+ IRQ_IMC_DSP_1 = IRQ_IMC_DSP_1_CODE,
+ IRQ_IMC_MMU_0 = IRQ_IMC_MMU_0_CODE,
+ IRQ_IMC_MMU_1 = IRQ_IMC_MMU_1_CODE,
+ IRQ_IMC_RXDMP = IRQ_IMC_RXDMP_CODE,
+ IRQ_IMC_RXTDB = IRQ_IMC_RXTDB_CODE,
+ IRQ_IMC_SRAM_CTRL = IRQ_IMC_SRAM_CTRL_CODE,
+ IRQ_INR_RAKE_CMIF_M2C_0 = IRQ_INR_RAKE_CMIF_M2C_0_CODE,
+ IRQ_INR_RAKE_CMIF_M2C_1 = IRQ_INR_RAKE_CMIF_M2C_1_CODE,
+ IRQ_INR_TD1_BRP_DMA = IRQ_INR_TD1_BRP_DMA_CODE,
+ IRQ_INR_TD1_CSCE = IRQ_INR_TD1_CSCE_CODE,
+ IRQ_INR_TD1_DFE_BRG = IRQ_INR_TD1_DFE_BRG_CODE,
+ IRQ_INR_TD1_JDA = IRQ_INR_TD1_JDA_CODE,
+ IRQ_INR_TD1_PP = IRQ_INR_TD1_PP_CODE,
+ IRQ_INR_TD2_BRP_DMA = IRQ_INR_TD2_BRP_DMA_CODE,
+ IRQ_INR_TD2_CSCE = IRQ_INR_TD2_CSCE_CODE,
+ IRQ_INR_TD2_DFE_BRG = IRQ_INR_TD2_DFE_BRG_CODE,
+ IRQ_INR_TD2_JDA = IRQ_INR_TD2_JDA_CODE,
+ IRQ_TD2_PP = IRQ_TD2_PP_CODE,
+ IRQ_L1_LTE_SLEEP = IRQ_L1_LTE_SLEEP_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE0 = IRQ_L1M_PHY_LTMR_INFORM_DONE0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE1 = IRQ_L1M_PHY_LTMR_INFORM_DONE1_CODE,
+ IRQ_L1M_PHY_LTMR_0 = IRQ_L1M_PHY_LTMR_0_CODE,
+ IRQ_L1M_PHY_LTMR_1 = IRQ_L1M_PHY_LTMR_1_CODE,
+ IRQ_L1M_PHY_LTMR_2 = IRQ_L1M_PHY_LTMR_2_CODE,
+ IRQ_L1M_PHY_LTMR_3 = IRQ_L1M_PHY_LTMR_3_CODE,
+ IRQ_L1M_PHY_LTMR_4 = IRQ_L1M_PHY_LTMR_4_CODE,
+ IRQ_L1M_PHY_LTMR_5 = IRQ_L1M_PHY_LTMR_5_CODE,
+ IRQ_L1M_PHY_LTMR_6 = IRQ_L1M_PHY_LTMR_6_CODE,
+ IRQ_L1M_PHY_LTMR_7 = IRQ_L1M_PHY_LTMR_7_CODE,
+ IRQ_LTEL1_CS = IRQ_LTEL1_CS_CODE,
+ IRQ_LTXB0_BSI_L_AB = IRQ_LTXB0_BSI_L_AB_CODE,
+ IRQ_LTXB0_BSI_L_C = IRQ_LTXB0_BSI_L_C_CODE,
+ IRQ_LTXB0_BSI_L_D = IRQ_LTXB0_BSI_L_D_CODE,
+ IRQ_LTXB0_TXENC_ERROR = IRQ_LTXB0_TXENC_ERROR_CODE,
+ IRQ_LTXB1_BSI_L_AB = IRQ_LTXB1_BSI_L_AB_CODE,
+ IRQ_LTXB1_BSI_L_C = IRQ_LTXB1_BSI_L_C_CODE,
+ IRQ_LTXB1_BSI_L_D = IRQ_LTXB1_BSI_L_D_CODE,
+ IRQ_LTXB1_TXENC_ERROR = IRQ_LTXB1_TXENC_ERROR_CODE,
+ IRQ_MMU_SRAM_CTRL = IRQ_MMU_SRAM_CTRL_CODE,
+ IRQ_MPC_DSP_0 = IRQ_MPC_DSP_0_CODE,
+ IRQ_MPC_DSP_1 = IRQ_MPC_DSP_1_CODE,
+ IRQ_MPC_SRAM_CTRL = IRQ_MPC_SRAM_CTRL_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_L1_LTE_WAKEUP = IRQ_L1_LTE_WAKEUP_CODE,
+ IRQ_FREQM = IRQ_FREQM_CODE,
+ IRQ_MDL1_TOPSM = IRQ_MDL1_TOPSM_CODE,
+ IRQ_RTR_FRAME = IRQ_RTR_FRAME_CODE,
+ IRQ_RTR_SLT = IRQ_RTR_SLT_CODE,
+ IRQ_WTIMER = IRQ_WTIMER_CODE,
+ IRQ_TDD_WAKEUP = IRQ_TDD_WAKEUP_CODE,
+ IRQ_TDMA_WAKEUP = IRQ_TDMA_WAKEUP_CODE,
+ IRQ_MODEML1_DVFS = IRQ_MODEML1_DVFS_CODE,
+ IRQ_MODEML1_DVFS_MIPS_DVS = IRQ_MODEML1_DVFS_MIPS_DVS_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_0 = IRQ_RESERVED_FOR_CC_IRQ_0_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_1 = IRQ_RESERVED_FOR_CC_IRQ_1_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_2 = IRQ_RESERVED_FOR_CC_IRQ_2_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_3 = IRQ_RESERVED_FOR_CC_IRQ_3_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_4 = IRQ_RESERVED_FOR_CC_IRQ_4_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_5 = IRQ_RESERVED_FOR_CC_IRQ_5_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_6 = IRQ_RESERVED_FOR_CC_IRQ_6_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_7 = IRQ_RESERVED_FOR_CC_IRQ_7_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_8 = IRQ_RESERVED_FOR_CC_IRQ_8_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_9 = IRQ_RESERVED_FOR_CC_IRQ_9_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_10 = IRQ_RESERVED_FOR_CC_IRQ_10_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_11 = IRQ_RESERVED_FOR_CC_IRQ_11_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_12 = IRQ_RESERVED_FOR_CC_IRQ_12_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_13 = IRQ_RESERVED_FOR_CC_IRQ_13_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_14 = IRQ_RESERVED_FOR_CC_IRQ_14_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_15 = IRQ_RESERVED_FOR_CC_IRQ_15_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_16 = IRQ_RESERVED_FOR_CC_IRQ_16_CODE,
+ IRQ_RESERVED_FOR_CC_IRQ_17 = IRQ_RESERVED_FOR_CC_IRQ_17_CODE,
+ IRQ_L1_GPTM1 = IRQ_L1_GPTM1_CODE,
+ IRQ_L1_GPTM2 = IRQ_L1_GPTM2_CODE,
+ IRQ_L1_GPTM3 = IRQ_L1_GPTM3_CODE,
+ IRQ_L1_GPTM4 = IRQ_L1_GPTM4_CODE,
+ IRQ_L1_GPTM5 = IRQ_L1_GPTM5_CODE,
+ IRQ_L1_GPTM6 = IRQ_L1_GPTM6_CODE,
+ IRQ_L1LITE_GPTM = IRQ_L1LITE_GPTM_CODE,
+ IRQ_PPC_CIRQ = IRQ_PPC_CIRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_OS = GIC_OS_priority,
+ GIC_DUMMY = GIC_DUMMY_priority,
+ GIC_INT = GIC_INT_priority,
+ GIC_INT_EX = GIC_INT_EX_priority,
+};
+
+
+#endif /* end of __INTRCTRL_ELBRUS_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS_SW_Handle.h
new file mode 100644
index 0000000..749eeeb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS_SW_Handle.h
@@ -0,0 +1,217 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_ELBRUS_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * ELBRUS
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ __CR4__ User:
+ SW_TRIGGER_CODE1 = Max Weng
+ SW_TRIGGER_CODE2 = Max Weng
+ SW_TRIGGER_CODE3 = Max Weng
+ SW_TRIGGER_CODE4 = Max Weng
+ SW_TRIGGER_CODE5 = Max Weng
+ SW_TRIGGER_CODE6 = Chuansheng Zhang
+ SW_TRIGGER_CODE7 = Chuansheng Zhang
+ SW_TRIGGER_CODE8 = Chuansheng Zhang
+ SW_TRIGGER_CODE9 = Ivan Hu
+ SW_TRIGGER_CODE10 = Kathie Ho
+ SW_TRIGGER_CODE11 = Dennis Chueh
+ SW_TRIGGER_CODE12 = Dennis Chueh
+ SW_TRIGGER_CODE13 = Dennis Chueh
+ SW_TRIGGER_CODE14 = Dennis Chueh
+ SW_TRIGGER_CODE15 = Dennis Chueh
+ SW_TRIGGER_CODE16 = Dennis Chueh
+ SW_TRIGGER_CODE17 = Dennis Chueh
+ SW_TRIGGER_CODE18 = Crilit Tu
+ SW_TRIGGER_CODE19 = Crilit Tu
+ SW_TRIGGER_CODE20 = Yung-Chang Chen
+ SW_TRIGGER_CODE21 = Chuansheng Zhang
+ SW_TRIGGER_CODE22 = Crilit Tu (exception usage)
+ SW_TRIGGER_CODE23 = Carl Kao (ADT)
+ SW_TRIGGER_CODE24 = Qmei Yang (exception usage)
+ SW_TRIGGER_CODE25-42 = Jun-Ying Huang (CCIRQ)
+ SW_TRIGGER_CODE43 = HC Yang (dummy lisr)
+ SW_TRIGGER_CODE44 = HC Yang (dummy lisr)
+ SW_TRIGGER_CODE45 = HC Yang (dummy lisr)
+ SW_TRIGGER_CODE46 =
+ SW_TRIGGER_CODE47 =
+ SW_TRIGGER_CODE48 =
+ SW_TRIGGER_CODE49 =
+ SW_TRIGGER_CODE50 =
+ SW_TRIGGER_CODE51 =
+ SW_TRIGGER_CODE52 =
+ SW_TRIGGER_CODE53 =
+ SW_TRIGGER_CODE54 =
+ */
+#if (defined(__CR4__) || defined(__MIPS_IA__))
+//SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_RESERVED_FOR_CC_IRQ_0_CODE, IRQ_RESERVED_FOR_CC_IRQ_0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_RESERVED_FOR_CC_IRQ_1_CODE, IRQ_RESERVED_FOR_CC_IRQ_1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_RESERVED_FOR_CC_IRQ_2_CODE, IRQ_RESERVED_FOR_CC_IRQ_2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_RESERVED_FOR_CC_IRQ_3_CODE, IRQ_RESERVED_FOR_CC_IRQ_3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_RESERVED_FOR_CC_IRQ_4_CODE, IRQ_RESERVED_FOR_CC_IRQ_4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_RESERVED_FOR_CC_IRQ_5_CODE, IRQ_RESERVED_FOR_CC_IRQ_5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_RESERVED_FOR_CC_IRQ_6_CODE, IRQ_RESERVED_FOR_CC_IRQ_6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_RESERVED_FOR_CC_IRQ_7_CODE, IRQ_RESERVED_FOR_CC_IRQ_7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_RESERVED_FOR_CC_IRQ_8_CODE, IRQ_RESERVED_FOR_CC_IRQ_8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_RESERVED_FOR_CC_IRQ_9_CODE, IRQ_RESERVED_FOR_CC_IRQ_9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_RESERVED_FOR_CC_IRQ_10_CODE, IRQ_RESERVED_FOR_CC_IRQ_10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_RESERVED_FOR_CC_IRQ_11_CODE, IRQ_RESERVED_FOR_CC_IRQ_11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_RESERVED_FOR_CC_IRQ_12_CODE, IRQ_RESERVED_FOR_CC_IRQ_12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_RESERVED_FOR_CC_IRQ_13_CODE, IRQ_RESERVED_FOR_CC_IRQ_13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_RESERVED_FOR_CC_IRQ_14_CODE, IRQ_RESERVED_FOR_CC_IRQ_14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_RESERVED_FOR_CC_IRQ_15_CODE, IRQ_RESERVED_FOR_CC_IRQ_15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_RESERVED_FOR_CC_IRQ_16_CODE, IRQ_RESERVED_FOR_CC_IRQ_16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_RESERVED_FOR_CC_IRQ_17_CODE, IRQ_RESERVED_FOR_CC_IRQ_17_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project ELBRUS for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739.h
new file mode 100644
index 0000000..761d9c2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6739.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6739_H__
+#define __INTRCTRL_MT6739_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (256)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TOPSM_CODE MD_IRQID_TOPSM
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBRP0_CODE MD_IRQID_TXBRP0
+#define IRQ_TXBRP1_CODE MD_IRQID_TXBRP1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_USIP3_1_CODE MD_IRQID_USIP3_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_PTP_SLPCTL_EVENT_CODE MD_IRQID_PTP_SLPCTL_EVENT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_MDCIRQ_WDT0_CODE MD_IRQID_MDCIRQ_WDT0
+#define IRQ_MDCIRQ_WDT1_CODE MD_IRQID_MDCIRQ_WDT1
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_DCXO_RDY_WO_ACK_IRQ_CODE MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_TOP_PLL_DSNS_IRQ_CODE MD_IRQID_TOP_PLL_DSNS_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_USB_MCU_CODE MD_IRQID_SSUSB_USB_MCU
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_BR_DMA_IRQ_CODE MD_IRQID_BR_DMA_IRQ
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_MDL1_TOPSM_IRQ_CODE MD_IRQID_MDL1_TOPSM_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_FRAME_IRQ_CODE MD_IRQID_RTR_FRAME_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_MD_DVFS_CTRL_IRQ_CODE MD_IRQID_MD_DVFS_CTRL_IRQ
+#define IRQ_BSI_MM_I_IRQ_RFIC_CODE MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define IRQ_BSI_MM_I_IRQ_MIPI_CODE MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_SPM2MD_DVFS_MDPERISYS_CODE MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define IRQ_TXDFE_BB_IRQ_CODE MD_IRQID_TXDFE_BB_IRQ
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define GIC0_FDCInt_CODE MD_IRQID_GIC0_FDCInt
+#define GIC0_FDCInt_1_CODE MD_IRQID_GIC0_FDCInt_1
+#define GIC0_PCInt_CODE MD_IRQID_GIC0_PCInt
+#define GIC0_PCInt_1_CODE MD_IRQID_GIC0_PCInt_1
+#define GIC0_TimerInt_CODE MD_IRQID_GIC0_TimerInt
+#define GIC0_TimerInt_1_CODE MD_IRQID_GIC0_TimerInt_1
+#define GIC1_FDCInt_CODE MD_IRQID_GIC1_FDCInt
+#define GIC1_FDCInt_1_CODE MD_IRQID_GIC1_FDCInt_1
+#define GIC1_PCInt_CODE MD_IRQID_GIC1_PCInt
+#define GIC1_PCInt_1_CODE MD_IRQID_GIC1_PCInt_1
+#define GIC1_TimerInt_CODE MD_IRQID_GIC1_TimerInt
+#define GIC1_TimerInt_1_CODE MD_IRQID_GIC1_TimerInt_1
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define SPRAM_DECERR_CODE MD_IRQID_IA_DECERR
+#define RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define MDSM_CORE_PWR_CTRL_CODE MD_IRQID_MDSM_CORE_PWR_CTRL
+#define AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/* 0 ~ 7 */ 69, 127, 67, 68, 66, 38, 32, 61, \
+/* 8 ~ 15 */ 88, 78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110, 42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127, 6, 7, 127, 6, 127, 127, 127, \
+/* 40 ~ 47 */ 127, 71, 41, 39, 62, 45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127, 6, 6, 6, 6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */ 45, 127, 127, 127, 56, 54, 127, 115, \
+/* 88 ~ 95 */ 58, 36, 55, 33, 86, 6, 6, 51, \
+/* 96 ~103 */ 40, 47, 30, 127, 46, 43, 43, 43, \
+/*104 ~111 */ 46, 44, 28, 86, 27, 34, 35, 110, \
+/*112 ~119 */ 31, 49, 26, 64, 25, 127, 127, 59, \
+/*120 ~127 */ 110, 58, 29, 59, 59, 58, 29, 90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */ 70, 77, 44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110, 7, 7, 76, 71, 77, \
+/*152 ~159 */ 50, 51, 52, 79, 76, 77, 39, 72, \
+/*160 ~167 */ 74, 75, 48, 127, 127, 63, 8, 127, \
+/*168 ~175 */ 110, 127, 110, 110, 6, 127, 127, 127, \
+/*176 ~183 */ 75, 75, 127, 127, 7, 111, 7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127, 6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+ IRQ_SW_LISR1_CODE
+ IRQ_SW_LISR2_CODE
+ IRQ_SW_LISR3_CODE
+ IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~223 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*224 ~231 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*232 ~239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~255 */ 0, 0, 0, 0, 0, 0, 0, 0
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 4, 1, 1, 1, 1, 1, 0, \
+ /* 8 ~ 15 */ 1, 1, 17, 4, 4, 0, 4, 4, \
+ /* 16 ~ 23 */ 4, 1, 1, 4, 4, 4, 4, 4, \
+ /* 24 ~ 31 */ 4, 4, 1, 4, 4, 4, 4, 4, \
+ /* 32 ~ 39 */ 0, 5, 0, 4, 5, 4, 4, 4, \
+ /* 40 ~ 47 */ 4, 0, 1, 1, 1, 3, 4, 4, \
+ /* 48 ~ 55 */ 4, 4, 0, 0, 4, 4, 4, 4, \
+ /* 56 ~ 63 */ 4, 4, 4, 4, 5, 5, 5, 5, \
+ /* 64 ~ 71 */ 1, 3, 0, 4, 4, 4, 4, 4, \
+ /* 72 ~ 79 */ 4, 4, 4, 4, 4, 5, 4, 4, \
+ /* 80 ~ 87 */ 3, 4, 4, 0, 1, 1, 4, 4, \
+ /* 88 ~ 95 */ 1, 1, 1, 1, 1, 5, 5, 3, \
+ /* 96 ~103 */ 1, 3, 1, 4, 3, 1, 1, 1, \
+ /*104 ~111 */ 3, 3, 3, 0, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 3, 1, 1, 0, 4, 4, 1, \
+ /*120 ~127 */ 1, 1, 1, 1, 1, 1, 1, 0, \
+ /*128 ~135 */ 4, 4, 0, 4, 4, 4, 4, 4, \
+ /*136 ~143 */ 1, 1, 3, 4, 4, 4, 4, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 2, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 6, 5, 4, 1, 0, 0, \
+ /*168 ~175 */ 1, 2, 3, 1, 5, 16, 0, 2, \
+ /*176 ~183 */ 1, 1, 0, 2, 0, 1, 2, 3, \
+ /*184 ~191 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*192 ~199 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*200 ~207 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*208 ~215 */ 0, 1, 0, 1, 0, 1, 2, 3, \
+ /*216 ~223 */ 2, 3, 2, 3, 4, 4, 4, 4, \
+ /*224 ~231 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*232 ~239 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*240 ~247 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*248 ~255 */ 4, 4, 4, 4, 4, 4, 4, 4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xE, \
+ /* Group1(1) */ 0xD, \
+ /* Group2(2) */ 0xB, \
+ /* Group3(3) */ 0x7, \
+ /* Group4(0,2) */ 0xA, \
+ /* Group5(0,1,2,3) */ 0x0, \
+ /* Group6(1,3) */ 0x5, \
+ /* Group7 */ 0xF, \
+ /* Group8 */ 0xF, \
+ /* Group9 */ 0xF, \
+ /* Group10 */ 0xF, \
+ /* Group11 */ 0xF, \
+ /* Group12 */ 0xF, \
+ /* Group13 */ 0xF, \
+ /* Group14*/ 0xF, \
+ /* Group15 */ 0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+ /* Group0(exception usage) */ 0xF, \
+ /* Group1 */ 0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x040627FD, \
+ /* 32-63 */ 0xF00C3E17, \
+ /* 64-95 */ 0xFF392007, \
+ /* 96-127 */ 0xFF9FFFF7, \
+ /* 128-159 */ 0xFFFF8704, \
+ /* 160-191 */ 0x00FFDFFF, \
+ /* 192-223 */ 0x0FFF0000, \
+ /* 224-255 */ 0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0xF0000012, \
+ /* 64-95 */ 0x60002000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x0000101C, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00002000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+#define INTERRUPT_HRT_MT \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00000000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+ /* VPE0 */ 0xFFFFFFFF,\
+ /* VPE1 */ 0xFFFFFFFF,\
+ /* VPE2 */ 0xFFFFFFFF,\
+ /* VPE3 */ 0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_DORMANT = 0,
+ VPE_STATUS_LISR_HIGHEST = 1,
+ VPE_STATUS_LISR_LOWEST = 127,
+ VPE_STATUS_HISR_TASK_HIGHEST = 128,
+ VPE_STATUS_HISR_TASK_LOWEST = 386,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_TOPSM = IRQ_TOPSM_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+ IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+ IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+ IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+ IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+ IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+ IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+ IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+ IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+ IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+ IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+ IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+ IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+ IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+ IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+ IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+ IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+ IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+ IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+ IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+ IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+ IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+ IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+ IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+ IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+ IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+ IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+ MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+ GIC0_FDCInt = GIC0_FDCInt_CODE,
+ GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+ GIC0_PCInt = GIC0_PCInt_CODE,
+ GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+ GIC0_TimerInt = GIC0_TimerInt_CODE,
+ GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+ GIC1_FDCInt = GIC1_FDCInt_CODE,
+ GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+ GIC1_PCInt = GIC1_PCInt_CODE,
+ GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+ GIC1_TimerInt = GIC1_TimerInt_CODE,
+ GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ MCUMMU_INT = MCUMMU_INT_CODE,
+ SPRAM_DECERR = SPRAM_DECERR_CODE,
+ RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+ MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+ AP2MD_MSDC0 = AP2MD_MSDC0_CODE
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6739_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739_SW_Handle.h
new file mode 100644
index 0000000..0d69b67
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6739_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6739
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver code.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW IRQ for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE5 = HC Yang
+ SW_TRIGGER_CODE6 = HC Yang
+ SW_TRIGGER_CODE7 = Max Weng
+ SW_TRIGGER_CODE8 = Max Weng
+ SW_TRIGGER_CODE9 = Max Weng
+ SW_TRIGGER_CODE10 = Max Weng
+ SW_TRIGGER_CODE11 = Max Weng
+ SW_TRIGGER_CODE12 = Max Weng
+ SW_TRIGGER_CODE13 = Zengling Jin
+ SW_TRIGGER_CODE14 = Zengling Jin
+ SW_TRIGGER_CODE15 = Zengling Jin
+ SW_TRIGGER_CODE16 = Chuansheng Zhang
+ SW_TRIGGER_CODE17 = Chuansheng Zhang
+ SW_TRIGGER_CODE18 = Chuansheng Zhang
+ SW_TRIGGER_CODE19 = Chuansheng Zhang
+ SW_TRIGGER_CODE20 = Huei-Ya Chang
+ SW_TRIGGER_CODE21 = Qmei Yang
+ SW_TRIGGER_CODE22 = Tee-Yuen Chun
+ SW_TRIGGER_CODE23 = Yuni Chang
+ SW_TRIGGER_CODE24 = SY Yeh
+ SW_TRIGGER_CODE25 = Owen Ho
+ SW_TRIGGER_CODE26 = Owen Ho
+ SW_TRIGGER_CODE27 = Owen Ho
+ SW_TRIGGER_CODE28 = Owen Ho
+ SW_TRIGGER_CODE29 = Carl Kao
+ SW_TRIGGER_CODE30 = Wade Huang
+ SW_TRIGGER_CODE31 = Woody kuo
+ SW_TRIGGER_CODE32 = Jun-Ying Huang
+ SW_TRIGGER_CODE33 = Jun-Ying Huang
+ SW_TRIGGER_CODE34 = Weimin Zeng
+ SW_TRIGGER_CODE35 = Weimin Zeng
+ SW_TRIGGER_CODE36 = HW Jheng
+ SW_TRIGGER_CODE37 = HW Jheng
+ SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE42 =
+ SW_TRIGGER_CODE43 =
+ SW_TRIGGER_CODE44 =
+ SW_TRIGGER_CODE45 =
+ SW_TRIGGER_CODE46 =
+ SW_TRIGGER_CODE47 =
+ SW_TRIGGER_CODE48 =
+ SW_TRIGGER_CODE49 =
+ SW_TRIGGER_CODE50 =
+ SW_TRIGGER_CODE51 =
+ SW_TRIGGER_CODE52 =
+ SW_TRIGGER_CODE53 =
+ SW_TRIGGER_CODE54 =
+ SW_TRIGGER_CODE55 =
+ SW_TRIGGER_CODE56 =
+ SW_TRIGGER_CODE57 =
+ SW_TRIGGER_CODE58 =
+ SW_TRIGGER_CODE59 =
+ SW_TRIGGER_CODE60 =
+ SW_TRIGGER_CODE61 =
+ SW_TRIGGER_CODE62 =
+ SW_TRIGGER_CODE63 =
+ SW_TRIGGER_CODE64 =
+ */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6739 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761.h
new file mode 100644
index 0000000..5550b1a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6761.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6761_H__
+#define __INTRCTRL_MT6761_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (256)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TOPSM_CODE MD_IRQID_TOPSM
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBRP0_CODE MD_IRQID_TXBRP0
+#define IRQ_TXBRP1_CODE MD_IRQID_TXBRP1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_AP2MD_CCIF2_0_CODE MD_IRQID_AP2MD_CCIF2_0
+#define IRQ_USIP3_1_CODE MD_IRQID_USIP3_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_PTP_SLPCTL_EVENT_CODE MD_IRQID_PTP_SLPCTL_EVENT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_MDCIRQ_WDT0_CODE MD_IRQID_MDCIRQ_WDT0
+#define IRQ_MDCIRQ_WDT1_CODE MD_IRQID_MDCIRQ_WDT1
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_DCXO_RDY_WO_ACK_IRQ_CODE MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_TOP_PLL_DSNS_IRQ_CODE MD_IRQID_TOP_PLL_DSNS_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_USB_MCU_CODE MD_IRQID_SSUSB_USB_MCU
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_BR_DMA_IRQ_CODE MD_IRQID_BR_DMA_IRQ
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_MDL1_TOPSM_IRQ_CODE MD_IRQID_MDL1_TOPSM_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_FRAME_IRQ_CODE MD_IRQID_RTR_FRAME_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_MD_DVFS_CTRL_IRQ_CODE MD_IRQID_MD_DVFS_CTRL_IRQ
+#define IRQ_BSI_MM_I_IRQ_RFIC_CODE MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define IRQ_BSI_MM_I_IRQ_MIPI_CODE MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_SPM2MD_DVFS_MDPERISYS_CODE MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define IRQ_TXDFE_BB_IRQ_CODE MD_IRQID_TXDFE_BB_IRQ
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define GIC0_FDCInt_CODE MD_IRQID_GIC0_FDCInt
+#define GIC0_FDCInt_1_CODE MD_IRQID_GIC0_FDCInt_1
+#define GIC0_PCInt_CODE MD_IRQID_GIC0_PCInt
+#define GIC0_PCInt_1_CODE MD_IRQID_GIC0_PCInt_1
+#define GIC0_TimerInt_CODE MD_IRQID_GIC0_TimerInt
+#define GIC0_TimerInt_1_CODE MD_IRQID_GIC0_TimerInt_1
+#define GIC1_FDCInt_CODE MD_IRQID_GIC1_FDCInt
+#define GIC1_FDCInt_1_CODE MD_IRQID_GIC1_FDCInt_1
+#define GIC1_PCInt_CODE MD_IRQID_GIC1_PCInt
+#define GIC1_PCInt_1_CODE MD_IRQID_GIC1_PCInt_1
+#define GIC1_TimerInt_CODE MD_IRQID_GIC1_TimerInt
+#define GIC1_TimerInt_1_CODE MD_IRQID_GIC1_TimerInt_1
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define SPRAM_DECERR_CODE MD_IRQID_IA_DECERR
+#define RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define MDSM_CORE_PWR_CTRL_CODE MD_IRQID_MDSM_CORE_PWR_CTRL
+#define AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/* 0 ~ 7 */ 69, 127, 67, 68, 66, 38, 32, 61, \
+/* 8 ~ 15 */ 88, 78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110, 42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127, 6, 7, 127, 6, 127, 127, 127, \
+/* 40 ~ 47 */ 127, 71, 41, 39, 62, 45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127, 6, 6, 6, 6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */ 45, 127, 127, 127, 56, 54, 127, 115, \
+/* 88 ~ 95 */ 58, 36, 55, 33, 86, 6, 6, 51, \
+/* 96 ~103 */ 40, 47, 30, 127, 46, 43, 43, 43, \
+/*104 ~111 */ 46, 44, 28, 86, 27, 34, 35, 110, \
+/*112 ~119 */ 31, 49, 26, 64, 25, 127, 127, 59, \
+/*120 ~127 */ 110, 58, 29, 59, 59, 58, 29, 90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */ 70, 77, 44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110, 7, 7, 76, 71, 77, \
+/*152 ~159 */ 50, 51, 52, 79, 76, 77, 39, 72, \
+/*160 ~167 */ 74, 75, 48, 127, 127, 63, 8, 127, \
+/*168 ~175 */ 110, 127, 110, 110, 6, 127, 127, 127, \
+/*176 ~183 */ 75, 75, 127, 127, 7, 111, 7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127, 6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+ IRQ_SW_LISR1_CODE
+ IRQ_SW_LISR2_CODE
+ IRQ_SW_LISR3_CODE
+ IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~223 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*224 ~231 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*232 ~239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~255 */ 0, 0, 0, 0, 0, 0, 0, 0
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 4, 1, 1, 1, 1, 1, 0, \
+ /* 8 ~ 15 */ 1, 1, 17, 4, 4, 0, 4, 4, \
+ /* 16 ~ 23 */ 4, 1, 1, 4, 4, 4, 4, 4, \
+ /* 24 ~ 31 */ 4, 4, 1, 4, 4, 4, 4, 4, \
+ /* 32 ~ 39 */ 0, 5, 0, 4, 5, 4, 4, 4, \
+ /* 40 ~ 47 */ 4, 0, 1, 1, 1, 3, 4, 4, \
+ /* 48 ~ 55 */ 4, 4, 0, 0, 4, 4, 4, 4, \
+ /* 56 ~ 63 */ 4, 4, 4, 4, 5, 5, 5, 5, \
+ /* 64 ~ 71 */ 1, 3, 0, 4, 4, 4, 4, 4, \
+ /* 72 ~ 79 */ 4, 4, 4, 4, 4, 5, 4, 4, \
+ /* 80 ~ 87 */ 3, 4, 4, 0, 1, 1, 4, 4, \
+ /* 88 ~ 95 */ 1, 1, 1, 1, 1, 5, 5, 3, \
+ /* 96 ~103 */ 1, 3, 1, 4, 3, 1, 1, 1, \
+ /*104 ~111 */ 3, 3, 3, 0, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 3, 1, 1, 0, 4, 4, 1, \
+ /*120 ~127 */ 1, 1, 1, 1, 1, 1, 1, 0, \
+ /*128 ~135 */ 4, 4, 0, 4, 4, 4, 4, 4, \
+ /*136 ~143 */ 1, 1, 3, 4, 4, 4, 4, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 2, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 6, 5, 4, 1, 0, 0, \
+ /*168 ~175 */ 1, 2, 3, 1, 5, 16, 0, 2, \
+ /*176 ~183 */ 1, 1, 0, 2, 0, 1, 2, 3, \
+ /*184 ~191 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*192 ~199 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*200 ~207 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*208 ~215 */ 0, 1, 0, 1, 0, 1, 2, 3, \
+ /*216 ~223 */ 2, 3, 2, 3, 4, 4, 4, 4, \
+ /*224 ~231 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*232 ~239 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*240 ~247 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*248 ~255 */ 4, 4, 4, 4, 4, 4, 4, 4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xE, \
+ /* Group1(1) */ 0xD, \
+ /* Group2(2) */ 0xB, \
+ /* Group3(3) */ 0x7, \
+ /* Group4(0,2) */ 0xA, \
+ /* Group5(0,1,2,3) */ 0x0, \
+ /* Group6(1,3) */ 0x5, \
+ /* Group7 */ 0xF, \
+ /* Group8 */ 0xF, \
+ /* Group9 */ 0xF, \
+ /* Group10 */ 0xF, \
+ /* Group11 */ 0xF, \
+ /* Group12 */ 0xF, \
+ /* Group13 */ 0xF, \
+ /* Group14*/ 0xF, \
+ /* Group15 */ 0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+ /* Group0(exception usage) */ 0xF, \
+ /* Group1 */ 0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x040627FD, \
+ /* 32-63 */ 0xF00C3E17, \
+ /* 64-95 */ 0xFF392007, \
+ /* 96-127 */ 0xFF9FFFF7, \
+ /* 128-159 */ 0xFFFF8704, \
+ /* 160-191 */ 0x00FFDFFF, \
+ /* 192-223 */ 0x0FFF0000, \
+ /* 224-255 */ 0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0xF0000012, \
+ /* 64-95 */ 0x60002000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x0000101C, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00002000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+#define INTERRUPT_HRT_MT \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00000000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+ /* VPE0 */ 0xFFFFFFFF,\
+ /* VPE1 */ 0xFFFFFFFF,\
+ /* VPE2 */ 0xFFFFFFFF,\
+ /* VPE3 */ 0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_DORMANT = 0,
+ VPE_STATUS_LISR_HIGHEST = 1,
+ VPE_STATUS_LISR_LOWEST = 127,
+ VPE_STATUS_HISR_TASK_HIGHEST = 128,
+ VPE_STATUS_HISR_TASK_LOWEST = 386,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_TOPSM = IRQ_TOPSM_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+ IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_AP2MD_CCIF2_0 = IRQ_AP2MD_CCIF2_0_CODE,
+ IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+ IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+ IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+ IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+ IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+ IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+ IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+ IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+ IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+ IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+ IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+ IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+ IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+ IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+ IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+ IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+ IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+ IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+ IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+ IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+ IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+ IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+ IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+ IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+ IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+ IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+ MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+ GIC0_FDCInt = GIC0_FDCInt_CODE,
+ GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+ GIC0_PCInt = GIC0_PCInt_CODE,
+ GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+ GIC0_TimerInt = GIC0_TimerInt_CODE,
+ GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+ GIC1_FDCInt = GIC1_FDCInt_CODE,
+ GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+ GIC1_PCInt = GIC1_PCInt_CODE,
+ GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+ GIC1_TimerInt = GIC1_TimerInt_CODE,
+ GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ MCUMMU_INT = MCUMMU_INT_CODE,
+ SPRAM_DECERR = SPRAM_DECERR_CODE,
+ RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+ MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+ AP2MD_MSDC0 = AP2MD_MSDC0_CODE
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6761_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761_SW_Handle.h
new file mode 100644
index 0000000..b6b12ed
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6761_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6761
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW interrupt for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE5 = HC Yang
+ SW_TRIGGER_CODE6 = HC Yang
+ SW_TRIGGER_CODE7 = Max Weng
+ SW_TRIGGER_CODE8 = Max Weng
+ SW_TRIGGER_CODE9 = Max Weng
+ SW_TRIGGER_CODE10 = Max Weng
+ SW_TRIGGER_CODE11 = Max Weng
+ SW_TRIGGER_CODE12 = Max Weng
+ SW_TRIGGER_CODE13 = Zengling Jin
+ SW_TRIGGER_CODE14 = Zengling Jin
+ SW_TRIGGER_CODE15 = Zengling Jin
+ SW_TRIGGER_CODE16 = Chuansheng Zhang
+ SW_TRIGGER_CODE17 = Chuansheng Zhang
+ SW_TRIGGER_CODE18 = Chuansheng Zhang
+ SW_TRIGGER_CODE19 = Chuansheng Zhang
+ SW_TRIGGER_CODE20 = Huei-Ya Chang
+ SW_TRIGGER_CODE21 = Qmei Yang
+ SW_TRIGGER_CODE22 = Tee-Yuen Chun
+ SW_TRIGGER_CODE23 = Yuni Chang
+ SW_TRIGGER_CODE24 = SY Yeh
+ SW_TRIGGER_CODE25 = Owen Ho
+ SW_TRIGGER_CODE26 = Owen Ho
+ SW_TRIGGER_CODE27 = Owen Ho
+ SW_TRIGGER_CODE28 = Owen Ho
+ SW_TRIGGER_CODE29 = Carl Kao
+ SW_TRIGGER_CODE30 = Wade Huang
+ SW_TRIGGER_CODE31 = Woody kuo
+ SW_TRIGGER_CODE32 = Jun-Ying Huang
+ SW_TRIGGER_CODE33 = Jun-Ying Huang
+ SW_TRIGGER_CODE34 = Weimin Zeng
+ SW_TRIGGER_CODE35 = Weimin Zeng
+ SW_TRIGGER_CODE36 = HW Jheng
+ SW_TRIGGER_CODE37 = HW Jheng
+ SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE42 =
+ SW_TRIGGER_CODE43 =
+ SW_TRIGGER_CODE44 =
+ SW_TRIGGER_CODE45 =
+ SW_TRIGGER_CODE46 =
+ SW_TRIGGER_CODE47 =
+ SW_TRIGGER_CODE48 =
+ SW_TRIGGER_CODE49 =
+ SW_TRIGGER_CODE50 =
+ SW_TRIGGER_CODE51 =
+ SW_TRIGGER_CODE52 =
+ SW_TRIGGER_CODE53 =
+ SW_TRIGGER_CODE54 =
+ SW_TRIGGER_CODE55 =
+ SW_TRIGGER_CODE56 =
+ SW_TRIGGER_CODE57 =
+ SW_TRIGGER_CODE58 =
+ SW_TRIGGER_CODE59 =
+ SW_TRIGGER_CODE60 =
+ SW_TRIGGER_CODE61 =
+ SW_TRIGGER_CODE62 =
+ SW_TRIGGER_CODE63 =
+ SW_TRIGGER_CODE64 =
+ */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6761 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763.h
new file mode 100644
index 0000000..4fbe1f6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6763.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6763_H__
+#define __INTRCTRL_MT6763_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (256)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TOPSM_CODE MD_IRQID_TOPSM
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBRP0_CODE MD_IRQID_TXBRP0
+#define IRQ_TXBRP1_CODE MD_IRQID_TXBRP1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_USIP3_1_CODE MD_IRQID_USIP3_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_PTP_SLPCTL_EVENT_CODE MD_IRQID_PTP_SLPCTL_EVENT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_MDCIRQ_WDT0_CODE MD_IRQID_MDCIRQ_WDT0
+#define IRQ_MDCIRQ_WDT1_CODE MD_IRQID_MDCIRQ_WDT1
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_DCXO_RDY_WO_ACK_IRQ_CODE MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_TOP_PLL_DSNS_IRQ_CODE MD_IRQID_TOP_PLL_DSNS_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_USB_MCU_CODE MD_IRQID_SSUSB_USB_MCU
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_BR_DMA_IRQ_CODE MD_IRQID_BR_DMA_IRQ
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_MDL1_TOPSM_IRQ_CODE MD_IRQID_MDL1_TOPSM_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_FRAME_IRQ_CODE MD_IRQID_RTR_FRAME_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_MD_DVFS_CTRL_IRQ_CODE MD_IRQID_MD_DVFS_CTRL_IRQ
+#define IRQ_BSI_MM_I_IRQ_RFIC_CODE MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define IRQ_BSI_MM_I_IRQ_MIPI_CODE MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_SPM2MD_DVFS_MDPERISYS_CODE MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define IRQ_TXDFE_BB_IRQ_CODE MD_IRQID_TXDFE_BB_IRQ
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define GIC0_FDCInt_CODE MD_IRQID_GIC0_FDCInt
+#define GIC0_FDCInt_1_CODE MD_IRQID_GIC0_FDCInt_1
+#define GIC0_PCInt_CODE MD_IRQID_GIC0_PCInt
+#define GIC0_PCInt_1_CODE MD_IRQID_GIC0_PCInt_1
+#define GIC0_TimerInt_CODE MD_IRQID_GIC0_TimerInt
+#define GIC0_TimerInt_1_CODE MD_IRQID_GIC0_TimerInt_1
+#define GIC1_FDCInt_CODE MD_IRQID_GIC1_FDCInt
+#define GIC1_FDCInt_1_CODE MD_IRQID_GIC1_FDCInt_1
+#define GIC1_PCInt_CODE MD_IRQID_GIC1_PCInt
+#define GIC1_PCInt_1_CODE MD_IRQID_GIC1_PCInt_1
+#define GIC1_TimerInt_CODE MD_IRQID_GIC1_TimerInt
+#define GIC1_TimerInt_1_CODE MD_IRQID_GIC1_TimerInt_1
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define SPRAM_DECERR_CODE MD_IRQID_IA_DECERR
+#define RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define MDSM_CORE_PWR_CTRL_CODE MD_IRQID_MDSM_CORE_PWR_CTRL
+#define AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/* 0 ~ 7 */ 69, 127, 67, 68, 66, 38, 32, 61, \
+/* 8 ~ 15 */ 88, 78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110, 42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127, 6, 7, 127, 6, 127, 127, 127, \
+/* 40 ~ 47 */ 127, 71, 41, 39, 62, 45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127, 6, 6, 6, 6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */ 45, 127, 127, 127, 56, 54, 127, 115, \
+/* 88 ~ 95 */ 58, 36, 55, 33, 86, 6, 6, 51, \
+/* 96 ~103 */ 40, 47, 30, 127, 46, 43, 43, 43, \
+/*104 ~111 */ 46, 44, 28, 86, 27, 34, 35, 110, \
+/*112 ~119 */ 31, 49, 26, 64, 25, 127, 127, 59, \
+/*120 ~127 */ 110, 58, 29, 59, 59, 58, 29, 90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */ 70, 77, 44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110, 7, 7, 76, 71, 77, \
+/*152 ~159 */ 50, 51, 52, 79, 76, 77, 39, 72, \
+/*160 ~167 */ 74, 75, 48, 127, 127, 63, 8, 127, \
+/*168 ~175 */ 110, 127, 110, 110, 6, 127, 127, 127, \
+/*176 ~183 */ 75, 75, 127, 127, 7, 111, 7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127, 6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+ IRQ_SW_LISR1_CODE
+ IRQ_SW_LISR2_CODE
+ IRQ_SW_LISR3_CODE
+ IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~223 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*224 ~231 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*232 ~239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~255 */ 0, 0, 0, 0, 0, 0, 0, 0
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 4, 1, 1, 1, 1, 1, 0, \
+ /* 8 ~ 15 */ 1, 1, 17, 4, 4, 0, 4, 4, \
+ /* 16 ~ 23 */ 4, 1, 1, 4, 4, 4, 4, 4, \
+ /* 24 ~ 31 */ 4, 4, 1, 4, 4, 4, 4, 4, \
+ /* 32 ~ 39 */ 0, 5, 0, 4, 5, 4, 4, 4, \
+ /* 40 ~ 47 */ 4, 0, 1, 1, 1, 3, 4, 4, \
+ /* 48 ~ 55 */ 4, 4, 0, 0, 4, 4, 4, 4, \
+ /* 56 ~ 63 */ 4, 4, 4, 4, 5, 5, 5, 5, \
+ /* 64 ~ 71 */ 1, 3, 0, 4, 4, 4, 4, 4, \
+ /* 72 ~ 79 */ 4, 4, 4, 4, 4, 5, 4, 4, \
+ /* 80 ~ 87 */ 3, 4, 4, 0, 1, 1, 4, 4, \
+ /* 88 ~ 95 */ 1, 1, 1, 1, 1, 5, 5, 3, \
+ /* 96 ~103 */ 1, 3, 1, 4, 3, 1, 1, 1, \
+ /*104 ~111 */ 3, 3, 3, 0, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 3, 1, 1, 0, 4, 4, 1, \
+ /*120 ~127 */ 1, 1, 1, 1, 1, 1, 1, 0, \
+ /*128 ~135 */ 4, 4, 0, 4, 4, 4, 4, 4, \
+ /*136 ~143 */ 1, 1, 3, 4, 4, 4, 4, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 2, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 6, 5, 4, 1, 0, 0, \
+ /*168 ~175 */ 1, 2, 3, 1, 5, 16, 0, 2, \
+ /*176 ~183 */ 1, 1, 0, 2, 0, 1, 2, 3, \
+ /*184 ~191 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*192 ~199 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*200 ~207 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*208 ~215 */ 0, 1, 0, 1, 0, 1, 2, 3, \
+ /*216 ~223 */ 2, 3, 2, 3, 4, 4, 4, 4, \
+ /*224 ~231 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*232 ~239 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*240 ~247 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*248 ~255 */ 4, 4, 4, 4, 4, 4, 4, 4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xE, \
+ /* Group1(1) */ 0xD, \
+ /* Group2(2) */ 0xB, \
+ /* Group3(3) */ 0x7, \
+ /* Group4(0,2) */ 0xA, \
+ /* Group5(0,1,2,3) */ 0x0, \
+ /* Group6(1,3) */ 0x5, \
+ /* Group7 */ 0xF, \
+ /* Group8 */ 0xF, \
+ /* Group9 */ 0xF, \
+ /* Group10 */ 0xF, \
+ /* Group11 */ 0xF, \
+ /* Group12 */ 0xF, \
+ /* Group13 */ 0xF, \
+ /* Group14*/ 0xF, \
+ /* Group15 */ 0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+ /* Group0(exception usage) */ 0xF, \
+ /* Group1 */ 0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x040627FD, \
+ /* 32-63 */ 0xF00C3E17, \
+ /* 64-95 */ 0xFF392007, \
+ /* 96-127 */ 0xFF9FFFF7, \
+ /* 128-159 */ 0xFFFF8704, \
+ /* 160-191 */ 0x00FFDFFF, \
+ /* 192-223 */ 0x0FFF0000, \
+ /* 224-255 */ 0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0xF0000012, \
+ /* 64-95 */ 0x60002000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x0000101C, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00002000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+#define INTERRUPT_HRT_MT \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00000000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+ /* VPE0 */ 0xFFFFFFFF,\
+ /* VPE1 */ 0xFFFFFFFF,\
+ /* VPE2 */ 0xFFFFFFFF,\
+ /* VPE3 */ 0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_DORMANT = 0,
+ VPE_STATUS_LISR_HIGHEST = 1,
+ VPE_STATUS_LISR_LOWEST = 127,
+ VPE_STATUS_HISR_TASK_HIGHEST = 128,
+ VPE_STATUS_HISR_TASK_LOWEST = 386,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_TOPSM = IRQ_TOPSM_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+ IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+ IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+ IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+ IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+ IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+ IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+ IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+ IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+ IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+ IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+ IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+ IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+ IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+ IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+ IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+ IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+ IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+ IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+ IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+ IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+ IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+ IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+ IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+ IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+ IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+ IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+ MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+ GIC0_FDCInt = GIC0_FDCInt_CODE,
+ GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+ GIC0_PCInt = GIC0_PCInt_CODE,
+ GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+ GIC0_TimerInt = GIC0_TimerInt_CODE,
+ GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+ GIC1_FDCInt = GIC1_FDCInt_CODE,
+ GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+ GIC1_PCInt = GIC1_PCInt_CODE,
+ GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+ GIC1_TimerInt = GIC1_TimerInt_CODE,
+ GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ MCUMMU_INT = MCUMMU_INT_CODE,
+ SPRAM_DECERR = SPRAM_DECERR_CODE,
+ RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+ MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+ AP2MD_MSDC0 = AP2MD_MSDC0_CODE
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6763_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763_SW_Handle.h
new file mode 100644
index 0000000..b080c51
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6763_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6763
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver code.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW IRQ for SWLA.
+ *
+ * 05 05 2017 yen-chun.liu
+ * [MOLY00246656] [BIANCO][MT6763][RDIT][C2K][SRLTE][Try run][SIM1: CTC][4]MOD_NIL, , TRACE_ERROR, [DSP-inner] Assert fail: Line 1417 Code 0x13 0xb000000 0x12 Filename: md32/usip/inner/modem/lte/lte_scheduler/src/lte_scheduler.c
+ * change IRQ priority of GDMA and one more SW trigger IRQ request.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE5 = HC Yang
+ SW_TRIGGER_CODE6 = HC Yang
+ SW_TRIGGER_CODE7 = Max Weng
+ SW_TRIGGER_CODE8 = Max Weng
+ SW_TRIGGER_CODE9 = Max Weng
+ SW_TRIGGER_CODE10 = Max Weng
+ SW_TRIGGER_CODE11 = Max Weng
+ SW_TRIGGER_CODE12 = Max Weng
+ SW_TRIGGER_CODE13 = Zengling Jin
+ SW_TRIGGER_CODE14 = Zengling Jin
+ SW_TRIGGER_CODE15 = Zengling Jin
+ SW_TRIGGER_CODE16 = Chuansheng Zhang
+ SW_TRIGGER_CODE17 = Chuansheng Zhang
+ SW_TRIGGER_CODE18 = Chuansheng Zhang
+ SW_TRIGGER_CODE19 = Chuansheng Zhang
+ SW_TRIGGER_CODE20 = Huei-Ya Chang
+ SW_TRIGGER_CODE21 = Qmei Yang
+ SW_TRIGGER_CODE22 = Tee-Yuen Chun
+ SW_TRIGGER_CODE23 = Yuni Chang
+ SW_TRIGGER_CODE24 = SY Yeh
+ SW_TRIGGER_CODE25 = Owen Ho
+ SW_TRIGGER_CODE26 = Owen Ho
+ SW_TRIGGER_CODE27 = Owen Ho
+ SW_TRIGGER_CODE28 = Owen Ho
+ SW_TRIGGER_CODE29 = Carl Kao
+ SW_TRIGGER_CODE30 = Wade Huang
+ SW_TRIGGER_CODE31 = Woody kuo
+ SW_TRIGGER_CODE32 = Jun-Ying Huang
+ SW_TRIGGER_CODE33 = Jun-Ying Huang
+ SW_TRIGGER_CODE34 = Weimin Zeng
+ SW_TRIGGER_CODE35 = Weimin Zeng
+ SW_TRIGGER_CODE36 = HW Jheng
+ SW_TRIGGER_CODE37 = HW Jheng
+ SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE42 =
+ SW_TRIGGER_CODE43 =
+ SW_TRIGGER_CODE44 =
+ SW_TRIGGER_CODE45 =
+ SW_TRIGGER_CODE46 =
+ SW_TRIGGER_CODE47 =
+ SW_TRIGGER_CODE48 =
+ SW_TRIGGER_CODE49 =
+ SW_TRIGGER_CODE50 =
+ SW_TRIGGER_CODE51 =
+ SW_TRIGGER_CODE52 =
+ SW_TRIGGER_CODE53 =
+ SW_TRIGGER_CODE54 =
+ SW_TRIGGER_CODE55 =
+ SW_TRIGGER_CODE56 =
+ SW_TRIGGER_CODE57 =
+ SW_TRIGGER_CODE58 =
+ SW_TRIGGER_CODE59 =
+ SW_TRIGGER_CODE60 =
+ SW_TRIGGER_CODE61 =
+ SW_TRIGGER_CODE62 =
+ SW_TRIGGER_CODE63 =
+ SW_TRIGGER_CODE64 =
+ */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6763 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765.h
new file mode 100644
index 0000000..274d812
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6765.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6765_H__
+#define __INTRCTRL_MT6765_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (256)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TOPSM_CODE MD_IRQID_TOPSM
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBRP0_CODE MD_IRQID_TXBRP0
+#define IRQ_TXBRP1_CODE MD_IRQID_TXBRP1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_AP2MD_CCIF2_0_CODE MD_IRQID_AP2MD_CCIF2_0
+#define IRQ_USIP3_1_CODE MD_IRQID_USIP3_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_PTP_SLPCTL_EVENT_CODE MD_IRQID_PTP_SLPCTL_EVENT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_MDCIRQ_WDT0_CODE MD_IRQID_MDCIRQ_WDT0
+#define IRQ_MDCIRQ_WDT1_CODE MD_IRQID_MDCIRQ_WDT1
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_DCXO_RDY_WO_ACK_IRQ_CODE MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_TOP_PLL_DSNS_IRQ_CODE MD_IRQID_TOP_PLL_DSNS_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_USB_MCU_CODE MD_IRQID_SSUSB_USB_MCU
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_BR_DMA_IRQ_CODE MD_IRQID_BR_DMA_IRQ
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_MDL1_TOPSM_IRQ_CODE MD_IRQID_MDL1_TOPSM_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_FRAME_IRQ_CODE MD_IRQID_RTR_FRAME_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_MD_DVFS_CTRL_IRQ_CODE MD_IRQID_MD_DVFS_CTRL_IRQ
+#define IRQ_BSI_MM_I_IRQ_RFIC_CODE MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define IRQ_BSI_MM_I_IRQ_MIPI_CODE MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_SPM2MD_DVFS_MDPERISYS_CODE MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define IRQ_TXDFE_BB_IRQ_CODE MD_IRQID_TXDFE_BB_IRQ
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define GIC0_FDCInt_CODE MD_IRQID_GIC0_FDCInt
+#define GIC0_FDCInt_1_CODE MD_IRQID_GIC0_FDCInt_1
+#define GIC0_PCInt_CODE MD_IRQID_GIC0_PCInt
+#define GIC0_PCInt_1_CODE MD_IRQID_GIC0_PCInt_1
+#define GIC0_TimerInt_CODE MD_IRQID_GIC0_TimerInt
+#define GIC0_TimerInt_1_CODE MD_IRQID_GIC0_TimerInt_1
+#define GIC1_FDCInt_CODE MD_IRQID_GIC1_FDCInt
+#define GIC1_FDCInt_1_CODE MD_IRQID_GIC1_FDCInt_1
+#define GIC1_PCInt_CODE MD_IRQID_GIC1_PCInt
+#define GIC1_PCInt_1_CODE MD_IRQID_GIC1_PCInt_1
+#define GIC1_TimerInt_CODE MD_IRQID_GIC1_TimerInt
+#define GIC1_TimerInt_1_CODE MD_IRQID_GIC1_TimerInt_1
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define SPRAM_DECERR_CODE MD_IRQID_IA_DECERR
+#define RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define MDSM_CORE_PWR_CTRL_CODE MD_IRQID_MDSM_CORE_PWR_CTRL
+#define AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/* 0 ~ 7 */ 69, 127, 67, 68, 66, 38, 32, 61, \
+/* 8 ~ 15 */ 88, 78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110, 42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127, 6, 7, 127, 6, 127, 127, 127, \
+/* 40 ~ 47 */ 127, 71, 41, 39, 62, 45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127, 6, 6, 6, 6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */ 45, 127, 127, 127, 56, 54, 127, 115, \
+/* 88 ~ 95 */ 58, 36, 55, 33, 86, 6, 6, 51, \
+/* 96 ~103 */ 40, 47, 30, 127, 46, 43, 43, 43, \
+/*104 ~111 */ 46, 44, 28, 86, 27, 34, 35, 110, \
+/*112 ~119 */ 31, 49, 26, 64, 25, 127, 127, 59, \
+/*120 ~127 */ 110, 58, 29, 59, 59, 58, 29, 90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */ 70, 77, 44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110, 7, 7, 76, 71, 77, \
+/*152 ~159 */ 50, 51, 52, 79, 76, 77, 39, 72, \
+/*160 ~167 */ 74, 75, 48, 127, 127, 63, 8, 127, \
+/*168 ~175 */ 110, 127, 110, 110, 6, 127, 127, 127, \
+/*176 ~183 */ 75, 75, 127, 127, 7, 111, 7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127, 6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+ IRQ_SW_LISR1_CODE
+ IRQ_SW_LISR2_CODE
+ IRQ_SW_LISR3_CODE
+ IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~223 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*224 ~231 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*232 ~239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~255 */ 0, 0, 0, 0, 0, 0, 0, 0
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 4, 1, 1, 1, 1, 1, 0, \
+ /* 8 ~ 15 */ 1, 1, 17, 4, 4, 0, 4, 4, \
+ /* 16 ~ 23 */ 4, 1, 1, 4, 4, 4, 4, 4, \
+ /* 24 ~ 31 */ 4, 4, 1, 4, 4, 4, 4, 4, \
+ /* 32 ~ 39 */ 0, 5, 0, 4, 5, 4, 4, 4, \
+ /* 40 ~ 47 */ 4, 0, 1, 1, 1, 3, 4, 4, \
+ /* 48 ~ 55 */ 4, 4, 0, 0, 4, 4, 4, 4, \
+ /* 56 ~ 63 */ 4, 4, 4, 4, 5, 5, 5, 5, \
+ /* 64 ~ 71 */ 1, 3, 0, 4, 4, 4, 4, 4, \
+ /* 72 ~ 79 */ 4, 4, 4, 4, 4, 5, 4, 4, \
+ /* 80 ~ 87 */ 3, 4, 4, 0, 1, 1, 4, 4, \
+ /* 88 ~ 95 */ 1, 1, 1, 1, 1, 5, 5, 3, \
+ /* 96 ~103 */ 1, 3, 1, 4, 3, 1, 1, 1, \
+ /*104 ~111 */ 3, 3, 3, 0, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 3, 1, 1, 0, 4, 4, 1, \
+ /*120 ~127 */ 1, 1, 1, 1, 1, 1, 1, 0, \
+ /*128 ~135 */ 4, 4, 0, 4, 4, 4, 4, 4, \
+ /*136 ~143 */ 1, 1, 3, 4, 4, 4, 4, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 2, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 6, 5, 4, 1, 0, 0, \
+ /*168 ~175 */ 1, 2, 3, 1, 5, 16, 0, 2, \
+ /*176 ~183 */ 1, 1, 0, 2, 0, 1, 2, 3, \
+ /*184 ~191 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*192 ~199 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*200 ~207 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*208 ~215 */ 0, 1, 0, 1, 0, 1, 2, 3, \
+ /*216 ~223 */ 2, 3, 2, 3, 4, 4, 4, 4, \
+ /*224 ~231 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*232 ~239 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*240 ~247 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*248 ~255 */ 4, 4, 4, 4, 4, 4, 4, 4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xE, \
+ /* Group1(1) */ 0xD, \
+ /* Group2(2) */ 0xB, \
+ /* Group3(3) */ 0x7, \
+ /* Group4(0,2) */ 0xA, \
+ /* Group5(0,1,2,3) */ 0x0, \
+ /* Group6(1,3) */ 0x5, \
+ /* Group7 */ 0xF, \
+ /* Group8 */ 0xF, \
+ /* Group9 */ 0xF, \
+ /* Group10 */ 0xF, \
+ /* Group11 */ 0xF, \
+ /* Group12 */ 0xF, \
+ /* Group13 */ 0xF, \
+ /* Group14*/ 0xF, \
+ /* Group15 */ 0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+ /* Group0(exception usage) */ 0xF, \
+ /* Group1 */ 0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x040627FD, \
+ /* 32-63 */ 0xF00C3E17, \
+ /* 64-95 */ 0xFF392007, \
+ /* 96-127 */ 0xFF9FFFF7, \
+ /* 128-159 */ 0xFFFF8704, \
+ /* 160-191 */ 0x00FFDFFF, \
+ /* 192-223 */ 0x0FFF0000, \
+ /* 224-255 */ 0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0xF0000012, \
+ /* 64-95 */ 0x60002000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x0000101C, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00002000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+#define INTERRUPT_HRT_MT \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00000000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+ /* VPE0 */ 0xFFFFFFFF,\
+ /* VPE1 */ 0xFFFFFFFF,\
+ /* VPE2 */ 0xFFFFFFFF,\
+ /* VPE3 */ 0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_DORMANT = 0,
+ VPE_STATUS_LISR_HIGHEST = 1,
+ VPE_STATUS_LISR_LOWEST = 127,
+ VPE_STATUS_HISR_TASK_HIGHEST = 128,
+ VPE_STATUS_HISR_TASK_LOWEST = 386,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_TOPSM = IRQ_TOPSM_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+ IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_AP2MD_CCIF2_0 = IRQ_AP2MD_CCIF2_0_CODE,
+ IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+ IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+ IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+ IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+ IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+ IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+ IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+ IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+ IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+ IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+ IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+ IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+ IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+ IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+ IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+ IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+ IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+ IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+ IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+ IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+ IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+ IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+ IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+ IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+ IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+ IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+ MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+ GIC0_FDCInt = GIC0_FDCInt_CODE,
+ GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+ GIC0_PCInt = GIC0_PCInt_CODE,
+ GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+ GIC0_TimerInt = GIC0_TimerInt_CODE,
+ GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+ GIC1_FDCInt = GIC1_FDCInt_CODE,
+ GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+ GIC1_PCInt = GIC1_PCInt_CODE,
+ GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+ GIC1_TimerInt = GIC1_TimerInt_CODE,
+ GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ MCUMMU_INT = MCUMMU_INT_CODE,
+ SPRAM_DECERR = SPRAM_DECERR_CODE,
+ RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+ MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+ AP2MD_MSDC0 = AP2MD_MSDC0_CODE
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6765_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765_SW_Handle.h
new file mode 100644
index 0000000..dcb848d
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6765_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6765
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW interrupt for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE5 = HC Yang
+ SW_TRIGGER_CODE6 = HC Yang
+ SW_TRIGGER_CODE7 = Max Weng
+ SW_TRIGGER_CODE8 = Max Weng
+ SW_TRIGGER_CODE9 = Max Weng
+ SW_TRIGGER_CODE10 = Max Weng
+ SW_TRIGGER_CODE11 = Max Weng
+ SW_TRIGGER_CODE12 = Max Weng
+ SW_TRIGGER_CODE13 = Zengling Jin
+ SW_TRIGGER_CODE14 = Zengling Jin
+ SW_TRIGGER_CODE15 = Zengling Jin
+ SW_TRIGGER_CODE16 = Chuansheng Zhang
+ SW_TRIGGER_CODE17 = Chuansheng Zhang
+ SW_TRIGGER_CODE18 = Chuansheng Zhang
+ SW_TRIGGER_CODE19 = Chuansheng Zhang
+ SW_TRIGGER_CODE20 = Huei-Ya Chang
+ SW_TRIGGER_CODE21 = Qmei Yang
+ SW_TRIGGER_CODE22 = Tee-Yuen Chun
+ SW_TRIGGER_CODE23 = Yuni Chang
+ SW_TRIGGER_CODE24 = SY Yeh
+ SW_TRIGGER_CODE25 = Owen Ho
+ SW_TRIGGER_CODE26 = Owen Ho
+ SW_TRIGGER_CODE27 = Owen Ho
+ SW_TRIGGER_CODE28 = Owen Ho
+ SW_TRIGGER_CODE29 = Carl Kao
+ SW_TRIGGER_CODE30 = Wade Huang
+ SW_TRIGGER_CODE31 = Woody kuo
+ SW_TRIGGER_CODE32 = Jun-Ying Huang
+ SW_TRIGGER_CODE33 = Jun-Ying Huang
+ SW_TRIGGER_CODE34 = Weimin Zeng
+ SW_TRIGGER_CODE35 = Weimin Zeng
+ SW_TRIGGER_CODE36 = HW Jheng
+ SW_TRIGGER_CODE37 = HW Jheng
+ SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE42 =
+ SW_TRIGGER_CODE43 =
+ SW_TRIGGER_CODE44 =
+ SW_TRIGGER_CODE45 =
+ SW_TRIGGER_CODE46 =
+ SW_TRIGGER_CODE47 =
+ SW_TRIGGER_CODE48 =
+ SW_TRIGGER_CODE49 =
+ SW_TRIGGER_CODE50 =
+ SW_TRIGGER_CODE51 =
+ SW_TRIGGER_CODE52 =
+ SW_TRIGGER_CODE53 =
+ SW_TRIGGER_CODE54 =
+ SW_TRIGGER_CODE55 =
+ SW_TRIGGER_CODE56 =
+ SW_TRIGGER_CODE57 =
+ SW_TRIGGER_CODE58 =
+ SW_TRIGGER_CODE59 =
+ SW_TRIGGER_CODE60 =
+ SW_TRIGGER_CODE61 =
+ SW_TRIGGER_CODE62 =
+ SW_TRIGGER_CODE63 =
+ SW_TRIGGER_CODE64 =
+ */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6765 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771.h
new file mode 100644
index 0000000..e488ff6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6771.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6771_H__
+#define __INTRCTRL_MT6771_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (256)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TOPSM_CODE MD_IRQID_TOPSM
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBRP0_CODE MD_IRQID_TXBRP0
+#define IRQ_TXBRP1_CODE MD_IRQID_TXBRP1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_AP2MD_CCIF2_0_CODE MD_IRQID_AP2MD_CCIF2_0
+#define IRQ_USIP3_1_CODE MD_IRQID_USIP3_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_PTP_SLPCTL_EVENT_CODE MD_IRQID_PTP_SLPCTL_EVENT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_MDCIRQ_WDT0_CODE MD_IRQID_MDCIRQ_WDT0
+#define IRQ_MDCIRQ_WDT1_CODE MD_IRQID_MDCIRQ_WDT1
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_DCXO_RDY_WO_ACK_IRQ_CODE MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_TOP_PLL_DSNS_IRQ_CODE MD_IRQID_TOP_PLL_DSNS_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_USB_MCU_CODE MD_IRQID_SSUSB_USB_MCU
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_BR_DMA_IRQ_CODE MD_IRQID_BR_DMA_IRQ
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_MDL1_TOPSM_IRQ_CODE MD_IRQID_MDL1_TOPSM_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_FRAME_IRQ_CODE MD_IRQID_RTR_FRAME_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_MD_DVFS_CTRL_IRQ_CODE MD_IRQID_MD_DVFS_CTRL_IRQ
+#define IRQ_BSI_MM_I_IRQ_RFIC_CODE MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define IRQ_BSI_MM_I_IRQ_MIPI_CODE MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_SPM2MD_DVFS_MDPERISYS_CODE MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define IRQ_TXDFE_BB_IRQ_CODE MD_IRQID_TXDFE_BB_IRQ
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define GIC0_FDCInt_CODE MD_IRQID_GIC0_FDCInt
+#define GIC0_FDCInt_1_CODE MD_IRQID_GIC0_FDCInt_1
+#define GIC0_PCInt_CODE MD_IRQID_GIC0_PCInt
+#define GIC0_PCInt_1_CODE MD_IRQID_GIC0_PCInt_1
+#define GIC0_TimerInt_CODE MD_IRQID_GIC0_TimerInt
+#define GIC0_TimerInt_1_CODE MD_IRQID_GIC0_TimerInt_1
+#define GIC1_FDCInt_CODE MD_IRQID_GIC1_FDCInt
+#define GIC1_FDCInt_1_CODE MD_IRQID_GIC1_FDCInt_1
+#define GIC1_PCInt_CODE MD_IRQID_GIC1_PCInt
+#define GIC1_PCInt_1_CODE MD_IRQID_GIC1_PCInt_1
+#define GIC1_TimerInt_CODE MD_IRQID_GIC1_TimerInt
+#define GIC1_TimerInt_1_CODE MD_IRQID_GIC1_TimerInt_1
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define SPRAM_DECERR_CODE MD_IRQID_IA_DECERR
+#define RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define MDSM_CORE_PWR_CTRL_CODE MD_IRQID_MDSM_CORE_PWR_CTRL
+#define AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/* 0 ~ 7 */ 69, 127, 67, 68, 66, 38, 32, 61, \
+/* 8 ~ 15 */ 88, 78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110, 42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127, 6, 7, 127, 6, 127, 127, 127, \
+/* 40 ~ 47 */ 127, 71, 41, 39, 62, 45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127, 6, 6, 6, 6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */ 45, 127, 127, 127, 56, 54, 127, 115, \
+/* 88 ~ 95 */ 58, 36, 55, 33, 86, 6, 6, 51, \
+/* 96 ~103 */ 40, 47, 30, 127, 46, 43, 43, 43, \
+/*104 ~111 */ 46, 44, 28, 86, 27, 34, 35, 110, \
+/*112 ~119 */ 31, 49, 26, 64, 25, 127, 127, 59, \
+/*120 ~127 */ 110, 58, 29, 59, 59, 58, 29, 90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */ 70, 77, 44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110, 7, 7, 76, 71, 77, \
+/*152 ~159 */ 50, 51, 52, 79, 76, 77, 39, 72, \
+/*160 ~167 */ 74, 75, 48, 127, 127, 63, 8, 127, \
+/*168 ~175 */ 110, 127, 110, 110, 6, 127, 127, 127, \
+/*176 ~183 */ 75, 75, 127, 127, 7, 111, 7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127, 6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+ IRQ_SW_LISR1_CODE
+ IRQ_SW_LISR2_CODE
+ IRQ_SW_LISR3_CODE
+ IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~223 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*224 ~231 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*232 ~239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~255 */ 0, 0, 0, 0, 0, 0, 0, 0
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 4, 1, 1, 1, 1, 1, 0, \
+ /* 8 ~ 15 */ 1, 1, 17, 4, 4, 0, 4, 4, \
+ /* 16 ~ 23 */ 4, 1, 1, 4, 4, 4, 4, 4, \
+ /* 24 ~ 31 */ 4, 4, 1, 4, 4, 4, 4, 4, \
+ /* 32 ~ 39 */ 0, 5, 0, 4, 5, 4, 4, 4, \
+ /* 40 ~ 47 */ 4, 0, 1, 1, 1, 3, 4, 4, \
+ /* 48 ~ 55 */ 4, 4, 0, 0, 4, 4, 4, 4, \
+ /* 56 ~ 63 */ 4, 4, 4, 4, 5, 5, 5, 5, \
+ /* 64 ~ 71 */ 1, 3, 0, 4, 4, 4, 4, 4, \
+ /* 72 ~ 79 */ 4, 4, 4, 4, 4, 5, 4, 4, \
+ /* 80 ~ 87 */ 3, 4, 4, 0, 1, 1, 4, 4, \
+ /* 88 ~ 95 */ 1, 1, 1, 1, 1, 5, 5, 3, \
+ /* 96 ~103 */ 1, 3, 1, 4, 3, 1, 1, 1, \
+ /*104 ~111 */ 3, 3, 3, 0, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 3, 1, 1, 0, 4, 4, 1, \
+ /*120 ~127 */ 1, 1, 1, 1, 1, 1, 1, 0, \
+ /*128 ~135 */ 4, 4, 0, 4, 4, 4, 4, 4, \
+ /*136 ~143 */ 1, 1, 3, 4, 4, 4, 4, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 2, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 6, 5, 4, 1, 0, 0, \
+ /*168 ~175 */ 1, 2, 3, 1, 5, 16, 0, 2, \
+ /*176 ~183 */ 1, 1, 0, 2, 0, 1, 2, 3, \
+ /*184 ~191 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*192 ~199 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*200 ~207 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*208 ~215 */ 0, 1, 0, 1, 0, 1, 2, 3, \
+ /*216 ~223 */ 2, 3, 2, 3, 4, 4, 4, 4, \
+ /*224 ~231 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*232 ~239 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*240 ~247 */ 4, 4, 4, 4, 4, 4, 4, 4, \
+ /*248 ~255 */ 4, 4, 4, 4, 4, 4, 4, 4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xE, \
+ /* Group1(1) */ 0xD, \
+ /* Group2(2) */ 0xB, \
+ /* Group3(3) */ 0x7, \
+ /* Group4(0,2) */ 0xA, \
+ /* Group5(0,1,2,3) */ 0x0, \
+ /* Group6(1,3) */ 0x5, \
+ /* Group7 */ 0xF, \
+ /* Group8 */ 0xF, \
+ /* Group9 */ 0xF, \
+ /* Group10 */ 0xF, \
+ /* Group11 */ 0xF, \
+ /* Group12 */ 0xF, \
+ /* Group13 */ 0xF, \
+ /* Group14*/ 0xF, \
+ /* Group15 */ 0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+ /* Group0(exception usage) */ 0xF, \
+ /* Group1 */ 0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x040627FD, \
+ /* 32-63 */ 0xF00C3E17, \
+ /* 64-95 */ 0xFF392007, \
+ /* 96-127 */ 0xFF9FFFF7, \
+ /* 128-159 */ 0xFFFF8704, \
+ /* 160-191 */ 0x00FFDFFF, \
+ /* 192-223 */ 0x0FFF0000, \
+ /* 224-255 */ 0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0xF0000012, \
+ /* 64-95 */ 0x60002000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x0000101C, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+ /* 0-31 */ 0x00000400, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00002000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+#define INTERRUPT_HRT_MT \
+ /* 0-31 */ 0x00000000, \
+ /* 32-63 */ 0x00000000, \
+ /* 64-95 */ 0x00000000, \
+ /* 96-127 */ 0x00000000, \
+ /* 128-159 */ 0x00000000, \
+ /* 160-191 */ 0x00000000, \
+ /* 192-223 */ 0x00000000, \
+ /* 224-255 */ 0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+ /* VPE0 */ 0xFFFFFFFF,\
+ /* VPE1 */ 0xFFFFFFFF,\
+ /* VPE2 */ 0xFFFFFFFF,\
+ /* VPE3 */ 0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_DORMANT = 0,
+ VPE_STATUS_LISR_HIGHEST = 1,
+ VPE_STATUS_LISR_LOWEST = 127,
+ VPE_STATUS_HISR_TASK_HIGHEST = 128,
+ VPE_STATUS_HISR_TASK_LOWEST = 386,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_TOPSM = IRQ_TOPSM_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+ IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_AP2MD_CCIF2_0 = IRQ_AP2MD_CCIF2_0_CODE,
+ IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+ IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+ IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+ IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+ IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+ IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+ IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+ IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+ IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+ IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+ IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+ IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+ IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+ IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+ IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+ IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+ IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+ IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+ IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+ IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+ IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+ IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+ IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+ IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+ IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+ IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+ MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+ GIC0_FDCInt = GIC0_FDCInt_CODE,
+ GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+ GIC0_PCInt = GIC0_PCInt_CODE,
+ GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+ GIC0_TimerInt = GIC0_TimerInt_CODE,
+ GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+ GIC1_FDCInt = GIC1_FDCInt_CODE,
+ GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+ GIC1_PCInt = GIC1_PCInt_CODE,
+ GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+ GIC1_TimerInt = GIC1_TimerInt_CODE,
+ GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ MCUMMU_INT = MCUMMU_INT_CODE,
+ SPRAM_DECERR = SPRAM_DECERR_CODE,
+ RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+ MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+ AP2MD_MSDC0 = AP2MD_MSDC0_CODE
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6771_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771_SW_Handle.h
new file mode 100644
index 0000000..7acf2d4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6771_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6771
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW interrupt for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+ SW_TRIGGER_CODE5 = HC Yang
+ SW_TRIGGER_CODE6 = HC Yang
+ SW_TRIGGER_CODE7 = Max Weng
+ SW_TRIGGER_CODE8 = Max Weng
+ SW_TRIGGER_CODE9 = Max Weng
+ SW_TRIGGER_CODE10 = Max Weng
+ SW_TRIGGER_CODE11 = Max Weng
+ SW_TRIGGER_CODE12 = Max Weng
+ SW_TRIGGER_CODE13 = Zengling Jin
+ SW_TRIGGER_CODE14 = Zengling Jin
+ SW_TRIGGER_CODE15 = Zengling Jin
+ SW_TRIGGER_CODE16 = Chuansheng Zhang
+ SW_TRIGGER_CODE17 = Chuansheng Zhang
+ SW_TRIGGER_CODE18 = Chuansheng Zhang
+ SW_TRIGGER_CODE19 = Chuansheng Zhang
+ SW_TRIGGER_CODE20 = Huei-Ya Chang
+ SW_TRIGGER_CODE21 = Qmei Yang
+ SW_TRIGGER_CODE22 = Tee-Yuen Chun
+ SW_TRIGGER_CODE23 = Yuni Chang
+ SW_TRIGGER_CODE24 = SY Yeh
+ SW_TRIGGER_CODE25 = Owen Ho
+ SW_TRIGGER_CODE26 = Owen Ho
+ SW_TRIGGER_CODE27 = Owen Ho
+ SW_TRIGGER_CODE28 = Owen Ho
+ SW_TRIGGER_CODE29 = Carl Kao
+ SW_TRIGGER_CODE30 = Wade Huang
+ SW_TRIGGER_CODE31 = Woody kuo
+ SW_TRIGGER_CODE32 = Jun-Ying Huang
+ SW_TRIGGER_CODE33 = Jun-Ying Huang
+ SW_TRIGGER_CODE34 = Weimin Zeng
+ SW_TRIGGER_CODE35 = Weimin Zeng
+ SW_TRIGGER_CODE36 = HW Jheng
+ SW_TRIGGER_CODE37 = HW Jheng
+ SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+ SW_TRIGGER_CODE42 =
+ SW_TRIGGER_CODE43 =
+ SW_TRIGGER_CODE44 =
+ SW_TRIGGER_CODE45 =
+ SW_TRIGGER_CODE46 =
+ SW_TRIGGER_CODE47 =
+ SW_TRIGGER_CODE48 =
+ SW_TRIGGER_CODE49 =
+ SW_TRIGGER_CODE50 =
+ SW_TRIGGER_CODE51 =
+ SW_TRIGGER_CODE52 =
+ SW_TRIGGER_CODE53 =
+ SW_TRIGGER_CODE54 =
+ SW_TRIGGER_CODE55 =
+ SW_TRIGGER_CODE56 =
+ SW_TRIGGER_CODE57 =
+ SW_TRIGGER_CODE58 =
+ SW_TRIGGER_CODE59 =
+ SW_TRIGGER_CODE60 =
+ SW_TRIGGER_CODE61 =
+ SW_TRIGGER_CODE62 =
+ SW_TRIGGER_CODE63 =
+ SW_TRIGGER_CODE64 =
+ */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6771 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..023efdd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_SW_Handle.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6763)
+ #include "intrCtrl_MT6763_SW_Handle.h"
+#endif
+
+#if defined(MT6739)
+ #include "intrCtrl_MT6739_SW_Handle.h"
+#endif
+
+#if defined(MT6771)
+ #include "intrCtrl_MT6771_SW_Handle.h"
+#endif
+
+#if defined(MT6765)
+ #include "intrCtrl_MT6765_SW_Handle.h"
+#endif
+
+#if defined(MT6761)
+ #include "intrCtrl_MT6761_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid.h b/mcu/interface/driver/devdrv/cirq/md93/irqid.h
new file mode 100644
index 0000000..5213110
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid.h
@@ -0,0 +1,23 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6763)
+ #include "irqid_MT6763.h"
+#endif
+
+#if defined(MT6739)
+ #include "irqid_MT6739.h"
+#endif
+
+#if defined(MT6771)
+ #include "irqid_MT6771.h"
+#endif
+
+#if defined(MT6765)
+ #include "irqid_MT6765.h"
+#endif
+
+#if defined(MT6761)
+ #include "irqid_MT6761.h"
+#endif
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_ELBRUS.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_ELBRUS.h
new file mode 100644
index 0000000..30fe5cb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_ELBRUS.h
@@ -0,0 +1,365 @@
+#ifndef __ELBRUS_IRQID_H__
+#define __ELBRUS_IRQID_H__
+
+
+//ELBURS MDCIRQ IRQID base on 0907
+#define MD_IRQID_OST 0
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 1
+#define MD_IRQID_LMAC_RAR 2
+#define MD_IRQID_LMAC_EAR 3
+#define MD_IRQID_MDWDT 4
+//#define MD_IRQID_NFI 5
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 5
+#define MD_IRQID_L2COPRO 6
+#define MD_IRQID_GPTM1 7
+#define MD_IRQID_GPTM2 8
+#define MD_IRQID_GPTM3 9
+#define MD_IRQID_GPTM4 10
+#define MD_IRQID_GPTM5 11
+#define MD_IRQID_GPTM6 12
+#define MD_IRQID_UART_MD0 13
+#define MD_IRQID_UART_MD1 14
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 15
+#define MD_IRQID_I2C_0 16
+#define MD_IRQID_USIM0 17
+#define MD_IRQID_USIM1 18
+#define MD_IRQID_UART_MD2 19
+#define MD_IRQID_MDGDMA0 20
+#define MD_IRQID_MDGDMA1 21
+#define MD_IRQID_MDGDMA2 22
+#define MD_IRQID_MDGDMA3 23
+#define MD_IRQID_EINT0 24
+#define MD_IRQID_EINT1 25
+#define MD_IRQID_EINT2 26
+#define MD_IRQID_EINT3 27
+#define MD_IRQID_EINT_SHARE 28
+#define MD_IRQID_BUS_ERR 29
+#define MD_IRQID_TOPSM 30
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 31
+#define MD_IRQID_C2K_ST_SLOT_INT 32
+#define MD_IRQID_C2K_ST_HALF_SLOT_INT 33
+#define MD_IRQID_C2K_MPDU_INT 34
+#define MD_IRQID_C2K_M2C_DAT_WRDY_INT 35
+#define MD_IRQID_C2K_M2C_CTL_WRDY_INT 36
+#define MD_IRQID_C2K_M2C_FST_WRDY_INT 37
+#define MD_IRQID_C2K_NIRQ 38
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 41
+//#define MD_IRQID_PMU 42
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 42
+#define MD_IRQID_ECT 43
+//#define MD_IRQID_PS_L1_WDT_INT 44
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 44
+#define MD_IRQID_PTP_THERM_INT_INT 45
+#define MD_IRQID_CLDMA 46
+#define MD_IRQID_MDINFRA_ABM_INT 47
+#define MD_IRQID_MDLITE_GPTM_INT 48
+#define MD_IRQID_AP2MD_PCCIF_IRQ 49
+#define MD_IRQID_PCCIF_AP_MD 50
+#define MD_IRQID_CCIF2_MD_IRQ 51
+#define MD_IRQID_CCIF2_MD_EVENT 52
+//#define MD_IRQID_SPI 53
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 53
+#define MD_IRQID_MDINFRA_ABM_ERROR_INT 54
+#define MD_IRQID_USB3 55
+//#define MD_IRQID_SDIO 56
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 56
+#define MD_IRQID_MSDC0 57
+#define MD_IRQID_EHPI0 58
+//#define MD_IRQID_RTC 59
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 59
+//#define MD_IRQID_SOE 60
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 60
+#define MD_IRQID_MSDC1 61
+//#define MD_IRQID_PFC_INT_LV 62
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 62
+//#define MD_IRQID_AUXACD 63
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 63
+//#define MD_IRQID_LED 64
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 64
+#define MD_IRQID_BT_CVSD 65
+#define MD_IRQID_ELMTOP_IOCU_IRQ 66
+#define MD_IRQID_ELMTOP_EMI_IRQ 67
+#define MD_IRQID_ULS_INTR 68
+#define MD_IRQID_SHARE_D12MINT1 69
+#define MD_IRQID_SHARE_D12MINT2 70
+#define MD_IRQID_SHARE_D12MINT3 71
+//#define MD_IRQID_LTE_TIMER_EMAC_SF_TICK 72
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 72
+#define MD_IRQID_IRDBG_MCU_INT 73
+#define MD_IRQID_LTE_MODEMSYS_TRACE_IRQ 74
+#define MD_IRQID_SI_CM_ERR 75
+#define MD_IRQ_ID_L1SYS_SLV_DECERR_IRQ_LEVEL 76
+#define MD_IRQID_ABM_INT 77
+#define MD_IRQID_ABM_ERROR_INT 78
+#define MD_IRQID_MO_WERR_INT 79
+#define MD_IRQID_BC_IRQ 80
+#define MD_IRQID_UEA_UIA_IRQ 81
+#define MD_IRQID_UPA_ACC_IRQ 82
+#define MD_IRQID_DPA_ACC_IRQ 83
+#define MD_IRQID_C2K_MD_INT_0 84
+#define MD_IRQID_C2K_MD_INT_1 85
+#define MD_IRQID_C2K_MD_INT_2 86
+#define MD_IRQID_C2K_MD_INT_3 87
+#define MD_IRQID_C2K_L1_INT_0 88
+#define MD_IRQID_C2K_L1_INT_1 89
+#define MD_IRQID_C2K_L1_INT_2 90
+#define MD_IRQID_C2K_L1_INT_3 91
+#define MD_IRQID_C2K_L1_INT_4 92
+#define MD_IRQID_C2K_L1_INT_5 93
+#define MD_IRQID_C2K_L1_INT_6 94
+#define MD_IRQID_C2K_L1_INT_7 95
+#define MD_IRQID_PB0_PM_CNTRSAT_INT_0 96
+#define MD_IRQID_PB0_PM_CNTRSAT_INT_1 97
+#define MD_IRQID_PB1_PM_CNTRSAT_INT_0 98
+#define MD_IRQID_PB1_PM_CNTRSAT_INT_1 99
+#define MD_IRQID_PB2_PM_CNTRSAT_INT_0 100
+#define MD_IRQID_PB2_PM_CNTRSAT_INT_1 101
+#define MD_IRQID_PB3_PM_CNTRSAT_INT_0 102
+#define MD_IRQID_PB3_PM_CNTRSAT_INT_1 103
+#define MD_IRQID_PTP_FSM_INT 104
+#define MD_IRQID_PTP_SLPCTL_EVENT 105
+#define MD_IRQID_PCCIF_MDMCU0_IRQ 106
+#define MD_IRQID_PCCIF_MDMCU1_IRQ 107
+#define MD_IRQID_ELM_DMA_IRQ 108
+#define MD_IRQID_ELM_L1_IRQ 109
+#define MD_IRQID_MDCIRQ_IRQ_LV 110
+#define MD_IRQID_LOGGDMA_IRQ0_LV 111
+#define MD_IRQID_SOE_INT_LV 112
+#define MD_IRQID_TRACE_INT 113
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS 114
+#define MD_IRQID_SI_CM_PCINT 115
+#define MD_IRQID_MDMCU_MACRO_BUS_INT 116
+#define MD_IRQID_MDMCU_PERI_BUS_INT 117
+#define MD_IRQID_MM_WERR_INT 118
+#define MD_IRQID_PLL_GEARHP_RDY 119
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ 120
+#define MD_IRQID_PLL_REQ_WO_DCXO_IRQ 121
+#define MD_IRQID_TOP_PLL_DSNS_IRQ 122
+#define MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_0 123
+#define MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_1 124
+#define MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_2 125
+#define MD_IRQID_CMP_CMTDB_IRQ 126
+#define MD_IRQID_CS_SRAM_CTRL_IRQ 127
+#define MD_IRQID_CSTXB_FDD_CS_IRQ 128
+#define MD_IRQID_CSTXB_TDD_CS_IRQ 129
+#define MD_IRQID_DFE0_CMIF_M2C_IRQ_0 130
+#define MD_IRQID_DFE0_CMIF_M2C_IRQ_1 131
+#define MD_IRQID_DFE0_CMIF_M2C_IRQ_2 132
+#define MD_IRQID_DFE0_PCC_TOP_0_FULL_IRQ 133
+#define MD_IRQID_DFE0_PCC_TOP_1_FULL_IRQ 134
+#define MD_IRQID_DFE0_RXDFEIF_L_IRQ 135
+#define MD_IRQID_DFE0_TCU_L1D_1_IRQ 136
+#define MD_IRQID_DFE0_TCU_L1D_2_IRQ 137
+#define MD_IRQID_DFE1_CMIF_M2C_IRQ_0 138
+#define MD_IRQID_DFE1_CMIF_M2C_IRQ_1 139
+#define MD_IRQID_DFE1_CMIF_M2C_IRQ_2 140
+#define MD_IRQID_DFE1_PCC_TOP_0_FULL_IRQ 141
+#define MD_IRQID_DFE1_PCC_TOP_1_FULL_IRQ 142
+#define MD_IRQID_DFE1_RXDFEIF_L_IRQ 143
+#define MD_IRQID_GDMA_IRQ 144
+#define MD_IRQID_ICC_DSP_IRQ_0 145
+#define MD_IRQID_ICC_DSP_IRQ_1 146
+#define MD_IRQID_ICC_SRAM_CTRL_IRQ 147
+#define MD_IRQID_IDC_PM_INT 148
+#define MD_IRQID_IDC_UART_IRQ 149
+#define MD_IRQID_IMC_DSP_IRQ_0 150
+#define MD_IRQID_IMC_DSP_IRQ_1 151
+#define MD_IRQID_IMC_MMU_IRQ_0 152
+#define MD_IRQID_IMC_MMU_IRQ_1 153
+#define MD_IRQID_IMC_RXDMP_IRQ 154
+#define MD_IRQID_IMC_RXTDB_IRQ 155
+#define MD_IRQID_IMC_SRAM_CTRL_IRQ 156
+#define MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_0 157
+#define MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_1 158
+#define MD_IRQID_INR_TD1_BRP_DMA_IRQ 159
+#define MD_IRQID_INR_TD1_CSCE_IRQ 160
+#define MD_IRQID_INR_TD1_DFE_BRG_IRQ 161
+#define MD_IRQID_INR_TD1_JDA_IRQ 162
+#define MD_IRQID_INR_TD1_PP_IRQ 163
+#define MD_IRQID_INR_TD2_BRP_DMA_IRQ 164
+#define MD_IRQID_INR_TD2_CSCE_IRQ 165
+#define MD_IRQID_INR_TD2_DFE_BRG_IRQ 166
+#define MD_IRQID_INR_TD2_JDA_IRQ 167
+#define MD_IRQID_TD2_PP_IRQ 168
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 169
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 170
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 171
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 172
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 173
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 174
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 175
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 176
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 177
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 178
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 179
+#define MD_IRQID_LTEL1_CS_IRQ 180
+#define MD_IRQID_LTXB0_BSI_L_AB_IRQ 181
+#define MD_IRQID_LTXB0_BSI_L_C_IRQ 182
+#define MD_IRQID_LTXB0_BSI_L_D_IRQ 183
+#define MD_IRQID_LTXB0_TXENC_ERROR_IRQ 184
+#define MD_IRQID_LTXB1_BSI_L_AB_IRQ 185
+#define MD_IRQID_LTXB1_BSI_L_C_IRQ 186
+#define MD_IRQID_LTXB1_BSI_L_D_IRQ 187
+#define MD_IRQID_LTXB1_TXENC_ERROR_IRQ 188
+#define MD_IRQID_MMU_SRAM_CTRL_IRQ 189
+#define MD_IRQID_MPC_DSP_IRQ_0 190
+#define MD_IRQID_MPC_DSP_IRQ_1 191
+#define MD_IRQID_MPC_SRAM_CTRL_IRQ 192
+#define MD_IRQID_TDMA_CTIRQ1 193
+#define MD_IRQID_TDMA_CTIRQ2 194
+#define MD_IRQID_TDMA_CTIRQ3 195
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 196
+#define MD_IRQID_FREQM_IRQ 197
+#define MD_IRQID_MDL1_TOPSM_IRQ 198
+#define MD_IRQID_RTR_FRAME_IRQ 199
+#define MD_IRQID_RTR_SLT_IRQ 200
+#define MD_IRQID_WTIMER_IRQ 201
+#define MD_IRQID_TDD_WAKEUP_IRQ 202
+#define MD_IRQID_TDMA_WAKEUP_IRQ 203
+#define MD_IRQID_MODEML1_DVFS_IRQ 204
+#define MD_IRQID_MODEML1_DVFS_MIPS_DVS_IRQ 205
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 206
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 207
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 208
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 209
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 210
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 211
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 212
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 213
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 214
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 215
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 216
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 217
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 218
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 219
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 220
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 221
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 222
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 223
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 224
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 225
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 226
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 227
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 228
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 229
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_0 230
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_1 231
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_2 232
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_3 233
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_4 234
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_5 235
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_6 236
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_7 237
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_8 238
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_9 239
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_10 240
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_11 241
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_12 242
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_13 243
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_14 244
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_15 245
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_16 246
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_17 247
+#define MD_IRQID_L1_GPTM1 248
+#define MD_IRQID_L1_GPTM2 249
+#define MD_IRQID_L1_GPTM3 250
+#define MD_IRQID_L1_GPTM4 251
+#define MD_IRQID_L1_GPTM5 252
+#define MD_IRQID_L1_GPTM6 253
+#define MD_IRQID_L1LITE_GPTM_INT 254
+#define MD_IRQID_PPC_CIRQ 255
+
+
+//GIC ID
+#define MD_GICID_VPE0IRQ 0
+#define MD_GICID_VPE1IRQ 1
+#define MD_GICID_VPE2IRQ 2
+#define MD_GICID_VPE3IRQ 3
+#define MD_GICID_VPE4IRQ 4
+#define MD_GICID_VPE5IRQ 5
+#define MD_GICID_VPE6IRQ 6
+#define MD_GICID_VPE7IRQ 7
+#define MD_GICID_VPE0NMI 8
+#define MD_GICID_VPE1NMI 9
+#define MD_GICID_VPE2NMI 10
+#define MD_GICID_VPE3NMI 11
+#define MD_GICID_VPE4NMI 12
+#define MD_GICID_VPE5NMI 13
+#define MD_GICID_VPE6NMI 14
+#define MD_GICID_VPE7NMI 15
+#define MD_GICID_VPE0WEDGE 16
+#define MD_GICID_VPE1WEDGE 17
+#define MD_GICID_VPE2WEDGE 18
+#define MD_GICID_VPE3WEDGE 19
+#define MD_GICID_VPE4WEDGE 20
+#define MD_GICID_VPE5WEDGE 21
+#define MD_GICID_VPE6WEDGE 22
+#define MD_GICID_VPE7WEDGE 23
+#define MD_GICID_VPE0YQ0 24
+#define MD_GICID_VPE0YQ1 25
+#define MD_GICID_VPE0YQ2 26
+#define MD_GICID_VPE0YQ3 27
+#define MD_GICID_VPE1YQ0 28
+#define MD_GICID_VPE1YQ1 29
+#define MD_GICID_VPE1YQ2 30
+#define MD_GICID_VPE1YQ3 31
+#define MD_GICID_VPE2YQ0 32
+#define MD_GICID_VPE2YQ1 33
+#define MD_GICID_VPE2YQ2 34
+#define MD_GICID_VPE2YQ3 35
+#define MD_GICID_VPE3YQ0 36
+#define MD_GICID_VPE3YQ1 37
+#define MD_GICID_VPE3YQ2 38
+#define MD_GICID_VPE3YQ3 39
+#define MD_GICID_VPE4YQ0 40
+#define MD_GICID_VPE4YQ1 41
+#define MD_GICID_VPE4YQ2 42
+#define MD_GICID_VPE4YQ3 43
+#define MD_GICID_VPE5YQ0 44
+#define MD_GICID_VPE5YQ1 45
+#define MD_GICID_VPE5YQ2 46
+#define MD_GICID_VPE5YQ3 47
+#define MD_GICID_VPE6YQ0 48
+#define MD_GICID_VPE6YQ1 49
+#define MD_GICID_VPE6YQ2 50
+#define MD_GICID_VPE6YQ3 51
+#define MD_GICID_VPE7YQ0 52
+#define MD_GICID_VPE7YQ1 53
+#define MD_GICID_VPE7YQ2 54
+#define MD_GICID_VPE7YQ3 55
+#define MD_GICID_RESERVED0 56
+#define MD_GICID_RESERVED1 57
+#define MD_GICID_RESERVED2 58
+#define MD_GICID_RESERVED3 59
+#define MD_GICID_RESERVED4 60
+#define MD_GICID_RESERVED5 61
+#define MD_GICID_RESERVED6 62
+#define MD_GICID_RESERVED7 63
+
+/*
+//#define TEST_VPE0_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define TEST_VPE0_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define TEST_VPE0_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+//#define TEST_VPE1_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+//#define TEST_VPE1_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define TEST_VPE1_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+//#define TEST_VPE2_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define TEST_VPE2_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define TEST_VPE2_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+//#define TEST_VPE3_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+//#define TEST_VPE3_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define TEST_VPE3_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+//#define TEST_VPE4_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define TEST_VPE4_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define TEST_VPE4_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+//#define TEST_VPE5_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+//#define TEST_VPE5_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define TEST_VPE5_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+//#define TEST_VPE6_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+//#define TEST_VPE6_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define TEST_VPE6_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+//#define TEST_VPE7_int_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+//#define TEST_VPE7_dummy_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define TEST_VPE7_OS_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+*/
+#endif /*end of __ELBRUS_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6739.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6739.h
new file mode 100644
index 0000000..f464591
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6739.h
@@ -0,0 +1,245 @@
+#ifndef __MT6739_IRQID_H__
+#define __MT6739_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_TOPSM 16
+#define MD_IRQID_MDGDMA0 17
+#define MD_IRQID_MDGDMA1 18
+#define MD_IRQID_MDGDMA2 19
+#define MD_IRQID_MDGDMA3 20
+#define MD_IRQID_EINT0 21
+#define MD_IRQID_EINT1 22
+#define MD_IRQID_EINT2 23
+#define MD_IRQID_EINT_SHARE 24
+#define MD_IRQID_BUS_ERR 25
+#define MD_IRQID_TXBRP0 26
+#define MD_IRQID_TXBRP1 27
+#define MD_IRQID_TXCRP 28
+#define MD_IRQ_ID_MML2_HRT 29
+#define MD_IRQ_ID_MML2_NOTIF 30
+#define MD_IRQ_ID_MML2_EXCEP 31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 32
+#define MD_IRQID_ECT 33
+#define MD_IRQID_PTP_THERM_INT_INT 34
+#define MD_IRQID_CLDMA 35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 36
+#define MD_IRQID_ELM_DMA_IRQ 37
+#define MD_IRQID_SOE 38
+#define MD_IRQID_ULSP_LOG_MD_INT 39
+#define MD_IRQID_ULSP_LOG_DSP_INT 40
+#define MD_IRQID_USIP0_0 41
+#define MD_IRQID_USIP1_0 42
+#define MD_IRQID_USIP2_0 43
+#define MD_IRQID_USIP3_0 44
+#define MD_IRQID_USIP0_1 45
+#define MD_IRQID_USIP1_1 46
+#define MD_IRQID_USIP2_1 47
+#define MD_IRQID_USIP3_1 48
+#define MD_IRQID_SI_CM_ERR 49
+#define MD_IRQID_ABM_INT 50
+#define MD_IRQID_ABM_ERROR_INT 51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 52
+#define MD_IRQID_ELMTOP_EMI_IRQ 53
+#define MD_IRQID_PPPHA_ENC0_INT 54
+#define MD_IRQID_PPPHA_ENC1_INT 55
+#define MD_IRQID_PPPHA_DEC0_INT 56
+#define MD_IRQID_PPPHA_DEC1_INT 57
+#define MD_IRQID_PTP_FSM_INT 58
+#define MD_IRQID_PTP_SLPCTL_EVENT 59
+#define MD_IRQID_IEBIT_CHECK_IRQ0 60
+#define MD_IRQID_IEBIT_CHECK_IRQ1 61
+#define MD_IRQID_IEBIT_CHECK_IRQ2 62
+#define MD_IRQID_IEBIT_CHECK_IRQ3 63
+#define MD_IRQID_MDCIRQ_WDT0 64
+#define MD_IRQID_MDCIRQ_WDT1 65
+#define MD_IRQID_TRACE_INT 66
+#define MD_IRQID_SI_CM_PCINT 67
+#define MD_IRQID_PLL_GEARHP_RDY 68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ 69
+#define MD_IRQID_REQ_ABNORM_IRQ 70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ 71
+#define MD_IRQID_BT_CVSD 72
+#define MD_IRQID_SSUSB_USB_MCU 73
+#define MD_IRQID_SSUSB_DEV 74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 75
+#define MD_IRQID_AP2MD_CCIF0_0 76
+#define MD_IRQID_AP2MD_CCIF0_1 77
+#define MD_IRQID_AP2MD_CCIF1_0 78
+#define MD_IRQID_AP2MD_CCIF1_1 79
+#define MD_IRQID_RXDFE_RXK_READBACK 80
+#define MD_IRQID_BR_DMA_IRQ 81
+#define MD_IRQID_IDC_PM_INT 82
+#define MD_IRQID_IDC_UART_IRQ 83
+#define MD_IRQID_MDRTT 84
+#define MD_IRQID_MDEVDO 85
+#define MD_IRQID_MDM2C_U3G 86
+#define MD_IRQID_MDDFE_DUMP 87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 92
+#define MD_IRQID_BIGRAM_IRQ 93
+#define MD_IRQID_BR_BDGE_IRQ 94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 106
+#define MD_IRQID_MDL1_TOPSM_IRQ 107
+#define MD_IRQID_TDD_WAKEUP_IRQ 108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 110
+#define MD_IRQID_RTR_FRAME_IRQ 111
+#define MD_IRQID_RTR_SLT_0_IRQ 112
+#define MD_IRQID_RTR_SLT_1_IRQ 113
+#define MD_IRQID_FDD_SLP_IRQ 114
+#define MD_IRQID_TDMA_WAKEUP_IRQ 115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ 116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC 117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI 118
+#define MD_IRQID_ST1X_CPINT 119
+#define MD_IRQID_ST1x_HALF_CPINT 120
+#define MD_IRQID_ST1x_CFG_CPINT 121
+#define MD_IRQID_ST1x_WAKEUP_IRQ 122
+#define MD_IRQID_STDO_CPINT 123
+#define MD_IRQID_STDO_HALF_CPINT 124
+#define MD_IRQID_STDO_CFG_CPINT 125
+#define MD_IRQID_STDO_WAKEUP_IRQ 126
+#define MD_IRQID_FREQM_IRQ 127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS 128
+#define MD_IRQID_TXDFE_BB_IRQ 129
+#define MD_IRQID_PCC_TOP_FULL_IRQ 130
+#define MD_IRQID_GPTM1 131
+#define MD_IRQID_GPTM2 132
+#define MD_IRQID_GPTM3 133
+#define MD_IRQID_GPTM4 134
+#define MD_IRQID_GPTM5 135
+#define MD_IRQID_GPTM6 136
+#define MD_IRQID_GPTM7 137
+#define MD_IRQID_GPTM8 138
+#define MD_IRQID_GPTM9 139
+#define MD_IRQID_GPTM10 140
+#define MD_IRQID_GPTM11 141
+#define MD_IRQID_BUSMPU_IRQ 142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 206
+#define MD_IRQID_MCU_BUS_DECERR 207
+#define MD_IRQID_GIC0_FDCInt 208
+#define MD_IRQID_GIC0_FDCInt_1 209
+#define MD_IRQID_GIC0_PCInt 210
+#define MD_IRQID_GIC0_PCInt_1 211
+#define MD_IRQID_GIC0_TimerInt 212
+#define MD_IRQID_GIC0_TimerInt_1 213
+#define MD_IRQID_GIC1_FDCInt 214
+#define MD_IRQID_GIC1_FDCInt_1 215
+#define MD_IRQID_GIC1_PCInt 216
+#define MD_IRQID_GIC1_PCInt_1 217
+#define MD_IRQID_GIC1_TimerInt 218
+#define MD_IRQID_GIC1_TimerInt_1 219
+#define MD_IRQID_EINT3 220
+#define MD_IRQID_MCUMMU_INT 221
+#define MD_IRQID_IA_DECERR 222
+#define MD_IRQID_RMPU_CTIREIGIN 223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL 224
+#define MD_IRQID_AP2MD_MSDC0 225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6739_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6761.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6761.h
new file mode 100644
index 0000000..f19e600
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6761.h
@@ -0,0 +1,245 @@
+#ifndef __MT6761_IRQID_H__
+#define __MT6761_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_TOPSM 16
+#define MD_IRQID_MDGDMA0 17
+#define MD_IRQID_MDGDMA1 18
+#define MD_IRQID_MDGDMA2 19
+#define MD_IRQID_MDGDMA3 20
+#define MD_IRQID_EINT0 21
+#define MD_IRQID_EINT1 22
+#define MD_IRQID_EINT2 23
+#define MD_IRQID_EINT_SHARE 24
+#define MD_IRQID_BUS_ERR 25
+#define MD_IRQID_TXBRP0 26
+#define MD_IRQID_TXBRP1 27
+#define MD_IRQID_TXCRP 28
+#define MD_IRQ_ID_MML2_HRT 29
+#define MD_IRQ_ID_MML2_NOTIF 30
+#define MD_IRQ_ID_MML2_EXCEP 31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 32
+#define MD_IRQID_ECT 33
+#define MD_IRQID_PTP_THERM_INT_INT 34
+#define MD_IRQID_CLDMA 35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 36
+#define MD_IRQID_ELM_DMA_IRQ 37
+#define MD_IRQID_SOE 38
+#define MD_IRQID_ULSP_LOG_MD_INT 39
+#define MD_IRQID_ULSP_LOG_DSP_INT 40
+#define MD_IRQID_USIP0_0 41
+#define MD_IRQID_USIP1_0 42
+#define MD_IRQID_USIP2_0 43
+#define MD_IRQID_USIP3_0 44
+#define MD_IRQID_USIP0_1 45
+#define MD_IRQID_USIP1_1 46
+#define MD_IRQID_AP2MD_CCIF2_0 47
+#define MD_IRQID_USIP3_1 48
+#define MD_IRQID_SI_CM_ERR 49
+#define MD_IRQID_ABM_INT 50
+#define MD_IRQID_ABM_ERROR_INT 51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 52
+#define MD_IRQID_ELMTOP_EMI_IRQ 53
+#define MD_IRQID_PPPHA_ENC0_INT 54
+#define MD_IRQID_PPPHA_ENC1_INT 55
+#define MD_IRQID_PPPHA_DEC0_INT 56
+#define MD_IRQID_PPPHA_DEC1_INT 57
+#define MD_IRQID_PTP_FSM_INT 58
+#define MD_IRQID_PTP_SLPCTL_EVENT 59
+#define MD_IRQID_IEBIT_CHECK_IRQ0 60
+#define MD_IRQID_IEBIT_CHECK_IRQ1 61
+#define MD_IRQID_IEBIT_CHECK_IRQ2 62
+#define MD_IRQID_IEBIT_CHECK_IRQ3 63
+#define MD_IRQID_MDCIRQ_WDT0 64
+#define MD_IRQID_MDCIRQ_WDT1 65
+#define MD_IRQID_TRACE_INT 66
+#define MD_IRQID_SI_CM_PCINT 67
+#define MD_IRQID_PLL_GEARHP_RDY 68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ 69
+#define MD_IRQID_REQ_ABNORM_IRQ 70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ 71
+#define MD_IRQID_BT_CVSD 72
+#define MD_IRQID_SSUSB_USB_MCU 73
+#define MD_IRQID_SSUSB_DEV 74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 75
+#define MD_IRQID_AP2MD_CCIF0_0 76
+#define MD_IRQID_AP2MD_CCIF0_1 77
+#define MD_IRQID_AP2MD_CCIF1_0 78
+#define MD_IRQID_AP2MD_CCIF1_1 79
+#define MD_IRQID_RXDFE_RXK_READBACK 80
+#define MD_IRQID_BR_DMA_IRQ 81
+#define MD_IRQID_IDC_PM_INT 82
+#define MD_IRQID_IDC_UART_IRQ 83
+#define MD_IRQID_MDRTT 84
+#define MD_IRQID_MDEVDO 85
+#define MD_IRQID_MDM2C_U3G 86
+#define MD_IRQID_MDDFE_DUMP 87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 92
+#define MD_IRQID_BIGRAM_IRQ 93
+#define MD_IRQID_BR_BDGE_IRQ 94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 106
+#define MD_IRQID_MDL1_TOPSM_IRQ 107
+#define MD_IRQID_TDD_WAKEUP_IRQ 108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 110
+#define MD_IRQID_RTR_FRAME_IRQ 111
+#define MD_IRQID_RTR_SLT_0_IRQ 112
+#define MD_IRQID_RTR_SLT_1_IRQ 113
+#define MD_IRQID_FDD_SLP_IRQ 114
+#define MD_IRQID_TDMA_WAKEUP_IRQ 115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ 116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC 117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI 118
+#define MD_IRQID_ST1X_CPINT 119
+#define MD_IRQID_ST1x_HALF_CPINT 120
+#define MD_IRQID_ST1x_CFG_CPINT 121
+#define MD_IRQID_ST1x_WAKEUP_IRQ 122
+#define MD_IRQID_STDO_CPINT 123
+#define MD_IRQID_STDO_HALF_CPINT 124
+#define MD_IRQID_STDO_CFG_CPINT 125
+#define MD_IRQID_STDO_WAKEUP_IRQ 126
+#define MD_IRQID_FREQM_IRQ 127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS 128
+#define MD_IRQID_TXDFE_BB_IRQ 129
+#define MD_IRQID_PCC_TOP_FULL_IRQ 130
+#define MD_IRQID_GPTM1 131
+#define MD_IRQID_GPTM2 132
+#define MD_IRQID_GPTM3 133
+#define MD_IRQID_GPTM4 134
+#define MD_IRQID_GPTM5 135
+#define MD_IRQID_GPTM6 136
+#define MD_IRQID_GPTM7 137
+#define MD_IRQID_GPTM8 138
+#define MD_IRQID_GPTM9 139
+#define MD_IRQID_GPTM10 140
+#define MD_IRQID_GPTM11 141
+#define MD_IRQID_BUSMPU_IRQ 142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 206
+#define MD_IRQID_MCU_BUS_DECERR 207
+#define MD_IRQID_GIC0_FDCInt 208
+#define MD_IRQID_GIC0_FDCInt_1 209
+#define MD_IRQID_GIC0_PCInt 210
+#define MD_IRQID_GIC0_PCInt_1 211
+#define MD_IRQID_GIC0_TimerInt 212
+#define MD_IRQID_GIC0_TimerInt_1 213
+#define MD_IRQID_GIC1_FDCInt 214
+#define MD_IRQID_GIC1_FDCInt_1 215
+#define MD_IRQID_GIC1_PCInt 216
+#define MD_IRQID_GIC1_PCInt_1 217
+#define MD_IRQID_GIC1_TimerInt 218
+#define MD_IRQID_GIC1_TimerInt_1 219
+#define MD_IRQID_EINT3 220
+#define MD_IRQID_MCUMMU_INT 221
+#define MD_IRQID_IA_DECERR 222
+#define MD_IRQID_RMPU_CTIREIGIN 223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL 224
+#define MD_IRQID_AP2MD_MSDC0 225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6761_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6763.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6763.h
new file mode 100644
index 0000000..26e6300
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6763.h
@@ -0,0 +1,245 @@
+#ifndef __MT6763_IRQID_H__
+#define __MT6763_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_TOPSM 16
+#define MD_IRQID_MDGDMA0 17
+#define MD_IRQID_MDGDMA1 18
+#define MD_IRQID_MDGDMA2 19
+#define MD_IRQID_MDGDMA3 20
+#define MD_IRQID_EINT0 21
+#define MD_IRQID_EINT1 22
+#define MD_IRQID_EINT2 23
+#define MD_IRQID_EINT_SHARE 24
+#define MD_IRQID_BUS_ERR 25
+#define MD_IRQID_TXBRP0 26
+#define MD_IRQID_TXBRP1 27
+#define MD_IRQID_TXCRP 28
+#define MD_IRQ_ID_MML2_HRT 29
+#define MD_IRQ_ID_MML2_NOTIF 30
+#define MD_IRQ_ID_MML2_EXCEP 31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 32
+#define MD_IRQID_ECT 33
+#define MD_IRQID_PTP_THERM_INT_INT 34
+#define MD_IRQID_CLDMA 35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 36
+#define MD_IRQID_ELM_DMA_IRQ 37
+#define MD_IRQID_SOE 38
+#define MD_IRQID_ULSP_LOG_MD_INT 39
+#define MD_IRQID_ULSP_LOG_DSP_INT 40
+#define MD_IRQID_USIP0_0 41
+#define MD_IRQID_USIP1_0 42
+#define MD_IRQID_USIP2_0 43
+#define MD_IRQID_USIP3_0 44
+#define MD_IRQID_USIP0_1 45
+#define MD_IRQID_USIP1_1 46
+#define MD_IRQID_USIP2_1 47
+#define MD_IRQID_USIP3_1 48
+#define MD_IRQID_SI_CM_ERR 49
+#define MD_IRQID_ABM_INT 50
+#define MD_IRQID_ABM_ERROR_INT 51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 52
+#define MD_IRQID_ELMTOP_EMI_IRQ 53
+#define MD_IRQID_PPPHA_ENC0_INT 54
+#define MD_IRQID_PPPHA_ENC1_INT 55
+#define MD_IRQID_PPPHA_DEC0_INT 56
+#define MD_IRQID_PPPHA_DEC1_INT 57
+#define MD_IRQID_PTP_FSM_INT 58
+#define MD_IRQID_PTP_SLPCTL_EVENT 59
+#define MD_IRQID_IEBIT_CHECK_IRQ0 60
+#define MD_IRQID_IEBIT_CHECK_IRQ1 61
+#define MD_IRQID_IEBIT_CHECK_IRQ2 62
+#define MD_IRQID_IEBIT_CHECK_IRQ3 63
+#define MD_IRQID_MDCIRQ_WDT0 64
+#define MD_IRQID_MDCIRQ_WDT1 65
+#define MD_IRQID_TRACE_INT 66
+#define MD_IRQID_SI_CM_PCINT 67
+#define MD_IRQID_PLL_GEARHP_RDY 68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ 69
+#define MD_IRQID_REQ_ABNORM_IRQ 70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ 71
+#define MD_IRQID_BT_CVSD 72
+#define MD_IRQID_SSUSB_USB_MCU 73
+#define MD_IRQID_SSUSB_DEV 74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 75
+#define MD_IRQID_AP2MD_CCIF0_0 76
+#define MD_IRQID_AP2MD_CCIF0_1 77
+#define MD_IRQID_AP2MD_CCIF1_0 78
+#define MD_IRQID_AP2MD_CCIF1_1 79
+#define MD_IRQID_RXDFE_RXK_READBACK 80
+#define MD_IRQID_BR_DMA_IRQ 81
+#define MD_IRQID_IDC_PM_INT 82
+#define MD_IRQID_IDC_UART_IRQ 83
+#define MD_IRQID_MDRTT 84
+#define MD_IRQID_MDEVDO 85
+#define MD_IRQID_MDM2C_U3G 86
+#define MD_IRQID_MDDFE_DUMP 87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 92
+#define MD_IRQID_BIGRAM_IRQ 93
+#define MD_IRQID_BR_BDGE_IRQ 94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 106
+#define MD_IRQID_MDL1_TOPSM_IRQ 107
+#define MD_IRQID_TDD_WAKEUP_IRQ 108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 110
+#define MD_IRQID_RTR_FRAME_IRQ 111
+#define MD_IRQID_RTR_SLT_0_IRQ 112
+#define MD_IRQID_RTR_SLT_1_IRQ 113
+#define MD_IRQID_FDD_SLP_IRQ 114
+#define MD_IRQID_TDMA_WAKEUP_IRQ 115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ 116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC 117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI 118
+#define MD_IRQID_ST1X_CPINT 119
+#define MD_IRQID_ST1x_HALF_CPINT 120
+#define MD_IRQID_ST1x_CFG_CPINT 121
+#define MD_IRQID_ST1x_WAKEUP_IRQ 122
+#define MD_IRQID_STDO_CPINT 123
+#define MD_IRQID_STDO_HALF_CPINT 124
+#define MD_IRQID_STDO_CFG_CPINT 125
+#define MD_IRQID_STDO_WAKEUP_IRQ 126
+#define MD_IRQID_FREQM_IRQ 127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS 128
+#define MD_IRQID_TXDFE_BB_IRQ 129
+#define MD_IRQID_PCC_TOP_FULL_IRQ 130
+#define MD_IRQID_GPTM1 131
+#define MD_IRQID_GPTM2 132
+#define MD_IRQID_GPTM3 133
+#define MD_IRQID_GPTM4 134
+#define MD_IRQID_GPTM5 135
+#define MD_IRQID_GPTM6 136
+#define MD_IRQID_GPTM7 137
+#define MD_IRQID_GPTM8 138
+#define MD_IRQID_GPTM9 139
+#define MD_IRQID_GPTM10 140
+#define MD_IRQID_GPTM11 141
+#define MD_IRQID_BUSMPU_IRQ 142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 206
+#define MD_IRQID_MCU_BUS_DECERR 207
+#define MD_IRQID_GIC0_FDCInt 208
+#define MD_IRQID_GIC0_FDCInt_1 209
+#define MD_IRQID_GIC0_PCInt 210
+#define MD_IRQID_GIC0_PCInt_1 211
+#define MD_IRQID_GIC0_TimerInt 212
+#define MD_IRQID_GIC0_TimerInt_1 213
+#define MD_IRQID_GIC1_FDCInt 214
+#define MD_IRQID_GIC1_FDCInt_1 215
+#define MD_IRQID_GIC1_PCInt 216
+#define MD_IRQID_GIC1_PCInt_1 217
+#define MD_IRQID_GIC1_TimerInt 218
+#define MD_IRQID_GIC1_TimerInt_1 219
+#define MD_IRQID_EINT3 220
+#define MD_IRQID_MCUMMU_INT 221
+#define MD_IRQID_IA_DECERR 222
+#define MD_IRQID_RMPU_CTIREIGIN 223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL 224
+#define MD_IRQID_AP2MD_MSDC0 225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6763_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6765.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6765.h
new file mode 100644
index 0000000..d4d7479
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6765.h
@@ -0,0 +1,245 @@
+#ifndef __MT6765_IRQID_H__
+#define __MT6765_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_TOPSM 16
+#define MD_IRQID_MDGDMA0 17
+#define MD_IRQID_MDGDMA1 18
+#define MD_IRQID_MDGDMA2 19
+#define MD_IRQID_MDGDMA3 20
+#define MD_IRQID_EINT0 21
+#define MD_IRQID_EINT1 22
+#define MD_IRQID_EINT2 23
+#define MD_IRQID_EINT_SHARE 24
+#define MD_IRQID_BUS_ERR 25
+#define MD_IRQID_TXBRP0 26
+#define MD_IRQID_TXBRP1 27
+#define MD_IRQID_TXCRP 28
+#define MD_IRQ_ID_MML2_HRT 29
+#define MD_IRQ_ID_MML2_NOTIF 30
+#define MD_IRQ_ID_MML2_EXCEP 31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 32
+#define MD_IRQID_ECT 33
+#define MD_IRQID_PTP_THERM_INT_INT 34
+#define MD_IRQID_CLDMA 35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 36
+#define MD_IRQID_ELM_DMA_IRQ 37
+#define MD_IRQID_SOE 38
+#define MD_IRQID_ULSP_LOG_MD_INT 39
+#define MD_IRQID_ULSP_LOG_DSP_INT 40
+#define MD_IRQID_USIP0_0 41
+#define MD_IRQID_USIP1_0 42
+#define MD_IRQID_USIP2_0 43
+#define MD_IRQID_USIP3_0 44
+#define MD_IRQID_USIP0_1 45
+#define MD_IRQID_USIP1_1 46
+#define MD_IRQID_AP2MD_CCIF2_0 47
+#define MD_IRQID_USIP3_1 48
+#define MD_IRQID_SI_CM_ERR 49
+#define MD_IRQID_ABM_INT 50
+#define MD_IRQID_ABM_ERROR_INT 51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 52
+#define MD_IRQID_ELMTOP_EMI_IRQ 53
+#define MD_IRQID_PPPHA_ENC0_INT 54
+#define MD_IRQID_PPPHA_ENC1_INT 55
+#define MD_IRQID_PPPHA_DEC0_INT 56
+#define MD_IRQID_PPPHA_DEC1_INT 57
+#define MD_IRQID_PTP_FSM_INT 58
+#define MD_IRQID_PTP_SLPCTL_EVENT 59
+#define MD_IRQID_IEBIT_CHECK_IRQ0 60
+#define MD_IRQID_IEBIT_CHECK_IRQ1 61
+#define MD_IRQID_IEBIT_CHECK_IRQ2 62
+#define MD_IRQID_IEBIT_CHECK_IRQ3 63
+#define MD_IRQID_MDCIRQ_WDT0 64
+#define MD_IRQID_MDCIRQ_WDT1 65
+#define MD_IRQID_TRACE_INT 66
+#define MD_IRQID_SI_CM_PCINT 67
+#define MD_IRQID_PLL_GEARHP_RDY 68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ 69
+#define MD_IRQID_REQ_ABNORM_IRQ 70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ 71
+#define MD_IRQID_BT_CVSD 72
+#define MD_IRQID_SSUSB_USB_MCU 73
+#define MD_IRQID_SSUSB_DEV 74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 75
+#define MD_IRQID_AP2MD_CCIF0_0 76
+#define MD_IRQID_AP2MD_CCIF0_1 77
+#define MD_IRQID_AP2MD_CCIF1_0 78
+#define MD_IRQID_AP2MD_CCIF1_1 79
+#define MD_IRQID_RXDFE_RXK_READBACK 80
+#define MD_IRQID_BR_DMA_IRQ 81
+#define MD_IRQID_IDC_PM_INT 82
+#define MD_IRQID_IDC_UART_IRQ 83
+#define MD_IRQID_MDRTT 84
+#define MD_IRQID_MDEVDO 85
+#define MD_IRQID_MDM2C_U3G 86
+#define MD_IRQID_MDDFE_DUMP 87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 92
+#define MD_IRQID_BIGRAM_IRQ 93
+#define MD_IRQID_BR_BDGE_IRQ 94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 106
+#define MD_IRQID_MDL1_TOPSM_IRQ 107
+#define MD_IRQID_TDD_WAKEUP_IRQ 108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 110
+#define MD_IRQID_RTR_FRAME_IRQ 111
+#define MD_IRQID_RTR_SLT_0_IRQ 112
+#define MD_IRQID_RTR_SLT_1_IRQ 113
+#define MD_IRQID_FDD_SLP_IRQ 114
+#define MD_IRQID_TDMA_WAKEUP_IRQ 115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ 116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC 117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI 118
+#define MD_IRQID_ST1X_CPINT 119
+#define MD_IRQID_ST1x_HALF_CPINT 120
+#define MD_IRQID_ST1x_CFG_CPINT 121
+#define MD_IRQID_ST1x_WAKEUP_IRQ 122
+#define MD_IRQID_STDO_CPINT 123
+#define MD_IRQID_STDO_HALF_CPINT 124
+#define MD_IRQID_STDO_CFG_CPINT 125
+#define MD_IRQID_STDO_WAKEUP_IRQ 126
+#define MD_IRQID_FREQM_IRQ 127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS 128
+#define MD_IRQID_TXDFE_BB_IRQ 129
+#define MD_IRQID_PCC_TOP_FULL_IRQ 130
+#define MD_IRQID_GPTM1 131
+#define MD_IRQID_GPTM2 132
+#define MD_IRQID_GPTM3 133
+#define MD_IRQID_GPTM4 134
+#define MD_IRQID_GPTM5 135
+#define MD_IRQID_GPTM6 136
+#define MD_IRQID_GPTM7 137
+#define MD_IRQID_GPTM8 138
+#define MD_IRQID_GPTM9 139
+#define MD_IRQID_GPTM10 140
+#define MD_IRQID_GPTM11 141
+#define MD_IRQID_BUSMPU_IRQ 142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 206
+#define MD_IRQID_MCU_BUS_DECERR 207
+#define MD_IRQID_GIC0_FDCInt 208
+#define MD_IRQID_GIC0_FDCInt_1 209
+#define MD_IRQID_GIC0_PCInt 210
+#define MD_IRQID_GIC0_PCInt_1 211
+#define MD_IRQID_GIC0_TimerInt 212
+#define MD_IRQID_GIC0_TimerInt_1 213
+#define MD_IRQID_GIC1_FDCInt 214
+#define MD_IRQID_GIC1_FDCInt_1 215
+#define MD_IRQID_GIC1_PCInt 216
+#define MD_IRQID_GIC1_PCInt_1 217
+#define MD_IRQID_GIC1_TimerInt 218
+#define MD_IRQID_GIC1_TimerInt_1 219
+#define MD_IRQID_EINT3 220
+#define MD_IRQID_MCUMMU_INT 221
+#define MD_IRQID_IA_DECERR 222
+#define MD_IRQID_RMPU_CTIREIGIN 223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL 224
+#define MD_IRQID_AP2MD_MSDC0 225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6765_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6771.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6771.h
new file mode 100644
index 0000000..32bcbb4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6771.h
@@ -0,0 +1,245 @@
+#ifndef __MT6771_IRQID_H__
+#define __MT6771_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_TOPSM 16
+#define MD_IRQID_MDGDMA0 17
+#define MD_IRQID_MDGDMA1 18
+#define MD_IRQID_MDGDMA2 19
+#define MD_IRQID_MDGDMA3 20
+#define MD_IRQID_EINT0 21
+#define MD_IRQID_EINT1 22
+#define MD_IRQID_EINT2 23
+#define MD_IRQID_EINT_SHARE 24
+#define MD_IRQID_BUS_ERR 25
+#define MD_IRQID_TXBRP0 26
+#define MD_IRQID_TXBRP1 27
+#define MD_IRQID_TXCRP 28
+#define MD_IRQ_ID_MML2_HRT 29
+#define MD_IRQ_ID_MML2_NOTIF 30
+#define MD_IRQ_ID_MML2_EXCEP 31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 32
+#define MD_IRQID_ECT 33
+#define MD_IRQID_PTP_THERM_INT_INT 34
+#define MD_IRQID_CLDMA 35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 36
+#define MD_IRQID_ELM_DMA_IRQ 37
+#define MD_IRQID_SOE 38
+#define MD_IRQID_ULSP_LOG_MD_INT 39
+#define MD_IRQID_ULSP_LOG_DSP_INT 40
+#define MD_IRQID_USIP0_0 41
+#define MD_IRQID_USIP1_0 42
+#define MD_IRQID_USIP2_0 43
+#define MD_IRQID_USIP3_0 44
+#define MD_IRQID_USIP0_1 45
+#define MD_IRQID_USIP1_1 46
+#define MD_IRQID_AP2MD_CCIF2_0 47
+#define MD_IRQID_USIP3_1 48
+#define MD_IRQID_SI_CM_ERR 49
+#define MD_IRQID_ABM_INT 50
+#define MD_IRQID_ABM_ERROR_INT 51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 52
+#define MD_IRQID_ELMTOP_EMI_IRQ 53
+#define MD_IRQID_PPPHA_ENC0_INT 54
+#define MD_IRQID_PPPHA_ENC1_INT 55
+#define MD_IRQID_PPPHA_DEC0_INT 56
+#define MD_IRQID_PPPHA_DEC1_INT 57
+#define MD_IRQID_PTP_FSM_INT 58
+#define MD_IRQID_PTP_SLPCTL_EVENT 59
+#define MD_IRQID_IEBIT_CHECK_IRQ0 60
+#define MD_IRQID_IEBIT_CHECK_IRQ1 61
+#define MD_IRQID_IEBIT_CHECK_IRQ2 62
+#define MD_IRQID_IEBIT_CHECK_IRQ3 63
+#define MD_IRQID_MDCIRQ_WDT0 64
+#define MD_IRQID_MDCIRQ_WDT1 65
+#define MD_IRQID_TRACE_INT 66
+#define MD_IRQID_SI_CM_PCINT 67
+#define MD_IRQID_PLL_GEARHP_RDY 68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ 69
+#define MD_IRQID_REQ_ABNORM_IRQ 70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ 71
+#define MD_IRQID_BT_CVSD 72
+#define MD_IRQID_SSUSB_USB_MCU 73
+#define MD_IRQID_SSUSB_DEV 74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 75
+#define MD_IRQID_AP2MD_CCIF0_0 76
+#define MD_IRQID_AP2MD_CCIF0_1 77
+#define MD_IRQID_AP2MD_CCIF1_0 78
+#define MD_IRQID_AP2MD_CCIF1_1 79
+#define MD_IRQID_RXDFE_RXK_READBACK 80
+#define MD_IRQID_BR_DMA_IRQ 81
+#define MD_IRQID_IDC_PM_INT 82
+#define MD_IRQID_IDC_UART_IRQ 83
+#define MD_IRQID_MDRTT 84
+#define MD_IRQID_MDEVDO 85
+#define MD_IRQID_MDM2C_U3G 86
+#define MD_IRQID_MDDFE_DUMP 87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 92
+#define MD_IRQID_BIGRAM_IRQ 93
+#define MD_IRQID_BR_BDGE_IRQ 94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 106
+#define MD_IRQID_MDL1_TOPSM_IRQ 107
+#define MD_IRQID_TDD_WAKEUP_IRQ 108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 110
+#define MD_IRQID_RTR_FRAME_IRQ 111
+#define MD_IRQID_RTR_SLT_0_IRQ 112
+#define MD_IRQID_RTR_SLT_1_IRQ 113
+#define MD_IRQID_FDD_SLP_IRQ 114
+#define MD_IRQID_TDMA_WAKEUP_IRQ 115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ 116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC 117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI 118
+#define MD_IRQID_ST1X_CPINT 119
+#define MD_IRQID_ST1x_HALF_CPINT 120
+#define MD_IRQID_ST1x_CFG_CPINT 121
+#define MD_IRQID_ST1x_WAKEUP_IRQ 122
+#define MD_IRQID_STDO_CPINT 123
+#define MD_IRQID_STDO_HALF_CPINT 124
+#define MD_IRQID_STDO_CFG_CPINT 125
+#define MD_IRQID_STDO_WAKEUP_IRQ 126
+#define MD_IRQID_FREQM_IRQ 127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS 128
+#define MD_IRQID_TXDFE_BB_IRQ 129
+#define MD_IRQID_PCC_TOP_FULL_IRQ 130
+#define MD_IRQID_GPTM1 131
+#define MD_IRQID_GPTM2 132
+#define MD_IRQID_GPTM3 133
+#define MD_IRQID_GPTM4 134
+#define MD_IRQID_GPTM5 135
+#define MD_IRQID_GPTM6 136
+#define MD_IRQID_GPTM7 137
+#define MD_IRQID_GPTM8 138
+#define MD_IRQID_GPTM9 139
+#define MD_IRQID_GPTM10 140
+#define MD_IRQID_GPTM11 141
+#define MD_IRQID_BUSMPU_IRQ 142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 206
+#define MD_IRQID_MCU_BUS_DECERR 207
+#define MD_IRQID_GIC0_FDCInt 208
+#define MD_IRQID_GIC0_FDCInt_1 209
+#define MD_IRQID_GIC0_PCInt 210
+#define MD_IRQID_GIC0_PCInt_1 211
+#define MD_IRQID_GIC0_TimerInt 212
+#define MD_IRQID_GIC0_TimerInt_1 213
+#define MD_IRQID_GIC1_FDCInt 214
+#define MD_IRQID_GIC1_FDCInt_1 215
+#define MD_IRQID_GIC1_PCInt 216
+#define MD_IRQID_GIC1_PCInt_1 217
+#define MD_IRQID_GIC1_TimerInt 218
+#define MD_IRQID_GIC1_TimerInt_1 219
+#define MD_IRQID_EINT3 220
+#define MD_IRQID_MCUMMU_INT 221
+#define MD_IRQID_IA_DECERR 222
+#define MD_IRQID_RMPU_CTIREIGIN 223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL 224
+#define MD_IRQID_AP2MD_MSDC0 225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6771_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/isrentry.h b/mcu/interface/driver/devdrv/cirq/md93/isrentry.h
new file mode 100644
index 0000000..2a4c711
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/isrentry.h
@@ -0,0 +1,192 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * isrentry.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+enum { WKUP_TM_NAME_MAX = 8, WKUP_LOG_BUF_MAX = 100 };
+
+typedef struct
+{
+ kal_uint32 vector;
+ void (*lisr_handler) (kal_uint32);
+ kal_char *description;
+} irqlisr_entry;
+
+typedef struct errorMenuType
+{
+ kal_uint32 irqMask;
+ kal_uint32 irqStatus;
+ kal_uint32 irqStatus2;
+ kal_uint32 fiqSelect;
+ kal_uint32 fiqControl;
+ kal_uint32 irqReturnAddr;
+ kal_uint32 fiqReturnAddr;
+} IntErrType;
+
+typedef struct wkup_intr_log_struct
+{
+ kal_uint32 irq;
+} wkup_intr_log_t;
+
+typedef struct wkup_intr_timer_struct
+{
+ kal_char *timer_name;
+} wkup_timer_log_t;
+
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(void);
+extern kal_int32 get_wkup_intr_log_buf(wkup_intr_log_t **buf, kal_uint32 *indx, kal_uint32 *max);
+extern kal_int32 get_wkup_timer_log_buf(wkup_timer_log_t **buf, kal_uint32 *indx, kal_uint32 *max);
+extern kal_int32 enable_wkup_log(void);
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h
new file mode 100644
index 0000000..dbbfd6c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h
@@ -0,0 +1,324 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MT6295M)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6295M.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6295M MDSYS."
+#endif
+#endif
+
+#if defined(MT3967)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT3967.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT3967 MDSYS."
+#endif
+#endif
+
+#if defined(MT6779)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6779.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6779 MDSYS."
+#endif
+#endif
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+
+#define EDGE_SENSITIVE KAL_TRUE
+#define LEVEL_SENSITIVE KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+ kal_uint32 irq_mask[8];
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+ Need to modify 3 files
+ 1. add a file intrCtrl_MTxxxx_SW_Handler.h
+ 2. add an entry on intrCtrl_SW_Handler.h
+ 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+ SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern const kal_uint8 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a) (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint8);
+extern void MDCIRQ_IRQMask(kal_uint8);
+extern void MDCIRQ_IRQUnmask(kal_uint8);
+extern void MDCIRQ_IRQSensitivity(kal_uint8, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint8 code);
+extern kal_uint32 IRQ_Status(void);
+extern kal_bool MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(kal_uint32 VPE, kal_uint32 code);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+ MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+//extern void IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+ IRQ_PRIORITY_END,
+ IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD = IRQ_USIP1_1_CODE_PRIORITY + 1,
+} IRQ_PRIORITY;
+
+typedef enum {
+ MDCIRQ_To_BUS_Normal = 0x0,
+ MDCIRQ_To_BUS_PreUltra = 0x1,
+ MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR() (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+// #define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && defined(__MIPS_IA__)
+#if defined(__NESTED_DI_CHECK__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ kal_uint32 vpe_num = 0;\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+ vpe_num = miu_get_current_vpe_id();\
+ sst_dhl_irq_count[vpe_num]++;\
+ sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+ DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h
new file mode 100644
index 0000000..78924fc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h
@@ -0,0 +1,664 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT3967.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT3967_H__
+#define __INTRCTRL_MT3967_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (204)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_MD_BUCK_CTRL_IRQ_CODE MD_IRQID_MD_BUCK_CTRL_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_USB_MCU_CODE MD_IRQID_USB_MCU
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDMCU_DVFS_CTRL_CODE MD_IRQID_MDMCU_DVFS_CTRL
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_IA_DECERR_CODE MD_IRQID_IA_DECERR
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_SPU_INT_CODE MD_IRQID_SPU_INT
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_AP2MD_CONN_CCIF_0_CODE MD_IRQID_AP2MD_CONN_CCIF_0
+#define IRQ_AP2MD_CONN_CCIF_1_CODE MD_IRQID_AP2MD_CONN_CCIF_1
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_CONN2MD_PDMA_IRQ_CODE MD_IRQID_CONN2MD_PDMA_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define IRQ_DUMMY_PRIORITY_CODE_2 MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ_8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ_9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ_10
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~203 */ 0, 0, 0, 0,
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 6, 1, 1, 1, 1, 1, 11, \
+ /* 8 ~ 15 */ 6, 6, 7, 6, 6, 0, 6, 6, \
+ /* 16 ~ 23 */ 6, 7, 6, 6, 6, 6, 6, 6, \
+ /* 24 ~ 31 */ 7, 1, 6, 6, 6, 6, 6, 7, \
+ /* 32 ~ 39 */ 6, 6, 6, 6, 6, 6, 6, 0, \
+ /* 40 ~ 47 */ 3, 1, 1, 10, 10, 3, 6, 0, \
+ /* 48 ~ 55 */ 0, 6, 6, 6, 6, 6, 6, 6, \
+ /* 56 ~ 63 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /* 64 ~ 71 */ 6, 6, 0, 6, 6, 6, 6, 6, \
+ /* 72 ~ 79 */ 6, 7, 6, 6, 1, 6, 6, 6, \
+ /* 80 ~ 87 */ 1, 1, 1, 1, 1, 1, 7, 6, \
+ /* 88 ~ 95 */ 3, 9, 12, 1, 1, 3, 1, 1, \
+ /* 96 ~103 */ 1, 3, 1, 3, 1, 1, 1, 1, \
+ /*104 ~111 */ 3, 1, 1, 1, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 1, 1, 0, 6, 6, 6, 6, \
+ /*120 ~127 */ 6, 6, 6, 1, 1, 7, 6, 6, \
+ /*128 ~135 */ 6, 7, 7, 6, 6, 7, 6, 12, \
+ /*136 ~143 */ 12, 1, 3, 12, 11, 6, 7, 6, \
+ /*144 ~151 */ 6, 1, 6, 6, 6, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 8, 7, 6, 8, 0, 0, \
+ /*168 ~175 */ 2, 4, 7, 0, 2, 4, 1, 1, \
+ /*176 ~183 */ 6, 6, 1, 6, 6, 6, 6, 0, \
+ /*184 ~191 */ 1, 2, 3, 4, 5, 6, 6, 6, \
+ /*192 ~199 */ 6, 6, 6, 6, 6, 6, 6, 6, \
+ /*200 ~203 */ 6, 6, 6, 6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4 */ 0x3F, \
+ /* Group5 */ 0x3F, \
+ /* Group6(0,2) */ 0x3A, \
+ /* Group7(0,1,2,3) */ 0x30, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4(4) */ 0x2F, \
+ /* Group5(5) */ 0x1F, \
+ /* Group6(0,2,4) */ 0x2A, \
+ /* Group7(0,1,2,3,4,5) */ 0x00, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 1, 0, 0, 0, 0, 0, 0, 1, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 1, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 1, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 1, 1, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 1, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~204 */ 0, 0, 0, 0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 204,
+ VPE_STATUS_HISR_TASK_HIGHEST = 256,
+ VPE_STATUS_HISR_TASK_LOWEST = 511,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+ IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+ IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+ IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+ IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+ IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+ IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+ IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+ IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+ IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+ IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+ IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+ IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT3967_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h
new file mode 100644
index 0000000..aa559c4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT3967_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT3967
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+ SW_TRIGGER_CODE14 = Woody Kuo
+ SW_TRIGGER_CODE15 = Carl Kao
+ SW_TRIGGER_CODE16 = Yuni Chang
+ SW_TRIGGER_CODE17 = SY Yeh
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Wade Huang
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Weimin Zeng
+ SW_TRIGGER_CODE26 = Weimin Zeng
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Kevin-KH Liu
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Nicole Hsu
+ SW_TRIGGER_CODE32 =
+ SW_TRIGGER_CODE33 =
+ SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+ */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT3967 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h
new file mode 100644
index 0000000..e1b818c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h
@@ -0,0 +1,664 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6295M.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6295M_H__
+#define __INTRCTRL_MT6295M_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (204)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_MD_BUCK_CTRL_IRQ_CODE MD_IRQID_MD_BUCK_CTRL_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_USB_MCU_CODE MD_IRQID_USB_MCU
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDMCU_DVFS_CTRL_CODE MD_IRQID_MDMCU_DVFS_CTRL
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_IA_DECERR_CODE MD_IRQID_IA_DECERR
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_SPU_INT_CODE MD_IRQID_SPU_INT
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_AP2MD_CONN_CCIF_0_CODE MD_IRQID_AP2MD_CONN_CCIF_0
+#define IRQ_AP2MD_CONN_CCIF_1_CODE MD_IRQID_AP2MD_CONN_CCIF_1
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_CONN2MD_PDMA_IRQ_CODE MD_IRQID_CONN2MD_PDMA_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define IRQ_DUMMY_PRIORITY_CODE_2 MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ_8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ_9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ_10
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~203 */ 0, 0, 0, 0,
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 6, 1, 1, 1, 1, 1, 11, \
+ /* 8 ~ 15 */ 6, 6, 7, 6, 6, 0, 6, 6, \
+ /* 16 ~ 23 */ 6, 7, 6, 6, 6, 6, 6, 6, \
+ /* 24 ~ 31 */ 7, 1, 6, 6, 6, 6, 6, 7, \
+ /* 32 ~ 39 */ 6, 6, 6, 6, 6, 6, 6, 0, \
+ /* 40 ~ 47 */ 3, 1, 1, 10, 10, 3, 6, 0, \
+ /* 48 ~ 55 */ 0, 6, 6, 6, 6, 6, 6, 6, \
+ /* 56 ~ 63 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /* 64 ~ 71 */ 6, 6, 0, 6, 6, 6, 6, 6, \
+ /* 72 ~ 79 */ 6, 7, 6, 6, 1, 6, 6, 6, \
+ /* 80 ~ 87 */ 1, 1, 1, 1, 1, 1, 7, 6, \
+ /* 88 ~ 95 */ 3, 9, 12, 1, 1, 3, 1, 1, \
+ /* 96 ~103 */ 1, 3, 1, 3, 1, 1, 1, 1, \
+ /*104 ~111 */ 3, 1, 1, 1, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 1, 1, 0, 6, 6, 6, 6, \
+ /*120 ~127 */ 6, 6, 6, 1, 1, 3, 6, 6, \
+ /*128 ~135 */ 6, 7, 7, 6, 6, 7, 6, 12, \
+ /*136 ~143 */ 12, 1, 3, 12, 11, 6, 7, 6, \
+ /*144 ~151 */ 6, 1, 6, 6, 6, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 8, 7, 6, 8, 0, 0, \
+ /*168 ~175 */ 2, 4, 7, 0, 2, 4, 1, 1, \
+ /*176 ~183 */ 6, 6, 1, 6, 6, 6, 6, 0, \
+ /*184 ~191 */ 1, 2, 3, 4, 5, 6, 6, 6, \
+ /*192 ~199 */ 6, 6, 6, 6, 6, 6, 6, 6, \
+ /*200 ~203 */ 6, 6, 6, 6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4 */ 0x3F, \
+ /* Group5 */ 0x3F, \
+ /* Group6(0,2) */ 0x3A, \
+ /* Group7(0,1,2,3) */ 0x30, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4(4) */ 0x2F, \
+ /* Group5(5) */ 0x1F, \
+ /* Group6(0,2,4) */ 0x2A, \
+ /* Group7(0,1,2,3,4,5) */ 0x00, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 1, 0, 0, 0, 0, 0, 0, 1, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 1, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 1, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 1, 1, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 1, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~204 */ 0, 0, 0, 0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 204,
+ VPE_STATUS_HISR_TASK_HIGHEST = 256,
+ VPE_STATUS_HISR_TASK_LOWEST = 511,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+ IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+ IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+ IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+ IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+ IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+ IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+ IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+ IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+ IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+ IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+ IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+ IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT6295M_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h
new file mode 100644
index 0000000..cb89e1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6295M_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6295M
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+ SW_TRIGGER_CODE14 = Woody Kuo
+ SW_TRIGGER_CODE15 = Carl Kao
+ SW_TRIGGER_CODE16 = Yuni Chang
+ SW_TRIGGER_CODE17 = SY Yeh
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Wade Huang
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Weimin Zeng
+ SW_TRIGGER_CODE26 = Weimin Zeng
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Kevin-KH Liu
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Nicole Hsu
+ SW_TRIGGER_CODE32 =
+ SW_TRIGGER_CODE33 =
+ SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+ */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6295M for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h
new file mode 100644
index 0000000..b56a7eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h
@@ -0,0 +1,666 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6779.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6779_H__
+#define __INTRCTRL_MT6779_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (204)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_MD_BUCK_CTRL_IRQ_CODE MD_IRQID_MD_BUCK_CTRL_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_USB_MCU_CODE MD_IRQID_USB_MCU
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDMCU_DVFS_CTRL_CODE MD_IRQID_MDMCU_DVFS_CTRL
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_IA_DECERR_CODE MD_IRQID_IA_DECERR
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_SPU_INT_CODE MD_IRQID_SPU_INT
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_AP2MD_CONN_CCIF_0_CODE MD_IRQID_AP2MD_CONN_CCIF_0
+#define IRQ_AP2MD_CONN_CCIF_1_CODE MD_IRQID_AP2MD_CONN_CCIF_1
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_CONN2MD_PDMA_IRQ_CODE MD_IRQID_CONN2MD_PDMA_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define IRQ_DUMMY_PRIORITY_CODE_2 MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ_8
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~203 */ 0, 0, 0, 0,
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 6, 1, 1, 1, 1, 1, 11, \
+ /* 8 ~ 15 */ 6, 6, 7, 6, 6, 0, 6, 6, \
+ /* 16 ~ 23 */ 6, 7, 6, 6, 6, 6, 6, 6, \
+ /* 24 ~ 31 */ 7, 1, 6, 6, 6, 6, 6, 7, \
+ /* 32 ~ 39 */ 6, 6, 6, 6, 6, 6, 6, 0, \
+ /* 40 ~ 47 */ 3, 1, 1, 10, 10, 3, 6, 0, \
+ /* 48 ~ 55 */ 0, 6, 6, 6, 6, 6, 6, 6, \
+ /* 56 ~ 63 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /* 64 ~ 71 */ 6, 6, 0, 6, 6, 6, 6, 6, \
+ /* 72 ~ 79 */ 6, 7, 6, 6, 1, 6, 6, 6, \
+ /* 80 ~ 87 */ 1, 1, 1, 1, 1, 1, 7, 6, \
+ /* 88 ~ 95 */ 3, 9, 12, 1, 1, 3, 1, 1, \
+ /* 96 ~103 */ 1, 3, 1, 3, 1, 1, 1, 1, \
+ /*104 ~111 */ 3, 1, 1, 1, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 1, 1, 0, 6, 6, 6, 6, \
+ /*120 ~127 */ 6, 6, 6, 1, 1, 7, 6, 6, \
+ /*128 ~135 */ 6, 7, 7, 6, 6, 7, 6, 12, \
+ /*136 ~143 */ 12, 1, 3, 12, 11, 6, 7, 6, \
+ /*144 ~151 */ 6, 1, 6, 6, 6, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 8, 7, 6, 8, 0, 0, \
+ /*168 ~175 */ 2, 4, 7, 0, 2, 4, 1, 1, \
+ /*176 ~183 */ 6, 6, 1, 6, 6, 6, 6, 0, \
+ /*184 ~191 */ 1, 2, 3, 4, 5, 6, 6, 6, \
+ /*192 ~199 */ 6, 6, 6, 6, 6, 6, 6, 6, \
+ /*200 ~203 */ 6, 6, 6, 6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4 */ 0x3F, \
+ /* Group5 */ 0x3F, \
+ /* Group6(0,2) */ 0x3A, \
+ /* Group7(0,1,2,3) */ 0x30, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4(4) */ 0x2F, \
+ /* Group5(5) */ 0x1F, \
+ /* Group6(0,2,4) */ 0x2A, \
+ /* Group7(0,1,2,3,4,5) */ 0x00, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 1, 0, 0, 0, 0, 0, 0, 1, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 1, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 1, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 1, 1, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 1, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~204 */ 0, 0, 0, 0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 204,
+ VPE_STATUS_HISR_TASK_HIGHEST = 256,
+ VPE_STATUS_HISR_TASK_LOWEST = 511,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+ IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+ IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+ IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+ IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+ IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+ IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+ IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+ IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+ IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+ IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+ IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+ IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+ IRQ_CONN_BT_ISOCH = IRQ_CONN_BT_ISOCH_CODE,
+ IRQ_AP2MD_UFS = IRQ_AP2MD_UFS_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT6779_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h
new file mode 100644
index 0000000..7c5ac1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6779_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6779
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+ SW_TRIGGER_CODE14 = Woody Kuo
+ SW_TRIGGER_CODE15 = Carl Kao
+ SW_TRIGGER_CODE16 = Yuni Chang
+ SW_TRIGGER_CODE17 = SY Yeh
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Wade Huang
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Weimin Zeng
+ SW_TRIGGER_CODE26 = Weimin Zeng
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Kevin-KH Liu
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Nicole Hsu
+ SW_TRIGGER_CODE32 =
+ SW_TRIGGER_CODE33 =
+ SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+ */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6779 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..ac6c23a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h
@@ -0,0 +1,92 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6295M)
+ #include "intrCtrl_MT6295M_SW_Handle.h"
+#endif
+
+#if defined(MT3967)
+ #include "intrCtrl_MT3967_SW_Handle.h"
+#endif
+
+#if defined(MT6779)
+ #include "intrCtrl_MT6779_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h
new file mode 100644
index 0000000..f932ab5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h
@@ -0,0 +1,11 @@
+#if defined(MT6295M)
+ #include "irqPriority_MT6295M.h"
+#endif
+
+#if defined(MT3967)
+ #include "irqPriority_MT3967.h"
+#endif
+
+#if defined(MT6779)
+ #include "irqPriority_MT6779.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h
new file mode 100644
index 0000000..050f9d2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h
new file mode 100644
index 0000000..1361e38
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h
new file mode 100644
index 0000000..af6548f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid.h b/mcu/interface/driver/devdrv/cirq/md95/irqid.h
new file mode 100644
index 0000000..eb8c5e1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid.h
@@ -0,0 +1,16 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6295M)
+ #include "irqid_MT6295M.h"
+#endif
+
+#if defined(MT3967)
+ #include "irqid_MT3967.h"
+#endif
+
+#if defined(MT6779)
+ #include "irqid_MT6779.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h
new file mode 100644
index 0000000..fa92526
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h
@@ -0,0 +1,222 @@
+#ifndef __MT3967_IRQID_H__
+#define __MT3967_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_MDGDMA0 16
+#define MD_IRQID_MDGDMA1 17
+#define MD_IRQID_MDGDMA2 18
+#define MD_IRQID_MDGDMA3 19
+#define MD_IRQID_EINT0 20
+#define MD_IRQID_EINT1 21
+#define MD_IRQID_EINT2 22
+#define MD_IRQID_EINT_SHARE 23
+#define MD_IRQID_BUS_ERR 24
+#define MD_IRQID_TXBSRP 25
+#define MD_IRQID_TXCRP 26
+#define MD_IRQ_ID_MML2_HRT 27
+#define MD_IRQ_ID_MML2_NOTIF 28
+#define MD_IRQ_ID_MML2_EXCEP 29
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 30
+#define MD_IRQID_ECT 31
+#define MD_IRQID_PTP_THERM_INT_INT 32
+#define MD_IRQID_CLDMA 33
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 34
+#define MD_IRQID_ELM_DMA_IRQ 35
+#define MD_IRQID_SOE 36
+#define MD_IRQID_ULSP_LOG_MD_INT 37
+#define MD_IRQID_ULSP_LOG_DSP_INT 38
+#define MD_IRQID_USIP0_0 39
+#define MD_IRQID_USIP1_0 40
+#define MD_IRQID_USIP2_0 41
+#define MD_IRQID_USIP3_0 42
+#define MD_IRQID_USIP0_1 43
+#define MD_IRQID_USIP1_1 44
+#define MD_IRQID_USIP2_1 45
+#define MD_IRQID_SI_CM_ERR 46
+#define MD_IRQID_ABM_INT 47
+#define MD_IRQID_ABM_ERROR_INT 48
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 49
+#define MD_IRQID_ELMTOP_EMI_IRQ 50
+#define MD_IRQID_PPPHA_ENC0_INT 51
+#define MD_IRQID_PPPHA_ENC1_INT 52
+#define MD_IRQID_PPPHA_DEC0_INT 53
+#define MD_IRQID_PPPHA_DEC1_INT 54
+#define MD_IRQID_PTP_FSM_INT 55
+#define MD_IRQID_IEBIT_CHECK_IRQ0 56
+#define MD_IRQID_IEBIT_CHECK_IRQ1 57
+#define MD_IRQID_IEBIT_CHECK_IRQ2 58
+#define MD_IRQID_IEBIT_CHECK_IRQ3 59
+#define MD_IRQID_IEBIT_CHECK_IRQ4 60
+#define MD_IRQID_IEBIT_CHECK_IRQ5 61
+#define MD_IRQID_TRACE_INT 62
+#define MD_IRQID_SI_CM_PCINT 63
+#define MD_IRQID_PLL_GEARHP_RDY 64
+#define MD_IRQID_MD_BUCK_CTRL_IRQ 65
+#define MD_IRQID_REQ_ABNORM_IRQ 66
+#define MD_IRQID_EINT3 67
+#define MD_IRQID_BT_CVSD 68
+#define MD_IRQID_SSUSB_DEV 69
+#define MD_IRQID_USB_MCU 70
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 71
+#define MD_IRQID_AP2MD_CCIF0_0 72
+#define MD_IRQID_AP2MD_CCIF0_1 73
+#define MD_IRQID_AP2MD_CCIF1_0 74
+#define MD_IRQID_AP2MD_CCIF1_1 75
+#define MD_IRQID_RXDFE_RXK_READBACK 76
+#define MD_IRQID_IDC_PM_INT 77
+#define MD_IRQID_IDC_UART_IRQ 78
+#define MD_IRQID_MDRTT 79
+#define MD_IRQID_MDEVDO 80
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 81
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 82
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 83
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 84
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 85
+#define MD_IRQID_BIGRAM_IRQ 86
+#define MD_IRQID_BR_BDGE_IRQ 87
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 88
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 89
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 90
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 91
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 92
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 93
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 94
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 95
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 96
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 98
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 99
+#define MD_IRQID_TDD_WAKEUP_IRQ 100
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 101
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 102
+#define MD_IRQID_RTR_SLT_0_IRQ 103
+#define MD_IRQID_RTR_SLT_1_IRQ 104
+#define MD_IRQID_FDD_SLP_IRQ 105
+#define MD_IRQID_TDMA_WAKEUP_IRQ 106
+#define MD_IRQID_ST1X_CPINT 107
+#define MD_IRQID_ST1x_HALF_CPINT 108
+#define MD_IRQID_ST1x_CFG_CPINT 109
+#define MD_IRQID_ST1x_WAKEUP_IRQ 110
+#define MD_IRQID_STDO_CPINT 111
+#define MD_IRQID_STDO_HALF_CPINT 112
+#define MD_IRQID_STDO_CFG_CPINT 113
+#define MD_IRQID_STDO_WAKEUP_IRQ 114
+#define MD_IRQID_FREQM_IRQ 115
+#define MD_IRQID_MDMCU_DVFS_CTRL 116
+#define MD_IRQID_PCC_TOP_FULL_IRQ 117
+#define MD_IRQID_GPTM1 118
+#define MD_IRQID_GPTM2 119
+#define MD_IRQID_GPTM3 120
+#define MD_IRQID_GPTM4 121
+#define MD_IRQID_GPTM5 122
+#define MD_IRQID_GPTM6 123
+#define MD_IRQID_GPTM7 124
+#define MD_IRQID_GPTM8 125
+#define MD_IRQID_GPTM9 126
+#define MD_IRQID_GPTM10 127
+#define MD_IRQID_GPTM11 128
+#define MD_IRQID_BUSMPU_IRQ 129
+#define MD_IRQID_MCU_BUS_DECERR 130
+#define MD_IRQID_MCUMMU_INT 131
+#define MD_IRQID_IA_DECERR 132
+#define MD_IRQID_RMPU_CTIREIGIN 133
+#define MD_IRQID_AP2MD_MSDC0 134
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 135
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 136
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 137
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 138
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 139
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 140
+#define MD_IRQID_AP2MD_CCIF2 141
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 142
+#define MD_IRQID_SPU_INT 143
+#define MD_IRQID_SDF_OVERFLOW_IRQ 144
+#define MD_IRQID_MDDFE_DUMP 145
+#define MD_IRQID_AP2MD_CONN_CCIF_0 146
+#define MD_IRQID_AP2MD_CONN_CCIF_1 147
+#define MD_IRQID_I2C_TOP_INT 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 191
+#define MD_IRQID_CONN2MD_PDMA_IRQ 192
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0 193
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1 194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2 195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3 196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4 197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5 198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6 199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7 200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8 201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_9 202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_10 203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT3967_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h
new file mode 100644
index 0000000..241e08c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h
@@ -0,0 +1,222 @@
+#ifndef __MT6295M_IRQID_H__
+#define __MT6295M_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_MDGDMA0 16
+#define MD_IRQID_MDGDMA1 17
+#define MD_IRQID_MDGDMA2 18
+#define MD_IRQID_MDGDMA3 19
+#define MD_IRQID_EINT0 20
+#define MD_IRQID_EINT1 21
+#define MD_IRQID_EINT2 22
+#define MD_IRQID_EINT_SHARE 23
+#define MD_IRQID_BUS_ERR 24
+#define MD_IRQID_TXBSRP 25
+#define MD_IRQID_TXCRP 26
+#define MD_IRQ_ID_MML2_HRT 27
+#define MD_IRQ_ID_MML2_NOTIF 28
+#define MD_IRQ_ID_MML2_EXCEP 29
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 30
+#define MD_IRQID_ECT 31
+#define MD_IRQID_PTP_THERM_INT_INT 32
+#define MD_IRQID_CLDMA 33
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 34
+#define MD_IRQID_ELM_DMA_IRQ 35
+#define MD_IRQID_SOE 36
+#define MD_IRQID_ULSP_LOG_MD_INT 37
+#define MD_IRQID_ULSP_LOG_DSP_INT 38
+#define MD_IRQID_USIP0_0 39
+#define MD_IRQID_USIP1_0 40
+#define MD_IRQID_USIP2_0 41
+#define MD_IRQID_USIP3_0 42
+#define MD_IRQID_USIP0_1 43
+#define MD_IRQID_USIP1_1 44
+#define MD_IRQID_USIP2_1 45
+#define MD_IRQID_SI_CM_ERR 46
+#define MD_IRQID_ABM_INT 47
+#define MD_IRQID_ABM_ERROR_INT 48
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 49
+#define MD_IRQID_ELMTOP_EMI_IRQ 50
+#define MD_IRQID_PPPHA_ENC0_INT 51
+#define MD_IRQID_PPPHA_ENC1_INT 52
+#define MD_IRQID_PPPHA_DEC0_INT 53
+#define MD_IRQID_PPPHA_DEC1_INT 54
+#define MD_IRQID_PTP_FSM_INT 55
+#define MD_IRQID_IEBIT_CHECK_IRQ0 56
+#define MD_IRQID_IEBIT_CHECK_IRQ1 57
+#define MD_IRQID_IEBIT_CHECK_IRQ2 58
+#define MD_IRQID_IEBIT_CHECK_IRQ3 59
+#define MD_IRQID_IEBIT_CHECK_IRQ4 60
+#define MD_IRQID_IEBIT_CHECK_IRQ5 61
+#define MD_IRQID_TRACE_INT 62
+#define MD_IRQID_SI_CM_PCINT 63
+#define MD_IRQID_PLL_GEARHP_RDY 64
+#define MD_IRQID_MD_BUCK_CTRL_IRQ 65
+#define MD_IRQID_REQ_ABNORM_IRQ 66
+#define MD_IRQID_EINT3 67
+#define MD_IRQID_BT_CVSD 68
+#define MD_IRQID_SSUSB_DEV 69
+#define MD_IRQID_USB_MCU 70
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 71
+#define MD_IRQID_AP2MD_CCIF0_0 72
+#define MD_IRQID_AP2MD_CCIF0_1 73
+#define MD_IRQID_AP2MD_CCIF1_0 74
+#define MD_IRQID_AP2MD_CCIF1_1 75
+#define MD_IRQID_RXDFE_RXK_READBACK 76
+#define MD_IRQID_IDC_PM_INT 77
+#define MD_IRQID_IDC_UART_IRQ 78
+#define MD_IRQID_MDRTT 79
+#define MD_IRQID_MDEVDO 80
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 81
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 82
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 83
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 84
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 85
+#define MD_IRQID_BIGRAM_IRQ 86
+#define MD_IRQID_BR_BDGE_IRQ 87
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 88
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 89
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 90
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 91
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 92
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 93
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 94
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 95
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 96
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 98
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 99
+#define MD_IRQID_TDD_WAKEUP_IRQ 100
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 101
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 102
+#define MD_IRQID_RTR_SLT_0_IRQ 103
+#define MD_IRQID_RTR_SLT_1_IRQ 104
+#define MD_IRQID_FDD_SLP_IRQ 105
+#define MD_IRQID_TDMA_WAKEUP_IRQ 106
+#define MD_IRQID_ST1X_CPINT 107
+#define MD_IRQID_ST1x_HALF_CPINT 108
+#define MD_IRQID_ST1x_CFG_CPINT 109
+#define MD_IRQID_ST1x_WAKEUP_IRQ 110
+#define MD_IRQID_STDO_CPINT 111
+#define MD_IRQID_STDO_HALF_CPINT 112
+#define MD_IRQID_STDO_CFG_CPINT 113
+#define MD_IRQID_STDO_WAKEUP_IRQ 114
+#define MD_IRQID_FREQM_IRQ 115
+#define MD_IRQID_MDMCU_DVFS_CTRL 116
+#define MD_IRQID_PCC_TOP_FULL_IRQ 117
+#define MD_IRQID_GPTM1 118
+#define MD_IRQID_GPTM2 119
+#define MD_IRQID_GPTM3 120
+#define MD_IRQID_GPTM4 121
+#define MD_IRQID_GPTM5 122
+#define MD_IRQID_GPTM6 123
+#define MD_IRQID_GPTM7 124
+#define MD_IRQID_GPTM8 125
+#define MD_IRQID_GPTM9 126
+#define MD_IRQID_GPTM10 127
+#define MD_IRQID_GPTM11 128
+#define MD_IRQID_BUSMPU_IRQ 129
+#define MD_IRQID_MCU_BUS_DECERR 130
+#define MD_IRQID_MCUMMU_INT 131
+#define MD_IRQID_IA_DECERR 132
+#define MD_IRQID_RMPU_CTIREIGIN 133
+#define MD_IRQID_AP2MD_MSDC0 134
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 135
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 136
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 137
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 138
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 139
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 140
+#define MD_IRQID_AP2MD_CCIF2 141
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 142
+#define MD_IRQID_SPU_INT 143
+#define MD_IRQID_SDF_OVERFLOW_IRQ 144
+#define MD_IRQID_MDDFE_DUMP 145
+#define MD_IRQID_AP2MD_CONN_CCIF_0 146
+#define MD_IRQID_AP2MD_CONN_CCIF_1 147
+#define MD_IRQID_I2C_TOP_INT 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 191
+#define MD_IRQID_CONN2MD_PDMA_IRQ 192
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0 193
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1 194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2 195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3 196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4 197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5 198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6 199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7 200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8 201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_9 202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_10 203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6295M_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h
new file mode 100644
index 0000000..db4fba9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h
@@ -0,0 +1,222 @@
+#ifndef __MT6779_IRQID_H__
+#define __MT6779_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_MDGDMA0 16
+#define MD_IRQID_MDGDMA1 17
+#define MD_IRQID_MDGDMA2 18
+#define MD_IRQID_MDGDMA3 19
+#define MD_IRQID_EINT0 20
+#define MD_IRQID_EINT1 21
+#define MD_IRQID_EINT2 22
+#define MD_IRQID_EINT_SHARE 23
+#define MD_IRQID_BUS_ERR 24
+#define MD_IRQID_TXBSRP 25
+#define MD_IRQID_TXCRP 26
+#define MD_IRQ_ID_MML2_HRT 27
+#define MD_IRQ_ID_MML2_NOTIF 28
+#define MD_IRQ_ID_MML2_EXCEP 29
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 30
+#define MD_IRQID_ECT 31
+#define MD_IRQID_PTP_THERM_INT_INT 32
+#define MD_IRQID_CLDMA 33
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 34
+#define MD_IRQID_ELM_DMA_IRQ 35
+#define MD_IRQID_SOE 36
+#define MD_IRQID_ULSP_LOG_MD_INT 37
+#define MD_IRQID_ULSP_LOG_DSP_INT 38
+#define MD_IRQID_USIP0_0 39
+#define MD_IRQID_USIP1_0 40
+#define MD_IRQID_USIP2_0 41
+#define MD_IRQID_USIP3_0 42
+#define MD_IRQID_USIP0_1 43
+#define MD_IRQID_USIP1_1 44
+#define MD_IRQID_USIP2_1 45
+#define MD_IRQID_SI_CM_ERR 46
+#define MD_IRQID_ABM_INT 47
+#define MD_IRQID_ABM_ERROR_INT 48
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 49
+#define MD_IRQID_ELMTOP_EMI_IRQ 50
+#define MD_IRQID_PPPHA_ENC0_INT 51
+#define MD_IRQID_PPPHA_ENC1_INT 52
+#define MD_IRQID_PPPHA_DEC0_INT 53
+#define MD_IRQID_PPPHA_DEC1_INT 54
+#define MD_IRQID_PTP_FSM_INT 55
+#define MD_IRQID_IEBIT_CHECK_IRQ0 56
+#define MD_IRQID_IEBIT_CHECK_IRQ1 57
+#define MD_IRQID_IEBIT_CHECK_IRQ2 58
+#define MD_IRQID_IEBIT_CHECK_IRQ3 59
+#define MD_IRQID_IEBIT_CHECK_IRQ4 60
+#define MD_IRQID_IEBIT_CHECK_IRQ5 61
+#define MD_IRQID_TRACE_INT 62
+#define MD_IRQID_SI_CM_PCINT 63
+#define MD_IRQID_PLL_GEARHP_RDY 64
+#define MD_IRQID_MD_BUCK_CTRL_IRQ 65
+#define MD_IRQID_REQ_ABNORM_IRQ 66
+#define MD_IRQID_EINT3 67
+#define MD_IRQID_BT_CVSD 68
+#define MD_IRQID_SSUSB_DEV 69
+#define MD_IRQID_USB_MCU 70
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 71
+#define MD_IRQID_AP2MD_CCIF0_0 72
+#define MD_IRQID_AP2MD_CCIF0_1 73
+#define MD_IRQID_AP2MD_CCIF1_0 74
+#define MD_IRQID_AP2MD_CCIF1_1 75
+#define MD_IRQID_RXDFE_RXK_READBACK 76
+#define MD_IRQID_IDC_PM_INT 77
+#define MD_IRQID_IDC_UART_IRQ 78
+#define MD_IRQID_MDRTT 79
+#define MD_IRQID_MDEVDO 80
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 81
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 82
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 83
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 84
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 85
+#define MD_IRQID_BIGRAM_IRQ 86
+#define MD_IRQID_BR_BDGE_IRQ 87
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 88
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 89
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 90
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 91
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 92
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 93
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 94
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 95
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 96
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 98
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 99
+#define MD_IRQID_TDD_WAKEUP_IRQ 100
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 101
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 102
+#define MD_IRQID_RTR_SLT_0_IRQ 103
+#define MD_IRQID_RTR_SLT_1_IRQ 104
+#define MD_IRQID_FDD_SLP_IRQ 105
+#define MD_IRQID_TDMA_WAKEUP_IRQ 106
+#define MD_IRQID_ST1X_CPINT 107
+#define MD_IRQID_ST1x_HALF_CPINT 108
+#define MD_IRQID_ST1x_CFG_CPINT 109
+#define MD_IRQID_ST1x_WAKEUP_IRQ 110
+#define MD_IRQID_STDO_CPINT 111
+#define MD_IRQID_STDO_HALF_CPINT 112
+#define MD_IRQID_STDO_CFG_CPINT 113
+#define MD_IRQID_STDO_WAKEUP_IRQ 114
+#define MD_IRQID_FREQM_IRQ 115
+#define MD_IRQID_MDMCU_DVFS_CTRL 116
+#define MD_IRQID_PCC_TOP_FULL_IRQ 117
+#define MD_IRQID_GPTM1 118
+#define MD_IRQID_GPTM2 119
+#define MD_IRQID_GPTM3 120
+#define MD_IRQID_GPTM4 121
+#define MD_IRQID_GPTM5 122
+#define MD_IRQID_GPTM6 123
+#define MD_IRQID_GPTM7 124
+#define MD_IRQID_GPTM8 125
+#define MD_IRQID_GPTM9 126
+#define MD_IRQID_GPTM10 127
+#define MD_IRQID_GPTM11 128
+#define MD_IRQID_BUSMPU_IRQ 129
+#define MD_IRQID_MCU_BUS_DECERR 130
+#define MD_IRQID_MCUMMU_INT 131
+#define MD_IRQID_IA_DECERR 132
+#define MD_IRQID_RMPU_CTIREIGIN 133
+#define MD_IRQID_AP2MD_MSDC0 134
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 135
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 136
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 137
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 138
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 139
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 140
+#define MD_IRQID_AP2MD_CCIF2 141
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 142
+#define MD_IRQID_SPU_INT 143
+#define MD_IRQID_SDF_OVERFLOW_IRQ 144
+#define MD_IRQID_MDDFE_DUMP 145
+#define MD_IRQID_AP2MD_CONN_CCIF_0 146
+#define MD_IRQID_AP2MD_CONN_CCIF_1 147
+#define MD_IRQID_I2C_TOP_INT 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 191
+#define MD_IRQID_CONN2MD_PDMA_IRQ 192
+#define MD_IRQID_CONN_BT_ISOCH 193
+#define MD_IRQID_AP2MD_UFS 194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0 195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1 196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2 197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3 198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4 199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5 200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6 201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7 202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8 203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6779_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/isrentry.h b/mcu/interface/driver/devdrv/cirq/md95/isrentry.h
new file mode 100644
index 0000000..7fa5cf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/isrentry.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * isrentry.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct
+{
+ kal_uint32 vector;
+ void (*lisr_handler) (kal_uint32);
+ kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl.h
new file mode 100644
index 0000000..41328c2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl.h
@@ -0,0 +1,422 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MT6297)
+#include "intrCtrl_MT6297.h"
+#endif
+
+#if defined(MT6885)
+#include "intrCtrl_MT6885.h"
+#endif
+
+#if defined(MT6873)
+#include "intrCtrl_MT6873.h"
+#endif
+
+#if defined(MT6853)
+#include "intrCtrl_MT6853.h"
+#endif
+
+#if defined(MT6833)
+#include "intrCtrl_MT6833.h"
+#endif
+
+#if defined(MT6877)
+#include "intrCtrl_MT6877.h"
+#endif
+
+#if defined(CHIP10992)
+#include "intrCtrl_CHIP10992.h"
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+// CIRQ MPB Statistic Enable Option
+#if !defined(__MPB_DISABLE__)
+#define __MDCIRQ_MPB_PROFILE__
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define EDGE_SENSITIVE KAL_TRUE
+#define LEVEL_SENSITIVE KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+ kal_uint32 irq_mask[12];
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+ Need to modify 3 files
+ 1. add a file intrCtrl_MTxxxx_SW_Handler.h
+ 2. add an entry on intrCtrl_SW_Handler.h
+ 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+ SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Activate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern const kal_uint16 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a) (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint16);
+extern void MDCIRQ_IRQMask(kal_uint16);
+extern void MDCIRQ_IRQUnmask(kal_uint16);
+extern void MDCIRQ_IRQSensitivity(kal_uint16, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint16 code);
+extern kal_uint32 IRQ_Status(void);
+
+#if defined(__MAUI_BASIC__) || !defined(__MTK_TARGET__)
+#define IRQ_Register_LISR(code, lisr, description) \
+ MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint16 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+#endif
+
+#define NRIRQ_Affinity_Change_NSA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA()
+#define NRIRQ_Affinity_Change_SA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA()
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA();
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA();
+
+#define LTEIRQ_Affinity_Change_ENDC() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC()
+#define LTEIRQ_Affinity_Change_LTEONLY() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY()
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC();
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY();
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+ IRQ_PRIORITY_END,
+#if defined __MIPS_I7200__
+ IRQ_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+ IRQ_EQUALLY_DISPATCH_PRIORITY_THRESHOLD = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE_PRIORITY,
+#else /* MT6297_IA */
+ IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+#endif
+} IRQ_PRIORITY;
+
+typedef enum {
+ MDCIRQ_To_BUS_Normal = 0x0,
+ MDCIRQ_To_BUS_PreUltra = 0x1,
+ MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR() (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+// #define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && (defined(__MIPS_IA__) || defined(__MIPS_I7200__))
+#if defined(__NESTED_DI_CHECK__) && !defined (__ESL_MASE_GEN97__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ kal_uint32 vpe_num = 0;\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+ vpe_num = miu_get_current_vpe_id();\
+ sst_dhl_irq_count[vpe_num]++;\
+ sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+ DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992.h
new file mode 100644
index 0000000..b25f0f9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_CHIP10992.h
+ *
+ * Project:
+ * --------
+ * CHIP10992
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_CHIP10992_H__
+#define __INTRCTRL_CHIP10992_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_CLDMA0_MD_IRQ_CODE MD_IRQID_CLDMA0_MD_IRQ
+#define IRQ_CLDMA1_MD_IRQ_CODE MD_IRQID_CLDMA1_MD_IRQ
+#define IRQ_CLDMA2_MD_IRQ_CODE MD_IRQID_CLDMA2_MD_IRQ
+#define IRQ_CLDMA3_MD_IRQ_CODE MD_IRQID_CLDMA3_MD_IRQ
+#define IRQ_MHCCIF_SAP2USIP_IRQ_CODE MD_IRQID_MHCCIF_SAP2USIP_IRQ
+#define IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE MD_IRQID_MHCCIF_SAP2MDMCU_IRQ
+#define IRQ_NFI_MD_CODE MD_IRQID_NFI_MD
+#define IRQ_CLDMA1_AP_INT_PCIE_MD_CODE MD_IRQID_CLDMA1_AP_INT_PCIE_MD
+#define IRQ_CLDMA3_AP_INT_PCIE_MD_CODE MD_IRQID_CLDMA3_AP_INT_PCIE_MD
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25(0,3,5,6,7,8,9,11) -> Workaround for Serdes HW bug */ 0x416, \
+ /* Group26(0,2,3,6,7,9,10) -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 342,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_CHIP10992_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992_SW_Handle.h
new file mode 100644
index 0000000..504958f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_CHIP10992_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * CHIP10992
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297.h
new file mode 100644
index 0000000..78b26fa
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297.h
@@ -0,0 +1,801 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6297.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6297_H__
+#define __INTRCTRL_MT6297_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (368)
+
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ0
+#define IRQ_CLDMA0_MD_IRQ_CODE MD_IRQID_CLDMA0_MD_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ1
+#define IRQ_CLDMA1_MD_IRQ_CODE MD_IRQID_CLDMA1_MD_IRQ
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_MDGDMA4_CODE MD_IRQID_MDGDMA4
+#define IRQ_MDGDMA5_CODE MD_IRQID_MDGDMA5
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_RXDFE_IRQ1_CODE MD_IRQID_RXDFE_IRQ1
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_RXDFE_IRQ4_CODE MD_IRQID_RXDFE_IRQ4
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_RXDFE_IRQ6_CODE MD_IRQID_RXDFE_IRQ6
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_NFI_MD_CODE MD_IRQID_NFI_MD
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_MHCCIF_SAP2USIP_IRQ_CODE MD_IRQID_MHCCIF_SAP2USIP_IRQ
+#define IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE MD_IRQID_MHCCIF_SAP2MDMCU_IRQ
+#define IRQ_MUSB_INTERRUPT_OUT_CODE MD_IRQID_MUSB_INTERRUPT_OUT
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_READ_IRQ_CODE MD_IRQID_MIPI_READ_IRQ
+#define IRQ_CLDMA2_MD_IRQ_CODE MD_IRQID_CLDMA2_MD_IRQ
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ7
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~223 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*224 ~231 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*232 ~239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~255 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*256 ~263 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*264 ~271 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*272 ~279 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*280 ~287 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*288 ~295 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*296 ~303 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*304 ~311 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*312 ~319 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*320 ~327 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*328 ~335 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*336 ~343 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*344 ~351 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*352 ~359 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*360 ~367 */ 0, 0, 0, 0, 0, 0, 1, 2
+
+#elif defined(__MD97_IS_2CORES__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 7, 7, 1, 1, 1, 1, 0, 1, \
+ /* 8 ~ 15 */ 1, 7, 7, 7, 7, 7, 7, 1, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 12, \
+ /* 24 ~ 31 */ 12, 11, 12, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 7, 0, 12, 12, 7, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 7, 0, 1, \
+ /* 96 ~ 103 */ 1, 1, 1, 1, 1, 7, 7, 0, \
+ /*104 ~ 111 */ 0, 0, 1, 1, 1, 1, 1, 1, \
+ /*112 ~ 119 */ 1, 1, 7, 7, 7, 7, 7, 7, \
+ /*120 ~ 127 */ 7, 7, 7, 7, 7, 7, 1, 1, \
+ /*128 ~ 135 */ 7, 7, 7, 7, 0, 0, 0, 7, \
+ /*136 ~ 143 */ 0, 7, 12, 7, 7, 0, 0, 0, \
+ /*144 ~ 151 */ 11, 1, 1, 11, 11, 11, 11, 11, \
+ /*152 ~ 159 */ 11, 11, 9, 1, 1, 0, 0, 0, \
+ /*160 ~ 167 */ 0, 7, 12, 12, 12, 12, 0, 0, \
+ /*168 ~ 175 */ 0, 0, 0, 12, 7, 8, 8, 8, \
+ /*176 ~ 183 */ 7, 7, 7, 12, 7, 7, 0, 1, \
+ /*184 ~ 191 */ 2, 3, 4, 5, 0, 0, 0, 0, \
+ /*192 ~ 199 */ 0, 0, 12, 12, 12, 0, 0, 0, \
+ /*200 ~ 207 */ 12, 0, 0, 1, 0, 0, 0, 0, \
+ /*208 ~ 215 */ 4, 11, 11, 11, 11, 1, 4, 7, \
+ /*216 ~ 223 */ 7, 7, 12, 12, 12, 12, 12, 12, \
+ /*224 ~ 231 */ 7, 7, 0, 12, 0, 0, 0, 0, \
+ /*232 ~ 239 */ 6, 1, 4, 1, 1, 1, 4, 1, \
+ /*240 ~ 247 */ 0, 4, 1, 1, 1, 1, 4, 1, \
+ /*248 ~ 255 */ 12, 7, 0, 0, 0, 0, 0, 0, \
+ /*256 ~ 263 */ 0, 12, 1, 1, 7, 1, 1, 0, \
+ /*264 ~ 271 */ 12, 12, 12, 7, 7, 7, 0, 0, \
+ /*272 ~ 279 */ 7, 7, 7, 12, 0, 12, 0, 0, \
+ /*280 ~ 287 */ 1, 1, 1, 4, 1, 4, 1, 1, \
+ /*288 ~ 295 */ 1, 1, 1, 1, 1, 1, 12, 0, \
+ /*296 ~ 303 */ 8, 0, 0, 0, 0, 0, 0, 3, \
+ /*304 ~ 311 */ 0, 0, 12, 0, 0, 1, 7, 1, \
+ /*312 ~ 319 */ 1, 0, 0, 0, 0, 0, 0, 0, \
+ /*320 ~ 327 */ 10, 7, 7, 7, 7, 7, 7, 7, \
+ /*328 ~ 335 */ 7, 7, 7, 7, 7, 0, 1, 2, \
+ /*336 ~ 343 */ 3, 4, 5, 0, 0, 0, 0, 0, \
+ /*344 ~ 351 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*352 ~ 359 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*360 ~ 367 */ 0, 0, 0, 0, 0, 0, 0, 0
+#else
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 15, 15, 1, 1, 1, 1, 0, 0, \
+ /* 8 ~ 15 */ 1, 15, 15, 15, 15, 15, 15, 1, \
+ /* 16 ~ 23 */ 16, 16, 18, 18, 18, 18, 19, 19, \
+ /* 24 ~ 31 */ 19, 17, 19, 15, 15, 15, 15, 16, \
+ /* 32 ~ 39 */ 16, 15, 17, 19, 19, 15, 10, 16, \
+ /* 40 ~ 47 */ 16, 14, 14, 14, 14, 14, 14, 14, \
+ /* 48 ~ 55 */ 14, 14, 14, 14, 14, 14, 14, 14, \
+ /* 56 ~ 63 */ 14, 14, 14, 14, 14, 14, 14, 14, \
+ /* 64 ~ 71 */ 14, 14, 18, 14, 14, 14, 14, 16, \
+ /* 72 ~ 79 */ 16, 16, 18, 18, 18, 18, 18, 18, \
+ /* 80 ~ 87 */ 18, 14, 14, 14, 14, 14, 14, 14, \
+ /* 88 ~ 95 */ 16, 16, 14, 14, 14, 19, 15, 1, \
+ /* 96 ~ 103 */ 1, 1, 1, 1, 1, 15, 15, 15, \
+ /*104 ~ 111 */ 15, 15, 1, 1, 1, 1, 1, 1, \
+ /*112 ~ 119 */ 1, 1, 15, 15, 15, 15, 15, 15, \
+ /*120 ~ 127 */ 15, 15, 15, 17, 15, 15, 17, 1, \
+ /*128 ~ 135 */ 15, 15, 15, 15, 0, 0, 0, 15, \
+ /*136 ~ 143 */ 0, 15, 19, 15, 15, 15, 15, 0, \
+ /*144 ~ 151 */ 17, 1, 1, 17, 17, 17, 17, 17, \
+ /*152 ~ 159 */ 17, 17, 17, 1, 1, 18, 18, 18, \
+ /*160 ~ 167 */ 15, 15, 19, 19, 15, 15, 15, 15, \
+ /*168 ~ 175 */ 15, 15, 15, 19, 15, 17, 15, 17, \
+ /*176 ~ 183 */ 15, 15, 15, 19, 15, 15, 0, 1, \
+ /*184 ~ 191 */ 2, 3, 4, 5, 6, 7, 8, 9, \
+ /*192 ~ 199 */ 10, 11, 17, 17, 17, 15, 17, 15, \
+ /*200 ~ 207 */ 15, 17, 15, 1, 15, 15, 16, 16, \
+ /*208 ~ 215 */ 17, 17, 17, 17, 17, 1, 4, 17, \
+ /*216 ~ 223 */ 17, 15, 19, 19, 19, 19, 19, 19, \
+ /*224 ~ 231 */ 15, 15, 15, 19, 0, 0, 0, 15, \
+ /*232 ~ 239 */ 13, 1, 4, 1, 1, 1, 4, 1, \
+ /*240 ~ 247 */ 0, 4, 1, 1, 1, 1, 4, 1, \
+ /*248 ~ 255 */ 15, 15, 15, 10, 17, 14, 19, 18, \
+ /*256 ~ 263 */ 14, 19, 1, 1, 15, 1, 0, 15, \
+ /*264 ~ 271 */ 15, 15, 15, 15, 15, 15, 15, 15, \
+ /*272 ~ 279 */ 15, 15, 15, 19, 15, 19, 17, 0, \
+ /*280 ~ 287 */ 1, 1, 1, 4, 1, 4, 1, 1, \
+ /*288 ~ 295 */ 1, 1, 1, 1, 1, 12, 19, 15, \
+ /*296 ~ 303 */ 17, 0, 0, 3, 6, 9, 0, 3, \
+ /*304 ~ 311 */ 6, 9, 19, 15, 15, 15, 15, 1, \
+ /*312 ~ 319 */ 1, 16, 16, 18, 18, 16, 14, 14, \
+ /*320 ~ 327 */ 17, 19, 19, 15, 15, 15, 15, 15, \
+ /*328 ~ 335 */ 15, 15, 15, 15, 19, 0, 1, 2, \
+ /*336 ~ 343 */ 3, 4, 5, 6, 7, 8, 9, 10, \
+ /*344 ~ 351 */ 11, 0, 0, 0, 0, 0, 0, 0, \
+ /*352 ~ 359 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*360 ~ 367 */ 0, 0, 0, 0, 0, 0, 0, 0
+#endif
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#elif defined(__MD97_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(0,1) */ 0xFFC, \
+ /* Group7(0,3) */ 0xFF6, \
+ /* Group8(1,4) */ 0xFED, \
+ /* Group9(3,4) */ 0xFE7, \
+ /* Group10(2,4,5) */ 0xFCB, \
+ /* Group11(0,1,3,4) */ 0xFE4, \
+ /* Group12(0,1,2,3,4,5) */ 0xFC0, \
+ /* Group13 */ 0xFFF, \
+ /* Group14 */ 0xFFF, \
+ /* Group15 */ 0xFFF, \
+ /* Group16 */ 0xFFF, \
+ /* Group17 */ 0xFFF, \
+ /* Group18 */ 0xFFF, \
+ /* Group19 */ 0xFFF, \
+ /* Group20 */ 0xFFF, \
+ /* Group21 */ 0xFFF, \
+ /* Group22 */ 0xFFF, \
+ /* Group23 */ 0xFFF, \
+ /* Group24 */ 0xFFF, \
+ /* Group25 */ 0xFFF, \
+ /* Group26 */ 0xFFF, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25 */ 0xFFF, \
+ /* Group26 */ 0xFFF, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~ 103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~ 111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~ 119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~ 127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~ 135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~ 143 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*144 ~ 151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~ 159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~ 167 */ 0, 0, 1, 1, 1, 1, 0, 0, \
+ /*168 ~ 175 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /*176 ~ 183 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~ 191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~ 199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~ 207 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*208 ~ 215 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*216 ~ 223 */ 0, 0, 1, 1, 1, 1, 1, 1, \
+ /*224 ~ 231 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /*232 ~ 239 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*240 ~ 247 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*248 ~ 255 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*256 ~ 263 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*264 ~ 271 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*272 ~ 279 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*280 ~ 287 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*288 ~ 295 */ 0, 0, 0, 0, 0, 1, 1, 0, \
+ /*296 ~ 303 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*304 ~ 311 */ 0, 0, 1, 1, 0, 0, 1, 0, \
+ /*312 ~ 319 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*320 ~ 327 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*328 ~ 335 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*336 ~ 343 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*344 ~ 351 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*352 ~ 359 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*360 ~ 367 */ 0, 0, 0, 0, 0, 0, 0, 0
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 337,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6297_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297_SW_Handle.h
new file mode 100644
index 0000000..9ab2495
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297_SW_Handle.h
@@ -0,0 +1,226 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6297_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6297
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 07 2018 chia-han.wu
+ * [MOLY00351302] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * 1. Reduce IRQ numbers from 372 to 368
+ * 2. Reduce YQ signals from 7 to 6
+ * 3. Define CRT Registers for Gen97
+ * 4. Raise TC priority in MIN_SAVE and reset TC priority according to IRQ priority in isrC_Main
+ * 5. Remove kal_if_hrt_domain and kal_if_chrt_domain and use kal_get_current_domain instead
+ * 6. Create drv_mdcirq_per_VPE_domain_type array to save all VPE's domain type
+ * 7. Reinitialize di_tc in interrupt_preinit
+ * 8. drv_mdcirq.c driver code modification
+ * 9. IRQ Configuration Settings according to Gen97_MDCIRQ_IRQ_Affinity_UserGuide
+ * 10. Remove redundant code
+ * 11. Bus monitor Runtime configure IRQ configuration settings
+ *
+ * 05 09 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * merge 97 MDCIRQ driver to UMOLYE.
+ *
+ * 05 08 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * check-in MDCIRQ driver for Gen97.
+ *
+ * 05 08 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * check-in MDCIRQ driver for Gen97.
+ *
+ * 03 07 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * fix build error.
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833.h
new file mode 100644
index 0000000..0739c93
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6833.h
+ *
+ * Project:
+ * --------
+ * MT6833
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6833_H__
+#define __INTRCTRL_MT6833_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25(0,3,5,6,7,8,9,11) -> Workaround for Serdes HW bug */ 0x416, \
+ /* Group26(0,2,3,6,7,9,10) -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 342,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6833_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833_SW_Handle.h
new file mode 100644
index 0000000..39efca2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6833_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6833
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853.h
new file mode 100644
index 0000000..518e661
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6853.h
+ *
+ * Project:
+ * --------
+ * MT6853
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6853_H__
+#define __INTRCTRL_MT6853_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25(0,3,5,6,7,8,9,11) -> Workaround for Serdes HW bug */ 0x416, \
+ /* Group26(0,2,3,6,7,9,10) -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 342,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6853_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853_SW_Handle.h
new file mode 100644
index 0000000..522593f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6853_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6853
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873.h
new file mode 100644
index 0000000..ba872eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6873.h
+ *
+ * Project:
+ * --------
+ * MT6873
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6873_H__
+#define __INTRCTRL_MT6873_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25(0,3,5,6,7,8,9,11) -> Workaround for Serdes HW bug */ 0x416, \
+ /* Group26(0,2,3,6,7,9,10) -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 342,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6873_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873_SW_Handle.h
new file mode 100644
index 0000000..0b3881c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6873_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6873
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877.h
new file mode 100644
index 0000000..e0b2360
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6877.h
+ *
+ * Project:
+ * --------
+ * MT6833
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6877_H__
+#define __INTRCTRL_MT6877_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25(0,3,5,6,7,8,9,11) -> Workaround for Serdes HW bug */ 0x416, \
+ /* Group26(0,2,3,6,7,9,10) -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 342,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6877_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877_SW_Handle.h
new file mode 100644
index 0000000..62e02dd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6877_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6877
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885.h
new file mode 100644
index 0000000..631e754
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6885.h
+ *
+ * Project:
+ * --------
+ * MT6885
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6885_H__
+#define __INTRCTRL_MT6885_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24(3,6,7,9,10) -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */ 0x937, \
+ /* Group25(0,3,5,6,7,8,9,11) -> Workaround for Serdes HW bug */ 0x416, \
+ /* Group26(0,2,3,6,7,9,10) -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS 256
+#define MAX_HISR_PRIORITY 2
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 340,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6885_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885_SW_Handle.h
new file mode 100644
index 0000000..241d5ad
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6885_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6885
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..7a3ca5a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_SW_Handle.h
@@ -0,0 +1,121 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6297)
+ #include "intrCtrl_MT6297_SW_Handle.h"
+#endif
+
+#if defined(MT6885)
+ #include "intrCtrl_MT6885_SW_Handle.h"
+#endif
+
+#if defined(MT6873)
+ #include "intrCtrl_MT6873_SW_Handle.h"
+#endif
+
+#if defined(MT6853)
+ #include "intrCtrl_MT6853_SW_Handle.h"
+#endif
+
+#if defined(MT6833)
+ #include "intrCtrl_MT6833_SW_Handle.h"
+#endif
+
+#if defined(MT6877)
+ #include "intrCtrl_MT6877_SW_Handle.h"
+#endif
+
+#if defined(CHIP10992)
+ #include "intrCtrl_CHIP10992_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority.h
new file mode 100644
index 0000000..318d6cc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority.h
@@ -0,0 +1,27 @@
+#if defined(MT6297)
+ #include "irqPriority_MT6297.h"
+#endif
+
+#if defined(MT6885)
+ #include "irqPriority_MT6885.h"
+#endif
+
+#if defined(MT6873)
+ #include "irqPriority_MT6873.h"
+#endif
+
+#if defined(MT6853)
+ #include "irqPriority_MT6853.h"
+#endif
+
+#if defined(MT6833)
+ #include "irqPriority_MT6833.h"
+#endif
+
+#if defined(MT6877)
+ #include "irqPriority_MT6877.h"
+#endif
+
+#if defined(CHIP10992)
+ #include "irqPriority_CHIP10992.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_CHIP10992.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_CHIP10992.h
new file mode 100644
index 0000000..21b3909
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_CHIP10992.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_CLDMA0_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA1_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA2_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA3_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2USIP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NFI_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA1_AP_INT_PCIE_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA3_AP_INT_PCIE_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6297.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6297.h
new file mode 100644
index 0000000..4f2f28e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6297.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_READ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2USIP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA2_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA0_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA1_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NFI_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6833.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6833.h
new file mode 100644
index 0000000..2accbab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6833.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6853.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6853.h
new file mode 100644
index 0000000..2accbab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6853.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6873.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6873.h
new file mode 100644
index 0000000..d117327
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6873.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6877.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6877.h
new file mode 100644
index 0000000..2accbab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6877.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6885.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6885.h
new file mode 100644
index 0000000..94eb3bd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6885.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid.h b/mcu/interface/driver/devdrv/cirq/md97/irqid.h
new file mode 100644
index 0000000..e7d88b7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid.h
@@ -0,0 +1,32 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6297)
+ #include "irqid_MT6297.h"
+#endif
+
+#if defined(MT6885)
+ #include "irqid_MT6885.h"
+#endif
+
+#if defined(MT6873)
+ #include "irqid_MT6873.h"
+#endif
+
+#if defined(MT6853)
+ #include "irqid_MT6853.h"
+#endif
+
+#if defined(MT6833)
+ #include "irqid_MT6833.h"
+#endif
+
+#if defined(MT6877)
+ #include "irqid_MT6877.h"
+#endif
+
+#if defined(CHIP10992)
+ #include "irqid_CHIP10992.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_CHIP10992.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_CHIP10992.h
new file mode 100644
index 0000000..69ab11e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_CHIP10992.h
@@ -0,0 +1,388 @@
+#ifndef __CHIP10992_IRQID_H__
+#define __CHIP10992_IRQID_H__
+
+
+//CHIP10992 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ 228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_CLDMA0_MD_IRQ 345
+#define MD_IRQID_CLDMA1_MD_IRQ 346
+#define MD_IRQID_CLDMA2_MD_IRQ 347
+#define MD_IRQID_CLDMA3_MD_IRQ 348
+#define MD_IRQID_MHCCIF_SAP2USIP_IRQ 349
+#define MD_IRQID_MHCCIF_SAP2MDMCU_IRQ 350
+#define MD_IRQID_NFI_MD 351
+#define MD_IRQID_CLDMA1_AP_INT_PCIE_MD 352
+#define MD_IRQID_CLDMA3_AP_INT_PCIE_MD 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __CHIP10992_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6297.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6297.h
new file mode 100644
index 0000000..d7de046
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6297.h
@@ -0,0 +1,387 @@
+#ifndef __MT6297_IRQID_H__
+#define __MT6297_IRQID_H__
+
+
+//Gen97 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_DUMMY_PRIORITY_IRQ0 134
+#define MD_IRQID_CLDMA0_MD_IRQ 135
+#define MD_IRQID_DUMMY_PRIORITY_IRQ1 136
+#define MD_IRQID_CLDMA1_MD_IRQ 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA0 172
+#define MD_IRQID_MDGDMA1 173
+#define MD_IRQID_MDGDMA2 174
+#define MD_IRQID_MDGDMA3 175
+#define MD_IRQID_MDGDMA4 176
+#define MD_IRQID_MDGDMA5 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_RXDFE_IRQ1 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_RXDFE_IRQ4 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_RXDFE_IRQ6 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3 228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_NFI_MD 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_MHCCIF_SAP2USIP_IRQ 270
+#define MD_IRQID_MHCCIF_SAP2MDMCU_IRQ 271
+#define MD_IRQID_MUSB_INTERRUPT_OUT 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_READ_IRQ 275
+#define MD_IRQID_CLDMA2_MD_IRQ 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_DUMMY_PRIORITY_IRQ7 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6297_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6833.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6833.h
new file mode 100644
index 0000000..a7e7eb6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6833.h
@@ -0,0 +1,388 @@
+#ifndef __MT6833_IRQID_H__
+#define __MT6833_IRQID_H__
+
+
+//MT6833 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ 228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6833_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6853.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6853.h
new file mode 100644
index 0000000..276b39e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6853.h
@@ -0,0 +1,388 @@
+#ifndef __MT6853_IRQID_H__
+#define __MT6853_IRQID_H__
+
+
+//MT6853 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ 228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6853_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6873.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6873.h
new file mode 100644
index 0000000..fe017a6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6873.h
@@ -0,0 +1,388 @@
+#ifndef __MT6873_IRQID_H__
+#define __MT6873_IRQID_H__
+
+
+//MT6873 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ 228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6873_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6877.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6877.h
new file mode 100644
index 0000000..3bf835b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6877.h
@@ -0,0 +1,388 @@
+#ifndef __MT6877_IRQID_H__
+#define __MT6877_IRQID_H__
+
+
+//MT6877 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ 228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6877_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6885.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6885.h
new file mode 100644
index 0000000..ed37ecc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6885.h
@@ -0,0 +1,388 @@
+#ifndef __MT6885_IRQID_H__
+#define __MT6885_IRQID_H__
+
+
+//MT6885 IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3 228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6885_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/isrentry.h b/mcu/interface/driver/devdrv/cirq/md97/isrentry.h
new file mode 100644
index 0000000..7fa5cf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/isrentry.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * isrentry.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct
+{
+ kal_uint32 vector;
+ void (*lisr_handler) (kal_uint32);
+ kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h
new file mode 100644
index 0000000..9228b1b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h
@@ -0,0 +1,294 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MERCURY)
+#include "intrCtrl_MERCURY.h"
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define EDGE_SENSITIVE KAL_TRUE
+#define LEVEL_SENSITIVE KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+ kal_uint32 irq_mask[12];
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+ Need to modify 3 files
+ 1. add a file intrCtrl_MTxxxx_SW_Handler.h
+ 2. add an entry on intrCtrl_SW_Handler.h
+ 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+ SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Activate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern const kal_uint16 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a) (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint16);
+extern void MDCIRQ_IRQMask(kal_uint16);
+extern void MDCIRQ_IRQUnmask(kal_uint16);
+extern void MDCIRQ_IRQSensitivity(kal_uint16, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint16 code);
+extern kal_uint32 IRQ_Status(void);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+ MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint16 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+#define NRIRQ_Affinity_Change_NSA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA()
+#define NRIRQ_Affinity_Change_SA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA()
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA();
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA();
+
+#define LTEIRQ_Affinity_Change_ENDC() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC()
+#define LTEIRQ_Affinity_Change_LTEONLY() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY()
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC();
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY();
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+ IRQ_PRIORITY_END,
+ IRQ_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+ IRQ_EQUALLY_DISPATCH_PRIORITY_THRESHOLD = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE_PRIORITY,
+} IRQ_PRIORITY;
+
+typedef enum {
+ MDCIRQ_To_BUS_Normal = 0x0,
+ MDCIRQ_To_BUS_PreUltra = 0x1,
+ MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR() (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+#define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && (defined(__MIPS_IA__) || defined(__MIPS_I7200__))
+#if defined(__NESTED_DI_CHECK__) && !defined (__ESL_MASE_GEN97__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ kal_uint32 vpe_num = 0;\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+ vpe_num = miu_get_current_vpe_id();\
+ sst_dhl_irq_count[vpe_num]++;\
+ sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+ DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h
new file mode 100644
index 0000000..9ab9a29
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h
@@ -0,0 +1,561 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MERCURY.h
+ *
+ * Project:
+ * --------
+ * MERCURY
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MERCURY_H__
+#define __INTRCTRL_MERCURY_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24 */ 0xFFF, \
+ /* Group25 */ 0xFFF, \
+ /* Group26 */ 0xFFF, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 337,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST+KAL_MAX_NUM_TASKS,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MERCURY_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h
new file mode 100644
index 0000000..ce65e41
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MERCURY_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MERCURY
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..5499477
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MERCURY)
+ #include "intrCtrl_MERCURY_SW_Handle.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h
new file mode 100644
index 0000000..07b86ff
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h
@@ -0,0 +1,3 @@
+#if defined(MERCURY)
+ #include "irqPriority_MERCURY.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h
new file mode 100644
index 0000000..8bbd894
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqid.h b/mcu/interface/driver/devdrv/cirq/md97p/irqid.h
new file mode 100644
index 0000000..e30d214
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqid.h
@@ -0,0 +1,8 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MERCURY)
+ #include "irqid_MERCURY.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h
new file mode 100644
index 0000000..39d74a3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h
@@ -0,0 +1,388 @@
+#ifndef __MERCURY_IRQID_H__
+#define __MERCURY_IRQID_H__
+
+
+//MERCURY IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3 228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MERCURY_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h b/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h
new file mode 100644
index 0000000..63ba404
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h
@@ -0,0 +1,103 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * isrentry.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct
+{
+ kal_uint32 vector;
+ void (*lisr_handler) (kal_uint32);
+ kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+