[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h
new file mode 100644
index 0000000..dbbfd6c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h
@@ -0,0 +1,324 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MT6295M)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6295M.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6295M MDSYS."
+#endif
+#endif
+
+#if defined(MT3967)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT3967.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT3967 MDSYS."
+#endif
+#endif
+
+#if defined(MT6779)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6779.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6779 MDSYS."
+#endif
+#endif
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+
+#define EDGE_SENSITIVE KAL_TRUE
+#define LEVEL_SENSITIVE KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+ kal_uint32 irq_mask[8];
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+ Need to modify 3 files
+ 1. add a file intrCtrl_MTxxxx_SW_Handler.h
+ 2. add an entry on intrCtrl_SW_Handler.h
+ 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+ SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern const kal_uint8 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a) (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint8);
+extern void MDCIRQ_IRQMask(kal_uint8);
+extern void MDCIRQ_IRQUnmask(kal_uint8);
+extern void MDCIRQ_IRQSensitivity(kal_uint8, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint8 code);
+extern kal_uint32 IRQ_Status(void);
+extern kal_bool MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(kal_uint32 VPE, kal_uint32 code);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+ MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+//extern void IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+ IRQ_PRIORITY_END,
+ IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD = IRQ_USIP1_1_CODE_PRIORITY + 1,
+} IRQ_PRIORITY;
+
+typedef enum {
+ MDCIRQ_To_BUS_Normal = 0x0,
+ MDCIRQ_To_BUS_PreUltra = 0x1,
+ MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR() (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+// #define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && defined(__MIPS_IA__)
+#if defined(__NESTED_DI_CHECK__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ kal_uint32 vpe_num = 0;\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+ vpe_num = miu_get_current_vpe_id();\
+ sst_dhl_irq_count[vpe_num]++;\
+ sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+ DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h
new file mode 100644
index 0000000..78924fc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h
@@ -0,0 +1,664 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT3967.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT3967_H__
+#define __INTRCTRL_MT3967_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (204)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_MD_BUCK_CTRL_IRQ_CODE MD_IRQID_MD_BUCK_CTRL_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_USB_MCU_CODE MD_IRQID_USB_MCU
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDMCU_DVFS_CTRL_CODE MD_IRQID_MDMCU_DVFS_CTRL
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_IA_DECERR_CODE MD_IRQID_IA_DECERR
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_SPU_INT_CODE MD_IRQID_SPU_INT
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_AP2MD_CONN_CCIF_0_CODE MD_IRQID_AP2MD_CONN_CCIF_0
+#define IRQ_AP2MD_CONN_CCIF_1_CODE MD_IRQID_AP2MD_CONN_CCIF_1
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_CONN2MD_PDMA_IRQ_CODE MD_IRQID_CONN2MD_PDMA_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define IRQ_DUMMY_PRIORITY_CODE_2 MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ_8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ_9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ_10
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~203 */ 0, 0, 0, 0,
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 6, 1, 1, 1, 1, 1, 11, \
+ /* 8 ~ 15 */ 6, 6, 7, 6, 6, 0, 6, 6, \
+ /* 16 ~ 23 */ 6, 7, 6, 6, 6, 6, 6, 6, \
+ /* 24 ~ 31 */ 7, 1, 6, 6, 6, 6, 6, 7, \
+ /* 32 ~ 39 */ 6, 6, 6, 6, 6, 6, 6, 0, \
+ /* 40 ~ 47 */ 3, 1, 1, 10, 10, 3, 6, 0, \
+ /* 48 ~ 55 */ 0, 6, 6, 6, 6, 6, 6, 6, \
+ /* 56 ~ 63 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /* 64 ~ 71 */ 6, 6, 0, 6, 6, 6, 6, 6, \
+ /* 72 ~ 79 */ 6, 7, 6, 6, 1, 6, 6, 6, \
+ /* 80 ~ 87 */ 1, 1, 1, 1, 1, 1, 7, 6, \
+ /* 88 ~ 95 */ 3, 9, 12, 1, 1, 3, 1, 1, \
+ /* 96 ~103 */ 1, 3, 1, 3, 1, 1, 1, 1, \
+ /*104 ~111 */ 3, 1, 1, 1, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 1, 1, 0, 6, 6, 6, 6, \
+ /*120 ~127 */ 6, 6, 6, 1, 1, 7, 6, 6, \
+ /*128 ~135 */ 6, 7, 7, 6, 6, 7, 6, 12, \
+ /*136 ~143 */ 12, 1, 3, 12, 11, 6, 7, 6, \
+ /*144 ~151 */ 6, 1, 6, 6, 6, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 8, 7, 6, 8, 0, 0, \
+ /*168 ~175 */ 2, 4, 7, 0, 2, 4, 1, 1, \
+ /*176 ~183 */ 6, 6, 1, 6, 6, 6, 6, 0, \
+ /*184 ~191 */ 1, 2, 3, 4, 5, 6, 6, 6, \
+ /*192 ~199 */ 6, 6, 6, 6, 6, 6, 6, 6, \
+ /*200 ~203 */ 6, 6, 6, 6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4 */ 0x3F, \
+ /* Group5 */ 0x3F, \
+ /* Group6(0,2) */ 0x3A, \
+ /* Group7(0,1,2,3) */ 0x30, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4(4) */ 0x2F, \
+ /* Group5(5) */ 0x1F, \
+ /* Group6(0,2,4) */ 0x2A, \
+ /* Group7(0,1,2,3,4,5) */ 0x00, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 1, 0, 0, 0, 0, 0, 0, 1, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 1, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 1, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 1, 1, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 1, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~204 */ 0, 0, 0, 0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 204,
+ VPE_STATUS_HISR_TASK_HIGHEST = 256,
+ VPE_STATUS_HISR_TASK_LOWEST = 511,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+ IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+ IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+ IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+ IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+ IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+ IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+ IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+ IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+ IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+ IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+ IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+ IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT3967_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h
new file mode 100644
index 0000000..aa559c4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT3967_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT3967
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+ SW_TRIGGER_CODE14 = Woody Kuo
+ SW_TRIGGER_CODE15 = Carl Kao
+ SW_TRIGGER_CODE16 = Yuni Chang
+ SW_TRIGGER_CODE17 = SY Yeh
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Wade Huang
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Weimin Zeng
+ SW_TRIGGER_CODE26 = Weimin Zeng
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Kevin-KH Liu
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Nicole Hsu
+ SW_TRIGGER_CODE32 =
+ SW_TRIGGER_CODE33 =
+ SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+ */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT3967 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h
new file mode 100644
index 0000000..e1b818c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h
@@ -0,0 +1,664 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6295M.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6295M_H__
+#define __INTRCTRL_MT6295M_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (204)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_MD_BUCK_CTRL_IRQ_CODE MD_IRQID_MD_BUCK_CTRL_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_USB_MCU_CODE MD_IRQID_USB_MCU
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDMCU_DVFS_CTRL_CODE MD_IRQID_MDMCU_DVFS_CTRL
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_IA_DECERR_CODE MD_IRQID_IA_DECERR
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_SPU_INT_CODE MD_IRQID_SPU_INT
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_AP2MD_CONN_CCIF_0_CODE MD_IRQID_AP2MD_CONN_CCIF_0
+#define IRQ_AP2MD_CONN_CCIF_1_CODE MD_IRQID_AP2MD_CONN_CCIF_1
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_CONN2MD_PDMA_IRQ_CODE MD_IRQID_CONN2MD_PDMA_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define IRQ_DUMMY_PRIORITY_CODE_2 MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ_8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ_9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ_10
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~203 */ 0, 0, 0, 0,
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 6, 1, 1, 1, 1, 1, 11, \
+ /* 8 ~ 15 */ 6, 6, 7, 6, 6, 0, 6, 6, \
+ /* 16 ~ 23 */ 6, 7, 6, 6, 6, 6, 6, 6, \
+ /* 24 ~ 31 */ 7, 1, 6, 6, 6, 6, 6, 7, \
+ /* 32 ~ 39 */ 6, 6, 6, 6, 6, 6, 6, 0, \
+ /* 40 ~ 47 */ 3, 1, 1, 10, 10, 3, 6, 0, \
+ /* 48 ~ 55 */ 0, 6, 6, 6, 6, 6, 6, 6, \
+ /* 56 ~ 63 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /* 64 ~ 71 */ 6, 6, 0, 6, 6, 6, 6, 6, \
+ /* 72 ~ 79 */ 6, 7, 6, 6, 1, 6, 6, 6, \
+ /* 80 ~ 87 */ 1, 1, 1, 1, 1, 1, 7, 6, \
+ /* 88 ~ 95 */ 3, 9, 12, 1, 1, 3, 1, 1, \
+ /* 96 ~103 */ 1, 3, 1, 3, 1, 1, 1, 1, \
+ /*104 ~111 */ 3, 1, 1, 1, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 1, 1, 0, 6, 6, 6, 6, \
+ /*120 ~127 */ 6, 6, 6, 1, 1, 3, 6, 6, \
+ /*128 ~135 */ 6, 7, 7, 6, 6, 7, 6, 12, \
+ /*136 ~143 */ 12, 1, 3, 12, 11, 6, 7, 6, \
+ /*144 ~151 */ 6, 1, 6, 6, 6, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 8, 7, 6, 8, 0, 0, \
+ /*168 ~175 */ 2, 4, 7, 0, 2, 4, 1, 1, \
+ /*176 ~183 */ 6, 6, 1, 6, 6, 6, 6, 0, \
+ /*184 ~191 */ 1, 2, 3, 4, 5, 6, 6, 6, \
+ /*192 ~199 */ 6, 6, 6, 6, 6, 6, 6, 6, \
+ /*200 ~203 */ 6, 6, 6, 6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4 */ 0x3F, \
+ /* Group5 */ 0x3F, \
+ /* Group6(0,2) */ 0x3A, \
+ /* Group7(0,1,2,3) */ 0x30, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4(4) */ 0x2F, \
+ /* Group5(5) */ 0x1F, \
+ /* Group6(0,2,4) */ 0x2A, \
+ /* Group7(0,1,2,3,4,5) */ 0x00, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 1, 0, 0, 0, 0, 0, 0, 1, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 1, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 1, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 1, 1, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 1, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~204 */ 0, 0, 0, 0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 204,
+ VPE_STATUS_HISR_TASK_HIGHEST = 256,
+ VPE_STATUS_HISR_TASK_LOWEST = 511,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+ IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+ IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+ IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+ IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+ IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+ IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+ IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+ IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+ IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+ IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+ IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+ IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT6295M_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h
new file mode 100644
index 0000000..cb89e1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6295M_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6295M
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+ SW_TRIGGER_CODE14 = Woody Kuo
+ SW_TRIGGER_CODE15 = Carl Kao
+ SW_TRIGGER_CODE16 = Yuni Chang
+ SW_TRIGGER_CODE17 = SY Yeh
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Wade Huang
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Weimin Zeng
+ SW_TRIGGER_CODE26 = Weimin Zeng
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Kevin-KH Liu
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Nicole Hsu
+ SW_TRIGGER_CODE32 =
+ SW_TRIGGER_CODE33 =
+ SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+ */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6295M for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h
new file mode 100644
index 0000000..b56a7eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h
@@ -0,0 +1,666 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6779.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6779_H__
+#define __INTRCTRL_MT6779_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES (204)
+
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_MDGDMA0_CODE MD_IRQID_MDGDMA0
+#define IRQ_MDGDMA1_CODE MD_IRQID_MDGDMA1
+#define IRQ_MDGDMA2_CODE MD_IRQID_MDGDMA2
+#define IRQ_MDGDMA3_CODE MD_IRQID_MDGDMA3
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_BUS_ERR_CODE MD_IRQID_BUS_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_MML2_HRT_CODE MD_IRQ_ID_MML2_HRT
+#define IRQ_MML2_NOTIF_CODE MD_IRQ_ID_MML2_NOTIF
+#define IRQ_MML2_EXCEP_CODE MD_IRQ_ID_MML2_EXCEP
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_CLDMA_CODE MD_IRQID_CLDMA
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ULSP_LOG_MD_INT_CODE MD_IRQID_ULSP_LOG_MD_INT
+#define IRQ_ULSP_LOG_DSP_INT_CODE MD_IRQID_ULSP_LOG_DSP_INT
+#define IRQ_USIP0_0_CODE MD_IRQID_USIP0_0
+#define IRQ_USIP1_0_CODE MD_IRQID_USIP1_0
+#define IRQ_USIP2_0_CODE MD_IRQID_USIP2_0
+#define IRQ_USIP3_0_CODE MD_IRQID_USIP3_0
+#define IRQ_USIP0_1_CODE MD_IRQID_USIP0_1
+#define IRQ_USIP1_1_CODE MD_IRQID_USIP1_1
+#define IRQ_USIP2_1_CODE MD_IRQID_USIP2_1
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_MD_BUCK_CTRL_IRQ_CODE MD_IRQID_MD_BUCK_CTRL_IRQ
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SSUSB_DEV_CODE MD_IRQID_SSUSB_DEV
+#define IRQ_USB_MCU_CODE MD_IRQID_USB_MCU
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_RXDFE_RXK_READBACK_CODE MD_IRQID_RXDFE_RXK_READBACK
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_BIGRAM_IRQ_CODE MD_IRQID_BIGRAM_IRQ
+#define IRQ_BR_BDGE_IRQ_CODE MD_IRQID_BR_BDGE_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_MDMCU_DVFS_CTRL_CODE MD_IRQID_MDMCU_DVFS_CTRL
+#define IRQ_PCC_TOP_FULL_IRQ_CODE MD_IRQID_PCC_TOP_FULL_IRQ
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_MCU_BUS_DECERR_CODE MD_IRQID_MCU_BUS_DECERR
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_IA_DECERR_CODE MD_IRQID_IA_DECERR
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_SPU_INT_CODE MD_IRQID_SPU_INT
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MDDFE_DUMP_CODE MD_IRQID_MDDFE_DUMP
+#define IRQ_AP2MD_CONN_CCIF_0_CODE MD_IRQID_AP2MD_CONN_CCIF_0
+#define IRQ_AP2MD_CONN_CCIF_1_CODE MD_IRQID_AP2MD_CONN_CCIF_1
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_CONN2MD_PDMA_IRQ_CODE MD_IRQID_CONN2MD_PDMA_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_DUMMY_PRIORITY_CODE_0 MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define IRQ_DUMMY_PRIORITY_CODE_1 MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define IRQ_DUMMY_PRIORITY_CODE_2 MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define IRQ_DUMMY_PRIORITY_CODE_7 MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ_8
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 0, 1, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 1, 2, 3, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~203 */ 0, 0, 0, 0,
+#else /* __ESL_MASE__*/
+#define INTERRUPT_GROUP_LIST \
+ /* 0 ~ 7 */ 1, 6, 1, 1, 1, 1, 1, 11, \
+ /* 8 ~ 15 */ 6, 6, 7, 6, 6, 0, 6, 6, \
+ /* 16 ~ 23 */ 6, 7, 6, 6, 6, 6, 6, 6, \
+ /* 24 ~ 31 */ 7, 1, 6, 6, 6, 6, 6, 7, \
+ /* 32 ~ 39 */ 6, 6, 6, 6, 6, 6, 6, 0, \
+ /* 40 ~ 47 */ 3, 1, 1, 10, 10, 3, 6, 0, \
+ /* 48 ~ 55 */ 0, 6, 6, 6, 6, 6, 6, 6, \
+ /* 56 ~ 63 */ 0, 1, 2, 3, 4, 5, 6, 6, \
+ /* 64 ~ 71 */ 6, 6, 0, 6, 6, 6, 6, 6, \
+ /* 72 ~ 79 */ 6, 7, 6, 6, 1, 6, 6, 6, \
+ /* 80 ~ 87 */ 1, 1, 1, 1, 1, 1, 7, 6, \
+ /* 88 ~ 95 */ 3, 9, 12, 1, 1, 3, 1, 1, \
+ /* 96 ~103 */ 1, 3, 1, 3, 1, 1, 1, 1, \
+ /*104 ~111 */ 3, 1, 1, 1, 1, 1, 1, 1, \
+ /*112 ~119 */ 1, 1, 1, 0, 6, 6, 6, 6, \
+ /*120 ~127 */ 6, 6, 6, 1, 1, 7, 6, 6, \
+ /*128 ~135 */ 6, 7, 7, 6, 6, 7, 6, 12, \
+ /*136 ~143 */ 12, 1, 3, 12, 11, 6, 7, 6, \
+ /*144 ~151 */ 6, 1, 6, 6, 6, 1, 1, 1, \
+ /*152 ~159 */ 3, 1, 3, 1, 1, 1, 1, 1, \
+ /*160 ~167 */ 1, 1, 8, 7, 6, 8, 0, 0, \
+ /*168 ~175 */ 2, 4, 7, 0, 2, 4, 1, 1, \
+ /*176 ~183 */ 6, 6, 1, 6, 6, 6, 6, 0, \
+ /*184 ~191 */ 1, 2, 3, 4, 5, 6, 6, 6, \
+ /*192 ~199 */ 6, 6, 6, 6, 6, 6, 6, 6, \
+ /*200 ~203 */ 6, 6, 6, 6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+ 0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4 */ 0x3F, \
+ /* Group5 */ 0x3F, \
+ /* Group6(0,2) */ 0x3A, \
+ /* Group7(0,1,2,3) */ 0x30, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0x3E, \
+ /* Group1(1) */ 0x3D, \
+ /* Group2(2) */ 0x3B, \
+ /* Group3(3) */ 0x37, \
+ /* Group4(4) */ 0x2F, \
+ /* Group5(5) */ 0x1F, \
+ /* Group6(0,2,4) */ 0x2A, \
+ /* Group7(0,1,2,3,4,5) */ 0x00, \
+ /* Group8(1,3) */ 0x35, \
+ /* Group9(0,1,2,3) */ 0x30, \
+ /* Group10(2,3) */ 0x33, \
+ /* Group11(0,2) */ 0x3A, \
+ /* Group12(0,2,3) */ 0x32, \
+ /* Group13 */ 0x3F, \
+ /* Group14 */ 0x3F, \
+ /* Group15 */ 0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+ /* 0 ~ 7 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 8 ~ 15 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /* 16 ~ 23 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 24 ~ 31 */ 1, 0, 0, 0, 0, 0, 0, 1, \
+ /* 32 ~ 39 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 40 ~ 47 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 48 ~ 55 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 56 ~ 63 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 64 ~ 71 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 72 ~ 79 */ 0, 1, 0, 0, 0, 0, 0, 0, \
+ /* 80 ~ 87 */ 0, 0, 0, 0, 0, 0, 1, 0, \
+ /* 88 ~ 95 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /* 96 ~103 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*104 ~111 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*112 ~119 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*120 ~127 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*128 ~135 */ 0, 1, 1, 0, 0, 0, 0, 0, \
+ /*136 ~143 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*144 ~151 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*152 ~159 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*160 ~167 */ 0, 0, 1, 1, 0, 0, 0, 0, \
+ /*168 ~175 */ 0, 0, 1, 0, 0, 0, 0, 0, \
+ /*176 ~183 */ 1, 0, 0, 1, 0, 0, 0, 0, \
+ /*184 ~191 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*192 ~199 */ 0, 0, 0, 0, 0, 0, 0, 0, \
+ /*200 ~204 */ 0, 0, 0, 0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 204,
+ VPE_STATUS_HISR_TASK_HIGHEST = 256,
+ VPE_STATUS_HISR_TASK_LOWEST = 511,
+ VPE_STATUS_END = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+ IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+ IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+ IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+ IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+ IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+ IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+ IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+ IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+ IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+ IRQ_MDWDT = IRQ_MDWDT_CODE,
+ IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+ IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+ IRQ_OST = IRQ_OST_CODE,
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+ IRQ_USIM1 = IRQ_USIM1_CODE,
+ IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+ IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+ IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+ IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+ IRQ_EINT0 = IRQ_EINT0_CODE,
+ IRQ_EINT1 = IRQ_EINT1_CODE,
+ IRQ_EINT2 = IRQ_EINT2_CODE,
+ IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+ IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+ IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+ IRQ_TXCRP = IRQ_TXCRP_CODE,
+ IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+ IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+ IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+ IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+ IRQ_ECT = IRQ_ECT_CODE,
+ IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+ IRQ_CLDMA = IRQ_CLDMA_CODE,
+ IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+ IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+ IRQ_SOE = IRQ_SOE_CODE,
+ IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+ IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+ IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+ IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+ IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+ IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+ IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+ IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+ IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+ IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+ IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+ IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+ IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+ IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+ IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+ IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+ IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+ IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+ IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+ IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+ IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+ IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+ IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+ IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+ IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+ IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+ IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+ IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+ IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+ IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+ IRQ_EINT3 = IRQ_EINT3_CODE,
+ IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+ IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+ IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+ IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+ IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+ IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+ IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+ IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+ IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+ IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+ IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+ IRQ_MDRTT = IRQ_MDRTT_CODE,
+ IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+ IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+ IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+ IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+ IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+ IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+ IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+ IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+ IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+ IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+ IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+ IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+ IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+ IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+ IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+ IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+ IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+ IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+ IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+ IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+ IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+ IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+ IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+ IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+ IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+ IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+ IRQ_GPTM1 = IRQ_GPTM1_CODE,
+ IRQ_GPTM2 = IRQ_GPTM2_CODE,
+ IRQ_GPTM3 = IRQ_GPTM3_CODE,
+ IRQ_GPTM4 = IRQ_GPTM4_CODE,
+ IRQ_GPTM5 = IRQ_GPTM5_CODE,
+ IRQ_GPTM6 = IRQ_GPTM6_CODE,
+ IRQ_GPTM7 = IRQ_GPTM7_CODE,
+ IRQ_GPTM8 = IRQ_GPTM8_CODE,
+ IRQ_GPTM9 = IRQ_GPTM9_CODE,
+ IRQ_GPTM10 = IRQ_GPTM10_CODE,
+ IRQ_GPTM11 = IRQ_GPTM11_CODE,
+ IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+ IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+ IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+ IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+ IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+ IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+ IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+ IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+ IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+ IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+ IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+ IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+ IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+ IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+ IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+ IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+ IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+ IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+ IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+ IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+ IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+ IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+ IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+ IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+ IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+ IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+ IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+ IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+ IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+ IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+ IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+ IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+ IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+ IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+ IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+ IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+ IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+ IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+ IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+ IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+ IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+ IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+ IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+ IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+ IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+ IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+ IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+ IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+ IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+ IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+ IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+ IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+ IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+ IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+ IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+ IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+ IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+ IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+ IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+ IRQ_CONN_BT_ISOCH = IRQ_CONN_BT_ISOCH_CODE,
+ IRQ_AP2MD_UFS = IRQ_AP2MD_UFS_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+ GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT6779_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h
new file mode 100644
index 0000000..7c5ac1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MT6779_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MT6779
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+ SW_TRIGGER_CODE14 = Woody Kuo
+ SW_TRIGGER_CODE15 = Carl Kao
+ SW_TRIGGER_CODE16 = Yuni Chang
+ SW_TRIGGER_CODE17 = SY Yeh
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Wade Huang
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Weimin Zeng
+ SW_TRIGGER_CODE26 = Weimin Zeng
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Kevin-KH Liu
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Nicole Hsu
+ SW_TRIGGER_CODE32 =
+ SW_TRIGGER_CODE33 =
+ SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+ SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+ */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6779 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..ac6c23a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h
@@ -0,0 +1,92 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6295M)
+ #include "intrCtrl_MT6295M_SW_Handle.h"
+#endif
+
+#if defined(MT3967)
+ #include "intrCtrl_MT3967_SW_Handle.h"
+#endif
+
+#if defined(MT6779)
+ #include "intrCtrl_MT6779_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h
new file mode 100644
index 0000000..f932ab5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h
@@ -0,0 +1,11 @@
+#if defined(MT6295M)
+ #include "irqPriority_MT6295M.h"
+#endif
+
+#if defined(MT3967)
+ #include "irqPriority_MT3967.h"
+#endif
+
+#if defined(MT6779)
+ #include "irqPriority_MT6779.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h
new file mode 100644
index 0000000..050f9d2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h
new file mode 100644
index 0000000..1361e38
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h
new file mode 100644
index 0000000..af6548f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid.h b/mcu/interface/driver/devdrv/cirq/md95/irqid.h
new file mode 100644
index 0000000..eb8c5e1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid.h
@@ -0,0 +1,16 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6295M)
+ #include "irqid_MT6295M.h"
+#endif
+
+#if defined(MT3967)
+ #include "irqid_MT3967.h"
+#endif
+
+#if defined(MT6779)
+ #include "irqid_MT6779.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h
new file mode 100644
index 0000000..fa92526
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h
@@ -0,0 +1,222 @@
+#ifndef __MT3967_IRQID_H__
+#define __MT3967_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_MDGDMA0 16
+#define MD_IRQID_MDGDMA1 17
+#define MD_IRQID_MDGDMA2 18
+#define MD_IRQID_MDGDMA3 19
+#define MD_IRQID_EINT0 20
+#define MD_IRQID_EINT1 21
+#define MD_IRQID_EINT2 22
+#define MD_IRQID_EINT_SHARE 23
+#define MD_IRQID_BUS_ERR 24
+#define MD_IRQID_TXBSRP 25
+#define MD_IRQID_TXCRP 26
+#define MD_IRQ_ID_MML2_HRT 27
+#define MD_IRQ_ID_MML2_NOTIF 28
+#define MD_IRQ_ID_MML2_EXCEP 29
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 30
+#define MD_IRQID_ECT 31
+#define MD_IRQID_PTP_THERM_INT_INT 32
+#define MD_IRQID_CLDMA 33
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 34
+#define MD_IRQID_ELM_DMA_IRQ 35
+#define MD_IRQID_SOE 36
+#define MD_IRQID_ULSP_LOG_MD_INT 37
+#define MD_IRQID_ULSP_LOG_DSP_INT 38
+#define MD_IRQID_USIP0_0 39
+#define MD_IRQID_USIP1_0 40
+#define MD_IRQID_USIP2_0 41
+#define MD_IRQID_USIP3_0 42
+#define MD_IRQID_USIP0_1 43
+#define MD_IRQID_USIP1_1 44
+#define MD_IRQID_USIP2_1 45
+#define MD_IRQID_SI_CM_ERR 46
+#define MD_IRQID_ABM_INT 47
+#define MD_IRQID_ABM_ERROR_INT 48
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 49
+#define MD_IRQID_ELMTOP_EMI_IRQ 50
+#define MD_IRQID_PPPHA_ENC0_INT 51
+#define MD_IRQID_PPPHA_ENC1_INT 52
+#define MD_IRQID_PPPHA_DEC0_INT 53
+#define MD_IRQID_PPPHA_DEC1_INT 54
+#define MD_IRQID_PTP_FSM_INT 55
+#define MD_IRQID_IEBIT_CHECK_IRQ0 56
+#define MD_IRQID_IEBIT_CHECK_IRQ1 57
+#define MD_IRQID_IEBIT_CHECK_IRQ2 58
+#define MD_IRQID_IEBIT_CHECK_IRQ3 59
+#define MD_IRQID_IEBIT_CHECK_IRQ4 60
+#define MD_IRQID_IEBIT_CHECK_IRQ5 61
+#define MD_IRQID_TRACE_INT 62
+#define MD_IRQID_SI_CM_PCINT 63
+#define MD_IRQID_PLL_GEARHP_RDY 64
+#define MD_IRQID_MD_BUCK_CTRL_IRQ 65
+#define MD_IRQID_REQ_ABNORM_IRQ 66
+#define MD_IRQID_EINT3 67
+#define MD_IRQID_BT_CVSD 68
+#define MD_IRQID_SSUSB_DEV 69
+#define MD_IRQID_USB_MCU 70
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 71
+#define MD_IRQID_AP2MD_CCIF0_0 72
+#define MD_IRQID_AP2MD_CCIF0_1 73
+#define MD_IRQID_AP2MD_CCIF1_0 74
+#define MD_IRQID_AP2MD_CCIF1_1 75
+#define MD_IRQID_RXDFE_RXK_READBACK 76
+#define MD_IRQID_IDC_PM_INT 77
+#define MD_IRQID_IDC_UART_IRQ 78
+#define MD_IRQID_MDRTT 79
+#define MD_IRQID_MDEVDO 80
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 81
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 82
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 83
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 84
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 85
+#define MD_IRQID_BIGRAM_IRQ 86
+#define MD_IRQID_BR_BDGE_IRQ 87
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 88
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 89
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 90
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 91
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 92
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 93
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 94
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 95
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 96
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 98
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 99
+#define MD_IRQID_TDD_WAKEUP_IRQ 100
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 101
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 102
+#define MD_IRQID_RTR_SLT_0_IRQ 103
+#define MD_IRQID_RTR_SLT_1_IRQ 104
+#define MD_IRQID_FDD_SLP_IRQ 105
+#define MD_IRQID_TDMA_WAKEUP_IRQ 106
+#define MD_IRQID_ST1X_CPINT 107
+#define MD_IRQID_ST1x_HALF_CPINT 108
+#define MD_IRQID_ST1x_CFG_CPINT 109
+#define MD_IRQID_ST1x_WAKEUP_IRQ 110
+#define MD_IRQID_STDO_CPINT 111
+#define MD_IRQID_STDO_HALF_CPINT 112
+#define MD_IRQID_STDO_CFG_CPINT 113
+#define MD_IRQID_STDO_WAKEUP_IRQ 114
+#define MD_IRQID_FREQM_IRQ 115
+#define MD_IRQID_MDMCU_DVFS_CTRL 116
+#define MD_IRQID_PCC_TOP_FULL_IRQ 117
+#define MD_IRQID_GPTM1 118
+#define MD_IRQID_GPTM2 119
+#define MD_IRQID_GPTM3 120
+#define MD_IRQID_GPTM4 121
+#define MD_IRQID_GPTM5 122
+#define MD_IRQID_GPTM6 123
+#define MD_IRQID_GPTM7 124
+#define MD_IRQID_GPTM8 125
+#define MD_IRQID_GPTM9 126
+#define MD_IRQID_GPTM10 127
+#define MD_IRQID_GPTM11 128
+#define MD_IRQID_BUSMPU_IRQ 129
+#define MD_IRQID_MCU_BUS_DECERR 130
+#define MD_IRQID_MCUMMU_INT 131
+#define MD_IRQID_IA_DECERR 132
+#define MD_IRQID_RMPU_CTIREIGIN 133
+#define MD_IRQID_AP2MD_MSDC0 134
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 135
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 136
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 137
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 138
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 139
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 140
+#define MD_IRQID_AP2MD_CCIF2 141
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 142
+#define MD_IRQID_SPU_INT 143
+#define MD_IRQID_SDF_OVERFLOW_IRQ 144
+#define MD_IRQID_MDDFE_DUMP 145
+#define MD_IRQID_AP2MD_CONN_CCIF_0 146
+#define MD_IRQID_AP2MD_CONN_CCIF_1 147
+#define MD_IRQID_I2C_TOP_INT 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 191
+#define MD_IRQID_CONN2MD_PDMA_IRQ 192
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0 193
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1 194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2 195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3 196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4 197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5 198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6 199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7 200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8 201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_9 202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_10 203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT3967_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h
new file mode 100644
index 0000000..241e08c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h
@@ -0,0 +1,222 @@
+#ifndef __MT6295M_IRQID_H__
+#define __MT6295M_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_MDGDMA0 16
+#define MD_IRQID_MDGDMA1 17
+#define MD_IRQID_MDGDMA2 18
+#define MD_IRQID_MDGDMA3 19
+#define MD_IRQID_EINT0 20
+#define MD_IRQID_EINT1 21
+#define MD_IRQID_EINT2 22
+#define MD_IRQID_EINT_SHARE 23
+#define MD_IRQID_BUS_ERR 24
+#define MD_IRQID_TXBSRP 25
+#define MD_IRQID_TXCRP 26
+#define MD_IRQ_ID_MML2_HRT 27
+#define MD_IRQ_ID_MML2_NOTIF 28
+#define MD_IRQ_ID_MML2_EXCEP 29
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 30
+#define MD_IRQID_ECT 31
+#define MD_IRQID_PTP_THERM_INT_INT 32
+#define MD_IRQID_CLDMA 33
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 34
+#define MD_IRQID_ELM_DMA_IRQ 35
+#define MD_IRQID_SOE 36
+#define MD_IRQID_ULSP_LOG_MD_INT 37
+#define MD_IRQID_ULSP_LOG_DSP_INT 38
+#define MD_IRQID_USIP0_0 39
+#define MD_IRQID_USIP1_0 40
+#define MD_IRQID_USIP2_0 41
+#define MD_IRQID_USIP3_0 42
+#define MD_IRQID_USIP0_1 43
+#define MD_IRQID_USIP1_1 44
+#define MD_IRQID_USIP2_1 45
+#define MD_IRQID_SI_CM_ERR 46
+#define MD_IRQID_ABM_INT 47
+#define MD_IRQID_ABM_ERROR_INT 48
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 49
+#define MD_IRQID_ELMTOP_EMI_IRQ 50
+#define MD_IRQID_PPPHA_ENC0_INT 51
+#define MD_IRQID_PPPHA_ENC1_INT 52
+#define MD_IRQID_PPPHA_DEC0_INT 53
+#define MD_IRQID_PPPHA_DEC1_INT 54
+#define MD_IRQID_PTP_FSM_INT 55
+#define MD_IRQID_IEBIT_CHECK_IRQ0 56
+#define MD_IRQID_IEBIT_CHECK_IRQ1 57
+#define MD_IRQID_IEBIT_CHECK_IRQ2 58
+#define MD_IRQID_IEBIT_CHECK_IRQ3 59
+#define MD_IRQID_IEBIT_CHECK_IRQ4 60
+#define MD_IRQID_IEBIT_CHECK_IRQ5 61
+#define MD_IRQID_TRACE_INT 62
+#define MD_IRQID_SI_CM_PCINT 63
+#define MD_IRQID_PLL_GEARHP_RDY 64
+#define MD_IRQID_MD_BUCK_CTRL_IRQ 65
+#define MD_IRQID_REQ_ABNORM_IRQ 66
+#define MD_IRQID_EINT3 67
+#define MD_IRQID_BT_CVSD 68
+#define MD_IRQID_SSUSB_DEV 69
+#define MD_IRQID_USB_MCU 70
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 71
+#define MD_IRQID_AP2MD_CCIF0_0 72
+#define MD_IRQID_AP2MD_CCIF0_1 73
+#define MD_IRQID_AP2MD_CCIF1_0 74
+#define MD_IRQID_AP2MD_CCIF1_1 75
+#define MD_IRQID_RXDFE_RXK_READBACK 76
+#define MD_IRQID_IDC_PM_INT 77
+#define MD_IRQID_IDC_UART_IRQ 78
+#define MD_IRQID_MDRTT 79
+#define MD_IRQID_MDEVDO 80
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 81
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 82
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 83
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 84
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 85
+#define MD_IRQID_BIGRAM_IRQ 86
+#define MD_IRQID_BR_BDGE_IRQ 87
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 88
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 89
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 90
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 91
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 92
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 93
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 94
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 95
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 96
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 98
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 99
+#define MD_IRQID_TDD_WAKEUP_IRQ 100
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 101
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 102
+#define MD_IRQID_RTR_SLT_0_IRQ 103
+#define MD_IRQID_RTR_SLT_1_IRQ 104
+#define MD_IRQID_FDD_SLP_IRQ 105
+#define MD_IRQID_TDMA_WAKEUP_IRQ 106
+#define MD_IRQID_ST1X_CPINT 107
+#define MD_IRQID_ST1x_HALF_CPINT 108
+#define MD_IRQID_ST1x_CFG_CPINT 109
+#define MD_IRQID_ST1x_WAKEUP_IRQ 110
+#define MD_IRQID_STDO_CPINT 111
+#define MD_IRQID_STDO_HALF_CPINT 112
+#define MD_IRQID_STDO_CFG_CPINT 113
+#define MD_IRQID_STDO_WAKEUP_IRQ 114
+#define MD_IRQID_FREQM_IRQ 115
+#define MD_IRQID_MDMCU_DVFS_CTRL 116
+#define MD_IRQID_PCC_TOP_FULL_IRQ 117
+#define MD_IRQID_GPTM1 118
+#define MD_IRQID_GPTM2 119
+#define MD_IRQID_GPTM3 120
+#define MD_IRQID_GPTM4 121
+#define MD_IRQID_GPTM5 122
+#define MD_IRQID_GPTM6 123
+#define MD_IRQID_GPTM7 124
+#define MD_IRQID_GPTM8 125
+#define MD_IRQID_GPTM9 126
+#define MD_IRQID_GPTM10 127
+#define MD_IRQID_GPTM11 128
+#define MD_IRQID_BUSMPU_IRQ 129
+#define MD_IRQID_MCU_BUS_DECERR 130
+#define MD_IRQID_MCUMMU_INT 131
+#define MD_IRQID_IA_DECERR 132
+#define MD_IRQID_RMPU_CTIREIGIN 133
+#define MD_IRQID_AP2MD_MSDC0 134
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 135
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 136
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 137
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 138
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 139
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 140
+#define MD_IRQID_AP2MD_CCIF2 141
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 142
+#define MD_IRQID_SPU_INT 143
+#define MD_IRQID_SDF_OVERFLOW_IRQ 144
+#define MD_IRQID_MDDFE_DUMP 145
+#define MD_IRQID_AP2MD_CONN_CCIF_0 146
+#define MD_IRQID_AP2MD_CONN_CCIF_1 147
+#define MD_IRQID_I2C_TOP_INT 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 191
+#define MD_IRQID_CONN2MD_PDMA_IRQ 192
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0 193
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1 194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2 195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3 196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4 197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5 198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6 199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7 200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8 201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_9 202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_10 203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6295M_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h
new file mode 100644
index 0000000..db4fba9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h
@@ -0,0 +1,222 @@
+#ifndef __MT6779_IRQID_H__
+#define __MT6779_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1 0
+#define MD_IRQID_IRDBG_MCU_INT 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 7
+#define MD_IRQID_CSSYS_1X_CS_IRQ 8
+#define MD_IRQID_CSSYS_DO_CS_IRQ 9
+#define MD_IRQID_MDWDT 10
+#define MD_IRQID_UART_MD0 11
+#define MD_IRQID_UART_MD1 12
+#define MD_IRQID_OST 13
+#define MD_IRQID_USIM0 14
+#define MD_IRQID_USIM1 15
+#define MD_IRQID_MDGDMA0 16
+#define MD_IRQID_MDGDMA1 17
+#define MD_IRQID_MDGDMA2 18
+#define MD_IRQID_MDGDMA3 19
+#define MD_IRQID_EINT0 20
+#define MD_IRQID_EINT1 21
+#define MD_IRQID_EINT2 22
+#define MD_IRQID_EINT_SHARE 23
+#define MD_IRQID_BUS_ERR 24
+#define MD_IRQID_TXBSRP 25
+#define MD_IRQID_TXCRP 26
+#define MD_IRQ_ID_MML2_HRT 27
+#define MD_IRQ_ID_MML2_NOTIF 28
+#define MD_IRQ_ID_MML2_EXCEP 29
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 30
+#define MD_IRQID_ECT 31
+#define MD_IRQID_PTP_THERM_INT_INT 32
+#define MD_IRQID_CLDMA 33
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 34
+#define MD_IRQID_ELM_DMA_IRQ 35
+#define MD_IRQID_SOE 36
+#define MD_IRQID_ULSP_LOG_MD_INT 37
+#define MD_IRQID_ULSP_LOG_DSP_INT 38
+#define MD_IRQID_USIP0_0 39
+#define MD_IRQID_USIP1_0 40
+#define MD_IRQID_USIP2_0 41
+#define MD_IRQID_USIP3_0 42
+#define MD_IRQID_USIP0_1 43
+#define MD_IRQID_USIP1_1 44
+#define MD_IRQID_USIP2_1 45
+#define MD_IRQID_SI_CM_ERR 46
+#define MD_IRQID_ABM_INT 47
+#define MD_IRQID_ABM_ERROR_INT 48
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 49
+#define MD_IRQID_ELMTOP_EMI_IRQ 50
+#define MD_IRQID_PPPHA_ENC0_INT 51
+#define MD_IRQID_PPPHA_ENC1_INT 52
+#define MD_IRQID_PPPHA_DEC0_INT 53
+#define MD_IRQID_PPPHA_DEC1_INT 54
+#define MD_IRQID_PTP_FSM_INT 55
+#define MD_IRQID_IEBIT_CHECK_IRQ0 56
+#define MD_IRQID_IEBIT_CHECK_IRQ1 57
+#define MD_IRQID_IEBIT_CHECK_IRQ2 58
+#define MD_IRQID_IEBIT_CHECK_IRQ3 59
+#define MD_IRQID_IEBIT_CHECK_IRQ4 60
+#define MD_IRQID_IEBIT_CHECK_IRQ5 61
+#define MD_IRQID_TRACE_INT 62
+#define MD_IRQID_SI_CM_PCINT 63
+#define MD_IRQID_PLL_GEARHP_RDY 64
+#define MD_IRQID_MD_BUCK_CTRL_IRQ 65
+#define MD_IRQID_REQ_ABNORM_IRQ 66
+#define MD_IRQID_EINT3 67
+#define MD_IRQID_BT_CVSD 68
+#define MD_IRQID_SSUSB_DEV 69
+#define MD_IRQID_USB_MCU 70
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM 71
+#define MD_IRQID_AP2MD_CCIF0_0 72
+#define MD_IRQID_AP2MD_CCIF0_1 73
+#define MD_IRQID_AP2MD_CCIF1_0 74
+#define MD_IRQID_AP2MD_CCIF1_1 75
+#define MD_IRQID_RXDFE_RXK_READBACK 76
+#define MD_IRQID_IDC_PM_INT 77
+#define MD_IRQID_IDC_UART_IRQ 78
+#define MD_IRQID_MDRTT 79
+#define MD_IRQID_MDEVDO 80
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 81
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 82
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 83
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 84
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 85
+#define MD_IRQID_BIGRAM_IRQ 86
+#define MD_IRQID_BR_BDGE_IRQ 87
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 88
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 89
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 90
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 91
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 92
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 93
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 94
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 95
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 96
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 98
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 99
+#define MD_IRQID_TDD_WAKEUP_IRQ 100
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 101
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 102
+#define MD_IRQID_RTR_SLT_0_IRQ 103
+#define MD_IRQID_RTR_SLT_1_IRQ 104
+#define MD_IRQID_FDD_SLP_IRQ 105
+#define MD_IRQID_TDMA_WAKEUP_IRQ 106
+#define MD_IRQID_ST1X_CPINT 107
+#define MD_IRQID_ST1x_HALF_CPINT 108
+#define MD_IRQID_ST1x_CFG_CPINT 109
+#define MD_IRQID_ST1x_WAKEUP_IRQ 110
+#define MD_IRQID_STDO_CPINT 111
+#define MD_IRQID_STDO_HALF_CPINT 112
+#define MD_IRQID_STDO_CFG_CPINT 113
+#define MD_IRQID_STDO_WAKEUP_IRQ 114
+#define MD_IRQID_FREQM_IRQ 115
+#define MD_IRQID_MDMCU_DVFS_CTRL 116
+#define MD_IRQID_PCC_TOP_FULL_IRQ 117
+#define MD_IRQID_GPTM1 118
+#define MD_IRQID_GPTM2 119
+#define MD_IRQID_GPTM3 120
+#define MD_IRQID_GPTM4 121
+#define MD_IRQID_GPTM5 122
+#define MD_IRQID_GPTM6 123
+#define MD_IRQID_GPTM7 124
+#define MD_IRQID_GPTM8 125
+#define MD_IRQID_GPTM9 126
+#define MD_IRQID_GPTM10 127
+#define MD_IRQID_GPTM11 128
+#define MD_IRQID_BUSMPU_IRQ 129
+#define MD_IRQID_MCU_BUS_DECERR 130
+#define MD_IRQID_MCUMMU_INT 131
+#define MD_IRQID_IA_DECERR 132
+#define MD_IRQID_RMPU_CTIREIGIN 133
+#define MD_IRQID_AP2MD_MSDC0 134
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 135
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 136
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 137
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 138
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 139
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 140
+#define MD_IRQID_AP2MD_CCIF2 141
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 142
+#define MD_IRQID_SPU_INT 143
+#define MD_IRQID_SDF_OVERFLOW_IRQ 144
+#define MD_IRQID_MDDFE_DUMP 145
+#define MD_IRQID_AP2MD_CONN_CCIF_0 146
+#define MD_IRQID_AP2MD_CONN_CCIF_1 147
+#define MD_IRQID_I2C_TOP_INT 148
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 191
+#define MD_IRQID_CONN2MD_PDMA_IRQ 192
+#define MD_IRQID_CONN_BT_ISOCH 193
+#define MD_IRQID_AP2MD_UFS 194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0 195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1 196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2 197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3 198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4 199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5 200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6 201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7 202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8 203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6779_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/isrentry.h b/mcu/interface/driver/devdrv/cirq/md95/isrentry.h
new file mode 100644
index 0000000..7fa5cf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/isrentry.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * isrentry.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct
+{
+ kal_uint32 vector;
+ void (*lisr_handler) (kal_uint32);
+ kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+