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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h
new file mode 100644
index 0000000..9228b1b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h
@@ -0,0 +1,294 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MERCURY)
+#include "intrCtrl_MERCURY.h"
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define EDGE_SENSITIVE KAL_TRUE
+#define LEVEL_SENSITIVE KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+ kal_uint32 irq_mask[12];
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+ Need to modify 3 files
+ 1. add a file intrCtrl_MTxxxx_SW_Handler.h
+ 2. add an entry on intrCtrl_SW_Handler.h
+ 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+ SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Activate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern const kal_uint16 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a) (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint16);
+extern void MDCIRQ_IRQMask(kal_uint16);
+extern void MDCIRQ_IRQUnmask(kal_uint16);
+extern void MDCIRQ_IRQSensitivity(kal_uint16, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint16 code);
+extern kal_uint32 IRQ_Status(void);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+ MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint16 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+#define NRIRQ_Affinity_Change_NSA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA()
+#define NRIRQ_Affinity_Change_SA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA()
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA();
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA();
+
+#define LTEIRQ_Affinity_Change_ENDC() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC()
+#define LTEIRQ_Affinity_Change_LTEONLY() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY()
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC();
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY();
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+ IRQ_PRIORITY_END,
+ IRQ_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+ IRQ_EQUALLY_DISPATCH_PRIORITY_THRESHOLD = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE_PRIORITY,
+} IRQ_PRIORITY;
+
+typedef enum {
+ MDCIRQ_To_BUS_Normal = 0x0,
+ MDCIRQ_To_BUS_PreUltra = 0x1,
+ MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR() (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+#define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && (defined(__MIPS_IA__) || defined(__MIPS_I7200__))
+#if defined(__NESTED_DI_CHECK__) && !defined (__ESL_MASE_GEN97__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ kal_uint32 vpe_num = 0;\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+ vpe_num = miu_get_current_vpe_id();\
+ sst_dhl_irq_count[vpe_num]++;\
+ sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+ DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+ miu_mt_dmt();\
+ __asm__ __volatile__\
+ (\
+ "di %0\n\t"\
+ "ehb\n\t"\
+ :"=&r"(oldmask), "=&r"(newmask)\
+ :\
+ :"$31","memory"\
+ );\
+ oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+ kal_uint32 tmp=1;\
+ __asm__ __volatile__\
+ (\
+ "bne %0, %1, END\n\t"\
+ "ei\n\t"\
+ "ehb\n\t"\
+ "END:emt\n\t"\
+ "ehb\n\t"\
+ :\
+ :"r"(oldmask), "r"(tmp)\
+ :"memory"\
+ );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+ oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+ kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h
new file mode 100644
index 0000000..9ab9a29
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h
@@ -0,0 +1,561 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MERCURY.h
+ *
+ * Project:
+ * --------
+ * MERCURY
+ *
+ * Description:
+ * ------------
+ * Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MERCURY_H__
+#define __INTRCTRL_MERCURY_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES (368)
+
+/* CIRQ Interrupt Sources */
+#define IRQ_USIM0_CODE MD_IRQID_USIM0
+#define IRQ_USIM1_CODE MD_IRQID_USIM1
+#define IRQ_TDMA_CTIRQ1_CODE MD_IRQID_TDMA_CTIRQ1
+#define IRQ_TDMA_CTIRQ2_CODE MD_IRQID_TDMA_CTIRQ2
+#define IRQ_TDMA_CTIRQ3_CODE MD_IRQID_TDMA_CTIRQ3
+#define IRQ_TDMA_WAKEUP_IRQ_CODE MD_IRQID_TDMA_WAKEUP_IRQ
+#define IRQ_OST_CODE MD_IRQID_OST
+#define IRQ_MDRTT_CODE MD_IRQID_MDRTT
+#define IRQ_MDEVDO_CODE MD_IRQID_MDEVDO
+#define IRQ_ULSP_LOG_MCU_RT_INT_CODE MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define IRQ_ULSP_LOG_MCU_OD_INT_CODE MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define IRQ_ULSP_LOG_DSP4G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define IRQ_ULSP_LOG_DSP4G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define IRQ_ULSP_LOG_DSP5G_RT_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define IRQ_ULSP_LOG_DSP5G_OD_INT_CODE MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define IRQ_SHARE_D12MINT1_CODE MD_IRQID_SHARE_D12MINT1
+#define IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define IRQ_AIRQ_SERDES_CODE MD_IRQID_AIRQ_SERDES
+#define IRQ_AIRQ_COS_CODE MD_IRQID_AIRQ_COS
+#define IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define IRQ_PPPHA_ENC0_INT_CODE MD_IRQID_PPPHA_ENC0_INT
+#define IRQ_PPPHA_ENC1_INT_CODE MD_IRQID_PPPHA_ENC1_INT
+#define IRQ_PPPHA_DEC0_INT_CODE MD_IRQID_PPPHA_DEC0_INT
+#define IRQ_PPPHA_DEC1_INT_CODE MD_IRQID_PPPHA_DEC1_INT
+#define IRQ_CS_NR_IRQ_CODE MD_IRQID_CS_NR_IRQ
+#define IRQ_CS_NR_ERR_IRQ_CODE MD_IRQID_CS_NR_ERR_IRQ
+#define IRQ_SDF_OVERFLOW_IRQ_CODE MD_IRQID_SDF_OVERFLOW_IRQ
+#define IRQ_MCUMMU_INT_CODE MD_IRQID_MCUMMU_INT
+#define IRQ_BIGRAM_0_IRQ_0_CODE MD_IRQID_BIGRAM_0_IRQ_0
+#define IRQ_COS_PREP_INT_CODE MD_IRQID_COS_PREP_INT
+#define IRQ_TRACE_INT_CODE MD_IRQID_TRACE_INT
+#define IRQ_NR_TIMER_IRQ0_CODE MD_IRQID_NR_TIMER_IRQ0
+#define IRQ_NR_TIMER_IRQ1_CODE MD_IRQID_NR_TIMER_IRQ1
+#define IRQ_NR_TIMER_IRQ2_CODE MD_IRQID_NR_TIMER_IRQ2
+#define IRQ_NR_TIMER_IRQ3_CODE MD_IRQID_NR_TIMER_IRQ3
+#define IRQ_NR_TIMER_IRQ4_CODE MD_IRQID_NR_TIMER_IRQ4
+#define IRQ_NR_TIMER_IRQ5_CODE MD_IRQID_NR_TIMER_IRQ5
+#define IRQ_NR_TIMER_IRQ6_CODE MD_IRQID_NR_TIMER_IRQ6
+#define IRQ_NR_TIMER_IRQ7_CODE MD_IRQID_NR_TIMER_IRQ7
+#define IRQ_NR_TIMER_IRQ8_CODE MD_IRQID_NR_TIMER_IRQ8
+#define IRQ_NR_TIMER_IRQ9_CODE MD_IRQID_NR_TIMER_IRQ9
+#define IRQ_NR_TIMER_IRQ10_CODE MD_IRQID_NR_TIMER_IRQ10
+#define IRQ_NR_TIMER_IRQ11_CODE MD_IRQID_NR_TIMER_IRQ11
+#define IRQ_NR_TIMER_IRQ12_CODE MD_IRQID_NR_TIMER_IRQ12
+#define IRQ_NR_TIMER_IRQ13_CODE MD_IRQID_NR_TIMER_IRQ13
+#define IRQ_NR_TIMER_IRQ14_CODE MD_IRQID_NR_TIMER_IRQ14
+#define IRQ_NR_TIMER_IRQ15_CODE MD_IRQID_NR_TIMER_IRQ15
+#define IRQ_NR_TIMER_IRQ16_CODE MD_IRQID_NR_TIMER_IRQ16
+#define IRQ_NR_TIMER_IRQ17_CODE MD_IRQID_NR_TIMER_IRQ17
+#define IRQ_NR_TIMER_IRQ18_CODE MD_IRQID_NR_TIMER_IRQ18
+#define IRQ_NR_TIMER_IRQ19_CODE MD_IRQID_NR_TIMER_IRQ19
+#define IRQ_NR_TIMER_IRQ20_CODE MD_IRQID_NR_TIMER_IRQ20
+#define IRQ_NR_TIMER_IRQ21_CODE MD_IRQID_NR_TIMER_IRQ21
+#define IRQ_NR_TIMER_IRQ22_CODE MD_IRQID_NR_TIMER_IRQ22
+#define IRQ_NR_TIMER_IRQ23_CODE MD_IRQID_NR_TIMER_IRQ23
+#define IRQ_NR_TIMER_IRQ24_CODE MD_IRQID_NR_TIMER_IRQ24
+#define IRQ_NR_TIMER_IRQ25_CODE MD_IRQID_NR_TIMER_IRQ25
+#define IRQ_NR_TIMER_IRQ26_CODE MD_IRQID_NR_TIMER_IRQ26
+#define IRQ_NR_TIMER_IRQ27_CODE MD_IRQID_NR_TIMER_IRQ27
+#define IRQ_NR_TIMER_IRQ28_CODE MD_IRQID_NR_TIMER_IRQ28
+#define IRQ_NR_TIMER_IRQ29_CODE MD_IRQID_NR_TIMER_IRQ29
+#define IRQ_NR_TIMER_IRQ30_CODE MD_IRQID_NR_TIMER_IRQ30
+#define IRQ_NR_TIMER_IRQ31_CODE MD_IRQID_NR_TIMER_IRQ31
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define IRQ_NR_TIMER_CNTDN_IRQ0_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define IRQ_NR_TIMER_CNTDN_IRQ1_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define IRQ_NR_TIMER_CNTDN_IRQ2_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define IRQ_NR_TIMER_CNTDN_IRQ3_CODE MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define IRQ_NR_EVENTGEN_SPU_CODE MD_IRQID_NR_EVENTGEN_SPU
+#define IRQ_SI_CM_ERR_CODE MD_IRQID_SI_CM_ERR
+#define IRQ_SI_CM_PCINT_CODE MD_IRQID_SI_CM_PCINT
+#define IRQ_MDM2C_U3G_CODE MD_IRQID_MDM2C_U3G
+#define IRQ_RAKE_CMIF_M2C_IRQ_0_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define IRQ_RAKE_CMIF_M2C_IRQ_1_CODE MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define IRQ_RAKE_CMIF_PD_DO_IRQ_CODE MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define IRQ_MDMCU_BUSMON_MATCH_STS_CODE MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define IRQ_MDINFRA_BUSMON_MATCH_STS_CODE MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define IRQ_ELMTOP_EMI_IRQ_CODE MD_IRQID_ELMTOP_EMI_IRQ
+#define IRQ_ELM_DMA_IRQ_CODE MD_IRQID_ELM_DMA_IRQ
+#define IRQ_BUSMPU_IRQ_CODE MD_IRQID_BUSMPU_IRQ
+#define IRQ_ST1X_CPINT_CODE MD_IRQID_ST1X_CPINT
+#define IRQ_ST1x_HALF_CPINT_CODE MD_IRQID_ST1x_HALF_CPINT
+#define IRQ_ST1x_CFG_CPINT_CODE MD_IRQID_ST1x_CFG_CPINT
+#define IRQ_ST1x_WAKEUP_IRQ_CODE MD_IRQID_ST1x_WAKEUP_IRQ
+#define IRQ_STDO_CPINT_CODE MD_IRQID_STDO_CPINT
+#define IRQ_STDO_HALF_CPINT_CODE MD_IRQID_STDO_HALF_CPINT
+#define IRQ_STDO_CFG_CPINT_CODE MD_IRQID_STDO_CFG_CPINT
+#define IRQ_STDO_WAKEUP_IRQ_CODE MD_IRQID_STDO_WAKEUP_IRQ
+#define IRQ_UART_MD0_CODE MD_IRQID_UART_MD0
+#define IRQ_UART_MD1_CODE MD_IRQID_UART_MD1
+#define IRQ_EINT0_CODE MD_IRQID_EINT0
+#define IRQ_EINT1_CODE MD_IRQID_EINT1
+#define IRQ_EINT2_CODE MD_IRQID_EINT2
+#define IRQ_EINT3_CODE MD_IRQID_EINT3
+#define IRQ_EINT_SHARE_CODE MD_IRQID_EINT_SHARE
+#define IRQ_GPTM1_CODE MD_IRQID_GPTM1
+#define IRQ_GPTM2_CODE MD_IRQID_GPTM2
+#define IRQ_GPTM3_CODE MD_IRQID_GPTM3
+#define IRQ_GPTM4_CODE MD_IRQID_GPTM4
+#define IRQ_GPTM5_CODE MD_IRQID_GPTM5
+#define IRQ_GPTM6_CODE MD_IRQID_GPTM6
+#define IRQ_GPTM7_CODE MD_IRQID_GPTM7
+#define IRQ_GPTM8_CODE MD_IRQID_GPTM8
+#define IRQ_GPTM9_CODE MD_IRQID_GPTM9
+#define IRQ_GPTM10_CODE MD_IRQID_GPTM10
+#define IRQ_GPTM11_CODE MD_IRQID_GPTM11
+#define IRQ_IDC_PM_INT_CODE MD_IRQID_IDC_PM_INT
+#define IRQ_IDC_UART_IRQ_CODE MD_IRQID_IDC_UART_IRQ
+#define IRQ_MDGDMA_FDMA5_CODE MD_IRQID_MDGDMA_FDMA5
+#define IRQ_MDGDMA_FDMA6_CODE MD_IRQID_MDGDMA_FDMA6
+#define IRQ_TDMA_CTIRQ4_CODE MD_IRQID_TDMA_CTIRQ4
+#define IRQ_PDMA_CODE MD_IRQID_PDMA
+#define IRQ_MDINFRA_BUS_DECERROR_CODE MD_IRQID_MDINFRA_BUS_DECERROR
+#define IRQ_I2C_TOP_INT_CODE MD_IRQID_I2C_TOP_INT
+#define IRQ_SOE_CODE MD_IRQID_SOE
+#define IRQ_ABM_INT_CODE MD_IRQID_ABM_INT
+#define IRQ_ABM_ERROR_INT_CODE MD_IRQID_ABM_ERROR_INT
+#define IRQ_USIP0_CODE MD_IRQID_USIP0
+#define IRQ_USIP1_CODE MD_IRQID_USIP1
+#define IRQ_USIP2_CODE MD_IRQID_USIP2
+#define IRQ_USIP3_CODE MD_IRQID_USIP3
+#define IRQ_USIP4_CODE MD_IRQID_USIP4
+#define IRQ_USIP5_CODE MD_IRQID_USIP5
+#define IRQ_USIP6_CODE MD_IRQID_USIP6
+#define IRQ_USIP7_CODE MD_IRQID_USIP7
+#define IRQ_USIP8_CODE MD_IRQID_USIP8
+#define IRQ_USIP9_CODE MD_IRQID_USIP9
+#define IRQ_USIP10_CODE MD_IRQID_USIP10
+#define IRQ_USIP11_CODE MD_IRQID_USIP11
+#define IRQ_USIP12_CODE MD_IRQID_USIP12
+#define IRQ_USIP13_CODE MD_IRQID_USIP13
+#define IRQ_TX_NR_CC0_IRQ_CODE MD_IRQID_TX_NR_CC0_IRQ
+#define IRQ_TX_NR_CC1_IRQ_CODE MD_IRQID_TX_NR_CC1_IRQ
+#define IRQ_TX_NR_ERR_CC_IRQ_CODE MD_IRQID_TX_NR_ERR_CC_IRQ
+#define IRQ_MDMCU_SPU_IRQ_CODE MD_IRQID_MDMCU_SPU_IRQ
+#define IRQ_DEM_TRIG_PS_INT_LE_CODE MD_IRQID_DEM_TRIG_PS_INT_LE
+#define IRQ_ECT_CODE MD_IRQID_ECT
+#define IRQ_MDMCU_BUS_DECERR_IRQ_CODE MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define IRQ_MDMCU_OSTD_THROTTLE_CODE MD_IRQID_MDMCU_OSTD_THROTTLE
+#define IRQ_SHAOLIN_OSTD_THROTTLE_CODE MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define IRQ_AP2MD_CONN_WF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define IRQ_MDWDT_CODE MD_IRQID_MDWDT
+#define IRQ_MDGDMA_FDMA0_2_CODE MD_IRQID_MDGDMA_FDMA0_2
+#define IRQ_MDGDMA_FDMA1_CODE MD_IRQID_MDGDMA_FDMA1
+#define IRQ_MDGDMA_FDMA3_CODE MD_IRQID_MDGDMA_FDMA3
+#define IRQ_MDGDMA_FDMA4_CODE MD_IRQID_MDGDMA_FDMA4
+#define IRQ_MDGDMA_HDMA0_1_CODE MD_IRQID_MDGDMA_HDMA0_1
+#define IRQ_MDGDMA_HDMA2_3_CODE MD_IRQID_MDGDMA_HDMA2_3
+#define IRQ_AP2MD_CCIF0_0_CODE MD_IRQID_AP2MD_CCIF0_0
+#define IRQ_AP2MD_CCIF0_1_CODE MD_IRQID_AP2MD_CCIF0_1
+#define IRQ_AP2MD_CCIF1_0_CODE MD_IRQID_AP2MD_CCIF1_0
+#define IRQ_AP2MD_CCIF1_1_CODE MD_IRQID_AP2MD_CCIF1_1
+#define IRQ_IEBIT_CHECK_IRQ0_CODE MD_IRQID_IEBIT_CHECK_IRQ0
+#define IRQ_IEBIT_CHECK_IRQ1_CODE MD_IRQID_IEBIT_CHECK_IRQ1
+#define IRQ_IEBIT_CHECK_IRQ2_CODE MD_IRQID_IEBIT_CHECK_IRQ2
+#define IRQ_IEBIT_CHECK_IRQ3_CODE MD_IRQID_IEBIT_CHECK_IRQ3
+#define IRQ_IEBIT_CHECK_IRQ4_CODE MD_IRQID_IEBIT_CHECK_IRQ4
+#define IRQ_IEBIT_CHECK_IRQ5_CODE MD_IRQID_IEBIT_CHECK_IRQ5
+#define IRQ_IEBIT_CHECK_IRQ6_CODE MD_IRQID_IEBIT_CHECK_IRQ6
+#define IRQ_IEBIT_CHECK_IRQ7_CODE MD_IRQID_IEBIT_CHECK_IRQ7
+#define IRQ_IEBIT_CHECK_IRQ8_CODE MD_IRQID_IEBIT_CHECK_IRQ8
+#define IRQ_IEBIT_CHECK_IRQ9_CODE MD_IRQID_IEBIT_CHECK_IRQ9
+#define IRQ_IEBIT_CHECK_IRQ10_CODE MD_IRQID_IEBIT_CHECK_IRQ10
+#define IRQ_IEBIT_CHECK_IRQ11_CODE MD_IRQID_IEBIT_CHECK_IRQ11
+#define IRQ_NRL2_HRT_CODE MD_IRQID_NRL2_HRT
+#define IRQ_NRL2_NOTIF_CODE MD_IRQID_NRL2_NOTIF
+#define IRQ_NRL2_EXCEP_CODE MD_IRQID_NRL2_EXCEP
+#define IRQ_NRL2_DPMAIF_MD_CODE MD_IRQID_NRL2_DPMAIF_MD
+#define IRQ_RXDFE_IRQ0_CODE MD_IRQID_RXDFE_IRQ0
+#define IRQ_IDC_UART_TX_FORCE_ON_CODE MD_IRQID_IDC_UART_TX_FORCE_ON
+#define IRQ_RXDFE_IRQ2_CODE MD_IRQID_RXDFE_IRQ2
+#define IRQ_RXDFE_IRQ3_CODE MD_IRQID_RXDFE_IRQ3
+#define IRQ_AP2MD_CONN_BGF_CCIF_0_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define IRQ_MD_RXDFE_BB_DUMP_CODE MD_IRQID_MD_RXDFE_BB_DUMP
+#define IRQ_AP2MD_CONN_BGF_CCIF_1_CODE MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define IRQ_TXCRP_CODE MD_IRQID_TXCRP
+#define IRQ_CM_NR_IRQ_CODE MD_IRQID_CM_NR_IRQ
+#define IRQ_CM_NR_ERR_IRQ_CODE MD_IRQID_CM_NR_ERR_IRQ
+#define IRQ_L1_LTE_SLEEP_IRQ_CODE MD_IRQID_L1_LTE_SLEEP_IRQ
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define IRQ_D_GDMA_0_IRQ_CODE MD_IRQID_D_GDMA_0_IRQ
+#define IRQ_D_GDMA_1_IRQ_CODE MD_IRQID_D_GDMA_1_IRQ
+#define IRQ_D_GDMA_2_IRQ_CODE MD_IRQID_D_GDMA_2_IRQ
+#define IRQ_D_GDMA_3_IRQ_CODE MD_IRQID_D_GDMA_3_IRQ
+#define IRQ_D_GDMA_4_IRQ_CODE MD_IRQID_D_GDMA_4_IRQ
+#define IRQ_D_GDMA_5_IRQ_CODE MD_IRQID_D_GDMA_5_IRQ
+#define IRQ_PLL_GEARHP_RDY_CODE MD_IRQID_PLL_GEARHP_RDY
+#define IRQ_REQ_ABNORM_IRQ_CODE MD_IRQID_REQ_ABNORM_IRQ
+#define IRQ_NRL2_DPMAIF_MDMCU_CODE MD_IRQID_NRL2_DPMAIF_MDMCU
+#define IRQ_AP2MD_APWDT_IRQ_CODE MD_IRQID_AP2MD_APWDT_IRQ
+#define IRQ_DUMMY_PRIORITY_CODE_3 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define IRQ_DUMMY_PRIORITY_CODE_4 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define IRQ_DUMMY_PRIORITY_CODE_5 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define IRQ_L1M_PHY_LTMR_IRQ_0_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define IRQ_L1M_PHY_LTMR_IRQ_1_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define IRQ_L1M_PHY_LTMR_IRQ_2_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define IRQ_L1M_PHY_LTMR_IRQ_3_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define IRQ_L1M_PHY_LTMR_IRQ_4_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define IRQ_L1M_PHY_LTMR_IRQ_5_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define IRQ_L1M_PHY_LTMR_IRQ_6_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define IRQ_L1M_PHY_LTMR_IRQ_7_CODE MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define IRQ_DUMMY_PRIORITY_CODE_6 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define IRQ_L1_LTE_WAKEUP_IRQ_CODE MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define IRQ_TDD_WAKEUP_IRQ_CODE MD_IRQID_TDD_WAKEUP_IRQ
+#define IRQ_TDD_TIMER_L1D_1_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define IRQ_TDD_TIMER_L1D_2_IRQ_CODE MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define IRQ_RTR_SLT_0_IRQ_CODE MD_IRQID_RTR_SLT_0_IRQ
+#define IRQ_RTR_SLT_1_IRQ_CODE MD_IRQID_RTR_SLT_1_IRQ
+#define IRQ_FDD_SLP_IRQ_CODE MD_IRQID_FDD_SLP_IRQ
+#define IRQ_IRDBG_MCU_INT_CODE MD_IRQID_IRDBG_MCU_INT
+#define IRQ_MD_DVFS_CTRL_IRQ_0_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define IRQ_MD_DVFS_CTRL_IRQ_1_CODE MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define IRQ_NR_SLP_WAKEUP_CODE MD_IRQID_NR_SLP_WAKEUP
+#define IRQ_NR_SLP_SLEEP_CODE MD_IRQID_NR_SLP_SLEEP
+#define IRQ_NR_TIMER_ERR_CODE MD_IRQID_NR_TIMER_ERR
+#define IRQ_TXBSRP_CODE MD_IRQID_TXBSRP
+#define IRQ_TXDFE_D_CODE MD_IRQID_TXDFE_D
+#define IRQ_NR_EVENTGEN_ERR_CODE MD_IRQID_NR_EVENTGEN_ERR
+#define IRQ_AIRQ_PAD_CODE MD_IRQID_AIRQ_PAD
+#define IRQ_CSSYS_FDD_CS_IRQ_CODE MD_IRQID_CSSYS_FDD_CS_IRQ
+#define IRQ_CSSYS_TDD_CS_IRQ_CODE MD_IRQID_CSSYS_TDD_CS_IRQ
+#define IRQ_CSSYS_LTE_CS_IRQ_CODE MD_IRQID_CSSYS_LTE_CS_IRQ
+#define IRQ_CSSYS_1X_CS_IRQ_CODE MD_IRQID_CSSYS_1X_CS_IRQ
+#define IRQ_CSSYS_DO_CS_IRQ_CODE MD_IRQID_CSSYS_DO_CS_IRQ
+#define IRQ_PCIE_INTERRUPT_OUT_CODE MD_IRQID_PCIE_INTERRUPT_OUT
+#define IRQ_UCNT_SCH_IRQ_CODE MD_IRQID_UCNT_SCH_IRQ
+#define IRQ_UCNT_ERR_IRQ_CODE MD_IRQID_UCNT_ERR_IRQ
+#define IRQ_UCNT_ADJ_IRQ_CODE MD_IRQID_UCNT_ADJ_IRQ
+#define IRQ_SL_WAITSLEEP_CODE MD_IRQID_SL_WAITSLEEP
+#define IRQ_PTP_THERM_INT_INT_CODE MD_IRQID_PTP_THERM_INT_INT
+#define IRQ_PTP_FSM_INT_CODE MD_IRQID_PTP_FSM_INT
+#define IRQ_AP2MD_DAPC_CODE MD_IRQID_AP2MD_DAPC
+#define IRQ_AP2MD_CCIF2_CODE MD_IRQID_AP2MD_CCIF2
+#define IRQ_AP2MD_UFS_CODE MD_IRQID_AP2MD_UFS
+#define IRQ_SSUSB_INTERRUPT_OUT_CODE MD_IRQID_SSUSB_INTERRUPT_OUT
+#define IRQ_AP2MD_MSDC0_CODE MD_IRQID_AP2MD_MSDC0
+#define IRQ_MIPI_IRQ_CODE MD_IRQID_MIPI_IRQ
+#define IRQ_CONN_BT_ISOCH_CODE MD_IRQID_CONN_BT_ISOCH
+#define IRQ_RMPU_CTIREIGIN_CODE MD_IRQID_RMPU_CTIREIGIN
+#define IRQ_FREQM_IRQ_CODE MD_IRQID_FREQM_IRQ
+#define IRQ_BT_CVSD_CODE MD_IRQID_BT_CVSD
+#define IRQ_SW_LISR0_CODE MD_IRQID_SW_TRIGGER_RESERVED_0
+#define IRQ_SW_LISR1_CODE MD_IRQID_SW_TRIGGER_RESERVED_1
+#define IRQ_SW_LISR2_CODE MD_IRQID_SW_TRIGGER_RESERVED_2
+#define IRQ_SW_LISR3_CODE MD_IRQID_SW_TRIGGER_RESERVED_3
+#define IRQ_SW_LISR4_CODE MD_IRQID_SW_TRIGGER_RESERVED_4
+#define IRQ_SW_LISR5_CODE MD_IRQID_SW_TRIGGER_RESERVED_5
+#define IRQ_SW_LISR6_CODE MD_IRQID_SW_TRIGGER_RESERVED_6
+#define IRQ_SW_LISR7_CODE MD_IRQID_SW_TRIGGER_RESERVED_7
+#define IRQ_SW_LISR8_CODE MD_IRQID_SW_TRIGGER_RESERVED_8
+#define IRQ_SW_LISR9_CODE MD_IRQID_SW_TRIGGER_RESERVED_9
+#define IRQ_SW_LISR10_CODE MD_IRQID_SW_TRIGGER_RESERVED_10
+#define IRQ_SW_LISR11_CODE MD_IRQID_SW_TRIGGER_RESERVED_11
+#define IRQ_SW_LISR12_CODE MD_IRQID_SW_TRIGGER_RESERVED_12
+#define IRQ_SW_LISR13_CODE MD_IRQID_SW_TRIGGER_RESERVED_13
+#define IRQ_SW_LISR14_CODE MD_IRQID_SW_TRIGGER_RESERVED_14
+#define IRQ_SW_LISR15_CODE MD_IRQID_SW_TRIGGER_RESERVED_15
+#define IRQ_SW_LISR16_CODE MD_IRQID_SW_TRIGGER_RESERVED_16
+#define IRQ_SW_LISR17_CODE MD_IRQID_SW_TRIGGER_RESERVED_17
+#define IRQ_SW_LISR18_CODE MD_IRQID_SW_TRIGGER_RESERVED_18
+#define IRQ_SW_LISR19_CODE MD_IRQID_SW_TRIGGER_RESERVED_19
+#define IRQ_SW_LISR20_CODE MD_IRQID_SW_TRIGGER_RESERVED_20
+#define IRQ_SW_LISR21_CODE MD_IRQID_SW_TRIGGER_RESERVED_21
+#define IRQ_SW_LISR22_CODE MD_IRQID_SW_TRIGGER_RESERVED_22
+#define IRQ_SW_LISR23_CODE MD_IRQID_SW_TRIGGER_RESERVED_23
+#define IRQ_SW_LISR24_CODE MD_IRQID_SW_TRIGGER_RESERVED_24
+#define IRQ_SW_LISR25_CODE MD_IRQID_SW_TRIGGER_RESERVED_25
+#define IRQ_SW_LISR26_CODE MD_IRQID_SW_TRIGGER_RESERVED_26
+#define IRQ_SW_LISR27_CODE MD_IRQID_SW_TRIGGER_RESERVED_27
+#define IRQ_SW_LISR28_CODE MD_IRQID_SW_TRIGGER_RESERVED_28
+#define IRQ_SW_LISR29_CODE MD_IRQID_SW_TRIGGER_RESERVED_29
+#define IRQ_SW_LISR30_CODE MD_IRQID_SW_TRIGGER_RESERVED_30
+#define IRQ_SW_LISR31_CODE MD_IRQID_SW_TRIGGER_RESERVED_31
+#define IRQ_SW_LISR32_CODE MD_IRQID_SW_TRIGGER_RESERVED_32
+#define IRQ_SW_LISR33_CODE MD_IRQID_SW_TRIGGER_RESERVED_33
+#define IRQ_SW_LISR34_CODE MD_IRQID_SW_TRIGGER_RESERVED_34
+#define IRQ_SW_LISR35_CODE MD_IRQID_SW_TRIGGER_RESERVED_35
+#define IRQ_SW_LISR36_CODE MD_IRQID_SW_TRIGGER_RESERVED_36
+#define IRQ_SW_LISR37_CODE MD_IRQID_SW_TRIGGER_RESERVED_37
+#define IRQ_SW_LISR38_CODE MD_IRQID_SW_TRIGGER_RESERVED_38
+#define IRQ_SW_LISR39_CODE MD_IRQID_SW_TRIGGER_RESERVED_39
+#define IRQ_SW_LISR40_CODE MD_IRQID_SW_TRIGGER_RESERVED_40
+#define IRQ_SW_LISR41_CODE MD_IRQID_SW_TRIGGER_RESERVED_41
+#define IRQ_SW_LISR42_CODE MD_IRQID_SW_TRIGGER_RESERVED_42
+#define IRQ_SW_LISR43_CODE MD_IRQID_SW_TRIGGER_RESERVED_43
+#define IRQ_SW_LISR44_CODE MD_IRQID_SW_TRIGGER_RESERVED_44
+#define IRQ_SW_LISR45_CODE MD_IRQID_SW_TRIGGER_RESERVED_45
+#define IRQ_SW_LISR46_CODE MD_IRQID_SW_TRIGGER_RESERVED_46
+#define IRQ_SW_LISR47_CODE MD_IRQID_SW_TRIGGER_RESERVED_47
+#define IRQ_SW_LISR48_CODE MD_IRQID_SW_TRIGGER_RESERVED_48
+#define IRQ_SW_LISR49_CODE MD_IRQID_SW_TRIGGER_RESERVED_49
+#define IRQ_SW_LISR50_CODE MD_IRQID_SW_TRIGGER_RESERVED_50
+#define IRQ_SW_LISR51_CODE MD_IRQID_SW_TRIGGER_RESERVED_51
+#define IRQ_SW_LISR52_CODE MD_IRQID_SW_TRIGGER_RESERVED_52
+#define IRQ_SW_LISR53_CODE MD_IRQID_SW_TRIGGER_RESERVED_53
+#define IRQ_SW_LISR54_CODE MD_IRQID_SW_TRIGGER_RESERVED_54
+#define IRQ_SW_LISR55_CODE MD_IRQID_SW_TRIGGER_RESERVED_55
+#define IRQ_SW_LISR56_CODE MD_IRQID_SW_TRIGGER_RESERVED_56
+#define IRQ_SW_LISR57_CODE MD_IRQID_SW_TRIGGER_RESERVED_57
+#define IRQ_SW_LISR58_CODE MD_IRQID_SW_TRIGGER_RESERVED_58
+#define IRQ_SW_LISR59_CODE MD_IRQID_SW_TRIGGER_RESERVED_59
+#define IRQ_SW_LISR60_CODE MD_IRQID_SW_TRIGGER_RESERVED_60
+#define IRQ_SW_LISR61_CODE MD_IRQID_SW_TRIGGER_RESERVED_61
+#define IRQ_SW_LISR62_CODE MD_IRQID_SW_TRIGGER_RESERVED_62
+#define IRQ_SW_LISR63_CODE MD_IRQID_SW_TRIGGER_RESERVED_63
+#define IRQ_SW_LISR64_CODE MD_IRQID_SW_TRIGGER_RESERVED_64
+#define IRQ_DUMMY_PRIORITY_CODE_8 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define IRQ_DUMMY_PRIORITY_CODE_9 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define IRQ_DUMMY_PRIORITY_CODE_10 MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define IRQ_DUMMY_PRIORITY_CODE_11 MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define IRQ_DUMMY_PRIORITY_CODE_12 MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define IRQ_DUMMY_PRIORITY_CODE_13 MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define IRQ_DUMMY_PRIORITY_CODE_14 MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define IRQ_DUMMY_PRIORITY_CODE_15 MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define IRQ_DUMMY_PRIORITY_CODE_16 MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define IRQ_DUMMY_PRIORITY_CODE_17 MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define IRQ_DUMMY_PRIORITY_CODE_18 MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define IRQ_DUMMY_PRIORITY_CODE_19 MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define IRQ_DUMMY_PRIORITY_CODE_20 MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define IRQ_DUMMY_PRIORITY_CODE_21 MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define IRQ_DUMMY_PRIORITY_CODE_22 MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define IRQ_DUMMY_PRIORITY_CODE_23 MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define IRQ_DUMMY_PRIORITY_CODE_24 MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define IRQ_DUMMY_PRIORITY_CODE_25 MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define IRQ_DUMMY_PRIORITY_CODE_26 MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define IRQ_DUMMY_PRIORITY_CODE_27 MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define IRQ_DUMMY_PRIORITY_CODE_28 MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define IRQ_DUMMY_PRIORITY_CODE_29 MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define IRQ_DUMMY_PRIORITY_CODE_30 MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define IRQ_SW_MODIS_MASE_HMU_CODE IRQ_DUMMY_PRIORITY_CODE_25
+#define IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_26
+#define IRQ_SW_MODIS_MASE_NR_TXLISR_CODE IRQ_DUMMY_PRIORITY_CODE_27
+#define IRQ_L1_PAE_SW_LISR0 IRQ_DUMMY_PRIORITY_CODE_28
+#define IRQ_L1_PAE_SW_LISR1 IRQ_DUMMY_PRIORITY_CODE_29
+#define IRQ_L1_PAE_SW_LISR2 IRQ_DUMMY_PRIORITY_CODE_30
+#endif
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+ 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+ /* Group0(0) */ 0xFFE, \
+ /* Group1(1) */ 0xFFD, \
+ /* Group2(2) */ 0xFFB, \
+ /* Group3(3) */ 0xFF7, \
+ /* Group4(4) */ 0xFEF, \
+ /* Group5(5) */ 0xFDF, \
+ /* Group6(6) */ 0xFBF, \
+ /* Group7(7) */ 0xF7F, \
+ /* Group8(8) */ 0xEFF, \
+ /* Group9(9) */ 0xDFF, \
+ /* Group10(10) */ 0xBFF, \
+ /* Group11(11) */ 0x7FF, \
+ /* Group12(1,4) */ 0xFED, \
+ /* Group13(0,1,2) */ 0xFF8, \
+ /* Group14(3,6,9) */ 0xDB7, \
+ /* Group15(0,3,6,9) */ 0xDB6, \
+ /* Group16(3,4,6,7,9,10) */ 0x927, \
+ /* Group17(0,1,2,3,4,6,7,9,10) */ 0x920, \
+ /* Group18(3,4,5,6,7,8,9,10,11) */ 0x007, \
+ /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */ 0x000, \
+ /* Group20(3,4,6,7,9,10) -> Reserved for NR runtime change affinity */ 0x927, \
+ /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */ 0x007, \
+ /* Group22(2) -> Reserved for LTE runtime change affinity */ 0xFFB, \
+ /* Group23(0,2,3,4,6,7,9,10) -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */ 0x922, \
+ /* Group24 */ 0xFFF, \
+ /* Group25 */ 0xFFF, \
+ /* Group26 */ 0xFFF, \
+ /* Group27 */ 0xFFF, \
+ /* Group28 */ 0xFFF, \
+ /* Group29 */ 0xFFF, \
+ /* Group30 */ 0xFFF, \
+ /* Group31 */ 0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions -
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0 0 //(0)
+#define IRQ_AFFINITY_GROUP_VPE1 1 //(1)
+#define IRQ_AFFINITY_GROUP_VPE2 2 //(2)
+#define IRQ_AFFINITY_GROUP_VPE3 3 //(3)
+#define IRQ_AFFINITY_GROUP_VPE4 4 //(4)
+#define IRQ_AFFINITY_GROUP_VPE5 5 //(5)
+#define IRQ_AFFINITY_GROUP_VPE6 6 //(6)
+#define IRQ_AFFINITY_GROUP_VPE7 7 //(7)
+#define IRQ_AFFINITY_GROUP_VPE8 8 //(8)
+#define IRQ_AFFINITY_GROUP_VPE9 9 //(9)
+#define IRQ_AFFINITY_GROUP_VPE10 10 //(10)
+#define IRQ_AFFINITY_GROUP_VPE11 11 //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4 12 //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0 13 //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR 14 //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP 15 //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR 16 //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP 17 //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR 18 //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE 19 //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11 ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+typedef enum
+{
+ VPE_STATUS_LISR_HIGHEST = 0,
+ VPE_STATUS_LISR_LOWEST = 337,
+ VPE_STATUS_HISR_TASK_HIGHEST = 512,
+ VPE_STATUS_HISR_TASK_LOWEST = VPE_STATUS_HISR_TASK_HIGHEST+KAL_MAX_NUM_TASKS,
+ VPE_STATUS_END = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+ IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MERCURY_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h
new file mode 100644
index 0000000..ce65e41
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_MERCURY_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * MERCURY
+ *
+ * Description:
+ * ------------
+ * This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+ 1st parameter: The name of software handler
+ 2nd parameter: The software handler number
+ 3th parameter: The mapping of software handler to hardware interrupt code
+ User:
+ SW_TRIGGER_CODE0 = Karthigeyan Reddy
+ SW_TRIGGER_CODE1 = Karthigeyan Reddy
+ SW_TRIGGER_CODE2 = Karthigeyan Reddy
+ SW_TRIGGER_CODE3 = Karthigeyan Reddy
+ SW_TRIGGER_CODE4 = Karthigeyan Reddy
+ SW_TRIGGER_CODE5 = Karthigeyan Reddy
+ SW_TRIGGER_CODE6 = Zengling Jin
+ SW_TRIGGER_CODE7 = Zengling Jin
+ SW_TRIGGER_CODE8 = Zengling Jin
+ SW_TRIGGER_CODE9 = Cruze Yu
+ SW_TRIGGER_CODE10 = Cruze Yu
+ SW_TRIGGER_CODE11 = Cruze Yu
+ SW_TRIGGER_CODE12 = Cruze Yu
+ SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+ SW_TRIGGER_CODE14 = HW Jheng
+ SW_TRIGGER_CODE15 = Frank Hu
+ SW_TRIGGER_CODE16 = KH Hsiao
+ SW_TRIGGER_CODE17 = Deepti Varadarajan
+ SW_TRIGGER_CODE18 = Owen Ho
+ SW_TRIGGER_CODE19 = Owen Ho
+ SW_TRIGGER_CODE20 = Owen Ho
+ SW_TRIGGER_CODE21 = Owen Ho
+ SW_TRIGGER_CODE22 = Jun-Ying Huang
+ SW_TRIGGER_CODE23 = Jun-Ying Huang
+ SW_TRIGGER_CODE24 = Jun-Ying Huang
+ SW_TRIGGER_CODE25 = Jun-Ying Huang
+ SW_TRIGGER_CODE26 = Wade Huang
+ SW_TRIGGER_CODE27 = Tee-Yuen Chun
+ SW_TRIGGER_CODE28 = YY Hsieh
+ SW_TRIGGER_CODE29 = Hamilton Liang
+ SW_TRIGGER_CODE30 = HW Jheng
+ SW_TRIGGER_CODE31 = Weimin Zeng
+ SW_TRIGGER_CODE32 = Weimin Zeng
+ SW_TRIGGER_CODE33 = Jocobrian Chang
+ SW_TRIGGER_CODE34 = JiaHong Hsu
+ SW_TRIGGER_CODE35 = Cheng-Long Wu
+ SW_TRIGGER_CODE36 = Cheng-Long Wu
+ SW_TRIGGER_CODE37 = Jocobrian Chang
+ SW_TRIGGER_CODE38 = Jocobrian Chang
+ SW_TRIGGER_CODE39 = Jocobrian Chang
+ SW_TRIGGER_CODE40 = Shu-Wei Ho
+ SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+ SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+ SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+ SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+ SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+ */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..5499477
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MERCURY)
+ #include "intrCtrl_MERCURY_SW_Handle.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h
new file mode 100644
index 0000000..07b86ff
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h
@@ -0,0 +1,3 @@
+#if defined(MERCURY)
+ #include "irqPriority_MERCURY.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h
new file mode 100644
index 0000000..8bbd894
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqid.h b/mcu/interface/driver/devdrv/cirq/md97p/irqid.h
new file mode 100644
index 0000000..e30d214
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqid.h
@@ -0,0 +1,8 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MERCURY)
+ #include "irqid_MERCURY.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h
new file mode 100644
index 0000000..39d74a3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h
@@ -0,0 +1,388 @@
+#ifndef __MERCURY_IRQID_H__
+#define __MERCURY_IRQID_H__
+
+
+//MERCURY IRQID
+#define MD_IRQID_USIM0 0
+#define MD_IRQID_USIM1 1
+#define MD_IRQID_TDMA_CTIRQ1 2
+#define MD_IRQID_TDMA_CTIRQ2 3
+#define MD_IRQID_TDMA_CTIRQ3 4
+#define MD_IRQID_TDMA_WAKEUP_IRQ 5
+#define MD_IRQID_OST 6
+#define MD_IRQID_MDRTT 7
+#define MD_IRQID_MDEVDO 8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT 9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT 11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT 12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT 13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT 14
+#define MD_IRQID_SHARE_D12MINT1 15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ 16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ 17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ 18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ 19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ 20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ 21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ 22
+#define MD_IRQID_AIRQ_SERDES 23
+#define MD_IRQID_AIRQ_COS 24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR 25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR 26
+#define MD_IRQID_PPPHA_ENC0_INT 27
+#define MD_IRQID_PPPHA_ENC1_INT 28
+#define MD_IRQID_PPPHA_DEC0_INT 29
+#define MD_IRQID_PPPHA_DEC1_INT 30
+#define MD_IRQID_CS_NR_IRQ 31
+#define MD_IRQID_CS_NR_ERR_IRQ 32
+#define MD_IRQID_SDF_OVERFLOW_IRQ 33
+#define MD_IRQID_MCUMMU_INT 34
+#define MD_IRQID_BIGRAM_0_IRQ_0 35
+#define MD_IRQID_COS_PREP_INT 36
+#define MD_IRQID_TRACE_INT 37
+#define MD_IRQID_NR_TIMER_IRQ0 38
+#define MD_IRQID_NR_TIMER_IRQ1 39
+#define MD_IRQID_NR_TIMER_IRQ2 40
+#define MD_IRQID_NR_TIMER_IRQ3 41
+#define MD_IRQID_NR_TIMER_IRQ4 42
+#define MD_IRQID_NR_TIMER_IRQ5 43
+#define MD_IRQID_NR_TIMER_IRQ6 44
+#define MD_IRQID_NR_TIMER_IRQ7 45
+#define MD_IRQID_NR_TIMER_IRQ8 46
+#define MD_IRQID_NR_TIMER_IRQ9 47
+#define MD_IRQID_NR_TIMER_IRQ10 48
+#define MD_IRQID_NR_TIMER_IRQ11 49
+#define MD_IRQID_NR_TIMER_IRQ12 50
+#define MD_IRQID_NR_TIMER_IRQ13 51
+#define MD_IRQID_NR_TIMER_IRQ14 52
+#define MD_IRQID_NR_TIMER_IRQ15 53
+#define MD_IRQID_NR_TIMER_IRQ16 54
+#define MD_IRQID_NR_TIMER_IRQ17 55
+#define MD_IRQID_NR_TIMER_IRQ18 56
+#define MD_IRQID_NR_TIMER_IRQ19 57
+#define MD_IRQID_NR_TIMER_IRQ20 58
+#define MD_IRQID_NR_TIMER_IRQ21 59
+#define MD_IRQID_NR_TIMER_IRQ22 60
+#define MD_IRQID_NR_TIMER_IRQ23 61
+#define MD_IRQID_NR_TIMER_IRQ24 62
+#define MD_IRQID_NR_TIMER_IRQ25 63
+#define MD_IRQID_NR_TIMER_IRQ26 64
+#define MD_IRQID_NR_TIMER_IRQ27 65
+#define MD_IRQID_NR_TIMER_IRQ28 66
+#define MD_IRQID_NR_TIMER_IRQ29 67
+#define MD_IRQID_NR_TIMER_IRQ30 68
+#define MD_IRQID_NR_TIMER_IRQ31 69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0 70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1 71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2 72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3 73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4 74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5 75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6 76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7 77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8 78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9 79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10 80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11 81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12 82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13 83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14 84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15 85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16 86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17 87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3 91
+#define MD_IRQID_NR_EVENTGEN_SPU 92
+#define MD_IRQID_SI_CM_ERR 93
+#define MD_IRQID_SI_CM_PCINT 94
+#define MD_IRQID_MDM2C_U3G 95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ 98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ 99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ 100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS 101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS 102
+#define MD_IRQID_ELMTOP_EMI_IRQ 103
+#define MD_IRQID_ELM_DMA_IRQ 104
+#define MD_IRQID_BUSMPU_IRQ 105
+#define MD_IRQID_ST1X_CPINT 106
+#define MD_IRQID_ST1x_HALF_CPINT 107
+#define MD_IRQID_ST1x_CFG_CPINT 108
+#define MD_IRQID_ST1x_WAKEUP_IRQ 109
+#define MD_IRQID_STDO_CPINT 110
+#define MD_IRQID_STDO_HALF_CPINT 111
+#define MD_IRQID_STDO_CFG_CPINT 112
+#define MD_IRQID_STDO_WAKEUP_IRQ 113
+#define MD_IRQID_UART_MD0 114
+#define MD_IRQID_UART_MD1 115
+#define MD_IRQID_EINT0 116
+#define MD_IRQID_EINT1 117
+#define MD_IRQID_EINT2 118
+#define MD_IRQID_EINT3 119
+#define MD_IRQID_EINT_SHARE 120
+#define MD_IRQID_GPTM1 121
+#define MD_IRQID_GPTM2 122
+#define MD_IRQID_GPTM3 123
+#define MD_IRQID_GPTM4 124
+#define MD_IRQID_GPTM5 125
+#define MD_IRQID_GPTM6 126
+#define MD_IRQID_GPTM7 127
+#define MD_IRQID_GPTM8 128
+#define MD_IRQID_GPTM9 129
+#define MD_IRQID_GPTM10 130
+#define MD_IRQID_GPTM11 131
+#define MD_IRQID_IDC_PM_INT 132
+#define MD_IRQID_IDC_UART_IRQ 133
+#define MD_IRQID_MDGDMA_FDMA5 134
+#define MD_IRQID_MDGDMA_FDMA6 135
+#define MD_IRQID_TDMA_CTIRQ4 136
+#define MD_IRQID_PDMA 137
+#define MD_IRQID_MDINFRA_BUS_DECERROR 138
+#define MD_IRQID_I2C_TOP_INT 139
+#define MD_IRQID_SOE 140
+#define MD_IRQID_ABM_INT 141
+#define MD_IRQID_ABM_ERROR_INT 142
+#define MD_IRQID_USIP0 143
+#define MD_IRQID_USIP1 144
+#define MD_IRQID_USIP2 145
+#define MD_IRQID_USIP3 146
+#define MD_IRQID_USIP4 147
+#define MD_IRQID_USIP5 148
+#define MD_IRQID_USIP6 149
+#define MD_IRQID_USIP7 150
+#define MD_IRQID_USIP8 151
+#define MD_IRQID_USIP9 152
+#define MD_IRQID_USIP10 153
+#define MD_IRQID_USIP11 154
+#define MD_IRQID_USIP12 155
+#define MD_IRQID_USIP13 156
+#define MD_IRQID_TX_NR_CC0_IRQ 157
+#define MD_IRQID_TX_NR_CC1_IRQ 158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ 159
+#define MD_IRQID_MDMCU_SPU_IRQ 160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE 161
+#define MD_IRQID_ECT 162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ 163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE 164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE 165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ 166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ 167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0 168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ 169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1 170
+#define MD_IRQID_MDWDT 171
+#define MD_IRQID_MDGDMA_FDMA0_2 172
+#define MD_IRQID_MDGDMA_FDMA1 173
+#define MD_IRQID_MDGDMA_FDMA3 174
+#define MD_IRQID_MDGDMA_FDMA4 175
+#define MD_IRQID_MDGDMA_HDMA0_1 176
+#define MD_IRQID_MDGDMA_HDMA2_3 177
+#define MD_IRQID_AP2MD_CCIF0_0 178
+#define MD_IRQID_AP2MD_CCIF0_1 179
+#define MD_IRQID_AP2MD_CCIF1_0 180
+#define MD_IRQID_AP2MD_CCIF1_1 181
+#define MD_IRQID_IEBIT_CHECK_IRQ0 182
+#define MD_IRQID_IEBIT_CHECK_IRQ1 183
+#define MD_IRQID_IEBIT_CHECK_IRQ2 184
+#define MD_IRQID_IEBIT_CHECK_IRQ3 185
+#define MD_IRQID_IEBIT_CHECK_IRQ4 186
+#define MD_IRQID_IEBIT_CHECK_IRQ5 187
+#define MD_IRQID_IEBIT_CHECK_IRQ6 188
+#define MD_IRQID_IEBIT_CHECK_IRQ7 189
+#define MD_IRQID_IEBIT_CHECK_IRQ8 190
+#define MD_IRQID_IEBIT_CHECK_IRQ9 191
+#define MD_IRQID_IEBIT_CHECK_IRQ10 192
+#define MD_IRQID_IEBIT_CHECK_IRQ11 193
+#define MD_IRQID_NRL2_HRT 194
+#define MD_IRQID_NRL2_NOTIF 195
+#define MD_IRQID_NRL2_EXCEP 196
+#define MD_IRQID_NRL2_DPMAIF_MD 197
+#define MD_IRQID_RXDFE_IRQ0 198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON 199
+#define MD_IRQID_RXDFE_IRQ2 200
+#define MD_IRQID_RXDFE_IRQ3 201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0 202
+#define MD_IRQID_MD_RXDFE_BB_DUMP 203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1 204
+#define MD_IRQID_TXCRP 205
+#define MD_IRQID_CM_NR_IRQ 206
+#define MD_IRQID_CM_NR_ERR_IRQ 207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ 208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0 209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1 210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2 211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3 212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4 213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5 214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6 215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7 216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8 217
+#define MD_IRQID_D_GDMA_0_IRQ 218
+#define MD_IRQID_D_GDMA_1_IRQ 219
+#define MD_IRQID_D_GDMA_2_IRQ 220
+#define MD_IRQID_D_GDMA_3_IRQ 221
+#define MD_IRQID_D_GDMA_4_IRQ 222
+#define MD_IRQID_D_GDMA_5_IRQ 223
+#define MD_IRQID_PLL_GEARHP_RDY 224
+#define MD_IRQID_REQ_ABNORM_IRQ 225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU 226
+#define MD_IRQID_AP2MD_APWDT_IRQ 227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3 228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4 229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5 230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ 231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6 240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ 241
+#define MD_IRQID_TDD_WAKEUP_IRQ 242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ 243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ 244
+#define MD_IRQID_RTR_SLT_0_IRQ 245
+#define MD_IRQID_RTR_SLT_1_IRQ 246
+#define MD_IRQID_FDD_SLP_IRQ 247
+#define MD_IRQID_IRDBG_MCU_INT 248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1 250
+#define MD_IRQID_NR_SLP_WAKEUP 251
+#define MD_IRQID_NR_SLP_SLEEP 252
+#define MD_IRQID_NR_TIMER_ERR 253
+#define MD_IRQID_TXBSRP 254
+#define MD_IRQID_TXDFE_D 255
+#define MD_IRQID_NR_EVENTGEN_ERR 256
+#define MD_IRQID_AIRQ_PAD 257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ 258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ 259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ 260
+#define MD_IRQID_CSSYS_1X_CS_IRQ 261
+#define MD_IRQID_CSSYS_DO_CS_IRQ 262
+#define MD_IRQID_PCIE_INTERRUPT_OUT 263
+#define MD_IRQID_UCNT_SCH_IRQ 264
+#define MD_IRQID_UCNT_ERR_IRQ 265
+#define MD_IRQID_UCNT_ADJ_IRQ 266
+#define MD_IRQID_SL_WAITSLEEP 267
+#define MD_IRQID_PTP_THERM_INT_INT 268
+#define MD_IRQID_PTP_FSM_INT 269
+#define MD_IRQID_AP2MD_DAPC 270
+#define MD_IRQID_AP2MD_CCIF2 271
+#define MD_IRQID_AP2MD_UFS 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT 273
+#define MD_IRQID_AP2MD_MSDC0 274
+#define MD_IRQID_MIPI_IRQ 275
+#define MD_IRQID_CONN_BT_ISOCH 276
+#define MD_IRQID_RMPU_CTIREIGIN 277
+#define MD_IRQID_FREQM_IRQ 278
+#define MD_IRQID_BT_CVSD 279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0 280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1 281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2 282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3 283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4 284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5 285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6 286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7 287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8 288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9 289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10 290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11 291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12 292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13 293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14 294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15 295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16 296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17 297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18 298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19 299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20 300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21 301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22 302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23 303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24 304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25 305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26 306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27 307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28 308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29 309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30 310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31 311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32 312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33 313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34 314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35 315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36 316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37 317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38 318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39 319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40 320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41 321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42 322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43 323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44 324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45 325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46 326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47 327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48 328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49 329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50 330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51 331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52 332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53 333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54 334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55 335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56 336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57 337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58 338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59 339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60 340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61 341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62 342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63 343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64 344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8 345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9 346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10 347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11 348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12 349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13 350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14 351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15 352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16 353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17 354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18 355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19 356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20 357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21 358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22 359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23 360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24 361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25 362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26 363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27 364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28 365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29 366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30 367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MERCURY_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h b/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h
new file mode 100644
index 0000000..63ba404
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h
@@ -0,0 +1,103 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * isrentry.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct
+{
+ kal_uint32 vector;
+ void (*lisr_handler) (kal_uint32);
+ kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+