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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon.h
new file mode 100644
index 0000000..f4fcf05
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon.h
@@ -0,0 +1,264 @@
+#ifndef __DRV_PCMON_H__
+#define __DRV_PCMON_H__
+
+/*****************************************************************************
+ * Includes
+ *****************************************************************************/
+
+#include "drv_pcmon_common.h"
+#include "drv_pcmon_v2.h"
+
+/*****************************************************************************
+ * Type Definition
+ *****************************************************************************/
+
+typedef PDAMON_CFG_V2_T PDAMON_CFG_T;
+typedef PDAMON_PC_PAIR_RAW_V2_T PDAMON_PC_PAIR_RAW_T;
+typedef PDAMON_RAW_PER_CORE_V2_T PDAMON_RAW_PER_CORE_T;
+typedef PDAMON_STOP_SOURCE_V2 PDAMON_STOP_SOURCE;
+typedef PDAMON_EVENT_MASK_V2 PDAMON_EVENT_MASK;
+typedef PDAMON_EX_RAW_V2_T PDAMON_EX_RAW_T;
+typedef PDAMON_NEX_RAW_V2_T PDAMON_NEX_RAW_T;
+
+#define PDAMON_IA_PIPED_CNT PDAMON_IA_PIPED_CNT_V2
+#define PDAMON_DA_PIPED_CNT PDAMON_DA_PIPED_CNT_V2
+
+/**
+ * For exception flow
+ */
+#define PDAMON_EX_PIPED_PC_CNT (PDAMON_EX_PIPED_PC_CNT_V2)
+#define PDAMON_EX_PC_PAIR_CNT (PDAMON_EX_PC_PAIR_CNT_V2)
+#define PDAMON_EX_PIPED_DA_CNT (PDAMON_EX_PIPED_DA_CNT_V2)
+#define PDAMON_EX_DA_PAIR_CNT (PDAMON_EX_DA_PAIR_CNT_V2)
+
+/**
+ * A structure for backup raw data of RMPU violation case
+ */
+typedef struct {
+ PDAMON_RAW_PER_CORE_T raw[PDAMON_CORE_NUM];
+} PDAMON_RMPU_VIO_BACKUP, *PPDAMON_RMPU_VIO_BACKUP;
+
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to initialize PDAMON driver
+///
+/// \return PDAMON_OK if initialization is successful
+/// \return PDAMON_FAIL if initialization is failed.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_init(void);
+
+///////////////////////////////////////////////////////////////////////////////
+//// \brief This function is to configure PCMON module when leave dormant.
+///
+/// \return PDAMON_OK if configuration is successful
+/// \return PDAMON_FAIL if configuration is failed.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_configure_dormant_leave(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to configure PDAMON of cores.
+///
+/// \param [in] cfg A configuration structure.
+/// \param [in] core Core ID.
+/// \return PDAMON_OK if configuration is successful;
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_set_config(PDAMON_CFG_T *cfg, PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to setup PC match address.
+///
+/// \param [in] index Match index from 0 to 5.
+/// \param [in] addr Program counter to match.
+/// \param [in] enabled Set this match as enabled or not.
+/// \return PDAMON_OK if configuration is successful;
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_set_pc_match(kal_uint32 index, kal_uint32 addr, kal_bool enabled);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to setup PC match address.
+///
+/// \param [in] index Match index from 0 to 5.
+/// \param [in] addr Program counter to match.
+/// \param [in] mask Mask of Program counter to match.
+/// \param [in] enabled Set this match as enabled or not.
+/// \return PDAMON_OK if configuration is successful;
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_set_pc_match_and_mask(kal_uint32 index, kal_uint32 addr, kal_uint32 mask, kal_bool enabled);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to start PDAMON of cores.
+///
+/// \param [in] core Core definition. One of PDAMON_CORE_SEL.
+/// \return PDAMON_OK if starting capture is successful;
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_start_capture(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to stop PDAMON of cores.
+///
+/// \param [in] core Core definition. One of PDAMON_CORE_SEL.
+/// \return PDAMON_OK if stopping capture is successful;
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_stop_capture(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is to stop capturing of PDAMON via GCR control
+/// \param [in] core The core of PDAMON to be stopped
+///
+/// \return PDAMON_RET_OK if stop capturing of PDAMON via GCR is successful
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_gcr_stop_capture(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to select PDAMON of specific
+/// core.
+///
+/// \param [in] core Core definition. One of PDAMON_CORE_SEL.
+/// \return PDAMON_OK if core selection is successful;
+/// Not PDAMON_OK if failure.
+/// \note V2 : Not support.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_core_select(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to check if PDAMON is stopped.
+///
+/// \return KAL_TRUE if PDAMON is stopped. KAL_FALSE otherwise.
+/// \note V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_pdamon_is_stopped(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to check if PDAMON is stopped
+/// by specific sources.
+///
+/// \return KAL_TRUE if PDAMON is stopped. KAL_FALSE otherwise.
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_pdamon_is_stopped_by_sources(PDAMON_CORE_SEL core, PDAMON_STOP_SOURCE source);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PC record count of
+/// specific core.
+///
+/// \return PC record count.
+/// \note V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_pc_count(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PC record count of
+/// a specific TC of a core.
+///
+/// \return PC record count.
+/// \note V2 support only.
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_pc_count_by_tc(PDAMON_CORE_SEL core, PDAMON_TC_SEL tc);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get DA record count of
+/// specific core.
+///
+/// \return DA record count.
+/// \note V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_da_count(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get DA record count of
+/// a specific TC of a core.
+///
+/// \return DA record count.
+/// \note V2 support only.
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_da_count_by_tc(PDAMON_CORE_SEL core, PDAMON_TC_SEL tc);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PDAMON status value
+///
+/// \param [in/out] status Buffer to store status value
+/// \return PDAMON_OK if status value is returned from PDAMON.
+/// Not PDAMON_OK if failure.
+/// \note V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_get_status(PDAMON_CORE_SEL core, kal_uint32 *status);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PDAMON status value
+///
+/// \param [in/out] status Pointer to a buffer to store PC/DA record.
+/// \return PDAMON_OK if record is available from PDAMON.
+/// Not PDAMON_OK if failure.
+/// \note V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_get_raw(PDAMON_CORE_SEL core, PDAMON_RAW_PER_CORE_T *raw);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PC/DA record of specific
+/// core in excpetion flow
+///
+/// \param [in] core Core definition. One of PDAMON_CORE_SEL.
+/// \param [in] raw Pointer to a buffer to store PC/DA record.
+/// \return PDAMON_OK if record is available.
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_ex_get_raw(PDAMON_CORE_SEL core, PDAMON_EX_RAW_T *raw);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PC/DA record of specific
+/// core in nested excpetion flow
+///
+/// \param [in] core Core definition. One of PDAMON_CORE_SEL.
+/// \param [in] raw Pointer to a buffer to store PC/DA record.
+/// \return PDAMON_OK if record is available.
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_nex_get_raw(PDAMON_CORE_SEL core, PDAMON_NEX_RAW_T *raw);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to get PC/DA record of all
+/// cores in excpetion flow
+///
+/// \return PDAMON_OK if all record are available.
+/// Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_ex_get_all_raw();
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to mask/un-mask stop sources.
+///
+/// \param [in] source Stop source enumeration.
+/// Please refer to PCMON_STOP_SOURCE.
+/// \param [in] mask KAL_TRUE means mask stop source.
+/// KAL_FALSE means unmask stop source.
+///
+/// \return PCMON_OK if mask/un-mask operation is done.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_mask_stop_sources(PDAMON_CORE_SEL core, PDAMON_STOP_SOURCE sources, kal_bool mask);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief This function is used to backup PC/DA record and
+/// re-start PCMon.
+///
+/// \param [in] mcu KAL_TRUE means backup PC/DA record by MCU.
+/// KAL_FALSE means backup PC/DA record by GDMA.
+/// \param [in/out] data_ptr A pointer of buffer to store PC/DA record.
+/// \param [in] size Size of data_ptr in byes. This value must be 256.
+/// \param [in] mask KAL_TRUE means mask RMPU stop source after backup.
+/// KAL_FALSE means unmask RMPU stop source after backup.
+///
+/// \return PCMON_INVALID_ARGUMENT means \size if not the
+/// proper value.
+/// \return PCMON_OK if backup and restart are done.
+/// \return PCMON_FAIL if PCMon is not stopped. Backup can not
+/// be done.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_backup_and_restart(kal_bool mcu, PPDAMON_RMPU_VIO_BACKUP data_ptr, kal_bool mask);
+
+#endif // end of __DRV_PCMON_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_common.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_common.h
new file mode 100644
index 0000000..7199827
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_common.h
@@ -0,0 +1,212 @@
+#ifndef __DRV_PCMON_COMMON_H__
+#define __DRV_PCMON_COMMON_H__
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name PDAMON Common Preprocessor Directives
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * Number of PC pairs supported by PDAMON
+ */
+#if defined(__MD97__)
+ #define PDAMON_TC_NUM_PER_CORE (6)
+#else
+ #define PDAMON_TC_NUM_PER_CORE (4)
+#endif
+
+/**
+ * Number of PC pairs supported by PDAMON
+ */
+#if defined(__MD93__) || defined(__MD95_IS_2CORES__) || defined(__MD97_IS_2CORES__)
+ #define PDAMON_CORE_NUM (2)
+#elif defined(__MD95__)
+ #define PDAMON_CORE_NUM (3)
+#elif defined(__MD97__)
+ #define PDAMON_CORE_NUM (4)
+#else
+ #error "ERROR in drv_pcmon_common.h #define PDAMON_CORE_NUM"
+#endif
+/**
+ * Number of PC pairs supported by PDAMON
+ */
+#if defined(__MD97__)
+ #define PDAMON_IA_RAW_CAPACITY (56)
+#else
+ #define PDAMON_IA_RAW_CAPACITY (32)
+#endif
+
+/**
+ * Number of DA pairs supported by PDAMON
+ */
+#if defined(__MD97__)
+ #define PDAMON_DA_RAW_CAPACITY (56)
+#else
+ #define PDAMON_DA_RAW_CAPACITY (32)
+#endif
+
+/**
+ * Number of PC pairs in pipeline
+ */
+#define PDAMON_IA_PIPED_CNT_V2 (3)
+
+/**
+ * Number of DA pairs in pipeline
+ */
+#define PDAMON_DA_PIPED_CNT_V2 (1)
+
+/**
+ * Max. size of PDAMON_EX_RAW_T
+ */
+#if defined(__MD97__)
+ #define PDAMON_EX_RAW_SIZE (2048)
+#else
+ #define PDAMON_EX_RAW_SIZE (1024)
+#endif
+
+/**
+ * Max. size of PDAMON_NEX_RAW_T
+ */
+#define PDAMON_NEX_RAW_SIZE (512)
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name Type Definition
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+#if defined(__MD93__)
+#define PDAMON_DORMANT_TRACE_MAGIC 2454
+typedef enum {
+ PDAMON_DORMANT_ALREADY_STOPPED = 1,
+ PDAMON_DORMANT_NON_STOPPED,
+ PDAMON_DORMANT_STOPPED_BY_OTHERS,
+ PDAMON_DORMANT_STOPPED_BY_MAIN, // Main means the SPRAM_DEC_ERR... such default want to mask.
+} PDAMON_DORMANT_STEP;
+#endif /* defined(__MD93__) */
+
+/**
+ * Core ID enumeration
+ */
+typedef enum {
+ PDAMON_CORE_0 = 0, ///< Core-0 PDAMON
+ PDAMON_CORE_1, ///< Core-1 PDAMON
+#if defined(__MD95__) && !defined(__MD95_IS_2CORES__)
+ PDAMON_CORE_2, ///< Core-2 PDAMON
+#endif
+#if defined(__MD97__) && !defined(__MD97_IS_2CORES__)
+ PDAMON_CORE_2, ///< Core-2 PDAMON
+ PDAMON_CORE_3, ///< Core-3 PDAMON
+#endif
+ PDAMON_CORE_CNT,
+ PDAMON_CORE_ALL = PDAMON_CORE_CNT, ///< All core PDAMON
+} PDAMON_CORE_SEL;
+
+/**
+ * TC ID enumeration
+ */
+typedef enum {
+ PDAMON_TC_0 = 0,
+ PDAMON_TC_1,
+ PDAMON_TC_2,
+ PDAMON_TC_3,
+#if defined(__MD97__)
+ PDAMON_TC_4,
+ PDAMON_TC_5,
+#endif
+ PDAMON_TC_CNT,
+} PDAMON_TC_SEL;
+
+/**
+ * Return value of API
+ */
+typedef enum {
+ PDAMON_RET_OK, ///< Function call is successful
+ PDAMON_RET_FAIL, ///< Function call is failed
+ PDAMON_RET_UNSUPPORTED, ///< Function call is not supported
+ PDAMON_RET_INVALID_ARGUMENT, ///< Invalid arguments of function call
+ PDAMON_RET_ALREADY_STARTED, ///< PDAMon is started
+ PDAMON_RET_ALREADY_STOPPED, ///< PDAMon is stopped
+} PDAMON_RET;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name CODA Structures
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * A structure to describe tag register of DA pair
+ */
+typedef union {
+ struct {
+ kal_uint32 TC : 5;
+ kal_uint32 rsv_1 : 26;
+ kal_uint32 IDX : 1;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_DA_PAIR_TAG, *PPDAMON_DA_PAIR_TAG;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name API Structure
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * A structure to describe design version
+ */
+typedef struct PDAMON_VERSION_S {
+ kal_uint32 new_design : 1; ///< Gen92 new design or not
+ kal_uint32 reserved : 31; ///< Reserved
+} PDAMON_VERSION_T;
+
+/**
+ * A structure to describe raw data of PC pair in pipeline
+ */
+typedef struct PDAMON_PIPED_PC_PAIR_RAW_S {
+ kal_uint32 pc; ///< PC
+ kal_uint32 tc; ///< TC index
+ kal_uint32 frc; ///< FRC
+} PDAMON_PIPED_PC_PAIR_RAW_T;
+
+/**
+ * A structure to describe raw data of PC pair in pipeline
+ */
+typedef struct PDAMON_PIPED_PC_PAIR_RAW_ALIGNED_S {
+ kal_uint32 pc; ///< PC
+ kal_uint32 tc; ///< TC index
+ kal_uint32 frc; ///< FRC
+ kal_uint32 reserved;
+} PDAMON_PIPED_PC_PAIR_RAW_ALIGNED_T;
+
+/**
+ * A structure to describe raw data of DA pair
+ */
+typedef struct PDAMON_DA_PAIR_RAW_S {
+ kal_uint32 da; ///< Data address
+ kal_uint32 pc; ///< PC
+ kal_uint32 frc; ///< FRC
+ PDAMON_DA_PAIR_TAG tag; ///< Tag value
+} PDAMON_DA_PAIR_RAW_T;
+
+/**
+ * A structure to describe raw data of DA pair in pipeline
+ */
+typedef struct PDAMON_PIPED_DA_PAIR_RAW_S {
+ kal_uint32 pc; ///< PC
+ kal_uint32 da; ///< Data address
+ kal_uint32 tc; ///< TC index
+ kal_uint32 frc; ///< FRC
+} PDAMON_PIPED_DA_PAIR_RAW_T;
+
+///@}
+
+#endif // __DRV_PCMON_COMMON_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_ex.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_ex.h
new file mode 100644
index 0000000..df9e21f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_ex.h
@@ -0,0 +1,43 @@
+#ifndef __DRV_PCMON_EX_H__
+#define __DRV_PCMON_EX_H__
+
+.macro PDAMON_STOP_ASM
+.set noreorder
+#if defined(__MD93__)
+ lui $k1, 0xA021
+ addiu $k1, $k1, 0x800
+ lw $k0, 0($k1)
+ ins $k0, $zero, 0, 8
+ ori $k0, $k0, 0x22
+ sw $k0, 0($k1)
+ lw $k0, 0($k1)
+#elif defined(__MD95__)
+ lui $k1, 0xA021
+ addiu $k1, $k1, 0x1000
+ lw $k0, 0($k1)
+ ins $k0, $zero, 0, 12
+ ori $k0, $k0, 0x222
+ sw $k0, 0($k1)
+ lw $k0, 0($k1)
+#elif defined(__MD97__) && !defined(MT6297_IA)
+ lui $k1, 0xA029
+ addiu $k1, $k1, 0x1C00
+ lw $k0, 0($k1)
+ ins $k0, $zero, 0, 16
+ li $k0, 0x2222
+ sw $k0, 0($k1)
+ lw $k0, 0($k1)
+#elif defined(__MD97__) && defined(MT6297_IA)
+ lui $k1, 0xA021
+ addiu $k1, $k1, 0x2000
+ lw $k0, 0($k1)
+ ins $k0, $zero, 0, 16
+ li $k0, 0x2222
+ sw $k0, 0($k1)
+ lw $k0, 0($k1)
+#else
+ #error "ERROR in drv_pcmon_ex.h, w/o define macro PDAMON_STOP_ASM"
+#endif
+.endm PDAMON_STOP_ASM
+
+#endif // __DRV_PCMON_EX_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_init.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_init.h
new file mode 100644
index 0000000..883b81e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_init.h
@@ -0,0 +1,124 @@
+#ifndef __DRV_PCMON_INIT_H__
+#define __DRV_PCMON_INIT_H__
+
+#if defined(__MD97__)
+#define PC_NULL_ADDR 0x6
+#define PC_NULL_MASK 0xFFFFF804
+#else
+#define PC_NULL_ADDR 0x0
+#define PC_NULL_MASK 0xFFFFF800
+#endif
+
+#define PC_FUNC_MASK 0xFFFFFFF0
+#define PC_MATCH_DISABLE 0x1
+
+#if defined(__MD93__)
+#define PC_MATCH_3_ADDR 0xA021088C
+#elif defined(__MD95__)
+#define PC_MATCH_3_ADDR 0xA021108C
+#elif defined(__MD97__) && defined(MT6297_IA)
+#define PC_MATCH_3_ADDR 0xA02120CC
+#elif defined(__MD97__) && !defined(MT6297_IA)
+#define PC_MATCH_0_ADDR 0xA0291CC0
+#define PC_MATCH_0_MASK 0xA0291CD8
+#define PC_MATCH_1_ADDR 0xA0291CC4
+#define PC_MATCH_1_MASK 0xA0291CDC
+#define PC_MATCH_2_ADDR 0xA0291CC8
+#define PC_MATCH_2_MASK 0xA0291CE0
+#define PC_MATCH_3_ADDR 0xA0291CCC
+#define PC_MATCH_3_MASK 0xA0291CE4
+#else
+ #error "ERROR in drv_pcmon_init.h #define PC_MATCH_3_ADDR"
+#endif
+
+.extern general_ex_vector
+.extern NMI_handler
+.extern INT_TEMP_general_ex_vector
+
+.macro PDAMON_CONFIG
+.set push
+.set nomips16
+#if !defined(__MD97__)
+PDAMON_PreSet_NULL_Protection:
+ la t1, PC_MATCH_3_ADDR
+ li t0, PC_NULL_ADDR
+ sw t0, 0(t1)
+ lw t0, 0(t1)
+#if defined(__MD93__)
+PDAMON_PreSet_Event_Mask:
+ lui t1, 0xA021
+ addiu t1, t1, 0x800
+ lw t0, 0(t1)
+ ins t0, zero, 0, 8
+ ori t0, t0, 0x22
+ sw t0, 0(t1)
+ lw t0, 0(t1)
+ lw t0, 0x10(t1)
+ ori t0, t0, 0x200
+ sw t0, 0x10(t1)
+ lw t0, 0x10(t1)
+ lw t0, 0(t1)
+ ins t0, zero, 0, 8
+ ori t0, t0, 0x11
+ sw t0, 0(t1)
+ lw t0, 0(t1)
+#endif
+#else //defined(__MD97__)
+PDAMON_PreSet_NULL_Protection:
+ // Set PC MATCH3
+ li $a1, PC_MATCH_3_ADDR
+ li $a0, PC_MATCH_DISABLE
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_3_MASK
+ li $a0, PC_NULL_MASK
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_3_ADDR
+ li $a0, PC_NULL_ADDR
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ // Set PC MATCH0
+ li $a1, PC_MATCH_0_ADDR
+ li $a0, PC_MATCH_DISABLE
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_0_MASK
+ li $a0, PC_FUNC_MASK
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_0_ADDR
+ li $a0, general_ex_vector
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ // Set PC MATCH1
+ li $a1, PC_MATCH_1_ADDR
+ li $a0, PC_MATCH_DISABLE
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_1_MASK
+ li $a0, PC_FUNC_MASK
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_1_ADDR
+ li $a0, NMI_handler
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ // Set PC MATCH2
+ li $a1, PC_MATCH_2_ADDR
+ li $a0, PC_MATCH_DISABLE
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_2_MASK
+ li $a0, PC_FUNC_MASK
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+ li $a1, PC_MATCH_2_ADDR
+ li $a0, INT_TEMP_general_ex_vector
+ sw $a0, 0($a1)
+ lw $a0, 0($a1)
+#endif //!defined(__MD97__)
+.set pop
+.endm PDAMON_CONFIG
+
+#endif // __DRV_PCMON_INIT_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_v2.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_v2.h
new file mode 100644
index 0000000..038c3eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_v2.h
@@ -0,0 +1,542 @@
+#ifndef __DRV_PCMON_V2_H__
+#define __DRV_PCMON_V2_H__
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name V2 Preprocessor Directives
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * Number of PC match registers
+ */
+#define PDAMON_PC_MATCH_CNT (6)
+
+/**
+ * Number of each TC's SPRAM size in EX
+ */
+#define PDAMON_EX_TC0_IA_MARGIN (0)
+#define PDAMON_EX_TC1_IA_MARGIN (1)
+#define PDAMON_EX_TC2_IA_MARGIN (1)
+#define PDAMON_EX_TC3_IA_MARGIN (1)
+#if defined(__MD97__)
+ #define PDAMON_EX_TC4_IA_MARGIN (1)
+ #define PDAMON_EX_TC5_IA_MARGIN (1)
+ #define PDAMON_EX_TC_TOTAL_IA_PAIR (PDAMON_IA_RAW_CAPACITY - PDAMON_EX_TC0_IA_MARGIN - PDAMON_EX_TC1_IA_MARGIN - PDAMON_EX_TC2_IA_MARGIN - PDAMON_EX_TC3_IA_MARGIN - PDAMON_EX_TC4_IA_MARGIN - PDAMON_EX_TC5_IA_MARGIN)
+#else
+ #define PDAMON_EX_TC_TOTAL_IA_PAIR (PDAMON_IA_RAW_CAPACITY - PDAMON_EX_TC0_IA_MARGIN - PDAMON_EX_TC1_IA_MARGIN - PDAMON_EX_TC2_IA_MARGIN - PDAMON_EX_TC3_IA_MARGIN)
+#endif
+#define PDAMON_EX_TC0_DA_MARGIN (1)
+#define PDAMON_EX_TC1_DA_MARGIN (1)
+#define PDAMON_EX_TC2_DA_MARGIN (1)
+#define PDAMON_EX_TC3_DA_MARGIN (1)
+#if defined(__MD97__)
+ #define PDAMON_EX_TC4_DA_MARGIN (1)
+ #define PDAMON_EX_TC5_DA_MARGIN (1)
+ #define PDAMON_EX_TC_TOTAL_DA_PAIR (PDAMON_DA_RAW_CAPACITY - PDAMON_EX_TC0_DA_MARGIN - PDAMON_EX_TC1_DA_MARGIN - PDAMON_EX_TC2_DA_MARGIN - PDAMON_EX_TC3_DA_MARGIN - PDAMON_EX_TC4_DA_MARGIN - PDAMON_EX_TC5_DA_MARGIN)
+#else
+#define PDAMON_EX_TC_TOTAL_DA_PAIR (PDAMON_DA_RAW_CAPACITY - PDAMON_EX_TC0_DA_MARGIN - PDAMON_EX_TC1_DA_MARGIN - PDAMON_EX_TC2_DA_MARGIN - PDAMON_EX_TC3_DA_MARGIN)
+#endif
+
+/**
+ * Number of each TC's SPRAM size in NEX
+ */
+#define PDAMON_NEX_TC0_IA_MARGIN (1)
+#define PDAMON_NEX_TC1_IA_MARGIN (1)
+#define PDAMON_NEX_TC2_IA_MARGIN (1)
+#define PDAMON_NEX_TC3_IA_MARGIN (2)
+#if defined(__MD97__)
+ #define PDAMON_NEX_TC4_IA_MARGIN (1)
+ #define PDAMON_NEX_TC5_IA_MARGIN (2)
+ #define PDAMON_NEX_TC_TOTAL_IA_PAIR (PDAMON_IA_RAW_CAPACITY - PDAMON_NEX_TC0_IA_MARGIN - PDAMON_NEX_TC1_IA_MARGIN - PDAMON_NEX_TC2_IA_MARGIN - PDAMON_NEX_TC3_IA_MARGIN - PDAMON_NEX_TC4_IA_MARGIN - PDAMON_NEX_TC5_IA_MARGIN)
+#else
+ #define PDAMON_NEX_TC_TOTAL_IA_PAIR (PDAMON_IA_RAW_CAPACITY - PDAMON_NEX_TC0_IA_MARGIN - PDAMON_NEX_TC1_IA_MARGIN - PDAMON_NEX_TC2_IA_MARGIN - PDAMON_NEX_TC3_IA_MARGIN)
+#endif
+
+/**
+ * For exception flow
+ */
+#define PDAMON_EX_PIPED_PC_CNT_V2 (PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2)
+#define PDAMON_EX_PC_PAIR_CNT_V2 (PDAMON_EX_TC_TOTAL_IA_PAIR)
+#define PDAMON_EX_PIPED_DA_CNT_V2 (PDAMON_DA_PIPED_CNT_V2)
+#define PDAMON_EX_DA_PAIR_CNT_V2 (PDAMON_EX_TC_TOTAL_DA_PAIR)
+#define PDAMON_EX_PIPED_FRC_CNT_V2 (PDAMON_TC_NUM_PER_CORE)
+#define PDAMON_NEX_PC_PAIR_CNT_V2 (PDAMON_NEX_TC_TOTAL_IA_PAIR)
+#define PDAMON_NEX_PIPED_FRC_CNT_V2 (PDAMON_EX_PIPED_FRC_CNT_V2 - 1) // -1 for insufficient room
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name Type Definition
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * Stop source of PCMon
+ */
+typedef enum {
+ PDAMON_SRC_NONE = 0,
+ PDAMON_SRC_MDMCU_BUSMON = 0x1,
+ PDAMON_SRC_MDINFRA_BUSMON = 0x2,
+ PDAMON_SRC_MD_BUSERR = 0x4,
+ PDAMON_SRC_BUS_MPU = 0x8,
+ PDAMON_SRC_RGU = 0x10,
+ PDAMON_SRC_RMPU = 0x20,
+ PDAMON_SRC_CTI = 0x40,
+ PDAMON_SRC_CMERR = 0x80,
+#if defined(__MD93__)
+ PDAMON_SRC_SPRAM_DECERR = 0x200,
+#endif
+ PDAMON_SRC_MDMCU_DECERR = 0x400,
+ PDAMON_SRC_GCR = 0x800,
+ PDAMON_SRC_SW = 0x1000,
+ PDAMON_SRC_PC0_MATCH = 0x2000,
+ PDAMON_SRC_PC1_MATCH = 0x4000,
+ PDAMON_SRC_PC2_MATCH = 0x8000,
+ PDAMON_SRC_PC3_MATCH = 0x10000,
+ PDAMON_SRC_PC4_MATCH = 0x20000,
+ PDAMON_SRC_PC5_MATCH = 0x40000,
+} PDAMON_STOP_SOURCE_V2;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name CODA Structures
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+#if defined(__MD95__) || defined(__MD97__)
+/**
+ * A structure to describe first stop event register
+ */
+typedef union {
+ struct {
+ kal_uint32 MDMCU_BUSMON : 1;
+ kal_uint32 MDINFRA_BUSMON : 1;
+ kal_uint32 MD_BUS_ERR : 1;
+ kal_uint32 BUSMPU : 1;
+ kal_uint32 RGU : 1;
+ kal_uint32 RMPU : 1;
+ kal_uint32 CTI : 1;
+ kal_uint32 CM_ERR : 1;
+ kal_uint32 rsv_1 : 2;
+ kal_uint32 MDMCU_DECERR : 1;
+ kal_uint32 GCR : 1;
+ kal_uint32 SW : 1;
+ kal_uint32 PC_MATCH_0 : 1;
+ kal_uint32 PC_MATCH_1 : 1;
+ kal_uint32 PC_MATCH_2 : 1;
+ kal_uint32 PC_MATCH_3 : 1;
+ kal_uint32 PC_MATCH_4 : 1;
+ kal_uint32 PC_MATCH_5 : 1;
+ kal_uint32 rsv_2 : 13;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_FIRST_STOP_EVENT, *PPDAMON_FIRST_STOP_EVENT;
+
+/**
+ * A structure to describe event mask register
+ */
+typedef union {
+ struct {
+ kal_uint32 MDMCU_BUSMON : 1;
+ kal_uint32 MDINFRA_BUSMON : 1;
+ kal_uint32 MD_BUS_ERR : 1;
+ kal_uint32 BUSMPU : 1;
+ kal_uint32 RGU : 1;
+ kal_uint32 RMPU : 1;
+ kal_uint32 CTI : 1;
+ kal_uint32 CM_ERR : 1;
+ kal_uint32 rsv_1 : 2;
+ kal_uint32 MDMCU_DECERR : 1;
+ kal_uint32 GCR : 1;
+ kal_uint32 SW : 1;
+ kal_uint32 PC_MATCH_0 : 1;
+ kal_uint32 PC_MATCH_1 : 1;
+ kal_uint32 PC_MATCH_2 : 1;
+ kal_uint32 PC_MATCH_3 : 1;
+ kal_uint32 PC_MATCH_4 : 1;
+ kal_uint32 PC_MATCH_5 : 1;
+ kal_uint32 rsv_2 : 13;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_EVENT_MASK_V2, *PPDAMON_EVENT_MASK_V2;
+
+/**
+ * A structure to describe record status register
+ */
+typedef union {
+ struct {
+ kal_uint32 MDMCU_BUSMON : 1;
+ kal_uint32 MDINFRA_BUSMON : 1;
+ kal_uint32 MD_BUS_ERR : 1;
+ kal_uint32 BUSMPU : 1;
+ kal_uint32 RGU : 1;
+ kal_uint32 RMPU : 1;
+ kal_uint32 CTI : 1;
+ kal_uint32 CM_ERR : 1;
+ kal_uint32 rsv_1 : 2;
+ kal_uint32 MDMCU_DECERR : 1;
+ kal_uint32 GCR : 1;
+ kal_uint32 SW : 1;
+ kal_uint32 PC_MATCH_0 : 1;
+ kal_uint32 PC_MATCH_1 : 1;
+ kal_uint32 PC_MATCH_2 : 1;
+ kal_uint32 PC_MATCH_3 : 1;
+ kal_uint32 PC_MATCH_4 : 1;
+ kal_uint32 PC_MATCH_5 : 1;
+ kal_uint32 rsv_2 : 12;
+ kal_uint32 STOPPED : 1;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_RECORD_STS_V2, *PPDAMON_RECORD_STS_V2;
+
+#elif defined(__MD93__)
+/**
+ * A structure to describe event mask register
+ */
+typedef union {
+ struct {
+ kal_uint32 MDMCU_BUSMON : 1;
+ kal_uint32 MDINFRA_BUSMON : 1;
+ kal_uint32 MD_BUS_ERR : 1;
+ kal_uint32 BUSMPU : 1;
+ kal_uint32 RGU : 1;
+ kal_uint32 RMPU : 1;
+ kal_uint32 CTI : 1;
+ kal_uint32 CM_ERR : 1;
+ kal_uint32 rsv_1 : 1;
+ kal_uint32 SPRAM_DECERR : 1;
+ kal_uint32 MDMCU_DECERR : 1;
+ kal_uint32 GCR : 1;
+ kal_uint32 SW : 1;
+ kal_uint32 PC_MATCH_0 : 1;
+ kal_uint32 PC_MATCH_1 : 1;
+ kal_uint32 PC_MATCH_2 : 1;
+ kal_uint32 PC_MATCH_3 : 1;
+ kal_uint32 PC_MATCH_4 : 1;
+ kal_uint32 PC_MATCH_5 : 1;
+ kal_uint32 rsv_2 : 13;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_EVENT_MASK_V2, *PPDAMON_EVENT_MASK_V2;
+
+/**
+ * A structure to describe record status register
+ */
+typedef union {
+ struct {
+ kal_uint32 MDMCU_BUSMON : 1;
+ kal_uint32 MDINFRA_BUSMON : 1;
+ kal_uint32 MD_BUS_ERR : 1;
+ kal_uint32 BUSMPU : 1;
+ kal_uint32 RGU : 1;
+ kal_uint32 RMPU : 1;
+ kal_uint32 CTI : 1;
+ kal_uint32 CM_ERR : 1;
+ kal_uint32 rsv_1 : 1;
+ kal_uint32 SPRAM_DECERR : 1;
+ kal_uint32 MDMCU_DECERR : 1;
+ kal_uint32 GCR : 1;
+ kal_uint32 SW : 1;
+ kal_uint32 PC_MATCH_0 : 1;
+ kal_uint32 PC_MATCH_1 : 1;
+ kal_uint32 PC_MATCH_2 : 1;
+ kal_uint32 PC_MATCH_3 : 1;
+ kal_uint32 PC_MATCH_4 : 1;
+ kal_uint32 PC_MATCH_5 : 1;
+ kal_uint32 rsv_2 : 12;
+ kal_uint32 STOPPED : 1;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_RECORD_STS_V2, *PPDAMON_RECORD_STS_V2;
+#endif
+
+/**
+ * A structure to describe SRAM wrap status
+ */
+typedef union {
+ struct {
+ kal_uint32 TC0_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_1 : 2;
+ kal_uint32 TC0_SRAM_WRAP : 1;
+ kal_uint32 TC1_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_2 : 2;
+ kal_uint32 TC1_SRAM_WRAP : 1;
+ kal_uint32 TC2_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_3 : 2;
+ kal_uint32 TC2_SRAM_WRAP : 1;
+ kal_uint32 TC3_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_4 : 2;
+ kal_uint32 TC3_SRAM_WRAP : 1;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_SRAM_WRAP_STS, *PPDAMON_SRAM_WRAP_STS;
+
+typedef union {
+ struct {
+ kal_uint32 TC4_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_1 : 2;
+ kal_uint32 TC4_SRAM_WRAP : 1;
+ kal_uint32 TC5_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_2 : 2;
+ kal_uint32 TC5_SRAM_WRAP : 1;
+ kal_uint32 TC6_SRAM_NON_WRAP_CNT: 5;
+ kal_uint32 rsv_3 : 2;
+ kal_uint32 TC6_SRAM_WRAP : 1;
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_SRAM_WRAP_STS_EXT, *PPDAMON_SRAM_WRAP_STS_EXT;
+
+
+/**
+ * A structure to describe "tag" fields of PC raw data
+ */
+typedef union {
+ struct {
+#if defined(__MD97__) && !defined(APOLLO)
+ kal_uint32 TC : 4; //0~3
+ kal_uint32 rsv_1 : 4; //4~7
+ kal_uint32 DA_TAG : 6; //8~13
+ kal_uint32 rsv_2 : 2; //14~15
+ kal_uint32 SEQ_COUNT : 11; //16~26
+ kal_uint32 rsv_3 : 2; //27~28
+ kal_uint32 DST_DUAL_ISSUE : 1; //29
+ kal_uint32 SRC_DUAL_ISSUE : 1; //30
+ kal_uint32 IDX : 1; //31
+#else
+ kal_uint32 TC : 5;
+ kal_uint32 rsv_1 : 11;
+ kal_uint32 DA_TAG : 5;
+ kal_uint32 rsv_2 : 10;
+ kal_uint32 IDX : 1;
+#endif
+ } Bits;
+ kal_uint32 Raw;
+} PDAMON_PC_PAIR_TAG_V2, *PPDAMON_PC_PAIR_TAG_V2;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name API Structure
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * A structure to describe configuration
+ */
+typedef struct PDAMON_CFG_V2_S {
+ PDAMON_STOP_SOURCE_V2 stop_src_mask; ///< Stop source mask
+} PDAMON_CFG_V2_T;
+
+/**
+ * A structure to describe raw data of PC pair
+ */
+typedef struct PDAMON_PC_PAIR_RAW_V2_S {
+ kal_uint32 src; ///< Source PC
+ kal_uint32 dst; ///< Destination PC
+ kal_uint32 frc; ///< FRC
+ PDAMON_PC_PAIR_TAG_V2 tag; ///< Tag value
+} PDAMON_PC_PAIR_RAW_V2_T;
+
+/**
+ * A structure to describe PC and DA raw data for exception
+ * Capacity is 1024 or 2048 bytes
+ */
+#if defined(__MD97__)
+#define PDAMON_EX_USED_V2 (sizeof(PDAMON_VERSION_T) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(PDAMON_SRAM_WRAP_STS_EXT) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(PDAMON_SRAM_WRAP_STS_EXT) + \
+ sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+ sizeof(kal_uint32)*PDAMON_EX_PIPED_FRC_CNT_V2 + \
+ sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_EX_PC_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_PIPED_DA_PAIR_RAW_T)*PDAMON_EX_PIPED_DA_CNT_V2 + \
+ sizeof(PDAMON_DA_PAIR_RAW_T)*PDAMON_EX_DA_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_RECORD_STS_V2) + \
+ sizeof(PDAMON_FIRST_STOP_EVENT) + \
+ sizeof(PDAMON_FIRST_STOP_EVENT) + \
+ sizeof(kal_uint32))
+#elif defined(__MD95__)
+#define PDAMON_EX_USED_V2 (sizeof(PDAMON_VERSION_T) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+ sizeof(kal_uint32)*PDAMON_EX_PIPED_FRC_CNT_V2 + \
+ sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_EX_PC_PAIR_CNT_V2 + \
+ sizeof(PDAMON_PIPED_DA_PAIR_RAW_T)*PDAMON_EX_PIPED_DA_CNT_V2 + \
+ sizeof(PDAMON_DA_PAIR_RAW_T)*PDAMON_EX_DA_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_RECORD_STS_V2) + \
+ sizeof(PDAMON_FIRST_STOP_EVENT) + \
+ sizeof(kal_uint32))
+#elif defined(__MD93__)
+#define PDAMON_EX_USED_V2 (sizeof(PDAMON_VERSION_T) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+ sizeof(kal_uint32)*PDAMON_EX_PIPED_FRC_CNT_V2 + \
+ sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_EX_PC_PAIR_CNT_V2 + \
+ sizeof(PDAMON_PIPED_DA_PAIR_RAW_T)*PDAMON_EX_PIPED_DA_CNT_V2 + \
+ sizeof(PDAMON_DA_PAIR_RAW_T)*PDAMON_EX_DA_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_RECORD_STS_V2) + \
+ sizeof(kal_uint32))
+#endif
+typedef struct PDAMON_EX_RAW_V2_S {
+ PDAMON_VERSION_T version;
+ PDAMON_SRAM_WRAP_STS pc_wrap;
+#if defined(__MD97__)
+ PDAMON_SRAM_WRAP_STS_EXT pc_wrap_ext;
+#endif
+ PDAMON_SRAM_WRAP_STS da_wrap;
+#if defined(__MD97__)
+ PDAMON_SRAM_WRAP_STS_EXT da_wrap_ext;
+#endif
+ kal_uint32 piped_pc[PDAMON_TC_NUM_PER_CORE][PDAMON_IA_PIPED_CNT_V2];
+ kal_uint32 piped_pc_frc[PDAMON_EX_PIPED_FRC_CNT_V2];
+ PDAMON_PC_PAIR_RAW_V2_T pc[PDAMON_EX_PC_PAIR_CNT_V2];
+#if (defined(__MD97__) && !defined(MT6297_IA))
+ kal_uint32 piped_pc_dual_issue;
+#endif
+ PDAMON_PIPED_DA_PAIR_RAW_T piped_da[PDAMON_EX_PIPED_DA_CNT_V2];
+ PDAMON_DA_PAIR_RAW_T da[PDAMON_EX_DA_PAIR_CNT_V2];
+ kal_uint32 last_tc_id;
+ PDAMON_RECORD_STS_V2 record_sts;
+#if defined(__MD95__) || defined(__MD97__)
+ PDAMON_FIRST_STOP_EVENT first_stop;
+#endif
+#if defined(__MD97__)
+ PDAMON_FIRST_STOP_EVENT first_stop_frc;
+#endif
+ kal_uint32 sw_trig;
+ kal_uint32 pad[(PDAMON_EX_RAW_SIZE - PDAMON_EX_USED_V2)/sizeof(kal_uint32)];
+} PDAMON_EX_RAW_V2_T;
+
+/**
+ * A structure to describe PC and DA raw data for nested exception
+ * Capacity is 512 bytes
+ */
+#if defined(__MD97__)
+#define PDAMON_NEX_USED_V2 (sizeof(PDAMON_VERSION_T) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(PDAMON_SRAM_WRAP_STS_EXT) + \
+ sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+ sizeof(kal_uint32)*PDAMON_NEX_PIPED_FRC_CNT_V2 + \
+ sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_NEX_PC_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_RECORD_STS_V2) + \
+ sizeof(PDAMON_FIRST_STOP_EVENT) + \
+ sizeof(PDAMON_FIRST_STOP_EVENT) + \
+ sizeof(kal_uint32))
+#elif defined(__MD95__)
+#define PDAMON_NEX_USED_V2 (sizeof(PDAMON_VERSION_T) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+ sizeof(kal_uint32)*PDAMON_NEX_PIPED_FRC_CNT_V2 + \
+ sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_NEX_PC_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_RECORD_STS_V2) + \
+ sizeof(PDAMON_FIRST_STOP_EVENT) + \
+ sizeof(kal_uint32))
+#elif defined(__MD93__)
+#define PDAMON_NEX_USED_V2 (sizeof(PDAMON_VERSION_T) + \
+ sizeof(PDAMON_SRAM_WRAP_STS) + \
+ sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+ sizeof(kal_uint32)*PDAMON_NEX_PIPED_FRC_CNT_V2 + \
+ sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_NEX_PC_PAIR_CNT_V2 + \
+ sizeof(kal_uint32) + \
+ sizeof(PDAMON_RECORD_STS_V2) + \
+ sizeof(kal_uint32))
+#endif
+typedef struct PDAMON_NEX_RAW_V2_S {
+ PDAMON_VERSION_T version;
+ PDAMON_SRAM_WRAP_STS pc_wrap;
+#if defined(__MD97__)
+ PDAMON_SRAM_WRAP_STS_EXT pc_wrap_ext;
+#endif
+ kal_uint32 piped_pc[PDAMON_TC_NUM_PER_CORE][PDAMON_IA_PIPED_CNT_V2];
+ kal_uint32 piped_pc_frc[PDAMON_NEX_PIPED_FRC_CNT_V2];
+ PDAMON_PC_PAIR_RAW_V2_T pc[PDAMON_NEX_PC_PAIR_CNT_V2];
+ kal_uint32 last_tc_id;
+ PDAMON_RECORD_STS_V2 record_sts;
+#if defined(__MD95__) || defined(__MD97__)
+ PDAMON_FIRST_STOP_EVENT first_stop;
+#endif
+#if defined(__MD97__)
+ PDAMON_FIRST_STOP_EVENT first_stop_frc;
+#endif
+ kal_uint32 sw_trig;
+// kal_uint32 pad[(PDAMON_NEX_RAW_SIZE - PDAMON_NEX_USED_V2)/sizeof(kal_uint32)];
+} PDAMON_NEX_RAW_V2_T;
+
+/**
+ * A structure to describe PC/DA history of a core
+ */
+typedef struct PDAMON_RAW_PER_CORE_V2_S {
+ PDAMON_SRAM_WRAP_STS pc_wrap;
+#if defined(__MD97__)
+ PDAMON_SRAM_WRAP_STS_EXT pc_wrap_ext;
+#endif
+ kal_uint32 last_tc_id;
+ kal_uint32 rsv_1[2];
+ PDAMON_PC_PAIR_RAW_V2_T pc[PDAMON_IA_RAW_CAPACITY];
+ PDAMON_PIPED_PC_PAIR_RAW_ALIGNED_T piped_pc[PDAMON_TC_NUM_PER_CORE][PDAMON_IA_PIPED_CNT_V2];
+#if (defined(__MD97__) && !defined(MT6297_IA))
+ kal_uint32 piped_pc_dual_issue;
+#endif
+ PDAMON_SRAM_WRAP_STS da_wrap;
+#if defined(__MD97__)
+ PDAMON_SRAM_WRAP_STS_EXT da_wrap_ext;
+#endif
+ kal_uint32 rsv_2[3];
+ PDAMON_DA_PAIR_RAW_T da[PDAMON_IA_RAW_CAPACITY];
+ PDAMON_PIPED_DA_PAIR_RAW_T piped_da[PDAMON_DA_PIPED_CNT_V2];
+ PDAMON_RECORD_STS_V2 record_sts;
+#if defined(__MD95__) || defined(__MD97__)
+ PDAMON_FIRST_STOP_EVENT first_stop;
+#endif
+#if defined(__MD97__)
+ PDAMON_FIRST_STOP_EVENT first_stop_frc;
+#endif
+ kal_uint32 sw_trig;
+ kal_uint32 flag;
+ kal_uint32 rsv_3[1];
+} PDAMON_RAW_PER_CORE_V2_T;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name Exception Macros
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+#define EX_PIPED_PC_PC(ptr, index) ((ptr)->piped_pc[(index)/(PDAMON_IA_PIPED_CNT_V2)][(index)%(PDAMON_IA_PIPED_CNT_V2)])
+#define EX_PIPED_PC_TC(ptr, index) ((index)/(PDAMON_IA_PIPED_CNT_V2))
+#define EX_PIPED_PC_FRC(ptr, index) ((ptr)->piped_pc_frc[(index)/(PDAMON_IA_PIPED_CNT_V2)])
+
+#define EX_PC_PAIR_SRC(ptr, index) ((ptr)->pc[(index)].src)
+#define EX_PC_PAIR_DST(ptr, index) ((ptr)->pc[(index)].dst)
+#define EX_PC_PAIR_FRC(ptr, index) ((ptr)->pc[(index)].frc)
+#define EX_PC_PAIR_TAG(ptr, index) ((ptr)->pc[(index)].tag.Raw)
+
+#define EX_PIPED_DA_PC(ptr, index) ((ptr)->piped_da[(index)].pc)
+#define EX_PIPED_DA_DA(ptr, index) ((ptr)->piped_da[(index)].da)
+#define EX_PIPED_DA_TC(ptr, index) ((ptr)->piped_da[(index)].tc)
+#define EX_PIPED_DA_FRC(ptr, index) ((ptr)->piped_da[(index)].frc)
+
+#define EX_DA_PAIR_PC(ptr, index) ((ptr)->da[(index)].pc)
+#define EX_DA_PAIR_DA(ptr, index) ((ptr)->da[(index)].da)
+#define EX_DA_PAIR_FRC(ptr, index) ((ptr)->da[(index)].frc)
+#define EX_DA_PAIR_TAG(ptr, index) ((ptr)->da[(index)].tag.Raw)
+
+///@}
+
+#endif // __DRV_PCMON_V2_H__