[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/regbase/reg_base_esl.h b/mcu/interface/driver/regbase/reg_base_esl.h
new file mode 100644
index 0000000..cc2cde6
--- /dev/null
+++ b/mcu/interface/driver/regbase/reg_base_esl.h
@@ -0,0 +1,86 @@
+#ifndef __REG_BASE_ESL_H__
+#define __REG_BASE_ESL_H__
+
+#if defined(MT6763) || defined(__MD97__)
+#if defined(__MD97__)
+ #define ESL_REG_BANK 0xD0000000
+#endif
+
+ #undef BASE_ADDR_MDCIRQ
+ #undef BASE_MADDR_MDCIRQ
+
+ #undef BASE_NADDR_MML2_QP_APB
+ #undef BASE_NADDR_MML2_QP_MEM
+ #undef BASE_NADDR_MML2_META_APB
+ #undef BASE_NADDR_MML2_META_MEM
+ #undef BASE_NADDR_MML2_VRB_MANAGER
+ #undef BASE_NADDR_MML2_MMU
+ #undef BASE_NADDR_MML2_DMA_RD
+ #undef BASE_NADDR_MML2_DMA_WR
+ #undef BASE_NADDR_MML2_LHIF
+ #undef BASE_NADDR_MML2_CIPHER
+ #undef BASE_NADDR_MML2_DL_LMAC
+ #undef BASE_NADDR_MML2_HARQ_CTRL
+ #undef BASE_NADDR_MML2_SRAM_WRAP
+ #undef BASE_NADDR_MML2_CFG_TOP
+ #undef BASE_NADDR_MML2_BYC
+ #undef BASE_MADDR_MML2_QP_APB
+ #undef BASE_MADDR_MML2_QP_MEM
+ #undef BASE_MADDR_MML2_META_APB
+ #undef BASE_MADDR_MML2_META_MEM
+ #undef BASE_MADDR_MML2_VRB_MANAGER
+ #undef BASE_MADDR_MML2_MMU
+ #undef BASE_MADDR_MML2_DMA_RD
+ #undef BASE_MADDR_MML2_DMA_WR
+ #undef BASE_MADDR_MML2_LHIF
+ #undef BASE_MADDR_MML2_CIPHER
+ #undef BASE_MADDR_MML2_DL_LMAC
+ #undef BASE_MADDR_MML2_HARQ_CTRL
+ #undef BASE_MADDR_MML2_SRAM_WRAP
+ #undef BASE_MADDR_MML2_CFG_TOP
+ #undef BASE_MADDR_MML2_BYC
+
+ #define BASE_ADDR_MDCIRQ (ESL_REG_BANK + 0x7000000)
+ #define BASE_MADDR_MDCIRQ (ESL_REG_BANK + 0x7000000)
+
+ #define BASE_USCOUNTER (ESL_REG_BANK + 0x1000000)
+ #define BASE_GLOBAL_TS (ESL_REG_BANK + 0x1000010)
+
+ #define BASE_MADDR_MML2_QP_APB (ESL_REG_BANK + 0x0600000)
+ #define BASE_MADDR_MML2_QP_MEM (ESL_REG_BANK + 0x0600800)
+ #define BASE_MADDR_MML2_META_APB (ESL_REG_BANK + 0x0601000)
+ #define BASE_MADDR_MML2_META_MEM (ESL_REG_BANK + 0x0601800)
+ #define BASE_MADDR_MML2_VRB_MANAGER (ESL_REG_BANK + 0x0602000)
+ #define BASE_MADDR_MML2_MMU (ESL_REG_BANK + 0x0603000)
+ #define BASE_MADDR_MML2_DMA_RD (ESL_REG_BANK + 0x0604000)
+ #define BASE_MADDR_MML2_DMA_WR (ESL_REG_BANK + 0x0605000)
+ #define BASE_MADDR_MML2_LHIF (ESL_REG_BANK + 0x0606000)
+ #define BASE_MADDR_MML2_CIPHER (ESL_REG_BANK + 0x0607000)
+ #define BASE_MADDR_MML2_DL_LMAC (ESL_REG_BANK + 0x0608000)
+ #define BASE_MADDR_MML2_HARQ_CTRL (ESL_REG_BANK + 0x0609000)
+ #define BASE_MADDR_MML2_SRAM_WRAP (ESL_REG_BANK + 0x060A000)
+ #define BASE_MADDR_MML2_CFG_TOP (ESL_REG_BANK + 0x060B000)
+ #define BASE_MADDR_MML2_BYC (ESL_REG_BANK + 0x060C000)
+
+ #define BASE_NADDR_MML2_QP_APB BASE_MADDR_MML2_QP_APB
+ #define BASE_NADDR_MML2_QP_MEM BASE_MADDR_MML2_QP_MEM
+ #define BASE_NADDR_MML2_META_APB BASE_MADDR_MML2_META_APB
+ #define BASE_NADDR_MML2_META_MEM BASE_MADDR_MML2_META_MEM
+ #define BASE_NADDR_MML2_VRB_MANAGER BASE_MADDR_MML2_VRB_MANAGER
+ #define BASE_NADDR_MML2_MMU BASE_MADDR_MML2_MMU
+ #define BASE_NADDR_MML2_DMA_RD BASE_MADDR_MML2_DMA_RD
+ #define BASE_NADDR_MML2_DMA_WR BASE_MADDR_MML2_DMA_WR
+ #define BASE_NADDR_MML2_LHIF BASE_MADDR_MML2_LHIF
+ #define BASE_NADDR_MML2_CIPHER BASE_MADDR_MML2_CIPHER
+ #define BASE_NADDR_MML2_DL_LMAC BASE_MADDR_MML2_DL_LMAC
+ #define BASE_NADDR_MML2_HARQ_CTRL BASE_MADDR_MML2_HARQ_CTRL
+ #define BASE_NADDR_MML2_SRAM_WRAP BASE_MADDR_MML2_SRAM_WRAP
+ #define BASE_NADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG_TOP
+ #define BASE_NADDR_MML2_BYC BASE_MADDR_MML2_BYC
+
+
+
+
+#endif /* ELBRUS */
+
+#endif /* end of __REG_BASE_ELBRUS_H__ */