[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/driver/sleep_drv/RM_public.h b/mcu/interface/driver/sleep_drv/RM_public.h
new file mode 100644
index 0000000..01ced85
--- /dev/null
+++ b/mcu/interface/driver/sleep_drv/RM_public.h
@@ -0,0 +1,596 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * RM_public.h
+ *
+ * Project:
+ * --------
+ * MT6280
+ *
+ * Description:
+ * ------------
+ * Resource Management configuration
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef RM_PUBLIC_H
+#define RM_PUBLIC_H
+
+#include "kal_general_types.h"
+#include "sleepdrv_common.h"
+#include "l1_rm_public.h" /* for modem related definition move to l1sm_public.h */
+
+
+typedef enum
+{
+ /* Resource on MCU RM */
+ //RM_MCU_BASE = 0,
+ /* Resource on MODEM RM */
+ MODEM_SLV_START = 0,
+ RM_MD2G_SPEECH = 0,
+ RM_C2K_TRIGGER = 4,
+ RM_LTE_CS = 5,
+ RM_FDD_TD = 6,/* talking & datalink */
+ RM_FDD_DL = 7, /* datalink */
+ MODEM_SLV_END = 7,
+ MODEM_DBG_START = 8,
+ RM_TDD_TD = 11,
+ RM_TDD_DL = 12,
+ MODEM_DBG_END = 12,
+ NUMBER_OF_RESOURCE,
+ /*Move original declared into RM_Module. */
+ RM_MODEM_BASE = 20,
+ RM_MODEM_DSP_1,
+ RM_MODEM_DSP_2,
+ RM_MODEM_L2_COPRO,
+ NUMBER_OF_RM_MODEM
+} RM_Module;
+
+typedef enum
+{
+#if defined(__MD93__)
+ CORE0_PWR = 0,
+ CORE1_PWR = 1,
+ USIP0_PWR = 2,
+ USIP1_PWR = 3,
+ MML2_PWR = 4,
+ MDCORE_PWR = 5,
+ MDINFRA_PWR = 6,
+ CM2_PWR = 7,
+ MAX_PWR = 8,
+#elif defined(__MD95__)
+ CORE0_PWR = 0,
+ CORE1_PWR = 1,
+ CORE2_PWR = 2,
+ USIP0_PWR = 3,
+ MDCORE_PWR = 4,
+ CM2_PWR = 5,
+ MML2_PWR = 6,
+ MAX_PWR = 7,
+#elif defined(__MD97__) || defined(__MD97P__)
+ CORE0_PWR = 0,
+ CORE1_PWR = 1,
+ CORE2_PWR = 2,
+ CORE3_PWR = 3,
+ USIP0_PWR = 4,
+ MDCORE_PWR = 5,
+ MML2_PWR = 6,
+ CM2_PWR = 11,
+ MAX_PWR = 12,
+#else
+ #error "no chip match"
+#endif
+} MDTOPSM_Power_Domain;
+
+typedef enum
+{
+ L1_COMMRES = 0,
+ EMI = 1,
+ MAX_CT = 2,
+} MDTOPSM_Cross_Trigger;
+
+//#endif
+
+void RM_Init( void );
+extern void MD_TOPSM_PWR_SW_Control(MDTOPSM_Power_Domain pwr_dom, kal_bool enable);
+extern void MD_TOPSM_CT_SW_Control(MDTOPSM_Cross_Trigger CT, kal_bool enable);
+extern void MD_TOPSM_DDR_SW_Control(kal_bool enable);
+extern void MD_TOPSM_Init_Other_Cores(void);
+extern void MD_TOPSM_SibAttach(void);
+extern kal_bool MD_TOPSM_Is_USIP_ForcedOn(void);
+extern kal_bool MD_TOPSM_Is_Pwr_Domain_Off_to_On(MDTOPSM_Power_Domain pwr_dom);
+extern void MD_TOPSM_PWR_SW_Control_CM2(kal_bool enable);
+extern void MD_TOPSM_PWR_SW_Control_MDCORE(kal_bool enable);
+extern kal_bool MD_TOPSM_Is_Pwr_Domain_on(MDTOPSM_Power_Domain pwr_dom);
+extern kal_bool MD_TOPSM_GetCsysReqSta(void);
+extern kal_bool MD_TOPSM_IsMDInfraPowerOn(void);
+extern kal_bool MD_TOPSM_IsUsipPowerOn(void);
+extern kal_uint32 MD_TOPSM_Get_F32K_Cnt(void);
+/* Should remove later */
+extern kal_uint32 MD_TOPSM_PollingTimingSyncSta(MODEM_TOPSM_TIMER_MODULE timer);
+extern kal_uint32 MD_TOPSM_GetSync26M(MODEM_TOPSM_TIMER_MODULE timer);
+extern void MD_TOPSM_ClearTimingSyncSta(MODEM_TOPSM_TIMER_MODULE timer);
+extern void MD_TOPSM_SetGPSSyncCon0(kal_uint32 value);
+extern void MD_TOPSM_SetGPSSyncCon1(kal_uint32 value);
+extern kal_bool MD_TOPSM_GetErrorStatus(void);
+#endif /* !RM_PUBLIC_H */
diff --git a/mcu/interface/driver/sleep_drv/dcxo_div_public.h b/mcu/interface/driver/sleep_drv/dcxo_div_public.h
new file mode 100644
index 0000000..1f1aebf
--- /dev/null
+++ b/mcu/interface/driver/sleep_drv/dcxo_div_public.h
@@ -0,0 +1,329 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcxo_div_public.h
+ *
+ * Project:
+ * --------
+ * General with 32K-Less Feature
+ *
+ * Description:
+ * ------------
+ * Provide public API interface of DCXO divider to other modulers for 32k-less control.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __DCXO_DIV_PUBLIC_H__
+#define __DCXO_DIV_PUBLIC_H__
+
+/* ----- 32K Removal ---------------------------------------------------- */
+#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
+#define IS_32K_REMOVAL_SUPPORT 1
+#define IS_32K_REMOVAL_SUPPORT_DEBUG 1 // debug code/trace for development
+#else
+#define IS_32K_REMOVAL_SUPPORT 0
+#define IS_32K_REMOVAL_SUPPORT_DEBUG 0 // debug code/trace for development
+#endif /* __F32_XOSC_REMOVAL_SUPPORT__ */
+
+#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
+
+#include "kal_general_types.h" // for kal type define
+#include "kal_public_defs.h"
+#include "kal_public_api.h" // for kal assert define
+
+/* for MT6763 check PMIC chip version*/
+#if defined(MT6763) && !defined(L1_SIM)
+#define SM_PMIC_MT6356E2_CHIP_CHECK 1
+#else
+#define SM_PMIC_MT6356E2_CHIP_CHECK 0
+#endif
+
+#if (defined(MT6359) || defined(MT6359P)) && (defined(__MD95__) || (defined(MT6885) && !defined(MT6893)))
+#define IS_6P5M_CLOCK_SOURCE 1
+#define IS_FPM_LPM_CO_CAPID 0 // for BBLPM can set capID the same as FPM lead to CLoad = 0, only with little error . (BBLPM capID != 255)
+#define COMPENSATION_VALUE_W 243 // Lafite, MT6359, F_FPM_255 -F_BBLPM_255 = 0.27ppm, ie., fix value: 0.27 (ppm) * 900M , for BBLPM capID = 255 case
+#else
+#define IS_6P5M_CLOCK_SOURCE 0
+#define IS_FPM_LPM_CO_CAPID 0 // for BBLPM can set capID as FPM lead to CLoad = 0, only with little error
+#define COMPENSATION_VALUE_W 0 // Eiger, MT6358, compensation value no set = 0 (ppm)
+#endif
+
+#define IS_32K_LESS_TEMPERATURE_SUPPORT 1
+#define DCXO_DIV_UPDATE_AFC_ONLY 0x80000000
+
+#define ABS_32KLESS(x) ((x) > 0 ? (x) : -(x))
+
+typedef enum
+{
+ DCXO_DIV_LPM_RESET,
+
+ DCXO_DIV_L1_UPDATE,
+ DCXO_DIV_L1_UPDATE_ONLY_F_OFFSET,
+ DCXO_DIV_L1_FORCE_UPDATE,
+
+ DCXO_DIV_UL1_UPDATE,
+ DCXO_DIV_UL1_UPDATE_ONLY_F_OFFSET,
+ DCXO_DIV_UL1_FORCE_UPDATE,
+
+ DCXO_DIV_TL1_UPDATE,
+ DCXO_DIV_TL1_UPDATE_ONLY_F_OFFSET,
+ DCXO_DIV_TL1_FORCE_UPDATE,
+
+ DCXO_DIV_EL1_UPDATE,
+ DCXO_DIV_EL1_UPDATE_AFC_ONLY,
+
+ DCXO_DIV_CL1_UPDATE,
+ DCXO_DIV_CL1_UPDATE_ONLY_F_OFFSET,
+ DCXO_DIV_CL1_FORCE_UPDATE,
+
+ DCXO_DIV_NL1_UPDATE,
+ DCXO_DIV_NL1_UPDATE_AFC_ONLY
+} DCXO_DIV_UPDATE_MODE;
+
+typedef enum
+{
+ DCXO_DIV_LPM = 0,
+ DCXO_DIV_FPM
+} DCXO_DIV_MODE;
+
+typedef enum
+{
+ DCXO_DIV_GSM = 0,
+ DCXO_DIV_USM,
+ DCXO_DIV_LTE,
+ DCXO_DIV_NR
+} DCXO_DIV_RAT;
+/* Leon: move following APIs from dcxo_div.c to dcxo_div_public.h because those APIs will be called by other modulo includes l1sm/ul1sm/el1sm.c & ostd.c to meet MSBB rule*/
+void DCXO_Div_UpdateLPMParam( DCXO_DIV_UPDATE_MODE mode, kal_int32 deltaFreqErr, kal_int32 deltaFreqCAFC, kal_uint8 adjuster );
+void DCXO_Div_UpdateFPMParam( DCXO_DIV_UPDATE_MODE mode, kal_int32 FreqOffset );
+kal_bool DCXO_Div_CheckFPMUpdate( void );
+kal_uint32 DCXO_Div_GetFPMParam( void );
+void DCXO_Div_Init( void );
+void DCXO_Div_InitCload( kal_int32 deltaFreq );
+void DCXO_Div_ResetLPM(void);
+kal_bool DCXO_Div_CheckExt32KCrystal( void );
+kal_bool DCXO_Div_Is32KLess( void );
+kal_bool DCXO_Div_IsCloadReady( void );
+void DCXO_Div_LPM_Counter_Start( void );
+void DCXO_Div_LPM_Counter_End( void );
+kal_bool DCXO_Div_LPM_Counter_CheckAndUpdate( kal_uint8 adjuster );
+kal_bool DCXO_Div_CheckHaveEnterLPM( void );
+kal_bool DCXO_Div_CheckErrorIsOverStable( DCXO_DIV_RAT rat, kal_int32 timingErrABS );
+void DCXO_Div_Test_SetDCXOMode( kal_uint32 dcxo_mode );
+void DCXO_Div_Test_ChangeDivider( kal_uint32 input_mode, kal_uint32 frac_offset );
+void DCXO_Div_Test_FPMDividerLock( kal_bool lock );
+void DCXO_Div_Test_FPMTrackingTrigger( kal_bool Is_trigger, kal_uint32 Trigger_mode );
+void DCXO_Div_Test_LPMTrackingTrigger( kal_bool Is_trigger, kal_uint32 Trigger_mode );
+#if IS_32K_LESS_TEMPERATURE_SUPPORT
+kal_bool DCXO_Div_Temperature_IsNearUbinVisited( DCXO_DIV_RAT rat );
+#endif
+#if defined(MT6763) && !defined(L1_SIM)
+kal_bool DCXO_Pmic_Chip_Is_MT6356E2( void );
+#endif
+/* -----------------------------------------------------------------------------------------------------------------------------------------------*/
+/* Remove LPM_DIV_UPDATE_LOCK_SUPPORT flag (it is old APIs for TDD). The following two APIs is now used by C2K in sys32kless.c */
+kal_uint32 DCXO_Div_GetAccLPMCnt( void );
+kal_uint32 DCXO_Div_GetLastUpdateLPMCnt( void );
+/* --------------------------------------------------------------------------------------------------------------*/
+
+#endif /* __F32_XOSC_REMOVAL_SUPPORT__ */
+#endif /* __DCXO_DIV_PUBLIC_H__ */
+
diff --git a/mcu/interface/driver/sleep_drv/l1_rm_public.h b/mcu/interface/driver/sleep_drv/l1_rm_public.h
new file mode 100644
index 0000000..44d35b6
--- /dev/null
+++ b/mcu/interface/driver/sleep_drv/l1_rm_public.h
@@ -0,0 +1,1292 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1sm_public.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for the public access for sleep mode operation.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Log$
+ *
+ * 01 22 2021 pj.chen
+ * [MOLY00620543] [Colgin][MT6880][MD_Sanity][MCD][core0,vpe0,tc0(vpe0)] Assert fail: MD_TOPSM.c 1923 0x6 0x0 0x0 - 0IDLE
+ *
+ * Increase EMI settle time (MD700)
+ *
+ * 11 11 2020 pj.chen
+ * [MOLY00554988] [Colgin] Sync code from T700.MP for sleep_drv
+ * Code sync from T700.MP to MD700.MP
+ *
+ * 07 14 2020 lian-li.tsai
+ * [MOLY00544033] Colgin Power optimization
+ * modify for sram type
+ * [EWSP0000131715]
+ *
+ * 07 08 2020 ethan.hsieh
+ * [MOLY00541152] �i20001�j�i?��??�j�imini dump�j[ASSERT] file:mcu/driver/sleep_drv/internal/src/ostd.c line:4482 p1:0x00000000
+ * [EWSP0000130019]
+ *
+ * 05 19 2020 sherry.wang
+ * [MOLY00521958] [MT6853] DIGRF A-Die reset flow[EWSP0000113180].
+ *
+ * 02 21 2020 jw.yu
+ * [MOLY00490615] [MT6853] add mouton chip option for sleep drv
+ * [EWSP0000085615] add mouton chip option.
+ *
+ * 11 14 2019 ws.yan
+ * [MOLY00452190] [MT6885][Petrus][Alpha phone][MP1][SQC][SH][5GMM][Static][CU][MDST][SWIFT][S][ASSERT] file:mcu/driver/sleep_drv/internal/src/MODEM_TOPSM.c line:2812
+ *
+ * [EWSP0000060046]
+ *
+ * 10 24 2019 hsiao-hsien.chen
+ * [MOLY00454049] [Rose][Petrus]BSP+][Q0]The Externel (EE),0,0,99,/data/vendor/core/,1,modem,md1:(MCU_core0.vpe1.tc2(VPE1)) [ASSERT] file:mcu/driver/devdrv/digrf_platform/src/digrf_bus_ao.c line:69 pop up.(once)
+ * .
+ *
+ * 10 21 2019 ws.yan
+ * [MOLY00452190] [MT6885][Petrus][Alpha phone][MP1][SQC][SH][5GMM][Static][CU][MDST][SWIFT][S][ASSERT] file:mcu/driver/sleep_drv/internal/src/MODEM_TOPSM.c line:2812
+ *
+ * modem topsm golden setting
+ * [EWSP0000053759]
+ *
+ * 09 17 2019 ws.yan
+ * [MOLY00440856] Gen97 sleep mode and sleep driver development: Enable sleep mode and power down
+ *
+ * .
+ * [EWSP0000043895 ]
+ *
+ * 07 24 2019 ws.yan
+ * [MOLY00422481] Gen97 sleep mode development: Lagecy RAT power down
+ *
+ * [EWSP0000028182]
+ *
+ * 07 18 2019 ws.yan
+ * [MOLY00422481] Gen97 sleep mode development: Lagecy RAT power down
+ *
+ * .rollback 8725463
+ *
+ * 07 03 2019 leon.yeh
+ * [MOLY00381082] [Gen97] Modem Sleep UMOLYE merge back
+ * - Krug settle parameter merge back
+ * .
+ *
+ * 07 01 2019 ws.yan
+ * [MOLY00417187] Gen97 sleep mode development: add MD97P option amd update rf topsm golden setting
+ *
+ * .
+ * [EWSP0000021808]
+ *
+ * 05 27 2019 ws.yan
+ * [MOLY00405206] [Power down]Legacy sleep mode test: RFSLPC prot issue workaround(sleep driver part)
+ * [EWSP0000012899]
+ * .
+ *
+ * 04 22 2019 hsiao-hsien.chen
+ * [MOLY00396310] VMOLY power down test: Assert fail: DVFS_drv.c 2574.
+ * [EWSP0000006054]
+ *
+ * 04 08 2019 ws.yan
+ * [MOLY00395725] Gen97 sleep mode development: ul1sm resource control modify
+ *
+ * .(SWRD)[EWSP0000003295 ]
+ *
+ * 03 08 2019 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ *
+ * check rf slpc status and lock rf slpc sleep api[ERS00030677]
+ *
+ * 01 31 2019 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ *
+ * 95 DSCC setting, remove 97 useless enum and define[ERS00029060 ]
+ *
+ * 01 31 2019 leon.yeh
+ * [MOLY00381082] [Gen97] Modem Sleep UMOLYE merge back - MDLPM interface (SWRD) [ERS00028476].
+ *
+ * 01 30 2019 leon.yeh
+ * [MOLY00381082] [Gen97] Modem Sleep UMOLYE merge back [ERS00028734]
+ * - add 2G slave (SW) trigger TXSYS power enum
+ * - TOPDM setting change based on DE spec for Lafite
+ * .
+ *
+ * 01 28 2019 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ *
+ * CPD for LTE DSCC
+ * ERS00028513 ]
+ *
+ * 12 19 2018 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ *
+ * .update modem topsm setting
+ * [ERS00024558 ]
+ *
+ * 11 14 2018 jw.yu
+ * [MOLY00325611] [UMOLYE][GEN97] xl1sim code submission
+ * [ERS00021711] add pll check list to 5G.
+ *
+ * 11 06 2018 jw.yu
+ * [MOLY00325611] [UMOLYE][GEN97] xl1sim code submission
+ * [ERS00020743] sync code from VMOLY.
+ *
+ * 10 24 2018 hsiao-hsien.chen
+ * [MOLY00346129] [GEN97] sleep driver modification. Drvier modify for DSCC.
+ * [ERS00018659]
+ *
+ * 09 27 2018 jw.yu
+ * [MOLY00325611] [UMOLYE][GEN97] xl1sim code submission
+ * nl1sm interface with sleep driver.
+ *
+ * 09 26 2018 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ *
+ * .
+ * add inject msg to force on power/pll
+ *
+ * 09 21 2018 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ * .
+ *
+ * 09 20 2018 ws.yan
+ * [MOLY00350903] Gen97 sleep mode and sleep driver develop
+ *
+ * .
+ *
+ * 09 11 2018 hsiao-hsien.chen
+ * [MOLY00346129] [GEN97] sleep driver modification.
+ * TOPSM driver modification.
+ *
+ * 08 21 2018 ws.yan
+ * [MOLY00346573] Gen97 merge sleep_drv patch to VMOLY
+ *
+ * .
+ *
+ *
+ * 08 17 2018 ws.yan
+ * [MOLY00346573] Gen97 merge sleep_drv patch to VMOLY
+ *
+ * .
+ *
+ * 08 14 2018 yen-sheng.lin
+ * [MOLY00312533] [Gen97] Modem Sleep driver development
+ * [GEN97 DEV to VMOLY]driver/md_sm.
+ *
+ * 05 30 2018 leon.yeh
+ * [MOLY00315332] [Eiger] modem sleep and LPWR change feature - IRQ & header file modification.
+ *
+ *
+ *
+ * 05 18 2018 leon.yeh
+ * [MOLY00326848] [Eiger] fix coding rule defect for sleep mode/driver/DVFS - 4G and driver part
+ *
+ * .
+ *
+ * 05 11 2018 james.pan
+ * [MOLY00324946] [MT6295][LTE][ET] Porting LTE ET Factory Calibration from UMOLYE.EIGER.SB.DEV
+ * porting MODEM_TOPSM_4GTX_METAControl() API.
+ *
+ * 05 02 2018 leon.yeh
+ * [MOLY00315332] [Eiger] modem sleep and LPWR change feature - setting MAS_TRIG_CORE0/1_SETTLE align.
+ *
+ * 04 02 2018 leon.yeh
+ * [MOLY00316801] for legacy chips option and feature options cleanup
+ *
+ * .
+ *
+ *
+ * 03 28 2018 leon.yeh
+ * [MOLY00315332] [Eiger] modem sleep and LPWR change feature - modify sysclk settle time, EMI settle time/SAL time according to AP team feedback
+ *
+ * 02 26 2018 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - remove MD2G SW PWR ctrl for audio usage and modify 3G offload in normal domain setting.
+ *
+ * 02 08 2018 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - modem topsm setting correct.
+ *
+ * 01 18 2018 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - modem topsm setting for pre antenna trigger modify according to Ver 2.0 (20180111) spec.
+ *
+ * 11 14 2017 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - fix build error for MT6295M_FPGA(LWTG_CA7) flavor.
+ *
+ * 11 07 2017 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - modem topsm setting for pre antenna trigger.
+ *
+ * 10 31 2017 pei-fei.wu
+ * [MOLY00285806] add EL2 sleep enable/disable API
+ *
+ * 10 30 2017 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - fix xl1sm build error.
+ *
+ * 10 23 2017 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - 95 setting porting & modem related header file reorganization.
+ *
+ * 02 06 2017 yen-sheng.lin
+ * [MOLY00204326] [MT6293] LTE sleep mode development.
+ * [SLEEP_DRV] remove SleepDrv_LockLMACPower related code.
+ *
+ * 12 26 2016 kevin-kh.liu
+ * [MOLY00216622] [2G] L1 dummy lisr removal check in
+ *
+ * reduce HWITC duration - check sleep status modification
+ *
+ * 11 01 2016 yen-sheng.lin
+ * [MOLY00204326] [MT6293] LTE sleep mode development
+ * add MPC task handle for sleep control and remove check sleep for MPC task .
+ *
+ * 10 17 2016 yen-sheng.lin
+ * [MOLY00204326] [MT6293] LTE sleep mode development
+ * 1) DI/EI region 2) share memory option 3) Code Sync.
+ *
+ * 09 30 2016 yen-sheng.lin
+ * [MOLY00204326] [MT6293] LTE sleep mode development
+ * merge EL1SM from UMOLY to UMOLYA.
+ *
+ * 04 19 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * Merging modem sleep mode related implementation from UMOLY to UMOLYA
+ *
+ * 03 29 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * L+L EL1-EL2 LMAC power notification handle bit extension
+ *
+ * 03 22 2016 kevin-kh.liu
+ * [MOLY00166741] [MT6292][Sleep Mode]sleep mode modification
+ *
+ * modify l1sm & ul1sm & sleep_drv to meet MSBB rule
+ *
+ * 03 17 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * enable sleep driver triggering CC_IRQ_L2P_SLEEP_MODE to Core 2
+ *
+ * 03 15 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * EL1-EL2 lock LMAC power Sleep Driver for EL1 part (without trigger CCIRQ)
+ *
+ * 03 14 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * 1. MSBB Violation
+ * 2. Remove EL1D DVFS avtive window check
+ * 3. 4G sleep mode locker for DVFS drivers
+ * 4. Add Data Sync Barrier
+ * 5. Rename global veriable
+ * 6. LMAC locker API implement
+ * 7. EL1D Backup functions relocated
+ *
+ * 03 11 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * Rollback CL2258329 CL2158833 CL2159108
+ *
+ * 03 09 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * remove re-defined macro
+ *
+ * 03 07 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * md_sm sleep_drv MSBB violation
+ *
+ * 02 25 2016 shengfu.tsai
+ * [MOLY00165958] [MT6292][Sleep Mode]L1 sleep mode modification
+ *
+ * .fix the MSBB violation, and add function prototype
+ *
+ * 03 21 2013 barry.hong
+ * [MOLY00012324] MOLY sleep driver sync
+ * .Sync Sleep Driver modification to MOLY trunk
+ *
+ * 02 26 2013 jeff.lee
+ * reorg. header file.
+ *
+ * 06 08 2012 jeff.lee
+ * removed!
+ * .
+ *
+ * 04 24 2012 wcpuser_integrator
+ * removed!
+ * .
+ *
+ * 07 27 2011 william.lin
+ * removed!
+ * removed!
+ * Define L1I_GetTimeStampXXX for non-hal members.
+ *
+ * 12 01 2010 raymond.chen
+ * removed!
+ * .
+ *
+ * removed!
+ * removed!
+ * uint8->kal_uint8
+ *
+ * removed!
+ * removed!
+ * Fix type error in the define.
+ *
+ * Rev 1.2 May 17 2005 00:29:14 BM_Trunk
+ * Karlos:
+ * add copyright and disclaimer statement
+ *
+ * Rev 1.1 Jan 18 2005 00:34:26 BM
+ * append new line in W05.04
+ *
+ * Rev 1.0 Nov 30 2002 19:49:58 admin
+ * Initial revision.
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __L1_RM_PUBLIC_H__
+#define __L1_RM_PUBLIC_H__
+
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "sleepdrv_common.h"
+//#include "reg_base.h"
+
+#if defined(__MD93__)
+#define PWR_ABBMIXSYS (0x1)
+#define PWR_MD2GSYS (0x2)
+#define PWR_RXDFESYS (0x4)
+#define PWR_TXSYS (0x8)
+#define PWR_CSSYS (0x10)
+#define PWR_RAKESYS (0x20)
+#define PWR_BRAMSYS (0x40)
+#define PWR_DMCSYS (0x80)
+
+#define PLL_MD2G (0x1)
+#define PLL_F208M (0x2)
+#define PLL_BSI (0x4)
+#define PLL_TX (0x8)
+#define PLL_CS (0x10)
+#define PLL_RAKE (0x20)
+#define PLL_VDSP (0x40)
+#define PLL_BRP (0x80)
+
+#define L1_RM_TXSYS (0x1)
+#define L1_RM_CSSYS (0x2)
+#define L1_RM_RAKE (0x4)
+#define L1_RM_BRAM_ALL (0x8)
+#define L1_RM_BRAM_RAM_VDSP (0x10)
+#define L1_RM_NUM (0x20)
+
+#define PWR_BRAM (PWR_BRAMSYS)
+#define PWR_DMC (PWR_DMCSYS)
+
+#elif defined(__MD95__)
+#define PWR_RXDFESYS (0x1)
+#define PWR_MD2GSYS (0x2)
+#define PWR_TXSYS (0x4)
+#define PWR_CSSYS (0x8)
+#define PWR_RAKESYS (0x10)
+#define PWR_INRMMSYS (0x20)
+#define PWR_RXBRPSYS (0x40)
+
+#define PLL_F208M (0x1)
+#define PLL_BSI (0x2)
+#define PLL_CS (0x4)
+#define PLL_RAKE (0x8)
+#define PLL_VDSP (0x10)
+#define PLL_BRP (0x20)
+#define PLL_DFESYNC (0x40)
+#define PLL_RXAGC (0x80)
+
+#define L1_RM_TXSYS (0x1)
+#define L1_RM_CSSYS (0x2)
+#define L1_RM_RAKE (0x4)
+#define L1_RM_INRMM (0x8)
+#define L1_RM_RXBRP (0x10)
+#define L1_RM_NUM (0x20)
+
+#define PWR_BRAM (PWR_INRMMSYS)
+#define PWR_DMC (PWR_RXBRPSYS)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define PWR_MD2GSYS (0x1)
+#define PWR_CSSYS (0x2)
+#define PWR_RAKESYS (0x4)
+#define PWR_INRMMSYS (0x8)
+#define PWR_RXBRPSYS (0x10)
+#define PWR_NRCMSYS (0x20)
+#define PWR_NRCSSYS (0x40)
+#define PWR_NRRXT2FSYS (0x80)
+#define PWR_NRTXSYS (0x100)
+#define PWR_NRRXCPCSYS (0x200)
+#define PWR_MCORESYS (0x400)
+#define PWR_MCOREINFRASYS (0x800)
+#define PWR_NRRXCSISYS (0x1000)
+#define PWR_NRRXDDMSYS (0x2000)
+#define PWR_NRRXDBRPSYS (0x4000)
+#define PWR_HRAMSYS (0x8000)
+#define PWR_VCORESIL2CSYS (0x10000)
+#define PWR_MDRXSYSPARENT (0x20000)
+#define PWR_FESYSPARENT (0x40000)
+
+#define PLL_DFE (0x1)
+#define PLL_BSI (0x2)
+#define PLL_CS (0x4)
+#define PLL_RAKE (0x8)
+#define PLL_INRMM (0x10)
+#define PLL_BRP (0x20)
+#define PLL_BUS4X (0x40)
+#define PLL_NRCM (0x80)
+#define PLL_NRCS (0x100)
+#define PLL_NRRXT2F (0x200)
+#define PLL_NRTXBSRP (0x400)
+#define PLL_NRRX (0x800)
+#define PLL_MCORE (0x1000)
+#define PLL_RXCSI (0x2000)
+#define PLL_HRAM (0x4000)
+#define PLL_VCORE (0x8000)
+
+#define L1_RM_CSSYS (0x1)
+#define L1_RM_RAKE (0x2)
+#define L1_RM_INRMM (0x4)
+#define L1_RM_RXBRP (0x8)
+#define L1_RM_NRRX (0x10)
+#define L1_RM_RXCPC (0x400)
+#define L1_RM_CMNR (0x800)
+#define L1_RM_CSNR (0x1000)
+#define L1_RM_RXCSINR (0x2000)
+#define L1_RM_NRDSP (0x4000)
+#define L1_RM_LOGGER (0x8000)
+#define L1_RM_NUM (0x10000)
+
+#endif
+
+#if defined(__MD93__) || defined(__MD95__)
+/* For TOPSM logger force on resource API */
+#define L1_RM_RAKE_MASK 0x0000F000
+#define L1_RM_BRAM_ALL_MASK 0x00FF0000 // MD93 = BRAMsys; MD95=INRMMsys
+
+#elif defined(__MD97__) || defined(__MD97P__)
+#define L1_RM_RAKE_MASK 0x0000003C
+#define L1_RM_BRAM_ALL_MASK 0x00000FC0 // MD97=INRMMsys
+#define L1_RM_LOGGER_MASK 0xF0000000 // MD97=INRMMsys
+#endif
+
+#if defined(__MD93__)
+#define RM_Str_Resource(var) RM_Str_Resource_93(var)
+#elif defined(__MD95__)
+#define RM_Str_Resource(var) RM_Str_Resource_95(var)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define RM_Str_Resource(var) RM_Str_Resource_97(var)
+#endif
+
+#if defined(__MD93__)
+#define PWR_RDY_CHECK_2G (PWR_ABBMIXSYS | PWR_MD2GSYS | PWR_RXDFESYS)
+#define PLL_RDY_CHECK_2G (PLL_MD2G | PLL_F208M | PLL_BSI)
+#define PWR_RDY_CHECK_3G (PWR_ABBMIXSYS | PWR_RXDFESYS | PWR_CSSYS)
+#define PLL_RDY_CHECK_3G (PLL_F208M | PLL_BSI | PLL_CS)
+#define PWR_RDY_CHECK_4G (PWR_ABBMIXSYS | PWR_RXDFESYS | PWR_RAKESYS | PWR_BRAMSYS)
+#define PLL_RDY_CHECK_4G (PLL_F208M | PLL_BSI | PLL_TX | PLL_RAKE | PLL_VDSP | PLL_VDSP | PLL_BRP)
+#elif defined(__MD95__)
+#define PWR_RDY_CHECK_2G (PWR_RXDFESYS | PWR_MD2GSYS)
+#define PLL_RDY_CHECK_2G (PLL_F208M | PLL_BSI | PLL_RXAGC)
+#define PWR_RDY_CHECK_3G (PWR_RXDFESYS | PWR_CSSYS)
+#define PLL_RDY_CHECK_3G (PLL_F208M | PLL_BSI | PLL_CS | PLL_RXAGC)
+#define PWR_RDY_CHECK_4G (PWR_RXDFESYS | PWR_INRMMSYS | PWR_RXBRPSYS)
+#define PLL_RDY_CHECK_4G (PLL_F208M | PLL_BSI | PLL_VDSP | PLL_BRP | PLL_DFESYNC | PLL_RXAGC)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define PWR_RDY_CHECK_2G (PWR_MD2GSYS | PWR_INRMMSYS)
+#define PLL_RDY_CHECK_2G (PLL_DFE | PLL_BSI | PLL_INRMM)
+#define PWR_RDY_CHECK_3G (PWR_CSSYS)
+#define PLL_RDY_CHECK_3G (PLL_DFE | PLL_BSI | PLL_CS)
+#define PWR_RDY_CHECK_4G (PWR_INRMMSYS | PWR_RXBRPSYS)
+#define PLL_RDY_CHECK_4G (PLL_DFE | PLL_BSI | PLL_INRMM | PLL_BRP)
+#define PWR_RDY_CHECK_5G (PWR_NRRXT2FSYS | PWR_NRRXCPCSYS | PWR_MCORESYS | PWR_MCOREINFRASYS | PWR_NRRXDDMSYS | PWR_NRRXDBRPSYS | PWR_HRAMSYS | PWR_VCORESIL2CSYS)
+#define PLL_RDY_CHECK_5G (PLL_DFE | PLL_BSI | PLL_BUS4X | PLL_NRRXT2F | PLL_NRRX | PLL_MCORE | PLL_HRAM | PLL_VCORE)
+#endif
+
+/* For inject cmd usage */
+#if defined(__MD93__)
+#define PWR_CON0 (PWR_ABBMIXSYS)
+#define PWR_CON1 (PWR_MD2GSYS)
+#define PWR_CON2 (PWR_RXDFESYS)
+#define PWR_CON3 (PWR_TXSYS)
+#define PWR_CON4 (PWR_CSSYS)
+#define PWR_CON5 (PWR_RAKESYS)
+#define PWR_CON6 (PWR_BRAMSYS)
+#define PWR_CON7 (PWR_DMCSYS)
+#define PWR_ALL (PWR_CON0 | PWR_CON1 | PWR_CON2 | PWR_CON3 | PWR_CON4 | PWR_CON5 | PWR_CON6 | PWR_CON7)
+
+#define PWR_CON0_PLL (PLL_F208M)
+#define PWR_CON1_PLL (PLL_MD2G | PLL_F208M | PLL_BSI)
+#define PWR_CON2_PLL (PLL_F208M | PLL_BSI)
+#define PWR_CON3_PLL (PLL_F208M | PLL_BSI | PLL_TX)
+#define PWR_CON4_PLL (PLL_F208M | PLL_CS)
+#define PWR_CON5_PLL (PLL_F208M | PLL_RAKE)
+#define PWR_CON6_PLL (PLL_F208M | PLL_VDSP | PLL_BRP)
+#define PWR_CON7_PLL (PLL_F208M | PLL_BRP)
+#define PWR_ALL_PLL (PLL_MD2G | PLL_F208M | PLL_BSI | PLL_TX | PLL_CS | PLL_RAKE | PLL_VDSP | PLL_BRP)
+
+typedef enum
+{
+ INJECT_ENUM_PWR_CON0,
+ INJECT_ENUM_PWR_CON1,
+ INJECT_ENUM_PWR_CON2,
+ INJECT_ENUM_PWR_CON3,
+ INJECT_ENUM_PWR_CON4,
+ INJECT_ENUM_PWR_CON5,
+ INJECT_ENUM_PWR_CON6,
+ INJECT_ENUM_PWR_CON7,
+ INJECT_ENUM_PWR_NUM
+} INJECT_PWR_ENUM;
+
+#elif defined(__MD95__)
+#define PWR_CON0 (PWR_RXDFESYS)
+#define PWR_CON1 (PWR_MD2GSYS)
+#define PWR_CON2 (PWR_TXSYS)
+#define PWR_CON3 (PWR_CSSYS)
+#define PWR_CON4 (PWR_RAKESYS)
+#define PWR_CON5 (PWR_INRMMSYS)
+#define PWR_CON6 (PWR_RXBRPSYS)
+#define PWR_ALL (PWR_CON0 | PWR_CON1 | PWR_CON2 | PWR_CON3 | PWR_CON4 | PWR_CON5 | PWR_CON6)
+
+#define PWR_CON0_PLL (PLL_F208M | PLL_BSI | PLL_RXAGC)
+#define PWR_CON1_PLL (PLL_F208M | PLL_BSI)
+#define PWR_CON2_PLL (PLL_F208M)
+#define PWR_CON3_PLL (PLL_F208M | PLL_CS)
+#define PWR_CON4_PLL (PLL_F208M | PLL_RAKE)
+#define PWR_CON5_PLL (PLL_F208M | PLL_VDSP | PLL_DFESYNC)
+#define PWR_CON6_PLL (PLL_F208M | PLL_BRP)
+#define PWR_ALL_PLL (PLL_F208M | PLL_BSI | PLL_CS | PLL_RAKE | PLL_VDSP | PLL_BRP | PLL_DFESYNC | PLL_RXAGC)
+
+typedef enum
+{
+ INJECT_ENUM_PWR_CON0,
+ INJECT_ENUM_PWR_CON1,
+ INJECT_ENUM_PWR_CON2,
+ INJECT_ENUM_PWR_CON3,
+ INJECT_ENUM_PWR_CON4,
+ INJECT_ENUM_PWR_CON5,
+ INJECT_ENUM_PWR_CON6,
+ INJECT_ENUM_PWR_NUM
+} INJECT_PWR_ENUM;
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+#define INJECT_INDEX_MAX 17
+
+#define PWR_CON0 (PWR_MD2GSYS | PWR_FESYSPARENT)
+#define PWR_CON1 (PWR_CSSYS | PWR_FESYSPARENT)
+#define PWR_CON2 (PWR_RAKESYS | PWR_MDRXSYSPARENT)
+#define PWR_CON3 (PWR_INRMMSYS | PWR_MDRXSYSPARENT)
+#define PWR_CON4 (PWR_RXBRPSYS | PWR_MDRXSYSPARENT)
+#define PWR_CON5 (PWR_NRCMSYS)
+#define PWR_CON6 (PWR_NRCSSYS)
+#define PWR_CON7 (PWR_NRRXT2FSYS)
+#define PWR_CON8 (PWR_NRTXSYS)
+#define PWR_CON9 (PWR_NRRXCPCSYS)
+#define PWR_CON10 (PWR_MCORESYS)
+#define PWR_CON11 (PWR_MCOREINFRASYS)
+#define PWR_CON12 (PWR_NRRXCSISYS)
+#define PWR_CON13 (PWR_NRRXDDMSYS)
+#define PWR_CON14 (PWR_NRRXDBRPSYS)
+#define PWR_CON15 (PWR_HRAMSYS)
+#define PWR_CON16 (PWR_VCORESIL2CSYS)
+
+#define PWR_ALL (0x7FFFF)
+
+#define PWR_CON0_PLL (PLL_DFE)
+#define PWR_CON1_PLL (PLL_DFE | PLL_CS)
+#define PWR_CON2_PLL (PLL_RAKE)
+#define PWR_CON3_PLL (PLL_DFE | PLL_RAKE | PLL_INRMM)
+#define PWR_CON4_PLL (PLL_DFE | PLL_BRP)
+#define PWR_CON5_PLL (PLL_BUS4X | PLL_NRCM)
+#define PWR_CON6_PLL (PLL_BUS4X | PLL_NRCS)
+#define PWR_CON7_PLL (PLL_NRRXT2F)
+#define PWR_CON8_PLL (PLL_DFE | PLL_BUS4X | PLL_NRTXBSRP)
+#define PWR_CON9_PLL (PLL_BUS4X | PLL_NRRX)
+#define PWR_CON10_PLL (PLL_DFE | PLL_BUS4X | PLL_MCORE)
+#define PWR_CON11_PLL (PLL_DFE | PLL_MCORE)
+#define PWR_CON12_PLL (PLL_BUS4X | PLL_RXCSI)
+#define PWR_CON13_PLL (PLL_BUS4X | PLL_NRRX)
+#define PWR_CON14_PLL (PLL_BUS4X | PLL_NRRX)
+#define PWR_CON15_PLL (PLL_DFE | PLL_HRAM | PLL_VCORE)
+#define PWR_CON16_PLL (PLL_DFE | PLL_VCORE)
+#define PWR_ALL_PLL (0xFFFF)
+
+#endif
+/* For inject cmd usage */
+
+
+#if defined(__MD93__)
+typedef enum
+{
+ L1_TXSYS_REQ_FDD = 0,
+ L1_TXSYS_REQ_TDD = 1,
+ L1_TXSYS_REQ_C2K1X = 2,
+ L1_TXSYS_REQ_C2KDO = 3,
+ L1_TXSYS_REQ_LTE = 4,
+ L1_TXSYS_REQ5 = 5,
+ L1_TXSYS_REQ_END = L1_TXSYS_REQ5,
+ L1_CSSYS_REQ0 = 6,
+ L1_CSSYS_REQ1 = 7,
+ L1_CSSYS_REQ2 = 8,
+ L1_CSSYS_REQ3 = 9,
+ L1_CSSYS_REQ_LTE = 10,
+ L1_CSSYS_REQ5 = 11,
+ L1_CSSYS_REQ_END = L1_CSSYS_REQ5,
+ L1_RAKE_REQ_FDD = 12,
+ L1_RAKE_REQ_LOG = 13,
+ L1_RAKE_REQ_C2K1X = 14,
+ L1_RAKE_REQ_C2KDO = 15,
+ L1_RAKE_REQ_END = L1_RAKE_REQ_C2KDO,
+ // Gen93
+ L1_BRAM_ALL_REQ_FDD = 16,
+ L1_BRAM_ALL_REQ_TDD = 17,
+ L1_BRAM_ALL_REQ_C2K1X = 18,
+ L1_BRAM_ALL_REQ_C2KDO = 19,
+ L1_BRAM_ALL_REQ_LTE = 20,
+ L1_BRAM_ALL_REQ_LOG = 21,
+ L1_BRAM_ALL_REQ6 = 22,
+ L1_BRAM_ALL_REQ7 = 23,
+ L1_BRAM_ALL_REQ_END = L1_BRAM_ALL_REQ7,
+ // Gen93
+ L1_BRAM_RAM_VDSP_REQ_FDD = 24,
+ L1_BRAM_RAM_VDSP_REQ_TDD = 25,
+ L1_BRAM_RAM_VDSP_REQ_C2K1X = 26,
+ L1_BRAM_RAM_VDSP_REQ_C2KDO = 27,
+ L1_BRAM_RAM_VDSP_REQ_LTE = 28,
+ L1_BRAM_RAM_VDSP_REQ_LOG = 29,
+ L1_BRAM_RAM_VDSP_REQ6 = 30,
+ L1_BRAM_RAM_VDSP_REQ7 = 31,
+ L1_BRAM_RAM_VDSP_REQ_END = L1_BRAM_RAM_VDSP_REQ7,
+ L1_NUMBER_OF_RESOURCE
+} L1_RM_Module;
+#elif defined(__MD95__)
+
+typedef enum
+{
+ L1_TXSYS_REQ_FDD = 0,
+ L1_TXSYS_REQ_TDD = 1,
+ L1_TXSYS_REQ_C2K1X = 2,
+ L1_TXSYS_REQ_C2KDO = 3,
+ L1_TXSYS_REQ_LTE = 4,
+ L1_TXSYS_REQ_GSM = 5,
+ L1_TXSYS_REQ_END = L1_TXSYS_REQ_GSM,
+ L1_CSSYS_REQ_LDSCC = 6,
+ L1_CSSYS_REQ1 = 7,
+ L1_CSSYS_REQ2 = 8,
+ L1_CSSYS_REQ3 = 9,
+ L1_CSSYS_REQ_LTE = 10,
+ L1_CSSYS_REQ5 = 11,
+ L1_CSSYS_REQ_END = L1_CSSYS_REQ5,
+ L1_RAKE_REQ_FDD = 12,
+ L1_RAKE_REQ_LOG = 13,
+ L1_RAKE_REQ_C2K1X = 14,
+ L1_RAKE_REQ_C2KDO = 15,
+ L1_RAKE_REQ_END = L1_RAKE_REQ_C2KDO,
+ // Gen95
+ L1_INRMM_REQ_FDD = 16,
+ L1_INRMM_REQ_TDD = 17,
+ L1_INRMM_REQ_C2K1X = 18,
+ L1_INRMM_REQ_C2KDO = 19,
+ L1_INRMM_REQ_LTE = 20,
+ L1_INRMM_REQ_LOG = 21,
+ L1_INRMM_REQ6 = 22,
+ L1_INRMM_REQ7 = 23,
+ L1_INRMM_REQ_END = L1_INRMM_REQ7,
+ // Gen95
+ L1_RXBRP_REQ_FDD = 24,
+ L1_RXBRP_REQ_TDD = 25,
+ L1_RXBRP_REQ_C2K1X = 26,
+ L1_RXBRP_REQ_C2KDO = 27,
+ L1_RXBRP_REQ_LTE = 28,
+ L1_RXBRP_REQ_LOG = 29,
+ L1_RXBRP_REQ6 = 30,
+ L1_RXBRP_REQ7 = 31,
+ L1_RXBRP_REQ_END = L1_RXBRP_REQ7,
+ L1_NUMBER_OF_RESOURCE
+} L1_RM_Module;
+#elif defined(__MD97__) || defined(__MD97P__)
+
+typedef enum
+{
+ L1_CSSYS_REQ_LTE = 0,
+ L1_CSSYS_REQ1 = 1,
+ L1_CSSYS_REQ_END = L1_CSSYS_REQ1,
+ L1_RAKE_REQ_FDD = 2,
+ L1_RAKE_REQ_C2K1X = 3,
+ L1_RAKE_REQ_C2KDO = 4,
+ L1_RAKE_REQ_LOG = 5,
+ L1_RAKE_REQ_END = L1_RAKE_REQ_LOG,
+ L1_INRMM_REQ_FDD = 6,
+ L1_INRMM_REQ_C2K1X = 7,
+ L1_INRMM_REQ_C2KDO = 8,
+ L1_INRMM_REQ_LOG = 9,
+ L1_INRMM_REQ_GSM = 10,
+ L1_INRMM_REQ5 = 11,
+ L1_INRMM_REQ_END = L1_INRMM_REQ5,
+ L1_RXBRP_REQ_FDD = 12,
+ L1_RXBRP_REQ_C2K1X = 13,
+ L1_RXBRP_REQ_C2KDO = 14,
+ L1_RXBRP_REQ_TDD = 15,
+ L1_RXBRP_REQ_END = L1_RXBRP_REQ_TDD,
+
+ L1_NRRX_REQ_NR = 16,
+ L1_NRRX_REQ1 = 17,
+ L1_NRRX_REQ_END = L1_NRRX_REQ1,
+ L1_WDSCC_REQ_FDD = 18,
+ L1_WDSCC_REQ_UL1SM = 19,
+ L1_WDSCC_REQ_END = L1_WDSCC_REQ_UL1SM,
+ L1_CMNR_REQ_NR = 20,
+ L1_CMNR_REQ1 = 21,
+ L1_CMNR_REQ_END = L1_CMNR_REQ1,
+ L1_CSNR_REQ_NR = 22,
+ L1_CSNR_REQ1 = 23,
+ L1_CSNR_REQ_END = L1_CSNR_REQ1,
+
+ L1_LDSCC_REQ_LTE = 24,
+ L1_LDSCC_REQ1 = 25,
+ L1_LDSCC_REQ_END = L1_LDSCC_REQ1,
+ L1_NRDSP_REQ_NR = 26,
+ L1_NRDSP_REQ1 = 27,
+ L1_NRDSP_REQ_END = L1_NRDSP_REQ1,
+ NR_LOGGER_REQ_LOG = 28,
+ NR_LOGGER_REQ_1 = 29,
+ NR_LOGGER_REQ_2 = 30,
+ NR_LOGGER_REQ_3 = 31,
+ NR_LOGGER_REQ_END = NR_LOGGER_REQ_3,
+ L1_NUMBER_OF_RESOURCE,
+
+} L1_RM_Module;
+
+#endif
+
+typedef enum
+{
+ MODEM_TOPSM_EMI_REQ_GSM = 0x0,
+ MODEM_TOPSM_EMI_REQ_UMTS = 0x1,
+ MODEM_TOPSM_EMI_REQ_LTE = 0x2
+} MODEM_TOPSM_EMI_REQ_MODULE;
+
+typedef enum
+{
+ TIMER_OSTD = 0,
+ TIMER_2G,
+ TIMER_3G_FDD,
+ TIMER_3G_TDD,
+ TIMER_C2K_1x,
+ TIMER_SSTA0_END = TIMER_C2K_1x,
+ TIMER_C2K_do,
+ TIMER_4G,
+ TIMER_5G,
+ TIMER_EXT_frame,
+ TIMER_NUM
+} MODEM_TOPSM_TIMER_MODULE;
+
+typedef enum
+{
+ TIMER_NORMAL = 0x1,
+ TIMER_MTOFF = 0x2,
+ TIMER_PAUSE = 0x4,
+ TIMER_PRE_PAUSE = 0x8,
+ TIMER_SYSCLK_SETTLE = 0x10,
+ TIMER_CCP_SETTLE = 0x20,
+ TIMER_MTON = 0x40
+} MODEM_TOPSM_TIMER_STATUS;
+
+
+#if defined(__MD93__)
+typedef enum
+{
+ MODEM_TOPSM_PWR_ENUM_ABBMIXSYS,
+ MODEM_TOPSM_PWR_ENUM_MD2GSYS,
+ MODEM_TOPSM_PWR_ENUM_RXDFESYS,
+ MODEM_TOPSM_PWR_ENUM_TXSYS,
+ MODEM_TOPSM_PWR_ENUM_CSSYS,
+ MODEM_TOPSM_PWR_ENUM_RAKESYS,
+ MODEM_TOPSM_PWR_ENUM_BRAMSYS,
+ MODEM_TOPSM_PWR_ENUM_DMCSYS,
+ MODEM_TOPSM_PWR_ENUM_NUM,
+ MODEM_TOPSM_PWR_ENUM_AO = MODEM_TOPSM_PWR_ENUM_NUM
+} MODEM_TOPSM_PWR_ENUM;
+
+typedef enum
+{
+ MODEM_TOPSM_PLL_ENUM_MD2G,
+ MODEM_TOPSM_PLL_ENUM_F208M,
+ MODEM_TOPSM_PLL_ENUM_BSI,
+ MODEM_TOPSM_PLL_ENUM_TX,
+ MODEM_TOPSM_PLL_ENUM_CS,
+ MODEM_TOPSM_PLL_ENUM_RAKE,
+ MODEM_TOPSM_PLL_ENUM_VDSP,
+ MODEM_TOPSM_PLL_ENUM_BRP,
+ MODEM_TOPSM_PLL_ENUM_NUM,
+ MODEM_TOPSM_PLL_ENUM_AO = MODEM_TOPSM_PLL_ENUM_NUM
+} MODEM_TOPSM_PLL_ENUM;
+
+typedef enum
+{
+ MODEM_TOPSM_SYSCLK_ENUM_RF1_SYSCLK,
+ MODEM_TOPSM_SYSCLK_ENUM_RF2_SYSCLK,
+ MODEM_TOPSM_SYSCLK_ENUM_RF1_VRF18,
+ MODEM_TOPSM_SYSCLK_ENUM_RF2_VRF18,
+ MODEM_TOPSM_SYSCLK_ENUM_NUM
+} MODEM_TOPSM_SYSCLK_ENUM;
+
+#elif defined(__MD95__)
+
+typedef enum
+{
+ MODEM_TOPSM_PWR_ENUM_RXDFESYS,
+ MODEM_TOPSM_PWR_ENUM_MD2GSYS,
+ MODEM_TOPSM_PWR_ENUM_TXSYS,
+ MODEM_TOPSM_PWR_ENUM_CSSYS,
+ MODEM_TOPSM_PWR_ENUM_RAKESYS,
+ MODEM_TOPSM_PWR_ENUM_INRMMSYS,
+ MODEM_TOPSM_PWR_ENUM_RXBRPSYS,
+ MODEM_TOPSM_PWR_ENUM_NUM,
+ MODEM_TOPSM_PWR_ENUM_AO = MODEM_TOPSM_PWR_ENUM_NUM
+} MODEM_TOPSM_PWR_ENUM;
+
+typedef enum
+{
+ MODEM_TOPSM_PLL_ENUM_F208M,
+ MODEM_TOPSM_PLL_ENUM_BSI,
+ MODEM_TOPSM_PLL_ENUM_CS,
+ MODEM_TOPSM_PLL_ENUM_RAKE,
+ MODEM_TOPSM_PLL_ENUM_VDSP,
+ MODEM_TOPSM_PLL_ENUM_BRP,
+ MODEM_TOPSM_PLL_ENUM_DFESYNC,
+ MODEM_TOPSM_PLL_ENUM_RXAGC,
+ MODEM_TOPSM_PLL_ENUM_NUM,
+ MODEM_TOPSM_PLL_ENUM_AO = MODEM_TOPSM_PLL_ENUM_NUM
+} MODEM_TOPSM_PLL_ENUM;
+
+typedef enum
+{
+ MODEM_TOPSM_SYSCLK_ENUM_RF1_SYSCLK,
+ MODEM_TOPSM_SYSCLK_ENUM_RF1_VRF18,
+ MODEM_TOPSM_SYSCLK_ENUM_NUM
+} MODEM_TOPSM_SYSCLK_ENUM;
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+typedef enum
+{
+ MODEM_TOPSM_PWR_ENUM_MD2GSYS,
+ MODEM_TOPSM_PWR_ENUM_CSSYS,
+ MODEM_TOPSM_PWR_ENUM_RAKESYS,
+ MODEM_TOPSM_PWR_ENUM_INRMMSYS,
+ MODEM_TOPSM_PWR_ENUM_BRPSYS,
+ MODEM_TOPSM_PWR_ENUM_CMNRSYS,
+ MODEM_TOPSM_PWR_ENUM_CSNRSYS,
+ MODEM_TOPSM_PWR_ENUM_RXT2FNRSYS,
+ MODEM_TOPSM_PWR_ENUM_TXNRSYS,
+ MODEM_TOPSM_PWR_ENUM_RXCPCNRSYS,
+ MODEM_TOPSM_PWR_ENUM_MCORESYS,
+ MODEM_TOPSM_PWR_ENUM_MCOREINFRASYS,
+ MODEM_TOPSM_PWR_ENUM_RXCSINRSYS,
+ MODEM_TOPSM_PWR_ENUM_RXDDMNRSYS,
+ MODEM_TOPSM_PWR_ENUM_RXDBRPSYS,
+ MODEM_TOPSM_PWR_ENUM_HRAMSYS,
+ MODEM_TOPSM_PWR_ENUM_VCORESIL2CSYS,
+ MODEM_TOPSM_PWR_ENUM_MDRXSYSPARENTSYS,
+ MODEM_TOPSM_PWR_ENUM_FESYSPARENTSYS,
+ MODEM_TOPSM_PWR_ENUM_NUM,
+ MODEM_TOPSM_PWR_ENUM_AO = MODEM_TOPSM_PWR_ENUM_NUM
+} MODEM_TOPSM_PWR_ENUM;
+
+typedef enum
+{
+ MODEM_TOPSM_PLL_ENUM_DFE,
+ MODEM_TOPSM_PLL_ENUM_BSI,
+ MODEM_TOPSM_PLL_ENUM_CS,
+ MODEM_TOPSM_PLL_ENUM_RAKE,
+ MODEM_TOPSM_PLL_ENUM_INRMM,
+ MODEM_TOPSM_PLL_ENUM_BRP,
+ MODEM_TOPSM_PLL_ENUM_BUS4X,
+ MODEM_TOPSM_PLL_ENUM_NRCM,
+ MODEM_TOPSM_PLL_ENUM_NRCS,
+ MODEM_TOPSM_PLL_ENUM_NRRXT2F,
+ MODEM_TOPSM_PLL_ENUM_NRTXBSRP,
+ MODEM_TOPSM_PLL_ENUM_NRRX,
+ MODEM_TOPSM_PLL_ENUM_MCORE,
+ MODEM_TOPSM_PLL_ENUM_RXCSI,
+ MODEM_TOPSM_PLL_ENUM_HRAM,
+ MODEM_TOPSM_PLL_ENUM_VCORE,
+ MODEM_TOPSM_PLL_ENUM_NUM,
+ MODEM_TOPSM_PLL_ENUM_AO = MODEM_TOPSM_PLL_ENUM_NUM
+} MODEM_TOPSM_PLL_ENUM;
+
+typedef enum
+{
+ MODEM_TOPSM_SYSCLK_ENUM_RF1_SYSCLK,
+ MODEM_TOPSM_SYSCLK_ENUM_RF1_VRF18,
+ MODEM_TOPSM_SYSCLK_ENUM_NUM
+} MODEM_TOPSM_SYSCLK_ENUM;
+#endif
+
+typedef enum
+{
+ MEM_CONF_SRAM_CTRL_LTE,
+ MEM_CONF_SRAM_CTRL_NR,
+ MEM_CONF_SRAM_CTRL_NUM
+} MEM_CONF_SRAM_CTRL_CLIENT_ENUM;
+
+typedef enum
+{
+ MEM_CG_CTRL_LTE,
+ MEM_CG_CTRL_WCDMA,
+ MEM_CG_CTRL_TDS,
+ MEM_CG_CTRL_C2K1XRTT,
+ MEM_CG_CTRL_C2KEVDO,
+ MEM_CG_CTRL_NUM
+} MEM_CG_CTRL_CLIENT_ENUM;
+
+/* power domain mask define end */
+
+/* for low power monitor usage start */
+typedef enum
+{
+ MDLPM_SIM_1 = 1,
+ MDLPM_SIM_2 = 2,
+ MDLPM_SIM_3 = 3
+} MDLPM_SIM_INDEX;
+
+typedef enum
+{
+ MDLPM_RAT_STANDBY = 0,
+ ACTIVE_RAT_2G_GSM = 1,
+ ACTIVE_RAT_3G_FDD = 2,
+ ACTIVE_RAT_3G_TDD = 3,
+ ACTIVE_RAT_3G_C2K = 4,
+ ACTIVE_RAT_4G = 5,
+ ACTIVE_RAT_5G = 6
+} MDLPM_ACTIVE_RAT_INDEX;
+/* for low power monitor usage end */
+
+
+/* for DspBootResourceControl start */
+#if defined(__MD93__)
+#define L1_RM_INNER_FDD (L1_BRAM_ALL_REQ_FDD)
+#define L1_RM_INNER_C2K (L1_BRAM_ALL_REQ_C2KDO)
+#define L1_RM_INNER_LTE (L1_BRAM_ALL_REQ_LTE)
+#define L1_RM_BRP_FDD (L1_BRAM_ALL_REQ_FDD)
+#define L1_RM_BRP_LTE (L1_BRAM_ALL_REQ_LTE)
+#define DSP_BOOT_PWR (PWR_RAKESYS | PWR_BRAMSYS | PWR_TXSYS)
+
+#elif defined(__MD95__)
+#define L1_RM_INNER_FDD (L1_INRMM_REQ_FDD)
+#define L1_RM_INNER_C2K (L1_INRMM_REQ_C2KDO)
+#define L1_RM_INNER_LTE (L1_INRMM_REQ_LTE)
+#define L1_RM_BRP_FDD (L1_RXBRP_REQ_FDD)
+#define L1_RM_BRP_LTE (L1_RXBRP_REQ_LTE)
+#define DSP_BOOT_PWR (PWR_RAKESYS|PWR_INRMMSYS|PWR_RXBRPSYS|PWR_TXSYS)
+
+#elif defined(__MD97__) || defined(__MD97P__)
+#define L1_RM_INNER_FDD (L1_INRMM_REQ_FDD)
+#define L1_RM_INNER_C2K (L1_INRMM_REQ_C2KDO)
+#define L1_RM_BRP_FDD (L1_RXBRP_REQ_FDD)
+#define DSP_BOOT_PWR (PWR_RAKESYS|PWR_INRMMSYS|PWR_RXBRPSYS)
+
+#endif
+/* for DspBootResourceControl end */
+
+#if defined(__MTK_TARGET__)
+#define F32K_CNT ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MD_TOPSM+0x850))
+#else
+#define F32K_CNT ((volatile kal_uint32*)(MODEM_TOPSM_base+0x850))
+#endif
+
+#ifndef MAX
+#define MAX(a,b) ( ( (a) > (b) ) ? (a) : (b) )
+#endif
+
+#ifndef MIN
+#define MIN(a,b) ( ( (a) < (b) ) ? (a) : (b) )
+#endif
+
+#define MAX4(a,b,c,d) MAX( MAX((a),(b)) , MAX((c),(d)) )
+#define MAX6(a,b,c,d,e,f) MAX( MAX((a),(b)) , MAX4((c),(d),(e),(f)))
+#define MAX8(a,b,c,d,e,f,g,h) MAX( MAX4((a),(b),(c),(d)) , MAX4((e),(f),(g),(h)))
+
+
+#if defined(__MD93__) /*resource settle*/
+//#define RM_SYS_CLK_SETTLE 0x66
+#define PLL_SETTLE 0x3 /* HW_WRITE( L1CORE_TOPSM_SM_CLK_SETTLE, ((PLL_SETTLE<<16) | (RM_SYS_CLK_SETTLE))); */
+
+#define MAS_TRIG_CORE0_SETTLE (0xE + 0x11)
+#define MAS_TRIG_CORE1_SETTLE (0xE + 0x11)
+#define MAS_TRIG_USIP0_SETTLE 0xB
+#define MAS_TRIG_USIP1_SETTLE 0xB
+#define MAS_TRIG_MD_COMMRES_SETTLE (0xB + 0x11)
+#define MAS_TRIG_EMI_SETTLE (0x12 + 0x11)
+/* max value of GRP settle PS_SRC0 /MIXEDSYS /PSBUS /EMI */
+/* assume Max GRP_settle1 the same as GRP_settle0*/
+
+#define MAS_TRIG_MAX_SETTLE MAX6(MAS_TRIG_CORE0_SETTLE, MAS_TRIG_CORE1_SETTLE, \
+ MAS_TRIG_USIP0_SETTLE, MAS_TRIG_USIP1_SETTLE, \
+ MAS_TRIG_MD_COMMRES_SETTLE, MAS_TRIG_EMI_SETTLE)
+
+#define TIMER_TRIG_SETTLE (0x4 + 0x11) /* HW_WRITE( L1CORE_TOPSM_SM_TIMER_TRIG_SETTLE, TIMER_TRIG_SETTLE);*/
+#define MAX_PWR_SETTLE 0x3 /* Maximun Power Settling Time */
+#define RM_RESOURCE_SETTLE ( RM_SYS_CLK_SETTLE + 4 + MAX4(PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 2 + 1)
+#define RM_RESOURCE_SETTLE_SYSCLK_FORCEON ( MAX4(PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 3 )
+
+#define MAS_TRIG_CORE0_SAL 0x6
+#define MAS_TRIG_CORE1_SAL 0x6
+#define MAS_TRIG_USIP0_SAL 0x2
+#define MAS_TRIG_USIP1_SAL 0x2
+#define MAS_TRIG_MD_COMMRES_SAL 0x2
+#define MAS_TRIG_EMI_SAL 0xA
+
+#elif defined(__MD95__) /*resource settle*/
+// James: for timer wakeup mcu dormant settle margin, add in 95.
+// LPGolden Setting might not be the same as in CODA if this value is non-zero
+#define MODEM_TOPSM_MCU_DORMANT_MARGIN 0xB // 20180322 Jun-Ying Huang: MDMCU 450M Hz + EMI Read latency: 417ns, EMI Write latency: 200ns, need 320us (Core 0 VPE 0)
+
+#define PLL_SETTLE 0x2 // according to Ver 2.0 (20180111) spec
+#if defined(MT6779) || defined(MT6785) // Lafite & Krug
+#define PRE_TRIG_SETTLE 0x9D // according to 2018/10/04 DE Wayne Liu's comment
+#else
+#define PRE_TRIG_SETTLE 0x9F // according to Ver 2.0 (20180327) spec
+#endif
+#define MAS_TRIG_CORE0_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // for Core0 power off/Core1 dormant abort issue, set core0 and core1 value the same (by Wayne Liu comment)
+#define MAS_TRIG_CORE1_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // TODO: Check if dormant margin have to be added for Core 1 & 2 settle
+#define MAS_TRIG_CORE2_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // TODO: 20170627 review if LTE requires Core 2 HW mode; ohterwise remove dormant margin
+#define MAS_TRIG_USIP_SETTLE 0x9
+#define MAS_TRIG_MD_COMMRES_SETTLE (0x11 + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to Ver 2.0 (20180111) spec
+#if defined(MT6779) || defined(MT6785) // Lafite & Krug
+#define MAS_TRIG_EMI_SETTLE (0x10 + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to 2018/10/04 DE Wayne Liu's comment
+#else
+#define MAS_TRIG_EMI_SETTLE (0xF + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to Ver 2.0 (20180327) spec
+#endif
+#define MAS_TRIG_MAX_SETTLE MAX6(MAS_TRIG_CORE0_SETTLE, MAS_TRIG_CORE1_SETTLE, \
+ MAS_TRIG_CORE2_SETTLE, MAS_TRIG_USIP_SETTLE, \
+ MAS_TRIG_MD_COMMRES_SETTLE, MAS_TRIG_EMI_SETTLE)
+
+#define TIMER_TRIG_SETTLE (0x4 + MODEM_TOPSM_MCU_DORMANT_MARGIN)
+#define MAX_PWR_SETTLE 0x2 /* Maximun Power Settling Time */
+#define RM_RESOURCE_SETTLE ( PRE_TRIG_SETTLE + RM_SYS_CLK_SETTLE + 4 + MAX4(PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 2 + 1)
+ // RM_SYS_CLK_SETTLE is defined in sleepdrv_common.h
+ // 4: 26M turn on delay; 2: MTCMOS on; 1: Total state machine enable margin (by confirm with DE Wayne)
+#define RM_RESOURCE_SETTLE_SYSCLK_FORCEON ( MAX4(PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 3 )
+
+#define MAS_TRIG_CORE0_SAL 0x6
+#define MAS_TRIG_CORE1_SAL 0x6
+#define MAS_TRIG_CORE2_SAL 0x6
+#define MAS_TRIG_USIP_SAL 0x2
+#define MAS_TRIG_MD_COMMRES_SAL 0x2
+#define MAS_TRIG_EMI_SAL 0xD // according to Ver 2.0 (20180327) spec
+
+#elif defined(__MD97__) || defined(__MD97P__)
+
+// James: for timer wakeup mcu dormant settle margin, add in 95.
+// LPGolden Setting might not be the same as in CODA if this value is non-zero
+#define MODEM_TOPSM_MCU_DORMANT_MARGIN 0xB // 20180322 Jun-Ying Huang: MDMCU 450M Hz + EMI Read latency: 417ns, EMI Write latency: 200ns, need 320us (Core 0 VPE 0)
+
+#define PLL_SETTLE 0x2 // according to Ver 2.0 (20180111) spec
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(CHIP10992)
+#define PRE_TRIG_SETTLE 0xDD // according to Petrus (20190926) spec
+#else
+#define PRE_TRIG_SETTLE 0x9B // according to Ver 2.0 (20180327) spec
+#endif
+
+#define MAS_TRIG_CORE0_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // for Core0 power off/Core1 dormant abort issue, set core0 and core1 value the same (by Wayne Liu comment)
+#define MAS_TRIG_CORE1_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // TODO: Check if dormant margin have to be added for Core 1 & 2 settle
+#define MAS_TRIG_CORE2_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // TODO: 20170627 review if LTE requires Core 2 HW mode; ohterwise remove dormant margin
+#define MAS_TRIG_CORE3_SETTLE (0xE + MODEM_TOPSM_MCU_DORMANT_MARGIN) // TODO: 20170627 review if LTE requires Core 2 HW mode; ohterwise remove dormant margin
+#if defined(MT6297)
+#define MAS_TRIG_USIP_SETTLE 0x18 // uSIP issue, should be fixed in Petrus
+#define MAS_TRIG_MD_COMMRES_SETTLE (0x18 + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to Ver 2.0 (20180111) spec
+#else
+#define MAS_TRIG_USIP_SETTLE 0xC // according to Petrus (20190926) spec
+#define MAS_TRIG_MD_COMMRES_SETTLE (0x14 + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to Petrus (20190926) spec
+#endif
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833)
+#define MAS_TRIG_EMI_SETTLE (0x15 + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to Petrus (20190926) spec
+#elif defined(CHIP10992)
+#define MAS_TRIG_EMI_SETTLE (0x28 + MODEM_TOPSM_MCU_DORMANT_MARGIN)
+#else
+#define MAS_TRIG_EMI_SETTLE (0xF + MODEM_TOPSM_MCU_DORMANT_MARGIN) // according to Ver 2.0 (20180327) spec
+#endif
+#define MAS_TRIG_RF_SETTLE 0x14
+#define MAS_TRIG_MAX_SETTLE MAX8(MAS_TRIG_CORE0_SETTLE, MAS_TRIG_CORE1_SETTLE, \
+ MAS_TRIG_CORE2_SETTLE, MAS_TRIG_CORE3_SETTLE, \
+ MAS_TRIG_USIP_SETTLE, MAS_TRIG_MD_COMMRES_SETTLE, \
+ MAS_TRIG_EMI_SETTLE, MAS_TRIG_RF_SETTLE)
+
+#define TIMER_TRIG_SETTLE MAS_TRIG_CORE0_SETTLE // ori: (0x4 + MODEM_TOPSM_MCU_DORMANT_MARGIN), align Core0 settle to prevent OST entering sleep and dormant flow if Core0 is awake and other RATs wakeup
+#define MAX_PWR_SETTLE 0x2 /* Maximun Power Settling Time */
+#define RM_RESOURCE_SETTLE ( PRE_TRIG_SETTLE + RM_SYS_CLK_SETTLE + 4 + MAX4(PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 2 + 3)
+ // RM_SYS_CLK_SETTLE is defined in sleepdrv_common.h
+ // 4: 26M turn on delay; 2: MTCMOS on; 1: Total state machine enable margin (by confirm with DE Wayne)
+#define RM_RESOURCE_SETTLE_SYSCLK_FORCEON ( MAX4(PLL_SETTLE, MAX_PWR_SETTLE, MAS_TRIG_MAX_SETTLE, TIMER_TRIG_SETTLE) + 3 + 3)
+
+#define MAS_TRIG_CORE0_SAL 0x6
+#define MAS_TRIG_CORE1_SAL 0x6
+#define MAS_TRIG_CORE2_SAL 0x6
+#define MAS_TRIG_CORE3_SAL 0x6
+#define MAS_TRIG_USIP_SAL 0x2
+#define MAS_TRIG_MD_COMMRES_SAL 0x2
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(MT6833) || defined(CHIP10992)
+#define MAS_TRIG_EMI_SAL 0x2 // according to Petrus (20190926) spec
+#else
+#define MAS_TRIG_EMI_SAL 0xD // according to Ver 2.0 (20180327) spec
+#endif
+#define MAS_TRIG_RF_SAL 0x2
+
+#else /*resource settle*/
+
+#error "please check the resource settle of modem topsm"
+
+#endif /*resource settle*/
+
+kal_int32 L1I_GetTimeStampEbits(void);
+kal_uint32 L1I_GetTimeStamp(void);
+void L1_RM_Resource_Control( L1_RM_Module module, kal_bool resource_on );
+kal_bool L1_RM_Resource_CheckReady( L1_RM_Module module );
+kal_bool L1_RM_Resource_CheckReadyMask( kal_uint32 module_mask );
+kal_uint32 L1_RM_Resource_GetReady( void );
+
+#if defined(__MD93__) || defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+extern kal_uint32 MODEM_TOPSM_GetF32k(void);
+#define RM_GetF32k() MODEM_TOPSM_GetF32k()
+#endif
+
+extern void L1_RM_UL1Resource_SWControl(kal_bool resource_on);
+extern kal_bool L1_RM_RFSLPC_CheckReady(void);
+extern void MODEM_TOPSM_DMC_PowerControl(kal_bool on);
+//extern void MODEM_TOPSM_MD2G_PowerControl(kal_bool on); // 93 & 95 audio is no use, now, use MD_TOPSM_PWR_SW_Control(USIP0_PWR, KAL_TRUE)
+extern kal_bool MODEM_TOPSM_CheckPowerRdy(kal_uint32 mask);
+extern kal_uint32 MODEM_TOPSM_GetPowerRdy(void);
+
+extern void MODEM_TOPSM_SW_PowerControl(MODEM_TOPSM_TIMER_MODULE timer, kal_uint32 mask, kal_bool on);
+extern void MODEM_TOPSM_ClearPowerRdyReg(kal_uint32 mask);
+extern kal_bool MODEM_TOPSM_CheckPowerRdyReg(kal_uint32 mask);
+extern void MODEM_TOPSM_BypassBRP4GHWMode(void);
+extern void MODEM_TOPSM_ResumeBRP4GHWMode(void);
+extern MODEM_TOPSM_TIMER_STATUS MODEM_TOPSM_GetTimerStatus(MODEM_TOPSM_TIMER_MODULE timer);
+extern void MODEM_TOPSM_ForceOnMTCMOS(kal_uint32 mask);
+extern void MODEM_TOPSM_NonForceOnMTCMOS(kal_uint32 mask);
+extern void MODEM_TOPSM_ForceOnPLL(kal_uint32 mask);
+extern void MODEM_TOPSM_NonForceOnPLL(kal_uint32 mask);
+extern void MODEM_TOPSM_ForceOnClockForDVFS(kal_bool enable);
+extern kal_bool MODEM_TOPSM_ForceOnDBGCK(void);
+extern void MODEM_TOPSM_DisableForceOnDBGCK(void);
+extern void MODEM_TOPSM_SW_TRIG_CSYS(kal_bool enable);
+extern void MODEM_TOPSM_4GTXHWModeEnable(void);
+extern void MODEM_TOPSM_4GTXHWModeDisable(void);
+extern void MODEM_TOPSM_5GTXHWModeEnable(void);
+extern void MODEM_TOPSM_5GTXHWModeDisable(void);
+extern void MODEM_TOPSM_4GTX_METAControl(kal_bool on);
+extern void MODEM_TOPSM_ForceOnLogResource(kal_bool enable);
+extern void MODEM_TOPSM_ForceOnAllResource(void);
+
+extern kal_bool RF_SLPC_CheckPowerRdyReg(void);
+
+/* Should remove later */
+//extern void MODEM_TOPSM_SetGPSSyncCon0(kal_uint32 value);
+//extern void MODEM_TOPSM_SetGPSSyncCon1(kal_uint32 value);
+
+extern void MODEM_TOPSM_ForceOn26M(kal_bool enable, MODEM_TOPSM_TIMER_MODULE timer);
+extern void MODEM_TOPSM_ForceOnVRF18(kal_bool enable);
+extern void MODEM_TOPSM_ForceOffVRF18(kal_bool enable);
+#if defined(__MD95__)
+extern kal_bool MODEM_TOPSM_ForceOn_PreTrig(kal_bool enable);
+#endif
+extern kal_bool MODEM_TOPSM_TPPA_Dump_Current_Info(void);
+
+#ifdef L1_SIM
+extern void MODEM_TOPSM_Check_Off();
+#endif
+extern kal_uint32 MODEM_TOPSM_GetPllStatus(void);
+
+extern void MEM_CONF_BIGRAM_TYPE_CONTROL(kal_bool is_sleep_type);
+extern void MEM_CONF_RAKECentralControl(MEM_CG_CTRL_CLIENT_ENUM client, kal_uint32 value);
+extern void CG_CTRL_RAKECentralControl(MEM_CG_CTRL_CLIENT_ENUM client, kal_uint32 value);
+extern void MEM_CONF_SRAM_PowerDownSetting(MEM_CONF_SRAM_CTRL_CLIENT_ENUM client);
+extern void MEM_CONF_SRAM_PowerOnSetting(MEM_CONF_SRAM_CTRL_CLIENT_ENUM client);
+
+/* Should remove later */
+
+/*for fm related function interface for other module outside the driver*/
+extern void FM_ReCalibration(void);
+extern void FM_SetCalibrationResult( kal_uint32 fm_dur, kal_uint32 fm_freq, kal_uint32 fmResult );
+extern void FM_GetCalibrationResult( kal_uint32 *fm_dur_ptr, kal_uint32 *fm_freq_ptr, kal_uint32 *fmResult_ptr );
+extern kal_bool FM_IsCalibrating(void);
+
+extern void MDLPM_SIM_Active_RAT_Info(MDLPM_SIM_INDEX sim_index, MDLPM_ACTIVE_RAT_INDEX rat_index, kal_uint32 drx_ms);
+extern void MDLPM_Data_Mapping( void );
+
+#if defined(__MD97__) || defined(__MD97P__)
+extern void RF_SLPC_Wakeup();
+extern void RF_SLPC_Sleep();
+extern void L1_RM_RFSLPC_SWControl(kal_bool resource_on);
+extern void L1_RM_RFSLPC_SWControl_Serdes(kal_bool resource_on);
+extern void RF_TOPSM_DebugRecord(void);
+extern void RF_SLPC_DebugRecord(void);
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+#if defined( __MTK_UL1_FDD__ )
+kal_uint16 SleepDrv_RTOS_CheckSleepGsm( void );
+#endif /* __MTK_UL1_FDD__ */
+#ifdef __MTK_UL1_FDD__
+kal_bool SleepDrv_RTOS_CheckSleepUmts( void );
+#endif /* __MTK_UL1_FDD__ */
+#if defined( __LTE_RAT__ )
+kal_bool SleepDrv_RTOS_CheckSleepLTE( void );
+#endif /* __LTE_RAT__ */
+#if defined( __NR_RAT__ )
+kal_uint16 SleepDrv_RTOS_CheckSleepNR( void );
+#endif /* __NR_RAT__ */
+
+#endif
diff --git a/mcu/interface/driver/sleep_drv/ostd_public.h b/mcu/interface/driver/sleep_drv/ostd_public.h
new file mode 100644
index 0000000..27e1bcd
--- /dev/null
+++ b/mcu/interface/driver/sleep_drv/ostd_public.h
@@ -0,0 +1,668 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ostd_public.h
+ *
+ * Project:
+ * --------
+ * MTK6276
+ *
+ * Description:
+ * ------------
+ * This is the driver layer and corresponding Sleep Mode of ARM OS Timer HW
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
+ *
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+ *
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+ *
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
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+ *
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if 1
+
+#ifndef OSTD_PUBLIC_H
+#define OSTD_PUBLIC_H
+
+#include "kal_general_types.h"
+#ifndef L1_SIM
+#include "ps_public_enum.h"
+#endif
+
+typedef void (*AP_STATUS_CHAGE_CALLBACK) (kal_uint32 ap_status);
+
+typedef enum
+{
+ OSTD_SUCCESS_FALSE = 0, /*OSTD read back AFN/UFN and found that current value is <=2*/
+ OSTD_SUCCESS_TRUE, /*OSTD has successfully set the AFN value into ARM OS Timer HW*/
+ OSTD_TIME_OUT, /*OSTD failed to poll ready bit*/
+ OSTD_FAIL, /* Other unknown fail reason */
+ OSTD_RESULT_NUM
+} OSTD_RESULT_E;
+
+typedef struct _OSTD_FRM_INFO_T
+{
+ kal_uint32 curr_afn; /* for OSTD to fill back current AFN value */
+ kal_uint32 curr_ufn; /* for OSTD to fill back current UFN value */
+ kal_uint32 curr_afn_dly; /* for OSTD to fill back current AFN_DLY value */
+} OSTD_FRM_INFO_T;
+
+typedef struct
+{
+ char* module_name;
+ module_type mod_id;
+ AP_STATUS_CHAGE_CALLBACK funp;
+ kal_bool pending_urc;
+} ostd_urc_src_module_info_struct;
+
+typedef enum _OSTD_TIMER_TYPE_E
+{
+ OSTD_OST,
+ OSTD_2G,
+ OSTD_3G_FDD,
+ OSTD_3G_TDD,
+ OSTD_3G_C2K_1X,
+ OSTD_3G_C2K_DO,
+ OSTD_4G,
+ OSTD_5G,
+ OSTD_TIMER_MAX
+} OSTD_TIMER_TYPE_E;
+
+typedef enum {
+ OSTD_BUSY,
+ OSTD_WAIT,
+ OSTD_DORMANT
+} kal_checksleep_e;
+
+typedef enum {
+ OSTD_ChkSlp_No_InfiniteSleep,
+ OSTD_ChkSlp_EFUN_CFUN,
+ OSTD_ChkSlp_EPOF
+} kal_chkslp_inf_e;
+
+typedef enum {
+ OSTD_IDLE_VPE0_ENTER,
+ OSTD_IDLE_VPE0_LEAVE,
+ OSTD_IDLE_VPE1_ENTER,
+ OSTD_IDLE_VPE1_LEAVE,
+ OSTD_IDLE_CALCULATE,
+ OSTD_IDLE_PRINT
+} kal_idlerate_e;
+
+#if defined(__MD97__)
+#if defined(CHIP10992)
+typedef enum
+{
+ EVENT_l1sm_timer_trig_F32K = 0,
+ EVENT_mdsm_timer_trig_F32K = 1,
+ EVENT_dem_trig_md_int_le_F32K = 2,
+ EVENT_fe_md_share_d12mint1_b_F32K = 3,
+ EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4,
+ EVENT_mcu_bus_decerr_irq_F32K = 5,
+ EVENT_usip_ia_ostimer_wakeup_b_F32K = 6,
+ EVENT_cs_nr_irq_F32K = 7,
+ EVENT_cs_err_irq_F32K = 8,
+ EVENT_ulsp_log_md_rt_int_F32K = 9,
+ EVENT_ulsp_log_md_od_int_F32K = 10,
+ EVENT_ulsp_log_dsp4g_rt_int_F32K = 11,
+ EVENT_ulsp_log_dsp4g_od_int_F32K = 12,
+ EVENT_ulsp_log_dsp5g_rt_int_F32K = 13,
+ EVENT_ulsp_log_dsp5g_od_int_F32K = 14,
+ EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15,
+ EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16,
+ EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 17,
+ EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 18,
+ EVENT_mml1_dspcsif_top_err_cirq_F32K = 19,
+ EVENT_ap2md_usb_rx_not_empty_F32K = 20,
+ EVENT_ap2md_usb_rx_gpd_done_F32K = 21,
+ EVENT_ap2md_usb_dma_active_F32K = 22,
+ EVENT_ap2md_usb_ip_wakeup_F32K = 23,
+ EVENT_ap2md_usb_mcu_irq_b_F32K = 24,
+ EVENT_ap2md_ssusb_rx_not_empty_F32K = 25,
+ EVENT_ap2md_ssusb_rx_gpd_done_F32K = 26,
+ EVENT_ap2md_ssusb_dma_active_F32K = 27,
+ EVENT_ap2md_ssusb_ip_wakeup_F32K = 28,
+ EVENT_ap2md_ssusb_dev_int_b_F32K = 29,
+ EVENT_ap2md_ccif0_md_event_b_F32K = 30,
+ EVENT_ap2md_ccif1_md_event_b_F32K = 31,
+ EVENT_ap2md_cldma_ip_busy_F32K = 32,
+ EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 33,
+ EVENT_conn2md_pdma_irq_b_F32K = 34,
+ EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 35,
+ EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 36,
+ EVENT_ipsec_so_int_lv_F32K = 37,
+ EVENT_conn_bt_cvsd_int_b_F32K = 38,
+ EVENT_conn_bt_isoch_irq_b_F32K = 39,
+ EVENT_rgu2md_irq_b_F32K = 40,
+ EVENT_ap2md_ccif2_md_event_b_F32K = 41,
+ EVENT_mhccif_sap2md_event_b_F32K = 42,
+ EVENT_ap2md_apmcu_suspend_irq_F32K = 43,
+ EVENT_ap2md_apmcu_active_irq_F32K = 44,
+ EVENT_eint_event0_F32K = 45,
+ EVENT_eint_event1_F32K = 46,
+ EVENT_eint_event2_F32K = 47,
+ EVENT_eint_event3_F32K = 48,
+ EVENT_eint_event4_F32K = 49,
+ EVENT_eint_event5_F32K = 50,
+ EVENT_eint_event6_F32K = 51,
+ EVENT_eint_event7_F32K = 52,
+ EVENT_eint_event8_F32K = 53,
+ EVENT_eint_event9_F32K = 54,
+ EVENT_eint_event10_F32K = 55,
+ EVENT_eint_event11_F32K = 56,
+ EVENT_ap2md_cldma0_md_ip_busy_lv_md_F32K = 57,
+ EVENT_ap2md_cldma1_md_ip_busy_lv_md_F32K = 58,
+ EVENT_ap2md_cldma2_md_ip_busy_lv_md_F32K = 59,
+ EVENT_ap2md_cldma3_md_ip_busy_lv_md_F32K = 60,
+ EVENT_pcie_interrupt_out_F32K = 61,
+
+ EVENT_l1sm_timer_trig_NON_F32K = 64,
+ EVENT_mdsm_timer_trig_NON_F32K = 65,
+ EVENT_dem_trig_md_int_le_NON_F32K = 66,
+ EVENT_fe_md_share_d12mint1_b_NON_F32K = 67,
+ EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68,
+ EVENT_mcu_bus_decerr_irq_NON_F32K = 69,
+ EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70,
+ EVENT_cs_nr_irq_NON_F32K,
+ EVENT_cs_err_irq_NON_F32K,
+ EVENT_ulsp_log_md_rt_int_NON_F32K = 73,
+ EVENT_ulsp_log_md_od_int_NON_F32K = 74,
+ EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75,
+ EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76,
+ EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77,
+ EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78,
+ EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79,
+ EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80,
+ EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K = 81,
+ EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K = 82,
+ EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 83,
+ EVENT_ap2md_usb_rx_not_empty_NON_F32K = 84,
+ EVENT_ap2md_usb_rx_gpd_done_NON_F32K = 85,
+ EVENT_ap2md_usb_dma_active_NON_F32K = 86,
+ EVENT_ap2md_usb_ip_wakeup_NON_F32K = 87,
+ EVENT_ap2md_usb_mcu_irq_b_NON_F32K = 88,
+ EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 89,
+ EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K = 90,
+ EVENT_ap2md_ssusb_dma_active_NON_F32K = 91,
+ EVENT_ap2md_ssusb_ip_wakeup_NON_F32K = 92,
+ EVENT_ap2md_ssusb_dev_int_b_NON_F32K = 93,
+ EVENT_ap2md_ccif0_md_event_b_NON_F32K = 94,
+ EVENT_ap2md_ccif1_md_event_b_NON_F32K = 95,
+ EVENT_ap2md_cldma_ip_busy_NON_F32K = 96,
+ EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 97,
+ EVENT_conn2md_pdma_irq_b_NON_F32K = 98,
+ EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 99,
+ EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 100,
+ EVENT_ipsec_so_int_lv_NON_F32K = 101,
+ EVENT_conn_bt_cvsd_int_b_NON_F32K = 102,
+ EVENT_conn_bt_isoch_irq_b_NON_F32K = 103,
+ EVENT_rgu2md_irq_b_NON_F32K = 104,
+ EVENT_ap2md_ccif2_md_event_b_NON_F32K = 105,
+ EVENT_mhccif_sap2md_event_b_NON_F32K = 106,
+ EVENT_ap2md_apmcu_suspend_irq_NON_F32K = 107,
+ EVENT_ap2md_apmcu_active_irq_NON_F32K = 108,
+ EVENT_eint_event0_NON_F32K = 109,
+ EVENT_eint_event1_NON_F32K = 110,
+ EVENT_eint_event2_NON_F32K = 111,
+ EVENT_eint_event3_NON_F32K = 112,
+ EVENT_eint_event4_NON_F32K = 113,
+ EVENT_eint_event5_NON_F32K = 114,
+ EVENT_eint_event6_NON_F32K = 115,
+ EVENT_eint_event7_NON_F32K = 116,
+ EVENT_eint_event8_NON_F32K = 117,
+ EVENT_eint_event9_NON_F32K = 118,
+ EVENT_eint_event10_NON_F32K = 119,
+ EVENT_eint_event11_NON_F32K = 120,
+ EVENT_ap2md_cldma0_md_ip_busy_lv_md_NON_F32K = 121,
+ EVENT_ap2md_cldma1_md_ip_busy_lv_md_NON_F32K = 122,
+ EVENT_ap2md_cldma2_md_ip_busy_lv_md_NON_F32K = 123,
+ EVENT_ap2md_cldma3_md_ip_busy_lv_md_NON_F32K = 124,
+ EVENT_pcie_interrupt_out_NON_F32K = 125,
+} sm_event_e;
+#elif defined(MT6885)
+typedef enum
+{
+ EVENT_l1sm_timer_trig_F32K = 0,
+ EVENT_mdsm_timer_trig_F32K = 1,
+ EVENT_dem_trig_md_int_le_F32K = 2,
+ EVENT_fe_md_share_d12mint1_b_F32K = 3,
+ EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4,
+ EVENT_mcu_bus_decerr_irq_F32K = 5,
+ EVENT_usip_ia_ostimer_wakeup_b_F32K = 6,
+ EVENT_cs_nr_irq_F32K,
+ EVENT_cs_err_irq_F32K,
+ EVENT_ulsp_log_md_rt_int_F32K = 9,
+ EVENT_ulsp_log_md_od_int_F32K = 10,
+ EVENT_ulsp_log_dsp4g_rt_int_F32K = 11,
+ EVENT_ulsp_log_dsp4g_od_int_F32K = 12,
+ EVENT_ulsp_log_dsp5g_rt_int_F32K = 13,
+ EVENT_ulsp_log_dsp5g_od_int_F32K = 14,
+ EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15,
+ EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16,
+ EVENT_vcore_mml1_dsppmu_top_emi_irq_F32K = 17,
+ EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 18,
+ EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 19,
+ EVENT_mml1_dspcsif_top_err_cirq_F32K = 20,
+ EVENT_ap2md_usb_rx_not_empty_F32K,
+ EVENT_ap2md_usb_rx_gpd_done_F32K = 22,
+ EVENT_ap2md_usb_dma_active_F32K,
+ EVENT_ap2md_usb_ip_wakeup_F32K = 24,
+ EVENT_ap2md_usb_mcu_irq_b_F32K =25,
+ EVENT_ap2md_ssusb_rx_not_empty_F32K,
+ EVENT_ap2md_ssusb_rx_gpd_done_F32K = 27,
+ EVENT_ap2md_ssusb_dma_active_F32K,
+ EVENT_ap2md_ssusb_ip_wakeup_F32K = 29,
+ EVENT_ap2md_ssusb_dev_int_b_F32K = 30,
+ EVENT_ap2md_ccif0_md_event_b_F32K = 31,
+ EVENT_ap2md_ccif1_md_event_b_F32K = 32,
+ EVENT_ap2md_cldma_ip_busy_F32K = 33,
+ EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 34,
+ EVENT_conn2md_pdma_irq_b_F32K = 35,
+ EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 36,
+ EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 37,
+ EVENT_ipsec_so_int_lv_F32K = 38,
+ EVENT_conn_bt_cvsd_int_b_F32K = 39,
+ EVENT_conn_bt_isoch_irq_b_F32K = 40,
+ EVENT_eint_int_lv_F32K = 41,
+ EVENT_eint_event0_F32K = 42,
+ EVENT_eint_event1_F32K = 43,
+ EVENT_eint_event2_F32K = 44,
+ EVENT_eint_event3_F32K = 45,
+ EVENT_rgu2md_irq_b_F32K = 46,
+ EVENT_ap2md_ccif2_md_event_b_F32K = 47,
+
+ EVENT_l1sm_timer_trig_NON_F32K = 64,
+ EVENT_mdsm_timer_trig_NON_F32K = 65,
+ EVENT_dem_trig_md_int_le_NON_F32K,
+ EVENT_fe_md_share_d12mint1_b_NON_F32K = 67,
+ EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68,
+ EVENT_mcu_bus_decerr_irq_NON_F32K = 69,
+ EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70,
+ EVENT_cs_nr_irq_NON_F32K,
+ EVENT_cs_err_irq_NON_F32K,
+ EVENT_ulsp_log_md_rt_int_NON_F32K = 73,
+ EVENT_ulsp_log_md_od_int_NON_F32K = 74,
+ EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75,
+ EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76,
+ EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77,
+ EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78,
+ EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79,
+ EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80,
+ EVENT_vcore_mml1_dsppmu_top_emi_irq_NON_F32K = 81,
+ EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K,
+ EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K,
+ EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 84,
+ EVENT_ap2md_usb_rx_not_empty_NON_F32K = 85,
+ EVENT_ap2md_usb_rx_gpd_done_NON_F32K,
+ EVENT_ap2md_usb_dma_active_NON_F32K = 87,
+ EVENT_ap2md_usb_ip_wakeup_NON_F32K,
+ EVENT_ap2md_usb_mcu_irq_b_NON_F32K,
+ EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 90,
+ EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K,
+ EVENT_ap2md_ssusb_dma_active_NON_F32K = 92,
+ EVENT_ap2md_ssusb_ip_wakeup_NON_F32K,
+ EVENT_ap2md_ssusb_dev_int_b_NON_F32K,
+ EVENT_ap2md_ccif0_md_event_b_NON_F32K = 95,
+ EVENT_ap2md_ccif1_md_event_b_NON_F32K = 96,
+ EVENT_ap2md_cldma_ip_busy_NON_F32K = 97,
+ EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 98,
+ EVENT_conn2md_pdma_irq_b_NON_F32K = 99,
+ EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 100,
+ EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 101,
+ EVENT_ipsec_so_int_lv_NON_F32K = 102,
+ EVENT_conn_bt_cvsd_int_b_NON_F32K = 103,
+ EVENT_conn_bt_isoch_irq_b_NON_F32K = 104,
+ EVENT_eint_int_lv_NON_F32K = 105,
+ EVENT_eint_event0_NON_F32K = 106,
+ EVENT_eint_event1_NON_F32K = 107,
+ EVENT_eint_event2_NON_F32K = 108,
+ EVENT_eint_event3_NON_F32K = 109,
+ EVENT_rgu2md_irq_b_NON_F32K = 110,
+ EVENT_ap2md_ccif2_md_event_b_NON_F32K = 111,
+} sm_event_e;
+#else
+typedef enum
+{
+ EVENT_l1sm_timer_trig_F32K = 0,
+ EVENT_mdsm_timer_trig_F32K = 1,
+ EVENT_dem_trig_md_int_le_F32K = 2,
+ EVENT_fe_md_share_d12mint1_b_F32K = 3,
+ EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4,
+ EVENT_mcu_bus_decerr_irq_F32K = 5,
+ EVENT_usip_ia_ostimer_wakeup_b_F32K = 6,
+ EVENT_cs_nr_irq_F32K,
+ EVENT_cs_err_irq_F32K,
+ EVENT_ulsp_log_md_rt_int_F32K = 9,
+ EVENT_ulsp_log_md_od_int_F32K = 10,
+ EVENT_ulsp_log_dsp4g_rt_int_F32K = 11,
+ EVENT_ulsp_log_dsp4g_od_int_F32K = 12,
+ EVENT_ulsp_log_dsp5g_rt_int_F32K = 13,
+ EVENT_ulsp_log_dsp5g_od_int_F32K = 14,
+ EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15,
+ EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16,
+ EVENT_vcore_mml1_dsppmu_top_emi_irq_F32K = 17,
+ EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 18,
+ EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 19,
+ EVENT_mml1_dspcsif_top_err_cirq_F32K = 20,
+ EVENT_ap2md_usb_rx_not_empty_F32K,
+ EVENT_ap2md_usb_rx_gpd_done_F32K = 22,
+ EVENT_ap2md_usb_dma_active_F32K,
+ EVENT_ap2md_usb_ip_wakeup_F32K = 24,
+ EVENT_ap2md_usb_mcu_irq_b_F32K =25,
+ EVENT_ap2md_ssusb_rx_not_empty_F32K,
+ EVENT_ap2md_ssusb_rx_gpd_done_F32K = 27,
+ EVENT_ap2md_ssusb_dma_active_F32K,
+ EVENT_ap2md_ssusb_ip_wakeup_F32K = 29,
+ EVENT_ap2md_ssusb_dev_int_b_F32K = 30,
+ EVENT_ap2md_ccif0_md_event_b_F32K = 31,
+ EVENT_ap2md_ccif1_md_event_b_F32K = 32,
+ EVENT_ap2md_cldma_ip_busy_F32K = 33,
+ EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 34,
+ EVENT_conn2md_pdma_irq_b_F32K = 35,
+ EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 36,
+ EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 37,
+ EVENT_ipsec_so_int_lv_F32K = 38,
+ EVENT_conn_bt_cvsd_int_b_F32K = 39,
+ EVENT_conn_bt_isoch_irq_b_F32K = 40,
+ EVENT_eint_int_lv_F32K = 41,
+ EVENT_eint_event0_F32K = 42,
+ EVENT_eint_event1_F32K = 43,
+ EVENT_eint_event2_F32K = 44,
+ EVENT_eint_event3_F32K = 45,
+ EVENT_rgu2md_irq_b_F32K = 46,
+ EVENT_ap2md_ccif2_md_event_b_F32K = 47,
+ EVENT_ap2md_apmcu_suspend_irq_F32K = 48,
+ EVENT_ap2md_apmcu_active_irq_F32K = 49,
+
+ EVENT_l1sm_timer_trig_NON_F32K = 64,
+ EVENT_mdsm_timer_trig_NON_F32K = 65,
+ EVENT_dem_trig_md_int_le_NON_F32K,
+ EVENT_fe_md_share_d12mint1_b_NON_F32K = 67,
+ EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68,
+ EVENT_mcu_bus_decerr_irq_NON_F32K = 69,
+ EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70,
+ EVENT_cs_nr_irq_NON_F32K,
+ EVENT_cs_err_irq_NON_F32K,
+ EVENT_ulsp_log_md_rt_int_NON_F32K = 73,
+ EVENT_ulsp_log_md_od_int_NON_F32K = 74,
+ EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75,
+ EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76,
+ EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77,
+ EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78,
+ EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79,
+ EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80,
+ EVENT_vcore_mml1_dsppmu_top_emi_irq_NON_F32K = 81,
+ EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K,
+ EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K,
+ EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 84,
+ EVENT_ap2md_usb_rx_not_empty_NON_F32K = 85,
+ EVENT_ap2md_usb_rx_gpd_done_NON_F32K,
+ EVENT_ap2md_usb_dma_active_NON_F32K = 87,
+ EVENT_ap2md_usb_ip_wakeup_NON_F32K,
+ EVENT_ap2md_usb_mcu_irq_b_NON_F32K,
+ EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 90,
+ EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K,
+ EVENT_ap2md_ssusb_dma_active_NON_F32K = 92,
+ EVENT_ap2md_ssusb_ip_wakeup_NON_F32K,
+ EVENT_ap2md_ssusb_dev_int_b_NON_F32K,
+ EVENT_ap2md_ccif0_md_event_b_NON_F32K = 95,
+ EVENT_ap2md_ccif1_md_event_b_NON_F32K = 96,
+ EVENT_ap2md_cldma_ip_busy_NON_F32K = 97,
+ EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 98,
+ EVENT_conn2md_pdma_irq_b_NON_F32K = 99,
+ EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 100,
+ EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 101,
+ EVENT_ipsec_so_int_lv_NON_F32K = 102,
+ EVENT_conn_bt_cvsd_int_b_NON_F32K = 103,
+ EVENT_conn_bt_isoch_irq_b_NON_F32K = 104,
+ EVENT_eint_int_lv_NON_F32K = 105,
+ EVENT_eint_event0_NON_F32K = 106,
+ EVENT_eint_event1_NON_F32K = 107,
+ EVENT_eint_event2_NON_F32K = 108,
+ EVENT_eint_event3_NON_F32K = 109,
+ EVENT_ap2md_apmcu_suspend_irq_NON_F32K = 110,
+ EVENT_ap2md_apmcu_active_irq_NON_F32K = 111,
+} sm_event_e;
+#endif
+#endif
+
+/*****************************************************************************
+* Functions provided by OSTD
+*****************************************************************************/
+
+/* For ARM Side OS Timer Upper Layer */
+extern void OSTD_Init( void );
+extern void OSTD_EnOST( kal_bool enable );
+extern void OSTD_SetFrmDur( kal_uint16 frm_dur );
+extern void OSTD_GetCurrFrm( OSTD_FRM_INFO_T *pFrm_Info );
+extern OSTD_RESULT_E OSTD_SetAfn( kal_uint32 afn );
+extern OSTD_RESULT_E OSTD_SetUfn( kal_uint32 ufn );
+extern OSTD_RESULT_E OSTD_SetAfnUfn( kal_uint32 afn,kal_uint32 ufn );
+
+
+/* For ARM Side OS Timer Sleep Mode Manager */
+extern kal_checksleep_e OSTD_CheckSleep( void );
+extern void OSTD_CSC_handler( void );
+extern kal_uint32 OSTD_CheckIsSleepLock(void);
+
+/* For AT CMD of AT+SLEEPCOUNT */
+extern kal_bool OSTD_SleepCountGet( kal_uint32 * cnt, kal_uint32 * time, kal_uint32 * acc_time );
+extern kal_bool OSTD_SleepCountSet( kal_uint32 op );
+extern kal_bool OSTD_GetModemSleepTime( kal_uint32 *acc_time );
+
+/* For Modem Infinite Sleep */
+extern kal_bool OSTD_Radio_On_Query(void);
+extern kal_bool OSTD_Infinite_Sleep_Query(void);
+extern kal_chkslp_inf_e OSTD_chkslp_is_all_timers_infinite_sleep(void);
+extern OSTD_RESULT_E OSTD_MD_Infinite_Sleep(void);
+extern OSTD_RESULT_E OSTD_Infinite_Sleep_TimerInform(OSTD_TIMER_TYPE_E timer, kal_bool sta);
+extern void OSTD_Radio_ON(void);
+extern void OSTD_Radio_OFF(void);
+extern void OSTD_Radio_OFF_SleepCheck(void);
+extern void OSTD_UnmaskIRQ( void );
+
+/* For Power Modelling */
+extern void OSTD_Idle_Rate_Logging(kal_uint32);
+
+/* For Mumtas*/
+#ifndef L1_SIM
+extern ostd_ap_core_status_enum OSTD_return_AP_status(void);
+extern void is_pending_data(char* module_name, kal_bool flag);
+#endif
+#endif
+
+#endif /*__CENTRALIZED_SLEEP_MANAGER__*/
+
diff --git a/mcu/interface/driver/sleep_drv/sleepdrv_common.h b/mcu/interface/driver/sleep_drv/sleepdrv_common.h
new file mode 100644
index 0000000..a1c271a
--- /dev/null
+++ b/mcu/interface/driver/sleep_drv/sleepdrv_common.h
@@ -0,0 +1,429 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sleepdrv_common.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is a common include file for l1core & pcore dual-core
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Log$
+ *
+ * 02 01 2021 pj.chen
+ * [MOLY00622176] [Colgin][MT6880][MD_Sanity][MCD][core0,vpe0,tc0(vpe0)] Assert fail: pll_gen97.c 525 0x1 0x1a 0x2222 - 0IDLE
+ *
+ * Increase 26M settle time
+ *
+ * 01 22 2021 pj.chen
+ * [MOLY00620543] [Colgin][MT6880][MD_Sanity][MCD][core0,vpe0,tc0(vpe0)] Assert fail: MD_TOPSM.c 1923 0x6 0x0 0x0 - 0IDLE
+ *
+ * Increase EMI settle time (MD700)
+ *
+ * 11 11 2020 pj.chen
+ * [MOLY00554988] [Colgin] Sync code from T700.MP for sleep_drv
+ * Code sync from T700.MP to MD700.MP
+ *
+ * 04 15 2020 guo-huei.chang
+ * [MOLY00509323] [Gen97] Power Model
+ * Power model (Sleep Driver Part)
+ * global variable from UnCache to Cache
+ *
+ * 04 06 2020 guo-huei.chang
+ * [MOLY00509323] [Gen97] Power Model
+ *
+ * Power model (Sleep Driver Part)
+ *
+ * 02 04 2020 owen.ho
+ * [MOLY00476151] [HCR][MT6873][Margux][Q0][MP2][SQC][MTBF][ErrorTimes:4]Externel (EE),0,0,99,/data/vendor/core/,1,modem,Trigger time:[2020-01-17 18:21:13.978100] md1:(MCU_core0.vpe0.tc0(VPE0)) [ASSERT] file:mcu/driver/devdrv/pll/src/pll_gen97.c line:494
+ *
+ * Rollback 26m settle time due to SPMFW bug fixed
+ *
+ * 12 03 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Update 26m settle for Margaux
+ *
+ * 09 25 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ *
+ * 1.Update 26m and apsrc settle time
+ * 2.Check 26m ready by ack
+ *
+ * 09 23 2019 guo-huei.chang
+ * [MOLY00442253] 5G Feature �\��API �ݨD
+ *
+ * MDLPM for customer
+ *
+ * 09 02 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Update low power related golden settings(26m/emi settle)
+ *
+ * 08 28 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Update sleep mode golden settings
+ *
+ * 07 01 2019 ws.yan
+ * [MOLY00417187] Gen97 sleep mode development: add MD97P option amd update rf topsm golden setting
+ *
+ * .
+ * [EWSP0000021808]
+ *
+ * 06 24 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Unify definition for 26m settle time
+ *
+ * 01 30 2019 leon.yeh
+ * [MOLY00381082] [Gen97] Modem Sleep UMOLYE merge back [ERS00028734]
+ * - add 2G slave (SW) trigger TXSYS power enum
+ * - TOPDM setting change based on DE spec for Lafite
+ * .
+ *
+ * 01 02 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Drvtest environment
+ *
+ * 11 26 2018 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Merge from VMOLY
+ *
+ * 10 19 2018 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Update golden settings
+ *
+ * 08 17 2018 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Integrate Gen97 driver from UMOYE.Gen97.DEV
+ *
+ * 05 18 2018 owen.ho
+ * [MOLY00312416] [Gen97] Sleep driver development
+ * Gen97 sleep driver
+ *
+ * 03 09 2018 owen.ho
+ * [MOLY00312416] [Gen97] Sleep driver development
+ * Solve build error for Gen97
+ * 06 14 2018 che-wei.chang
+ * [MOLY00333397] [TOPSM/OST] remove legacy code and log reduction
+ *
+ * 05 16 2018 che-wei.chang
+ * [MOLY00318930] [Eiger] topsm/ost - update 26m settle time
+ *
+ * 05 09 2018 che-wei.chang
+ * [MOLY00318930] [Eiger] topsm/ost - modify 26m setle time to 154T
+ *
+ * 03 14 2018 che-wei.chang
+ * [MOLY00281049] [93/95 re-arch] MD topsm/ost - update 26m settle time to 143T+4T
+ *
+ * 03 09 2018 che-wei.chang
+ * [MOLY00281049] [93/95 re-arch] MD topsm/ost - modify 95 26m settle time
+ *
+ * 01 18 2018 leon.yeh
+ * [MOLY00283840] [93/95 re-arch][MT6295] code merge - modem topsm setting for pre antenna trigger modify according to Ver 2.0 (20180111) spec.
+ *
+ * 11 30 2017 owen.ho
+ * [MOLY00293253] [MT6771][Sylvia]DCXO_RDY_WO_ACK assert after Dormant
+ * Modify 26m settle time
+ *
+ * 03 03 2017 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Update sys_clk settle time
+ *
+ * 01 20 2017 guo-huei.chang
+ * [MOLY00207227] [MT6293] Sleep Driver
+ * add flight mode support for C2K
+ *
+ * 11 02 2016 guo-huei.chang
+ * [MOLY00207227] [MT6293] Sleep Driver
+ *
+ * 1. move OSTD, MO_TOPSM, and Sleep_driver from L1 to PS trace
+ * 2. sync log with Gen92
+ *
+ * 03 30 2016 hsiao-hsien.chen
+ * [MOLY00171976] [GEN93] Fix sleep driver build error.
+ * Add 93 option.
+ *
+ * 08 20 2015 shengfu.tsai
+ * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
+ * .submit the modem topsm initial function for Elbrus
+ *
+ * 08 04 2015 che-wei.chang
+ * [MOLY00120320] [TK6291/Jade] DVFS Code Submission
+ * update ccirq cmd enum for dvfs
+ *
+ * 07 23 2015 ethan.hsieh
+ * [MOLY00131103] Sleep Mode Debug Shared Memory Mechanism Improvement
+ *
+ * 07 10 2015 che-wei.chang
+ * [MOLY00127376] [MT6755][UMOLY]update md 26m settle time to 4ms
+ *
+ * 07 10 2015 che-wei.chang
+ * [MOLY00120320] [TK6291/Jade] DVFS Code Submission,add ccirq enum for DVFS
+ *
+ * 07 07 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY]
+ * sync low power Cbr
+ * 1.add stress test AT CMD (ps side)
+ * 2.add at_sleepcount AT CMD (ps side)
+ * 3.update setting for JADE
+ *
+ * 06 18 2015 hsiao-hsien.chen
+ * [MOLY00072109] [MT6291] Sleep mode code modification.
+ * Fix build error. Add CCIRQ enum for pcore stress test.
+ *
+ * 06 11 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY]
+ * update SleepDrv_CCIRQ_CMD_E for DVFS
+ *
+ * 05 28 2015 ethan.hsieh
+ * [MOLY00085137] [TK6291] Sleep Mode Modifications - Move infinite sleep compile option to sleepdrv_common.h for both Pcore and L1core
+ *
+ * 05 14 2015 ethan.hsieh
+ * [MOLY00085137] [TK6291] Sleep Mode Modifications - Infinite Sleep for Jade
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __SLEEPDRV_COMMON_H__
+#define __SLEEPDRV_COMMON_H__
+
+#ifndef MAX
+#define MAX(a,b) ( ( (a) > (b) ) ? (a) : (b) )
+#endif
+
+#ifndef MAX4
+#define MAX4(a,b,c,d) MAX( MAX((a),(b)) , MAX((c),(d)) )
+#endif
+
+#if defined(__MD93__)
+ #if defined(MT6763) || defined(MT6739)
+ #define RM_SYS_CLK_SETTLE 0x8C
+ #elif defined(MT6771)
+ #define RM_SYS_CLK_SETTLE 0x97
+ #else
+ #define RM_SYS_CLK_SETTLE 0x97
+ #endif
+#elif defined(__MD95__)
+ #if defined(MT6779) // Lafite
+ #define RM_SYS_CLK_SETTLE 0x93 // according to 2018/10/04 DE Wayne Liu's comment
+ #else
+ #define RM_SYS_CLK_SETTLE 0x9E // according to Ver 2.0 (20180111) spec
+ #endif
+#elif defined(__MD97__) || defined(__MD97P__)
+ #if defined(MT6297) || defined(MT6297_IA)
+ #define SYS_CLK_SETTLE 0x96
+ #define RM_SYS_CLK_SETTLE SYS_CLK_SETTLE+4
+ #define MD_MAS_TRIG_EMI_SETTLE (0x12)
+ #elif defined(MT6885)
+ #define SYS_CLK_SETTLE 0x51
+ #define RM_SYS_CLK_SETTLE SYS_CLK_SETTLE+4
+ #define MD_MAS_TRIG_EMI_SETTLE (0x15)
+ #elif defined(CHIP10992)
+ #define REAL_SYS_CLK_SETTLE 0x3B
+ #define TIA_SETTLE 0x5E
+ #define MD_MAS_TRIG_EMI_SETTLE (0x28)
+ #define PLL_PWR_MASTRIG_TIMER_SETTLE MAX4(MD_RM_PLL_SETTLE, MD_MAX_PWR_SETTLE, MD_MAS_TRIG_MAX_SETTLE, MD_TIMER_TRIG_SETTLE)
+ // 26M+EMI settle time need to cover TIA settle time
+ #define SYS_CLK_SETTLE (MAX(TIA_SETTLE, REAL_SYS_CLK_SETTLE+PLL_PWR_MASTRIG_TIMER_SETTLE) - PLL_PWR_MASTRIG_TIMER_SETTLE)
+ #define RM_SYS_CLK_SETTLE SYS_CLK_SETTLE+4
+ #else
+ #define SYS_CLK_SETTLE 0x53
+ #define RM_SYS_CLK_SETTLE SYS_CLK_SETTLE+4
+ #define MD_MAS_TRIG_EMI_SETTLE (0x16)
+ #endif
+ #define MD_MAS_TRIG_L1_COMM_SETTLE (0xE)
+ #define MD_MAS_TRIG_MAX_SETTLE MAX(MD_MAS_TRIG_EMI_SETTLE, MD_MAS_TRIG_L1_COMM_SETTLE)
+ #define MD_TIMER_TRIG_SETTLE (0x4)
+ #define MD_MAX_PWR_SETTLE (0x2)
+ #define MD_RM_PLL_SETTLE (0x2)
+#else
+ #error "no chip match"
+#endif
+
+typedef enum {
+ SLP_DBG_SHM_FIX_REG_PS_ISR_SM_SLV_REQ_STA,
+ SLP_DBG_SHM_FIX_REG_PS_NON_F32K_WKUP_STA,
+ SLP_DBG_SHM_FIX_REG_PS_F32K_WKUP_STA,
+ SLP_DBG_SHM_FIX_REG_PS_F32K2_WKUP_STA,
+ SLP_DBG_SHM_FIX_REG_PS_PRE_TIMESTAMP,
+ SLP_DBG_SHM_FIX_REG_PS_AFT_TIMESTAMP,
+ SLP_DBG_SHM_FIX_REG_PS_SW_LOCK,
+ SLP_DBG_SHM_FIX_REG_PS_RM_PWR_STA,
+ SLP_DBG_SHM_FIX_REG_PS_SW_PWR_CLK_FORCE_ON,
+ SLP_DBG_SHM_FIX_REG_PS_PWRPLL_OFF_REC,
+ SLP_DBG_SHM_FIX_REG_PS_MD_SYSCLK_GATING_STA,
+ SLP_DBG_SHM_FIX_REG_PS_RESERVED1,
+ SLP_DBG_SHM_FIX_REG_PS_END = SLP_DBG_SHM_FIX_REG_PS_RESERVED1,
+ SLP_DBG_SHM_FIX_REG_L1_ISR_SM_SLV_REQ_STA,
+ SLP_DBG_SHM_FIX_REG_L1_NON_F32K_WKUP_STA,
+ SLP_DBG_SHM_FIX_REG_L1_F32K_WKUP_STA,
+ SLP_DBG_SHM_FIX_REG_L1_PRE_TIMESTAMP,
+ SLP_DBG_SHM_FIX_REG_L1_AFT_TIMESTAMP,
+ SLP_DBG_SHM_FIX_REG_L1_SW_LOCK,
+ SLP_DBG_SHM_FIX_REG_L1_SM_PWR_RDY,
+ SLP_DBG_SHM_FIX_REG_L1_SM_PLL_STA,
+ SLP_DBG_SHM_FIX_REG_L1_SM_DBG_REQ_STA,
+ SLP_DBG_SHM_FIX_REG_L1_SM_MAS_REQ_STA,
+ SLP_DBG_SHM_FIX_REG_L1_SM_PWR_ON_SW_CTRL0,
+ SLP_DBG_SHM_FIX_REG_L1_SW_PLL_FORCE_ON,
+ SLP_DBG_SHM_FIX_REG_L1_END = SLP_DBG_SHM_FIX_REG_L1_SW_PLL_FORCE_ON,
+ SLP_DBG_SHM_FIX_REG_END
+} SLP_DBG_SHM_FIX_REG_INDEX;
+
+typedef struct {
+ kal_uint32 guard_pat;
+ // fix pattern of buffer selection for pscore
+ kal_uint32 buf_sel_ps;
+ // fix pattern of buffer selection for l1core
+ kal_uint32 buf_sel_l1;
+ kal_uint32 revision;
+ // double size for fix pattern
+ kal_uint32 fix_reg[SLP_DBG_SHM_FIX_REG_END<<1];
+} slp_dbg_shm_fix_pat_t;
+
+typedef enum {
+ //SLP_DBG_SHM_LockSleep = 0x1,
+ //SLP_DBG_SHM_UnLockSleep,
+ SLP_DBG_SHM_2G_Sleep = 0x1,
+ SLP_DBG_SHM_2G_Wakeup,
+ SLP_DBG_SHM_3G_Sleep,
+ SLP_DBG_SHM_3G_Wakeup,
+ SLP_DBG_SHM_4G_Sleep,
+ SLP_DBG_SHM_4G_Wakeup,
+ SLP_DBG_SHM_RAT_InfiniteSleep_Done,
+} SLP_DBG_SHM_RING_BUFFER_INDEX;
+
+typedef struct {
+ // index is for recording enumrate SLP_DBG_SHM_RING_BUFFER_INDEX
+ kal_uint32 index:4;
+ // Bi[0] = 1 if 2G RM_TMR_SSTA is not in pause state
+ // Bi[1] = 1 if 3G RM_TMR_SSTA is not in pause state
+ // Bi[2] = 1 if SM_SLV_REQ_STA shows TD is slave ready
+ // Bi[3] = 1 if 4G RM_TMR_SSTA is not in pause state
+ kal_uint32 status:4;
+ // record for FMA global timestamp, and unit is 256 us.
+ kal_uint32 timestamp:24;
+ // additional debug information for user.
+ kal_uint32 dbg_info;
+} slp_dbg_shm_ring_buf_t;
+
+// Now, AP only dumps 512 bytes although shared memory size is 1K bytes
+#define SLP_DBG_SHM_AP_DUMP_SIZE 512
+typedef struct {
+ kal_uint32 guard_pat1;
+ kal_uint32 guard_pat2;
+ kal_uint32 guard_pat3;
+ kal_uint32 revision;
+ slp_dbg_shm_ring_buf_t info[(SLP_DBG_SHM_AP_DUMP_SIZE-sizeof(slp_dbg_shm_fix_pat_t)-sizeof(kal_uint32)*4)/sizeof(slp_dbg_shm_ring_buf_t)];
+} slp_dbg_shm_ring_pat_t;
+
+typedef struct {
+ slp_dbg_shm_fix_pat_t fix_pat;
+ slp_dbg_shm_ring_pat_t ring_pat;
+} slp_dbg_shm_t;
+
+typedef enum _slp_lock_type_e {
+ SLP_IS_NO_LOCK,
+ SLP_IS_SW_LOCK,
+ SLP_IS_HW_LOCK
+} slp_lock_type_e;
+
+typedef enum _power_model_mdlpm_e {
+ POWER_MODEL_MDLPM_RESERVED_0 = 0, // Reserve 0 for speicial purpose
+ POWER_MODEL_MDLPM_UTC_0,
+ POWER_MODEL_MDLPM_UTC_1,
+ POWER_MODEL_MDLPM_FRC,
+ POWER_MODEL_MDLPM_WALL_CLK_0,
+ POWER_MODEL_MDLPM_WALL_CLK_1,
+ POWER_MODEL_MDLPM_MD_SLEEP_DUR,
+ POWER_MODEL_MDLPM_GL1_SLEEP_DUR,
+ POWER_MODEL_MDLPM_UL1_SLEEP_DUR,
+ POWER_MODEL_MDLPM_EL1_SLEEP_DUR,
+ POWER_MODEL_MDLPM_NL1_SLEEP_DUR = 10,
+ POWER_MODEL_MDLPM_GL1_CONNECT_DUR,
+ POWER_MODEL_MDLPM_GL1_CONNECT_DRX_DUR,
+ POWER_MODEL_MDLPM_GL1_RX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_GL1_TX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_GL1_TX_POWER_RATIO_0,
+ POWER_MODEL_MDLPM_GL1_TX_POWER_RATIO_1,
+ POWER_MODEL_MDLPM_RESERVED_20 = 20,
+ POWER_MODEL_MDLPM_UL1_CONNECT_DUR,
+ POWER_MODEL_MDLPM_UL1_CONNECT_DRX_DUR,
+ POWER_MODEL_MDLPM_UL1_RX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_UL1_TX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_UL1_TX_POWER_RATIO_0,
+ POWER_MODEL_MDLPM_UL1_TX_POWER_RATIO_1,
+ POWER_MODEL_MDLPM_RESERVED_30 = 30,
+ POWER_MODEL_MDLPM_EL1_CONNECT_DUR,
+ POWER_MODEL_MDLPM_EL1_CONNECT_DRX_DUR,
+ POWER_MODEL_MDLPM_EL1_RX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_EL1_TX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_EL1_TX_POWER_RATIO_0,
+ POWER_MODEL_MDLPM_EL1_TX_POWER_RATIO_1,
+ POWER_MODEL_MDLPM_EL1_CC_RATIO_0,
+ POWER_MODEL_MDLPM_EL1_CC_RATIO_1,
+ POWER_MODEL_MDLPM_EL1_RAS_RATIO,
+ POWER_MODEL_MDLPM_RESERVED_45 = 45,
+ POWER_MODEL_MDLPM_NL1_CONNECT_DUR,
+ POWER_MODEL_MDLPM_NL1_CONNECT_DRX_DUR,
+ POWER_MODEL_MDLPM_NL1_RX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_NL1_TX_WINDOW_DUR,
+ POWER_MODEL_MDLPM_NL1_TX_POWER_RATIO_0,
+ POWER_MODEL_MDLPM_NL1_TX_POWER_RATIO_1,
+ POWER_MODEL_MDLPM_DVFS_GEAR_RATIO_0 = 61,
+ POWER_MODEL_MDLPM_DVFS_GEAR_RATIO_1 = 62,
+ POWER_MODEL_MDLPM_REC_INDEX = 63,
+ POWER_MODEL_MDLPM_MAX_ITEM = 64
+} power_model_mdlpm_e;
+
+#endif
diff --git a/mcu/interface/driver/sleep_drv/sleepdrv_interface.h b/mcu/interface/driver/sleep_drv/sleepdrv_interface.h
new file mode 100644
index 0000000..b6ffa7e
--- /dev/null
+++ b/mcu/interface/driver/sleep_drv/sleepdrv_interface.h
@@ -0,0 +1,1147 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sleepdrv_interface.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for the public access for sleep mode operation.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Log$
+ *
+ * 02 11 2022 yuhao.ye
+ * [MOLY00764790] [FBC][FM350-GL][NA][NA][USB]fm350 iot USB suspend and resume problem
+ *
+ * .
+ *
+ * 08 11 2021 pj.chen
+ * [MOLY00681687] [FM350-GL][FM350-GL][Nick Zhang][memory dump][NA][NA][NA]md_self_detect_by_hmu_long_time_no_response modem dump
+ * Add MCF lock sleep enum
+ *
+ * 11 10 2020 pj.chen
+ * [MOLY00528192] [Colgin][Sleep Mode]Driver development
+ * Add lock sleep enum for LVTS whole system reset
+ *
+ * 04 15 2020 guo-huei.chang
+ * [MOLY00509323] [Gen97] Power Model
+ * Power model (Sleep Driver Part)
+ * global variable from UnCache to Cache
+ *
+ * 04 06 2020 guo-huei.chang
+ * [MOLY00509323] [Gen97] Power Model
+ *
+ * Power model (Sleep Driver Part)
+ *
+ * 12 02 2019 jack.tung
+ * [MOLY00462428] [VMOLY][Gen97 Petrus] Structure Reordering in Sleep Driver
+ *
+ * .
+ *
+ * 10 24 2019 lian-li.tsai
+ * [MOLY00452393] For Low power monitor, raw data modify
+ * [EWSP0000054581_R1]
+ * [EWSP0000054581]
+ *
+ * 08 08 2019 guo-huei.chang
+ * [MOLY00421978] [VMOLY]Sleep and low power modify
+ * add md low power monitor (OSTD part)
+ *
+ * 08 06 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Solve build error for Mercury
+ *
+ * 07 18 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Add compile option for MD97P
+ *
+ * 04 15 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Add sleep control enum
+ *
+ * 04 11 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * 1.Add sleep comtrol enum
+ * 2.DDr_en settings
+ * 3.Wakeup event settings
+ * 4.Add wallclk define
+ * 5.Force on IA for early csys_req
+ * 6.Modify AT command
+ *
+ * 03 11 2019 che-wei.chang
+ * [MOLY00389209] [MT6297] topsm/ost for apollo dram power index
+ *
+ * 01 31 2019 guo-huei.chang
+ * [MOLY00353483] [GEN95] MD Low Power Monitor
+ * fix build error for GEN95
+ *
+ * 01 31 2019 guo-huei.chang
+ * [MOLY00353483] [GEN95] MD Low Power Monitor
+ *
+ * merge MD Low Power Monitor from UMOLYE (OSTD & Sleep Driver Part)
+ *
+ * 11 22 2018 guo-huei.chang
+ * [MOLY00366073] [Lafite] MD part of OPPO P80 sleep information
+ * 1.add MD sleep time and sleep count to share memory
+ * 2.add iA idle time to MD low power monitor
+ *
+ * 10 30 2018 leon.yeh
+ * [MOLY00356811] [GEN95] MD Low Power Monitor L1 modulo fill data
+ * - add debug data
+ * .
+ *
+ * 10 15 2018 leon.yeh
+ * [MOLY00356811] [GEN95] MD Low Power Monitor L1 modulo fill data
+ * - 4G TX/RX path interface modify.
+ *
+ * 09 14 2018 jack.tung
+ * [MOLY00351968] [DFR][Gen95] Assertion Removal
+ *
+ * .
+ *
+ * 09 04 2018 ej.farn
+ * [MOLY00332776] [Gen95] MD Low Power Montior Development
+ * [Gen95] MD Low Power Monitor
+ *
+ * 08 30 2018 ej.farn
+ * [MOLY00332776] [Gen95] MD Low Power Montior Development
+ * [Gen95] MD Low Power Monitor
+ *
+ * 08 28 2018 ej.farn
+ * [MOLY00332776] [Gen95] MD Low Power Montior Development
+ * [Gen95] MD Low Power Monitor
+ *
+ * 01 08 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Add SLEEP_CTL_MML1 for MD95.
+ *
+ * 01 07 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Modify lock 26m interface
+ *
+ * 01 02 2019 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Add lock sleep control enum for 97
+ *
+ * 09 18 2018 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Add enum for 5G NL1
+ *
+ * 08 17 2018 owen.ho
+ * [MOLY00312416] [Gen97][Need Patch]Sleep driver development
+ * Integrate Gen97 driver from UMOYE.Gen97.DEV
+ *
+ * 05 18 2018 owen.ho
+ * [MOLY00312416] [Gen97] Sleep driver development
+ * Gen97 sleep driver
+ * Solve build error for Gen97
+ * 06 14 2018 che-wei.chang
+ * [MOLY00333397] [TOPSM/OST] remove legacy code and log reduction
+ *
+ * 05 29 2018 guo-huei.chang
+ * [MOLY00327413] [UMOLYE]Low power monitor patch sync
+ * md low power monitor (ostd part)
+ *
+ * 04 26 2018 che-wei.chang
+ * [MOLY00318930] [Eiger] topsm/ost - add lock sleep enum id for sim3/sim4
+ *
+ * 04 02 2018 leon.yeh
+ * [MOLY00316801] for legacy chips option and feature options cleanup
+ *
+ * .
+ *
+ * 09 28 2017 che-wei.chang
+ * [MOLY00281049] [93/95 re-arch] MD topsm/ost
+ *
+ * 09 08 2017 jack.tung
+ * [MOLY00274378] [MD Platform Low-Power] Check Flight Mode Condition on HW Status
+ *
+ * 08 15 2017 owen.ho
+ * [MOLY00266818] [BIANCO][MT6763][MTBF][C2K][SIM1:CTC][SIM2:CU][ASSERT] file:mcu/common/driver/devdrv/log_seq/src/logseq_drv.c line:1195
+ * Force on usip API
+ *
+ * 06 28 2017 jack.tung
+ * [MOLY00257950] [Gen93] Flight Mode Debugging Information Improvement
+ *
+ * <saved by Perforce>
+ *
+ * 06 20 2017 owen.ho
+ * [MOLY00258341] [MT6763][Bianco][N1][E2][MD issue][TW] Assert on ulsp_mod_function with PLS mode
+ *
+ * Add sleep control enum for PLS
+ *
+ * 06 12 2017 jack.tung
+ * [MOLY00256211] [Gen93][UMOLYA][SleepDrv] Step-Logging Feature
+ *
+ * <saved by Perforce>
+ *
+ * 05 08 2017 owen.ho
+ * [MOLY00247811] [Bianco] Fatal Error (0xb34, 0x90f9c520, 0xcccccccc) - SQN_EL1 when enabling ostd sleep
+ *
+ * 05 05 2017 owen.ho
+ * [MOLY00246118] [BIANCO]Assert fail: wuldch.c 1439 0x0 0x0 0x0 - (LISR)UL1D_HISR_LISR
+ *
+ * Add sleep controller enumeration
+ *
+ * 03 31 2017 guo-huei.chang
+ * [MOLY00238980] [DHL] MET timer for sync between MET & ELT
+ * add SleepDrv_GetWallClk function
+ *
+ * 03 08 2017 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * 1.Update sleep_ctl_user enum
+ * 2.Porting EMM debug info function
+ * 3.Correct sleepDisable variable index
+ *
+ * 01 19 2017 kevin-kh.liu
+ * [MOLY00173902] [MT6293][Sleep Mode]sleep mode modification
+ * xL1SIM 2G Fixed AFC support - SM part
+ *
+ * 12 30 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ * Update SLEEP_CTL enum list
+ *
+ * 12 20 2016 owen.ho
+ * [MOLY00171832] [UMOLYA][Bianco] Update SLEEP_CTL enum list
+ *
+ * 12 19 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ * Update sleep_ctl enum and md power domain enum
+ *
+ * 12 14 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Update SLEEP_CTL enum
+ *
+ * 12 12 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Update SLEEP_CTL user enum
+ *
+ * 12 09 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Add SLEEP control user enum
+ *
+ * 12 02 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Update lock/unlock core sleep control user list
+ *
+ * 11 23 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * 6293 sleep driver development (Modoify Lock/Unlock Sleep API)
+ *
+ * 11 09 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Solve build error
+ *
+ * 07 20 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ *
+ * Gen93 topsm/ostd driver develpement
+ *
+ * 07 06 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ * 6293 topsm/ostd driver development
+ *
+ * 06 24 2016 owen.ho
+ * [MOLY00171832] [UMOLYA]
+ * GEN93 md topsm/ostd driver development
+ *
+ * 03 31 2016 vmick.lin
+ * [MOLY00171891] [6293] sleep driver development
+ *
+ * .
+ *
+ * 03 30 2016 vmick.lin
+ * [MOLY00171891] [6293] sleep driver development
+ *
+ * .
+ *
+ * 03 15 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * EL1-EL2 lock LMAC power Sleep Driver for EL1 part (without trigger CCIRQ)
+ *
+ * 03 14 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * 1. MSBB Violation
+ * 2. Remove EL1D DVFS avtive window check
+ * 3. 4G sleep mode locker for DVFS drivers
+ * 4. Add Data Sync Barrier
+ * 5. Rename global veriable
+ * 6. LMAC locker API implement
+ * 7. EL1D Backup functions relocated
+ *
+ * 03 11 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * Rollback CL2258329 CL2158833 CL2159108
+ *
+ * 03 07 2016 james.pan
+ * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation
+ * md_sm sleep_drv MSBB violation
+ *
+ * 02 23 2016 kevin-kh.liu
+ * [MOLY00163589] [6292][sleep mode] code merge from LR11 to UMOLY
+ *
+ * Sleep Mode Debug Shared Memory Mechanism
+ *
+ * 02 18 2016 leon.yeh
+ * [MOLY00165273] [6292][sleep mode] code merge from LR11 to UMOLY (fixAFC & 32K-less) - fix build error: INVALID_FREQ_OFF define changed to sleepdrv_interface.h
+ *
+ * 02 16 2016 dennis.chueh
+ * [MOLY00141188] [ELBRUS][FPGA] Add new features.
+ * Share memory debug functions:
+ * void SleepDrv_UpdatePSSlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
+ * void SleepDrv_UpdateL1SlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
+ * void SleepDrv_SlpDbgShmRingBufAdd(SLP_DBG_SHM_RING_BUFFER_INDEX index, kal_uint32 status, kal_uint32 dbg_info);
+ *
+ * 01 29 2016 jack.tung
+ * [MOLY00163331] MD-TOPSM API Atomicity Access Implementation
+ * Atomicity Operation Test and Implementation for TOPSM Software Force-On Control
+ *
+ * 01 20 2016 shengfu.tsai
+ * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
+ *
+ * .fixed xl1sm build issue
+ *
+ * 01 19 2016 shengfu.tsai
+ * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
+ *
+ * . modify l1sm\ul1sm include file to meet MSBB rule
+ *
+ * 11 03 2015 dennis.chueh
+ * [MOLY00141188] [ELBRUS][FPGA] Add new features.
+ *
+ * Add ENUM define for drvtest.
+ * Add Power down API.
+ *
+ * 11 02 2015 dennis.chueh
+ * [MOLY00141188] [ELBRUS][FPGA] Add new features.
+ *
+ * add MIPS_CPC_PowerOn to sleepdrv_interface.h.
+ *
+ * 10 30 2015 shengfu.tsai
+ * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
+ *
+ * .merge some change from XL1SM branch
+ *
+ * 08 17 2015 dennis.chueh
+ * [MOLY00070771] [6291][FPGA]solve build error
+ * Solve build error after applying ELBRUS_FPGA.
+ *
+ * 08 16 2015 dennis.chueh
+ * [MOLY00070771] [6291][FPGA]solve build error
+ * Solve build error after applying ELBRUS make file.
+ *
+ * 08 13 2015 dennis.chueh
+ * [MOLY00070771] [6291][FPGA]solve build error
+ * Solve build error after merging back to UMOLY trunk.
+ *
+ * 08 13 2015 dennis.chueh
+ * [MOLY00070771] [6291][FPGA]solve build error
+ * Solve build error after merging back.
+ *
+ * 08 12 2015 shengfu.tsai
+ * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus
+ * .add SleepDrv_LockPcoreSleepMode and SleepDrv_LockLMACPower
+ * but these function need to modify in the future
+ *
+ * 08 04 2015 dennis.chueh
+ * [MOLY00070771] [6291][FPGA]solve build error
+ * SleepDrv_GetHandle() --> SleepDrv_GetHandle(SMP).
+ *
+ * 07 23 2015 guo-huei.chang
+ * [MOLY00131103] Sleep Mode Debug Shared Memory Mechanism Improvement
+ * 1. add CCIRQ CMD for L1core querying shared memory address
+ * 2. add fix pat API for PScore and L1core and ring buffer API for L1core
+ * 3. add fix pat in CheckSleep function
+ * 4. add declarion for DBM and PTPOD shared memory
+ *
+ * 06 11 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY]
+ * 1.add MT6755 flag for Jade
+ * 2.update ostd elt log
+ * 3.update SleepDrv_GetHandle return value for assert
+ *
+ * 05 05 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY] add enum PS_PLL_FORCEON_USER_SIB to PS_PLL_FORCEON_USER for SIB
+ *
+ * 04 29 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY] add a new API MD_TOPSM_PLL_SW_Control for force on PS side PLLs
+ *
+ * 04 29 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY] Sync vmick Cbr (Ccirq)
+ *
+ * 02 26 2015 che-wei.chang
+ * [MOLY00089700] [TK6291][UMOLY] Sync MT6291_DEV branch
+ *
+ * 02 10 2015 yu-hung.huang
+ * [MOLY00095165] [TK6291] Check in LITE GPT Driver and New Sleep API
+ * [UMOLY] 2-leve GPT solution: refine SRCLK (26M) force on/off API interface for multiple user
+ *
+ * 09 05 2014 yu-hung.huang
+ * [MOLY00078094] [UMOLY] Sleep Codes Sync from MOLY TRUNK to UMOLY TK6291_DEV
+ * [TK6291_DEV] Sync SD3 Sleep Driver Codes from MOLY TRUNK to UMOLY (Changelists before 2014/9/4 in MOLY TRUNK)
+ *
+ * 08 27 2014 vmick.lin
+ * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97
+ * .
+ *
+ * 08 27 2014 vmick.lin
+ * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97
+ * .
+ *
+ * 08 26 2014 vmick.lin
+ * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97
+ * .
+ * Add 99T 32K period while OST struggle in SETTLE state
+ *
+ * 10 25 2013 alvin.chen
+ * [MOLY00043719] [MT6290][MDTOPSM] Patch for Phone Field trial activity
+ * Integration change.
+ *
+ * 10 03 2013 alvin.chen
+ * [MOLY00040177] [MT6290][MD_TOPSM] Add FRC enable API for Early Stage Debug
+ * <saved by Perforce>
+ *
+ * 07 26 2013 barry.hong
+ * [MOLY00030921] [MT6290]Low Power Feature patch back from CBr
+ * Low Power Feature patch back from CBr
+ *
+ * 02 26 2013 jeff.lee
+ * reorg. header file.
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __SLEEPDRV_INTERFACE_H__
+#define __SLEEPDRV_INTERFACE_H__
+
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "sleepdrv_common.h"
+
+
+#if defined(__SMART_PHONE_MODEM__) && defined(__MODEM_CCCI_EXIST__) && defined(__HIF_SDIO_SUPPORT__)
+#define PHONE_TYPE_FOR_HQA
+#endif
+
+#define BIG_DAC_CHANGE_RECALIBRATION /* This compiler option is default defined in Moly branch to enable this feature */
+
+#ifdef BIG_DAC_CHANGE_RECALIBRATION
+#define FREQ_OFF_THR 11700 /* 13ppm freqeuncy offset based on 900MHz */
+#define FREQ_OFF_VALID 65528 /* Valid DAC frequency offset shall be below 8191x8=65528(Hz) */
+#define INVALID_FREQ_OFF 0x7FFFFFFF /* When L1D/UL1D detect the frequency error is unreliable, return 0x7FFFFFFF to sleep mode */
+#endif //BIG_DAC_CHANGE_RECALIBRATION
+
+typedef enum
+{
+ PS_USIP_FORCEON_USER_AUDIO = 0,
+ PS_USIP_FORCEON_USER_LOG,
+ NUM_OF_USIP_FORCEON_USER
+} PS_USIP_FORCEON_USER;
+
+typedef enum
+{
+ SRCLK_FORCEON_USER_SIM = 0,
+ SRCLK_FORCEON_USER_USB,
+#if defined(__MD97__) && defined(__MTK_TARGET__) && defined(MT6297)
+ SRCLK_FORCEON_USER_DRAM,
+#endif
+ NUM_OF_SRCLK_FORCEON_USER
+} SRCLK_FORCEON_USER;
+
+typedef enum
+{
+ PS_PLL_FORCEON_USER_CTI = 0,
+ PS_PLL_FORCEON_USER_SIB,
+ NUM_OF_PLL_FORCEON_USER
+} PS_PLL_FORCEON_USER;
+
+typedef enum
+{
+#if defined(__MD93__)
+ PS_TOPSM_MDCORE_PLL = 0,
+ PS_TOPSM_BUS2X_PLL,
+ PS_TOPSM_F208M_PLL,
+ PS_TOPSM_DBG_PLL,
+ PS_TOPSM_LOG_PLL,
+ PS_TOPSM_SDF_ATB_PLL,
+ NUM_OF_PS_TOPSM_PLL,
+#elif defined(__MD95__)
+ PS_TOPSM_MDCORE_PLL = 0,
+ PS_TOPSM_BUS2X_PLL = 1,
+ PS_TOPSM_F208M_PLL = 2,
+ PS_TOPSM_DBG_PLL = 3,
+ PS_TOPSM_LOG_PLL = 4,
+ PS_TOPSM_SDF_ATB_PLL = 5,
+ PS_TOPSM_MML2_PLL = 6,
+ NUM_OF_PS_TOPSM_PLL = 7,
+#elif defined(__MD97__) || defined(__MD97P__)
+ PS_TOPSM_MDCORE_PLL = 0,
+ PS_TOPSM_BUS4X_PLL = 1,
+ PS_TOPSM_F208M_PLL = 2,
+ PS_TOPSM_DBG_PLL = 3,
+ PS_TOPSM_LOG_PLL = 4,
+ PS_TOPSM_SDF_ATB_PLL = 5,
+ PS_TOPSM_MML2_PLL = 6,
+ PS_TOPSM_SHAOLIN_PLL = 7,
+ PS_TOPSM_IA_PLL = 8,
+ NUM_OF_PS_TOPSM_PLL = 9,
+#else
+ #error "no chip match"
+#endif
+} PS_TOPSM_PLL;
+
+typedef enum
+{
+#if defined(__MD93__)
+ SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function
+ SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage
+ SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep
+ SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario
+ SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt
+ SLEEP_CTL_3G_FDD_UL1D = 5, // 0x05, L1 lock CORE1 sleep before sending L2P CCIRQ to core1
+ SLEEP_CTL_USB = 6, // 0x06, To lock sleep when driver get rx gpd done event
+ SLEEP_CTL_ADT = 7, // 0x07, DL data by GDMA to ISPRAM0, we need to avoid power down core0
+ SLEEP_CTL_L4 = 8, // 0x08, AT+ESLP to control sleep mode
+ SLEEP_CTL_3G_TDD_TL1 = 9, // 0x09, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state
+ SLEEP_CTL_USIM0 = 10, // 0x0A,
+ SLEEP_CTL_USIM1 = 11, // 0x0B,
+ SLEEP_CTL_USIM2 = 12, // 0x0C,
+ SLEEP_CTL_USIM3 = 13, // 0x0D,
+ SLEEP_CTL_C2K_1X = 14, // 0x0E,
+ SLEEP_CTL_C2K_DO = 15, // 0x0F,
+ SLEEP_CTL_C2K_SS = 16, // 0x10,
+ SLEEP_CTL_2G_TDD_MPAL = 17, // 0x11, GAS lock CORE1 sleep before sending msg to core1
+ SLEEP_CTL_FM = 18, // 0x12, Lock sleep while do calibration
+ SLEEP_CTL_EL1SM = 19, // 0x13, To lock core0/core1 sleep when LTE timer wakeup
+ SLEEP_CTL_EL1SM_DEBUG = 20, // 0x14, Debug for LTE sleep mode verify
+ SLEEP_CTL_UL1SM = 21, // 0x15, To lock core0 sleep when 3G FDD timer wakeup
+ SLEEP_CTL_L1SM = 22, // 0x16, To lock core0 sleep when 2G timer wakeup
+ SLEEP_CTL_GCU = 23, // 0x17,
+ SLEEP_CTL_IDC = 24, // 0x18, Lock core until idc_uart tx confirms last two bytes of data was sent
+ SLEEP_CTL_SPEECH = 25, // 0x19, Lock core while MD speech is working
+ SLEEP_CTL_MTD_NAND = 26, // 0x1A, Not used in 93, but owner request to perserve for future use
+ SLEEP_CTL_RR_FDD = 27, // 0x1B, To Lock/Unlock MPAL sleep
+ SLEEP_CTL_2G_SMM_DPS = 28, // 0x1C, To Lock/Unlock 2G SMM in Dummy PS TASK
+ SLEEP_CTL_3G_SMM_DPS = 29, // 0x1D, To Lock/Unlock 3G SMM in Dummy PS TASK
+ SLEEP_CTL_3G_FDD_SLCE = 30, // 0x1E, To Lock CORE1 sleep when in 3G connected mode for stack 1
+ SLEEP_CTL_3G_FDD_SLCE2 = 31, // 0x1F, To Lock CORE1 sleep when in 3G connected mode for stack 2
+ SLEEP_CTL_3G_FDD_SLCE3 = 32, // 0x20, To Lock CORE1 sleep when in 3G connected mode for stack 3
+ SLEEP_CTL_EL2 = 33, // 0x21, To ensure mcu awake until EL2 polling complete
+ SLEEP_CTL_ERRC = 34, // 0x22, Lock current core for avoiding delay when lower layer control
+ SLEEP_CTL_ERRC2 = 35, // 0x23, Because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement
+ SLEEP_CTL_PLS = 36, // 0x24, Lock sleep to make sure the user's tag will succeed in the PLS logging mode.
+ SLEEP_CTL_SIM1 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM2 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM3 = 39, // 0x27, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM4 = 40, // 0x28, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ MAX_SLEEP_HANDLE = 46
+#elif defined(__MD95__)
+ SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function
+ SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage
+ SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep
+ SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario
+ SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt
+ SLEEP_CTL_USB = 5, // 0x05, To lock sleep when driver get rx gpd done event
+ SLEEP_CTL_L4 = 6, // 0x06, AT+ESLP to control sleep mode
+ SLEEP_CTL_3G_TDD_TL1 = 7, // 0x07, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state
+ SLEEP_CTL_USIM0 = 8, // 0x08,
+ SLEEP_CTL_USIM1 = 9, // 0x09,
+ SLEEP_CTL_USIM2 = 10, // 0x0A,
+ SLEEP_CTL_USIM3 = 11, // 0x0B,
+ SLEEP_CTL_C2K_1X = 12, // 0x0C,
+ SLEEP_CTL_C2K_DO = 13, // 0x0D,
+ SLEEP_CTL_C2K_SS = 14, // 0x0E,
+ SLEEP_CTL_2G_TDD_MPAL = 15, // 0x0F, GAS lock CORE1 sleep before sending msg to core1
+ SLEEP_CTL_FM = 16, // 0x10, Lock sleep while do calibration
+ SLEEP_CTL_EL1SM = 17, // 0x11, To lock core0/core1 sleep when LTE timer wakeup
+ SLEEP_CTL_EL1SM_DEBUG = 18, // 0x12, Debug for LTE sleep mode verify
+ SLEEP_CTL_UL1SM = 19, // 0x13, To lock core0 sleep when 3G FDD timer wakeup
+ SLEEP_CTL_L1SM = 20, // 0x14, To lock core0 sleep when 2G timer wakeup
+ SLEEP_CTL_IDC = 21, // 0x15, Lock core until idc_uart tx confirms last two bytes of data was sent
+ SLEEP_CTL_MTD_NAND = 22, // 0x16, Not used in 93, but owner request to perserve for future use
+ SLEEP_CTL_RR_FDD = 23, // 0x17, To Lock/Unlock MPAL sleep
+ SLEEP_CTL_2G_SMM_DPS = 24, // 0x18, To Lock/Unlock 2G SMM in Dummy PS TASK
+ SLEEP_CTL_3G_SMM_DPS = 25, // 0x19, To Lock/Unlock 3G SMM in Dummy PS TASK
+ SLEEP_CTL_3G_FDD_SLCE = 26, // 0x1A, To Lock CORE1 sleep when in 3G connected mode for stack 1
+ SLEEP_CTL_3G_FDD_SLCE2 = 27, // 0x1B, To Lock CORE1 sleep when in 3G connected mode for stack 2
+ SLEEP_CTL_3G_FDD_SLCE3 = 28, // 0x1C, To Lock CORE1 sleep when in 3G connected mode for stack 3
+ SLEEP_CTL_ERRC = 29, // 0x1D, Lock current core for avoiding delay when lower layer control
+ SLEEP_CTL_ERRC2 = 30, // 0x1E, because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement
+ SLEEP_CTL_PLS = 31, // 0x1F, lock sleep to make sure the user's tag will successd in PLS logging mode
+ SLEEP_CTL_SS = 32, // 0x20, for performance profiling
+ SLEEP_CTL_SOE = 33, // 0x21, lock CPU when using SOE
+ SLEEP_CTL_SPEECH = 34, // 0x22, reserved enum for speech
+ SLEEP_CTL_SIM1 = 35, // 0x23, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM2 = 36, // 0x24, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM3 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM4 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_MML1 = 39,
+ MAX_SLEEP_HANDLE = 40
+#elif defined(__MD97__) || defined(__MD97P__)
+ SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function
+ SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage
+ SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep
+ SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario
+ SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt
+ SLEEP_CTL_USB = 5, // 0x05, To lock sleep when driver get rx gpd done event
+ SLEEP_CTL_L4 = 6, // 0x06, AT+ESLP to control sleep mode
+ SLEEP_CTL_3G_TDD_TL1 = 7, // 0x07, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state
+ SLEEP_CTL_USIM0 = 8, // 0x08
+ SLEEP_CTL_USIM1 = 9, // 0x09
+ SLEEP_CTL_USIM2 = 10, // 0x0A
+ SLEEP_CTL_USIM3 = 11, // 0x0B
+ SLEEP_CTL_C2K_1X = 12, // 0x0C
+ SLEEP_CTL_C2K_DO = 13, // 0x0D
+ SLEEP_CTL_C2K_SS = 14, // 0x0E
+ SLEEP_CTL_2G_TDD_MPAL = 15, // 0x0F, GAS lock CORE1 sleep before sending msg to core1
+ SLEEP_CTL_FM = 16, // 0x10, Lock sleep while do calibration
+ SLEEP_CTL_EL1SM = 17, // 0x11, To lock core0/core1 sleep when LTE timer wakeup
+ SLEEP_CTL_EL1SM_DEBUG = 18, // 0x12, Debug for LTE sleep mode verify
+ SLEEP_CTL_UL1SM = 19, // 0x13, To lock core0 sleep when 3G FDD timer wakeup
+ SLEEP_CTL_L1SM = 20, // 0x14, To lock core0 sleep when 2G timer wakeup
+ SLEEP_CTL_IDC = 21, // 0x15, Lock core until idc_uart tx confirms last two bytes of data was sent
+ SLEEP_CTL_MTD_NAND = 22, // 0x16, Not used in 93, but owner request to perserve for future use
+ SLEEP_CTL_RR_FDD = 23, // 0x17, To Lock/Unlock MPAL sleep
+ SLEEP_CTL_2G_SMM_DPS = 24, // 0x18, To Lock/Unlock 2G SMM in Dummy PS TASK
+ SLEEP_CTL_3G_SMM_DPS = 25, // 0x19, To Lock/Unlock 3G SMM in Dummy PS TASK
+ SLEEP_CTL_3G_FDD_SLCE = 26, // 0x1A, To Lock CORE1 sleep when in 3G connected mode for stack 1
+ SLEEP_CTL_3G_FDD_SLCE2 = 27, // 0x1B, To Lock CORE1 sleep when in 3G connected mode for stack 2
+ SLEEP_CTL_3G_FDD_SLCE3 = 28, // 0x1C, To Lock CORE1 sleep when in 3G connected mode for stack 3
+ SLEEP_CTL_ERRC = 29, // 0x1D, Lock current core for avoiding delay when lower layer control
+ SLEEP_CTL_ERRC2 = 30, // 0x1E, Because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement
+ SLEEP_CTL_PLS = 31, // 0x1F, lock sleep to make sure the user's tag will successd in PLS logging mode
+ SLEEP_CTL_SS = 32, // 0x20, for performance profiling
+ SLEEP_CTL_SOE = 33, // 0x21, lock CPU when using SOE
+ SLEEP_CTL_SPEECH = 34, // 0x22, reserved enum for speech
+ SLEEP_CTL_SIM1 = 35, // 0x23, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM2 = 36, // 0x24, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM3 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_SIM4 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running
+ SLEEP_CTL_NL1SM = 39, // 0x27
+ SLEEP_CTL_NL1SM_DEBUG = 40, // 0x28
+ SLEEP_CTL_MML1 = 41, // 0x29
+ SLEEP_CTL_USB_2 = 42, // 0x2A
+ SLEEP_CTL_CLDMA = 43, // 0x2B
+ SLEEP_CTL_LVTS_RESET = 44, // 0x2C
+ SLEEP_CTL_MCF = 45, // 0x2D
+ SLEEP_CTL_USBCORE = 46, // 0x2E
+ MAX_SLEEP_HANDLE = 47
+#else
+ #error "no chip match"
+#endif
+
+} SLEEP_CTL_USER;
+
+
+typedef enum
+{
+ MDLPM_VERSION = 0, //MDLPM_VERSION
+ MDLPM_REC_INDEX = 1, //MD RECORD INDEX
+ MDLPM_UTC_0 = 2, //UTC 0~31 bits
+ MDLPM_UTC_1 = 3, //UTC 32~63 bits
+ MDLPM_FRC = 4, //MD Free RUN Counter
+ MDLPM_TIMESTAMP = 5, //MD UTC Timestamp
+ MDLPM_WALL_CLK_0 = 6, //MD Wall Clock 0~31 bits
+ MDLPM_WALL_CLK_1 = 7, //MD Wall Clock 32~63 bits
+ MDLPM_MD_SLEEP_DUR = 8, //MD 26M Off tick
+ MDLPM_SOC_SLEEP_DUR = 9, //SOC 26M off tick
+ MDLPM_MD_TOPSM_PWR_RDY = 10, //MD_TOPSM PWR READY
+ MDLPM_MD_SW_LOCK_0 = 11, //SW Lock 0~31 bit
+ MDLPM_MD_SW_LOCK_1 = 12, //SW Lock 32~64 bit
+ MDLPM_MD_DATA13 = 13, //unused
+ MDLPM_MD_DATA14 = 14, //unused
+ MDLPM_MD_OST_F32_WAKEUP_0 = 15, //32k wakeup event 0~31 bit
+ MDLPM_MD_OST_F32_WAKEUP_1 = 16, //32k wakeup event 32~63 bit
+ MDLPM_MD_OST_26M_WAKEUP_0 = 17, //26m wakeup event 0~31 bit
+ MDLPM_MD_OST_26M_WAKEUP_1 = 18, //26m wakeup event 32~63 bit
+ MDLPM_MD_TOPSM_SLV_REQ_STA = 19, //MD_TOPSM SLV_REQ
+ MDLPM_MD_TOPSM_DBG_REQ_STA = 20, //MD_TOPSM DBG_REQ
+ MDLPM_MDMCU_IDLE_TIME = 21, //Reserve for MD_TOPSM extend
+ MDLPM_USIP_IDLE_TIME = 22, //Reserve for MD_TOPSM extend
+ MDLPM_DATA23 = 23, //Reserve for MD_TOPSM extend
+
+ // AMIF & MD DVFS
+ MDLPM_AMIF_GROUP_0 = 24, //unused
+ MDLPM_AMIF_GROUP_1 = 25, //unused
+ MDLPM_AMIF_GROUP_2 = 26, //unused
+ MDLPM_AMIF_GROUP_3 = 27, //unused
+ MDLPM_AMIF_GROUP_4 = 28, //unused
+ MDLPM_AMIF_GROUP_5 = 29, //unused
+ MDLPM_AMIF_GROUP_6 = 30, //unused
+ MDLPM_AMIF_GROUP_7 = 31, //unused
+ MDLPM_MD_DVFS_GEAR_0 = 32, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_1 = 33, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_2 = 34, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_3 = 35, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_4 = 36, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_5 = 37, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_6 = 38, //MD DVFS
+ MDLPM_MD_DVFS_GEAR_7 = 39, //MD DVFS
+
+ //Others
+ MDLPM_DATA40 = 40, //unused
+ MDLPM_DATA41 = 41, //unused
+ MDLPM_DATA42 = 42, //unused
+ MDLPM_DATA43 = 43, //unused
+ MDLPM_VOLTE_UL = 44, //VOLTE UL
+ MDLPM_VOLTE_DL = 45, //VOLTE DL
+ MDLPM_VOLTE_CODEC = 46, //VOLTE CODEC
+ MDLPM_DATA47 = 47, //unsued
+
+ /* debug info in 93 adding */
+ MDLPM_GL1_SLEEP_ACTIVE_DUR = 48, //2G acc sleep info.
+ MDLPM_GL1_SLEEP_STATUS = 49, //2G sleep status info.
+ MDLPM_UL1_SLEEP_ACTIVE_DUR = 50, //3G acc sleep info.
+ MDLPM_UL1_SLEEP_STATUS = 51, //2G sleep status info.
+ MDLPM_EL1_SLEEP_ACTIVE_DUR = 52, //3G acc sleep info.
+ MDLPM_EL1_SLEEP_STATUS = 53, //2G sleep status info.
+ MDLPM_MODEM_TOPSM_SM_TOPSM_APP_OUTCR_SET = 54,
+ MDLPM_MODEM_TOPSM_SM_DBG_REQ_STA = 55,
+ MDLPM_MODEM_TOPSM_DEBUG = 56,
+ /* debug info in 93 adding end */
+ /* 2G L1 behavior list */
+ MDLPM_GL1_BCCH = 57,
+ MDLPM_GL1_PAGING = 58,
+ MDLPM_GL1_CBCH = 59,
+ MDLPM_GL1_POWER_SCAN = 60,
+ MDLPM_GL1_BSIC_READ = 61, //FB/SB
+ MDLPM_GL1_STANDBY_GAP = 62,
+ MDLPM_GL1_ACCESS = 63, //Access mode is RACH in UL and listening AGCH/CCCH in DL
+ MDLPM_GL1_CS = 64, //dedicated mode circuit-switch
+ MDLPM_GL1_PS = 65, //dedicated mode packet-switch
+ /* 3G L1 behavior list */
+ MDLPM_UL1_BCH = 66, //BCH channel such as SIB/SFN
+ MDLPM_UL1_PCH = 67, //PCH channel
+ MDLPM_UL1_CTCH = 68, //CTCH channel
+ MDLPM_UL1_FS = 69, //frequency scan or power scan
+ MDLPM_UL1_CS = 70, //cell search
+ MDLPM_UL1_CM = 71, //cell measurement
+ MDLPM_UL1_TAS = 72, //TAS/RAS feature
+ MDLPM_UL1_ACTIVE_GAP = 73, //active gap assignment
+ MDLPM_UL1_STANDBY_GAP = 74, //receive standby gap
+ MDLPM_UL1_FACH = 75, //FACH/RACH channel
+ MDLPM_UL1_DCH = 76, //DCH channel
+ MDLPM_UL1_R5R6 = 77, //R5/R6 channel
+ MDLPM_UL1_R7R8 = 78, //R7/R8 channel
+ MDLPM_UL1_OTHERS = 79,
+ MDLPM_UL1_RESOURCE = 80, //RTB or Inter-SIM resource
+ MDLPM_UL1_CC = 81, //channel/mode change
+ MDLPM_UL1_DDL = 82, //DDL
+ MDLPM_UL1_EM = 83, //EM
+ /* 4G L1 behavior list */
+ MDLPM_EL1_MIB_SIB = 84,
+ MDLPM_EL1_PAGE = 85,
+ MDLPM_EL1_CSR = 86,
+ MDLPM_EL1_INTRA_CS = 87,
+ MDLPM_EL1_INTER_CS = 88,
+ MDLPM_EL1_INTRA_CM = 89,
+ MDLPM_EL1_INTER_CM = 90,
+ MDLPM_EL1_INTRA_POS = 91,
+ MDLPM_EL1_INTER_POS = 92,
+ MDLPM_EL1_MBMS = 93,
+ MDLPM_EL1_ACTIVE_GAP = 94, //active gap assignment
+ MDLPM_EL1_STANDBY_GAP = 95, //receive standby gap
+ MDLPM_EL1_CONNECT_START = 96,
+ MDLPM_EL1_CONNECT_END = 97,
+ MDLPM_EL1_CONNECT_DUR = 98, //accumulated connection duration
+ /* RAT L1 behavior list end */
+ /* MLL1 activate RAT monitor data start*/
+ MDLPM_SIM1_ACTIVATE_RAT = 99, //SIM1 activate RAT
+ MDLPM_SIM1_RAT_DRX = 100, //SIM1 activate RAT drx
+ MDLPM_SIM1_UPDATE_FRC = 101, //SIM1 info. update FRC
+ MDLPM_SIM2_ACTIVATE_RAT = 102, //SIM2 activate RAT
+ MDLPM_SIM2_RAT_DRX = 103, //SIM2 activate RAT drx
+ MDLPM_SIM2_UPDATE_FRC = 104, //SIM2 info. update FRC
+ MDLPM_SIM3_ACTIVATE_RAT = 105, //SIM3 activate RAT
+ MDLPM_SIM3_RAT_DRX = 106, //SIM3 activate RAT drx
+ MDLPM_SIM3_UPDATE_FRC = 107, //SIM3 info. update FRC
+ /* 2G monitor data start*/
+ MDLPM_GL1_RX_WINDOW_DUR = 108, //2G RX window open duration
+ MDLPM_GL1_TX_WINDOW_DUR = 109, //2G TX window open duration
+ MDLPM_GL1_TX_POWER_REG1 = 110, //2G TX power region 1: 0 ~ 5dBm; [0, 5]
+ MDLPM_GL1_TX_POWER_REG2 = 111, //2G TX power region 2: 5 ~ 10dBm; (5, 10]
+ MDLPM_GL1_TX_POWER_REG3 = 112, //2G TX power region 3: 10 ~ 15dBm; (10, 15]
+ MDLPM_GL1_TX_POWER_REG4 = 113, //2G TX power region 4: 15 ~ 20dBm; (15, 20]
+ MDLPM_GL1_TX_POWER_REG5 = 114, //2G TX power region 5: 20 ~ 25dBm; (20, 25]
+ MDLPM_GL1_TX_POWER_REG6 = 115, //2G TX power region 6: 25 ~ 30dBm; (25, 30]
+ MDLPM_GL1_TX_POWER_REG7 = 116, //2G TX power region 7: 30 ~ 33dBm; (30, 33]
+ /* 2G monitor data end */
+ /* 3G monitor data start */
+ MDLPM_UL1_RX_WINDOW_START = 117, //3G RX window open start frc
+ MDLPM_UL1_TX_WINDOW_START = 118, //3G TX window open start frc
+ MDLPM_UL1_RX_PATH_USED = 119, //3G RX path used flag
+ MDLPM_UL1_TX_PATH_USED = 120, //3G TX path used flag
+ MDLPM_UL1_RX_PATH1_CNT = 121, //3G use RX path 1 used cnt
+ MDLPM_UL1_RX_PATH2_CNT = 122, //3G use RX path 2 used cnt
+ MDLPM_UL1_RX_PATH3_CNT = 123, //3G use RX path 3 used cnt
+ MDLPM_UL1_RX_PATH4_CNT = 124, //3G use RX path 4 used cnt
+ MDLPM_UL1_RX_PATH5_CNT = 125, //3G use RX path 5 used cnt
+ MDLPM_UL1_RX_PATH6_CNT = 126, //3G use RX path 6 used cnt
+ MDLPM_UL1_TX_PATH1_CNT = 127, //3G use TX path 1 used cnt
+ MDLPM_UL1_TX_PATH2_CNT = 128, //3G use TX path 2 used cnt
+ MDLPM_UL1_RX_WINDOW_DUR = 129, //3G RX window open duration
+ MDLPM_UL1_TX_WINDOW_DUR = 130, //3G TX window open duration
+ MDLPM_UL1_TX_POWER_REG1 = 131, //3G TX power region 1: <= -5dBm
+ MDLPM_UL1_TX_POWER_REG2 = 132, //3G TX power region 2: -5 ~ 1dBm; (-5, 1]
+ MDLPM_UL1_TX_POWER_REG3 = 133, //3G TX power region 3: 1 ~ 5dBm; (1,5]
+ MDLPM_UL1_TX_POWER_REG4 = 134, //3G TX power region 4: 5 ~ 10dBm; (5,10]
+ MDLPM_UL1_TX_POWER_REG5 = 135, //3G TX power region 5: 10 ~ 15dBm; (10,15]
+ MDLPM_UL1_TX_POWER_REG6 = 136, //3G TX power region 6: 15 ~ 20dBm; (15,20]
+ MDLPM_UL1_TX_POWER_REG7 = 137, //3G TX power region 7: 20 ~ 24dBm; (20,24]
+ MDLPM_UL1_LORX_MODE0 = 138, //3G LoRX mode 0 (LORX_OFF) cnt
+ MDLPM_UL1_LORX_MODE1 = 139, //3G LoRX mode 1 (LORX_ON) cnt
+ MDLPM_UL1_LORX_TRIG_FALSE = 140, //3G LoRX triger is false
+ MDLPM_UL1_LORX_TRIG_TRUE = 141, //3G LoRX triger is true
+ MDLPM_UL1_ARX_HPM = 142, //3G ARX mode 0 (HPM) cnt
+ MDLPM_UL1_ARX_LPM_VOICE = 143, //3G ARX mode 1 (LPM_VOICE) cnt
+ MDLPM_UL1_ARX_LPM_DATA = 144, //3G ARX mode 2 (LPM_DATA) cnt
+ MDLPM_UL1_RAS_1RX_INVALID = 145, //3G RAS mode 0 (1RX_INVALID) cnt
+ MDLPM_UL1_RAS_1RX_PATH_MAIN = 146, //3G RAS mode 1 (1RX_PATH_MAIN) cnt
+ MDLPM_UL1_RAS_2RX_PATH_BOTH = 147, //3G RAS mode 2 (2RX_PATH_BOTH) cnt
+ /* 3G monitor data end */
+ /* 4G monitor data start */
+ MDLPM_EL1_ACTIVE_1CC = 148, //active 1CC (Pcell only) cnt
+ MDLPM_EL1_ACTIVE_2CC = 149, //active 2CC cnt
+ MDLPM_EL1_ACTIVE_3CC = 150, //active 3CC cnt
+ MDLPM_EL1_ACTIVE_4CC = 151, //active 4CC cnt
+ MDLPM_EL1_ACTIVE_5CC = 152, //active 5CC cnt
+ MDLPM_EL1_CC_LAST = 153, //last active CC number
+ MDLPM_EL1_CC_LAST_FRC = 154, //last active CC number
+ MDLPM_EL1_RX_WINDOW_START = 155, //4G RX window open start frc
+ MDLPM_EL1_TX_WINDOW_START = 156, //4G TX window open start frc
+ MDLPM_EL1_RX_PATH_USED = 157, //4G RX path used flag
+ MDLPM_EL1_TX_PATH_USED = 158, //4G TX path used flag
+ MDLPM_EL1_RX_PATH1_CNT = 159, //4G use RX path 1 used cnt
+ MDLPM_EL1_RX_PATH2_CNT = 160, //4G use RX path 2 used cnt
+ MDLPM_EL1_RX_PATH3_CNT = 161, //4G use RX path 3 used cnt
+ MDLPM_EL1_RX_PATH4_CNT = 162, //4G use RX path 4 used cnt
+ MDLPM_EL1_RX_PATH5_CNT = 163, //4G use RX path 5 used cnt
+ MDLPM_EL1_TX_PATH1_CNT = 164, //4G use TX path 1 used cnt
+ MDLPM_EL1_TX_PATH2_CNT = 165, //4G use TX path 2 used cnt
+ MDLPM_EL1_RX_WINDOW_DUR = 166, //4G RX window open duration
+ MDLPM_EL1_TX_WINDOW_DUR = 167, //4G TX window open duration
+ MDLPM_EL1_TX_POWER_CC0_REG1 = 168, //4G CC0 TX power region 1: <= -5dBm
+ MDLPM_EL1_TX_POWER_CC0_REG2 = 169, //4G CC0 TX power region 2: -5 ~ 1dBm; (-5, 1]
+ MDLPM_EL1_TX_POWER_CC0_REG3 = 170, //4G CC0 TX power region 3: 1 ~ 5dBm; (1,5]
+ MDLPM_EL1_TX_POWER_CC0_REG4 = 171, //4G CC0 TX power region 4: 5 ~ 10dBm; (5,10]
+ MDLPM_EL1_TX_POWER_CC0_REG5 = 172, //4G CC0 TX power region 5: 10 ~ 15dBm; (10,15]
+ MDLPM_EL1_TX_POWER_CC0_REG6 = 173, //4G CC0 TX power region 6: 15 ~ 20dBm; (15,20]
+ MDLPM_EL1_TX_POWER_CC0_REG7 = 174, //4G CC0 TX power region 7: 20 ~ 23dBm; (20,23]
+ MDLPM_EL1_TX_POWER_CC0_REG8 = 175, //4G CC0 TX power region 8: 23 ~ 26dBm; (23,26]
+ MDLPM_EL1_TX_POWER_CC1_REG1 = 176, //4G CC1 TX power region 1: <= -5dBm
+ MDLPM_EL1_TX_POWER_CC1_REG2 = 177, //4G CC1 TX power region 2: -5 ~ 1dBm; (-5, 1]
+ MDLPM_EL1_TX_POWER_CC1_REG3 = 178, //4G CC1 TX power region 3: 1 ~ 5dBm; (1,5]
+ MDLPM_EL1_TX_POWER_CC1_REG4 = 179, //4G CC1 TX power region 4: 5 ~ 10dBm; (5,10]
+ MDLPM_EL1_TX_POWER_CC1_REG5 = 180, //4G CC1 TX power region 5: 10 ~ 15dBm; (10,15]
+ MDLPM_EL1_TX_POWER_CC1_REG6 = 181, //4G CC1 TX power region 6: 15 ~ 20dBm; (15,20]
+ MDLPM_EL1_TX_POWER_CC1_REG7 = 182, //4G CC1 TX power region 7: 20 ~ 23dBm; (20,23]
+ MDLPM_EL1_TX_POWER_CC1_REG8 = 183, //4G CC1 TX power region 8: 23 ~ 26dBm; (23,26]
+ MDLPM_EL1_TX_POWER_CC2_REG1 = 184, //4G CC2 TX power region 1: <= -5dBm
+ MDLPM_EL1_TX_POWER_CC2_REG2 = 185, //4G CC2 TX power region 2: -5 ~ 1dBm; (-5, 1]
+ MDLPM_EL1_TX_POWER_CC2_REG3 = 186, //4G CC2 TX power region 3: 1 ~ 5dBm; (1,5]
+ MDLPM_EL1_TX_POWER_CC2_REG4 = 187, //4G CC2 TX power region 4: 5 ~ 10dBm; (5,10]
+ MDLPM_EL1_TX_POWER_CC2_REG5 = 188, //4G CC2 TX power region 5: 10 ~ 15dBm; (10,15]
+ MDLPM_EL1_TX_POWER_CC2_REG6 = 189, //4G CC2 TX power region 6: 15 ~ 20dBm; (15,20]
+ MDLPM_EL1_TX_POWER_CC2_REG7 = 190, //4G CC2 TX power region 7: 20 ~ 23dBm; (20,23]
+ MDLPM_EL1_TX_POWER_CC2_REG8 = 191, //4G CC2 TX power region 8: 23 ~ 26dBm; (23,26]
+ MDLPM_EL1_TX_POWER_ALL_REG1 = 192, //4G total TX power region 1: <= -5dBm
+ MDLPM_EL1_TX_POWER_ALL_REG2 = 193, //4G total TX power region 2: -5 ~ 1dBm; (-5, 1]
+ MDLPM_EL1_TX_POWER_ALL_REG3 = 194, //4G total TX power region 3: 1 ~ 5dBm; (1,5]
+ MDLPM_EL1_TX_POWER_ALL_REG4 = 195, //4G total TX power region 4: 5 ~ 10dBm; (5,10]
+ MDLPM_EL1_TX_POWER_ALL_REG5 = 196, //4G total TX power region 5: 10 ~ 15dBm; (10,15]
+ MDLPM_EL1_TX_POWER_ALL_REG6 = 197, //4G total TX power region 6: 15 ~ 20dBm; (15,20]
+ MDLPM_EL1_TX_POWER_ALL_REG7 = 198, //4G total TX power region 7: 20 ~ 23dBm; (20,23]
+ MDLPM_EL1_TX_POWER_ALL_REG8 = 199, //4G total TX power region 8: 23 ~ 26dBm; (23,26]
+ MDLPM_EL1_LORX_MODE0 = 200, //4G LoRX mode 0 (LORX_OFF) cnt
+ MDLPM_EL1_LORX_MODE1 = 201, //4G LoRX mode 1 (LORX_TYPE1, symobol mode) cnt
+ MDLPM_EL1_LORX_MODE2 = 202, //4G LoRX mode 2 (LORX_TYPE2, PDCCH early stop) cnt
+ MDLPM_EL1_LORX_MODE3 = 203, //4G LoRX mode 3 (LORX_TYPE3, PDCCH early stop with sync) cnt
+ MDLPM_EL1_LOSX_CC0_ENABLE = 204, //4G LoSX CC0 enable cnt
+ MDLPM_EL1_LOSX_CC1_ENABLE = 205, //4G LoSX CC1 enable cnt
+ MDLPM_EL1_LOSX_CC2_ENABLE = 206, //4G LoSX CC2 enable cnt
+ MDLPM_EL1_LOSX_CC3_ENABLE = 207, //4G LoSX CC3 enable cnt
+ MDLPM_EL1_LOSX_CC4_ENABLE = 208, //4G LoSX CC4 enable cnt
+ MDLPM_EL1_LORX_TRIG_FALSE = 209, //4G LoRX triger is false
+ MDLPM_EL1_LORX_TRIG_TRUE = 210, //4G LoRX triger is true
+ MDLPM_EL1_LOSX_CC0_TRIG = 211, //4G LoSX CC0 triger cnt
+ MDLPM_EL1_LOSX_CC1_TRIG = 212, //4G LoSX CC1 triger cnt
+ MDLPM_EL1_LOSX_CC2_TRIG = 213, //4G LoSX CC2 triger cnt
+ MDLPM_EL1_LOSX_CC3_TRIG = 214, //4G LoSX CC3 triger cnt
+ MDLPM_EL1_LOSX_CC4_TRIG = 215, //4G LoSX CC4 triger cnt
+ MDLPM_EL1_CC0_ARX_HPM = 216, //4G ARX CC0 mode 0 (HPM) cnt
+ MDLPM_EL1_CC0_ARX_LPM_DATA = 217, //4G ARX CC0 mode 1 (LPM_DATA) cnt
+ MDLPM_EL1_CC0_ARX_LPM_LMCS = 218, //4G ARX CC0 mode 2 (LPM_LMCS) cnt
+ MDLPM_EL1_CC0_ARX_LPM_VOICE = 219, //4G ARX CC0 mode 3 (LPM_VOICE) cnt
+ MDLPM_EL1_CC0_ARX_LPM_HMCS = 220, //4G ARX CC0 mode 4 (LPM_HMCS) cnt
+ MDLPM_EL1_CC1_ARX_HPM = 221, //4G ARX CC1 mode 0 (HPM) cnt
+ MDLPM_EL1_CC1_ARX_LPM_DATA = 222, //4G ARX CC1 mode 1 (LPM_DATA) cnt
+ MDLPM_EL1_CC1_ARX_LPM_LMCS = 223, //4G ARX CC1 mode 2 (LPM_LMCS) cnt
+ MDLPM_EL1_CC1_ARX_LPM_VOICE = 224, //4G ARX CC1 mode 3 (LPM_VOICE) cnt
+ MDLPM_EL1_CC1_ARX_LPM_HMCS = 225, //4G ARX CC1 mode 4 (LPM_HMCS) cnt
+ MDLPM_EL1_CC2_ARX_HPM = 226, //4G ARX CC2 mode 0 (HPM) cnt
+ MDLPM_EL1_CC2_ARX_LPM_DATA = 227, //4G ARX CC2 mode 1 (LPM_DATA) cnt
+ MDLPM_EL1_CC2_ARX_LPM_LMCS = 228, //4G ARX CC2 mode 2 (LPM_LMCS) cnt
+ MDLPM_EL1_CC2_ARX_LPM_VOICE = 229, //4G ARX CC2 mode 3 (LPM_VOICE) cnt
+ MDLPM_EL1_CC2_ARX_LPM_HMCS = 230, //4G ARX CC2 mode 4 (LPM_HMCS) cnt
+ MDLPM_EL1_CC3_ARX_HPM = 231, //4G ARX CC3 mode 0 (HPM) cnt
+ MDLPM_EL1_CC3_ARX_LPM_DATA = 232, //4G ARX CC3 mode 1 (LPM_DATA) cnt
+ MDLPM_EL1_CC3_ARX_LPM_LMCS = 233, //4G ARX CC3 mode 2 (LPM_LMCS) cnt
+ MDLPM_EL1_CC3_ARX_LPM_VOICE = 234, //4G ARX CC3 mode 3 (LPM_VOICE) cnt
+ MDLPM_EL1_CC3_ARX_LPM_HMCS = 235, //4G ARX CC3 mode 4 (LPM_HMCS) cnt
+ MDLPM_EL1_CC4_ARX_HPM = 236, //4G ARX CC4 mode 0 (HPM) cnt
+ MDLPM_EL1_CC4_ARX_LPM_DATA = 237, //4G ARX CC4 mode 1 (LPM_DATA) cnt
+ MDLPM_EL1_CC4_ARX_LPM_LMCS = 238, //4G ARX CC4 mode 2 (LPM_LMCS) cnt
+ MDLPM_EL1_CC4_ARX_LPM_VOICE = 239, //4G ARX CC4 mode 3 (LPM_VOICE) cnt
+ MDLPM_EL1_CC4_ARX_LPM_HMCS = 240, //4G ARX CC4 mode 4 (LPM_HMCS) cnt
+ MDLPM_EL1_CC0_RAS_1RX = 241, //4G RAS CC0 mode 0 (1RX) cnt
+ MDLPM_EL1_CC0_RAS_2RX = 242, //4G RAS CC0 mode 1 (2RX) cnt
+ MDLPM_EL1_CC0_RAS_4RX = 243, //4G RAS CC0 mode 2 (4RX) cnt
+ MDLPM_EL1_CC1_RAS_1RX = 244, //4G RAS CC1 mode 0 (1RX) cnt
+ MDLPM_EL1_CC1_RAS_2RX = 245, //4G RAS CC1 mode 1 (2RX) cnt
+ MDLPM_EL1_CC1_RAS_4RX = 246, //4G RAS CC1 mode 2 (4RX) cnt
+ MDLPM_EL1_CC2_RAS_1RX = 247, //4G RAS CC2 mode 0 (1RX) cnt
+ MDLPM_EL1_CC2_RAS_2RX = 248, //4G RAS CC2 mode 1 (2RX) cnt
+ MDLPM_EL1_CC2_RAS_4RX = 249, //4G RAS CC2 mode 2 (4RX) cnt
+ MDLPM_EL1_CC3_RAS_1RX = 250, //4G RAS CC3 mode 0 (1RX) cnt
+ MDLPM_EL1_CC3_RAS_2RX = 251, //4G RAS CC3 mode 1 (2RX) cnt
+ MDLPM_EL1_CC3_RAS_4RX = 252, //4G RAS CC3 mode 2 (4RX) cnt
+ MDLPM_EL1_CC4_RAS_1RX = 253, //4G RAS CC4 mode 0 (1RX) cnt
+ MDLPM_EL1_CC4_RAS_2RX = 254, //4G RAS CC4 mode 1 (2RX) cnt
+ MDLPM_EL1_CC4_RAS_4RX = 255, //4G RAS CC4 mode 2 (4RX) cnt
+ /* 4G monitor data end */
+
+ /* 5G monitor data start */
+ MDLPM_NL1_SLEEP_ACTIVE_DUR = 256, //5G acc sleep info.
+ MDLPM_NL1_SLEEP_STATUS = 257, //5G sleep status info.
+ MDLPM_NL1_MMW_SLEEP_ACTIVE_DUR = 258, //5G mmW acc sleep info.
+ MDLPM_NL1_MMW_SLEEP_STATUS = 259, //5G mmW sleep status info.
+ // RX/TX window related
+ MDLPM_NL1_RX_WINDOW_DUR = 260, //5G RX window acc. open duration
+ MDLPM_NL1_TX_WINDOW_DUR = 261, //5G TX window acc. open duration
+ MDLPM_NL1_CONNECT_DUR = 262, //5G connection duration
+ MDLPM_NL1_TX_POWER_TG0_CC0 = 263, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26
+ MDLPM_NL1_TX_POWER_TG1_CC0 = 264, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26
+ MDLPM_NL1_TX_POWER_TG2_CC0 = 265, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26
+ MDLPM_NL1_ARX_TG0_CC0 = 266, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
+ MDLPM_NL1_ARX_TG1_CC0 = 267, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
+ MDLPM_NL1_ARX_TG2_CC0 = 268, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
+ MDLPM_NL1_ARX_TG0_CC1 = 269, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
+ MDLPM_NL1_ARX_TG1_CC1 = 270, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
+ MDLPM_NL1_ARX_TG2_CC1 = 271, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS
+ MDLPM_NL1_ARX_TG0_CC0_CNT = 272, //5G ARX change counter info
+ MDLPM_NL1_ARX_TG1_CC0_CNT = 273, //5G ARX change counter info
+ MDLPM_NL1_ARX_TG2_CC0_CNT = 274, //5G ARX change counter info
+ MDLPM_NL1_ARX_TG0_CC1_CNT = 275, //5G ARX change counter info
+ MDLPM_NL1_ARX_TG1_CC1_CNT = 276, //5G ARX change counter info
+ MDLPM_NL1_ARX_TG2_CC1_CNT = 277, //5G ARX change counter info
+ MDLPM_NL1_RAS_TG0_CC0 = 278, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
+ MDLPM_NL1_RAS_TG1_CC0 = 279, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
+ MDLPM_NL1_RAS_TG2_CC0 = 280, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
+ MDLPM_NL1_RAS_TG0_CC1 = 281, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
+ MDLPM_NL1_RAS_TG1_CC1 = 282, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
+ MDLPM_NL1_RAS_TG2_CC1 = 283, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX
+ MDLPM_NL1_RAS_TG0_CC0_CNT = 284, //5G RAS change counter info
+ MDLPM_NL1_RAS_TG1_CC0_CNT = 285, //5G RAS change counter info
+ MDLPM_NL1_RAS_TG2_CC0_CNT = 286, //5G RAS change counter info
+ MDLPM_NL1_RAS_TG0_CC1_CNT = 287, //5G RAS change counter info
+ MDLPM_NL1_RAS_TG1_CC1_CNT = 288, //5G RAS change counter info
+ MDLPM_NL1_RAS_TG2_CC1_CNT = 289, //5G RAS change counter info
+ MDLPM_NL1_SLEEP_ACTIVE_DUR_TG0 = 290, //5G acc sleep info.
+ MDLPM_NL1_SLEEP_STATUS_TG0 = 291, //5G sleep status info.
+ MDLPM_NL1_SLEEP_ACTIVE_DUR_TG1 = 292, //5G acc sleep info.
+ MDLPM_NL1_SLEEP_STATUS_TG1 = 293, //5G sleep status info.
+ /* 5G monitor data end */
+ MDLPM_MAX_ITEMS = 512
+} MDLPM_INDEX;
+
+#ifdef SMP
+#undef SMP
+#endif
+
+typedef enum
+{
+ SMP = 0,
+ CORE0 = 0,
+ CORE1,
+ CORE2,
+ CORE3
+} SLPDRV_CORE_e;
+
+//#ifdef BIG_DAC_CHANGE_RECALIBRATION
+
+typedef enum
+{
+ MODEM_TOPSM_INPUT_2G = 0, /* Input module is 2G */
+ MODEM_TOPSM_INPUT_3G /* Input module is 3G */
+} MODEM_TOPSM_INPUT_MODULE;
+
+typedef enum
+{
+ MODEM_TOPSM_RF1 = 0,
+ MODEM_TOPSM_RF2,
+ NUM_OF_CLOCK_SOURCE
+} CLOCK_INPUT_SOURCE;
+
+//#endif
+typedef enum{
+#if defined(__MD93__)
+ SLP_EMM_CORE0_SLP_SW_LOCK = 0,
+ SLP_EMM_CORE0_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE1_SLP_SW_LOCK,
+ SLP_EMM_CORE1_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE0_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE1_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_SLP_INIFINITE_ENTER,
+#elif defined(__MD95__)
+ SLP_EMM_CORE0_SLP_SW_LOCK = 0,
+ SLP_EMM_CORE0_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE1_SLP_SW_LOCK,
+ SLP_EMM_CORE1_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE2_SLP_SW_LOCK,
+ SLP_EMM_CORE2_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE0_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE1_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE2_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_CORE2_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_SLP_INIFINITE_ENTER,
+#elif defined(__MD97__) || defined(__MD97P__)
+ SLP_EMM_CORE0_SLP_SW_LOCK = 0,
+ SLP_EMM_CORE0_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE1_SLP_SW_LOCK,
+ SLP_EMM_CORE1_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE2_SLP_SW_LOCK,
+ SLP_EMM_CORE2_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE3_SLP_SW_LOCK,
+ SLP_EMM_CORE3_SLP_SW_EXT_LOCK,
+ SLP_EMM_CORE0_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE1_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE2_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE3_SLP_SW_LOCK_TIME,
+ SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_CORE2_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_CORE3_SLP_SW_UNLOCK_TIME,
+ SLP_EMM_SLP_INIFINITE_ENTER,
+#else
+ #error "no chip match"
+#endif
+}SLP_EMM_LOG_INDEX;
+
+void SleepDrv_LockSleep( SLEEP_CTL_USER user, kal_uint8 target_core);
+void SleepDrv_UnlockSleep( SLEEP_CTL_USER user, kal_uint8 target_core);
+
+void Sleep_DrvLowPowerMonitorInit(void);
+
+void SleepDrv_LowPowerMonitorFlushCheck( void );
+void SleepDrv_LowPowerMonitorDelete(void);
+void SleepDrv_LowPowerMonitorCreate(void);
+void SleepDrv_LowPowerMonitorStart(void);
+void SleepDrv_LowPowerMonitorStop(void);
+kal_bool SleepDrv_LowPowerMonitorSetParameter(kal_uint32 data_len, kal_uint8 *data_str);
+
+void SleepDrv_UpdatePSSlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
+void SleepDrv_UpdateL1SlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value);
+void SleepDrv_SlpDbgShmRingBufAdd(SLP_DBG_SHM_RING_BUFFER_INDEX index, kal_uint32 status, kal_uint32 dbg_info);
+
+extern kal_bool MD_TOPSM_StartLPM(kal_uint8 data_str0, kal_uint8 data_str1, kal_uint8 data_str2);
+extern kal_bool MD_TOPSM_DumpLPM(void);
+
+
+/* MDTOPSM Public API */
+extern kal_uint32 SleepDrv_GetWallClk(void);
+extern kal_uint32 SleepDrv_GetWallClk_H(void);
+extern void MD_TOPSM_EnableFRC(void); /* Enable FRC API for exception handling */
+extern kal_uint8 MD_TOPSM_SRCLK_SW_Control_GetHandle( kal_char* module_name ); /* Register the module as a SRCLK force on user */
+extern void MD_TOPSM_SRCLK_SW_Control( SRCLK_FORCEON_USER user, kal_bool fOn ); /* SW lock or unlock 26M */
+extern void MD_TOPSM_PLL_SW_Control(PS_PLL_FORCEON_USER USER,PS_TOPSM_PLL PLL, kal_bool fOn);
+extern void MD_TOPSM_USIP_SW_Control(PS_USIP_FORCEON_USER USER, kal_bool fOn);
+
+#include "reg_base.h"
+
+
+#define GET_TOPSM_FRC_VAL_R() (*(volatile kal_uint32 *)(BASE_ADDR_MDTOPSM+0x830))
+#define GET_TOPSM_FRC_SYNC_VAL_2G_US()
+#define GET_TOPSM_FRC_SYNC_VAL_2G_26M()
+#define GET_TOPSM_FRC_SYNC_VAL_3G_US()
+#define GET_TOPSM_FRC_SYNC_VAL_3G_26M()
+#define GET_TOPSM_FRC_SYNC_VAL_TDD_US()
+#define GET_TOPSM_FRC_SYNC_VAL_TDD_26M()
+#define SET_GPS_SYNC_TIME(_val)
+
+
+
+#ifdef BIG_DAC_CHANGE_RECALIBRATION
+extern void MODEM_TOPSM_SetCurrentFreqOffset( kal_int32 freq_offset, MODEM_TOPSM_INPUT_MODULE module, CLOCK_INPUT_SOURCE clockSource );
+extern void MODEM_TOPSM_SetFreqOffsetBase( kal_int32 freq_offset, MODEM_TOPSM_INPUT_MODULE module, CLOCK_INPUT_SOURCE clockSource );
+#endif
+
+extern kal_uint32 MODEM_TOPSM_GetSSTA0(void);
+extern kal_uint32 MODEM_TOPSM_GetSSTA1(void);
+
+extern kal_bool OSTD_Is3gEnabled (void);
+
+
+#endif